soc/intel/common/uart: Refactor uart_common_init

1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.

2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.

BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.

Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Kconfig

@@ -351,4 +351,14 @@ config APL_SKIP_SET_POWER_LIMITS
 	  Limits (RAPL) algorithm for a constant power management.
 	  Set this config option to skip the RAPL configuration.
 
+# M and N divisor values for clock frequency configuration.
+# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+	hex
+	default 0x25a
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+	hex
+	default 0x7fff
+
 endif

src/soc/intel/apollolake/include/soc/uart.h

@@ -18,13 +18,6 @@
 #ifndef _SOC_APOLLOLAKE_UART_H_
 #define _SOC_APOLLOLAKE_UART_H_
 
-/*
-* M and N divisor values for clock frequency configuration.
-* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-*/
-#define CLK_M_VAL	0x025a
-#define CLK_N_VAL	0x7fff
-
 /* Initialize the console UART including the pads for the configured UART. */
 void pch_uart_init(void);
 

src/soc/intel/apollolake/uart_early.c

@@ -69,6 +69,6 @@ void pch_uart_init(void)
 	gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
 
 	/* Program UART2 BAR0, command, reset and clock register */
-	uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+	uart_common_init(uart, base);
 
 }