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soc/intel/common: Add whiskeylake celeron v-0 support

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New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
2019-02-15 05:36:50 -08:00
committed by Duncan Laurie
parent 04aae87da7
commit 34745f613f
5 changed files with 5 additions and 0 deletions
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1
src/include/device/pci_ids.h
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@@ -2969,6 +2969,7 @@
#define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85
#define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184
#define PCI_DEVICE_ID_INTEL_GLK_IGD_EU12 0x3185
#define PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1 0x3EA1
#define PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1 0x3EA0
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1 0x5A51
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2 0x5A59