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sb/intel/i82801jx: Add correct PCI ids and change names

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Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
2017-04-09 20:48:37 +02:00
committed by Martin Roth
parent 7b9c139ac2
commit 349e08535a
29 changed files with 165 additions and 122 deletions
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58
src/southbridge/intel/i82801jx/lpc.c
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@@ -30,7 +30,7 @@
#include <arch/acpigen.h>
#include <cbmem.h>
#include <string.h>
#include "i82801ix.h"
#include "i82801jx.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
#include <drivers/intel/gma/i915.h>
@@ -40,9 +40,9 @@
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_i82801ix_config config_t;
typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801ix_enable_apic(struct device *dev)
static void i82801jx_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
@@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev)
setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
}
static void i82801ix_enable_serial_irqs(struct device *dev)
static void i82801jx_enable_serial_irqs(struct device *dev)
{
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, D31F0_SERIRQ_CNTL,
@@ -90,7 +90,7 @@ static void i82801ix_enable_serial_irqs(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
static void i82801ix_pirq_init(device_t dev)
static void i82801jx_pirq_init(device_t dev)
{
device_t irq_dev;
/* Get the chip configuration */
@@ -132,7 +132,7 @@ static void i82801ix_pirq_init(device_t dev)
}
}
static void i82801ix_gpi_routing(device_t dev)
static void i82801jx_gpi_routing(device_t dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -161,7 +161,7 @@ static void i82801ix_gpi_routing(device_t dev)
pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
}
static void i82801ix_power_options(device_t dev)
static void i82801jx_power_options(device_t dev)
{
u8 reg8;
u16 reg16, pmbase;
@@ -245,7 +245,7 @@ static void i82801ix_power_options(device_t dev)
// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using
/* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using
* periodic SMIs.
*/
reg16 |= (3 << 0); // Periodic SMI every 8s
@@ -268,7 +268,7 @@ static void i82801ix_power_options(device_t dev)
}
// Set the board's GPI routing.
i82801ix_gpi_routing(dev);
i82801jx_gpi_routing(dev);
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
@@ -293,7 +293,7 @@ static void i82801ix_power_options(device_t dev)
outl(reg32, pmbase + 0x10);
}
static void i82801ix_configure_cstates(device_t dev)
static void i82801jx_configure_cstates(device_t dev)
{
u8 reg8;
@@ -311,7 +311,7 @@ static void i82801ix_configure_cstates(device_t dev)
/* We could enable slow-C4 exit here, if someone needs it? */
}
static void i82801ix_rtc_init(struct device *dev)
static void i82801jx_rtc_init(struct device *dev)
{
u8 reg8;
int rtc_failed;
@@ -370,7 +370,7 @@ static void enable_clock_gating(void)
}
#if CONFIG_HAVE_SMI_HANDLER
static void i82801ix_lock_smm(struct device *dev)
static void i82801jx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
@@ -426,28 +426,28 @@ static void i82801ix_lock_smm(struct device *dev)
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801ix: lpc_init\n");
printk(BIOS_DEBUG, "i82801jx: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
i82801ix_enable_apic(dev);
i82801jx_enable_apic(dev);
i82801ix_enable_serial_irqs(dev);
i82801jx_enable_serial_irqs(dev);
/* Setup the PIRQ. */
i82801ix_pirq_init(dev);
i82801jx_pirq_init(dev);
/* Setup power options. */
i82801ix_power_options(dev);
i82801jx_power_options(dev);
/* Configure Cx state registers */
if (LPC_IS_MOBILE(dev))
i82801ix_configure_cstates(dev);
i82801jx_configure_cstates(dev);
/* Initialize the real time clock. */
i82801ix_rtc_init(dev);
i82801jx_rtc_init(dev);
/* Initialize ISA DMA. */
isa_dma_init();
@@ -465,11 +465,11 @@ static void lpc_init(struct device *dev)
i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
i82801ix_lock_smm(dev);
i82801jx_lock_smm(dev);
#endif
}
static void i82801ix_lpc_read_resources(device_t dev)
static void i82801jx_lpc_read_resources(device_t dev)
{
/*
* I/O Resources
@@ -571,7 +571,7 @@ static struct pci_operations pci_ops = {
};
static struct device_operations device_ops = {
.read_resources = i82801ix_lpc_read_resources,
.read_resources = i82801jx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
@@ -583,16 +583,16 @@ static struct device_operations device_ops = {
};
static const unsigned short pci_device_ids[] = {
0x2912, /* ICH9DH */
0x2914, /* ICH9DO */
0x2916, /* ICH9R */
0x2918, /* ICH9 */
0x2917, /* ICH9M-E */
0x2919, /* ICH9M */
0x3a10, /* ICH10R Eng. Sample */
0x3a14, /* ICH10DO */
0x3a16, /* ICH10R */
0x3a18, /* ICH10 */
0x3a1a, /* ICH10D */
0x3a1e, /* ICH10 Eng. Sample */
0
};
static const struct pci_driver ich9_lpc __pci_driver = {
static const struct pci_driver ich10_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,