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drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs

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This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Subrata Banik
2022-02-10 12:38:02 +05:30
committed by Felix Held
parent 03c0853f4d
commit 34f26b2989
16 changed files with 131 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/jasperlake/Kconfig
View File

@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select COS_MAPPED_TO_MSB
select DISPLAY_FSP_VERSION_INFO_2
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
@@ -22,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
@@ -63,8 +65,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO_2
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config DCACHE_RAM_BASE
default 0xfef00000