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Docs: Replace Recommonmark with MyST Parser

Browse Source 
Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nicholas Chin
2023-02-21 19:41:06 -07:00
committed by Martin L Roth
parent 9203e25a35
commit 35599f9a66
178 changed files with 1261 additions and 1021 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/northbridge/index.md
View File

@@ -4,4 +4,8 @@ This section contains documentation about coreboot on specific northbridges.
## Vendor
- [Intel](intel/index.md)
```{toctree}
:maxdepth: 1
Intel <intel/index.md>
```

12
Documentation/northbridge/intel/haswell/index.md
View File

@@ -5,8 +5,16 @@ coreboot.
## Proprietary blobs
- [mrc.bin](mrc.bin.md)
```{toctree}
:maxdepth: 1
mrc.bin <mrc.bin.md>
```
## Issues
- [Known issues](known-issues.md)
```{toctree}
:maxdepth: 1
Known issues <known-issues.md>
```

2
Documentation/northbridge/intel/haswell/known-issues.md
View File

@@ -5,7 +5,7 @@ mainboard, there might be additional issues to those listed here.
## PCIe graphics
```eval_rst
```{eval-rst}
Using a PCIe graphics card for display output is not currently
supported. This is because :doc:`./mrc.bin` requires workarounds to
have such a feature working correctly.

8
Documentation/northbridge/intel/index.md
View File

@@ -4,5 +4,9 @@ This section contains documentation about coreboot on specific Intel Northbridge
## Platforms
- [Haswell](haswell/index.md)
- [Sandy Bridge](sandybridge/index.md)
```{toctree}
:maxdepth: 1
Haswell <haswell/index.md>
Sandy Bridge <sandybridge/index.md>
```

10
Documentation/northbridge/intel/sandybridge/index.md
View File

@@ -4,6 +4,10 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid
## Topics
- [Native RAM Initialization](nri.md)
- [RAM initialization feature matrix](nri_features.md)
- [ME Cleaner](me_cleaner.md)
```{toctree}
:maxdepth: 1
Native RAM Initialization <nri.md>
RAM initialization feature matrix <nri_features.md>
ME Cleaner <me_cleaner.md>
```

20
Documentation/northbridge/intel/sandybridge/nri.md
View File

@@ -18,7 +18,7 @@ The memory initialization code has to take care of lots of duties:
* Error handling
## Definitions
```eval_rst
```{eval-rst}
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
+=========+===================================================================+============+==============+
@@ -41,13 +41,25 @@ The memory initialization code has to take care of lots of duties:
```
## (Unofficial) register documentation
- [Sandy Bridge - Register documentation](nri_registers.md)
```{toctree}
:maxdepth: 1
Sandy Bridge - Register documentation <nri_registers.md>
```
## Frequency selection
- [Sandy Bridge - Frequency selection](nri_freq.md)
```{toctree}
:maxdepth: 1
Sandy Bridge - Frequency selection <nri_freq.md>
```
## Read training
- [Sandy Bridge - Read training](nri_read.md)
```{toctree}
:maxdepth: 1
Sandy Bridge - Read training <nri_read.md>
```
### SMBIOS type 17
The SMBIOS specification allows to report the memory configuration in use.

2
Documentation/northbridge/intel/sandybridge/nri_features.md
View File

@@ -14,7 +14,7 @@
## Native raminit implemented features
```eval_rst
```{eval-rst}
+---------------------------+----------------------+-------------+---------+---------------------+
| Option | Supported | Implemented | Working | Comments |
+===========================+======================+=============+=========+=====================+

6
Documentation/northbridge/intel/sandybridge/nri_freq.md
View File

@@ -5,7 +5,7 @@ This chapter explains the frequency selection done on Sandy Bridge and Ivy
Bridge memory initialization.
## Definitions
```eval_rst
```{eval-rst}
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
+=========+===================================================================+============+==============+
@@ -94,7 +94,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
## Sandy Bridge's supported frequencies
```eval_rst
```{eval-rst}
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
+============+===========+==================+=========================+===============+
@@ -113,7 +113,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
```
## Ivy Bridge's supported frequencies
```eval_rst
```{eval-rst}
+------------+-----------+------------------+-------------------------+---------------+
| SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |
+============+===========+==================+=========================+===============+

2
Documentation/northbridge/intel/sandybridge/nri_read.md
View File

@@ -23,7 +23,7 @@ actual delay of every lane can be measured.
The values programmed in read training effect DRAM-to-MC transfers only !
## Definitions
```eval_rst
```{eval-rst}
+---------+-------------------------------------------------------------------+------------+--------------+
| Symbol | Description | Units | Valid region |
+=========+===================================================================+============+==============+

224
Documentation/northbridge/intel/sandybridge/nri_registers.md
View File

@@ -11,7 +11,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -26,7 +26,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -46,7 +46,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -66,7 +66,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -86,7 +86,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -106,7 +106,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -126,7 +126,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -146,7 +146,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -166,7 +166,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -186,7 +186,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -201,7 +201,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -221,7 +221,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -241,7 +241,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -261,7 +261,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -281,7 +281,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -301,7 +301,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -321,7 +321,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -341,7 +341,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -361,7 +361,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -376,7 +376,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -396,7 +396,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -416,7 +416,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -436,7 +436,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -456,7 +456,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -476,7 +476,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -496,7 +496,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -516,7 +516,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -536,7 +536,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -551,7 +551,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -571,7 +571,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -591,7 +591,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -611,7 +611,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -631,7 +631,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -651,7 +651,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -671,7 +671,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -691,7 +691,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -711,7 +711,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -726,7 +726,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -746,7 +746,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -766,7 +766,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -786,7 +786,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -806,7 +806,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -826,7 +826,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -846,7 +846,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -866,7 +866,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 4
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -886,7 +886,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -901,7 +901,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -921,7 +921,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -941,7 +941,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -961,7 +961,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -981,7 +981,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1001,7 +1001,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1021,7 +1021,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1041,7 +1041,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 5
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1061,7 +1061,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1076,7 +1076,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1096,7 +1096,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1126,7 +1126,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1154,7 +1154,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1174,7 +1174,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1194,7 +1194,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1214,7 +1214,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1234,7 +1234,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 6
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1254,7 +1254,7 @@ Please handle with care!
*Desc:* Lane training result Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1269,7 +1269,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 0 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1289,7 +1289,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 1 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1309,7 +1309,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 2 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1329,7 +1329,7 @@ Please handle with care!
*Desc:* Read delay settings, Rank 3 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1349,7 +1349,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 0 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1369,7 +1369,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 1 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1389,7 +1389,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 2 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1409,7 +1409,7 @@ Please handle with care!
*Desc:* Write delay settings, Rank 3 Register, Channel 0, lane 7
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1429,7 +1429,7 @@ Please handle with care!
*Desc:* COMP1 Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1447,7 +1447,7 @@ Please handle with care!
*Desc:* Command crossover enable Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1469,7 +1469,7 @@ Please handle with care!
*Desc:* COMP2 Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1483,7 +1483,7 @@ Please handle with care!
*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1505,7 +1505,7 @@ Please handle with care!
*Desc:* TC_RAP - Timing of DDR - Regular Access Parameters Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1545,7 +1545,7 @@ Please handle with care!
*Desc:* OTHP ODT control Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1565,7 +1565,7 @@ Please handle with care!
*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1581,7 +1581,7 @@ Please handle with care!
*Desc:* Rounttrip time Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1601,7 +1601,7 @@ Please handle with care!
*Desc:* SC_IO_LATENCY Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1623,7 +1623,7 @@ Please handle with care!
*Desc:* RAM training queue, address Register, Channel 0, queue idx 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1641,7 +1641,7 @@ Please handle with care!
*Desc:* RAM training queue, address Register, Channel 0, queue idx 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1659,7 +1659,7 @@ Please handle with care!
*Desc:* RAM training queue, address Register, Channel 0, queue idx 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1677,7 +1677,7 @@ Please handle with care!
*Desc:* RAM training queue, address Register, Channel 0, queue idx 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1695,7 +1695,7 @@ Please handle with care!
*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1713,7 +1713,7 @@ Please handle with care!
*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1731,7 +1731,7 @@ Please handle with care!
*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1749,7 +1749,7 @@ Please handle with care!
*Desc:* RAM training queue, command IO Register, Channel 0, queue idx 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1767,7 +1767,7 @@ Please handle with care!
*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1781,7 +1781,7 @@ Please handle with care!
*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 1
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1795,7 +1795,7 @@ Please handle with care!
*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 2
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1809,7 +1809,7 @@ Please handle with care!
*Desc:* RAM training queue, cooldown Register, Channel 0, queue idx 3
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1823,7 +1823,7 @@ Please handle with care!
*Desc:* RAM training queue, cooldown Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1839,7 +1839,7 @@ Please handle with care!
*Desc:* TC - Refresh parameters Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1859,7 +1859,7 @@ Please handle with care!
*Desc:* SRFTP Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1879,7 +1879,7 @@ Please handle with care!
*Desc:* Scheduler parameters Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1893,7 +1893,7 @@ Please handle with care!
*Desc:* PM - Power-down configuration, Broadcast Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1929,7 +1929,7 @@ Please handle with care!
*Desc:* Power mode preset Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1943,7 +1943,7 @@ Please handle with care!
*Desc:* TC - Refresh parameters Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1964,7 +1964,7 @@ Please handle with care!
*Desc:* TC - Refresh parameters Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -1984,7 +1984,7 @@ Please handle with care!
*Desc:* Global channel size control Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2023,7 +2023,7 @@ Please handle with care!
*Desc:* Address Decode Register, Channel 0
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2072,7 +2072,7 @@ Please handle with care!
*Desc:* Global DDR3 control Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2090,7 +2090,7 @@ Please handle with care!
*Desc:* Version Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2104,7 +2104,7 @@ Please handle with care!
*Desc:* PM - Self refresh config Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2123,7 +2123,7 @@ Please handle with care!
*Desc:* RCOMP status Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2137,7 +2137,7 @@ Please handle with care!
*Desc:* ECC - Address compare for ECC error injection Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2151,7 +2151,7 @@ Please handle with care!
*Desc:* ECC - Address mask for ECC error injection Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2168,7 +2168,7 @@ Please handle with care!
*Desc:* MC_BIOS_REQ Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2189,7 +2189,7 @@ Please handle with care!
*Desc:* MC_BIOS_DATA Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+
@@ -2208,7 +2208,7 @@ Please handle with care!
*Desc:* RCOMP control Register
```eval_rst
```{eval-rst}
+-----------+------------------------------------------------------------------+
| Bit | Description |
+===========+==================================================================+