From 3588243177b8a6af1ca239001aba1251f74e738e Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 14 Mar 2024 15:15:40 +0900 Subject: [PATCH] mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMe NVMe using clk_src[0] and clk_req[1] mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=0,clk_req=1 in mFIT. BUG=b:328318578 TEST=build firmware and veirfy suspend function on NVMe SKU DUT. Cq-Depend: chrome-internal:7063434 Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/xol/overridetree.cb | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index b825ddd2f5..80d15feb62 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -268,10 +268,13 @@ chip soc/intel/alderlake end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 0 + # Enable NVMe SSD using clk_src0 and clk_req1 mapping to hardware + # design. Due to inconsistency between PMC firmware and FSP, we need + # to set clk_src to clk_req number, not same as hardware mapping in + # coreboot. Then swap correct setting clksrc, clkreq in mFIT. register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 0, + .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME