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tree: Replace And(a,b,c) with ASL 2.0 syntax

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Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.

Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2022-12-16 07:11:17 +01:00
parent 86bc2e708d
commit 35e65a8bc3
21 changed files with 60 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/gma/acpi/configure_brightness_levels.asl
View File

@ -76,7 +76,7 @@
Sleep (1)
If (And (ASLC, 0x2) == 0) {
/* Request has been processed, check status: */
And (ASLC >> 12, 0x3, Local1)
Local1 = (ASLC >> 12) & 3
If (Local1 == 0) {
Return (Zero)
} Else {

2
src/ec/google/chromeec/acpi/ec.asl
View File

@ -630,7 +630,7 @@ Device (EC0)
*/
Method (UPPC, 1, Serialized)
{
And (USPP, Not (1 << Arg0), USPP)
USPP &= Not (1 << Arg0)
}
#endif

2
src/ec/quanta/ene_kb3940q/acpi/ec.asl
View File

@ -131,7 +131,7 @@ Device (EC0)
Local0 = CTMP
// Use Local0 to avoid iasl warning: Method Local is set but never used
And(Local0, Ones, Local0)
Local0 &= Ones
// Find and program number of P-States
MPST = SizeOf (\_SB.CP00._PSS)

4
src/ec/quanta/it8518/acpi/battery.asl
View File

@ -244,7 +244,7 @@ Device (BATX)
If (ACPW)
{
// Set only charging/discharging bits
And (Local0, 0x03, Local1)
Local1 = Local0 & 3
}
Else
{
@ -253,7 +253,7 @@ Device (BATX)
}
// Flag if the battery level is critical
And (Local0, 0x04, Local4)
Local4 = Local0 & 4
Local1 |= Local4
PBST[0] = Local1

6
src/ec/smsc/mec1308/acpi/battery.asl
View File

@ -61,7 +61,7 @@ Device (BAT0)
{
Local0 = Arg0 >> 8
Local1 = Arg0 << 8
And (Local1, 0xFF00, Local1)
Local1 &= 0xFF00
Local0 |= Local1
If (Local0 == 0xFFFF) {
Local0 = 0xFFFFFFFF
@ -111,14 +111,14 @@ Device (BAT0)
// Check if AC is present
If (ACEX) {
// Set only charging/discharging bits
And (Local0, 0x03, Local1)
Local1 = Local0 & 3
} Else {
// Always discharging when on battery power
Local1 = 0x01
}
// Flag if the battery level is critical
And (Local0, 0x04, Local4)
Local4 = Local0 & 4
Local1 |= Local4
PBST[0] = Local1

4
src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
View File

@ -36,7 +36,7 @@ Device (MBRS)
CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
And (\_SB.PCI0.RLAR, 0x03FF, Local1)
Local1 = \_SB.PCI0.RLAR & 0x03FF
Local1++
If (Local1 > 0x40)
{
@ -47,7 +47,7 @@ Device (MBRS)
CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
And (\_SB.PCI0.TOLM, 0xF800, Local1)
Local1 = \_SB.PCI0.TOLM & 0xF800
Local1 >>= 4
Local1--
If (Local1 > 0x10)

2
src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
View File

@ -41,7 +41,7 @@ Method (_CRS, 0, NotSerialized)
CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
And (\_SB.PCI0.TOLM, 0xF800, Local1)
Local1 = \_SB.PCI0.TOLM & 0xF800
Local1 >>= 4
MEML = Local1 << 0x14
MEMH = IO_APIC_ADDR - 1

4
src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
View File

@ -115,7 +115,7 @@ Device (ICH0)
Local0 = PBAR
If (Local0 && 1)
{
And (Local0, 0xFFFE, Local0)
Local0 &= 0xFFFE
IOA1 = Local0
IOA2 = Local0
IOAL = 0x80
@ -129,7 +129,7 @@ Device (ICH0)
Local0 = GBAR
If (Local0 && 1) {
And (Local0, 0xFFFE, Local0)
Local0 &= 0xFFFE
IOS1 = Local0
IOS2 = Local0
IOSL = 0x40

10
src/mainboard/aopen/dxplplusu/acpi/superio.asl
View File

@ -110,28 +110,28 @@ Method (_INI, 0, NotSerialized)
/* GPIO initial output levels */
Local0 = GP_1
And( Local0, 0x7C, Local0)
Local0 &= 0x7C
Local0 |= 0x81
GP_1 = Local0
Local0 = GP_2
And( Local0, 0xFE, Local0)
Local0 &= 0xFE
Local0 |= 0
GP_2 = Local0
Local0 = GP_3
And( Local0, 0x7F, Local0)
Local0 &= 0x7F
Local0 |= 0x80
GP_3 = Local0
Local0 = GP_4
And( Local0, 0x7F, Local0)
Local0 &= 0x7F
Local0 |= 0
GP_4 = Local0
/* Power Led */
Local0 = LED1
And( Local0, 0xfc, Local0)
Local0 &= 0xfc
Local0 |= 1
LED1 = Local0

2
src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl
View File

@ -10,7 +10,7 @@ Scope (\_SB)
{
Method (GPID, 0, Serialized) // GPID: Get Project ID for Terra2/Terra3
{
And(\BDID >> 3, 0x01, Local0)
Local0 = (\BDID >> 3) & 1
Return (Local0)
}
}

2
src/mainboard/lenovo/s230u/acpi/gpe.asl
View File

@ -20,7 +20,7 @@ Scope (_GPE)
Local0 = One << Arg1
If (Arg0 == Zero) {
Not (Local0, Local0)
And (GIV0, Local0, GIV0)
GIV0 &= Local0
} Else {
GIV0 |= Local0
}

2
src/soc/intel/baytrail/acpi/lpe.asl
View File

@ -93,7 +93,7 @@ Device (LPEA)
Method (_ON)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

20
src/soc/intel/baytrail/acpi/lpss.asl
View File

@ -118,7 +118,7 @@ Device (I2C1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -177,7 +177,7 @@ Device (I2C2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -236,7 +236,7 @@ Device (I2C3)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -295,7 +295,7 @@ Device (I2C4)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -354,7 +354,7 @@ Device (I2C5)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -413,7 +413,7 @@ Device (I2C6)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -472,7 +472,7 @@ Device (I2C7)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -525,7 +525,7 @@ Device (SPI1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -634,7 +634,7 @@ Device (UAR1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -687,7 +687,7 @@ Device (UAR2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

6
src/soc/intel/baytrail/acpi/scc.asl
View File

@ -47,7 +47,7 @@ Device (EMMC)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
@ -110,7 +110,7 @@ Device (SDIO)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -162,7 +162,7 @@ Device (SDCD)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

2
src/soc/intel/braswell/acpi/lpe.asl
View File

@ -93,7 +93,7 @@ Device (LPEA)
Method (_ON)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

18
src/soc/intel/braswell/acpi/lpss.asl
View File

@ -149,7 +149,7 @@ Device (I2C1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -208,7 +208,7 @@ Device (I2C2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -267,7 +267,7 @@ Device (I2C3)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -326,7 +326,7 @@ Device (I2C4)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -385,7 +385,7 @@ Device (I2C5)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -444,7 +444,7 @@ Device (I2C6)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -503,7 +503,7 @@ Device (I2C7)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -556,7 +556,7 @@ Device (UAR1)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -609,7 +609,7 @@ Device (UAR2)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

6
src/soc/intel/braswell/acpi/scc.asl
View File

@ -47,7 +47,7 @@ Device (EMMC)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
@ -148,7 +148,7 @@ Device (SDIO)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}
@ -200,7 +200,7 @@ Device (SDCD)
Method (_PS0)
{
And (PSAT, 0xfffffffc, PSAT)
PSAT &= 0xfffffffc
PSAT |= 0
}
}

4
src/soc/intel/cannonlake/acpi/scs.asl
View File

@ -45,7 +45,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}
@ -209,7 +209,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE)

4
src/soc/intel/icelake/acpi/scs.asl
View File

@ -43,7 +43,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}
@ -96,7 +96,7 @@ Scope (\_SB.PCI0) {
^^SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
PMCR &= 0xFFFC
^TEMP = PMCR
}

16
src/superio/winbond/w83627hf/acpi/superio.asl
View File

@ -399,9 +399,9 @@ Device(SIO) {
Name (_UID, "w83627hf-pport")
Method (MODE, 1) {
And(Arg0, 0x07, Local0)
Local0 = Arg0 & 7
ENTER_CONFIG_MODE (1)
And(OPT1, 0x3, Local1)
Local1 = OPT1 & 3
OPT1 = Local1 | Local0
EXIT_CONFIG_MODE()
}
@ -420,7 +420,7 @@ Device(SIO) {
{
Local0 = 0x00
ENTER_CONFIG_MODE (1)
And(OPT1, 0x3, Local1)
Local1 = OPT1 & 3
If (ACTR) {
If (Local1 != 2) {
Local0 = 0x0D
@ -488,8 +488,8 @@ Device(SIO) {
IOR0 = Local1
/* Set align and length based on active parallel port mode */
And(Local2, 0x3, Local3)
And(Local2, 0x4, Local4)
Local3 = Local2 & 3
Local4 = Local2 & 4
If (Local4) {
IOAL = 0x04
}
@ -578,7 +578,7 @@ Device(SIO) {
IO1H = Local1
/* Mode */
Local3 = OPT1
And (Local3, 0xF8, Local3)
Local3 &= 0xF8
OPT1 = Local2 | Local3
/* DMA off */
DMA0 = 0x04
@ -1347,7 +1347,7 @@ Device(SIO) {
{
ENTER_CONFIG_MODE (9)
Local0 = OPT4
And(Local0, 63, Local0)
Local0 &= 63
OPT4 = Local0 | (And(Arg0, 0x03) << 6)
EXIT_CONFIG_MODE ()
}
@ -1357,7 +1357,7 @@ Device(SIO) {
{
ENTER_CONFIG_MODE (8)
Local0 = OPT4
And(Local0, 63, Local0)
Local0 &= 63
OPT4 = Local0 | (And(Arg0, 0x03) << 6)
EXIT_CONFIG_MODE ()
}

2
src/superio/winbond/w83667hg-a/ps2_controller.asl
View File

@ -49,7 +49,7 @@
SIOI = 0x87
/* Read Pin56 function select */
And(CR2A, 0x2, Local0)
Local0 = CR2A & 2
/* Restore default SuperIO access */
SIOI = 0xAA