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nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK

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There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.

Enabling the console will be done in a followup patch.

Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2019-11-12 18:11:03 +01:00
committed by Patrick Georgi
parent 67d59d1756
commit 360d94745f
52 changed files with 65 additions and 64 deletions
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6
src/cpu/intel/model_206ax/Kconfig
View File

@@ -21,10 +21,8 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
select C_ENVIRONMENT_BOOTBLOCK
select NO_BOOTBLOCK_CONSOLE
config SMM_TSEG_SIZE
hex

6
src/cpu/intel/model_206ax/Makefile.inc
View File

@@ -21,7 +21,11 @@ smm-y += finalize.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += bootblock.c
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../../x86/early_reset.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c

37
src/cpu/intel/model_206ax/bootblock.c
View File

@@ -13,13 +13,11 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <halt.h>
#include <cpu/intel/car/bootblock.h>
#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"
#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
@@ -30,35 +28,6 @@
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif
static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
{
msr_t msr;
disable_cache();
set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
@@ -109,10 +78,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
halt();
}
static void bootblock_cpu_init(void)
void bootblock_early_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
enable_rom_caching();
intel_update_microcode_from_cbfs();
}