nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK

There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.

Enabling the console will be done in a followup patch.

Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/southbridge/intel/bd82x6x/Kconfig

@@ -57,10 +57,6 @@ config DRAM_RESET_GATE_GPIO
 	int
 	default 60
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/bd82x6x/bootblock.c"
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default n

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -15,6 +15,9 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
 
+bootblock-y += bootblock.c
+bootblock-y += early_pch.c
+
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c

src/southbridge/intel/bd82x6x/bootblock.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/intel/car/bootblock.h>
 #include <device/pci_ops.h>
 #include "pch.h"
 
@@ -32,18 +33,8 @@ static void enable_spi_prefetch(void)
 
 static void enable_port80_on_lpc(void)
 {
-	pci_devfn_t dev = PCH_LPC_DEV;
-
 	/* Enable port 80 POST on LPC */
-	pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-#if 0
 	RCBA32(GCS) &= (~0x04);
-#else
-	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
-	u32 reg32 = *gcs;
-	reg32 = reg32 & ~0x04;
-	*gcs = reg32;
-#endif
 }
 
 static void set_spi_speed(void)
@@ -66,9 +57,12 @@ static void set_spi_speed(void)
 	RCBA8(0x3893) = ssfc;
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	enable_spi_prefetch();
+
+	early_pch_init();
+
 	enable_port80_on_lpc();
 	set_spi_speed();