libpayload: Add dwc2 usb driver
BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211053 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Patrick Georgi
parent
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356
payloads/libpayload/drivers/usb/dwc2.c
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356
payloads/libpayload/drivers/usb/dwc2.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Rockchip Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <libpayload.h>
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#include <arch/cache.h>
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#include "dwc2.h"
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#include "dwc2_private.h"
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static void dummy(hci_t *controller)
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{
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}
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static void dwc2_reinit(hci_t *controller)
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{
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dwc2_reg_t *reg = DWC2_REG(controller);
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gusbcfg_t gusbcfg = { .d32 = 0 };
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grstctl_t grstctl = { .d32 = 0 };
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gintsts_t gintsts = { .d32 = 0 };
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gahbcfg_t gahbcfg = { .d32 = 0 };
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grxfsiz_t grxfsiz = { .d32 = 0 };
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hcintmsk_t hcintmsk = { .d32 = 0 };
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gnptxfsiz_t gnptxfsiz = { .d32 = 0 };
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const int timeout = 10000;
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int i;
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/* Wait for AHB idle */
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for (i = 0; i < timeout; i++) {
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udelay(1);
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grstctl.d32 = readl(®->core.grstctl);
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if (grstctl.ahbidle)
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break;
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}
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if (i == timeout)
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fatal("DWC2 Init error AHB Idle\n");
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/* Restart the Phy Clock */
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writel(0x0, ®->pcgr.pcgcctl);
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/* Core soft reset */
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grstctl.csftrst = 1;
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writel(grstctl.d32, ®->core.grstctl);
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for (i = 0; i < timeout; i++) {
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udelay(1);
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grstctl.d32 = readl(®->core.grstctl);
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if (!grstctl.csftrst)
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break;
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}
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if (i == timeout)
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fatal("DWC2 Init error reset fail\n");
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/* Set 16bit PHY if & Force host mode */
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gusbcfg.d32 = readl(®->core.gusbcfg);
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gusbcfg.phyif = 1;
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gusbcfg.forcehstmode = 1;
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gusbcfg.forcedevmode = 0;
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writel(gusbcfg.d32, ®->core.gusbcfg);
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/* Wait for force host mode effect, it may takes 100ms */
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for (i = 0; i < timeout; i++) {
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udelay(10);
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gintsts.d32 = readl(®->core.gintsts);
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if (gintsts.curmod)
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break;
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}
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if (i == timeout)
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fatal("DWC2 Init error force host mode fail\n");
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/*
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* Config FIFO
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* The non-periodic tx fifo and rx fifo share one continuous
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* piece of IP-internal SRAM.
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*/
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grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH;
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writel(grxfsiz.d32, ®->core.grxfsiz);
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gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH;
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gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH;
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writel(gnptxfsiz.d32, ®->core.gnptxfsiz);
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/* Init host channels */
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hcintmsk.xfercomp = 1;
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hcintmsk.xacterr = 1;
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hcintmsk.stall = 1;
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hcintmsk.chhltd = 1;
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hcintmsk.bblerr = 1;
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for (i = 0; i < MAX_EPS_CHANNELS; i++)
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writel(hcintmsk.d32, ®->host.hchn[i].hcintmaskn);
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/* Unmask interrupt and configure DMA mode */
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gahbcfg.glblintrmsk = 1;
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gahbcfg.hbstlen = DMA_BURST_INCR8;
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gahbcfg.dmaen = 1;
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writel(gahbcfg.d32, ®->core.gahbcfg);
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DWC2_INST(controller)->hprt0 = ®->host.hprt;
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usb_debug("DWC2 init finished!\n");
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}
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static void dwc2_shutdown(hci_t *controller)
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{
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detach_controller(controller);
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free(DWC2_INST(controller)->dma_buffer);
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free(DWC2_INST(controller));
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free(controller);
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}
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/*
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* This function returns the actual transfer length when the transfer succeeded
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* or an error code if the transfer failed
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*/
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static int
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wait_for_complete(endpoint_t *ep, uint32_t ch_num)
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{
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hcint_t hcint;
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hcchar_t hcchar;
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hctsiz_t hctsiz;
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dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
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int timeout = 600000; /* time out after 600000 * 5us == 3s */
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/*
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* TODO: We should take care of up to three times of transfer error
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* retry here, according to the USB 2.0 spec 4.5.2
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*/
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do {
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udelay(5);
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hcint.d32 = readl(®->host.hchn[ch_num].hcintn);
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hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn);
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if (hcint.chhltd) {
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writel(hcint.d32, ®->host.hchn[ch_num].hcintn);
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if (hcint.xfercomp)
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return hctsiz.xfersize;
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else if (hcint.xacterr)
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return -HCSTAT_XFERERR;
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else if (hcint.bblerr)
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return -HCSTAT_BABBLE;
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else if (hcint.stall)
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return -HCSTAT_STALL;
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else
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return -HCSTAT_UNKNOW;
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}
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} while (timeout--);
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/* Release the channel on timeout */
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hcchar.d32 = readl(®->host.hchn[ch_num].hccharn);
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if (hcchar.chen) {
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/*
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* Programming the HCCHARn register with the chdis and
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* chena bits set to 1 at the same time to disable the
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* channel and the core will generate a channel halted
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* interrupt.
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*/
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hcchar.chdis = 1;
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writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
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do {
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hcchar.d32 = readl(®->host.hchn[ch_num].hccharn);
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} while (hcchar.chen);
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}
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/* Clear all pending interrupt flags */
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hcint.d32 = ~0;
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writel(hcint.d32, ®->host.hchn[ch_num].hcintn);
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return -HCSTAT_TIMEOUT;
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}
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static int
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dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
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uint32_t ch_num, u8 *data_buf)
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{
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uint32_t do_copy;
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int ret;
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uint32_t packet_cnt;
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uint32_t packet_size;
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uint32_t transferred = 0;
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uint32_t inpkt_length;
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hctsiz_t hctsiz = { .d32 = 0 };
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hcchar_t hcchar = { .d32 = 0 };
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void *aligned_buf;
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dwc2_reg_t *reg = DWC2_REG(ep->dev->controller);
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packet_size = ep->maxpacketsize;
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packet_cnt = ALIGN_UP(size, packet_size) / packet_size;
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inpkt_length = packet_cnt * packet_size;
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/* At least 1 packet should be programed */
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packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt;
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/*
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* For an IN, this field is the buffer size that the application has
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* reserved for the transfer. The application should program this field
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* as integer multiple of the maximum packet size for IN transactions.
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*/
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hctsiz.xfersize = (dir == EPDIR_OUT) ? size : inpkt_length;
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hctsiz.pktcnt = packet_cnt;
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hctsiz.pid = pid;
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hcchar.mps = packet_size;
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hcchar.epnum = ep->endpoint & 0xf;
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hcchar.epdir = dir;
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hcchar.eptype = ep->type;
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hcchar.multicnt = 1;
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hcchar.devaddr = ep->dev->address;
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hcchar.chdis = 0;
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hcchar.chen = 1;
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if (size > DMA_SIZE) {
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usb_debug("Transfer too large: %d\n", size);
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return -1;
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}
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/*
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* Check the buffer address which should be 4-byte aligned and DMA
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* coherent
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*/
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do_copy = !dma_coherent(data_buf) || ((uintptr_t)data_buf & 0x3);
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aligned_buf = do_copy ? DWC2_INST(ep->dev->controller)->dma_buffer :
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data_buf;
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if (do_copy && (dir == EPDIR_OUT))
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memcpy(aligned_buf, data_buf, size);
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writel(hctsiz.d32, ®->host.hchn[ch_num].hctsizn);
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writel((uint32_t)aligned_buf, ®->host.hchn[ch_num].hcdman);
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writel(hcchar.d32, ®->host.hchn[ch_num].hccharn);
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ret = wait_for_complete(ep, ch_num);
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if (ret >= 0) {
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/* Calculate actual transferred length */
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transferred = (dir == EPDIR_IN) ? inpkt_length - ret : ret;
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if (do_copy && (dir == EPDIR_IN))
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memcpy(data_buf, aligned_buf, transferred);
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}
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/* Save data toggle */
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hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn);
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ep->toggle = hctsiz.pid;
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if (ret < 0) {
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usb_debug("%s Transfer stop code: %x\n", __func__, ret);
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return ret;
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}
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return transferred;
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}
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static int
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dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
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{
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ep_dir_t data_dir;
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if (ep->direction == IN)
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data_dir = EPDIR_IN;
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else if (ep->direction == OUT)
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data_dir = EPDIR_OUT;
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else
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return -1;
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return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src);
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}
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static int
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dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
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int dalen, u8 *src)
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{
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int ret = 0;
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ep_dir_t data_dir;
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if (dir == IN)
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data_dir = EPDIR_IN;
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else if (dir == OUT)
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data_dir = EPDIR_OUT;
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else
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return -1;
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/* Setup Phase */
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if (dwc2_transfer(&dev->endpoints[0], drlen, PID_SETUP, EPDIR_OUT, 0,
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setup) < 0)
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return -1;
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/* Data Phase */
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if (dalen > 0) {
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ret = dwc2_transfer(&dev->endpoints[0], dalen, PID_DATA1,
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data_dir, 0, src);
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if (ret < 0)
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return -1;
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}
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/* Status Phase */
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if (dwc2_transfer(&dev->endpoints[0], 0, PID_DATA1, !data_dir, 0,
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NULL) < 0)
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return -1;
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return ret;
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}
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hci_t *dwc2_init(void *bar)
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{
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hci_t *controller = new_controller();
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controller->instance = xzalloc(sizeof(dwc_ctrl_t));
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DWC2_INST(controller)->dma_buffer = dma_malloc(DMA_SIZE);
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if (!DWC2_INST(controller)->dma_buffer) {
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usb_debug("Not enough DMA memory for DWC2 bounce buffer\n");
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goto free_dwc2;
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}
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controller->type = DWC2;
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controller->start = dummy;
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controller->stop = dummy;
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controller->reset = dummy;
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controller->init = dwc2_reinit;
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controller->shutdown = dwc2_shutdown;
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controller->bulk = dwc2_bulk;
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controller->control = dwc2_control;
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controller->set_address = generic_set_address;
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controller->finish_device_config = NULL;
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controller->destroy_device = NULL;
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controller->create_intr_queue = NULL;
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controller->destroy_intr_queue = NULL;
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controller->poll_intr_queue = NULL;
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controller->reg_base = (uintptr_t)bar;
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init_device_entry(controller, 0);
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/* Init controller */
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controller->init(controller);
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/* Setup up root hub */
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controller->devices[0]->controller = controller;
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controller->devices[0]->init = dwc2_rh_init;
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controller->devices[0]->init(controller->devices[0]);
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return controller;
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free_dwc2:
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detach_controller(controller);
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free(DWC2_INST(controller));
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free(controller);
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return NULL;
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}
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