soc/intel/apollolake: Add support for GSPI

BUG=b:73133848
BRANCH=None
TEST=Build coreboot for Octopus board. Tested the GSPI interface
with a SPI EEPROM and got correct response to a RDID command

Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/24906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/chip.h

@@ -20,6 +20,7 @@
 #define _SOC_APOLLOLAKE_CHIP_H_
 
 #include <commonlib/helpers.h>
+#include <intelblocks/gspi.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #include <intelblocks/lpc_lib.h>
@@ -39,6 +40,9 @@ enum pnp_settings {
 };
 
 struct soc_intel_apollolake_config {
+	/* GSPI */
+	struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
 	/*
 	 * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
 	 * four CLKREQ inputs, but six root ports. Root ports without an