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ec/google/chromec: Add DPTC support for host event 1/2/9

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DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for
host event lid-open/lid-close/Thermal Threshold.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
EricKY Cheng
2022-09-23 17:04:01 +08:00
committed by Raul Rangel
parent 23d224069f
commit 366b205f2d
1 changed files with 16 additions and 0 deletions
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16
src/ec/google/chromeec/acpi/ec.asl
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@@ -229,6 +229,11 @@ Device (EC0)
Method (_Q01, 0, NotSerialized) Method (_Q01, 0, NotSerialized)
{ {
Printf ("EC: LID CLOSE") Printf ("EC: LID CLOSE")
#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC()
}
#endif
Store (LIDS, \LIDS) Store (LIDS, \LIDS)
#ifdef EC_ENABLE_LID_SWITCH #ifdef EC_ENABLE_LID_SWITCH
Notify (LID0, 0x80) Notify (LID0, 0x80)
@@ -239,6 +244,11 @@ Device (EC0)
Method (_Q02, 0, NotSerialized) Method (_Q02, 0, NotSerialized)
{ {
Printf ("EC: LID OPEN") Printf ("EC: LID OPEN")
#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC()
}
#endif
Store (LIDS, \LIDS) Store (LIDS, \LIDS)
Notify (CREC, 0x2) Notify (CREC, 0x2)
#ifdef EC_ENABLE_LID_SWITCH #ifdef EC_ENABLE_LID_SWITCH
@@ -540,6 +550,12 @@ Device (EC0)
*/ */
Method (_Q09, 0, NotSerialized) Method (_Q09, 0, NotSerialized)
{ {
#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC()
}
#endif
If (!Acquire (^PATM, 1000)) { If (!Acquire (^PATM, 1000)) {
/* Read sensor ID for event */ /* Read sensor ID for event */
Store (^PATI, Local0) Store (^PATI, Local0)