mainboard: Add ASRock H81M-HDS
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Tristan Corrick
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Patrick Georgi
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Documentation/mainboard/asrock/h81m-hds.md
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Documentation/mainboard/asrock/h81m-hds.md
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# ASRock H81M-HDS
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This page describes how to run coreboot on the [ASRock H81M-HDS].
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## Required proprietary blobs
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This board currently requires a proprietary blob in order to initialise
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the RAM and a few other components. The blob largely consists of Intel's
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Memory Reference Code (shortened to mrc), and is just under 200 KiB
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in size. It is also known as a system agent binary. Unfortunately,
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it is not currently possible to distribute this as part of coreboot.
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However, the mrc can be obtained from a Haswell Chromebook firmware
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image, and you might find one online. The mrc from a ChromeOS image can
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be extracted with the following command. If extracting from a "standard"
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coreboot image, omit `-r RO_SECTION`.
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```bash
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cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION
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```
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Now, place mrc.bin in the root of the coreboot directory.
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Alternatively, place it anywhere you want, and set `MRC_FILE` to its
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location when building coreboot.
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## Building coreboot
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A fully working image should be possible just by setting your MAC
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address and obtaining the Haswell mrc. You can set the basic config
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with the following commands. However, it is strongly advised to use
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`make menuconfig` afterwards (or instead), so that you can see all of
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the settings.
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```bash
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make distclean # Note: this will remove your current config, if it exists.
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touch .config
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./util/scripts/config --enable VENDOR_ASROCK
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./util/scripts/config --enable BOARD_ASROCK_H81M_HDS
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./util/scripts/config --enable HAVE_MRC
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./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in!
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make olddefconfig
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```
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If you don't plan on using coreboot's serial console to collect logs,
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you might want to disable it at this point (`./util/scripts/config
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--disable CONSOLE_SERIAL`). It should reduce the boot time by several
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seconds. However, a more flexible method is to change the console log
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level from within an OS using `util/nvramtool`, or with the `nvramcui`
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payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. By default, only
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the BIOS region of the flash is writable. If you wish to change any
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other region, such as the Management Engine or firmware descriptor, then
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an external programmer is required (unless you find a clever way around
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the flash protection).
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The following command may be used to flash coreboot:
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```bash
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sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
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```
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The use of `--noverify-all` is required since the Management Engine
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region is not readable even by the host.
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### External programming
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The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a
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Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV].
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The chip is located to the bottom right-hand side of the board. For
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a precise location, refer to section 1.4 (Motherboard Layout) of the
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[board manual], where the chip is labelled "32Mb BIOS". Take note of
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the chip's orientation, remove it from its socket, and flash it with
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an external programmer. For reference, the notch in the chip should be
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facing towards the bottom of the board.
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## Known issues
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- PCIe graphics is non-functional. The PCIe 16x slot doesn't work
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with other devices, either.
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- The VGA port doesn't work until the OS reinitialises the display.
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- There is no automatic, OS-independent fan control. This is because
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the super I/O hardware monitor can only obtain valid CPU temperature
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readings from the PECI agent, but the required driver doesn't exist
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in coreboot. The `coretemp` driver can still be used for accurate CPU
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temperature readings from an OS.
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## Untested
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- parallel port
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- PS/2 keyboard
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- EHCI debug
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- TPM
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- infrared module
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- chassis intrusion header
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- chassis speaker header
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## Working
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- USB
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- S3 suspend/resume
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- Gigabit Ethernet
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- integrated graphics
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- PCIe (but not the 16x slot, see [Known issues](#known-issues))
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- SATA
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- PS/2 mouse
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- serial port
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- hardware monitor (see [Known issues](#known-issues))
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- onboard audio
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- front panel audio
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- initialisation with Haswell mrc version 1.6.1 build 2
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- graphics init with libgfxinit (see [Known issues](#known-issues))
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- flashrom under the vendor firmware
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- flashrom under coreboot
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- Wake-on-LAN
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- Using `me_cleaner`
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | Intel Haswell |
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+------------------+--------------------------------------------------+
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| Southbridge | Intel Lynx Point (H81) |
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+------------------+--------------------------------------------------+
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| CPU | Intel Haswell (LGA1150) |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776 |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
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[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
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@@ -6,6 +6,10 @@ This section contains documentation about coreboot on specific mainboards.
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- [P8H61-M LX](asus/p8h61-m_lx.md)
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## ASRock
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- [H81M-HDS](asrock/h81m-hds.md)
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## Cavium
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- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
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