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mainboard: Add ASRock H81M-HDS

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Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9.

This board works quite well under coreboot. A list of what works and
what doesn't can be found in the documentation part of this commit.

The file `data.vbt` matches the VBT in the latest stable version of the
vendor firmware (version 2.20).

Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Tristan Corrick
2018-10-31 03:02:11 +13:00
committed by Patrick Georgi
parent b2632cec0e
commit 3693294112
20 changed files with 1042 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
src/mainboard/asrock/h81m-hds/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_ASROCK_H81M_HDS
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096
select CPU_INTEL_HASWELL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
select NORTHBRIDGE_INTEL_HASWELL
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select TSC_MONOTONIC_TIMER
config CBFS_SIZE
hex
default 0x200000
#
# The override of GFX_GMA_CPU_VARIANT should be removed once the patches
# for dynamic CPU detection are merged in libgfxinit.
#
config GFX_GMA_CPU_VARIANT
string
default "Normal"
config MAINBOARD_DIR
string
default asrock/h81m-hds
config MAINBOARD_PART_NUMBER
string
default "H81M-HDS"
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x8c5c
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1849
# This is overridden if CMOS is used for configuration values.
config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
bool
default n
config MAX_CPUS
int
default 8
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
#
# Since this is a desktop board, the assumption is made that most users
# would want CMOS configuration enabled by default.
#
config USE_OPTION_TABLE
bool
default y
endif

2
src/mainboard/asrock/h81m-hds/Kconfig.name Normal file
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config BOARD_ASROCK_H81M_HDS
bool "H81M-HDS"

17
src/mainboard/asrock/h81m-hds/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

0
src/mainboard/asrock/h81m-hds/acpi/ec.asl Normal file
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24
src/mainboard/asrock/h81m-hds/acpi/platform.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Method(_WAK, 1)
{
Return (Package() { 0, 0 })
}
Method(_PTS, 1)
{
}

26
src/mainboard/asrock/h81m-hds/acpi/superio.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define NCT6776_SHOW_PP
#define NCT6776_SHOW_SP1
#define NCT6776_SHOW_KBC
#define NCT6776_SHOW_HWM
#undef NCT6776_SHOW_GPIO
#include <superio/nuvoton/nct6776/acpi/superio.asl>

21
src/mainboard/asrock/h81m-hds/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/lynxpoint/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs)
{
}

7
src/mainboard/asrock/h81m-hds/board_info.txt Normal file
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Category: desktop
Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/
ROM package: DIP-8
ROM protocol: SPI
ROM socketed: y
Flashrom support: y
Release year: 2013

4
src/mainboard/asrock/h81m-hds/cmos.default Normal file
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boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable

90
src/mainboard/asrock/h81m-hds/cmos.layout Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 3 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 4 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 1 power_on_after_fail
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
3 0 Fallback
3 1 Normal
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
# -----------------------------------------------------------------
checksums
checksum 392 415 984

BIN
src/mainboard/asrock/h81m-hds/data.vbt Normal file
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Binary file not shown.

173
src/mainboard/asrock/h81m-hds/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/haswell
register "gpu_ddi_e_connected" = "1"
device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x1849 0x0c00
end
device pci 01.0 on # PCIe graphics
subsystemid 0x1849 0x0c01
end
device pci 02.0 on # VGA controller
subsystemid 0x1849 0x0402
end
device pci 03.0 on # Mini-HD audio
subsystemid 0x1849 0x0c0c
end
chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8a"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x8a"
register "sata_ahci" = "1"
register "sata_port_map" = "0x33"
register "gen1_dec" = "0x00000295" # Super I/O HWM
device pci 14.0 on # xHCI controller
subsystemid 0x1849 0x8c31
end
device pci 16.0 on # Management Engine interface 1
subsystemid 0x1849 0x8c3a
end
device pci 16.1 off end # Management Engine interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on # EHCI controller #2
subsystemid 0x1849 0x8c2d
end
device pci 1b.0 on # HD audio controller
subsystemid 0x1849 0x7662
end
device pci 1c.0 on # PCIe port #1
subsystemid 0x1849 0x8c10
end
device pci 1c.1 off end # PCIe port #2
device pci 1c.2 off end # PCIe port #3
device pci 1c.3 on # Realtek Gigabit Ethernet
subsystemid 0x1849 0x8c16
chip drivers/net
register "customized_leds" = "0x0824"
device pci 00.0 on
subsystemid 0x1849 0x8168
end
end
end
device pci 1c.4 on # ASMedia USB controller
subsystemid 0x1849 0x8c18
device pci 00.0 on
subsystemid 0x1849 0x1042
end
end
device pci 1c.5 on # PCIe 1x slot
subsystemid 0x1849 0x8c1a
end
device pci 1c.6 off end # PCIe port #7
device pci 1c.7 off end # PCIe port #8
device pci 1d.0 on # EHCI controller #1
subsystemid 0x1849 0x8c26
end
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x8c5c
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel
io 0x60 = 0x0378
irq 0x70 = 7
drq 0x74 = 4 # No DMA
irq 0xf0 = 0x3c # Printer mode
end
device pnp 2e.2 on # UART A
io 0x60 = 0x03f8
irq 0x70 = 4
end
device pnp 2e.3 on # IR
io 0x60 = 0x02f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 KBC
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GPIO8
device pnp 2e.107 off end # GPIO9
device pnp 2e.8 off end # WDT
device pnp 2e.108 off end # GPIO0
device pnp 2e.208 off end # GPIOA
device pnp 2e.308 off end # GPIO base
device pnp 2e.109 off end # GPIO1
device pnp 2e.209 off end # GPIO2
device pnp 2e.309 off end # GPIO3
device pnp 2e.409 off end # GPIO4
device pnp 2e.509 off end # GPIO5
device pnp 2e.609 off end # GPIO6
device pnp 2e.709 off end # GPIO7
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HWM, LED
io 0x60 = 0x0290
io 0x62 = 0
irq 0x70 = 0
end
device pnp 2e.d off end # VID
device pnp 2e.e off end # CIR wake-up
device pnp 2e.f off end # GPIO PP/OD
device pnp 2e.14 off end # SVID
device pnp 2e.16 off end # Deep sleep
device pnp 2e.17 off end # GPIOA
end
end
device pci 1f.2 on # SATA controller 1
subsystemid 0x1849 0x8c02
end
device pci 1f.3 on # SMBus
subsystemid 0x1849 0x8c22
end
device pci 1f.5 off end # SATA controller 2
device pci 1f.6 off end # Thermal
end
end
end

41
src/mainboard/asrock/h81m-hds/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, /* DSDT Revision: ACPI v3.0 */
"COREv4", /* OEM ID */
"COREBOOT", /* OEM Table ID */
0x20181031 /* OEM Revision */
)
{
#include "acpi/platform.asl"
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
#include <cpu/intel/haswell/acpi/cpu.asl>
Scope (\_SB)
{
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
}

31
src/mainboard/asrock/h81m-hds/gma-mainboard.ads Normal file
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--
-- This file is part of the coreboot project.
--
-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI1,
HDMI3,
Analog,
others => Disabled);
end GMA.Mainboard;

168
src/mainboard/asrock/h81m-hds/gpio.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ASROCK_H81M_HDS_GPIO_H
#define ASROCK_H81M_HDS_GPIO_H
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio12 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio8 = GPIO_RESET_RSMRST,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio13 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio42 = GPIO_MODE_GPIO,
.gpio43 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio42 = GPIO_DIR_OUTPUT,
.gpio43 = GPIO_DIR_OUTPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio57 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio35 = GPIO_LEVEL_LOW,
.gpio42 = GPIO_LEVEL_LOW,
.gpio43 = GPIO_LEVEL_LOW,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};
#endif /* ASROCK_H81M_HDS_GPIO_H */

39
src/mainboard/asrock/h81m-hds/hda_verb.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0662, /* Realtek ALC662 rev1 */
0x18497662, /* Subsystem ID */
11, /* Number of entries */
AZALIA_SUBVENDOR(1, 0x18497662),
AZALIA_PIN_CFG(1, 0x14, 0x01014010),
AZALIA_PIN_CFG(1, 0x15, 0x40000000),
AZALIA_PIN_CFG(1, 0x16, 0x411111f0),
AZALIA_PIN_CFG(1, 0x18, 0x01a19040),
AZALIA_PIN_CFG(1, 0x19, 0x02a19050),
AZALIA_PIN_CFG(1, 0x1a, 0x0181304f),
AZALIA_PIN_CFG(1, 0x1b, 0x02214020),
AZALIA_PIN_CFG(1, 0x1c, 0x411111f0),
AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601),
AZALIA_PIN_CFG(1, 0x1e, 0x411111f0),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

29
src/mainboard/asrock/h81m-hds/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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src/mainboard/asrock/h81m-hds/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include "gpio.h"
static const struct rcba_config_instruction rcba_config[] = {
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),
RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
RCBA_END_CONFIG,
};
void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
/*
* Don't know what's needed here, just set the same as the vendor
* firmware.
*/
pnp_set_logical_device(IR_DEV);
pnp_write_config(IR_DEV, 0xf1, 0x5c);
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}
void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.system_type = 1, /* desktop/server */
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
.dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
.dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */
.max_ddr3_freq = 1600,
.usb2_ports = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
},
.usb3_ports = {
/* Enable, OCn# */
{ 1, 0 },
{ 1, 0 },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
},
};
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
.bist = bist,
};
romstage_common(&romstage_params);
}