armv7: add wrappers to read/write L2ACTLR
This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val)
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isb();
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isb();
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}
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}
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/* read L2 Auxiliary Control Register (L2ACTLR) */
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static inline uint32_t read_l2actlr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
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return val;
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}
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/* write L2 Auxiliary Control Register (L2ACTLR) */
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static inline void write_l2actlr(uint32_t val)
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{
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asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
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isb();
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}
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/* read system control register (SCTLR) */
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/* read system control register (SCTLR) */
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static inline uint32_t read_sctlr(void)
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static inline uint32_t read_sctlr(void)
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{
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{
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@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val)
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isb();
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isb();
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}
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}
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/* read L2 Auxiliary Control Register (L2ACTLR) */
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static inline uint32_t read_l2actlr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
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return val;
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}
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/* write L2 Auxiliary Control Register (L2ACTLR) */
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static inline void write_l2actlr(uint32_t val)
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{
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asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
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isb();
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}
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/* read system control register (SCTLR) */
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/* read system control register (SCTLR) */
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static inline uint32_t read_sctlr(void)
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static inline uint32_t read_sctlr(void)
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{
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{
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