armv7: add wrappers to read/write L2ACTLR
This adds inline wrappers to read the L2 cache auxiliary control register (L2ACTLR). Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f Reviewed-on: https://gerrit.chromium.org/gerrit/64861 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4437 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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			| @@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val) | |||||||
| 	isb(); | 	isb(); | ||||||
| } | } | ||||||
|  |  | ||||||
|  | /* read L2 Auxiliary Control Register (L2ACTLR) */ | ||||||
|  | static inline uint32_t read_l2actlr(void) | ||||||
|  | { | ||||||
|  | 	uint32_t val = 0; | ||||||
|  | 	asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); | ||||||
|  | 	return val; | ||||||
|  | } | ||||||
|  |  | ||||||
|  | /* write L2 Auxiliary Control Register (L2ACTLR) */ | ||||||
|  | static inline void write_l2actlr(uint32_t val) | ||||||
|  | { | ||||||
|  | 	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); | ||||||
|  | 	isb(); | ||||||
|  | } | ||||||
|  |  | ||||||
| /* read system control register (SCTLR) */ | /* read system control register (SCTLR) */ | ||||||
| static inline uint32_t read_sctlr(void) | static inline uint32_t read_sctlr(void) | ||||||
| { | { | ||||||
|   | |||||||
| @@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val) | |||||||
| 	isb(); | 	isb(); | ||||||
| } | } | ||||||
|  |  | ||||||
|  | /* read L2 Auxiliary Control Register (L2ACTLR) */ | ||||||
|  | static inline uint32_t read_l2actlr(void) | ||||||
|  | { | ||||||
|  | 	uint32_t val = 0; | ||||||
|  | 	asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); | ||||||
|  | 	return val; | ||||||
|  | } | ||||||
|  |  | ||||||
|  | /* write L2 Auxiliary Control Register (L2ACTLR) */ | ||||||
|  | static inline void write_l2actlr(uint32_t val) | ||||||
|  | { | ||||||
|  | 	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); | ||||||
|  | 	isb(); | ||||||
|  | } | ||||||
|  |  | ||||||
| /* read system control register (SCTLR) */ | /* read system control register (SCTLR) */ | ||||||
| static inline uint32_t read_sctlr(void) | static inline uint32_t read_sctlr(void) | ||||||
| { | { | ||||||
|   | |||||||
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