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soc/intel/.../Kconfig: Move GPIO debug option into debug menu

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Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the
Debugging menu.

Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Nico Huber
2018-11-13 22:06:40 +01:00
parent b2b3ab7c43
commit 371a6674ac
4 changed files with 11 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/Kconfig
View File

@@ -693,6 +693,13 @@ config FATAL_ASSERTS
help help
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT(). If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
config HAVE_DEBUG_GPIO
bool
config DEBUG_GPIO
bool "Output verbose GPIO debug messages"
depends on HAVE_DEBUG_GPIO
config DEBUG_CBFS config DEBUG_CBFS
bool "Output verbose CBFS debug messages" bool "Output verbose CBFS debug messages"
default n default n

8
src/soc/intel/common/block/gpio/Kconfig
View File

@@ -1,15 +1,9 @@
config SOC_INTEL_COMMON_BLOCK_GPIO config SOC_INTEL_COMMON_BLOCK_GPIO
bool bool
select HAVE_DEBUG_GPIO
help help
Intel Processor common GPIO support Intel Processor common GPIO support
config DEBUG_SOC_COMMON_BLOCK_GPIO
depends on SOC_INTEL_COMMON_BLOCK_GPIO
bool "Output verbose GPIO debug messages"
default n
help
This option enables GPIO debug messages
# Use to program Interrupt Polarity Control (IPCx) register # Use to program Interrupt Polarity Control (IPCx) register
# Each bit represents IRQx Active High Polarity Disable configuration: # Each bit represents IRQx Active High Polarity Disable configuration:
# when set to 1, the interrupt polarity associated with IRQx is inverted # when set to 1, the interrupt polarity associated with IRQx is inverted

4
src/soc/intel/common/block/gpio/gpio.c
View File

@@ -265,7 +265,7 @@ static void gpio_configure_pad(const struct pad_config *cfg)
soc_pad_conf &= mask[i]; soc_pad_conf &= mask[i];
soc_pad_conf |= pad_conf & ~mask[i]; soc_pad_conf |= pad_conf & ~mask[i];
if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) if (IS_ENABLED(CONFIG_DEBUG_GPIO))
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
" : 0x%08x]\n", " : 0x%08x]\n",
@@ -533,7 +533,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
MISCCFG_GPE0_DW1_MASK | MISCCFG_GPE0_DW1_MASK |
MISCCFG_GPE0_DW0_MASK); MISCCFG_GPE0_DW0_MASK);
if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) if (IS_ENABLED(CONFIG_DEBUG_GPIO))
printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n",
misccfg_mask, misccfg_value); misccfg_mask, misccfg_value);
comm = soc_gpio_get_community(&gpio_communities); comm = soc_gpio_get_community(&gpio_communities);

2
src/soc/intel/denverton_ns/Kconfig
View File

@@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
select BOOTBLOCK_CONSOLE select BOOTBLOCK_CONSOLE
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select DEBUG_GPIO
select POSTCAR_CONSOLE select POSTCAR_CONSOLE
select SOC_INTEL_COMMON select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
@@ -50,7 +51,6 @@ config CPU_SPECIFIC_OPTIONS
# select SOC_INTEL_COMMON_BLOCK_SA # select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO
select DEBUG_SOC_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PCR
select TSC_CONSTANT_RATE select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER