soc/intel/common/block/cse: prevent HECI commands when flash descriptor override is set
Sending the disable and EOP commands will not work if flash descriptor override is set on meteorlake. Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
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@ -11,6 +11,7 @@
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/me.h>
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#include <intelblocks/me.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/post_codes.h>
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#include <intelblocks/post_codes.h>
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@ -1268,6 +1269,10 @@ static void me_reset_with_count(void)
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static void cse_set_state(struct device *dev)
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static void cse_set_state(struct device *dev)
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{
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{
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if (fast_spi_flash_descriptor_override()) {
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printk(BIOS_WARNING, "ME: not setting state because flash descriptor override is enabled\n");
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return;
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}
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/* (CS)ME Disable Command */
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/* (CS)ME Disable Command */
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struct me_disable_command {
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struct me_disable_command {
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@ -4,6 +4,7 @@
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#include <bootstate.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pmc_ipc.h>
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#include <intelblocks/pmc_ipc.h>
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#include <security/vboot/vboot_common.h>
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#include <security/vboot/vboot_common.h>
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#include <soc/intel/common/reset.h>
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#include <soc/intel/common/reset.h>
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@ -243,6 +244,11 @@ static void do_send_end_of_post(bool wait_for_completion)
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return;
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return;
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}
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}
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if (fast_spi_flash_descriptor_override()) {
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printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n");
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return;
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}
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if (!eop_sent) {
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if (!eop_sent) {
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set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
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set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);
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timestamp_add_now(TS_ME_END_OF_POST_START);
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timestamp_add_now(TS_ME_END_OF_POST_START);
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@ -483,6 +483,15 @@ void fast_spi_clear_outstanding_status(void)
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write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
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write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
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}
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}
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/* Check if flash descriptor override is asserted */
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bool fast_spi_flash_descriptor_override(void)
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{
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void *spibar = fast_spi_get_bar();
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uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL);
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printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts);
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return !(hsfsts & SPIBAR_HSFSTS_FDOPSS);
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}
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/* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
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/* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
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static const char *fast_spi_acpi_hid(const struct device *dev)
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static const char *fast_spi_acpi_hid(const struct device *dev)
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@ -111,5 +111,7 @@ void fast_spi_set_bde(void);
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* Set FAST_SPIBAR Vendor Component Lock bit.
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* Set FAST_SPIBAR Vendor Component Lock bit.
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*/
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*/
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void fast_spi_set_vcl(void);
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void fast_spi_set_vcl(void);
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/* Check if flash descriptor override is asserted */
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bool fast_spi_flash_descriptor_override(void);
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#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
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#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
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