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soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

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The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from brya board variant's devicetree. Please refer
Intel doc#723158 for more information.

BUG=b:221461379
TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sridhar Siricilla
2022-04-02 10:33:00 +05:30
committed by Felix Held
parent 4bc2ca522d
commit 37c33052e5
2 changed files with 9 additions and 0 deletions
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src/soc/intel/alderlake/fsp_params.c
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@@ -500,6 +500,8 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
if (config->tcss_ports[i].enable)
s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
}
s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
}
static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,