diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig index bacc5084a5..3c56ea18d3 100644 --- a/src/mainboard/system76/whl-u/Kconfig +++ b/src/mainboard/system76/whl-u/Kconfig @@ -12,9 +12,12 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE # select MAINBOARD_HAS_SPI_TPM_CR50 # select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO + select PCIE_DEBUG_INFO + select PCIEXP_HOTPLUG select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB @@ -43,11 +46,11 @@ config CBFS_SIZE hex default 0xA00000 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +config SUBSYSTEM_VENDOR_ID hex default 0x1558 -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +config SUBSYSTEM_DEVICE_ID hex default 0x1323 if BOARD_SYSTEM76_GALP3_C default 0x1325 if BOARD_SYSTEM76_DARP5 @@ -60,10 +63,9 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -# This causes UEFI to hang -#config UART_FOR_CONSOLE -# int -# default 2 +config UART_FOR_CONSOLE + int + default 2 config MAX_CPUS int diff --git a/src/mainboard/system76/whl-u/acpi/mainboard.asl b/src/mainboard/system76/whl-u/acpi/mainboard.asl index 39f0462f41..1a3e8ae8d6 100644 --- a/src/mainboard/system76/whl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/whl-u/acpi/mainboard.asl @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 +#if defined(CONFIG_BOARD_SYSTEM76_DARP5) #define COLOR_KEYBOARD 1 -#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 +#elif defined(CONFIG_BOARD_SYSTEM76_GALP3_C) #define COLOR_KEYBOARD 0 #else #error Unknown Mainboard diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 04b88ff21f..be3eea3784 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -127,8 +127,9 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[5]" = "5" # Misc - register "Device4Enable" = "1" - register "HeciEnabled" = "1" + register "Device4Enable" = "0" + register "HeciEnabled" = "0" + register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" @@ -198,7 +199,7 @@ chip soc/intel/cannonlake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -207,7 +208,7 @@ chip soc/intel/cannonlake device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 + device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 diff --git a/src/mainboard/system76/whl-u/gpio.h b/src/mainboard/system76/whl-u/gpio.h index 7c46639827..5431a7d73c 100644 --- a/src/mainboard/system76/whl-u/gpio.h +++ b/src/mainboard/system76/whl-u/gpio.h @@ -232,7 +232,7 @@ static const struct pad_config gpio_table[] = { // TBCIO_PLUG_EVENT _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBT_FRC_PWR - PAD_CFG_TERM_GPO(GPP_C10, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // NC PAD_CFG_NC(GPP_C11), @@ -537,7 +537,7 @@ static const struct pad_config gpio_table[] = { // GPPC_H21 PAD_CFG_NC(GPP_H21), // TBT_RTD3_PWR_EN_R - PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST), + PAD_NC(GPP_H22, NONE), // NC, WIGIG_PEWAKE PAD_CFG_NC(GPP_H23), }; diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c index 4aebe3b426..133627d150 100644 --- a/src/mainboard/system76/whl-u/ramstage.c +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#include +#include +#include #include #include #include @@ -75,8 +78,128 @@ static void mainboard_init(struct device *dev) { } } +static bool mainboard_pcie_hotplug(int port_number) { + printk(BIOS_DEBUG, "system76: pcie_hotplug(%d)\n", port_number); + /* RP01 */ + return port_number == 0; +} + +static void pcie_hotplug_generator(int port_number) +{ + int port; + int have_hotplug = 0; + + for (port = 0; port < port_number; port++) { + if (mainboard_pcie_hotplug(port)) { + have_hotplug = 1; + } + } + + if (!have_hotplug) { + return; + } + + for (port = 0; port < port_number; port++) { + if (mainboard_pcie_hotplug(port)) { + char scope_name[] = "\\_SB.PCI0.RP0x"; + scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; + acpigen_write_scope(scope_name); + + /* + Device (SLOT) + { + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } + } + */ + + acpigen_write_device("SLOT"); + + acpigen_write_name_byte("_ADR", 0x00); + + acpigen_write_method("_RMV", 0); + /* ReturnOp */ + acpigen_emit_byte (0xa4); + /* One */ + acpigen_emit_byte (0x01); + acpigen_pop_len(); + acpigen_pop_len(); + acpigen_pop_len(); + } + } + + /* Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP04.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP04.HPCS) + If (\_SB.PCI0.RP04.PDC) + { + Store (0x01, \_SB.PCI0.RP04.PDC) + Notify (\_SB.PCI0.RP04, 0x00) + } + } + } + + */ + acpigen_write_scope("\\_GPE"); + acpigen_write_method("_L01", 0); + for (port = 0; port < port_number; port++) { + if (mainboard_pcie_hotplug(port)) { + char reg_name[] = "\\_SB.PCI0.RP0x.HPCS"; + reg_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port; + acpigen_emit_byte(0xa0); /* IfOp. */ + acpigen_write_len_f(); + acpigen_emit_namestring(reg_name); + + /* Sleep (100) */ + acpigen_emit_byte(0x5b); /* SleepOp. */ + acpigen_emit_byte(0x22); + acpigen_write_byte(100); + + /* Store (0x01, \_SB.PCI0.RP04.HPCS) */ + acpigen_emit_byte(0x70); + acpigen_emit_byte(0x01); + acpigen_emit_namestring(reg_name); + + memcpy(reg_name + sizeof("\\_SB.PCI0.RP0x.") - 1, "PDC", 4); + + /* If (\_SB.PCI0.RP04.PDC) */ + acpigen_emit_byte(0xa0); /* IfOp. */ + acpigen_write_len_f(); + acpigen_emit_namestring(reg_name); + + /* Store (0x01, \_SB.PCI0.RP04.PDC) */ + acpigen_emit_byte(0x70); + acpigen_emit_byte(0x01); + acpigen_emit_namestring(reg_name); + + reg_name[sizeof("\\_SB.PCI0.RP0x") - 1] = '\0'; + + /* Notify(\_SB.PCI0.RP04, 0x00) */ + acpigen_emit_byte(0x86); + acpigen_emit_namestring(reg_name); + acpigen_emit_byte(0x00); + acpigen_pop_len(); + acpigen_pop_len(); + } + } + acpigen_pop_len(); + acpigen_pop_len(); +} + +static void fill_ssdt(struct device *device) { + printk(BIOS_INFO, "system76: fill_ssdt\n"); + pcie_hotplug_generator(CONFIG_MAX_ROOT_PORTS); +} + static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_fill_ssdt_generator = fill_ssdt; // Configure pad for DisplayPort uint32_t config = 0x44000200;