kbl-u: Sync some changes from whl-u
This commit is contained in:
Jeremy Soller
parent
5c6c34c32b
commit
37dc6de31d
@ -2,27 +2,26 @@ if BOARD_SYSTEM76_GALP2 || BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ADD_FSP_BINARIES
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select BOARD_ROMSIZE_KB_8192
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select EC_ACPI
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select EXCLUDE_EMMC_INTERFACE
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select FSP_USE_REPO
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_USES_FSP2_0
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_KABYLAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select USE_BLOBS
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select USE_OPTION_TABLE
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select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
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@ -1,35 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 System76
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* SPDX-License-Identifier: GPL-2.0-only */
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Device (AC)
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{
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Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (ACFG, One)
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Name (ACFG, One)
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Method (_PSR, 0, NotSerialized) // _PSR: Power Source
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{
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Return (ACFG)
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}
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Method (_PSR, 0, NotSerialized) // _PSR: Power Source
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{
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Return (ACFG)
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}
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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Return (0x0F)
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}
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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Return (0x0F)
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}
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}
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@ -1,183 +1,170 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 System76
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* SPDX-License-Identifier: GPL-2.0-only */
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Device (BAT0)
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{
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Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (BFCC, Zero)
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Return (0x1F)
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}
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Else
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{
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Return (0x0F)
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}
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}
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Else
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{
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Return (0x0F)
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}
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}
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Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_PCL, Package (0x01) // _PCL: Power Consumer List
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{
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_SB
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})
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Name (BFCC, Zero)
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Return (0x1F)
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}
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Else
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{
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Return (0x0F)
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}
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}
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Else
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{
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Return (0x0F)
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}
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}
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Name (PBIF, Package (0x0D)
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{
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One,
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0xFFFFFFFF,
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0xFFFFFFFF,
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One,
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0x39D0,
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Zero,
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Zero,
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0x40,
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0x40,
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"BAT",
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"0001",
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"LION",
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"Notebook"
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})
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Method (IVBI, 0, NotSerialized)
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{
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PBIF [One] = 0xFFFFFFFF
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PBIF [0x02] = 0xFFFFFFFF
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PBIF [0x04] = 0xFFFFFFFF
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PBIF [0x09] = " "
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PBIF [0x0A] = " "
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PBIF [0x0B] = " "
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PBIF [0x0C] = " "
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BFCC = Zero
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}
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Name (PBIF, Package (0x0D)
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{
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One,
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0xFFFFFFFF,
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0xFFFFFFFF,
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One,
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0x39D0,
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Zero,
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Zero,
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0x40,
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0x40,
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"BAT",
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"0001",
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"LION",
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"Notebook"
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})
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Method (IVBI, 0, NotSerialized)
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{
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PBIF [One] = 0xFFFFFFFF
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PBIF [0x02] = 0xFFFFFFFF
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PBIF [0x04] = 0xFFFFFFFF
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PBIF [0x09] = " "
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PBIF [0x0A] = " "
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PBIF [0x0B] = " "
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PBIF [0x0C] = " "
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BFCC = Zero
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}
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Method (UPBI, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
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PBIF [One] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
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PBIF [0x02] = Local0
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BFCC = Local0
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Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
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PBIF [0x04] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
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PBIF [0x05] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
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PBIF [0x06] = Local0
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PBIF [0x09] = "BAT"
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PBIF [0x0A] = "0001"
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PBIF [0x0B] = "LION"
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PBIF [0x0C] = "Notebook"
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}
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Else
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{
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IVBI ()
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}
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}
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Method (UPBI, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
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PBIF [One] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
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PBIF [0x02] = Local0
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BFCC = Local0
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Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
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PBIF [0x04] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
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PBIF [0x05] = Local0
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Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
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PBIF [0x06] = Local0
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PBIF [0x09] = "BAT"
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PBIF [0x0A] = "0001"
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PBIF [0x0B] = "LION"
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PBIF [0x0C] = "Notebook"
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}
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Else
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{
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IVBI ()
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}
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}
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Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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UPBI ()
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}
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Else
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{
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IVBI ()
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}
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Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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UPBI ()
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}
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Else
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{
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IVBI ()
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}
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Return (PBIF) /* \_SB_.BAT0.PBIF */
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}
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Return (PBIF) /* \_SB_.BAT0.PBIF */
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}
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Name (PBST, Package (0x04)
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{
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Zero,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0x3D90
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})
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Method (IVBS, 0, NotSerialized)
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{
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PBST [Zero] = Zero
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PBST [One] = 0xFFFFFFFF
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PBST [0x02] = 0xFFFFFFFF
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PBST [0x03] = 0x2710
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}
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Name (PBST, Package (0x04)
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{
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Zero,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0x3D90
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})
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Method (IVBS, 0, NotSerialized)
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{
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PBST [Zero] = Zero
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PBST [One] = 0xFFFFFFFF
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PBST [0x02] = 0xFFFFFFFF
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PBST [0x03] = 0x2710
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}
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Method (UPBS, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Local0 = Zero
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Local1 = Zero
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If (^^AC.ACFG)
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{
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If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
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{
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Local0 |= 0x02
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Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
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}
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}
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Else
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{
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Local0 |= One
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Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
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}
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Method (UPBS, 0, NotSerialized)
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{
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If (^^PCI0.LPCB.EC0.BAT0)
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{
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Local0 = Zero
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Local1 = Zero
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If (^^AC.ACFG)
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{
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If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
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{
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Local0 |= 0x02
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Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
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}
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}
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Else
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{
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Local0 |= One
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Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
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}
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Local7 = (Local1 & 0x8000)
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If ((Local7 == 0x8000))
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{
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Local1 ^= 0xFFFF
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}
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Local7 = (Local1 & 0x8000)
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If ((Local7 == 0x8000))
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{
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Local1 ^= 0xFFFF
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}
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Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
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Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
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PBST [Zero] = Local0
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PBST [One] = Local1
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PBST [0x02] = Local2
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PBST [0x03] = Local3
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If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
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{
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Notify (BAT0, 0x81) // Information Change
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}
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}
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Else
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{
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IVBS ()
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}
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}
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Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
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Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
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PBST [Zero] = Local0
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PBST [One] = Local1
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PBST [0x02] = Local2
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PBST [0x03] = Local3
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If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
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{
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Notify (BAT0, 0x81) // Information Change
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}
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}
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Else
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{
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IVBS ()
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}
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}
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Method (_BST, 0, NotSerialized) // _BST: Battery Status
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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UPBS ()
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}
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Else
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{
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IVBS ()
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}
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Method (_BST, 0, NotSerialized) // _BST: Battery Status
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{
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If (^^PCI0.LPCB.EC0.ECOK)
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{
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UPBS ()
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}
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Else
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{
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IVBS ()
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}
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Return (PBST) /* \_SB_.BAT0.PBST */
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}
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Return (PBST) /* \_SB_.BAT0.PBST */
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}
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}
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@ -1,26 +1,13 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
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Device (PWRB)
|
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{
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Name (_HID, EisaId ("PNP0C0C"))
|
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Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
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Name (_HID, EisaId ("PNP0C0C"))
|
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Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
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}
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Device (SLPB)
|
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{
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Name (_HID, EisaId ("PNP0C0E"))
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Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
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Name (_HID, EisaId ("PNP0C0E"))
|
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Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
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}
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@ -1,231 +1,222 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (EC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
|
||||
Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events
|
||||
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0062, // Range Minimum
|
||||
0x0062, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0066, // Range Minimum
|
||||
0x0066, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
})
|
||||
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
|
||||
Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events
|
||||
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0062, // Range Minimum
|
||||
0x0062, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0066, // Range Minimum
|
||||
0x0066, // Range Maximum
|
||||
0x00, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
})
|
||||
|
||||
#include "acpi/ec_ram.asl"
|
||||
#include "acpi/ec_ram.asl"
|
||||
|
||||
Name (ECOK, Zero)
|
||||
Method (_REG, 2, Serialized) // _REG: Region Availability
|
||||
{
|
||||
Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
|
||||
If (((Arg0 == 0x03) && (Arg1 == One))) {
|
||||
// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
|
||||
ECOS = 1
|
||||
Name (ECOK, Zero)
|
||||
Method (_REG, 2, Serialized) // _REG: Region Availability
|
||||
{
|
||||
Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1))))
|
||||
If (((Arg0 == 0x03) && (Arg1 == One))) {
|
||||
// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
|
||||
ECOS = 1
|
||||
|
||||
// Enable software display brightness keys
|
||||
WINF = 1
|
||||
// Enable software display brightness keys
|
||||
WINF = 1
|
||||
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
PNOT ()
|
||||
PNOT ()
|
||||
|
||||
// EC is now available
|
||||
ECOK = Arg1
|
||||
// EC is now available
|
||||
ECOK = Arg1
|
||||
|
||||
// Reset System76 Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
// Reset System76 Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
|
||||
Method (PTS, 1, Serialized) {
|
||||
Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Clear wake cause
|
||||
WFNO = Zero
|
||||
}
|
||||
}
|
||||
Method (PTS, 1, Serialized) {
|
||||
Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Clear wake cause
|
||||
WFNO = Zero
|
||||
}
|
||||
}
|
||||
|
||||
Method (WAK, 1, Serialized) {
|
||||
Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
Method (WAK, 1, Serialized) {
|
||||
Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
|
||||
If (ECOK) {
|
||||
// Set current AC state
|
||||
^^^^AC.ACFG = ADP
|
||||
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
// Update battery information and status
|
||||
^^^^BAT0.UPBI()
|
||||
^^^^BAT0.UPBS()
|
||||
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, Zero)
|
||||
Notify(^^^^BAT0, Zero)
|
||||
// Notify of changes
|
||||
Notify(^^^^AC, Zero)
|
||||
Notify(^^^^BAT0, Zero)
|
||||
|
||||
Sleep (1000)
|
||||
Sleep (1000)
|
||||
|
||||
// Reset System76 Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
// Reset System76 Device
|
||||
^^^^S76D.RSET()
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
|
||||
{
|
||||
Debug = "EC: Touchpad Toggle"
|
||||
}
|
||||
Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
|
||||
{
|
||||
Debug = "EC: Touchpad Toggle"
|
||||
}
|
||||
|
||||
Method (_Q0B, 0, NotSerialized) // Screen Toggle
|
||||
{
|
||||
Debug = "EC: Screen Toggle"
|
||||
}
|
||||
Method (_Q0B, 0, NotSerialized) // Screen Toggle
|
||||
{
|
||||
Debug = "EC: Screen Toggle"
|
||||
}
|
||||
|
||||
Method (_Q0C, 0, NotSerialized) // Mute
|
||||
{
|
||||
Debug = "EC: Mute"
|
||||
}
|
||||
Method (_Q0C, 0, NotSerialized) // Mute
|
||||
{
|
||||
Debug = "EC: Mute"
|
||||
}
|
||||
|
||||
Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
|
||||
{
|
||||
Debug = "EC: Keyboard Backlight"
|
||||
}
|
||||
Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
|
||||
{
|
||||
Debug = "EC: Keyboard Backlight"
|
||||
}
|
||||
|
||||
Method (_Q0E, 0, NotSerialized) // Volume Down
|
||||
{
|
||||
Debug = "EC: Volume Down"
|
||||
}
|
||||
Method (_Q0E, 0, NotSerialized) // Volume Down
|
||||
{
|
||||
Debug = "EC: Volume Down"
|
||||
}
|
||||
|
||||
Method (_Q0F, 0, NotSerialized) // Volume Up
|
||||
{
|
||||
Debug = "EC: Volume Up"
|
||||
}
|
||||
Method (_Q0F, 0, NotSerialized) // Volume Up
|
||||
{
|
||||
Debug = "EC: Volume Up"
|
||||
}
|
||||
|
||||
Method (_Q10, 0, NotSerialized) // Switch Video Mode
|
||||
{
|
||||
Debug = "EC: Switch Video Mode"
|
||||
}
|
||||
Method (_Q10, 0, NotSerialized) // Switch Video Mode
|
||||
{
|
||||
Debug = "EC: Switch Video Mode"
|
||||
}
|
||||
|
||||
Method (_Q11, 0, NotSerialized) // Brightness Down
|
||||
{
|
||||
Debug = "EC: Brightness Down"
|
||||
^^^^HIDD.HPEM (20)
|
||||
}
|
||||
Method (_Q11, 0, NotSerialized) // Brightness Down
|
||||
{
|
||||
Debug = "EC: Brightness Down"
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (20)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q12, 0, NotSerialized) // Brightness Up
|
||||
{
|
||||
Debug = "EC: Brightness Up"
|
||||
^^^^HIDD.HPEM (19)
|
||||
}
|
||||
Method (_Q12, 0, NotSerialized) // Brightness Up
|
||||
{
|
||||
Debug = "EC: Brightness Up"
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (19)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q13, 0, NotSerialized) // Camera Toggle
|
||||
{
|
||||
Debug = "EC: Camera Toggle"
|
||||
}
|
||||
Method (_Q13, 0, NotSerialized) // Camera Toggle
|
||||
{
|
||||
Debug = "EC: Camera Toggle"
|
||||
}
|
||||
|
||||
Method (_Q14, 0, NotSerialized) // Airplane Mode
|
||||
{
|
||||
Debug = "EC: Airplane Mode"
|
||||
// Only send HIDD message when hardware airplane mode not in use
|
||||
If (ECOS == 2) {
|
||||
^^^^HIDD.HPEM (8)
|
||||
}
|
||||
}
|
||||
Method (_Q14, 0, NotSerialized) // Airplane Mode
|
||||
{
|
||||
Debug = "EC: Airplane Mode"
|
||||
if (^^^^HIDD.HRDY) {
|
||||
^^^^HIDD.HPEM (8)
|
||||
}
|
||||
// TODO: hardware airplane mode
|
||||
}
|
||||
|
||||
Method (_Q15, 0, NotSerialized) // Suspend Button
|
||||
{
|
||||
Debug = "EC: Suspend Button"
|
||||
Notify (SLPB, 0x80)
|
||||
}
|
||||
Method (_Q15, 0, NotSerialized) // Suspend Button
|
||||
{
|
||||
Debug = "EC: Suspend Button"
|
||||
Notify (SLPB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q16, 0, NotSerialized) // AC Detect
|
||||
{
|
||||
Debug = "EC: AC Detect"
|
||||
^^^^AC.ACFG = ADP
|
||||
Notify (AC, 0x80) // Status Change
|
||||
Sleep (0x01F4)
|
||||
If (BAT0)
|
||||
{
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
Sleep (0x32)
|
||||
Notify (^^^^BAT0, 0x80) // Status Change
|
||||
Sleep (0x32)
|
||||
}
|
||||
}
|
||||
Method (_Q16, 0, NotSerialized) // AC Detect
|
||||
{
|
||||
Debug = "EC: AC Detect"
|
||||
^^^^AC.ACFG = ADP
|
||||
Notify (AC, 0x80) // Status Change
|
||||
Sleep (0x01F4)
|
||||
If (BAT0)
|
||||
{
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
Sleep (0x32)
|
||||
Notify (^^^^BAT0, 0x80) // Status Change
|
||||
Sleep (0x32)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_Q17, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Debug = "EC: BAT0 Update (17)"
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
Method (_Q17, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Debug = "EC: BAT0 Update (17)"
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q19, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Debug = "EC: BAT0 Update (19)"
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
Method (_Q19, 0, NotSerialized) // BAT0 Update
|
||||
{
|
||||
Debug = "EC: BAT0 Update (19)"
|
||||
Notify (^^^^BAT0, 0x81) // Information Change
|
||||
}
|
||||
|
||||
Method (_Q1B, 0, NotSerialized) // Lid Close
|
||||
{
|
||||
Debug = "EC: Lid Close"
|
||||
Notify (LID0, 0x80)
|
||||
}
|
||||
Method (_Q1B, 0, NotSerialized) // Lid Close
|
||||
{
|
||||
Debug = "EC: Lid Close"
|
||||
Notify (LID0, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q1C, 0, NotSerialized) // Thermal Trip
|
||||
{
|
||||
Debug = "EC: Thermal Trip"
|
||||
/* TODO
|
||||
Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
|
||||
Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
|
||||
*/
|
||||
}
|
||||
Method (_Q1C, 0, NotSerialized) // Thermal Trip
|
||||
{
|
||||
Debug = "EC: Thermal Trip"
|
||||
/* TODO
|
||||
Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
|
||||
Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
|
||||
*/
|
||||
}
|
||||
|
||||
Method (_Q1D, 0, NotSerialized) // Power Button
|
||||
{
|
||||
Debug = "EC: Power Button"
|
||||
Notify (PWRB, 0x80)
|
||||
}
|
||||
Method (_Q1D, 0, NotSerialized) // Power Button
|
||||
{
|
||||
Debug = "EC: Power Button"
|
||||
Notify (PWRB, 0x80)
|
||||
}
|
||||
|
||||
Method (_Q50, 0, NotSerialized) // Other Events
|
||||
{
|
||||
Local0 = OEM4
|
||||
If (Local0 == 0x8A) {
|
||||
Debug = "EC: White Keyboard Backlight"
|
||||
Notify (^^^^S76D, 0x80)
|
||||
} ElseIf (Local0 == 0x9F) {
|
||||
Debug = "EC: Color Keyboard Toggle"
|
||||
Notify (^^^^S76D, 0x81)
|
||||
} ElseIf (Local0 == 0x81) {
|
||||
Debug = "EC: Color Keyboard Down"
|
||||
Notify (^^^^S76D, 0x82)
|
||||
} ElseIf (Local0 == 0x82) {
|
||||
Debug = "EC: Color Keyboard Up"
|
||||
Notify (^^^^S76D, 0x83)
|
||||
} ElseIf (Local0 == 0x80) {
|
||||
Debug = "EC: Color Keyboard Color Change"
|
||||
Notify (^^^^S76D, 0x84)
|
||||
} Else {
|
||||
Debug = Concatenate("EC: Other: ", ToHexString(Local0))
|
||||
}
|
||||
}
|
||||
Method (_Q50, 0, NotSerialized) // Other Events
|
||||
{
|
||||
Local0 = OEM4
|
||||
If (Local0 == 0x8A) {
|
||||
Debug = "EC: White Keyboard Backlight"
|
||||
Notify (^^^^S76D, 0x80)
|
||||
} ElseIf (Local0 == 0x9F) {
|
||||
Debug = "EC: Color Keyboard Toggle"
|
||||
Notify (^^^^S76D, 0x81)
|
||||
} ElseIf (Local0 == 0x81) {
|
||||
Debug = "EC: Color Keyboard Down"
|
||||
Notify (^^^^S76D, 0x82)
|
||||
} ElseIf (Local0 == 0x82) {
|
||||
Debug = "EC: Color Keyboard Up"
|
||||
Notify (^^^^S76D, 0x83)
|
||||
} ElseIf (Local0 == 0x80) {
|
||||
Debug = "EC: Color Keyboard Color Change"
|
||||
Notify (^^^^S76D, 0x84)
|
||||
} Else {
|
||||
Debug = Concatenate("EC: Other: ", ToHexString(Local0))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,185 +1,172 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
|
||||
Field (ERAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
NMSG, 8,
|
||||
SLED, 4,
|
||||
Offset (0x02),
|
||||
MODE, 1,
|
||||
FAN0, 1,
|
||||
TME0, 1,
|
||||
TME1, 1,
|
||||
FAN1, 1,
|
||||
, 2,
|
||||
Offset (0x03),
|
||||
LSTE, 1,
|
||||
LSW0, 1,
|
||||
LWKE, 1,
|
||||
WAKF, 1,
|
||||
, 2,
|
||||
PWKE, 1,
|
||||
MWKE, 1,
|
||||
AC0, 8,
|
||||
PSV, 8,
|
||||
CRT, 8,
|
||||
TMP, 8,
|
||||
AC1, 8,
|
||||
BBST, 8,
|
||||
Offset (0x0B),
|
||||
Offset (0x0C),
|
||||
Offset (0x0D),
|
||||
Offset (0x0E),
|
||||
SLPT, 8,
|
||||
SWEJ, 1,
|
||||
SWCH, 1,
|
||||
Offset (0x10),
|
||||
ADP, 1,
|
||||
AFLT, 1,
|
||||
BAT0, 1,
|
||||
BAT1, 1,
|
||||
, 3,
|
||||
PWOF, 1,
|
||||
WFNO, 8,
|
||||
BPU0, 32,
|
||||
BDC0, 32,
|
||||
BFC0, 32,
|
||||
BTC0, 32,
|
||||
BDV0, 32,
|
||||
BST0, 32,
|
||||
BPR0, 32,
|
||||
BRC0, 32,
|
||||
BPV0, 32,
|
||||
BTP0, 16,
|
||||
BRS0, 16,
|
||||
BCW0, 32,
|
||||
BCL0, 32,
|
||||
BCG0, 32,
|
||||
BG20, 32,
|
||||
BMO0, 64,
|
||||
BIF0, 64,
|
||||
BSN0, 32,
|
||||
BTY0, 64,
|
||||
Offset (0x67),
|
||||
Offset (0x68),
|
||||
ECOS, 8,
|
||||
LNXD, 8,
|
||||
ECPS, 8,
|
||||
Offset (0x6C),
|
||||
BTMP, 16,
|
||||
EVTN, 8,
|
||||
Offset (0x72),
|
||||
PRCL, 8,
|
||||
PRC0, 8,
|
||||
PRC1, 8,
|
||||
PRCM, 8,
|
||||
PRIN, 8,
|
||||
PSTE, 8,
|
||||
PCAD, 8,
|
||||
PEWL, 8,
|
||||
PWRL, 8,
|
||||
PECD, 8,
|
||||
PEHI, 8,
|
||||
PECI, 8,
|
||||
PEPL, 8,
|
||||
PEPM, 8,
|
||||
PWFC, 8,
|
||||
PECC, 8,
|
||||
PDT0, 8,
|
||||
PDT1, 8,
|
||||
PDT2, 8,
|
||||
PDT3, 8,
|
||||
PRFC, 8,
|
||||
PRS0, 8,
|
||||
PRS1, 8,
|
||||
PRS2, 8,
|
||||
PRS3, 8,
|
||||
PRS4, 8,
|
||||
PRCS, 8,
|
||||
PEC0, 8,
|
||||
PEC1, 8,
|
||||
PEC2, 8,
|
||||
PEC3, 8,
|
||||
CMDR, 8,
|
||||
CVRT, 8,
|
||||
GTVR, 8,
|
||||
FANT, 8,
|
||||
SKNT, 8,
|
||||
AMBT, 8,
|
||||
MCRT, 8,
|
||||
DIM0, 8,
|
||||
DIM1, 8,
|
||||
PMAX, 8,
|
||||
PPDT, 8,
|
||||
PECH, 8,
|
||||
PMDT, 8,
|
||||
TSD0, 8,
|
||||
TSD1, 8,
|
||||
TSD2, 8,
|
||||
TSD3, 8,
|
||||
CPUP, 16,
|
||||
MCHP, 16,
|
||||
SYSP, 16,
|
||||
CPAP, 16,
|
||||
MCAP, 16,
|
||||
SYAP, 16,
|
||||
CFSP, 16,
|
||||
CPUE, 16,
|
||||
Offset (0xC6),
|
||||
Offset (0xC7),
|
||||
VGAT, 8,
|
||||
OEM1, 8,
|
||||
OEM2, 8,
|
||||
OEM3, 16,
|
||||
OEM4, 8,
|
||||
Offset (0xCE),
|
||||
DUT1, 8,
|
||||
DUT2, 8,
|
||||
RPM1, 16,
|
||||
RPM2, 16,
|
||||
RPM4, 16,
|
||||
Offset (0xD7),
|
||||
DTHL, 8,
|
||||
DTBP, 8,
|
||||
AIRP, 8,
|
||||
WINF, 8,
|
||||
RINF, 8,
|
||||
Offset (0xDD),
|
||||
INF2, 8,
|
||||
MUTE, 1,
|
||||
Offset (0xE0),
|
||||
RPM3, 16,
|
||||
ECKS, 8,
|
||||
Offset (0xE4),
|
||||
, 4,
|
||||
XTUF, 1,
|
||||
EP12, 1,
|
||||
Offset (0xE5),
|
||||
INF3, 8,
|
||||
Offset (0xE7),
|
||||
GFOF, 8,
|
||||
Offset (0xF0),
|
||||
PL1T, 16,
|
||||
PL2T, 16,
|
||||
TAUT, 8,
|
||||
Offset (0xF8),
|
||||
FCMD, 8,
|
||||
FDAT, 8,
|
||||
FBUF, 8,
|
||||
FBF1, 8,
|
||||
FBF2, 8,
|
||||
FBF3, 8
|
||||
NMSG, 8,
|
||||
SLED, 4,
|
||||
Offset (0x02),
|
||||
MODE, 1,
|
||||
FAN0, 1,
|
||||
TME0, 1,
|
||||
TME1, 1,
|
||||
FAN1, 1,
|
||||
, 2,
|
||||
Offset (0x03),
|
||||
LSTE, 1,
|
||||
LSW0, 1,
|
||||
LWKE, 1,
|
||||
WAKF, 1,
|
||||
, 2,
|
||||
PWKE, 1,
|
||||
MWKE, 1,
|
||||
AC0, 8,
|
||||
PSV, 8,
|
||||
CRT, 8,
|
||||
TMP, 8,
|
||||
AC1, 8,
|
||||
BBST, 8,
|
||||
Offset (0x0B),
|
||||
Offset (0x0C),
|
||||
Offset (0x0D),
|
||||
Offset (0x0E),
|
||||
SLPT, 8,
|
||||
SWEJ, 1,
|
||||
SWCH, 1,
|
||||
Offset (0x10),
|
||||
ADP, 1,
|
||||
AFLT, 1,
|
||||
BAT0, 1,
|
||||
BAT1, 1,
|
||||
, 3,
|
||||
PWOF, 1,
|
||||
WFNO, 8,
|
||||
BPU0, 32,
|
||||
BDC0, 32,
|
||||
BFC0, 32,
|
||||
BTC0, 32,
|
||||
BDV0, 32,
|
||||
BST0, 32,
|
||||
BPR0, 32,
|
||||
BRC0, 32,
|
||||
BPV0, 32,
|
||||
BTP0, 16,
|
||||
BRS0, 16,
|
||||
BCW0, 32,
|
||||
BCL0, 32,
|
||||
BCG0, 32,
|
||||
BG20, 32,
|
||||
BMO0, 64,
|
||||
BIF0, 64,
|
||||
BSN0, 32,
|
||||
BTY0, 64,
|
||||
Offset (0x67),
|
||||
Offset (0x68),
|
||||
ECOS, 8,
|
||||
LNXD, 8,
|
||||
ECPS, 8,
|
||||
Offset (0x6C),
|
||||
BTMP, 16,
|
||||
EVTN, 8,
|
||||
Offset (0x72),
|
||||
PRCL, 8,
|
||||
PRC0, 8,
|
||||
PRC1, 8,
|
||||
PRCM, 8,
|
||||
PRIN, 8,
|
||||
PSTE, 8,
|
||||
PCAD, 8,
|
||||
PEWL, 8,
|
||||
PWRL, 8,
|
||||
PECD, 8,
|
||||
PEHI, 8,
|
||||
PECI, 8,
|
||||
PEPL, 8,
|
||||
PEPM, 8,
|
||||
PWFC, 8,
|
||||
PECC, 8,
|
||||
PDT0, 8,
|
||||
PDT1, 8,
|
||||
PDT2, 8,
|
||||
PDT3, 8,
|
||||
PRFC, 8,
|
||||
PRS0, 8,
|
||||
PRS1, 8,
|
||||
PRS2, 8,
|
||||
PRS3, 8,
|
||||
PRS4, 8,
|
||||
PRCS, 8,
|
||||
PEC0, 8,
|
||||
PEC1, 8,
|
||||
PEC2, 8,
|
||||
PEC3, 8,
|
||||
CMDR, 8,
|
||||
CVRT, 8,
|
||||
GTVR, 8,
|
||||
FANT, 8,
|
||||
SKNT, 8,
|
||||
AMBT, 8,
|
||||
MCRT, 8,
|
||||
DIM0, 8,
|
||||
DIM1, 8,
|
||||
PMAX, 8,
|
||||
PPDT, 8,
|
||||
PECH, 8,
|
||||
PMDT, 8,
|
||||
TSD0, 8,
|
||||
TSD1, 8,
|
||||
TSD2, 8,
|
||||
TSD3, 8,
|
||||
CPUP, 16,
|
||||
MCHP, 16,
|
||||
SYSP, 16,
|
||||
CPAP, 16,
|
||||
MCAP, 16,
|
||||
SYAP, 16,
|
||||
CFSP, 16,
|
||||
CPUE, 16,
|
||||
Offset (0xC6),
|
||||
Offset (0xC7),
|
||||
VGAT, 8,
|
||||
OEM1, 8,
|
||||
OEM2, 8,
|
||||
OEM3, 16,
|
||||
OEM4, 8,
|
||||
Offset (0xCE),
|
||||
DUT1, 8,
|
||||
DUT2, 8,
|
||||
RPM1, 16,
|
||||
RPM2, 16,
|
||||
RPM4, 16,
|
||||
Offset (0xD7),
|
||||
DTHL, 8,
|
||||
DTBP, 8,
|
||||
AIRP, 8,
|
||||
WINF, 8,
|
||||
RINF, 8,
|
||||
Offset (0xDD),
|
||||
INF2, 8,
|
||||
MUTE, 1,
|
||||
Offset (0xE0),
|
||||
RPM3, 16,
|
||||
ECKS, 8,
|
||||
Offset (0xE4),
|
||||
, 4,
|
||||
XTUF, 1,
|
||||
EP12, 1,
|
||||
Offset (0xE5),
|
||||
INF3, 8,
|
||||
Offset (0xE7),
|
||||
GFOF, 8,
|
||||
Offset (0xF0),
|
||||
PL1T, 16,
|
||||
PL2T, 16,
|
||||
TAUT, 8,
|
||||
Offset (0xF8),
|
||||
FCMD, 8,
|
||||
FDAT, 8,
|
||||
FBUF, 8,
|
||||
FBF1, 8,
|
||||
FBF2, 8,
|
||||
FBF3, 8
|
||||
}
|
||||
|
||||
@ -1,24 +1,11 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// GPP_C19 SCI
|
||||
Method (_L13, 0, Serialized) {
|
||||
Debug = Concatenate("GPE _L13: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
|
||||
If (\_SB.PCI0.LPCB.EC0.ECOK) {
|
||||
If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
|
||||
Notify(\_SB.LID0, 0x80)
|
||||
}
|
||||
}
|
||||
Debug = Concatenate("GPE _L13: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
|
||||
If (\_SB.PCI0.LPCB.EC0.ECOK) {
|
||||
If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
|
||||
Notify(\_SB.LID0, 0x80)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,63 +1,50 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (HIDD)
|
||||
{
|
||||
Name (_HID, "INT33D5")
|
||||
Name (HBSY, Zero)
|
||||
Name (HIDX, Zero)
|
||||
Name (HRDY, Zero)
|
||||
Name (_HID, "INT33D5")
|
||||
Name (HBSY, Zero)
|
||||
Name (HIDX, Zero)
|
||||
Name (HRDY, Zero)
|
||||
|
||||
Method (HDEM, 0, Serialized)
|
||||
{
|
||||
HBSY = Zero
|
||||
Return (HIDX)
|
||||
}
|
||||
Method (HDEM, 0, Serialized)
|
||||
{
|
||||
HBSY = Zero
|
||||
Return (HIDX)
|
||||
}
|
||||
|
||||
Method (HDMM, 0, Serialized)
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
Method (HDMM, 0, Serialized)
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
|
||||
Method (HDSM, 1, Serialized)
|
||||
{
|
||||
HRDY = Arg0
|
||||
}
|
||||
Method (HDSM, 1, Serialized)
|
||||
{
|
||||
HRDY = Arg0
|
||||
}
|
||||
|
||||
Method (HPEM, 1, Serialized)
|
||||
{
|
||||
HBSY = One
|
||||
HIDX = Arg0
|
||||
Method (HPEM, 1, Serialized)
|
||||
{
|
||||
HBSY = One
|
||||
HIDX = Arg0
|
||||
|
||||
Notify (HIDD, 0xC0)
|
||||
Local0 = Zero
|
||||
While (((Local0 < 0xFA) && HBSY))
|
||||
{
|
||||
Sleep (0x04)
|
||||
Local0++
|
||||
}
|
||||
Notify (HIDD, 0xC0)
|
||||
Local0 = Zero
|
||||
While (((Local0 < 0xFA) && HBSY))
|
||||
{
|
||||
Sleep (0x04)
|
||||
Local0++
|
||||
}
|
||||
|
||||
If ((HBSY == One))
|
||||
{
|
||||
HBSY = Zero
|
||||
HIDX = Zero
|
||||
Return (One)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
}
|
||||
If ((HBSY == One))
|
||||
{
|
||||
HBSY = Zero
|
||||
HIDX = Zero
|
||||
Return (One)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (Zero)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,36 +1,23 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 })
|
||||
|
||||
Method (_LID, 0, NotSerialized) {
|
||||
DEBUG = "LID: _LID"
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
Return (^^PCI0.LPCB.EC0.LSTE)
|
||||
} Else {
|
||||
Return (One)
|
||||
}
|
||||
}
|
||||
Method (_LID, 0, NotSerialized) {
|
||||
DEBUG = "LID: _LID"
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
Return (^^PCI0.LPCB.EC0.LSTE)
|
||||
} Else {
|
||||
Return (One)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PSW, 1, NotSerialized) {
|
||||
DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0))
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.LWKE = Arg0
|
||||
}
|
||||
}
|
||||
Method (_PSW, 1, NotSerialized) {
|
||||
DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0))
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.LWKE = Arg0
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,30 +1,15 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define COLOR_KEYBOARD 0
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "ac.asl"
|
||||
#include "battery.asl"
|
||||
#include "buttons.asl"
|
||||
#include "hid.asl"
|
||||
#include "lid.asl"
|
||||
#include "s76.asl"
|
||||
#include "sleep.asl"
|
||||
#include "ac.asl"
|
||||
#include "battery.asl"
|
||||
#include "buttons.asl"
|
||||
#include "hid.asl"
|
||||
#include "lid.asl"
|
||||
#include "s76.asl"
|
||||
#include "sleep.asl"
|
||||
}
|
||||
|
||||
Scope (_GPE) {
|
||||
#include "gpe.asl"
|
||||
#include "gpe.asl"
|
||||
}
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// Notifications:
|
||||
// 0x80 - hardware backlight toggle
|
||||
@ -20,108 +7,78 @@
|
||||
// 0x83 - backlight up
|
||||
// 0x84 - backlight color change
|
||||
Device (S76D) {
|
||||
Name (_HID, "17761776")
|
||||
Name (_UID, 0)
|
||||
Name (_HID, "17761776")
|
||||
Name (_UID, 0)
|
||||
|
||||
Method (RSET, 0, Serialized) {
|
||||
Debug = "S76D: RSET"
|
||||
SAPL(0)
|
||||
SKBL(0)
|
||||
#if COLOR_KEYBOARD
|
||||
SKBC(0xFFFFFF)
|
||||
#endif
|
||||
}
|
||||
Method (RSET, 0, Serialized) {
|
||||
Debug = "S76D: RSET"
|
||||
SAPL(0)
|
||||
SKBL(0)
|
||||
}
|
||||
|
||||
Method (INIT, 0, Serialized) {
|
||||
Debug = "S76D: INIT"
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use software control
|
||||
^^PCI0.LPCB.EC0.ECOS = 2
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Method (INIT, 0, Serialized) {
|
||||
Debug = "S76D: INIT"
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use software control
|
||||
^^PCI0.LPCB.EC0.ECOS = 2
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
Method (FINI, 0, Serialized) {
|
||||
Debug = "S76D: FINI"
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use hardware control
|
||||
^^PCI0.LPCB.EC0.ECOS = 1
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Method (FINI, 0, Serialized) {
|
||||
Debug = "S76D: FINI"
|
||||
RSET()
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
// Set flags to use hardware control
|
||||
^^PCI0.LPCB.EC0.ECOS = 1
|
||||
Return (0)
|
||||
} Else {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
|
||||
// Get Airplane LED
|
||||
Method (GAPL, 0, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
// Get Airplane LED
|
||||
Method (GAPL, 0, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
|
||||
// Set Airplane LED
|
||||
Method (SAPL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0) {
|
||||
^^PCI0.LPCB.EC0.AIRP |= 0x40
|
||||
} Else {
|
||||
^^PCI0.LPCB.EC0.AIRP &= 0xBF
|
||||
}
|
||||
}
|
||||
}
|
||||
// Set Airplane LED
|
||||
Method (SAPL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
If (Arg0) {
|
||||
^^PCI0.LPCB.EC0.AIRP |= 0x40
|
||||
} Else {
|
||||
^^PCI0.LPCB.EC0.AIRP &= 0xBF
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if COLOR_KEYBOARD
|
||||
// Set KB LED Brightness
|
||||
Method (SKBL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 6
|
||||
^^PCI0.LPCB.EC0.FBUF = Arg0
|
||||
^^PCI0.LPCB.EC0.FBF1 = 0
|
||||
^^PCI0.LPCB.EC0.FBF2 = Arg0
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
// Get KB LED
|
||||
Method (GKBL, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = One
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
^^PCI0.LPCB.EC0.FCMD = Zero
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set Keyboard Color
|
||||
Method (SKBC, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = 0x3
|
||||
^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Return (Arg0)
|
||||
} Else {
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
#else
|
||||
// Get KB LED
|
||||
Method (GKBL, 0, Serialized) {
|
||||
Local0 = 0
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = One
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
Local0 = ^^PCI0.LPCB.EC0.FBUF
|
||||
^^PCI0.LPCB.EC0.FCMD = Zero
|
||||
}
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Set KB Led
|
||||
Method (SKBL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = Zero
|
||||
^^PCI0.LPCB.EC0.FBUF = Arg0
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
#endif
|
||||
// Set KB Led
|
||||
Method (SKBL, 1, Serialized) {
|
||||
If (^^PCI0.LPCB.EC0.ECOK) {
|
||||
^^PCI0.LPCB.EC0.FDAT = Zero
|
||||
^^PCI0.LPCB.EC0.FBUF = Arg0
|
||||
^^PCI0.LPCB.EC0.FCMD = 0xCA
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Method called from _PTS prior to enter sleep state */
|
||||
Method (MPTS, 1) {
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
@ -1,22 +1,10 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void bootblock_mainboard_init(void) {
|
||||
void bootblock_mainboard_init(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
||||
@ -1,250 +1,250 @@
|
||||
chip soc/intel/skylake
|
||||
|
||||
# Enable deep Sx states
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
||||
# Enable deep Sx states
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
||||
|
||||
register "eist_enable" = "1"
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_C"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_C"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
register "gen1_dec" = "0x000c0681"
|
||||
register "gen2_dec" = "0x000c1641"
|
||||
register "gen3_dec" = "0x000c0081"
|
||||
register "gen4_dec" = "0x00040069"
|
||||
register "gen1_dec" = "0x000c0681"
|
||||
register "gen2_dec" = "0x000c1641"
|
||||
register "gen3_dec" = "0x000c0081"
|
||||
register "gen4_dec" = "0x00040069"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
# FSP Configuration
|
||||
register "ProbelessTrace" = "0"
|
||||
register "EnableLan" = "0"
|
||||
register "EnableSata" = "1"
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "0"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsDevSlp[0]" = "0"
|
||||
register "SataPortsDevSlp[2]" = "0"
|
||||
register "SataSpeedLimit" = "2"
|
||||
register "EnableAzalia" = "1"
|
||||
register "DspEnable" = "0"
|
||||
register "IoBufferOwnership" = "0"
|
||||
register "EnableTraceHub" = "0"
|
||||
register "SsicPortEnable" = "0"
|
||||
register "SmbusEnable" = "1"
|
||||
register "Cio2Enable" = "0"
|
||||
register "ScsEmmcEnabled" = "0"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "0"
|
||||
register "PttSwitch" = "0"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "Device4Enable" = "1"
|
||||
register "HeciEnabled" = "1"
|
||||
register "SaGv" = "3"
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||
register "PmConfigSlpS4MinAssert" = "1" # 1s
|
||||
register "PmConfigSlpSusMinAssert" = "3" # 500ms
|
||||
register "PmConfigSlpAMinAssert" = "3" # 2s
|
||||
register "PmTimerDisabled" = "0"
|
||||
# FSP Configuration
|
||||
register "ProbelessTrace" = "0"
|
||||
register "EnableLan" = "0"
|
||||
register "EnableSata" = "1"
|
||||
register "SataSalpSupport" = "0"
|
||||
register "SataMode" = "0"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "0"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsDevSlp[0]" = "0"
|
||||
register "SataPortsDevSlp[2]" = "0"
|
||||
register "SataSpeedLimit" = "2"
|
||||
register "EnableAzalia" = "1"
|
||||
register "DspEnable" = "0"
|
||||
register "IoBufferOwnership" = "0"
|
||||
register "EnableTraceHub" = "0"
|
||||
register "SsicPortEnable" = "0"
|
||||
register "SmbusEnable" = "1"
|
||||
register "Cio2Enable" = "0"
|
||||
register "ScsEmmcEnabled" = "0"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "0"
|
||||
register "PttSwitch" = "0"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "Device4Enable" = "1"
|
||||
register "HeciEnabled" = "1"
|
||||
register "SaGv" = "3"
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
||||
register "PmConfigSlpS4MinAssert" = "1" # 1s
|
||||
register "PmConfigSlpSusMinAssert" = "3" # 500ms
|
||||
register "PmConfigSlpAMinAssert" = "3" # 2s
|
||||
register "PmTimerDisabled" = "0"
|
||||
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
|
||||
# Root port #1 x4 (TBT)
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpClkReqSupport[0]" = "1"
|
||||
register "PcieRpClkReqNumber[0]" = "4"
|
||||
register "PcieRpClkSrcNumber[0]" = "4"
|
||||
register "PcieRpAdvancedErrorReporting[0]" = "1"
|
||||
register "PcieRpLtrEnable[0]" = "1"
|
||||
register "PcieRpHotPlug[0]" = "1"
|
||||
# Root port #1 x4 (TBT)
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpClkReqSupport[0]" = "1"
|
||||
register "PcieRpClkReqNumber[0]" = "4"
|
||||
register "PcieRpClkSrcNumber[0]" = "4"
|
||||
register "PcieRpAdvancedErrorReporting[0]" = "1"
|
||||
register "PcieRpLtrEnable[0]" = "1"
|
||||
register "PcieRpHotPlug[0]" = "1"
|
||||
|
||||
# Root port #5 x1 (LAN)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpClkReqSupport[4]" = "1"
|
||||
register "PcieRpClkReqNumber[4]" = "3"
|
||||
register "PcieRpClkSrcNumber[4]" = "3"
|
||||
register "PcieRpAdvancedErrorReporting[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
# Root port #5 x1 (LAN)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpClkReqSupport[4]" = "1"
|
||||
register "PcieRpClkReqNumber[4]" = "3"
|
||||
register "PcieRpClkSrcNumber[4]" = "3"
|
||||
register "PcieRpAdvancedErrorReporting[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
|
||||
# Root port #6 x1 (WLAN)
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpClkReqSupport[5]" = "1"
|
||||
register "PcieRpClkReqNumber[5]" = "2"
|
||||
register "PcieRpClkSrcNumber[5]" = "2"
|
||||
register "PcieRpAdvancedErrorReporting[5]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
# Root port #6 x1 (WLAN)
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpClkReqSupport[5]" = "1"
|
||||
register "PcieRpClkReqNumber[5]" = "2"
|
||||
register "PcieRpClkSrcNumber[5]" = "2"
|
||||
register "PcieRpAdvancedErrorReporting[5]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
|
||||
# Root port #9 x4 (NVMe)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpClkReqSupport[8]" = "1"
|
||||
register "PcieRpClkReqNumber[8]" = "5"
|
||||
register "PcieRpClkSrcNumber[8]" = "5"
|
||||
register "PcieRpAdvancedErrorReporting[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
# Root port #9 x4 (NVMe)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpClkReqSupport[8]" = "1"
|
||||
register "PcieRpClkReqNumber[8]" = "5"
|
||||
register "PcieRpClkSrcNumber[8]" = "5"
|
||||
register "PcieRpAdvancedErrorReporting[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
|
||||
# Configure USB2 ports
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right
|
||||
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC
|
||||
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left
|
||||
register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
|
||||
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC
|
||||
# Configure USB2 ports
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right
|
||||
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
|
||||
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC
|
||||
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left
|
||||
register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
|
||||
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC
|
||||
|
||||
# Configure USB3 ports
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left
|
||||
# Configure USB3 ports
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left
|
||||
|
||||
# PL2 override 44W
|
||||
register "tdp_pl2_override" = "40"
|
||||
# PL2 override 44W
|
||||
register "tdp_pl2_override" = "40"
|
||||
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Domain/Setting | SA | IA | GT Unsliced | GT |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 4A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| IccMax | 5A | 64A | 31A | 31A |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(4),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(5),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1030,
|
||||
.dc_loadline = 1030,
|
||||
}"
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Domain/Setting | SA | IA | GT Unsliced | GT |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 4A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| IccMax | 5A | 64A | 31A | 31A |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#+----------------+-----------+-----------+-------------+----------+
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(4),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(5),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1030,
|
||||
.dc_loadline = 1030,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(64),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 240,
|
||||
.dc_loadline = 240,
|
||||
}"
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(64),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 240,
|
||||
.dc_loadline = 240,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 16.0 off end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 on end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 16.0 off end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 on end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1f.0 on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
||||
@ -1,19 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 System76
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user