Add sunrise

Change-Id: I4ae434552b2fa00a56e4e1ec4ec9360c9e82ee9b

src/mainboard/system76/sunrise/Kconfig

@@ -0,0 +1,85 @@
+if BOARD_SYSTEM76_SUNRISE
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select AMD_SOC_CONSOLE_UART
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
+	select NO_UART_ON_SUPERIO
+	select SOC_AMD_CEZANNE
+	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/sunrise"
+
+config MAINBOARD_PART_NUMBER
+	default "sunrise"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Sunrise"
+
+config MAINBOARD_VERSION
+	default "sunrise"
+
+config AMD_FWM_POSITION_INDEX
+	default 3
+
+config AMDFW_CONFIG_FILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_MAX
+	default 4
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EFS_SPI_READ_MODE
+	default 5          # Quad IO (1-4-4)
+
+config EFS_SPI_SPEED
+	default 0	# 66MHz
+
+config EFS_SPI_MICRON_FLAG
+	default 2
+
+config NORMAL_READ_SPI_SPEED
+	default 1	# 33MHz
+
+config ALT_SPI_SPEED
+	default 0	# 66MHz
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config PSP_LOAD_MP2_FW
+	default y
+
+config PSP_POSTCODES_ON_ESPI
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+endif

src/mainboard/system76/sunrise/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_SUNRISE
+	bool "sunrise"

src/mainboard/system76/sunrise/Makefile.inc

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+
+romstage-y += port_descriptors.c
+
+APCB_SOURCES = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb
+APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_recovery
+APCB_SOURCES_68 = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_68

src/mainboard/system76/sunrise/amdfw.cfg

@@ -0,0 +1,38 @@
+# PSP fw config file
+
+FIRMWARE_LOCATION      3rdparty/amd_blobs/cezanne/PSP
+
+# type                    file
+# PSP
+AMD_PUBKEY_FILE         TypeId0x00_CezannePublicKey.tkn
+PSPBTLDR_FILE           TypeId0x01_PspBootLoader_CZN.sbin
+PSPSECUREOS_FILE        TypeId0x02_PspOS_CZN.sbin
+PSPRCVR_FILE            TypeId0x03_PspRecoveryBootLoader_CZN.sbin
+PSP_SMUFW1_SUB0_FILE    TypeId0x08_SmuFirmware_CZN.csbin
+PSPSECUREDEBUG_FILE     TypeId0x09_SecureDebugUnlockKey_CZN.stkn
+PSPTRUSTLETS_FILE       TypeId0x0C_FtpmDrv_CZN.csbin
+PSP_SMUFW2_SUB0_FILE    TypeId0x12_SmuFirmware2_CZN.csbin
+PSP_SEC_DEBUG_FILE      TypeId0x13_PspEarlyUnlock_CZN.sbin
+PSP_HW_IPCFG_FILE       TypeId0x20_HwIpCfg_CZN_A0.sbin
+PSP_IKEK_FILE           TypeId0x21_PspIkek_CZN.bin
+PSP_SECG0_FILE          TypeId0x24_SecurePolicyL0_CZN.sbin
+PSP_MP2FW0_FILE         TypeId0x25_Mp2Fw_CZN.sbin
+AMD_DRIVER_ENTRIES      TypeId0x28_PspSystemDriver_CZN.sbin
+PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
+PSP_S0I3_FILE           TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
+PSP_ABL0_FILE           TypeId0x30_AgesaBootloaderU_CZN.csbin
+VBIOS_BTLOADER_FILE       TypeId0x3C_VbiosBootLoader_CZN.sbin
+UNIFIEDUSB_FILE         TypeId0x44_UnifiedUsb_CZN.sbin
+SECURE_POLICY_L1_FILE   TypeId0x45_SecurePolicyL1_CZN.sbin
+DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
+KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
+KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
+DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
+DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
+
+# BDT
+PSP_PMUI_FILE1  TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE1  TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
+PSP_PMUI_FILE2  TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE2  TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
+PSP_MP2CFG_FILE MP2FWConfig.sbin

src/mainboard/system76/sunrise/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: sunrise
+Category: laptop
+Release year: 2022
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/sunrise/bootblock.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <amdblocks/lpc.h>
+#include <console/console.h>
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+	post_code(0x76);
+	post_code(0x01);
+
+	mainboard_program_early_gpios();
+
+	post_code(0x76);
+	post_code(0x02);
+
+	// AP/EC command
+	lpc_set_wideio_range(0xE00, 256);
+
+	// AP/EC debug
+	lpc_set_wideio_range(0xF00, 256);
+
+	post_code(0x76);
+	post_code(0x03);
+}
+
+void bootblock_mainboard_init(void)
+{
+	post_code(0x76);
+	post_code(0x10);
+}

src/mainboard/system76/sunrise/devicetree.cb

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/cezanne
+
+	register "common_config.acp_config" = "{
+		.acp_pin_cfg = I2S_PINS_I2S_TDM,
+		.acp_i2s_wake_enable = 0,
+		.acp_pme_enable = 0,
+		.dmic_present = 1,
+	}"
+
+	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+	# I2C Pad Control RX Select Configuration
+	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad
+	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # ALS
+	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # DDR4
+	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # USB-PD
+
+
+	register "s0ix_enable" = "true"
+
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
+	#TODO
+	register "gpp_clk_config[0]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[1]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[2]" = "GPP_CLK_REQ" # XHCI
+	register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD
+	register "gpp_clk_config[4]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[5]" = "GPP_CLK_REQ" # WLAN
+	register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
+	#TODO: USB?
+
+	device domain 0 on
+		#TODO
+		device ref iommu on end
+		device ref gpp_gfx_bridge_0 on end # DGPU
+		device ref gpp_bridge_0 on end # LAN
+		device ref gpp_bridge_1 on end # WLAN
+		device ref gpp_bridge_2 on end # SSD2
+		device ref gpp_bridge_3 on end # SSD1
+		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
+			device ref gfx on end # Internal GPU (GFX)
+			device ref gfx_hda on end # GFX HD Audio Controller
+			device ref crypto on end # Crypto Coprocessor
+			device ref xhci_0 on end # USB 3.1 (USB0)
+			device ref xhci_1 on end # USB 3.1 (USB1)
+			device ref acp on end # Audio Processor
+			device ref hda on end # HD Audio Controller
+		end
+		device ref gpp_bridge_b on  # Internal GPP Bridge 1 to Bus B
+			device ref sata_0 on end # SATA
+			device ref sata_1 on end # SATA
+		end
+	end
+
+	device ref uart_0 on end # UART0
+
+end

src/mainboard/system76/sunrise/dsdt.asl

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <soc.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#define EC_GPE_SCI 0x6E
+	#define EC_GPE_SWI 0x6B
+	#include <ec/system76/ec/acpi/ec.asl>
+}

src/mainboard/system76/sunrise/early_gpio.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+	//TODO
+};
+
+void mainboard_program_early_gpios(void)
+{
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}

src/mainboard/system76/sunrise/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
+
+#endif  /* MAINBOARD_GPIO_H */

src/mainboard/system76/sunrise/mainboard.c

@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/amd_pci_util.h>
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <string.h>
+#include <types.h>
+
+/*
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system.  It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair.  These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ */
+static uint8_t fch_pic_routing[0x80];
+static uint8_t fch_apic_routing[0x80];
+
+_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
+	"PIC and APIC FCH interrupt tables must be the same size");
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ *  0: timer < soc/amd/common/acpi/lpc.asl
+ *  1: i8042 - Keyboard
+ *  2: cascade
+ *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ *  9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing {
+	uint8_t intr_index;
+	uint8_t pic_irq_num;
+	uint8_t apic_irq_num;
+} sunrise_fch[] = {
+	{ PIRQ_A,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_B,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_C,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_D,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_E,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_F,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_G,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_H,	PIRQ_NC,	PIRQ_NC },
+
+	{ PIRQ_SCI,	ACPI_SCI_IRQ,	ACPI_SCI_IRQ },
+	{ PIRQ_SD,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SDIO,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SATA,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_EMMC,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_GPIO,	7,		7 },
+	{ PIRQ_I2C2,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_I2C3,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_UART0,	 4,		 4 },
+	{ PIRQ_UART1,	 3,		 3 },
+
+	/* The MISC registers are not interrupt numbers */
+	{ PIRQ_MISC,	0xfa,		0x00 },
+	{ PIRQ_MISC0,	0x91,		0x00 },
+	{ PIRQ_HPET_L,	0x00,		0x00 },
+	{ PIRQ_HPET_H,	0x00,		0x00 },
+};
+
+static void init_tables(void)
+{
+	const struct fch_irq_routing *entry;
+	int i;
+
+	memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
+	memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
+
+	for (i = 0; i < ARRAY_SIZE(sunrise_fch); i++) {
+		entry = sunrise_fch + i;
+		fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
+		fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
+	}
+}
+
+static void pirq_setup(void)
+{
+	intr_data_ptr = fch_apic_routing;
+	picr_data_ptr = fch_pic_routing;
+}
+
+static void mainboard_init(void *chip_info)
+{
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	init_tables();
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/system76/sunrise/port_descriptors.c

@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/platform_descriptors.h>
+#include <types.h>
+
+static const fsp_dxio_descriptor sunrise_dxio_descriptors[] = {
+	// TODO
+	// { /* DGPU */
+	// 	.engine_type = PCIE_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 16,
+	// 	.end_logical_lane = 23,
+	// 	.device_number = 1,
+	// 	.function_number = 1,
+	// 	.turn_off_unused_lanes = true,
+	// 	.clk_req = CLK_REQ0,
+	// 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	// },
+	// { /* LAN */
+	// 	.engine_type = PCIE_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 0,
+	// 	.end_logical_lane = 0,
+	// 	.device_number = 2,
+	// 	.function_number = 1,
+	// 	.turn_off_unused_lanes = true,
+	// 	.clk_req = CLK_REQ1,
+	// 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	// },
+	// { /* WLAN */
+	// 	.engine_type = PCIE_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 1,
+	// 	.end_logical_lane = 1,
+	// 	.device_number = 2,
+	// 	.function_number = 2,
+	// 	.turn_off_unused_lanes = true,
+	// 	.clk_req = CLK_REQ6,
+	// 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	// },
+	// { /* SSD2 */
+	// 	.engine_type = PCIE_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 4,
+	// 	.end_logical_lane = 7,
+	// 	.device_number = 2,
+	// 	.function_number = 3,
+	// 	.turn_off_unused_lanes = true,
+	// 	.clk_req = CLK_REQ4_GFX,
+	// 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	// },
+	// { /* SSD1 */
+	// 	.engine_type = PCIE_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 8,
+	// 	.end_logical_lane = 11,
+	// 	.device_number = 2,
+	// 	.function_number = 4,
+	// 	.turn_off_unused_lanes = true,
+	// 	.clk_req = CLK_REQ5,
+	// 	.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	// },
+	// { /* HDD */
+	// 	.engine_type = SATA_ENGINE,
+	// 	.port_present = true,
+	// 	.start_logical_lane = 0,
+	// 	.end_logical_lane = 0,
+	// 	.channel_type = SATA_CHANNEL_LONG,
+	// }
+};
+
+static const fsp_ddi_descriptor sunrise_ddi_descriptors[] = {
+	{ /* DDI0 - eDP */
+		.connector_type = DDI_EDP,
+		.aux_index = DDI_AUX1,
+		.hdp_index = DDI_HDP1
+	},
+	{ /* DDI1 - HDMI */
+		.connector_type = DDI_HDMI,
+		.aux_index = DDI_AUX2,
+		.hdp_index = DDI_HDP2
+	},
+	{ /* DDI2 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI3 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI4 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX4,
+		.hdp_index = DDI_HDP4,
+	}
+};
+
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+	*dxio_descs = sunrise_dxio_descriptors;
+	*dxio_num = ARRAY_SIZE(sunrise_dxio_descriptors);
+	*ddi_descs = sunrise_ddi_descriptors;
+	*ddi_num = ARRAY_SIZE(sunrise_ddi_descriptors);
+}