mainboard/google/zoombini: Provide memory configuration variant API

Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure
that required SPD hex files are included in the SPD binary.

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/zoombini/Kconfig

@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
 	select HAVE_ACPI_TABLES
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_CANNONLAKE
+	select SOC_INTEL_CANNONLAKE_LPDDR4_INIT
 
 if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
 
@@ -19,6 +20,10 @@ config DEVICETREE
 	string
 	default "variants/baseboard/devicetree.cb"
 
+config DIMM_SPD_SIZE
+	int
+	default 512
+
 config DRIVER_TPM_I2C_BUS
 	depends on ZOOMBINI_USE_I2C_TPM
 	default 0x1

src/mainboard/google/zoombini/Makefile.inc

@@ -20,6 +20,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-y += boardid.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += memory.c
 romstage-y += romstage.c
 
 ramstage-y += boardid.c
@@ -34,3 +35,23 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+# If variant using SPD files, include them in the CBFS
+ifneq ($(SPD_SOURCES),)
+        SPD_BIN = $(obj)/spd.bin
+        SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+        for f in $+; \
+                do for c in $$(cat $$f | grep -v ^#); \
+                        do printf $$(printf '\%o' 0x$$c); \
+                done; \
+        done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
+endif
+
+subdirs-y += variants/$(VARIANT_DIR)/spd

src/mainboard/google/zoombini/memory.c

@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/cnl_lpddr4_init.h>
+
+static const struct lpddr4_cfg baseboard_lpddr4_cfg = {
+	.dq_map[LP4_CH0] = {
+		/*
+		 * CLK0 goes to package 0 - Bytes[3:0],
+		 * CLK1 goes to package 1 - Bytes[7:4]
+		 */
+		{ 0x0F, 0xF0 },
+
+		/*
+		 * Cmd CAA goes to Bytes[3:0],
+		 * Cmd CAB goes to Bytes[7:4]
+		 */
+		{ 0x0F, 0xF0 },
+
+		/* CTL (CS) goes to all bytes */
+		{ 0xFF, 0x00 },
+	},
+
+	.dq_map[LP4_CH1] = {
+		/*
+		 * CLK0 goes to package 0 - Bytes[3:0],
+		 * CLK1 goes to package 1 - Bytes[7:4]
+		 */
+		{ 0x0F, 0xF0 },
+
+		/*
+		 * Cmd CAA goes to Bytes[3:0],
+		 * Cmd CAB goes to Bytes[7:4]
+		 */
+		{ 0x0F, 0xF0 },
+
+		/* CTL (CS) goes to all bytes */
+		{ 0xFF, 0x00 },
+	},
+
+	/*
+	 * The dqs_map arrays map the lpddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on lpddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[LP4_CH0] = { 3, 1, 2, 0, 7, 5, 6, 4 },
+	.dqs_map[LP4_CH1] = { 3, 2, 0, 1, 7, 5, 6, 4 },
+
+	/* Baseboard uses three 100 Ohm rcomp resistors */
+	.rcomp_resistor = { 100, 100, 100 },
+
+	/*
+	 * Baseboard Rcomp target values.
+	 * Rcomp targets for baseboard should be
+	 * { 80, 40, 40, 40, 30 }, but we need to
+	 * nil out rcomp targets for now to avoid bug b:70896346
+	 */
+	.rcomp_targets = { 0, 0, 0, 0, 0 },
+
+	/* Baseboard is a non-interleaved design */
+	.dq_pins_interleaved = 0,
+
+	/* Disable Early Command Training */
+	.ect = 0,
+};
+
+const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void)
+{
+	return &baseboard_lpddr4_cfg;
+}
+
+size_t __attribute__((weak)) variant_memory_sku(void)
+{
+	const gpio_t pads[] = {
+		[3] = GPIO_MEM_CONFIG_3, [2] = GPIO_MEM_CONFIG_2,
+		[1] = GPIO_MEM_CONFIG_1, [0] = GPIO_MEM_CONFIG_0,
+	};
+
+	return gpio_base2_value(pads, ARRAY_SIZE(pads));
+}

src/mainboard/google/zoombini/romstage.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Google Inc.
+ * Copyright 2017 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,12 +13,17 @@
  * GNU General Public License for more details.
  */
 
+#include <baseboard/variants.h>
+#include <soc/cnl_lpddr4_init.h>
 #include <soc/romstage.h>
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-/*
+	const struct spd_info spd = {
-	meminit_lpddr4_by_sku(&memupd->FspmConfig, get_lpddr4_config(),
+		.spd_by_index = true,
-			get_memory_sku());
+		.spd_spec.spd_index = variant_memory_sku(),
-*/
+	};
+
+	cannonlake_lpddr4_init(&memupd->FspmConfig,
+				variant_lpddr4_config(), &spd);
 }

src/mainboard/google/zoombini/variants/baseboard/Makefile.inc

@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2017 Google Inc.
+## Copyright 2017 Google Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by

src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h

@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __MAINBOARD_GPIO_H__
+#ifndef __BASEBOARD_GPIO_H__
-#define __MAINBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
 
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h

@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2017 Google Inc.
  * Copyright 2017 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -16,6 +17,7 @@
 #ifndef __BASEBOARD_VARIANTS_H__
 #define __BASEBOARD_VARIANTS_H__
 
+#include <soc/cnl_lpddr4_init.h>
 #include <soc/gpio.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -32,4 +34,10 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
 
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
+/* Return LPDDR4 configuration structure. */
+const struct lpddr4_cfg *variant_lpddr4_config(void);
+
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */

src/mainboard/google/zoombini/variants/zoombini/spd/Hynix_H9HCNNN8KUMLHR_1GB.spd.hex

@@ -0,0 +1,32 @@
+23 11 10 0E 15 19 05 08 00 40 00 00 02 22 00 00
+48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 9E 00 A7 CF D0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/google/zoombini/variants/zoombini/spd/Makefile.inc

@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2017 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = Hynix_H9HCNNN8KUMLHR_1GB		# 0b000
+SPD_SOURCES += Micron_MT53B512M32D2_2GB		# 1b001
+SPD_SOURCES += Micron_MT53B1024M32D4_4GB	# 2b010

src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B1024M32D4_4GB.spd.hex

@@ -0,0 +1,32 @@
+23 11 10 OE 15 21 B5 08 00 40 00 00 0A 63 00 00
+51 00 05 FF D2 5D 01 00 A0 41 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/google/zoombini/variants/zoombini/spd/Micron_MT53B512M32D2_2GB.spd.hex

@@ -0,0 +1,32 @@
+23 11 10 OE 15 19 95 08 00 40 00 00 0A 63 00 00
+09 00 04 00 D2 5D 05 00 89 41 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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