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Broadcom BCM5785: Add TINY_BOOTBLOCK support.

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In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
and use 'dev' instead of 'addr' as device_t variable name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-11-26 22:42:41 +00:00
parent e89d8a57ac
commit 39124dd6c5
7 changed files with 17 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/broadcom/blast/romstage.c
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@@ -10,7 +10,6 @@
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
@@ -82,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc(); bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
} }

2
src/mainboard/hp/dl145_g3/romstage.c
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@@ -41,7 +41,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
@@ -145,7 +144,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc(); bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
} }

2
src/mainboard/hp/dl165_g6_fam10/romstage.c
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@@ -40,7 +40,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h> #include <lib.h>
@@ -109,7 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */ /* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc(); bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
} }

2
src/mainboard/msi/ms9185/romstage.c
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@@ -35,7 +35,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
@@ -115,7 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc(); bcm5785_enable_lpc();
//enable RTC //enable RTC
pc87417_enable_dev(RTC_DEV); pc87417_enable_dev(RTC_DEV);

1
src/southbridge/broadcom/bcm5785/Kconfig
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@@ -1,6 +1,7 @@
config SOUTHBRIDGE_BROADCOM_BCM5785 config SOUTHBRIDGE_BROADCOM_BCM5785
bool bool
select HAVE_HARD_RESET select HAVE_HARD_RESET
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string

21
src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
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@@ -18,17 +18,22 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
static void bcm5785_enable_rom(void) static void bcm5785_enable_rom(void)
{ {
unsigned char byte; u8 byte;
device_t addr; device_t dev;
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
/* Locate the BCM 5785 SB PCI Main */ PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
/* Set the 4MB enable bit bit */ /* Set the 4MB enable bits. */
byte = pci_read_config8(addr, 0x41); byte = pci_read_config8(dev, 0x41);
byte |= 0x0e; byte |= 0x0e;
pci_write_config8(addr, 0x41, byte); pci_write_config8(dev, 0x41, byte);
} }

3
src/southbridge/broadcom/bcm5785/bootblock.c
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@@ -20,6 +20,7 @@
#include "bcm5785_enable_rom.c" #include "bcm5785_enable_rom.c"
static void bootblock_southbridge_init(void) { static void bootblock_southbridge_init(void)
{
bcm5785_enable_rom(); bcm5785_enable_rom();
} }