Update whl-u memory config
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		@@ -18,6 +18,18 @@
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//TODO: find correct values
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					//TODO: find correct values
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static const struct cnl_mb_cfg memcfg = {
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					static const struct cnl_mb_cfg memcfg = {
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						/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
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						.spd[0] = {
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							.read_type = READ_SMBUS,
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							.spd_spec = {.spd_smbus_address = 0xa0},
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						},
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						.spd[1] = {.read_type = NOT_EXISTING},
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						.spd[2] = {
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							.read_type = READ_SMBUS,
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							.spd_spec = {.spd_smbus_address = 0xa4},
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						},
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						.spd[3] = {.read_type = NOT_EXISTING},
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	/*
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						/*
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	 * For each channel, there are 3 sets of DQ byte mappings,
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						 * For each channel, there are 3 sets of DQ byte mappings,
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	 * where each set has a package 0 and a package 1 value (package 0
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						 * where each set has a package 0 and a package 1 value (package 0
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@@ -77,14 +89,9 @@ static const struct cnl_mb_cfg memcfg = {
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	.vref_ca_config = 2,
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						.vref_ca_config = 2,
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	/* Early Command Training Enabled */
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						/* Early Command Training Enabled */
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	.ect = 1,
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						.ect = 0,
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};
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					};
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void mainboard_memory_init_params(FSPM_UPD *memupd) {
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					void mainboard_memory_init_params(FSPM_UPD *memupd) {
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	const struct spd_info spd = {
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						cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
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		.spd_smbus_address[0] = 0xA0,
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		.spd_smbus_address[2] = 0xA4,
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	};
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	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd);
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}
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					}
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