added new superio. added new simple util.

modified dell 1850


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/dell/s1850/Config.lb

@@ -147,23 +147,19 @@ chip northbridge/intel/E7520 # mch
 		
 			# -> ISA
 			device pci 1f.0 on 
-				chip superio/winbond/w83627hf
+				chip superio/NSC/pc8734
 					device pnp 2e.0 off end
-					device pnp 2e.2 on 
+					device pnp 2e.1 off end
+					device pnp 2e.2 off end
+					device pnp 2e.3 on 
 						 io 0x60 = 0x3f8
 						irq 0x70 = 4
 					end
-					device pnp 2e.3 on
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
 					device pnp 2e.4 off end
 					device pnp 2e.5 off end
 					device pnp 2e.6 off end
 					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a on  end
-					device pnp 2e.b off end
+					device pnp 2e.8 off end
 				end
 			end
 			# -> IDE
@@ -172,8 +168,8 @@ chip northbridge/intel/E7520 # mch
 			device pci 1f.2 on end
 			device pci 1f.3 on end
 
-			register "pirq_a_d" = "0x0b070a05"
-			register "pirq_e_h" = "0x0a808080"
+			register "pirq_a_d" = "0x8a07030b"
+			register "pirq_e_h" = "0x85808080"
 		end
 		device pci 00.0 on end 
 		device pci 00.1 on end
@@ -204,6 +200,6 @@ chip northbridge/intel/E7520 # mch
 			device apic 6 on end
 		end
 	end
-	register "intrline" = "0x00070105"
+	register "intrline" = "0x00070100"
 end
 

src/superio/NSC/pc8374/Config.lb

@@ -0,0 +1,2 @@
+config chip.h
+object superio.o

src/superio/NSC/pc8374/chip.h

@@ -0,0 +1,17 @@
+#ifndef SIO_COM1
+#define SIO_COM1_BASE   0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE   0x2F8
+#endif
+
+struct chip_operations;
+extern struct chip_operations superio_NSC_pc8374_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_NSC_pc8374_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};

src/superio/NSC/pc8374/pc87360.h

@@ -0,0 +1,9 @@
+#define PC8374_FDC  0x00 /* Floppy */
+#define PC8374_PP   0x01 /* Parallel port */
+#define PC8374_SP2  0x02 /* Com2 */
+#define PC8374_SP1  0x03 /* Com1 */
+#define PC8374_SWC  0x04
+#define PC8374_KBCM 0x05 /* Mouse */
+#define PC8374_KBCK 0x06 /* Keyboard */
+#define PC8374_GPIO 0x07
+#define PC8374_HM  0x08

src/superio/NSC/pc8374/pc87360_early_serial.c

@@ -0,0 +1,11 @@
+#include <arch/romcc_io.h>
+#include "pc8374.h"
+
+
+static void pc8374_enable_serial(device_t dev, unsigned iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 1);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}

src/superio/NSC/pc8374/superio.c

@@ -0,0 +1,73 @@
+/* Copyright 2000  AG Electronics Ltd. */
+/* Copyright 2003-2004 Linux Networx */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "pc8374.h"
+
+static void init(device_t dev)
+{
+	struct superio_NSC_pc8374_config *conf;
+	struct resource *res0, *res1;
+	/* Wishlist handle well known programming interfaces more
+	 * generically.
+	 */
+	if (!dev->enabled) {
+		return;
+	}
+	conf = dev->chip_info;
+	switch(dev->path.u.pnp.device) {
+	case PC8374_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC8374_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case PC8374_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, PC8374_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+ { &ops, PC8374_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
+ { &ops, PC8374_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
+ { &ops, PC8374_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, PC8374_SWC,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
+ { &ops, PC8374_KBCM, PNP_IRQ0 },
+ { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
+};
+
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_NSC_pc8374_ops = {
+	CHIP_NAME("NSC 8374")
+	.enable_dev = enable_dev,
+};