soc/intel/apollolake: Enable TPM in bootblock stage
Configure gpio FST_SPI_CS2_N before verstage so that tpm can be accessed. Change-Id: I238bf1cd508880b686f0625f28175a80de450971 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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| bootblock-$(CONFIG_LPC_TPM) += bootblock.c | ||||
|  | ||||
|  | ||||
|   | ||||
							
								
								
									
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								src/mainboard/intel/apollolake_rvp/bootblock.c
									
									
									
									
									
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								src/mainboard/intel/apollolake_rvp/bootblock.c
									
									
									
									
									
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| /* | ||||
|  * This file is part of the coreboot project. | ||||
|  * | ||||
|  * Copyright (C) 2016 Intel Corp. | ||||
|  * | ||||
|  * This program is free software; you can redistribute it and/or modify | ||||
|  * it under the terms of the GNU General Public License as published by | ||||
|  * the Free Software Foundation; either version 2 of the License, or | ||||
|  * (at your option) any later version. | ||||
|  */ | ||||
|  | ||||
| #include <bootblock_common.h> | ||||
| #include <soc/gpio.h> | ||||
|  | ||||
| static const struct pad_config tpm_spi_configs[] = { | ||||
| 	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */ | ||||
| }; | ||||
|  | ||||
| static void tpm_enable(void) | ||||
| { | ||||
| 	/* Configure gpios */ | ||||
| 	gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); | ||||
| } | ||||
|  | ||||
| void bootblock_mainboard_init(void) { | ||||
| 	if (IS_ENABLED(CONFIG_LPC_TPM)) | ||||
| 		tpm_enable(); | ||||
| } | ||||
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