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sb/intel/i82801gx: Add common early code

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Remove some of the code duplication on i82801gx.
x4x boards are left untouched for now since that northbridge
also supports i82801jx.

The order of some things has changed:
- on i945 early_ich7_init is now done before the raminit
- enabling the IOAPIC is done before the raminit

Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2019-11-11 19:12:57 +01:00
committed by Patrick Georgi
parent 949ff57bca
commit 399b6c11ef
15 changed files with 71 additions and 405 deletions
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18
src/northbridge/intel/pineview/early_init.c
View File

@@ -136,8 +136,6 @@ static void early_misc_setup(void)
pci_write_config8(LPC, 0x8, 0x0);
RCBA32(0x3410) = 0x00020465;
ich7_setup_cir();
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
@@ -156,22 +154,6 @@ static void early_misc_setup(void)
static void pineview_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
i82801gx_setup_bars();
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
pci_write_config8(D0F0, 0x8, 0x69);

11
src/northbridge/intel/pineview/romstage.c
View File

@@ -24,7 +24,6 @@
#include <cf9_reset.h>
#include <romstage_handoff.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <arch/romstage.h>
#include <cpu/x86/lapic.h>
@@ -36,9 +35,6 @@ static void rcba_config(void)
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
}
__weak void mb_pirq_setup(void)
@@ -55,17 +51,12 @@ void mainboard_romstage_entry(void)
enable_lapic();
/* Enable GPIOs */
pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
enable_smbus();
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
pineview_early_initialization();
post_code(0x30);