soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/uart.c

@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#define __SIMPLE_DEVICE__
+
 #include <assert.h>
 #include <console/uart.h>
 #include <device/pci_def.h>
@@ -60,8 +62,10 @@ void pch_uart_init(void)
 	gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
 }
 
+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
 uintptr_t uart_platform_base(int idx)
 {
 	/* We can only have one serial console at a time */
 	return UART_DEBUG_BASE_ADDRESS;
 }
+#endif