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soc/amd/picasso: Update southbridge

Browse Source 
Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary.  The most notable changes are:
 * Update the index values for the C00/C01 interrupt routing
 * FORCE_STPCLK_RETRY is not present
 * PCIB is not defined
 * FCH MISC Registers 0xfed80e00 numbering has changed
 * C-state base moves from PM register to MSR
 * Add option to determine the intended MUX settion for LPC vs. eMMC
 * Remove the LEGACY_FREE option

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
2019-06-20 16:28:33 -06:00
committed by Martin Roth
parent 06fd982030
commit 39a4ac1502
8 changed files with 112 additions and 179 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/soc/amd/picasso/Kconfig
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@@ -178,12 +178,6 @@ config AHCI_ROM_ID
endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5
config PICASSO_LEGACY_FREE
bool "System is legacy free"
help
Select y if there is no keyboard controller in the system.
This sets a variable in ACPI.
config SERIRQ_CONTINUOUS_MODE config SERIRQ_CONTINUOUS_MODE
bool bool
default n default n
@@ -251,6 +245,12 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int int
default 133 default 133
config PICASSO_LPC_IOMUX
bool
help
Picasso's LPC bus signals are MUXed with some of the EMMC signals.
Select this option if LPC signals are required.
config MAINBOARD_POWER_RESTORE config MAINBOARD_POWER_RESTORE
def_bool n def_bool n
help help

2
src/soc/amd/picasso/acpi.c
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@@ -135,7 +135,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alarm work */ fadt->century = 0; /* 0x7f to make rtc alarm work */
fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C1_SUPPORTED |

6
src/soc/amd/picasso/include/soc/acpi.h
View File

@@ -20,12 +20,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#if CONFIG(PICASSO_LEGACY_FREE)
#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
#else
#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
#endif
#ifndef FADT_PM_PROFILE #ifndef FADT_PM_PROFILE
#define FADT_PM_PROFILE PM_UNSPECIFIED #define FADT_PM_PROFILE PM_UNSPECIFIED
#endif #endif

50
src/soc/amd/picasso/include/soc/amd_pci_int_defs.h
View File

@@ -2,7 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2014 Sage Electronic Engineering, LLC. * Copyright (C) 2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2017 Advanced Micro Devices, Inc. * Copyright (C) 2019 Advanced Micro Devices, Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -21,7 +21,10 @@
* PIRQ and device routing - these define the index into the * PIRQ and device routing - these define the index into the
* FCH PCI_INTR 0xC00/0xC01 interrupt routing table. * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
*/ */
/*
* PIRQ and device routing - these define the index into the
* FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
*/
#define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_NC 0x1f /* Not Used */
#define PIRQ_A 0x00 /* INT A */ #define PIRQ_A 0x00 /* INT A */
#define PIRQ_B 0x01 /* INT B */ #define PIRQ_B 0x01 /* INT B */
@@ -31,7 +34,7 @@
#define PIRQ_F 0x05 /* INT F */ #define PIRQ_F 0x05 /* INT F */
#define PIRQ_G 0x06 /* INT G */ #define PIRQ_G 0x06 /* INT G */
#define PIRQ_H 0x07 /* INT H */ #define PIRQ_H 0x07 /* INT H */
#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */
#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */
@@ -40,22 +43,39 @@
#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ #define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ #define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
#define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SCI 0x10 /* SCI IRQ */
#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_SMBUS 0x11 /* SMBUS */
#define PIRQ_ASF 0x12 /* ASF */ #define PIRQ_ASF 0x12 /* ASF */
#define PIRQ_HDA 0x13 /* HDA 14h.2 */ /* 0x13-0x15 reserved */
#define PIRQ_FC 0x14 /* FC */
#define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_PMON 0x16 /* Performance Monitor */
#define PIRQ_SD 0x17 /* SD */ #define PIRQ_SD 0x17 /* SD */
#define PIRQ_SDIO 0x1a /* SDIO */ #define PIRQ_SDIO 0x1a /* SDIO */
#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ /* 0x1b-0x1f reserved */
#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ #define PIRQ_CIR 0x20 /* CIR, no IRQ connected */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */
#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */
#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */
/* 0x24-0x48 reserved */
#define PIRQ_SATA 0x41 /* SATA */
/* 0x42 reserved */
#define PIRQ_EMMC 0x43 /* eMMC */
/* 0x44-0x4f reserved */
#define PIRQ_GPP0 0x50 /* GPPInt0 */
#define PIRQ_GPP1 0x51 /* GPPInt1 */
#define PIRQ_GPP2 0x52 /* GPPInt2 */
#define PIRQ_GPP3 0x53 /* GPPInt3 */
/* 0x54-0x61 reserved */
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
#define PIRQ_I2C0 0x70 /* 0x63-0x6f reserved */
#define PIRQ_I2C1 0x71 #define PIRQ_I2C0 0x70 /* I2C0 */
#define PIRQ_I2C2 0x72 #define PIRQ_I2C1 0x71 /* I2C1 */
#define PIRQ_I2C3 0x73 #define PIRQ_I2C2 0x72 /* I2C2 */
#define PIRQ_UART0 0x74 #define PIRQ_I2C3 0x73 /* I2C3 */
#define PIRQ_UART1 0x75 #define PIRQ_UART0 0x74 /* UART0 */
#define PIRQ_UART1 0x75 /* UART1 */
#define PIRQ_I2C4 0x76 /* I2C4 */
#define PIRQ_I2C5 0x77 /* I2C5 */
#define PIRQ_UART2 0x78 /* UART2 */
#define PIRQ_UART3 0x79 /* UART3 */
/* 0x7a-0x7f reserved */
#endif /* __AMD_PCI_INT_DEFS_H__ */ #endif /* __AMD_PCI_INT_DEFS_H__ */

4
src/soc/amd/picasso/include/soc/cpu.h
View File

@@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2017 Advanced Micro Devices, Inc. * Copyright (C) 2019 Advanced Micro Devices, Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,8 @@
#define SOC_EARLY_VMTRR_FLASH 1 #define SOC_EARLY_VMTRR_FLASH 1
#define SOC_EARLY_VMTRR_TEMPRAM 2 #define SOC_EARLY_VMTRR_TEMPRAM 2
#define CSTATE_BASE_REG 0xc0010073
void picasso_init_cpus(struct device *dev); void picasso_init_cpus(struct device *dev);
int get_cpu_count(void); int get_cpu_count(void);
void check_mca(void); void check_mca(void);

66
src/soc/amd/picasso/include/soc/southbridge.h
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@@ -30,15 +30,14 @@
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_DECODE_EN 0x00 #define PM_DECODE_EN 0x00
#define SMBUS_ASF_IO_EN BIT(4)
#define CF9_IO_EN BIT(1) #define CF9_IO_EN BIT(1)
#define LEGACY_IO_EN BIT(0) #define LEGACY_IO_EN BIT(0)
#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */
#define PM_ISA_CONTROL 0x04 #define PM_ISA_CONTROL 0x04
#define MMIO_EN BIT(1) #define MMIO_EN BIT(1)
#define PM_PCI_CTRL 0x08 #define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_SLPSTATE_RETRY BIT(25)
#define FORCE_STPCLK_RETRY BIT(24)
#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */
#define PWR_RESET_CFG 0x10 #define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD BIT(1) #define TOGGLE_ALL_PWR_GOOD BIT(1)
@@ -94,8 +93,6 @@
#define PM_RST_CTRL1 0xbe #define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5) #define SLPTYPE_CONTROL_EN BIT(5)
#define PM_RST_STATUS 0xc0 #define PM_RST_STATUS 0xc0
#define PM_PCIB_CFG 0xea
#define PM_GENINT_DISABLE BIT(0)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)
@@ -105,13 +102,13 @@
/* SMBUS MMIO offsets 0xfed80a00 */ /* SMBUS MMIO offsets 0xfed80a00 */
#define SMBHSTSTAT 0x0 #define SMBHSTSTAT 0x0
#define SMBHST_STAT_FAILED 0x10 #define SMBHST_STAT_FAILED BIT(4)
#define SMBHST_STAT_COLLISION 0x08 #define SMBHST_STAT_COLLISION BIT(3)
#define SMBHST_STAT_ERROR 0x04 #define SMBHST_STAT_ERROR BIT(2)
#define SMBHST_STAT_INTERRUPT 0x02 #define SMBHST_STAT_INTERRUPT BIT(1)
#define SMBHST_STAT_BUSY 0x01 #define SMBHST_STAT_BUSY BIT(0)
#define SMBHST_STAT_CLEAR 0xff #define SMBHST_STAT_CLEAR 0xff
#define SMBHST_STAT_NOERROR 0x02 #define SMBHST_STAT_NOERROR BIT(1)
#define SMBHST_STAT_VAL_BITS 0x1f #define SMBHST_STAT_VAL_BITS 0x1f
#define SMBHST_STAT_ERROR_BITS 0x1c #define SMBHST_STAT_ERROR_BITS 0x1c
@@ -149,32 +146,27 @@
/* FCH MISC Registers 0xfed80e00 */ /* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00 #define GPP_CLK_CNTRL 0x00
#define GPP_CLK2_REQ_MAP_SHIFT 8 #define GPP_CLK0_REQ_SHL 0
#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) #define GPP_CLK1_REQ_SHL 2
#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 #define GFX_CLK0_REQ_SHL 4
#define GPP_CLK0_REQ_MAP_SHIFT 0 #define GPP_CLK2_REQ_SHL 6
#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) #define GPP_CLK3_REQ_SHL 8
#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 #define GFX_CLK1_REQ_SHL 10
#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL)
#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL)
#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
#define MISC_CGPLL_CONFIG1 0x08 #define MISC_CGPLL_CONFIG1 0x08
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CGPLL_CONFIG3 0x10
#define CG1PLL_REFDIV_SHIFT 0
#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
#define CG1PLL_FBDIV_SHIFT 10
#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
#define MISC_CGPLL_CONFIG4 0x14
#define SS_STEP_SIZE_DSFRAC_SHIFT 0
#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT)
#define SS_AMOUNT_DSFRAC_SHIFT 16
#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT)
#define MISC_CGPLL_CONFIG5 0x18
#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8
#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT)
#define MISC_CGPLL_CONFIG6 0x1c
#define CG1PLL_LF_MODE_SHIFT 9
#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40 #define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
@@ -215,7 +207,9 @@
#define FCH_AOAC_DEV_I2C4 9 #define FCH_AOAC_DEV_I2C4 9
#define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_UART2 16
#define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_ESPI 27
/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
@@ -323,8 +317,8 @@ void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info); void southbridge_init(void *chip_info);
void sb_read_mode(u32 mode); void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void bootblock_fch_early_init(void); void fch_pre_init(void);
void bootblock_fch_init(void); void fch_early_init(void);
/** /**
* @brief Save the UMA bize * @brief Save the UMA bize
* *

1
src/soc/amd/picasso/smihandler.c
View File

@@ -163,7 +163,6 @@ static void sb_slp_typ_handler(void)
/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
pci_ctrl = pm_read32(PM_PCI_CTRL); pci_ctrl = pm_read32(PM_PCI_CTRL);
pci_ctrl &= ~FORCE_SLPSTATE_RETRY; pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
pci_ctrl |= FORCE_STPCLK_RETRY;
pm_write32(PM_PCI_CTRL, pci_ctrl); pm_write32(PM_PCI_CTRL, pci_ctrl);
/* Enable SlpTyp */ /* Enable SlpTyp */

150
src/soc/amd/picasso/southbridge.c
View File

@@ -17,6 +17,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <bootstate.h> #include <bootstate.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@@ -26,6 +27,7 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h> #include <amdblocks/lpc.h>
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <soc/cpu.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <soc/smbus.h> #include <soc/smbus.h>
#include <soc/smi.h> #include <soc/smi.h>
@@ -54,6 +56,7 @@ const static int aoac_devs[] = {
FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C2,
FCH_AOAC_DEV_I2C3, FCH_AOAC_DEV_I2C3,
FCH_AOAC_DEV_I2C4, FCH_AOAC_DEV_I2C4,
FCH_AOAC_DEV_ESPI,
}; };
/* /*
@@ -69,7 +72,7 @@ const static struct irq_idx_name irq_association[] = {
{ PIRQ_C, "INTC#" }, { PIRQ_C, "INTC#" },
{ PIRQ_D, "INTD#" }, { PIRQ_D, "INTD#" },
{ PIRQ_E, "INTE#" }, { PIRQ_E, "INTE#" },
{ PIRQ_F, "INTF#" }, { PIRQ_F, "INTF#/GENINT2" },
{ PIRQ_G, "INTG#" }, { PIRQ_G, "INTG#" },
{ PIRQ_H, "INTH#" }, { PIRQ_H, "INTH#" },
{ PIRQ_MISC, "Misc" }, { PIRQ_MISC, "Misc" },
@@ -83,14 +86,19 @@ const static struct irq_idx_name irq_association[] = {
{ PIRQ_SCI, "SCI" }, { PIRQ_SCI, "SCI" },
{ PIRQ_SMBUS, "SMBUS" }, { PIRQ_SMBUS, "SMBUS" },
{ PIRQ_ASF, "ASF" }, { PIRQ_ASF, "ASF" },
{ PIRQ_HDA, "HDA" },
{ PIRQ_FC, "FC" },
{ PIRQ_PMON, "PerMon" }, { PIRQ_PMON, "PerMon" },
{ PIRQ_SD, "SD" }, { PIRQ_SD, "SD" },
{ PIRQ_SDIO, "SDIOt" }, { PIRQ_SDIO, "SDIO" },
{ PIRQ_EHCI, "EHCI" }, { PIRQ_CIR, "CIR" },
{ PIRQ_XHCI, "XHCI" }, { PIRQ_GPIOA, "GPIOa" },
{ PIRQ_GPIOB, "GPIOb" },
{ PIRQ_GPIOC, "GPIOc" },
{ PIRQ_SATA, "SATA" }, { PIRQ_SATA, "SATA" },
{ PIRQ_EMMC, "eMMC" },
{ PIRQ_GPP0, "GPP0" },
{ PIRQ_GPP1, "GPP1" },
{ PIRQ_GPP2, "GPP2" },
{ PIRQ_GPP3, "GPP3" },
{ PIRQ_GPIO, "GPIO" }, { PIRQ_GPIO, "GPIO" },
{ PIRQ_I2C0, "I2C0" }, { PIRQ_I2C0, "I2C0" },
{ PIRQ_I2C1, "I2C1" }, { PIRQ_I2C1, "I2C1" },
@@ -98,6 +106,10 @@ const static struct irq_idx_name irq_association[] = {
{ PIRQ_I2C3, "I2C3" }, { PIRQ_I2C3, "I2C3" },
{ PIRQ_UART0, "UART0" }, { PIRQ_UART0, "UART0" },
{ PIRQ_UART1, "UART1" }, { PIRQ_UART1, "UART1" },
{ PIRQ_I2C4, "I2C4" },
{ PIRQ_I2C5, "I2C5" },
{ PIRQ_UART2, "UART2" },
{ PIRQ_UART3, "UART3" },
}; };
const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
@@ -173,31 +185,6 @@ static void sb_enable_lpc(void)
pm_io_write8(PM_LPC_GATING, byte); pm_io_write8(PM_LPC_GATING, byte);
} }
static void sb_lpc_decode(void)
{
u32 tmp = 0;
/* Enable I/O decode to LPC bus */
tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
| DECODE_ENABLE_ADLIB_PORT;
/* Decode SIOs at 2E/2F and 4E/4F */
if (CONFIG(PICASSO_LEGACY_FREE))
tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
lpc_enable_decode(tmp);
}
static void sb_enable_cf9_io(void) static void sb_enable_cf9_io(void)
{ {
uint32_t reg = pm_read32(PM_DECODE_EN); uint32_t reg = pm_read32(PM_DECODE_EN);
@@ -262,72 +249,6 @@ void sb_read_mode(u32 mode)
& ~SPI_READ_MODE_MASK) | mode); & ~SPI_READ_MODE_MASK) | mode);
} }
static void setup_spread_spectrum(int *reboot)
{
uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
pm_write16(PWR_RESET_CFG, rstcfg);
uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
if (cntl1 & CG1PLL_FBDIV_TEST) {
printk(BIOS_DEBUG, "Spread spectrum is ready\n");
misc_write32(MISC_CGPLL_CONFIG1,
misc_read32(MISC_CGPLL_CONFIG1) |
CG1PLL_SPREAD_SPECTRUM_ENABLE);
return;
}
printk(BIOS_DEBUG, "Setting up spread spectrum\n");
uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
cfg6 &= ~CG1PLL_LF_MODE_MASK;
cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
misc_write32(MISC_CGPLL_CONFIG6, cfg6);
uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
cfg3 &= ~CG1PLL_REFDIV_MASK;
cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
cfg3 &= ~CG1PLL_FBDIV_MASK;
cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
misc_write32(MISC_CGPLL_CONFIG3, cfg3);
uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;
cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;
misc_write32(MISC_CGPLL_CONFIG5, cfg5);
uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;
cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;
cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;
cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)
& SS_STEP_SIZE_DSFRAC_MASK;
misc_write32(MISC_CGPLL_CONFIG4, cfg4);
rstcfg |= TOGGLE_ALL_PWR_GOOD;
pm_write16(PWR_RESET_CFG, rstcfg);
cntl1 |= CG1PLL_FBDIV_TEST;
misc_write32(MISC_CLK_CNTL1, cntl1);
*reboot = 1;
}
static void setup_misc(int *reboot)
{
/* Undocumented register */
uint32_t reg = misc_read32(0x50);
if (!(reg & BIT(16))) {
reg |= BIT(16);
misc_write32(0x50, reg);
*reboot = 1;
}
}
static void fch_smbus_init(void) static void fch_smbus_init(void)
{ {
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
@@ -340,28 +261,27 @@ static void fch_smbus_init(void)
} }
/* Before console init */ /* Before console init */
void bootblock_fch_early_init(void) void fch_pre_init(void)
{ {
int reboot = 0; /* Turn on LPC in case the PSP didn't use it. However, ensure all
* decoding is cleared as the PSP may have enabled decode paths. */
lpc_enable_rom();
sb_enable_lpc(); sb_enable_lpc();
lpc_enable_port80(); lpc_disable_decodes();
sb_lpc_decode();
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)
&& CONFIG(PICASSO_LPC_IOMUX))
lpc_enable_port80();
lpc_enable_spi_prefetch(); lpc_enable_spi_prefetch();
sb_init_spi_base(); sb_init_spi_base();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_disable_4dw_burst();
sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M,
SPI_SPEED_16M, SPI_SPEED_16M);
enable_acpimmio_decode(); enable_acpimmio_decode();
fch_smbus_init(); fch_smbus_init();
sb_enable_cf9_io(); sb_enable_cf9_io();
setup_spread_spectrum(&reboot);
setup_misc(&reboot);
if (reboot)
warm_reset();
sb_enable_legacy_io(); sb_enable_legacy_io();
enable_aoac_devices(); enable_aoac_devices();
sb_reset_i2c_slaves();
} }
static void print_num_status_bits(int num_bits, uint32_t status, static void print_num_status_bits(int num_bits, uint32_t status,
@@ -417,9 +337,10 @@ static void sb_print_pmxc0_status(void)
} }
/* After console init */ /* After console init */
void bootblock_fch_init(void) void fch_early_init(void)
{ {
sb_print_pmxc0_status(); sb_print_pmxc0_status();
i2c_soc_early_init();
} }
void sb_enable(struct device *dev) void sb_enable(struct device *dev)
@@ -430,6 +351,7 @@ void sb_enable(struct device *dev)
static void sb_init_acpi_ports(void) static void sb_init_acpi_ports(void)
{ {
u32 reg; u32 reg;
msr_t cst_addr;
/* We use some of these ports in SMM regardless of whether or not /* We use some of these ports in SMM regardless of whether or not
* ACPI tables are generated. Enable these ports indiscriminately. * ACPI tables are generated. Enable these ports indiscriminately.
@@ -439,8 +361,11 @@ static void sb_init_acpi_ports(void)
pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
/* CpuControl is in \_PR.CP00, 6 bytes */ /* CpuControl is in \_PR.CP00, 6 bytes */
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
wrmsr(CSTATE_BASE_REG, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */ /* APMC - SMI Command Port */
@@ -453,7 +378,6 @@ static void sb_init_acpi_ports(void)
*/ */
reg = pm_read32(PM_PCI_CTRL); reg = pm_read32(PM_PCI_CTRL);
reg |= FORCE_SLPSTATE_RETRY; reg |= FORCE_SLPSTATE_RETRY;
reg &= ~FORCE_STPCLK_RETRY;
pm_write32(PM_PCI_CTRL, reg); pm_write32(PM_PCI_CTRL, reg);
/* Disable SlpTyp feature */ /* Disable SlpTyp feature */