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soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP

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Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot.  Do the same
for the northbridge's IOAPIC base address.

Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson
2020-09-04 12:07:27 -06:00
parent 39a8040ddc
commit 39c64b0bdd
6 changed files with 47 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/amd/picasso/root_complex.c
View File

@ -12,6 +12,7 @@
#include <fsp/util.h>
#include <stdint.h>
#include <soc/memmap.h>
#include <soc/iomap.h>
/*
*
@ -72,6 +73,7 @@ static void read_resources(struct device *dev)
unsigned int idx = 0;
const struct hob_header *hob = fsp_get_hob_list();
const struct hob_resource *res;
struct resource *gnb_apic;
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@ -129,6 +131,12 @@ static void read_resources(struct device *dev)
printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
res->type);
}
/* GNB IOAPIC resource */
gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR);
gnb_apic->base = GNB_IO_APIC_ADDR;
gnb_apic->size = 0x00001000;
gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/* Used by \_SB.PCI0._CRS */