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soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs

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This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for
10-Core ID.

Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Gaggery Tsai
2020-01-08 15:22:13 -08:00
committed by Nico Huber
parent 06a078a067
commit 39e1f44f33
3 changed files with 8 additions and 2 deletions
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6
src/include/device/pci_ids.h
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@@ -3399,9 +3399,11 @@
#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51
#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60
#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55
#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53
#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35
#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B33
#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43
#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2 0x9B53
#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_4 0x9B63
#define PCI_DEVICE_ID_INTEL_CML_S_G0G1_2 0x9B73
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44