sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/guybrush: disable KBRSTEN

Browse Source 
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.

BUG=b:183340503
TEST=build

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kangheui Won
2021-03-23 14:56:31 +11:00
committed by Martin Roth
parent 6d837df908
commit 39ef890336
2 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/guybrush/mainboard.c
View File

@@ -1,9 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h> #include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <device/device.h> #include <device/device.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/southbridge.h>
#include <variant/ec.h> #include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
@@ -88,6 +90,16 @@ static void mainboard_configure_gpios(void)
{ {
size_t base_num_gpios, override_num_gpios; size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios;
u32 reg;
/*
* Disable KBRST feature
* KBRSTEN is set to 1 on reset and this causes system reset
* if GPIO 129 is configured as GPO_LOW.
* */
reg = pm_read8(PM_RST_CTRL1);
reg &= ~KBRSTEN;
pm_write8(PM_RST_CTRL1, reg);
base_gpios = variant_base_gpio_table(&base_num_gpios); base_gpios = variant_base_gpio_table(&base_num_gpios);
override_gpios = variant_override_gpio_table(&override_num_gpios); override_gpios = variant_override_gpio_table(&override_num_gpios);

1
src/soc/amd/cezanne/include/soc/southbridge.h
View File

@@ -54,6 +54,7 @@
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe #define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5) #define SLPTYPE_CONTROL_EN BIT(5)
#define KBRSTEN BIT(4)
#define PM_LPC_GATING 0xec #define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1) #define PM_LPC_A20_EN BIT(1)