nb/intel/pineview: Clean up code and comments
- Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
committed by
Patrick Georgi
Patrick Georgi
parent
099975debd
commit
39ff703aa9
@ -36,7 +36,7 @@
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#include "chip.h"
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#include "pineview.h"
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#define GTTSIZE (512*1024)
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#define GTTSIZE (512 * 1024)
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#define PGETBL2_CTL 0x20c4
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#define PGETBL2_1MB (1 << 8)
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@ -54,7 +54,7 @@
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ADPA_CRT_HOTPLUG_VOLREF_325MV | \
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ADPA_CRT_HOTPLUG_ENABLE)
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static struct resource *gtt_res = NULL;
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static struct resource *gtt_res = NULL;
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static struct resource *mmio_res = NULL;
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uintptr_t gma_get_gnvs_aslb(const void *gnvs)
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@ -126,8 +126,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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| ADPA_DPMS_ON);
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write32(mmio + 0x7041c, 0x0);
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@ -137,14 +136,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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write32(mmio + PIPESRC(1), 0x027f01df);
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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const u8 cr[25] = {
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0x5f, 0x4f, 0x50, 0x82, 0x55,
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0x81, 0xbf, 0x1f, 0x00, 0x4f,
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0x0d, 0x0e, 0x00, 0x00, 0x00,
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0x00, 0x9c, 0x8e, 0x8f, 0x28,
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0x1f, 0x96, 0xb9, 0xa3, 0xff,
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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for (i = 0; i < ARRAY_SIZE(cr); i++)
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vga_cr_write(i, cr[i]);
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// Disable screen memory to prevent garbage from appearing.
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@ -157,15 +158,14 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_VGA_MODE_DIS
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x400601
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);
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| 0x400601);
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mdelay(1);
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
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| DPLL_VGA_MODE_DIS
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| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
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| 0x400601
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);
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| 0x400601);
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write32(mmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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@ -173,8 +173,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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| ADPA_DPMS_ON);
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write32(mmio + HTOTAL(1), 0x031f027f);
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write32(mmio + HBLANK(1), 0x03170287);
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@ -183,23 +182,12 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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write32(mmio + VBLANK(1), 0x020401e7);
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write32(mmio + VSYNC(1), 0x01eb01e9);
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write32(mmio + HTOTAL(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(mmio + HBLANK(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(mmio + HSYNC(0),
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((hactive - 1) << 16)
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| (hactive - 1));
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write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + VBLANK(0), ((vactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + VSYNC(0),
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((vactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1));
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write32(mmio + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1));
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write32(mmio + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1));
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write32(mmio + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1));
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write32(mmio + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1));
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write32(mmio + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1));
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write32(mmio + PF_WIN_POS(0), 0);
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@ -228,8 +216,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON
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);
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| ADPA_DPMS_ON);
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write32(mmio + DSPFW3, 0x7f3f00c1);
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write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
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@ -246,16 +233,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
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temp = read32(mmio + PGETBL2_CTL);
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printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
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/* Clear interrupts. */
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write32(mmio + DEIIR, 0xffffffff);
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/* Clear interrupts */
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + SDEIIR, 0xffffffff);
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write32(mmio + IIR, 0xffffffff);
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write32(mmio + IMR, 0xffffffff);
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write32(mmio + EIR, 0xffffffff);
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write32(mmio + IIR, 0xffffffff);
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write32(mmio + IMR, 0xffffffff);
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write32(mmio + EIR, 0xffffffff);
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vga_textmode_init();
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/* Enable screen memory. */
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/* Enable screen memory */
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vga_sr_write(1, vga_sr_read(1) & ~0x20);
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}
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@ -269,7 +256,7 @@ static void gma_func0_init(struct device *dev)
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pci_write_config32(dev, PCI_COMMAND, reg32);
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if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
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/* PCI Init, will run VBIOS */
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/* PCI init, will run VBIOS */
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pci_dev_init(dev);
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} else {
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u32 physbase;
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@ -280,14 +267,14 @@ static void gma_func0_init(struct device *dev)
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/* Find base addresses */
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mmio_res = find_resource(dev, 0x10);
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gtt_res = find_resource(dev, 0x1c);
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pio_res = find_resource(dev, 0x14);
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gtt_res = find_resource(dev, 0x1c);
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pio_res = find_resource(dev, 0x14);
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physbase = pci_read_config32(dev, 0x5c) & ~0xf;
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if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
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if (vga_disable) {
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printk(BIOS_INFO,
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"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
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printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: "
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"skipping NATIVE graphic init\n");
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} else {
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printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
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mmio_res->base);
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@ -307,7 +294,7 @@ static void gma_func0_init(struct device *dev)
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const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
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{
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struct device *dev = pcidev_on_root(0x2, 0);
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struct device *dev = pcidev_on_root(2, 0);
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if (!dev) {
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printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n");
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return NULL;
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@ -316,10 +303,8 @@ const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
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return &chip->gfx;
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}
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static unsigned long
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gma_write_acpi_tables(struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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igd_opregion_t *opregion = (igd_opregion_t *)current;
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global_nvs_t *gnvs;
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@ -352,25 +337,25 @@ static struct pci_operations gma_pci_ops = {
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};
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static struct device_operations gma_func0_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.acpi_fill_ssdt_generator = 0,
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.init = gma_func0_init,
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.scan_bus = 0,
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.enable = 0,
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.ops_pci = &gma_pci_ops,
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.acpi_name = gma_acpi_name,
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.write_acpi_tables = gma_write_acpi_tables,
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.acpi_fill_ssdt_generator = NULL,
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.init = gma_func0_init,
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.scan_bus = NULL,
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.enable = NULL,
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.ops_pci = &gma_pci_ops,
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.acpi_name = gma_acpi_name,
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.write_acpi_tables = gma_write_acpi_tables,
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};
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static const unsigned short pci_device_ids[] =
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{
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0xa001, 0
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0xa001, 0,
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};
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static const struct pci_driver gma __pci_driver = {
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.ops = &gma_func0_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.ops = &gma_func0_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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