nb/intel/pineview: Clean up code and comments
- Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons
committed by
Patrick Georgi
Patrick Georgi
parent
099975debd
commit
39ff703aa9
@ -31,8 +31,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
return current;
|
||||
|
||||
max_buses = length >> 20;
|
||||
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
|
||||
pciexbar, 0x0, 0x0, max_buses - 1);
|
||||
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
|
||||
max_buses - 1);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
@ -20,6 +20,6 @@
|
||||
|
||||
void bootblock_early_northbridge_init(void)
|
||||
{
|
||||
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
|
||||
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
|
||||
CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
|
||||
}
|
||||
|
||||
@ -22,14 +22,10 @@
|
||||
#include <option.h>
|
||||
#include <types.h>
|
||||
|
||||
#define LPC PCI_DEV(0, 0x1f, 0)
|
||||
#define D0F0 PCI_DEV(0, 0, 0)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
#define PCI_GCFC 0xf0
|
||||
#define MCH_GCFGC 0xc8c
|
||||
#define CRCLK_PINEVIEW 0x02
|
||||
#define CDCLK_PINEVIEW 0x10
|
||||
#define MCH_HPLLVCO 0xc38
|
||||
#define CRCLK_PINEVIEW 0x02
|
||||
#define CDCLK_PINEVIEW 0x10
|
||||
|
||||
static void early_graphics_setup(void)
|
||||
{
|
||||
@ -40,17 +36,18 @@ static void early_graphics_setup(void)
|
||||
const struct device *d0f0 = pcidev_on_root(0, 0);
|
||||
const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
|
||||
|
||||
pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
|
||||
pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
|
||||
|
||||
/* vram size from CMOS option */
|
||||
/* Fetch VRAM size from CMOS option */
|
||||
if (get_option(®8, "gfx_uma_size") != CB_SUCCESS)
|
||||
reg8 = 0; /* 0 for 8MB */
|
||||
/* make sure no invalid setting is used */
|
||||
|
||||
/* Ensure the setting is valid */
|
||||
if (reg8 > 6)
|
||||
reg8 = 0;
|
||||
|
||||
/* Select 1M GTT */
|
||||
pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8)
|
||||
| ((reg8 + 3) << 4));
|
||||
pci_write_config16(HOST_BRIDGE, GGC, (1 << 8) | ((reg8 + 3) << 4));
|
||||
|
||||
printk(BIOS_SPEW, "Set GFX clocks...");
|
||||
reg16 = MCHBAR16(MCH_GCFGC);
|
||||
@ -61,10 +58,10 @@ static void early_graphics_setup(void)
|
||||
MCHBAR16(MCH_GCFGC) = reg16;
|
||||
|
||||
/* Graphics core */
|
||||
reg8 = MCHBAR8(MCH_HPLLVCO);
|
||||
reg8 = MCHBAR8(HPLLVCO);
|
||||
reg8 &= 0x7;
|
||||
|
||||
reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff;
|
||||
reg16 = pci_read_config16(GMCH_IGD, 0xcc) & ~0x1ff;
|
||||
|
||||
if (reg8 == 0x4) {
|
||||
/* 2666MHz */
|
||||
@ -77,60 +74,58 @@ static void early_graphics_setup(void)
|
||||
reg16 |= 0xad;
|
||||
}
|
||||
|
||||
pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16);
|
||||
pci_write_config16(GMCH_IGD, 0xcc, reg16);
|
||||
|
||||
pci_write_config8(PCI_DEV(0,2,0), 0x62,
|
||||
pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3);
|
||||
pci_write_config8(PCI_DEV(0,2,0), 0x62,
|
||||
pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2);
|
||||
pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) & ~0x3);
|
||||
pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) | 2);
|
||||
|
||||
if (config->use_crt) {
|
||||
/* Enable VGA */
|
||||
MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15);
|
||||
MCHBAR32_OR(DACGIOCTRL1, 1 << 15);
|
||||
} else {
|
||||
/* Disable VGA */
|
||||
MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15);
|
||||
MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15));
|
||||
}
|
||||
|
||||
if (config->use_lvds) {
|
||||
/* Enable LVDS */
|
||||
reg32 = MCHBAR32(0x3004);
|
||||
reg32 = MCHBAR32(LVDSICR2);
|
||||
reg32 &= ~0xf1000000;
|
||||
reg32 |= 0x90000000;
|
||||
MCHBAR32(0x3004) = reg32;
|
||||
MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9);
|
||||
reg32 |= 0x90000000;
|
||||
MCHBAR32(LVDSICR2) = reg32;
|
||||
MCHBAR32_OR(IOCKTRR1, 1 << 9);
|
||||
} else {
|
||||
/* Disable LVDS */
|
||||
MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25);
|
||||
MCHBAR32_OR(DACGIOCTRL1, 3 << 25);
|
||||
}
|
||||
|
||||
MCHBAR32(0xff4) = 0x0c6db8b5f;
|
||||
MCHBAR16(0xff8) = 0x24f;
|
||||
MCHBAR32(CICTRL) = 0xc6db8b5f;
|
||||
MCHBAR16(CISDCTRL) = 0x024f;
|
||||
|
||||
MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00;
|
||||
MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5);
|
||||
MCHBAR32_AND(DACGIOCTRL1, 0xffffff00);
|
||||
MCHBAR32_OR(DACGIOCTRL1, 1 << 5);
|
||||
|
||||
/* Legacy backlight control */
|
||||
pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c);
|
||||
pci_write_config8(GMCH_IGD, 0xf4, 0x4c);
|
||||
}
|
||||
|
||||
static void early_misc_setup(void)
|
||||
{
|
||||
MCHBAR32(0x30);
|
||||
MCHBAR32(0x30) = 0x21800;
|
||||
DMIBAR32(0x2c) = 0x86000040;
|
||||
MCHBAR32(HIT0);
|
||||
MCHBAR32(HIT0) = 0x00021800;
|
||||
DMIBAR32(HTBONUS1) = 0x86000040;
|
||||
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
|
||||
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
|
||||
|
||||
early_graphics_setup();
|
||||
|
||||
MCHBAR32(0x40);
|
||||
MCHBAR32(0x40) = 0x0;
|
||||
MCHBAR32(0x40);
|
||||
MCHBAR32(0x40) = 0x8;
|
||||
MCHBAR32(HIT4);
|
||||
MCHBAR32(HIT4) = 0;
|
||||
MCHBAR32(HIT4);
|
||||
MCHBAR32(HIT4) = 8;
|
||||
|
||||
pci_write_config8(LPC, 0x8, 0x1d);
|
||||
pci_write_config8(LPC, 0x8, 0x0);
|
||||
pci_write_config8(LPC_DEV, 0x08, 0x1d);
|
||||
pci_write_config8(LPC_DEV, 0x08, 0x00);
|
||||
RCBA32(0x3410) = 0x00020465;
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
|
||||
@ -138,41 +133,41 @@ static void early_misc_setup(void)
|
||||
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
|
||||
|
||||
RCBA32(0x3100) = 0x42210;
|
||||
RCBA32(0x3100) = 0x00042210;
|
||||
RCBA32(0x3108) = 0x10004321;
|
||||
RCBA32(0x310c) = 0x00214321;
|
||||
RCBA32(0x3110) = 0x1;
|
||||
RCBA32(0x3110) = 1;
|
||||
RCBA32(0x3140) = 0x01460132;
|
||||
RCBA32(0x3142) = 0x02370146;
|
||||
RCBA32(0x3144) = 0x32010237;
|
||||
RCBA32(0x3146) = 0x01463201;
|
||||
RCBA32(0x3148) = 0x146;
|
||||
RCBA32(0x3148) = 0x00000146;
|
||||
}
|
||||
|
||||
static void pineview_setup_bars(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
|
||||
pci_write_config8(D0F0, 0x8, 0x69);
|
||||
pci_write_config8(HOST_BRIDGE, 0x08, 0x69);
|
||||
|
||||
/* Set up all hardcoded northbridge BARs */
|
||||
pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
|
||||
pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
|
||||
pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
|
||||
pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
|
||||
pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1);
|
||||
pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1);
|
||||
pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1);
|
||||
pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
|
||||
|
||||
/* Set C0000-FFFFF to access RAM on both reads and writes */
|
||||
pci_write_config8(D0F0, PAM0, 0x30);
|
||||
pci_write_config8(D0F0, PAM1, 0x33);
|
||||
pci_write_config8(D0F0, PAM2, 0x33);
|
||||
pci_write_config8(D0F0, PAM3, 0x33);
|
||||
pci_write_config8(D0F0, PAM4, 0x33);
|
||||
pci_write_config8(D0F0, PAM5, 0x33);
|
||||
pci_write_config8(D0F0, PAM6, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
|
||||
pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
|
||||
pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
|
||||
|
||||
printk(BIOS_DEBUG, " done.\n");
|
||||
}
|
||||
|
||||
void pineview_early_initialization(void)
|
||||
void pineview_early_init(void)
|
||||
{
|
||||
/* Print some chipset specific information */
|
||||
printk(BIOS_DEBUG, "Intel Pineview northbridge\n");
|
||||
@ -180,10 +175,10 @@ void pineview_early_initialization(void)
|
||||
/* Setup all BARs required for early PCIe and raminit */
|
||||
pineview_setup_bars();
|
||||
|
||||
/* Miscellaneous set up */
|
||||
/* Miscellaneous setup */
|
||||
early_misc_setup();
|
||||
|
||||
/* Change port80 to LPC */
|
||||
/* Route port80 to LPC */
|
||||
RCBA32(GCS) &= (~0x04);
|
||||
RCBA32(0x2010) |= (1 << 10);
|
||||
}
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
#include "chip.h"
|
||||
#include "pineview.h"
|
||||
|
||||
#define GTTSIZE (512*1024)
|
||||
#define GTTSIZE (512 * 1024)
|
||||
|
||||
#define PGETBL2_CTL 0x20c4
|
||||
#define PGETBL2_1MB (1 << 8)
|
||||
@ -54,7 +54,7 @@
|
||||
ADPA_CRT_HOTPLUG_VOLREF_325MV | \
|
||||
ADPA_CRT_HOTPLUG_ENABLE)
|
||||
|
||||
static struct resource *gtt_res = NULL;
|
||||
static struct resource *gtt_res = NULL;
|
||||
static struct resource *mmio_res = NULL;
|
||||
|
||||
uintptr_t gma_get_gnvs_aslb(const void *gnvs)
|
||||
@ -126,8 +126,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
| ADPA_USE_VGA_HVPOLARITY
|
||||
| ADPA_VSYNC_CNTL_ENABLE
|
||||
| ADPA_HSYNC_CNTL_ENABLE
|
||||
| ADPA_DPMS_ON
|
||||
);
|
||||
| ADPA_DPMS_ON);
|
||||
|
||||
write32(mmio + 0x7041c, 0x0);
|
||||
|
||||
@ -137,14 +136,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
write32(mmio + PIPESRC(1), 0x027f01df);
|
||||
|
||||
vga_misc_write(0x67);
|
||||
const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
|
||||
0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
|
||||
0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
|
||||
0xff
|
||||
const u8 cr[25] = {
|
||||
0x5f, 0x4f, 0x50, 0x82, 0x55,
|
||||
0x81, 0xbf, 0x1f, 0x00, 0x4f,
|
||||
0x0d, 0x0e, 0x00, 0x00, 0x00,
|
||||
0x00, 0x9c, 0x8e, 0x8f, 0x28,
|
||||
0x1f, 0x96, 0xb9, 0xa3, 0xff,
|
||||
};
|
||||
vga_cr_write(0x11, 0);
|
||||
|
||||
for (i = 0; i <= 0x18; i++)
|
||||
for (i = 0; i < ARRAY_SIZE(cr); i++)
|
||||
vga_cr_write(i, cr[i]);
|
||||
|
||||
// Disable screen memory to prevent garbage from appearing.
|
||||
@ -157,15 +158,14 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
|
||||
| DPLL_VGA_MODE_DIS
|
||||
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
|
||||
| 0x400601
|
||||
);
|
||||
| 0x400601);
|
||||
|
||||
mdelay(1);
|
||||
write32(mmio + DPLL(0),
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
|
||||
| DPLL_VGA_MODE_DIS
|
||||
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
|
||||
| 0x400601
|
||||
);
|
||||
| 0x400601);
|
||||
|
||||
write32(mmio + ADPA, ADPA_DAC_ENABLE
|
||||
| ADPA_PIPE_A_SELECT
|
||||
@ -173,8 +173,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
| ADPA_USE_VGA_HVPOLARITY
|
||||
| ADPA_VSYNC_CNTL_ENABLE
|
||||
| ADPA_HSYNC_CNTL_ENABLE
|
||||
| ADPA_DPMS_ON
|
||||
);
|
||||
| ADPA_DPMS_ON);
|
||||
|
||||
write32(mmio + HTOTAL(1), 0x031f027f);
|
||||
write32(mmio + HBLANK(1), 0x03170287);
|
||||
@ -183,23 +182,12 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
write32(mmio + VBLANK(1), 0x020401e7);
|
||||
write32(mmio + VSYNC(1), 0x01eb01e9);
|
||||
|
||||
write32(mmio + HTOTAL(0),
|
||||
((hactive - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + HBLANK(0),
|
||||
((hactive - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + HSYNC(0),
|
||||
((hactive - 1) << 16)
|
||||
| (hactive - 1));
|
||||
|
||||
write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + VBLANK(0), ((vactive - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + VSYNC(0),
|
||||
((vactive - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1));
|
||||
write32(mmio + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1));
|
||||
write32(mmio + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1));
|
||||
write32(mmio + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1));
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
|
||||
@ -228,8 +216,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
| ADPA_USE_VGA_HVPOLARITY
|
||||
| ADPA_VSYNC_CNTL_ENABLE
|
||||
| ADPA_HSYNC_CNTL_ENABLE
|
||||
| ADPA_DPMS_ON
|
||||
);
|
||||
| ADPA_DPMS_ON);
|
||||
|
||||
write32(mmio + DSPFW3, 0x7f3f00c1);
|
||||
write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
|
||||
@ -246,16 +233,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
|
||||
temp = read32(mmio + PGETBL2_CTL);
|
||||
printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
|
||||
|
||||
/* Clear interrupts. */
|
||||
write32(mmio + DEIIR, 0xffffffff);
|
||||
/* Clear interrupts */
|
||||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
write32(mmio + IIR, 0xffffffff);
|
||||
write32(mmio + IMR, 0xffffffff);
|
||||
write32(mmio + EIR, 0xffffffff);
|
||||
write32(mmio + IIR, 0xffffffff);
|
||||
write32(mmio + IMR, 0xffffffff);
|
||||
write32(mmio + EIR, 0xffffffff);
|
||||
|
||||
vga_textmode_init();
|
||||
|
||||
/* Enable screen memory. */
|
||||
/* Enable screen memory */
|
||||
vga_sr_write(1, vga_sr_read(1) & ~0x20);
|
||||
}
|
||||
|
||||
@ -269,7 +256,7 @@ static void gma_func0_init(struct device *dev)
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
|
||||
/* PCI Init, will run VBIOS */
|
||||
/* PCI init, will run VBIOS */
|
||||
pci_dev_init(dev);
|
||||
} else {
|
||||
u32 physbase;
|
||||
@ -280,14 +267,14 @@ static void gma_func0_init(struct device *dev)
|
||||
|
||||
/* Find base addresses */
|
||||
mmio_res = find_resource(dev, 0x10);
|
||||
gtt_res = find_resource(dev, 0x1c);
|
||||
pio_res = find_resource(dev, 0x14);
|
||||
gtt_res = find_resource(dev, 0x1c);
|
||||
pio_res = find_resource(dev, 0x14);
|
||||
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
|
||||
if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
|
||||
if (vga_disable) {
|
||||
printk(BIOS_INFO,
|
||||
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
|
||||
printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: "
|
||||
"skipping NATIVE graphic init\n");
|
||||
} else {
|
||||
printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
|
||||
mmio_res->base);
|
||||
@ -307,7 +294,7 @@ static void gma_func0_init(struct device *dev)
|
||||
|
||||
const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
|
||||
{
|
||||
struct device *dev = pcidev_on_root(0x2, 0);
|
||||
struct device *dev = pcidev_on_root(2, 0);
|
||||
if (!dev) {
|
||||
printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n");
|
||||
return NULL;
|
||||
@ -316,10 +303,8 @@ const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
|
||||
return &chip->gfx;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
gma_write_acpi_tables(struct device *const dev,
|
||||
unsigned long current,
|
||||
struct acpi_rsdp *const rsdp)
|
||||
static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current,
|
||||
struct acpi_rsdp *const rsdp)
|
||||
{
|
||||
igd_opregion_t *opregion = (igd_opregion_t *)current;
|
||||
global_nvs_t *gnvs;
|
||||
@ -352,25 +337,25 @@ static struct pci_operations gma_pci_ops = {
|
||||
};
|
||||
|
||||
static struct device_operations gma_func0_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.acpi_fill_ssdt_generator = 0,
|
||||
.init = gma_func0_init,
|
||||
.scan_bus = 0,
|
||||
.enable = 0,
|
||||
.ops_pci = &gma_pci_ops,
|
||||
.acpi_name = gma_acpi_name,
|
||||
.write_acpi_tables = gma_write_acpi_tables,
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.acpi_fill_ssdt_generator = NULL,
|
||||
.init = gma_func0_init,
|
||||
.scan_bus = NULL,
|
||||
.enable = NULL,
|
||||
.ops_pci = &gma_pci_ops,
|
||||
.acpi_name = gma_acpi_name,
|
||||
.write_acpi_tables = gma_write_acpi_tables,
|
||||
};
|
||||
|
||||
static const unsigned short pci_device_ids[] =
|
||||
{
|
||||
0xa001, 0
|
||||
0xa001, 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver gma __pci_driver = {
|
||||
.ops = &gma_func0_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.ops = &gma_func0_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
|
||||
@ -20,5 +20,6 @@
|
||||
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
|
||||
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
|
||||
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
|
||||
#define DEFAULT_PMIOBAR 0x00000400
|
||||
|
||||
#endif /* PINEVIEW_IOMAP_H */
|
||||
|
||||
578
src/northbridge/intel/pineview/mchbar_regs.h
Normal file
578
src/northbridge/intel/pineview/mchbar_regs.h
Normal file
@ -0,0 +1,578 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2020 Angel Pons <th3fanbus@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __PINEVIEW_MCHBAR_REGS_H__
|
||||
#define __PINEVIEW_MCHBAR_REGS_H__
|
||||
|
||||
/* Indexed register helper macros */
|
||||
#define Gz(r, z) ((r) + ((z) * 0x100))
|
||||
#define Ly(r, y) ((r) + ((y) * 4))
|
||||
#define Cx(r, x) ((r) + ((x) * 0x400))
|
||||
#define CxLy(r, x, y) (((x) * 0x400) + (r) + ((y) * 4))
|
||||
|
||||
#define HTPACER 0x10
|
||||
#define HPWRCTL1 0x14
|
||||
#define HPWRCTL2 0x18
|
||||
#define HPWRCTL3 0x1C
|
||||
#define HTCLKGTCTL 0x20
|
||||
#define SLIMCFGTMG 0x24
|
||||
#define HTBONUS0 0x28
|
||||
#define HTBONUS1 0x2C
|
||||
#define HIT0 0x30
|
||||
#define HIT1 0x34
|
||||
#define HIT2 0x38
|
||||
#define HIT3 0x3C
|
||||
#define HIT4 0x40
|
||||
#define HIT5 0x44
|
||||
#define HICLKGTCTL 0x48
|
||||
#define HIBONUS 0x4C
|
||||
#define XTPR0 0x50
|
||||
#define XTPR1 0x54
|
||||
#define XTPR2 0x58
|
||||
#define XTPR3 0x5C
|
||||
#define XTPR4 0x60
|
||||
#define XTPR5 0x64
|
||||
#define XTPR6 0x68
|
||||
#define XTPR7 0x6C
|
||||
#define XTPR8 0x70
|
||||
#define XTPR9 0x74
|
||||
#define XTPR10 0x78
|
||||
#define XTPR11 0x7C
|
||||
#define XTPR12 0x80
|
||||
#define XTPR13 0x84
|
||||
#define XTPR14 0x88
|
||||
#define XTPR15 0x8C
|
||||
#define FCCREQ0SET 0x90
|
||||
#define FCCREQ1SET 0x98
|
||||
#define FCCREQ0MSK 0xA0
|
||||
#define FCCREQ1MSK 0xA8
|
||||
#define FCCDATASET 0xB0
|
||||
#define FCCDATAMSK 0xB8
|
||||
#define FCCCTL 0xC0
|
||||
#define CFGPOCTL1 0xC8
|
||||
#define CFGPOCTL2 0xCC
|
||||
#define NOACFGBUSCTL 0xD0
|
||||
#define POC 0xF4
|
||||
#define POCRL 0xFA
|
||||
#define CHDECMISC 0x111
|
||||
#define ZQCALQT 0x114
|
||||
#define SHC2REGI 0x115
|
||||
#define SHC2REGII 0x117
|
||||
#define WRWMCONFIG 0x120
|
||||
#define SHC2REGIII 0x124
|
||||
#define SHPENDREG 0x125
|
||||
#define SHPAGECTRL 0x127
|
||||
#define SHCMPLWRCMD 0x129
|
||||
#define SHC2MINTM 0x12A
|
||||
#define SHC2IDLETM 0x12C
|
||||
#define BYPACTSF 0x12D
|
||||
#define BYPKNRULE 0x12E
|
||||
#define SHBONUSREG 0x12F
|
||||
#define COMPCTRL1 0x130
|
||||
#define COMPCTRL2 0x134
|
||||
#define COMPCTRL3 0x138
|
||||
#define XCOMP 0x13C
|
||||
#define RCMEASBUFXOVR 0x140
|
||||
#define ACTXCOMP 0x144
|
||||
#define FINALXRCOMPRD 0x148
|
||||
#define SCOMP 0x14C
|
||||
#define SCMEASBUFOVR 0x150
|
||||
#define ACTSCOMP 0x154
|
||||
#define FINALXSCOMP 0x158
|
||||
#define XSCSTART 0x15A
|
||||
#define DCOMPRAW1 0x15C
|
||||
#define DCOMPRAW2 0x160
|
||||
#define DCMEASBUFOVR 0x164
|
||||
#define FINALDELCOMP 0x168
|
||||
#define OFREQDELSEL 0x16C
|
||||
#define XCOMPDFCTRL 0x170
|
||||
#define ZQCALCTRL 0x178
|
||||
#define XCOMPCMNBNS 0x17A
|
||||
#define PSMIOVR 0x17C
|
||||
#define CSHRPDCTL 0x180
|
||||
#define CSPDSLVWT 0x182
|
||||
#define CSHRPDSHFTOUTLO 0x184
|
||||
#define CSHRFIFOCTL 0x188
|
||||
#define CSHWRIOBONUS 0x189
|
||||
#define CSHRPDCTL2 0x18A
|
||||
#define CSHRWRIOMLNS 0x18C
|
||||
#define CSHRPDCTL3 0x18E
|
||||
#define CSHRPDCTL4 0x190
|
||||
#define CSHWRIOBONUS2 0x192
|
||||
#define CSHRMSTDYNDLLENB 0x193
|
||||
#define C0TXCCCMISC 0x194
|
||||
#define CSHRMSTRCTL0 0x198
|
||||
#define CSHRMSTRCTL1 0x19C
|
||||
#define CSHRDQSTXPGM 0x1A0
|
||||
#define CSHRDQSCMN 0x1A4
|
||||
#define CSHRDDR3CTL 0x1A8
|
||||
#define CSHRDIGANAOBSCTL 0x1B0
|
||||
#define CSHRMISCCTL 0x1B4
|
||||
#define CSHRMISCCTL1 0x1B6
|
||||
#define CSHRDFTCTL 0x1B8
|
||||
#define MPLLCTL 0x1C0
|
||||
#define MPLLDBG 0x1C4
|
||||
#define CREFPI 0x1C8
|
||||
#define CSHRDQSDQTX 0x1E0
|
||||
#define C0DRB0 0x200
|
||||
#define C0DRB1 0x202
|
||||
#define C0DRB2 0x204
|
||||
#define C0DRB3 0x206
|
||||
#define C0DRA01 0x208
|
||||
#define C0DRA23 0x20A
|
||||
#define CLOCKGATINGIII 0x210
|
||||
#define SHC3C4REG1 0x212
|
||||
#define SHC2REG4 0x216
|
||||
#define C0COREBONUS2 0x218
|
||||
#define C0GNT2LNCH3 0x21C
|
||||
#define C0GNT2LNCH1 0x220
|
||||
#define C0GNT2LNCH2 0x224
|
||||
#define C0MISCTM 0x228
|
||||
#define SHCYCTRKRDWRSFLV 0x22C
|
||||
#define SHCYCTRKRFSHSFLV 0x232
|
||||
#define SHCYCTRKCTLLVOV 0x234
|
||||
#define C0WRDPYN 0x239
|
||||
#define C0C2REG 0x23C
|
||||
#define C0STATRDADJV 0x23E
|
||||
#define C0LATCTRL 0x240
|
||||
#define C0BYPCTRL 0x241
|
||||
#define C0CWBCTRL 0x243
|
||||
#define C0ARBCTRL 0x244
|
||||
#define C0ADDCSCTRL 0x246
|
||||
#define C0STATRDCTRL 0x248
|
||||
#define C0RDFIFOCTRL 0x24C
|
||||
#define C0WRDATACTRL 0x24D
|
||||
#define C0CYCTRKPCHG 0x250
|
||||
#define C0CYCTRKACT 0x252
|
||||
#define C0CYCTRKWR 0x256
|
||||
#define C0CYCTRKRD 0x258
|
||||
#define C0CYCTRKREFR 0x25B
|
||||
#define C0CYCTRKPCHG2 0x25D
|
||||
#define C0RDQCTRL 0x25E
|
||||
#define C0CKECTRL 0x260
|
||||
#define C0CKEDELAY 0x264
|
||||
#define C0PWLRCTRL 0x265
|
||||
#define C0EPCONFIG 0x267
|
||||
#define C0REFRCTRL2 0x268
|
||||
#define C0REFRCTRL 0x269
|
||||
#define C0PVCFG 0x26F
|
||||
#define C0JEDEC 0x271
|
||||
#define C0ARBSPL 0x272
|
||||
#define C0DYNRDCTRL 0x274
|
||||
#define C0WRWMFLSH 0x278
|
||||
#define C0ECCERRLOG 0x280
|
||||
#define C0DITCTRL 0x288
|
||||
#define C0ODTRKCTRL 0x294
|
||||
#define C0ODT 0x298
|
||||
#define C0ODTCTRL 0x29C
|
||||
#define C0GTEW 0x2A0
|
||||
#define C0GTC 0x2A4
|
||||
#define C0DTPEW 0x2A8
|
||||
#define C0DTAEW 0x2AC
|
||||
#define C0DTC 0x2B4
|
||||
#define C0REFCTRL 0x2B8
|
||||
#define C0NOASEL 0x2BF
|
||||
#define C0COREBONUS 0x2C0
|
||||
#define C0DARBTEST 0x2C8
|
||||
#define CLOCKGATINGI 0x2D1
|
||||
#define MEMTDPCTW 0x2D4
|
||||
#define MTDPCTWHOTTH 0x2D8
|
||||
#define MTDPCTWHOTTH2 0x2DC
|
||||
#define MTDPCTWHOTTH3 0x2E0
|
||||
#define MTDPCTWHOTTH4 0x2E4
|
||||
#define MTDPCTWAUXTH 0x2E8
|
||||
#define MTDPCTWIRTH 0x2EC
|
||||
#define MTDPCCRWTWHOTTH 0x2F0
|
||||
#define MTDPCCRWTWHOTTH2 0x2F4
|
||||
#define MTDPCCRWTWHOTTH3 0x2F8
|
||||
#define MTDPCCRWTWHOTTH4 0x2FC
|
||||
#define MTDPCHOTTHINT 0x300
|
||||
#define MTDPCHOTTHINT2 0x304
|
||||
#define MTDPCTLAUXTNTINT 0x308
|
||||
#define MTDPCMISC 0x30C
|
||||
|
||||
/* RCOMP 0 */
|
||||
#define C0RCOMPCTRL0 0x31C
|
||||
#define C0RCOMPMULT0 0x320
|
||||
#define C0RCOMPOVR0 0x322
|
||||
#define C0RCOMPOSV0 0x326
|
||||
#define C0SCOMPVREF0 0x32A
|
||||
#define C0SCOMPOVR0 0x32C
|
||||
#define C0SCOMPOFF0 0x32E
|
||||
#define C0DCOMP0 0x330
|
||||
#define C0SLEWBASE0 0x332
|
||||
#define C0SLEWPULUT0 0x334
|
||||
#define C0SLEWPDLUT0 0x338
|
||||
#define C0DCOMPOVR0 0x33C
|
||||
#define C0DCOMPOFF0 0x340
|
||||
|
||||
/* RCOMP 2 */
|
||||
#define C0RCOMPCTRL2 0x374
|
||||
#define C0RCOMPMULT2 0x378
|
||||
#define C0RCOMPOVR2 0x37A
|
||||
#define C0RCOMPOSV2 0x37E
|
||||
#define C0SCOMPVREF2 0x382
|
||||
#define C0SCOMPOVR2 0x384
|
||||
#define C0SCOMPOFF2 0x386
|
||||
#define C0DCOMP2 0x388
|
||||
#define C0SLEWBASE2 0x38A
|
||||
#define C0SLEWPULUT2 0x38C
|
||||
#define C0SLEWPDLUT2 0x390
|
||||
#define C0DCOMPOVR2 0x394
|
||||
#define C0DCOMPOFF2 0x398
|
||||
|
||||
/* RCOMP 3 */
|
||||
#define C0RCOMPCTRL3 0x3A2
|
||||
#define C0RCOMPMULT3 0x3A6
|
||||
#define C0RCOMPOVR3 0x3A8
|
||||
#define C0RCOMPOSV3 0x3AC
|
||||
#define C0SCOMPVREF3 0x3B0
|
||||
#define C0SCOMPOVR3 0x3B2
|
||||
#define C0SCOMPOFF3 0x3B4
|
||||
#define C0DCOMP3 0x3B6
|
||||
#define C0SLEWBASE3 0x3B8
|
||||
#define C0SLEWPULUT3 0x3BA
|
||||
#define C0SLEWPDLUT3 0x3BE
|
||||
#define C0DCOMPOVR3 0x3C2
|
||||
#define C0DCOMPOFF3 0x3C6
|
||||
|
||||
/* RCOMP 4 */
|
||||
#define C0RCOMPCTRL4 0x3D0
|
||||
#define C0RCOMPMULT4 0x3D4
|
||||
#define C0RCOMPOVR4 0x3D6
|
||||
#define C0RCOMPOSV4 0x3DA
|
||||
#define C0SCOMPVREF4 0x3DE
|
||||
#define C0SCOMPOVR4 0x3E0
|
||||
#define C0SCOMPOFF4 0x3E2
|
||||
#define C0DCOMP4 0x3E4
|
||||
#define C0SLEWBASE4 0x3E6
|
||||
#define C0SLEWPULUT4 0x3E8
|
||||
#define C0SLEWPDLUT4 0x3EC
|
||||
#define C0DCOMPOVR4 0x3F0
|
||||
#define C0DCOMPOFF4 0x3F4
|
||||
|
||||
/* RCOMP 5 */
|
||||
#define C0RCOMPCTRL5 0x3FE
|
||||
#define C0RCOMPMULT5 0x402
|
||||
#define C0RCOMPOVR5 0x404
|
||||
#define C0RCOMPOSV5 0x408
|
||||
#define C0SCOMPVREF5 0x40C
|
||||
#define C0SCOMPOVR5 0x40E
|
||||
#define C0SCOMPOFF5 0x410
|
||||
#define C0DCOMP5 0x412
|
||||
#define C0SLEWBASE5 0x414
|
||||
#define C0SLEWPULUT5 0x416
|
||||
#define C0SLEWPDLUT5 0x41A
|
||||
#define C0DCOMPOVR5 0x41E
|
||||
#define C0DCOMPOFF5 0x422
|
||||
|
||||
/* RCOMP 6 */
|
||||
#define C0RCOMPCTRL6 0x42C
|
||||
#define C0RCOMPMULT6 0x430
|
||||
#define C0RCOMPOVR6 0x432
|
||||
#define C0RCOMPOSV6 0x436
|
||||
#define C0SCOMPVREF6 0x43A
|
||||
#define C0SCOMPOVR6 0x43C
|
||||
#define C0SCOMPOFF6 0x43E
|
||||
#define C0DCOMP6 0x440
|
||||
#define C0SLEWBASE6 0x442
|
||||
#define C0SLEWPULUT6 0x444
|
||||
#define C0SLEWPDLUT6 0x448
|
||||
#define C0DCOMPOVR6 0x44C
|
||||
#define C0DCOMPOFF6 0x450
|
||||
|
||||
#define C0ODTRECORDX 0x45A
|
||||
#define C0DQSODTRECORDX 0x462
|
||||
#define XCOMPSDR0BNS 0x4B0
|
||||
#define C0TXDQ0R0DLL 0x500
|
||||
#define C0TXDQ0R1DLL 0x501
|
||||
#define C0TXDQ0R2DLL 0x502
|
||||
#define C0TXDQ0R3DLL 0x503
|
||||
#define C0TXDQ1R0DLL 0x504
|
||||
#define C0TXDQ1R1DLL 0x505
|
||||
#define C0TXDQ1R2DLL 0x506
|
||||
#define C0TXDQ1R3DLL 0x507
|
||||
#define C0TXDQ2R0DLL 0x508
|
||||
#define C0TXDQ2R1DLL 0x509
|
||||
#define C0TXDQ2R2DLL 0x50A
|
||||
#define C0TXDQ2R3DLL 0x50B
|
||||
#define C0TXDQ3R0DLL 0x50C
|
||||
#define C0TXDQ3R1DLL 0x50D
|
||||
#define C0TXDQ3R2DLL 0x50E
|
||||
#define C0TXDQ3R3DLL 0x50F
|
||||
#define C0TXDQ4R0DLL 0x510
|
||||
#define C0TXDQ4R1DLL 0x511
|
||||
#define C0TXDQ4R2DLL 0x512
|
||||
#define C0TXDQ4R3DLL 0x513
|
||||
#define C0TXDQ5R0DLL 0x514
|
||||
#define C0TXDQ5R1DLL 0x515
|
||||
#define C0TXDQ5R2DLL 0x516
|
||||
#define C0TXDQ5R3DLL 0x517
|
||||
#define C0TXDQ6R0DLL 0x518
|
||||
#define C0TXDQ6R1DLL 0x519
|
||||
#define C0TXDQ6R2DLL 0x51A
|
||||
#define C0TXDQ6R3DLL 0x51B
|
||||
#define C0TXDQ7R0DLL 0x51C
|
||||
#define C0TXDQ7R1DLL 0x51D
|
||||
#define C0TXDQ7R2DLL 0x51E
|
||||
#define C0TXDQ7R3DLL 0x51F
|
||||
#define C0TXDQS0R0DLL 0x520
|
||||
#define C0TXDQS0R1DLL 0x521
|
||||
#define C0TXDQS0R2DLL 0x522
|
||||
#define C0TXDQS0R3DLL 0x523
|
||||
#define C0TXDQS1R0DLL 0x524
|
||||
#define C0TXDQS1R1DLL 0x525
|
||||
#define C0TXDQS1R2DLL 0x526
|
||||
#define C0TXDQS1R3DLL 0x527
|
||||
#define C0TXDQS2R0DLL 0x528
|
||||
#define C0TXDQS2R1DLL 0x529
|
||||
#define C0TXDQS2R2DLL 0x52A
|
||||
#define C0TXDQS2R3DLL 0x52B
|
||||
#define C0TXDQS3R0DLL 0x52C
|
||||
#define C0TXDQS3R1DLL 0x52D
|
||||
#define C0TXDQS3R2DLL 0x52E
|
||||
#define C0TXDQS3R3DLL 0x52F
|
||||
#define C0TXDQS4R0DLL 0x530
|
||||
#define C0TXDQS4R1DLL 0x531
|
||||
#define C0TXDQS4R2DLL 0x532
|
||||
#define C0TXDQS4R3DLL 0x533
|
||||
#define C0TXDQS5R0DLL 0x534
|
||||
#define C0TXDQS5R1DLL 0x535
|
||||
#define C0TXDQS5R2DLL 0x536
|
||||
#define C0TXDQS5R3DLL 0x537
|
||||
#define C0TXDQS6R0DLL 0x538
|
||||
#define C0TXDQS6R1DLL 0x539
|
||||
#define C0TXDQS6R2DLL 0x53A
|
||||
#define C0TXDQS6R3DLL 0x53B
|
||||
#define C0TXDQS7R0DLL 0x53C
|
||||
#define C0TXDQS7R1DLL 0x53D
|
||||
#define C0TXDQS7R2DLL 0x53E
|
||||
#define C0TXDQS7R3DLL 0x53F
|
||||
|
||||
#define C0DLLRCVCTLy(y) Ly(0x540, y)
|
||||
#define C0RXRCVyDLL(y) Ly(0x560, y)
|
||||
#define C0MISCCTLy(y) Ly(0x561, y)
|
||||
|
||||
#define C0TXCMD0DLL 0x580
|
||||
#define C0TXCK0DLL 0x581
|
||||
#define C0TXCK1DLL 0x582
|
||||
#define C0TXCMD1DLL 0x583
|
||||
#define C0TXCTL0DLL 0x584
|
||||
#define C0TXCTL1DLL 0x585
|
||||
#define C0TXCTL2DLL 0x586
|
||||
#define C0TXCTL3DLL 0x587
|
||||
#define C0RCVMISCCTL1 0x588
|
||||
#define C0RCVMISCCTL2 0x58C
|
||||
#define C0MCHODTMISCCTL1 0x590
|
||||
#define C0DYNSLVDLLEN 0x592
|
||||
#define C0CMDTX1 0x594
|
||||
#define C0CMDTX2 0x598
|
||||
#define C0CTLTX2 0x59C
|
||||
#define C0CKTX 0x5A0
|
||||
|
||||
#define C0DQRyTX1(y) Ly(0x5A4, y)
|
||||
#define C0DQSRyTX1(y) Ly(0x5B4, y)
|
||||
|
||||
#define C0DQSDQTX2 0x5C4
|
||||
|
||||
#define C0DQSDQRyTX3(y) Ly(0x5C8, y)
|
||||
|
||||
#define C0RSTCTL 0x5D8
|
||||
#define C0MISCCTL 0x5D9
|
||||
#define C0MISC2 0x5DA
|
||||
#define C0BONUS 0x5DB
|
||||
#define CMNDQFIFORST 0x5DC
|
||||
#define C0IOBUFACTCTL 0x5DD
|
||||
#define C0BONUS2 0x5DE
|
||||
#define C0DLLPIEN 0x5F0
|
||||
#define C0COARSEDLY0 0x5FA
|
||||
#define C0COARSEDLY1 0x5FC
|
||||
#define SHC3C4REG2 0x610
|
||||
#define SHC3C4REG3 0x612
|
||||
#define SHC3C4REG4 0x614
|
||||
#define SHCYCTRKCKEL 0x62C
|
||||
#define SHCYCTRKACTSFLV 0x630
|
||||
#define SHCYCTRKPCHGSFLV 0x634
|
||||
#define C1COREBONUS 0x6C0
|
||||
#define CLOCKGATINGII 0x6D1
|
||||
#define CLKXSSH2MCBYPPHAS 0x6D4
|
||||
#define CLKXSSH2MCBYP 0x6D8
|
||||
#define CLKXSSH2MCRDQ 0x6E0
|
||||
#define CLKXSSH2MCRDCST 0x6E8
|
||||
#define CLKXSSMC2H 0x6F0
|
||||
#define CLKXSSMC2HALT 0x6F8
|
||||
#define CLKXSSH2MD 0x700
|
||||
#define CLKXSSH2X2MD 0x708
|
||||
#define XSBFTCTL 0xB00
|
||||
#define XSBFTDRR 0xB04
|
||||
#define DACGIOCTRL1 0xB08
|
||||
#define CLKCFG 0xC00
|
||||
#define HMCCMP 0xC04
|
||||
#define HMCCMC 0xC08
|
||||
#define HMPLLO 0xC10
|
||||
#define CPCTL 0xC1C
|
||||
#define SSKPD 0xC20
|
||||
#define HMCCPEXT 0xC28
|
||||
#define HMDCPEXT 0xC2C
|
||||
#define CPBUP 0xC30
|
||||
#define HMBYPEXT 0xC34
|
||||
#define HPLLVCO 0xC38
|
||||
#define HPLLMONCTLA 0xC3C
|
||||
#define HPLLMONCTLB 0xC40
|
||||
#define HPLLMONCTLC 0xC44
|
||||
#define DPLLMONCTLA 0xC48
|
||||
#define DPLLMONCTLB 0xC4C
|
||||
#define HMDCMP 0xC50
|
||||
#define HMBYPCP 0xC54
|
||||
#define FLRCSSEL 0xC58
|
||||
#define DPLLMONCTLC 0xC5C
|
||||
#define MPLLMONCTLA 0xC60
|
||||
#define MPLLMONCTLB 0xC64
|
||||
#define MPLLMONCTLC 0xC68
|
||||
#define PLLFUSEOVR1 0xC70
|
||||
#define PLLFUSEOVR2 0xC74
|
||||
#define GCRCSCP 0xC80
|
||||
#define GCRCSCMP 0xC84
|
||||
#define GCRCSBYPCP 0xC86
|
||||
#define GCPLLO 0xC88
|
||||
#define MCH_GCFGC 0xC8C /* Note: 'GCFGC' is also defined in 'i915_reg.h' */
|
||||
#define GTDPCTSHOTTH 0xD00
|
||||
#define GTDPCTSHOTTH2 0xD04
|
||||
#define MTDPCTSHOTTH 0xD08
|
||||
#define MTDPCTSHOTTH2 0xD0C
|
||||
#define TSROTDPC 0xD10
|
||||
#define TSMISC 0xD14
|
||||
#define TEST_MC 0xE00
|
||||
#define APSMCTL 0xE04
|
||||
#define DFT_STRAP1 0xE08
|
||||
#define DFT_STRAP2 0xE0C
|
||||
#define CFGFUSE1 0xE10
|
||||
#define FUSEOVR1 0xE1C
|
||||
#define FUSEOVR2 0xE20
|
||||
#define FUSEOVR3 0xE24
|
||||
#define FUSEOVR4 0xE28
|
||||
#define NOA_RCOMP 0xE2C
|
||||
#define NOAR1 0xE30
|
||||
#define NOAR2 0xE34
|
||||
#define NOAR3 0xE38
|
||||
#define NOAR4 0xE3C
|
||||
#define NOAR5 0xE40
|
||||
#define NOAR6 0xE44
|
||||
#define NOAR7 0xE48
|
||||
#define NOAR8 0xE4C
|
||||
#define NOAR9 0xE50
|
||||
#define NOAR10 0xE54
|
||||
#define ODOC1 0xE58
|
||||
#define ODOC2 0xE5C
|
||||
#define ODOSTAT 0xE60
|
||||
#define ODOSTAT2 0xE64
|
||||
#define ODOSTAT3 0xE68
|
||||
#define DPLLMMC 0xE6C
|
||||
#define CFGFUSE2 0xE70
|
||||
#define FUSEOVR5 0xE78
|
||||
#define NOA_LVDSCTRL 0xE7C
|
||||
#define NOABUFMSK 0xE80
|
||||
#define PMCFG 0xF10
|
||||
#define PMSTS 0xF14
|
||||
#define PMMISC 0xF18
|
||||
#define GTDPCNME 0xF20
|
||||
#define GTDPCTW 0xF24
|
||||
#define GTDPCTW2 0xF28
|
||||
#define GTDPTWHOTTH 0xF2C
|
||||
#define GTDPTWHOTTH2 0xF30
|
||||
#define GTDPTWHOTTH3 0xF34
|
||||
#define GTDPTWHOTTH4 0xF38
|
||||
#define GTDPTWAUXTH 0xF3C
|
||||
#define GTDPCTWIRTH 0xF40
|
||||
#define GTDPCTWIRTH2NMISC 0xF44
|
||||
#define GTDPHTM 0xF48
|
||||
#define GTDPHTM2 0xF4C
|
||||
#define GTDPHTM3 0xF50
|
||||
#define GTDPHTM4 0xF54
|
||||
#define GTDPAHTMOV 0xF58
|
||||
#define GTDPAHTMOV2 0xF5C
|
||||
#define GTDPAHTMOV3 0xF60
|
||||
#define GTDPAHTMOV4 0xF64
|
||||
#define GTDPATM 0xF68
|
||||
#define GTDPCGC 0xF6C
|
||||
#define PCWBFC 0xF90
|
||||
#define SCWBFC 0xF98
|
||||
#define SBCTL 0xFA0
|
||||
#define SBCTL2 0xFA4
|
||||
#define PCWBPFC 0xFA8
|
||||
#define SBCTL3 0xFAC
|
||||
#define SBCLKGATECTRL 0xFB0
|
||||
#define SBBONUS0 0xFB4
|
||||
#define SBBONUS1 0xFB6
|
||||
#define PSMICTL 0xFC0
|
||||
#define PSMIMBASE 0xFC4
|
||||
#define PSMIMLIMIT 0xFC8
|
||||
#define PSMIDEBUG 0xFCC
|
||||
#define PSMICTL2 0xFD0
|
||||
#define PSMIRPLYNOAMAP 0xFD4
|
||||
#define CICGDIS 0xFF0
|
||||
#define CICTRL 0xFF4
|
||||
#define CISDCTRL 0xFF8
|
||||
#define CIMBSR 0xFFC
|
||||
#define GFXC3C4 0x1104
|
||||
#define PMDSLFRC 0x1108
|
||||
#define PMMSPMRES 0x110C
|
||||
#define PMCLKRC 0x1110
|
||||
#define PMPXPRC 0x1114
|
||||
#define PMC6CTL 0x111C
|
||||
#define PMICHTST 0x1120
|
||||
#define PMBAK 0x1124
|
||||
#define C0TXDQDQS0MISC 0x2800
|
||||
#define C0TXDQDQS1MISC 0x2804
|
||||
#define C0TXDQDQS2MISC 0x2808
|
||||
#define C0TXDQDQS3MISC 0x280C
|
||||
#define C0TXDQDQS4MISC 0x2810
|
||||
#define C0TXDQDQS5MISC 0x2814
|
||||
#define C0TXDQDQS6MISC 0x2818
|
||||
#define C0TXDQDQS7MISC 0x281C
|
||||
#define CSHRPDCTL5 0x2C00
|
||||
#define CSHWRIOBONUSX 0x2C02
|
||||
#define C0CALRESULT1 0x2C04
|
||||
#define C0CALRESULT2 0x2C08
|
||||
#define C0MODREFOFFSET1 0x2C0C
|
||||
#define C0MODREFOFFSET2 0x2C10
|
||||
#define C0SLVDLLOUTEN 0x2C14
|
||||
#define C0DYNSLVDLLEN2 0x2C15
|
||||
#define LVDSICR1 0x3000
|
||||
#define LVDSICR2 0x3004
|
||||
#define IOCKTRR1 0x3008
|
||||
#define IOCKTRR2 0x300C
|
||||
#define IOCKTRR3 0x3010
|
||||
#define IOCKTSTTR 0x3014
|
||||
#define IUB 0x3800
|
||||
#define BIR 0x3804
|
||||
#define TSC1 0x3808
|
||||
#define TSC2 0x3809
|
||||
#define TSS 0x380A
|
||||
#define TR 0x380B
|
||||
#define TSTTP 0x380C
|
||||
#define TCO 0x3812
|
||||
#define TST 0x3813
|
||||
#define THERM1 0x3814
|
||||
#define THERM3 0x3816
|
||||
#define TIS 0x381A
|
||||
#define TERRCMD 0x3820
|
||||
#define TSMICMD 0x3821
|
||||
#define TSCICMD 0x3822
|
||||
#define TSC3 0x3824
|
||||
#define EXTTSCS 0x3825
|
||||
#define C0THRMSTS 0x3830
|
||||
|
||||
#endif /* __PINEVIEW_MCHBAR_REGS_H__ */
|
||||
@ -32,7 +32,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
|
||||
{
|
||||
*base = 0;
|
||||
*len = 0;
|
||||
const pci_devfn_t dev = PCI_DEV(0,0,0);
|
||||
const pci_devfn_t dev = HOST_BRIDGE;
|
||||
u32 pciexbar = 0;
|
||||
u32 pciexbar_reg;
|
||||
u32 reg32;
|
||||
@ -49,7 +49,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
|
||||
|
||||
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
|
||||
|
||||
// MMCFG not supported or not enabled.
|
||||
/* MMCFG not supported or not enabled */
|
||||
if (!(pciexbar_reg & (1 << 0))) {
|
||||
printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
|
||||
return 0;
|
||||
@ -72,9 +72,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
|
||||
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
|
||||
u32 decode_igd_memory_size(const u32 gms)
|
||||
{
|
||||
const u32 gmssize[] = {
|
||||
0, 1, 4, 8, 16, 32, 48, 64, 128, 256
|
||||
};
|
||||
const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256};
|
||||
|
||||
if (gms > 9) {
|
||||
printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n");
|
||||
@ -86,9 +84,7 @@ u32 decode_igd_memory_size(const u32 gms)
|
||||
/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */
|
||||
u32 decode_igd_gtt_size(const u32 gsm)
|
||||
{
|
||||
const u8 gsmsize[] = {
|
||||
0, 1, 0, 0,
|
||||
};
|
||||
const u8 gsmsize[] = {0, 1, 0, 0};
|
||||
|
||||
if (gsm > 3) {
|
||||
printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n");
|
||||
@ -118,43 +114,42 @@ static u32 decode_tseg_size(const u32 esmramc)
|
||||
|
||||
static size_t northbridge_get_tseg_size(void)
|
||||
{
|
||||
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
|
||||
const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
|
||||
return decode_tseg_size(esmramc);
|
||||
}
|
||||
|
||||
static uintptr_t northbridge_get_tseg_base(void)
|
||||
{
|
||||
return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
|
||||
return pci_read_config32(HOST_BRIDGE, TSEG);
|
||||
}
|
||||
|
||||
|
||||
/* Depending of UMA and TSEG configuration, TSEG might start at any
|
||||
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
|
||||
* CBMEM top downwards to 4 MiB boundary.
|
||||
/*
|
||||
* Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
|
||||
* As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
|
||||
*/
|
||||
void *cbmem_top_chipset(void)
|
||||
{
|
||||
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
|
||||
return (void *) top_of_ram;
|
||||
return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
|
||||
|
||||
}
|
||||
|
||||
void smm_region(uintptr_t *start, size_t *size)
|
||||
{
|
||||
*start = northbridge_get_tseg_base();
|
||||
*size = northbridge_get_tseg_size();
|
||||
*size = northbridge_get_tseg_size();
|
||||
}
|
||||
|
||||
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||
{
|
||||
uintptr_t top_of_ram;
|
||||
|
||||
/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
|
||||
* RAM to cover both cbmem as the TSEG region.
|
||||
/*
|
||||
* Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
|
||||
* CBMEM and the TSEG region.
|
||||
*/
|
||||
top_of_ram = (uintptr_t)cbmem_top();
|
||||
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
|
||||
MTRR_TYPE_WRBACK);
|
||||
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
|
||||
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
||||
postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
|
||||
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
|
||||
MTRR_TYPE_WRBACK);
|
||||
}
|
||||
|
||||
@ -25,7 +25,8 @@
|
||||
#include <northbridge/intel/pineview/pineview.h>
|
||||
#include <cpu/intel/smm_reloc.h>
|
||||
|
||||
/* Reserve everything between A segment and 1MB:
|
||||
/*
|
||||
* Reserve everything between A segment and 1MB:
|
||||
*
|
||||
* 0xa0000 - 0xbffff: legacy VGA
|
||||
* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
|
||||
@ -40,13 +41,14 @@ static void add_fixed_resources(struct device *dev, int index)
|
||||
resource = new_resource(dev, index++);
|
||||
resource->base = (resource_t) 0xfed00000;
|
||||
resource->size = (resource_t) 0x00100000;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
|
||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
resource->flags = IORESOURCE_MEM
|
||||
| IORESOURCE_RESERVE
|
||||
| IORESOURCE_FIXED
|
||||
| IORESOURCE_STORED
|
||||
| IORESOURCE_ASSIGNED;
|
||||
|
||||
mmio_resource(dev, index++, legacy_hole_base_k,
|
||||
(0xc0000 >> 10) - legacy_hole_base_k);
|
||||
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
|
||||
(0x100000 - 0xc0000) >> 10);
|
||||
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
|
||||
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
|
||||
}
|
||||
|
||||
static void mch_domain_read_resources(struct device *dev)
|
||||
@ -72,11 +74,10 @@ static void mch_domain_read_resources(struct device *dev)
|
||||
tolud <<= 16;
|
||||
|
||||
/* Top of Memory - does not account for any UMA */
|
||||
tom = pci_read_config16(mch, TOM) & 0x1ff;
|
||||
tom = pci_read_config16(mch, TOM) & 0x01ff;
|
||||
tom <<= 27;
|
||||
|
||||
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",
|
||||
touud, tolud, tom);
|
||||
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", touud, tolud, tom);
|
||||
|
||||
tomk = tolud >> 10;
|
||||
|
||||
@ -106,15 +107,14 @@ static void mch_domain_read_resources(struct device *dev)
|
||||
delta_cbmem = tomk - cbmem_topk;
|
||||
tomk -= delta_cbmem;
|
||||
|
||||
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n",
|
||||
delta_cbmem);
|
||||
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem);
|
||||
|
||||
/* Report the memory regions */
|
||||
ram_resource(dev, index++, 0, 640);
|
||||
ram_resource(dev, index++, 768, tomk - 768);
|
||||
reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek);
|
||||
reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek);
|
||||
reserved_ram_resource(dev, index++, igd_basek, gms_sizek);
|
||||
reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek);
|
||||
reserved_ram_resource(dev, index++, igd_basek, gms_sizek);
|
||||
reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem);
|
||||
|
||||
/*
|
||||
@ -125,12 +125,13 @@ static void mch_domain_read_resources(struct device *dev)
|
||||
if (touud > top32memk) {
|
||||
ram_resource(dev, index++, top32memk, touud - top32memk);
|
||||
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
|
||||
(touud - top32memk) >> 10);
|
||||
(touud - top32memk) >> 10);
|
||||
}
|
||||
|
||||
if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
|
||||
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
|
||||
"size=0x%x\n", pcie_config_base, pcie_config_size);
|
||||
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
|
||||
pcie_config_base, pcie_config_size);
|
||||
|
||||
fixed_mem_resource(dev, index++, pcie_config_base >> 10,
|
||||
pcie_config_size >> 10, IORESOURCE_RESERVE);
|
||||
}
|
||||
@ -185,12 +186,12 @@ static const char *northbridge_acpi_name(const struct device *dev)
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = mch_domain_read_resources,
|
||||
.set_resources = mch_domain_set_resources,
|
||||
.init = mch_domain_init,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.read_resources = mch_domain_read_resources,
|
||||
.set_resources = mch_domain_set_resources,
|
||||
.init = mch_domain_init,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.acpi_fill_ssdt_generator = generate_cpu_entries,
|
||||
.acpi_name = northbridge_acpi_name,
|
||||
.acpi_name = northbridge_acpi_name,
|
||||
};
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
|
||||
@ -31,6 +31,7 @@
|
||||
#define SYSINFO_DIMM_X8DDS 0x06
|
||||
|
||||
/* Device 0:0.0 PCI configuration space (Host Bridge) */
|
||||
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
|
||||
|
||||
#define EPBAR 0x40
|
||||
#define MCHBAR 0x48
|
||||
@ -38,9 +39,9 @@
|
||||
#define DMIBAR 0x68
|
||||
#define PMIOBAR 0x78
|
||||
|
||||
#define GGC 0x52 /* GMCH Graphics Control */
|
||||
#define GGC 0x52 /* GMCH Graphics Control */
|
||||
|
||||
#define DEVEN 0x54 /* Device Enable */
|
||||
#define DEVEN 0x54 /* Device Enable */
|
||||
#define DEVEN_D0F0 (1 << 0)
|
||||
#define DEVEN_D1F0 (1 << 1)
|
||||
#define DEVEN_D2F0 (1 << 3)
|
||||
@ -84,9 +85,10 @@
|
||||
|
||||
/* Device 0:1.0 PCI configuration space (PCI Express) */
|
||||
|
||||
#define PEGSTS 0x214 /* 32bit */
|
||||
#define PEGSTS 0x214 /* 32 bits */
|
||||
|
||||
/* Device 0:2.0 PCI configuration space (Graphics Device) */
|
||||
/* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */
|
||||
#define GMCH_IGD PCI_DEV(0, 2, 0)
|
||||
|
||||
#define GMADR 0x18
|
||||
#define GTTADR 0x1c
|
||||
@ -98,15 +100,28 @@
|
||||
* MCHBAR
|
||||
*/
|
||||
|
||||
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
|
||||
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
|
||||
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */
|
||||
#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
|
||||
#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
|
||||
#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
|
||||
#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
|
||||
#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
|
||||
#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
|
||||
#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
|
||||
#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
|
||||
#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
|
||||
|
||||
/* As there are many registers, define them on a separate file */
|
||||
|
||||
#include "mchbar_regs.h"
|
||||
|
||||
/*
|
||||
* EPBAR - Egress Port Root Complex Register Block
|
||||
*/
|
||||
|
||||
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
|
||||
|
||||
@ -114,7 +129,7 @@
|
||||
* DMIBAR
|
||||
*/
|
||||
|
||||
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
|
||||
|
||||
@ -229,7 +244,7 @@ struct sysinfo {
|
||||
u8 mvco4x; /* 0 (8x) or 1 (4x) */
|
||||
};
|
||||
|
||||
void pineview_early_initialization(void);
|
||||
void pineview_early_init(void);
|
||||
u32 decode_igd_memory_size(const u32 gms);
|
||||
u32 decode_igd_gtt_size(const u32 gsm);
|
||||
u8 decode_pciebar(u32 *const base, u32 *const len);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -13,10 +13,6 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* Platform has no romstage entry point under mainboard directory,
|
||||
* so this one is named with prefix mainboard.
|
||||
*/
|
||||
|
||||
#include <timestamp.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ops.h>
|
||||
@ -32,7 +28,7 @@
|
||||
|
||||
static void rcba_config(void)
|
||||
{
|
||||
/* Set up virtual channel 0 */
|
||||
/* Set up Virtual Channel 0 */
|
||||
RCBA32(0x0014) = 0x80000001;
|
||||
RCBA32(0x001c) = 0x03128010;
|
||||
}
|
||||
@ -41,8 +37,7 @@ __weak void mb_pirq_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
#define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0)
|
||||
|
||||
/* The romstage entry point for this platform is not mainboard-specific, hence the name. */
|
||||
void mainboard_romstage_entry(void)
|
||||
{
|
||||
u8 spd_addrmap[4] = {};
|
||||
@ -51,11 +46,9 @@ void mainboard_romstage_entry(void)
|
||||
|
||||
enable_lapic();
|
||||
|
||||
/* Perform some early chipset initialization required
|
||||
* before RAM initialization can work
|
||||
*/
|
||||
/* Do some early chipset init, necessary for RAM init to work */
|
||||
i82801gx_early_init();
|
||||
pineview_early_initialization();
|
||||
pineview_early_init();
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
@ -64,7 +57,7 @@ void mainboard_romstage_entry(void)
|
||||
if (s3resume) {
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
} else {
|
||||
if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
|
||||
if (MCHBAR32(PMSTS) & (1 << 8)) /* HOT RESET */
|
||||
boot_path = BOOT_PATH_RESET;
|
||||
else
|
||||
boot_path = BOOT_PATH_NORMAL;
|
||||
|
||||
Reference in New Issue
Block a user