diff --git a/.gitignore b/.gitignore index ed667765fb..2fabfeef4b 100644 --- a/.gitignore +++ b/.gitignore @@ -97,7 +97,6 @@ util/cbfstool/ifwitool util/cbfstool/rmodtool util/cbmem/.dependencies util/cbmem/cbmem -util/dumpmmcr/dumpmmcr util/ectool/ectool util/futility/futility util/genprof/genprof @@ -106,16 +105,14 @@ util/ifdtool/ifdtool util/intelmetool/intelmetool util/inteltool/.dependencies util/inteltool/inteltool +util/intelp2m/intelp2m +util/intelp2m/generate/gpio.h util/intelvbttool/intelvbttool -util/k8resdump/k8resdump -util/lbtdump/lbtdump -util/mptable/mptable util/msrtool/Makefile util/msrtool/Makefile.deps util/msrtool/msrtool util/nvramtool/.dependencies util/nvramtool/nvramtool -util/optionlist/Options.wiki util/pmh7tool/pmh7tool util/runfw/googlesnow util/superiotool/superiotool @@ -123,6 +120,8 @@ util/vgabios/testbios util/autoport/autoport util/kbc1126/kbc1126_ec_dump util/kbc1126/kbc1126_ec_insert +util/spd_tools/*/gen_spd +util/spd_tools/*/gen_part_id Documentation/*.aux Documentation/*.idx diff --git a/.gitmodules b/.gitmodules index 2a9c60f8bb..0ed79be37c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -51,3 +51,10 @@ url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty +[submodule "3rdparty/intel-sec-tools"] + path = 3rdparty/intel-sec-tools + url = ../9esec-security-tooling.git +[submodule "3rdparty/stm"] + path = 3rdparty/stm + url = ../STM + branch = stmpe diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 1ac6d42bf3..e393a885c8 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 1ac6d42bf336af639ae849933cbb818e51b1ffd1 +Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index ace23683be..a4c979ade4 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit ace23683beb81354d6edbc61c087ab8c384d0631 +Subproject commit a4c979ade4438dfdd69c1b6e23b64e88eb648183 diff --git a/3rdparty/blobs b/3rdparty/blobs index bbe5d99780..1aff9c32eb 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit bbe5d99780d2d085e92d9bae2c0f7b6787419d72 +Subproject commit 1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21 diff --git a/3rdparty/fsp b/3rdparty/fsp index 2263d48a00..eb25f19ef7 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 2263d48a006d8653df1fc742c3f7d5ffd6b75d68 +Subproject commit eb25f19ef7fbe88fb207c6896a37a2035bba9bc5 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 33b7b2f381..0e4288f81f 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 33b7b2f3817e362111cd91910026ab8907f21710 +Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools new file mode 160000 index 0000000000..a86ff5d400 --- /dev/null +++ b/3rdparty/intel-sec-tools @@ -0,0 +1 @@ +Subproject commit a86ff5d400983d685d4389c07433452c7a503300 diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 126fef6b99..6b7fe498eb 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 126fef6b996237403039aa603945fc4caa75c8d6 +Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 diff --git a/3rdparty/stm b/3rdparty/stm new file mode 160000 index 0000000000..1f3258261a --- /dev/null +++ b/3rdparty/stm @@ -0,0 +1 @@ +Subproject commit 1f3258261a4f4d6c60ec4447c7a03acf2509b984 diff --git a/3rdparty/vboot b/3rdparty/vboot index 68de90c7e2..4c523ed10f 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 68de90c7e2f4a27d3a76489199176d2ab8f56de1 +Subproject commit 4c523ed10f25de872ac0513ebd6ca53d3970b9de diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index f5546d18d5..11d8a4f77b 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -5,16 +5,19 @@ This section contains documentation about coreboot on x86 architecture. * [x86 PAE support](pae.md) ## State of x86_64 support -At the moment there's no single board that supports x86_64 or to be exact -`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`. +At the moment there's only experimental x86_64 support. +The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support +*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*. -In order to add support for x86_64 the following assumptions are made: +In order to add support for x86_64 the following assumptions were made: * The CPU supports long mode * All memory returned by malloc must be below 4GiB in physical memory * All code that is to be run must be below 4GiB in physical memory * The high dword of pointers is always zero * The reference implementation is qemu * The CPU supports 1GiB hugepages +* x86 payloads are loaded below 4GiB in physical memory and are jumped + to in *protected mode* ## Assuptions for all stages using the reference implementation * 0-4GiB are identity mapped using 2MiB-pages as WB @@ -37,18 +40,16 @@ The page tables contains the following structure: At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. -## Steps to add basic support for x86_64 -* Add x86_64 toolchain support - *DONE* -* Fix compilation errors - *DONE* -* Fix linker errors - *TODO* -* Add x86_64 rmodule support - *DONE* -* Add x86_64 exception handlers - *DONE* -* Setup page tables for long mode - *DONE* -* Add assembly code for long mode - *DONE* -* Add assembly code for SMM - *DONE* -* Add assembly code for postcar stage - *TODO* -* Add assembly code to return to protected mode - *TODO* -* Implement reference code for mainboard `emulation/qemu-q35` - *TODO* +## Basic x86_64 support +Basic support for x86_64 has been implemented for QEMU mainboard target. + +## Reference implementation +The reference implementation is +* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md) +* [QEMU Q35](../../mainboard/emulation/qemu-q35.md) + +## TODO +* Identity map memory above 4GiB in ramstage ## Future work diff --git a/Documentation/community/language_style.md b/Documentation/community/language_style.md new file mode 100644 index 0000000000..97f9601286 --- /dev/null +++ b/Documentation/community/language_style.md @@ -0,0 +1,136 @@ +# Language style + +Following our [Code of Conduct](code_of_conduct.md) the project aims to +be a space where people are considerate in natural language communication: + +There are terms in computing that were probably considered benign when +introduced but are uncomfortable to some. The project aims to de-emphasize +such terms in favor of alternatives that are at least as expressive - +but often manage to be even more descriptive. + +## Political Correctness + +A common thread in discussions was that the project merely follows some +fad, or that this is a "political correctness" measure, designed to please +one particular "team". While the project doesn't exist in a vacuum and +so there are outside influences on project members, the proposal wasn't +made with the purpose of demonstrating allegiance to any given cause - +except one: + +There are people who feel uncomfortable with some terms being used, +_especially_ when that use takes them out of their grave context +(e.g. slave when discussing slavery) and applies them to a rather benign +topic (e.g. coordination of multiple technical systems), taking away +the gravity of the term. + +That gets especially jarring when people aren't exposed to such terms +in abstract sociological discussions but when they stand for real issues +they encountered. + +When having to choose between using a well-established term that +affects people negatively who could otherwise contribute more happily +and undisturbed or an alternative just-as-good term that doesn't, the +decision should be simple. + +## Token gesture + +The other major point of contention is that such decisions are a token +gesture that doesn't change anything. It's true: No slave is freed +because coreboot rejects the use of the word. + +coreboot is ambitious enough as-is, in that the project offers +an alternative approach to firmware, sometimes against the vested +interests (and deep pockets) of the leaders of a multi-billion dollar +industry. Changing the preferred vocabulary isn't another attempt at +changing the world, it's one thing we do to try to make coreboot (and +coreboot only) a comfortable environment for everybody. + +## For everybody + +For everybody, but with a qualifier: We have certain community etiquette, +and we define some behavior we don't accept in our community, both +detailed in the Code of Conduct. + +Other than that, we're trying to accommodate people: The CoC lays out +that language should be interpreted as friendly by default, and to be +graceful in light of accidents. This also applies to the use of terms +that the project tries to avoid: The consequence of the use of such +terms (unless obviously employed to provoke a reaction - in that case, +please contact the arbitration team as outlined in the Code of Conduct) +should be a friendly reminder. The project is slow to sanction and that +won't change just because the wrong kind of words is used. + +## Interfacing with the world + +The project doesn't exist in a vacuum, and that also applies to the choice +of words made by other initiatives in low-level technology. When JEDEC +calls the participants of a SPI transaction "master" and "slave", there's +little we can do about that. We _could_ decide to use different terms, +but that wouldn't make things easier but harder, because such a deliberate +departure means that the original terms (and their original use) gain +lots of visibility every time (so there's no practical advantage) while +adding confusion, and therefore even more attention, to that situation. + +Sometimes there are abbreviations that can be used as substitutes, +and in that case the recommendation is to do that. + +As terms that we found to be best avoided are replaced in such +initiatives, we can follow up. Members of the community with leverage +in such organizations are encouraged to raise the concern there. + +## Dealing with uses + +There are existing uses in our documentation and code. When we decide to +retire a term that doesn't mean that everybody is supposed to stop doing +whatever they're doing and spend their time on purging terms. Instead, +ongoing development should look for alternatives (and so this could come +up in review). + +People can go through existing code and docs and sort out older instances, +and while that's encouraged it's no "stop the world" event. Changes +in flight in review may still be merged with such terms intact, but if +there's more work required for other reasons, we'd encourage moving away +from such terms. + +This document has a section on retired terms, presenting the rationale +as well as alternative terms that could be used instead. The main goal is +to be expressive: There's no point in just picking any alternative term, +choose something that explains the purpose well. + +As mentioned, missteps will happen. Point them out, but assume no ill +intent for as long as you can manage. + +## Discussing words to remove from active use + +There ought to be some process when terminology is brought up as a +negative to avoid. Do not to tell people that "they're feeling wrong" +when they have a negative reaction to certain terms, but also try to +avoid being offended for the sake of others. + +When bringing up a term, on the project's mailing list or, if you don't +feel safe doing that, by contacting the arbitration team, explain what's +wrong with the term and offer alternatives for uses within coreboot. + +With a term under discussion, see if there's particular value for us to +continue using the term (maybe in limited situations, like continuing +to use "slave" in SPI related code). + +Once the arbitration team considers the topic discussed completely and +found a consensus, it will present a decision in a leadership meeting. It +should explain why a term should or should not be used and in the latter +case offer alternatives. These decisions shall then be added to this +document. + +## Retired terminology + +### slave + +Replacing this term for something else had the highest approval rating +in early discussions, so it seems pretty universally considered a bad +choice and therefore should be avoided where possible. + +An exception is made where it's a term used in current standards and data +sheets: Trying to "hide" the term in such cases only puts a spotlight +on it every time code and data sheet are compared. + +Alternatives: subordinate, secondary, follower diff --git a/Documentation/conf.py b/Documentation/conf.py index f82fa0e182..3180fd9720 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -48,7 +48,7 @@ try: except ImportError: print("Error: Please install sphinxcontrib.ditaa for ASCII art conversion\n") else: - extensions += 'sphinxcontrib.ditaa' + extensions += ['sphinxcontrib.ditaa'] # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 59f675a2ff..4547f919ce 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -43,15 +43,42 @@ employer is aware and you are authorized to submit the code. For clarification, see the Developer's Certificate of Origin in the coreboot [Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). -* Let non-trivial patches sit in a review state for at least 24 hours -before submission. Remember that there are coreboot developers in timezones -all over the world, and everyone should have a chance to contribute. -Trivial patches would be things like whitespace changes or spelling fixes, -in general those that don’t impact the final binary output. The -24-hour period would start at submission, and would be restarted at any -update which significantly changes any part of the patch. Patches can be -'Fast-tracked' and submitted in under 24 hours with the agreement of at -least 3 +2 votes. +* In general, patches should remain open for review for at least 24 hours +since the last significant modification to the change. The purpose is to +let coreboot developers around the world have a chance to review. Complex +reworks, even if they don't change the purpose of the patch but the way +it's implemented, should restart the wait period. + +* A change can go in without the wait period if its purpose is to fix +a recently-introduced issue (build, boot or OS-level compatibility, not +necessarily identified by coreboot.org facilities). Its commit message +has to explain what change introduced the problem and the nature of +the problem so that the emergency need becomes apparent. The change +itself should be as limited in scope and impact as possible to make it +simple to assess the impact. Such a change can be merged early with 3 +Code-Review+2. For emergency fixes that affect a single project (SoC, +mainboard, ...) it's _strongly_ recommended to get a review by somebody +not involved with that project to ensure that the documentation of the +issue is clear enough. + +* Trivial changes that deal with minor issues like inconsistencies in +whitespace or spelling fixes that don't impact the final binary output +also don't need to wait. Such changes should point out in their commit +messages how the the author verified that the binary output is identical +(e.g. a TIMELESS build for a given configuration). When submitting +such changes early, the submitter must be different from the author +and must document the intent in the Gerrit discussion, e.g. "landed the +change early because it's trivial". Note that trivial fixes shouldn't +necessarily be expedited: Just like they're not critical enough for +things to go wrong because of them, they're not critical enough to +require quick handling. This exception merely serves to acknowledge that +a round-the-world review just isn't necessary for some types of changes. + +* As explained in our Code of Conduct, we try to assume the best of each +other in this community. It's okay to discuss mistakes (e.g. isolated +instances of non-trivial and non-critical changes submitted early) but +try to keep such inquiries blameless. If a change leads to problems with +our code, the focus should be on fixing the issue, not on assigning blame. * Do not +2 patches that you authored or own, even for something as trivial as whitespace fixes. When working on your own patches, it’s easy to diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 81a06eb410..13aeed5bd2 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -88,11 +88,6 @@ configurations together into a set of macros, e.g., ```C /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) - /* - * Set native function with RX Level/Edge configuration and disable - * input/output buffer if necessary - */ - #define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) /* General purpose output, with termination specified */ diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index ecdfe62d4a..037371bd34 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -52,7 +52,7 @@ command line. not have an answer yet, it stops and queries the user for the desired value. - olddefconfig - Generates a config, using the default value for any symbols not listed in the .config file. -- savedefconfig - Creates a ‘mini-config’ file, stripping out all of the symbols +- savedefconfig - Creates a ‘defconfig’ file, stripping out all of the symbols that were left as default values. This is very useful for debugging, and is how config files should be saved. - silentoldconfig - This evaluates the .config file the same way that the @@ -398,6 +398,8 @@ default <expr> \[if <expr>\] - If there is no 'default' entry for a symbol, it gets set to 'n', 0, 0x0, or “” depending on the type, however the 'bool' type is the only type that should be left without a default value. +- If possible, the declaration should happen before all default entries to make + it visible in Kconfig tools like menuconfig. -------------------------------------------------------------------------------- diff --git a/Documentation/index.md b/Documentation/index.md index a7c4869db2..fd1ecb1639 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -166,6 +166,7 @@ Contents: * [Project Ideas](contributing/project_ideas.md) * [Documentation Ideas](contributing/documentation_ideas.md) * [Code of Conduct](community/code_of_conduct.md) +* [Language style](community/language_style.md) * [Community forums](community/forums.md) * [Project services](community/services.md) * [coreboot at conferences](community/conferences.md) diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index c6ccc7b868..ef5e892c36 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -5,6 +5,7 @@ ## Supported architectures +* aarch32 * aarch64 * riscv @@ -26,6 +27,13 @@ The section must be named in order to be found by the FIT parser: The FIT parser needs architecure support. +### aarch32 +The source code can be found in `src/arch/arm/fit_payload.c`. + +On aarch32 the kernel (a section named 'kernel') must be in **Image** +format and it needs a devicetree (a section named 'fdt') to boot. +The kernel will be placed close to "*DRAMSTART*". + ### aarch64 The source code can be found in `src/arch/arm64/fit_payload.c`. diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md new file mode 100644 index 0000000000..77615313e0 --- /dev/null +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -0,0 +1,170 @@ +# ASUS A88XM-E + +This page describes how to run coreboot on the [ASUS A88XM-E]. + +## Technology + +Both "Trinity" and "Richland" FM2 desktop processing units are working, +the CPU architecture in these CPUs/APUs are [Piledriver], +and their GPU is [TeraScale 3] (VLIW4-based). + +Kaveri is non-working at the moment (FM2+), +the CPU architecture in these CPUs/APUs are [Steamroller], +and their GPU is [Sea Islands] (GCN2-based). + +A10 Richland is recommended for the best performance and working IOMMU. + +```eval_rst ++------------------+--------------------------------------------------+ +| A88XM-E | | ++------------------+--------------------------------------------------+ +| DDR voltage IC | Nuvoton 3101S | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111G | ++------------------+--------------------------------------------------+ +| Northbridge | Integrated into CPU with IMC and GPU (APUs only) | ++------------------+--------------------------------------------------+ +| Southbridge | Bolton-D4 | ++------------------+--------------------------------------------------+ +| Sound IC | Realtek ALC887 | ++------------------+--------------------------------------------------+ +| Super I/O | ITE IT8603E | ++------------------+--------------------------------------------------+ +| VRM controller | DIGI VRM ASP1206 | ++------------------+--------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | [GD25Q64] | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | yes | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom], if the +AmdSpiRomProtect modules have been deleted in the factory image previously. + +### External flashing + +Using a PLCC Extractor or any other appropriate tool, carefully remove the +DIP-8 BIOS chip from its' socket while avoiding the bent pins, if possible. +To flash it, use a [flashrom]-supported USB CH341A programmer - preferably with a +green PCB - and double check that it's giving a 3.3V voltage on the socket pins. + +## Integrated graphics + +### Retrieve the VGA optionrom ("Retrieval via Linux kernel" method) + +Make sure a proprietary UEFI is flashed and boot Linux with iomem=relaxed flag. +Some Linux drivers (e.g. radeon for AMD) make option ROMs like the video blob +available to user space via sysfs. To use that to get the blob you need to +enable it first. To that end you need to determine the path within /sys +corresponding to your graphics chip. It looks like this: + + # /sys/devices/pci:/::./rom. + +You can get the respective information with lspci, for example: + + # lspci -tv + # -[0000:00]-+-00.0 Advanced Micro Devices, Inc. [AMD] Family 16h Processor Root Complex + # +-01.0 Advanced Micro Devices, Inc. [AMD/ATI] Kabini [Radeon HD 8210] + # ... + +Here the the needed bits (for the ROM of the Kabini device) are: + + # PCI domain: (almost always) 0000 + # PCI bus: (also very commonly) 00 + # PCI slot: 01 (logical slot; different from any physical slots) + # PCI function: 0 (a PCI device might have multiple functions... shouldn't matter here) + +To enable reading of the ROM you need to write 1 to the respective file, e.g.: + + # echo 1 > /sys/devices/pci0000:00/0000:00:01.0/rom + +The same file should then contain the video blob and it should be possible to simply copy it, e.g.: + + # cp /sys/devices/pci0000:00/0000:00:01.0/rom vgabios.bin + +romheaders should print reasonable output for this file. + +This version is usable for all the GPUs. + 1002,9901 Trinity (Radeon HD 7660D) + 1002,9904 Trinity (Radeon HD 7560D) + 1002,990c Richland (Radeon HD 8670D) + 1002,990e Richland (Radeon HD 8570D) + 1002,9991 Trinity (Radeon HD 7540D) + 1002,9993 Trinity (Radeon HD 7480D) + 1002,9996 Richland (Radeon HD 8470D) + 1002,9998 Richland (Radeon HD 8370D) + 1002,999d Richland (Radeon HD 8550D) + 1002,130f Kaveri (Radeon R7) + +## Known issues + +- AHCI hot-plug +- S3 resume (sometimes) +- Windows 7 can't boot because of the incomplete ACPI implementation +- XHCI + +### XHCI ports can break after using any of the blobs, restarting the +board with factory image makes it work again as fallback. +Tested even with/without the Bolton and Hudson blobs. + +## Untested + +- audio over HDMI + +## TODOs + +- one ATOMBIOS module for all the integrated GPUs +- manage to work with Kaveri/Godavary (they are using a binaryPI) +- IRQ routing is done incorrect way - common problem of fam15h boards + +## Working + +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Gigabit Ethernet +- Hardware monitoring +- Integrated graphics +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard mouse (during payload, bootloader) +- SATA +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) +- IOMMU + +## Extra resources + +- [Board manual] + +[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/ +[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf +[flashrom]: https://flashrom.org/Flashrom +[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf +[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines +[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation +[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture) +[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 diff --git a/Documentation/mainboard/emulation/qemu-i440fx.md b/Documentation/mainboard/emulation/qemu-i440fx.md new file mode 100644 index 0000000000..059ad123c5 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-i440fx.md @@ -0,0 +1,64 @@ +# qemu i440fx mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-i440fx mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot + +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M pc +``` + +### To run the experimental x86_64 version of coreboot +Running on qemu-system-x86_64 allows to run a 32 bit or 64 bit operating system, +as well as firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc -accel kvm -cpu host +``` diff --git a/Documentation/mainboard/emulation/qemu-q35.md b/Documentation/mainboard/emulation/qemu-q35.md new file mode 100644 index 0000000000..00163e89fc --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-q35.md @@ -0,0 +1,64 @@ +# qemu q35 mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-q35 mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M q35 +``` + +### To run the experimental x86_64 version of coreboot +Running on `qemu-system-x86_64` allows to run a 32 bit or 64 bit operating system +and firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 -accel kvm -cpu host +``` + diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index cdd32089e6..022a4e5ef1 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -2,7 +2,7 @@ This page describes how to run coreboot on the Facebook Monolith. -Please note: the coreboot implementation for this boards is in its +Please note: the coreboot implementation for this board is in its Beta state and isn't fully tested yet. ## Required blobs @@ -104,7 +104,7 @@ solution. Wires need to be connected to be able to flash using an external progr - SMBus - Initialization with FSP - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) -- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) +- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629) - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7) - eMMC diff --git a/Documentation/mainboard/hp/2560p.md b/Documentation/mainboard/hp/2560p.md new file mode 100644 index 0000000000..0b51a89e38 --- /dev/null +++ b/Documentation/mainboard/hp/2560p.md @@ -0,0 +1,99 @@ +# HP EliteBook 2560p + +This page is about the notebook [HP EliteBook 2560p]. + +## Release status + +HP EliteBook 2560p was released in 2011 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: +1. EC firmware +2. Intel ME firmware + +EC firmware can be retrieved from the HP firmware update image, or the firmware +backup of the laptop. EC Firmware is part of the coreboot build process. +The guide on extracting EC firmware and using it to build coreboot is in +document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops). + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +## Programming + +The flash chip is located between the memory slots and the PCH, +covered by the base enclosure, which needs to be removed according to +the [Maintenance and Service Guide] to access the flash chip. An SPI +flash programmer using 3.3V voltage such as a ch341a programmer, and +an SOIC-8 clip can be used to read and flash the chip in-circuit. + +Pin 1 of the flash chip is at the side near the PCH. + +![Flash Chip in 2560p](2560p_flash.webp) + +For more details have a look at the general [flashing tutorial]. + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the back +bottom USB port. + +Schematic of this laptop can be found on [Lab One]. + +## Test status + +### Known issues + +- GRUB payload freezes if at_keyboard module is in the GRUB image + ([bug #141]) + +### Untested + +- Optical Drive +- VGA +- Fingerprint Reader +- Modem + +### Working + +- Integrated graphics init with libgfxinit +- SATA +- Audio: speaker and microphone +- Ethernet +- WLAN +- WWAN +- Bluetooth +- ExpressCard +- SD Card Reader +- SmartCard Reader +- eSATA +- USB +- DisplayPort +- Keyboard, touchpad and trackpoint +- EC ACPI support and thermal control +- Dock: all USB ports, DisplayPort, eSATA +- TPM +- Internal flashing when IFD is unlocked +- Using `me_cleaner` + + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Sandy/Ivy Bridge (FCPGA988) | ++------------------+--------------------------------------------------+ +| PCH | Intel Cougar Point QM67 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618 +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/ +[bug #141]: https://ticket.coreboot.org/issues/141 diff --git a/Documentation/mainboard/hp/2560p_flash.webp b/Documentation/mainboard/hp/2560p_flash.webp new file mode 100644 index 0000000000..8583fa0845 Binary files /dev/null and b/Documentation/mainboard/hp/2560p_flash.webp differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3a7dd31742..998de613c0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -37,6 +37,8 @@ The boards in this section are not real mainboards, but emulators. - [Spike RISC-V emulator](emulation/spike-riscv.md) - [Qemu RISC-V emulator](emulation/qemu-riscv.md) - [Qemu AArch64 emulator](emulation/qemu-aarch64.md) +- [Qemu x86 Q35](emulation/qemu-q35.md) +- [Qemu x86 PC](emulation/qemu-i440fx.md) ## Facebook @@ -59,6 +61,7 @@ The boards in this section are not real mainboards, but emulators. ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) ## Intel @@ -115,6 +118,7 @@ The boards in this section are not real mainboards, but emulators. ## OCP +- [Delta Lake](ocp/deltalake.md) - [Tioga Pass](ocp/tiogapass.md) ## Open Cellular @@ -135,6 +139,10 @@ The boards in this section are not real mainboards, but emulators. - [Hermes](prodrive/hermes.md) +## Purism + +- [Librem Mini](purism/librem_mini.md) + ## Protectli - [FW2B / FW4B](protectli/fw2b_fw4b.md) diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e87969f9..c886a21bfa 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -89,7 +89,7 @@ $ make ``` If your flash is not 8 MB, you need to change values of `flcomp_density1` and -`flreg1_limit` in the ifd-x200.set file according to following table: +`flreg1_limit` in the `ifd-x200.set` file according to following table: ```eval_rst +-----------------+-------+-------+--------+ diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index 08df76fdca..f364f07784 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -30,7 +30,6 @@ the laptop able to power on. ## Known Issues -- No audio output when using a headphone - Cannot get the mainboard serial number from the mainboard: the OEM UEFI firmware gets the serial number from an "emulated EEPROM" via I/O port 0x1630/0x1634, but it's still unknown how to make it work diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index c4c3284b8f..57e727f9bd 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -1,7 +1,8 @@ # OCP Delta Lake This page describes coreboot support status for the [OCP] (Open Compute Project) -Delta Lake server platform. +Delta Lake server platform. This page is updated following each 4-weeks +build/test/release cycle. ## Introduction @@ -13,8 +14,9 @@ Delta Lake server is a single socket Cooper Lake Scalable Processor server. Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled. -Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners -jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative solution. +The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners +jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative +solution. This development is moving toward EVT exit equivalent status. ## Required blobs @@ -22,7 +24,7 @@ This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP (Mass Production) of CooperLake Scalable Processor when the FSP is mature. -- Microcode: Not yet available to the public. +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. - ME binary: Not yet available to the public. ## Payload @@ -55,26 +57,49 @@ as initramfs. - Type 2 -- Baseboard Information - Type 3 -- System Enclosure or Chassis - Type 4 -- Processor Information + - Type 7 -- Cache Information - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String - - Type 13 -- BIOS Language Information - - Type 16 -- Physical Memory Array - - Type 19 -- Memory Array Mapped Address + - Type 32 -- System Boot Information + - Type 38 -- IPMI Device Information - Type 127 -- End-of-Table - - BMC integration: - BMC readiness check - IPMI commands - watchdog timer - POST complete pin acknowledgement + - Check BMC version: ipmidump -device - SEL record generation - Early serial output - port 80h direct to GPIO -- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT - Skipping memory training upon subsequent reboots by using MRC cache - BMC crash dump - Error injection through ITP +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - NIC card + - All 5 data drives +- Power button +- localboot +- netboot from IPv6 +- TPM + +## Stress/performance tests passed +- OS warm reboot (300 cycles) +- DC reboot (300 cycles) +- AC reboot (300 cycle) +- Mprime test (6 hours) +- StressAppTest (6 hours) +- Ptugen (6 hours) +- MLC (Intel Memory Latency Check) +- Linkpack +- Iperf(IPv6) +- FIO ## Firmware configurations [ChromeOS VPD] is used to store most of the firmware configurations. @@ -84,29 +109,22 @@ values. VPD variables supported are: - firmware_version: This variable holds overall firmware version. coreboot uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. ## Known issues -- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not - support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. -- VT-d is not supported. An IPS ticket is filed with Intel. -- PCIe bifuration is not supported. An IPS ticket is filed with Intel. -- ME based power capping. This is a bug in ME. An IPS ticket is filed - with Intel. -- RO_VPD region as well as other RO regions are not write protected. -- HECI is not set up correctly, so BMC is not able to get PCH and DIMM - temperature sensor readings. +- spsInfoLinux64 command fail to return ME version. +- fwts test failures related to mtrr. +- kernel error message related to SleepButton ACPI event. ## Feature gaps -- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers - at the moment. - SMBIOS: - - Type 7 -- Cache Information + - Type 16 -- Physical Memory Array - Type 17 -- Memory Device - - Type 38 -- IPMI Device Information + - Type 19 -- Memory Array Mapped Address - Type 41 -- Onboard Devices Extended Information -- ACPI: - - DMAR -- PFR/CBnT +- Verified measurement through CBnT +- Boot guard of CBnT +- RO_VPD region as well as other RO regions are not write protected. ## Technology @@ -116,7 +134,7 @@ VPD variables supported are: +------------------------+---------------------------------------------+ | BMC | Aspeed AST 2500 | +------------------------+---------------------------------------------+ -| PCH | Intel Lewisburg C621 | +| PCH | Intel Lewisburg C620 Series | +------------------------+---------------------------------------------+ ``` diff --git a/Documentation/mainboard/purism/librem_mini.jpg b/Documentation/mainboard/purism/librem_mini.jpg new file mode 100644 index 0000000000..004235d013 Binary files /dev/null and b/Documentation/mainboard/purism/librem_mini.jpg differ diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md new file mode 100644 index 0000000000..be9a3e5632 --- /dev/null +++ b/Documentation/mainboard/purism/librem_mini.md @@ -0,0 +1,122 @@ +# Purism Librem Mini + +This page describes how to run coreboot on the [Purism Librem Mini]. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-8565U | ++------------------+--------------------------------------------------+ +| PCH | Whiskey Lake / Cannon Point LP | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8528E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine (CSME 12.x) | ++------------------+--------------------------------------------------+ +``` + +![](librem_mini.jpg) +![](librem_mini_flash.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Coffee Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by the build +system from the `3rdparty/intel-microcode` submodule. Official Purism release +images may include newer microcode, which is instead pulled from Purism's +[purism-blobs] repository. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using FSP/GOP display init). It can +be extracted via cbfstool from the existing board firmware or pulled from +the [purism-blobs] repository. + +## Intel Management Engine + +The Librem Mini uses version 12.x of the Intel Management Engine (ME) / +Converged Security Engine (CSE). The ME/CSE is disabled using the High +Assurance Platform (HAP) bit, which puts the ME into a disabled state +after platform bring-up (BUP) and disables all PCI/HECI interfaces. +This can be verified via the coreboot cbmem utility: +`sudo ./cbmem -1 | grep 'ME:'` +provided coreboot has been modified to output the ME status even when +the PCI device is not visible/active (as it is in Purism's release builds). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.2. Firmware an be easily flashed +with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip, +and has a diode attached to the VCC line for in-system programming. +This chip is located on the bottom side of the board under the CPU heatsink, +in line with the front USB 2.0 ports. + +One has to remove all screws (in order): + + * 2 top cover screws + * 4 screws securing the mainboard to the chassis + * 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs) + +The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to +an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip. +Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV]. + +The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV), +but is not protected by a diode and therefore cannot be read/written to without +desoldering it from the mainboard. + +## Known issues + + * SeaBIOS can be finicky with detecting USB devices + * Booting can sometimes hang when a bootsplash image is used with SeaBIOS + and VGA option ROM display init, related to display mode changing + * Issues with some SATA devices have been mitigated by limiting the SATA speed to 3Gbps + until the correct HSIO PHY settings can be determined. + +## Working + + * External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init + (no libgfxinit support yet) + * SeaBIOS (1.13.x), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads + * Ethernet, m.2 2230 Wi-Fi + * System firmware updates via flashrom + * PCIe NVMe + * m.2 and SATA III + * Audio via front 3.5mm jack, HDMI, and DisplayPort + * SMBus (reading SPD from DIMMs) + * Initialization with CFL FSP 2.0 + * S3 Suspend/Resume + * Booting PureOS 9.x, Debian 10.x, Qubes 4.0.3, Linux Mint 19.3, Windows 10 2004 + +## Not working / untested + + * ITE IT8528E Super IO functions + + +[Purism Librem Mini]: https://puri.sm/products/librem-mini/ +[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs +[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/purism/librem_mini_flash.jpg b/Documentation/mainboard/purism/librem_mini_flash.jpg new file mode 100644 index 0000000000..d1c6071f25 Binary files /dev/null and b/Documentation/mainboard/purism/librem_mini_flash.jpg differ diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 2910867f78..8d19067c70 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -39,4 +39,23 @@ attributes as per their datasheet and convert those attributes into SPD files fo the platforms. More details about the tools are added in [README.md](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/spd_tools/intel/lp4x/README.md). +### New version of SMM loader + +A new version of the SMM loader which accomodates platforms with over 32 CPU +CPU threads. The existing version of SMM loader uses a 64K code/data +segment and only a limited number of CPU threads can fit into one segment +(because of save state, STM, other features, etc). This loader extends beyond +the 64K segment to accomodate additional CPUs and in theory allows as many +CPU threads as possible limited only by SMRAM space and not by 64K. By default +this loader version is disabled. Please see cpu/x86/Kconfig for more info. + +### Initial support for x86_64 + +The x86_64 code support has been revived and enabled for qemu. While it started +as PoC and the only supported platform is an emulator, there's interest in +enabling additional platforms. It would allow to access more than 4GiB of memory +at runtime and possibly brings optimised code for faster execution times. +It still needs changes in assembly, fixed integer to pointer conversions in C, +wrappers for blobs, support for running Option ROMs, among other things. + ### Add significant changes here diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 845c0e7109..30083f0c90 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -142,6 +142,7 @@ - Trogdor - Lazor - Bubs +- Coachz - Veyron_Jaq (Haier Chromebook 11) - Veyron_Jerry (Hisense Chromebook 11) - Veyron_Mighty (Haier Chromebook 11(edu)) diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index 23088cd12b..fffe25b023 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -240,47 +240,12 @@ in an Integration Guide. ## APCB setup APCBs are used to provide the PSP with SPD information and optionally a set of -GPIOs to use for selecting which SPD to load. - -### Prebuilt -The picasso `Makefile` expects APCBs to be located in -`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just -add the following to your mainboard's Makefile. - -``` -# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin -APCB_SOURCES = mandolin -``` +GPIOs to use for selecting which SPD to load. A list of APCB files should be +specified in `APCB_SOURCES`. ### Generating APCBs If you have a template APCB file, the `apcb_edit` tool can be used to inject the -SPD and GPIOs used to select the correct slot. Entries should match this -pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in -`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. -The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. -If a slot is empty, the special empty keyword can be used. This will generate -an APCB with an empty SPD. - -``` -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 -``` - -#### APCB Board ID GPIO configuration. -The GPIOs determine which memory SPD will be used during boot. -``` -# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL -# GPIO_NUMBER: FCH GPIO number -# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO -# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO - -APCB_BOARD_ID_GPIO0 = 121 1 0 -APCB_BOARD_ID_GPIO1 = 120 1 0 -APCB_BOARD_ID_GPIO2 = 131 3 0 -APCB_BOARD_ID_GPIO3 = 116 1 0 -``` +SPD and GPIOs used to select the correct slot. ## Footnotes diff --git a/Documentation/soc/intel/cse_fw_update/Layout_after.svg b/Documentation/soc/intel/cse_fw_update/Layout_after.svg new file mode 100644 index 0000000000..95720db6b5 --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/Layout_after.svg @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + Page-1 + + Rectangle.116 + DESC + + DESC + + Rectangle.117 + CSE - RO + + CSE - RO + + Rectangle.118 + + + + Rectangle.119 + COREBOOT_RO + + COREBOOT_RO + + Rectangle.120 + RW_MISC + + RW_MISC + + Rectangle.121 + FW_MAIN_B + + FW_MAIN_B + + Rectangle.122 + FW_MAIN_A + + FW_MAIN_A + + Sheet.123 + 0x1FFFFFF + + 0x1FFFFFF + + Sheet.124 + 0x0 + + 0x0 + + Rectangle.125 + RW_LEGACY + + RW_LEGACY + + Right Brace.126 + + + + Sheet.127 + HW WP + + HW WP + + Right Brace.128 + + + + Sheet.129 + SPI Controller WP via descriptor + + SPI Controller WP via descriptor + + Sheet.130 + + Rectangle.423 + CSE-RW + + CSE-RW + + + Sheet.132 + + Rectangle.423 + CSE-RW + + CSE-RW + + + Rectangle.134 + CSE-RW + + CSE-RW + + Universal connector.473 + + + + Universal connector.136 + + + + Sheet.138 + CSE RW copied during an update + + CSE RW copied during an update + + Right Brace.139 + + + + Sheet.140 + GRP0 Protected + + GRP0 Protected + + diff --git a/Documentation/soc/intel/cse_fw_update/Layout_before.svg b/Documentation/soc/intel/cse_fw_update/Layout_before.svg new file mode 100644 index 0000000000..d03754880e --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/Layout_before.svg @@ -0,0 +1,95 @@ + + + + + + + + Page-1 + + Rectangle.178 + DESC + + DESC + + Rectangle.179 + CSME/PMC + + CSME/PMC + + Rectangle.180 + + + + Rectangle.181 + COREBOOT_RO + + COREBOOT_RO + + Rectangle.182 + RW_MISC + + RW_MISC + + Rectangle.183 + FW_MAIN_B + + FW_MAIN_B + + Rectangle.184 + FW_MAIN_A + + FW_MAIN_A + + Sheet.94 + 0x1FFFFFF + + 0x1FFFFFF + + Sheet.95 + 0x0 + + 0x0 + + Rectangle.106 + RW_LEGACY + + RW_LEGACY + + Right Brace.398 + + + + Sheet.96 + HW WP + + HW WP + + Right Brace.115 + + + + Sheet.97 + SPI Controller WP via descriptor + + SPI Controller WP via descriptor + + diff --git a/Documentation/soc/intel/cse_fw_update/cse_fw_update.md b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md new file mode 100644 index 0000000000..98fe310113 --- /dev/null +++ b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md @@ -0,0 +1,127 @@ +CSE FW update mechanism for devices in field + +## Introduction + +CSE Firmware and PMC Firmware are critical components of Intel SoCs. +CSE and PMC cooperate by providing platform services during boot and other +power transition flows. + +## Problem Statement + +Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW +versions that are released by Intel to address important functional and security +bugs post-product launch will not be available to the end-user. Hence, the proposed +solution allows in-field CSE FW update to propagate those bug fixes +to end user platforms. + +## Design Proposal + +### CSE FW design Proposal: + +Key Elements: + +- CSE FW layout is composed of two bootable partitions (RO Recovery Partition + and RW Normal Partition). + +- Boot partition selection: An API-based mechanism is used to decide from which partition + CSE will boot. + +- The HECI APIs below will be supported in this CSE FW: + + - HMRFPO_ENABLE: This command requests the CSE enter a mode in which writes to + the CSE region from the CSE are disabled. It also grants temporary write access + to the RW partition from the host (RO is still protected by GPR0). + + - GET_PARTITION_INFO: The command retrieves information for each boot partition from CSE + like version, start/end offsets of a partition within CSE region, and boot + partition status. Also, it provides below information: + - The current boot partition which was used during this boot, + - The boot partition that will be used on the next CSE reset + - The number of boot partitions available in the CSE region + + - SET_BOOT_PARTITION_INFO: This command allows the firmware to request the + CSE to boot from either its RO or RW partition at its next reset. + + - DATA_CLEAR: This command requests the CSE to reset its data partition back + to manufacturing defaults + +FW Layout, RW/RO Partitions: + +The CSE RO partition is the first in the CSE boot order, hence it will be used +out of G3. RO partition contains minimum CSE code capable to boot platform and +execute FW update of RW partition. In addition to CSE code, the RO partition also +contains PMC FW patch and other CSE-loadable platform FW components. + +RW partition contains fully operational CSE FW, PMC FW, other CSE loadable +platform FW components. + +Boot partition selection: + +CSE FW shall support 2 APIs to get boot partition info, and set boot partition +info to notify CSE to select the partition on the next boot. + +### HOST FW Design proposal: + +Key Elements: + +- Build time artifacts: + + CSE RW Version update binary - The FW shall pack CSE RW update blob and + corresponding version binary which contains version of the CSE RW blob. + +- FW Update: + + coreboot will implement the logic to compare the CSE's FW version with CBFS + CSE RW binary's version in the firmware slot (FW_MAIN_A/FW_MAIN_B) and update + the CSE RW region if there is a version mismatch. If there is no version + mismatch, firmware skips CSE FW update. + +- Handling of CSE FW Downgrade: + + coreboot will send DATA_CLEAR HECI command when there is a CSE FW downgrade. + This must be done to avoid data mismatch due to CSE FW downgrade. Further, + CSE will restore the data back to manufacturing defaults after data reset. + + +## Implementation Details + + +To enable CSE FW update flow the following changes are required in coreboot: + +* Descriptor change may be required to accommodate CSE binary. The CSE binary is tied with +a platform. So CSE size may vary from one platform to another. +* FMAP changes may be required to accommodate CSE binary and CSE RW blob in the RW CBFS region. +Please check platform specific CSE kit for CSE binary information. +* CSE Lite SKU binary and CSE RW blob +* Makefile change to pack CSE RW binaries in the CBFS +* Implementation of update flow: + - Get CSE boot partition info using GET_BOOT_PARTITION_INFO HECI command. + - Get the cbfs_me_rw.version from the currently selected RW slot. + - If the version from the above 2 locations don't match, then start CSE FW update. + - If CSE is not booting from RO, then + - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION_INFO + HECI command. + - Send GLOBAL_RESET HECI command to reset the system. + - If RW update is a CSE FW downgrade, then coreboot has to send + DATA_CLEAR command to clear run time data of CSE. + - Enable HMRFPO Mode (Host ME Region Flash Protection Override) by + sending HMRFPO_ENABLE HECI command to CSE. + - Erase and Copy the CBFS CSE RW to CSE RW partition + - Set CSE's next boot partition to RW. + - Trigger Global Reset which resets both CSE and Host. + Then system should boot with the updated CSE. + +* The resulting flash layout is shown below: + +![Flash Layout](./Layout_before.svg) ![FlashLayout](./Layout_after.svg) + + + - Typical boot flow + + - Vboot selects the RW FW (FW_MAIN_A or FW_MAIN_B) to boot. + - coreboot skips CSE FW update flow if boot mode is recovery. + - If CSE RW blob is not locatable in the CBFS, then RW Firmware skips update flow + and sends SET_BOOT_PARTITION_INFO command to switch CSE to boot from RW + and issues Global Reset if CSE is already not booting from RW partition. + - The RW firmware will compare the CSE RW version with CSE RW blob in the slot. + - If there is a mismatch, then firmware will carry out update flow as explained before. diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a1d6..5c7239af6b 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -8,5 +8,7 @@ This section contains documentation about coreboot on specific Intel SOCs. - [FSP](fsp/index.md) - [Ice Lake/9th Gen Core-i series](icelake/index.md) - [MP Initialization](mp_init/mp_init.md) +- [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) +- [CSE FW Update](cse_fw_update/cse_fw_update_model.md) diff --git a/Documentation/soc/intel/microcode.md b/Documentation/soc/intel/microcode.md new file mode 100644 index 0000000000..0d65b74b11 --- /dev/null +++ b/Documentation/soc/intel/microcode.md @@ -0,0 +1,136 @@ +# Microcode updates + +When booting a modern x86 platform, one task of the firmware is to update +[microcode] to correct hardware bugs and mitigate security issues found +after silicon has been shipped. The [Pentium FDIV bug] could have been +fixed with a microcode update, had the Pentium used updateable microcode. +Starting with the Pentium Pro, CPU microcode can be updated by software. + +As per BIOS Writer's Guides, Intel defines a processor as the silicon and +the accompanying microcode update, and considers any processor that does +not have its microcode updated to be running out of specification. This +suggests that microcode is a crucial ingredient for correct operation. + +On multi-processor or Hyper-Threading-enabled systems, each thread has +its own microcode. Therefore, microcode must be updated on every thread. + +## When to update microcode + +When a CPU core comes out of reset, it uses microcode from an internal +ROM. This “default” microcode often contains bugs, so it needs to be +updated as soon as possible. For example, Core 2 CPUs can boot without +microcode updates, but have stability problems. On newer platforms, +it is nearly impossible to boot without having updated the microcode. +On some platforms, an updated microcode is required in order to enable +Cache-As-RAM or to be able to successfully initialize the DRAM. + +Plus, microcode needs to be loaded multiple times. Intel Document 504790 +explains that this is because of so-called *enhanced microcode updates*, +which are large updates with errata workarounds for both core and uncore. +In order to correctly apply enhanced microcode updates, the [MP-Init] +algorithm must be decomposed into multiple initialization phases. + +### Firmware Interface Table + +Beginning with 4th generation Intel Core processors, it is possible for +microcode to be updated before the CPU is taken out of reset. This is +accomplished by means of [FIT], a data structure which contains pointers +to various firmware ingredients in the BIOS flash. + +In rare cases, FIT microcode updates may not be successful. Therefore, +it is important to check that the microcode is up-to-date and, if not, +update it. This needs to be done as early as possible, like on older +processor generations without FIT support. + +Whether all threads on a processor get their microcode updated through +FIT is not clear. According to Intel Documents 493770 and 535094, FIT +microcode updates are applied to all cores within the package. However, +Intel Document 550049 states that FIT microcode updates are applied to +all threads within the package. + +## SMM bring-up + +Prior to SMM relocation, microcode must have been updated at least once. + +## Multi-Processor bring-up + +The BWG briefly describes microcode updates as part of the *MP-Init*. + +### MP-Init + +As part of the [MP-Init] sequence, two microcode updates are required. + +* The first update must happen as soon as one AP comes out of reset. +* The second update must happen after the MP-Init sequence has written MTRRs, + PRMRR, DCU mode and prefetcher configuration, SMM has been relocated, but + before clearing the MCE banks. + +## Recommendations + +The Linux kernel developer's recommendations are: +* Serialize microcode updates if possible. +* Idle as many APs as possible while updating. +* Idle the sibling thread on a Hyper-Threading enabled CPU while updating. + +## Platform BWGs + +The requirements specified in BWGs differ between platforms: + +### Sandy Bridge + +* Before setting up Cache-As-RAM, load microcode update into the SBSP. +* Losing (non-SBSP) NBSPs must load their microcode update before being placed + back in the wait-for-SIPI state. +* Sibling threads on HT must use a semaphore. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and PRMRRs. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and PRMRRs. + +Refer to Intel Document 504790 for details. + +### Haswell/Broadwell Client + +* A microcode update must exist in FIT. +* During the race to the BSP semaphore, each NBSP must load its microcode update. +* All HT enabled threads can load microcode in parallel. However, the + IA32_BIOS_UPDT_TRIG MSR is core-scoped, just like on other platforms. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and EMRR. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and EMRR and after SMM initialization. + +Refer to Intel Document 493770 and 535094 for details. + +### Broadwell Server + +* A microcode update must exist in FIT. +* Before setting up Cache-As-RAM, load microcode update into each BSP. +* In MP-Init the microcode update on an AP must be done before initializing the + cache, MTRRs, SMRRs and EMRR. +* In MP-Init a second update must happen on all threads after initializing the + cache, MTRRs, SMRRs and EMRR and after SMM initialization. + +Refer to Intel Document 546625 for details. + +### Skylake/Kaby Lake/Coffee Lake/Whiskey Lake/Comet Lake + +* A microcode update must exist in FIT. +* Before setting up Cache-As-RAM, load microcode update into the BSP. +* Microcode update loading has been done prior to SMM relocation. +* In MP-Init the first update must happen as soon as one AP comes out of reset. +* In MP-Init the second update must happen after the MP-Init sequence has + written MTRRs, PRMRR, DCU mode and prefetcher configuration, but before + clearing the MCE banks. +* Microcode updates must happen on all threads. +* Sibling threads on HT should use a semaphore. + +Refer to Intel Document 550049 for details. + +[microcode]: https://en.wikipedia.org/wiki/Microcode +[Pentium FDIV bug]: https://en.wikipedia.org/wiki/Pentium_FDIV_bug +[FIT]: fit.md +[SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf +[MP-Init]: mp_init/mp_init.md diff --git a/Documentation/technotes/asan.md b/Documentation/technotes/asan.md new file mode 100644 index 0000000000..e0d503a2a2 --- /dev/null +++ b/Documentation/technotes/asan.md @@ -0,0 +1,302 @@ +# Address Sanitizer + +Memory safety is hard to achieve. We, as humans, are bound to make mistakes in +our code. While it may be straightforward to detect memory corruption bugs in +few lines of code, it becomes quite challenging to find those bugs in a massive +code. In such cases, 'Address Sanitizer' may prove to be useful and could help +save time. + +[Address Sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) +, also known as ASan, is a runtime memory debugger designed to find +out-of-bounds accesses and use-after-scope bugs. coreboot has an in-built +Address Sanitizer. Therefore, it is advised to take advantage of this debugging +tool while working on large patches. This would further help to ensure code +quality and make runtime code more robust. + +## Types of errors detected +ASan in coreboot catches the following types of memory bugs: + +### Stack buffer overflow +Example stack-out-of-bounds: +```c +void foo() +{ + int stack_array[5] = {0}; + int i, out; + for (i = 0; i < 10; i++) + out = stack_array[i]; +} +``` +In this example, the array is of length 5 but it is being read even beyond the +index 4. + +### Global buffer overflow +Example global-out-of-bounds: +```c +char a[] = "I use coreboot"; + +void foo() +{ + char b[] = "proprietary BIOS"; + strcpy(a + 6, b); +} +``` +In this example, +> well, you are replacing coreboot with proprietary BIOS. In any case, that's +an "error". + +Let's come to the memory bug. The string 'a' is of length 14 but it is being +written to even beyond that. + +### Use after scope +Example use-after-scope: +```c +volatile int *p = 0; + +void foo() { + { + int x = 0; + p = &x; + } + *p = 5; +} +``` +In this example, the value 5 is written to an undefined address instead of the +variable 'x'. This happens because 'x' can't be accessed outside its scope. + +## Using ASan + +In order to enable ASan on a supported platform, +select `Address sanitizer support` from `General setup` menu while configuring +coreboot. + +Then build coreboot and run the image as usual. If your code contains any of the +above-mentioned memory bugs, ASan will report them in the console log as shown +below: +```text +ASan: in + of bytes at addr +``` +where, + +`bug type` is either `stack-out-of-bounds`, `global-out-of-bounds` or +`use-after-scope`, + +`ip` is the address of the last good instruction before the bad access, + +`access type` is either `Read` or `Write`, + +`access size` is the number of bytes read or written, and + +`access address` is the memory location which is accessed while the error +occurs. + +Next, you have to use `ip` to retrieve the instruction which causes the error. +Since stages in coreboot are relocated, you need to normalize `ip`. For this, +first subtract the start address of the stage from `ip`. Then, read the section +headers from `.debug` file to determine the offset of the text segment. +Add this offset to the difference you calculated earlier. Let's call the +resultant address `ip'`. + +Next, read the contents of the symbol table and search for a function having +an address closest to `ip'`. This is the function in which our memory bug is +present. Let's denote the address of this function by `ip''`. + +Finally, read the assembly contents of the object file where this function is +present. Look for the affected function. Here, the instruction which exists at +the offset `ip' - ip''` corresponds to the address `ip`. Therefore, the very +next instruction is the one which causes the error. + +To see ASan in action, let's take an example. Suppose, there is a +stack-out-of-bounds error in cbfs.c that we aren’t aware of and we want ASan +to help us detect it. +```c +int cbfs_boot_region_device(struct region_device *rdev) +{ + int array[5], i; + boot_device_init(); + + for (i = 10; i > 0; i--) + array[i] = i; + + return vboot_locate_cbfs(rdev) && + fmap_locate_area_as_rdev("COREBOOT", rdev); +} +``` +First, we enable ASan from the configuration menu as shown above. Then, we +build coreboot and run the image. + +ASan reports the following error in the console log: +```text +ASan: stack-out-of-bounds in 0x7f7432fd +Write of 4 bytes at addr 0x7f7c2ac8 +``` +Here 0x7f7432fd is `ip` i.e. the address of the last good instruction before +the bad access. First we have to normalize this address as stated above. +As per the console log, this error happened in ramstage and the stage starts +from 0x7f72c000. So, let’s look at the sections headers of ramstage from +`ramstage.debug`. +```text +$ objdump -h build/cbfs/fallback/ramstage.debug + +build/cbfs/fallback/ramstage.debug: file format elf32-i386 + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00070b20 00e00000 00e00000 00001000 2**12 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .ctors 0000036c 00e70b20 00e70b20 00071b20 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 .data 0001c8f4 00e70e8c 00e70e8c 00071e8c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 3 .bss 00012940 00e8d780 00e8d780 0008e780 2**7 + ALLOC + 4 .heap 00004000 00ea00c0 00ea00c0 0008e780 2**0 + ALLOC +``` +As you can see, the offset of the text segment is 0x00e00000. Let's subtract the +start address of the stage from `ip` and add this offset to the difference. The +resultant address i.e. `ip'` is 0x00e172fd. + +Next, we read the contents of the symbol table and search for a function having +an address closest to 0x00e172fd. +```text +$ nm -n build/cbfs/fallback/ramstage.debug +........ +........ +00e17116 t _GLOBAL__sub_I_65535_1_gfx_get_init_done +00e17129 t tohex16 +00e171db T cbfs_load_and_decompress +00e1729b T cbfs_boot_region_device +00e17387 T cbfs_boot_locate +00e1740d T cbfs_boot_map_with_leak +00e174ef T cbfs_boot_map_optionrom +........ +........ +``` +The symbol having an address closest to 0x00e172fd is `cbfs_boot_region_device` and +its address i.e. `ip''` is 0x00e1729b. + +Now, as we know the affected function, let's read the assembly contents of +`cbfs_boot_region_device()` which is present in `cbfs.o` to find the faulty +instruction. +```text +$ objdump -d build/ramstage/lib/cbfs.o +........ +........ + 51: e8 fc ff ff ff call 52 + 56: 83 ec 0c sub $0xc,%esp + 59: 57 push %edi + 5a: 83 ef 04 sub $0x4,%edi + 5d: e8 fc ff ff ff call 5e + 62: 83 c4 10 add $0x10,%esp + 65: 89 5f 04 mov %ebx,0x4(%edi) + 68: 4b dec %ebx + 69: 75 eb jne 56 +........ +........ +``` +Here, we look for the instruction present at the offset 62 i.e. `ip' - ip''`. +The instruction is `add $0x10,%esp` and it corresponds to +`for (i = 10; i > 0; i--)` in our code. It means the very next instruction +i.e. `mov %ebx,0x4(%edi)` is the one that causes the error. Now, as we look at +C code of `cbfs_boot_region_device()` again, we find that this instruction +corresponds to `array[i] = i`. + +Voilà! We just caught the memory bug using ASan. + +## Supported platforms +Presently, the following architectures support ASan in ramstage: +```eval_rst ++------------------+--------------------------------+ +| Architecture | Notes | ++==================+================================+ +| x86 | Support for all x86 platforms | ++------------------+--------------------------------+ +``` + +And in romstage ASan is available on the following platforms: +```eval_rst ++---------------------+-----------------------------+ +| Platform | Notes | ++=====================+=============================+ +| QEMU i440-fx | | ++---------------------+-----------------------------+ +| Intel Apollo Lake | | ++---------------------+-----------------------------+ +| Intel Haswell | | ++---------------------+-----------------------------+ +``` +Alternatively, you can use `grep` to view the list of platforms that support +ASan in romstage: + + $ git grep "select HAVE_ASAN_IN_ROMSTAGE" + +If the x86 platform you are using is not listed here, there is +still a chance that it supports ASan in romstage. + +To test it, select `HAVE_ASAN_IN_ROMSTAGE` from the Kconfig file in the +platform's dedicated directory. Then, enable ASan from the config menu as +indicated in the previous section. + +If you are able to build coreboot without any errors and boot cleanly, that +means the platform supports ASan in romstage. In that case, please upload a +patch on Gerrit selecting this config option using 'ASan' topic. Also, update +the platform name in the table. + +However, if you end up in compilation errors or the linker error saying that +the cache got full, additional steps need to be taken to enable ASan in +romstage on the platform. While compile errors could be resolved easily and +therefore ASan in romstage has a good chance to be supported, a full cache is +an indication that it is way more work or even likely impossible to enable +ASan in romstage. + +## Future work +### Heap buffer overflow +Presently, ASan doesn't detect out-of-bounds accesses for the objects defined +in heap. + +To add support for these type of memory bugs, you have to make sure that +whenever some block of memory is allocated in the heap, the surrounding areas +(redzones) are poisoned. Correspondingly, these redzones should be unpoisoned +when the memory block is de-allocated. + +### ASan on other architectures +The following points should help when adding support for ASan to other +architectures like ARM or RISC-V: + +* Enabling ASan in ramstage on other architectures should be easy. You just +have to make sure the shadow memory is initialized as early as possible when +ramstage is loaded. This can be done by making a function call to `asan_init()` +at the appropriate place. + +* For romstage, you have to find out if there is enough room in the cache to fit +the shadow memory region. For this, find the boundary linker symbols for the +region you'd want to run ASan on, excluding the hardware mapped addresses. +Then define a new linker section named `asan_shadow` of size +`(_end - _start) >> 3`, where `_start` and `_end` are the linker symbols you +found earlier. This section should be appended to the region already occupied +by the coreboot program. Now build coreboot. If you don't see any errors while +building with the current translation function, ASan can be enabled on that +platform. + +* The shadow region we currently use consumes memory equal to 1/8th of the +program memory. So, if you end up in a linker error saying that the memory got +full, you'll have to use a more compact shadow region. In that case, the +translation function could be something like +`shadow = (mem >> 7) | shadow_offset`. Since the stack buffers are protected by +the compiler, you'll also have to create a GCC patch forcing it to use the new +translation function for this particular architecture. + +* Once you are sure that the architecture supports ASan in ramstage, select +`HAVE_ASAN_IN_RAMSTAGE` from the Kconfig file of that architecture. Similarly, +if the platform supports ASan in romstage, select `HAVE_ASAN_IN_ROMSTAGE` from +the platform's dedicated Kconfig file. + +### Post-processing script +Unlike Linux, coreboot doesn't have `%pS` printk format to dereference pointer +to its symbolic name. Therefore, we normalise the pointer address manually to +determine the name of the affected function and further use it to find the +instruction which causes the error. + +A custom script can be written to automate this process. diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index 5367e69aa2..a9320fb782 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,3 +3,4 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Address Sanitizer](asan.md) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 7e3da01572..e02812b68f 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -19,9 +19,21 @@ Download, configure, and build coreboot $ cd coreboot ### Step 3 - Build the coreboot toolchain -Please note that this can take a significant amount of time. +Please note that this can take a significant amount of time. Use `CPUS=` to +specify number of `make` jobs to run in parallel. - $ make crossgcc-i386 CPUS=$(nproc) +This will list toolchain options and supported architectures: + + $ make help_toolchain + +Here are some examples: + + $ make crossgcc-i386 CPUS=$(nproc) # build i386 toolchain + $ make crossgcc-aarch64 CPUS=$(nproc) # build Aarch64 toolchain + $ make crossgcc-riscv CPUS=$(nproc) # build RISC-V toolchain + +Note that the i386 toolchain is currently used for all x86 platforms, including +x86_64. Also note that you can possibly use your system toolchain, but the results are not reproducible, and may have issues, so this is not recommended. See step 5 diff --git a/MAINTAINERS b/MAINTAINERS index 924247edaf..4020accc0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,6 @@ M: Julius Werner S: Supported F: src/arch/arm/ F: src/arch/arm64/ -F: src/soc/mediatek/ F: src/soc/nvidia/ F: src/soc/rockchip/ F: util/nvidia/ @@ -547,10 +546,15 @@ F: src/soc/intel/xeon_sp F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +MEDIATEK SOCS +M: Hung-Te Lin +S: Supported +F: src/soc/mediatek + ORPHANED ARM SOCS S: Orphaned F: src/cpu/armltd/ -F: src/cpu/ti/ +F: src/soc/ti/ F: src/soc/qualcomm/ F: src/soc/samsung/ F: util/exynos/ diff --git a/Makefile.inc b/Makefile.inc index 89bb3e4239..882673b4c9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -13,6 +13,7 @@ CONFIG_CBFS_PREFIX:=$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE)) CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE)) CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) +CONFIG_CHIPSET_DEVICETREE:=$(call strip_quotes, $(CONFIG_CHIPSET_DEVICETREE)) CONFIG_MEMLAYOUT_LD_FILE:=$(call strip_quotes, $(CONFIG_MEMLAYOUT_LD_FILE)) ####################################################################### @@ -81,7 +82,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) @@ -264,12 +265,14 @@ REDUNDANT_OFFSET_REMARK = 2158 # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 +IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK) + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) -else -IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) +IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING) endif +IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST)) + define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw @@ -280,6 +283,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl + echo " IASL "$(IASL_WARNINGS_LIST)" warning types were ignored!" if ! $(IASL) -d $$@ 2>&1 | grep -Eq 'ACPI (Warning|Error)'; then \ echo " IASL $$@ disassembled correctly."; \ true; \ @@ -411,6 +415,10 @@ CPPFLAGS_common += -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler. CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" +ifeq ($(BUILD_TIMELESS),1) +CPPFLAGS_common += -D__TIMELESS__ +endif + ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL)$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y) CPPFLAGS_ramstage += -Isrc/device/oprom/include endif @@ -418,10 +426,10 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie +CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) @@ -569,9 +577,6 @@ $(IFDTOOL): cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool -$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -588,19 +593,28 @@ $(obj)/config.h: $(objutil)/kconfig/conf # Creation of these is architecture and mainboard independent DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_DEVICETREE) +SCONFIG_OPTIONS := --mainboard_devtree=$(DEVICETREE_FILE) + ifneq ($(CONFIG_OVERRIDE_DEVICETREE),) - OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_DEVICETREE) +SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE_FILE) +endif +ifneq ($(CONFIG_CHIPSET_DEVICETREE),) +CHIPSET_DEVICETREE_FILE := $(src)/$(CONFIG_CHIPSET_DEVICETREE) +SCONFIG_OPTIONS += --chipset_devtree=$(CHIPSET_DEVICETREE_FILE) endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c -DEVICETREE_STATIC_H := $(obj)/static.h +SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) -$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig +DEVICETREE_STATIC_H := $(obj)/static.h +SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) + +$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) @@ -1097,7 +1111,6 @@ RAMSTAGE= endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 new file mode 100644 index 0000000000..11a27bf671 --- /dev/null +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -0,0 +1,44 @@ +# Not meant for actual use. Exercises, among other things: +# + Code coverage +# + UBSAN +# + Debug options +# + SMMSTORE +# + Silicon Image SIL3114 driver +# + Genesys Logic GL9763E driver +# + EM100 support +CONFIG_COVERAGE=y +CONFIG_UBSAN=y +CONFIG_VENDOR_ASROCK=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_CONSOLE_POST=y +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_FINALIZE_USB_ROUTE_XHCI is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_SIZE=0x30000 +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_USBDEBUG=y +CONFIG_USBDEBUG_DONGLE_FTDI_FT232H=y +CONFIG_DRIVERS_SIL_3114=y +CONFIG_DRIVERS_GENESYSLOGIC_GL9763E=y +# CONFIG_SQUELCH_EARLY_SMP is not set +CONFIG_CONSOLE_SPI_FLASH=y +CONFIG_POST_DEVICE_PCI_PCIE=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_COVERAGE=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y +CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_EM100=y diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index 011f16356c..e39ff590fd 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -4,6 +4,5 @@ CONFIG_FATAL_ASSERTS=y CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_PIRQ=y CONFIG_DEBUG_MALLOC=y -CONFIG_TRACE=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 new file mode 100644 index 0000000000..0ddb3f1339 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -0,0 +1 @@ +CONFIG_CPU_QEMU_X86_64=y diff --git a/configs/config.purism_librem15_v4.txt_build_test b/configs/config.purism_librem15_v4.txt_build_test new file mode 100644 index 0000000000..f2de8bc59f --- /dev/null +++ b/configs/config.purism_librem15_v4.txt_build_test @@ -0,0 +1,8 @@ +# Not meant for actual use. Exercises Intel TXT code. Since BIOS +# and SINIT ACM blobs are missing, use something else as placeholder. +CONFIG_VENDOR_PURISM=y +CONFIG_BOARD_PURISM_LIBREM15_V4=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_LOGGING=y diff --git a/configs/config.stm b/configs/config.purism_librem15_v4_stm similarity index 100% rename from configs/config.stm rename to configs/config.purism_librem15_v4_stm diff --git a/payloads/Kconfig b/payloads/Kconfig index cfb28d6e81..627bb95c9c 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_ELF config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -97,7 +97,7 @@ config PAYLOAD_FIT_SUPPORT bool "FIT support" default n default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. diff --git a/payloads/coreinfo/AUTHORS b/payloads/coreinfo/AUTHORS new file mode 100644 index 0000000000..772018081d --- /dev/null +++ b/payloads/coreinfo/AUTHORS @@ -0,0 +1,14 @@ +# This is the list of coreinfo authors for copyright purposes. +# +# This does not necessarily list everyone who has contributed code, since in +# some cases, their employer may be the copyright holder. To see the full list +# of contributors, and their email addresses, see the revision history in source +# control. +# Run the below commands in the coreinfo repo for additional information. +# To see a list of contributors: git log --pretty=format:%an | sort | uniq +# For patches adding or removing a name: git log -i -S "NAME" --source --all + +Advanced Micro Devices, Inc. +Dave Jones +Jordan Crouse +Uwe Hermann diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index 3b69c0c559..eafb879363 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2008 Uwe Hermann -## ## SPDX-License-Identifier: GPL-2.0-only # For a description of the syntax of this configuration file, diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 4171796350..d842b469c4 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -1,8 +1,3 @@ -## -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2008 Uwe Hermann -## ## SPDX-License-Identifier: GPL-2.0-only src := $(CURDIR) @@ -128,10 +123,9 @@ include $(srck)/Makefile else clean: - rm -rf build/*.elf build/*.o .xcompile + rm -rf build lpbuild .xcompile distclean: clean - rm -rf build lpbuild rm -f .config* lp.config* .PHONY: clean distclean diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index 1502a559dd..5a87f28340 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" @@ -19,14 +7,12 @@ #define LINES_SHOWN 19 #define TAB_WIDTH 2 - /* Globals that are used for tracking screen state */ static char *g_buf = NULL; static s32 g_line = 0; static s32 g_lines_count = 0; static s32 g_max_cursor_line = 0; - /* Copied from libpayload/drivers/cbmem_console.c */ struct cbmem_console { u32 size; @@ -37,7 +23,6 @@ struct cbmem_console { #define CURSOR_MASK ((1 << 28) - 1) #define OVERFLOW (1 << 31) - static u32 char_width(char c, u32 cursor, u32 screen_width) { if (c == '\n') { @@ -110,7 +95,7 @@ static int bootlog_module_init(void) return -1; } - struct cbmem_console *console = lib_sysinfo.cbmem_cons; + struct cbmem_console *console = phys_to_virt(lib_sysinfo.cbmem_cons); if (console == NULL) { return -1; } diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index f22453e4e8..adbe2778aa 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2009 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include "endian.h" diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 074d73a475..87032d5990 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 35e5016ae6..b357f97988 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/coreinfo.h b/payloads/coreinfo/coreinfo.h index 004a5e9663..b96af89efd 100644 --- a/payloads/coreinfo/coreinfo.h +++ b/payloads/coreinfo/coreinfo.h @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef COREINFO_H_ #define COREINFO_H_ diff --git a/payloads/coreinfo/cpuid.S b/payloads/coreinfo/cpuid.S index b004052080..84cdc77874 100644 --- a/payloads/coreinfo/cpuid.S +++ b/payloads/coreinfo/cpuid.S @@ -1,18 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ /* calling syntax: docpuid(idx,eax,ebx,ecx,edx) */ diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 96c495a170..b937e4c1d4 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -1,19 +1,6 @@ -/* - * - * It is derived from the x86info project, which is GPLv2-licensed. - * - * Copyright (C) 2001-2007 Dave Jones - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* It is derived from the x86info project, which is GPLv2-licensed. */ #include "coreinfo.h" diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index dd5ce366fb..2ec9929b60 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Jordan Crouse - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include "coreinfo.h" diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c index 9ac734a76c..99c6e9b69f 100644 --- a/payloads/coreinfo/nvram_module.c +++ b/payloads/coreinfo/nvram_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 019f8d05a4..0385e9d73a 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index abb8472ff5..762707f5e5 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -1,16 +1,4 @@ -/* - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index 32f1866693..3a24930748 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -1,14 +1,4 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "coreinfo.h" #include @@ -147,7 +137,7 @@ static int timestamps_module_init(void) if (ret) return -1; - struct timestamp_table *timestamps = lib_sysinfo.tstamp_table; + struct timestamp_table *timestamps = phys_to_virt(lib_sysinfo.tstamp_table); if (timestamps == NULL) return -1; diff --git a/payloads/external/BOOTBOOT/Kconfig b/payloads/external/BOOTBOOT/Kconfig new file mode 100644 index 0000000000..c9d7133b71 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig @@ -0,0 +1,6 @@ +if PAYLOAD_BOOTBOOT + +config PAYLOAD_FILE + default "payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf" + +endif diff --git a/payloads/external/BOOTBOOT/Kconfig.name b/payloads/external/BOOTBOOT/Kconfig.name new file mode 100644 index 0000000000..082a9b1ec2 --- /dev/null +++ b/payloads/external/BOOTBOOT/Kconfig.name @@ -0,0 +1,8 @@ +config PAYLOAD_BOOTBOOT + bool "BOOTBOOT" + depends on ARCH_X86 || ARCH_ARM64 + help + Select this option if you want to build a coreboot image + with a BOOTBOOT Protocol payload. + + See https://gitlab.com/bztsrc/bootboot for more information. diff --git a/payloads/external/BOOTBOOT/Makefile b/payloads/external/BOOTBOOT/Makefile new file mode 100644 index 0000000000..2460c183bb --- /dev/null +++ b/payloads/external/BOOTBOOT/Makefile @@ -0,0 +1,44 @@ +project_git_repo=https://gitlab.com/bztsrc/bootboot.git +project_dir=bootboot +ifeq ($(CONFIG_COREBOOT_BUILD),) +include ../../../.config +endif +ifeq ($(CONFIG_ARCH_ARM64),y) +loader_dir=$(project_dir)/aarch64-cb +else +loader_dir=$(project_dir)/x86_64-cb +endif + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +all: bootboot + +checkout: + echo " GIT BOOTBOOT $(loader_dir)" + test -L $(project_dir) || test -d $(project_dir) || \ + git clone $(project_git_repo) $(project_dir) + +bootboot: libpayload + echo " MAKE $(loader_dir)" + $(MAKE) -C $(loader_dir) LIBCONFIG_PATH=../../../libpayload + +libpayload: checkout + cp $(loader_dir)/lib.config ../../libpayload/.config + cd ../../libpayload && $(MAKE) oldconfig && \ + $(MAKE) && $(MAKE) DESTDIR=../external/BOOTBOOT/$(loader_dir) install + +clean: + test -d $(loader_dir) && $(MAKE) -C $(loader_dir) clean || exit 0 + +distclean: + rm -rf $(project_dir) + +print-repo-info: + echo "$(project_git_repo) $(project_dir)" + +.PHONY: checkout bootboot libpayload clean distclean print-repo-info diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 591d649d8f..6171217ee2 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -135,7 +135,6 @@ config LINUXBOOT_KERNEL_UIMAGE endchoice - config LINUXBOOT_DTB_FILE string "Compiled devicetree file" depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ef0990c9b7..da199e4bd3 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -303,3 +303,8 @@ payloads/external/Yabits/uefi/build/uefi.elf yabits: CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ MFLAGS= MAKEFLAGS= + +# BOOTBOOT + +payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf: + $(MAKE) -C payloads/external/BOOTBOOT all diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 21e47206f4..9aea2d012b 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.13.0" + bool "1.14.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index cd646d9d73..cdcd426770 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069 +TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 253bfea9dd..9473c02c57 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -18,9 +18,9 @@ patch: download cd tint; \ if [ -e debian ]; then \ rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi + touch Makefile; \ + patch -l -p1 < ../libpayload_tint.patch; \ + fi download: test -d tint || { wget $(project_url); \ diff --git a/payloads/libpayload/arch/arm/cpu.S b/payloads/libpayload/arch/arm/cpu.S index 4a1d41dc4d..a5ff12dc3d 100644 --- a/payloads/libpayload/arch/arm/cpu.S +++ b/payloads/libpayload/arch/arm/cpu.S @@ -81,7 +81,7 @@ lsl ip, ip, r2 @ shift by that into way position mov r0, #1 lsl r2, r0, r2 @ r2 now contains the way decr - mov r0, r3 @ get sets/level (no way yet) + mov r0, r3 @ get sets/level (no way yet) orr r3, r3, ip @ merge way into way/set/level bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1 sub r2, r2, r0 @ subtract from way decr diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 1fa9ced1be..cb0081b789 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -625,14 +625,10 @@ static void mmu_extract_ranges(struct memrange *cb_ranges, static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) { struct mmu_memrange *fb_range; - static struct cb_framebuffer modified_fb; - struct cb_framebuffer *framebuffer = lib_sysinfo.framebuffer; + struct cb_framebuffer *framebuffer = &lib_sysinfo.framebuffer; uint32_t fb_size; /* Check whether framebuffer is needed */ - if (framebuffer == NULL) - return; - fb_size = framebuffer->bytes_per_line * framebuffer->y_resolution; if (!fb_size) return; @@ -652,16 +648,7 @@ static void mmu_add_fb_range(struct mmu_ranges *mmu_ranges) if (fb_range == NULL) mmu_error(); - /* - * Set framebuffer address. However, one needs to use a freshly - * allocated framebuffer structure because the one in the coreboot - * table is part of a checksum calculation. Therefore, one cannot - * modify a field without recomputing the necessary checksum - * calcuation. - */ - modified_fb = *framebuffer; - modified_fb.physical_address = fb_range->base; - lib_sysinfo.framebuffer = &modified_fb; + framebuffer->physical_address = fb_range->base; } /* diff --git a/payloads/libpayload/arch/arm64/virtual.c b/payloads/libpayload/arch/arm64/virtual.c index 2d336e301e..9450ac0d86 100644 --- a/payloads/libpayload/arch/arm64/virtual.c +++ b/payloads/libpayload/arch/arm64/virtual.c @@ -30,7 +30,6 @@ unsigned long virtual_offset = 0; - int getpagesize(void) { return 4096; diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index 2be47bc0ce..05cf58b446 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -52,5 +52,4 @@ config DIE_ON_UNKNOWN_INTERRUPT endchoice - endif diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 62011612a5..e0671064c8 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -127,7 +127,6 @@ void apic_start_delay(unsigned int usec) enable_interrupts(); } - void apic_wait_delay(void) { /* Loop in case another interrupt has fired and resumed execution. */ diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index bf16b71f97..38ede875c7 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -49,7 +49,7 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) { - info->mrc_cache = get_cbmem_ptr(ptr); + info->mrc_cache = get_cbmem_addr(ptr); } int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c index df2c0ac9ba..373c8417b3 100644 --- a/payloads/libpayload/arch/x86/delay.c +++ b/payloads/libpayload/arch/x86/delay.c @@ -38,7 +38,6 @@ /* Let's assume APIC interrupts take at least 100us */ #define APIC_INTERRUPT_LATENCY_NS (100 * NSECS_PER_USEC) - void arch_ndelay(uint64_t ns) { uint64_t delta = ns * timer_hz() / NSECS_PER_SEC; diff --git a/payloads/libpayload/arch/x86/virtual.c b/payloads/libpayload/arch/x86/virtual.c index 2d336e301e..9450ac0d86 100644 --- a/payloads/libpayload/arch/x86/virtual.c +++ b/payloads/libpayload/arch/x86/virtual.c @@ -30,7 +30,6 @@ unsigned long virtual_offset = 0; - int getpagesize(void) { return 4096; diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 896039ea0b..4ef1ed15b7 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -5,4 +5,4 @@ CONFIG_LP_USB_UHCI=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -CONFIG_LP_HEAP_SIZE=262144 +CONFIG_LP_HEAP_SIZE=1048576 diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c index fce96a3463..5f54431a82 100644 --- a/payloads/libpayload/crypto/sha1.c +++ b/payloads/libpayload/crypto/sha1.c @@ -115,7 +115,6 @@ SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH]) a = b = c = d = e = 0; } - /* * SHA1Init - Initialize new context */ @@ -132,7 +131,6 @@ SHA1Init(SHA1_CTX *context) context->state[4] = 0xC3D2E1F0; } - /* * Run your data through this. */ @@ -155,7 +153,6 @@ SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len) (void)memcpy(&context->buffer[j], &data[i], len - i); } - /* * Add padding and return the message digest. */ diff --git a/payloads/libpayload/curses/PDCurses/demos/tui.c b/payloads/libpayload/curses/PDCurses/demos/tui.c index 62e0d53767..41f34ba410 100644 --- a/payloads/libpayload/curses/PDCurses/demos/tui.c +++ b/payloads/libpayload/curses/PDCurses/demos/tui.c @@ -46,14 +46,12 @@ void rmerror(void); # define EDITBOXCOLOR (A_BOLD | A_REVERSE) #endif - #define th 1 /* title window height */ #define mh 1 /* main menu height */ #define sh 2 /* status window height */ #define bh (LINES - th - mh - sh) /* body window height */ #define bw COLS /* body window width */ - /******************************* STATIC ************************************/ static WINDOW *wtitl, *wmain, *wbody, *wstat; /* title, menu, body, status win*/ @@ -360,7 +358,6 @@ static void cleanup(void) /* cleanup curses settings */ } } - /******************************* EXTERNAL **********************************/ void clsbody(void) diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c index e77d2c78ce..b96a027282 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.c @@ -116,7 +116,6 @@ ScrollBoxClassRec scrollBoxClassRec = { WidgetClass scrollBoxWidgetClass = (WidgetClass)&scrollBoxClassRec; - /************************************************************************ * * * Private Routines * diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h index 5825862744..9ba7d67331 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBox.h @@ -42,7 +42,6 @@ */ - /* Class record constants */ extern WidgetClass scrollBoxWidgetClass; diff --git a/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h b/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h index 44551386bc..902edeebb7 100644 --- a/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h +++ b/payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h @@ -56,7 +56,6 @@ typedef struct { XtGeometryMask last_query_mode; } ScrollBoxPart; - /************************************************************************ * * * Full instance record declaration * diff --git a/payloads/libpayload/curses/PDCurses/x11/x11.c b/payloads/libpayload/curses/PDCurses/x11/x11.c index 69c3199b54..46444d4471 100644 --- a/payloads/libpayload/curses/PDCurses/x11/x11.c +++ b/payloads/libpayload/curses/PDCurses/x11/x11.c @@ -276,7 +276,6 @@ static char *program_name; #define RCOLOR(name, value) RPIXEL(color##name, Color##name, value) - #define RSTRINGP(name1, name2, param) { \ #name1, #name2, XtRString, \ MAX_PATH, APPDATAOFF(name1), XtRString, (XtPointer)param \ diff --git a/payloads/libpayload/curses/curses.priv.h b/payloads/libpayload/curses/curses.priv.h index 78b7ff3cc9..31ec80f1bb 100644 --- a/payloads/libpayload/curses/curses.priv.h +++ b/payloads/libpayload/curses/curses.priv.h @@ -32,7 +32,6 @@ * and: Thomas E. Dickey 1996-on * ****************************************************************************/ - /* * $Id: curses.priv.h,v 1.314 2006/12/10 00:55:14 tom Exp $ * @@ -497,7 +496,6 @@ struct screen { chtype * _acs_map; /* the real alternate-charset map */ bool * _screen_acs_map; - /* used in lib_vidattr.c */ bool _use_rmso; /* true if we may use 'rmso' */ bool _use_rmul; /* true if we may use 'rmul' */ @@ -980,7 +978,6 @@ extern NCURSES_EXPORT(void) name (void); \ }\ TR(TRACE_ATTRS, ("new attribute is %s", _traceattr((S))));} - #define toggle_attr_off(S,at) {\ if (PAIR_NUMBER(at) > 0) {\ (S) &= ~(at|A_COLOR);\ diff --git a/payloads/libpayload/curses/form/form.h b/payloads/libpayload/curses/form/form.h index d7bb85adf4..2f55e42591 100644 --- a/payloads/libpayload/curses/form/form.h +++ b/payloads/libpayload/curses/form/form.h @@ -106,7 +106,6 @@ typedef struct fieldnode { NCURSES_FIELD_INTERNALS } FIELD; - /********* * FORM * *********/ @@ -138,7 +137,6 @@ typedef struct formnode { } FORM; - /************** * FIELDTYPE * **************/ diff --git a/payloads/libpayload/curses/menu/eti.h b/payloads/libpayload/curses/menu/eti.h index baa6190d8f..152ada76ce 100644 --- a/payloads/libpayload/curses/menu/eti.h +++ b/payloads/libpayload/curses/menu/eti.h @@ -36,19 +36,19 @@ #define NCURSES_ETI_H_incl 1 #define E_OK (0) -#define E_SYSTEM_ERROR (-1) -#define E_BAD_ARGUMENT (-2) -#define E_POSTED (-3) -#define E_CONNECTED (-4) -#define E_BAD_STATE (-5) -#define E_NO_ROOM (-6) +#define E_SYSTEM_ERROR (-1) +#define E_BAD_ARGUMENT (-2) +#define E_POSTED (-3) +#define E_CONNECTED (-4) +#define E_BAD_STATE (-5) +#define E_NO_ROOM (-6) #define E_NOT_POSTED (-7) #define E_UNKNOWN_COMMAND (-8) #define E_NO_MATCH (-9) #define E_NOT_SELECTABLE (-10) -#define E_NOT_CONNECTED (-11) +#define E_NOT_CONNECTED (-11) #define E_REQUEST_DENIED (-12) -#define E_INVALID_FIELD (-13) +#define E_INVALID_FIELD (-13) #define E_CURRENT (-14) #endif diff --git a/payloads/libpayload/curses/menu/menu.h b/payloads/libpayload/curses/menu/menu.h index 1fdd9e795d..1df980c551 100644 --- a/payloads/libpayload/curses/menu/menu.h +++ b/payloads/libpayload/curses/menu/menu.h @@ -132,7 +132,6 @@ typedef struct tagMENU } MENU; - /* Define keys */ #define REQ_LEFT_ITEM (KEY_MAX + 1) @@ -170,7 +169,6 @@ typedef struct tagMENU # define MAX_COMMAND (KEY_MAX + 128) #endif - /* --------- prototypes for libmenu functions ----------------------------- */ extern NCURSES_EXPORT(ITEM **) menu_items (const MENU *); @@ -244,7 +242,6 @@ extern NCURSES_EXPORT(int) menu_request_by_name (const char *); extern NCURSES_EXPORT(int) set_menu_spacing (MENU *,int,int,int); extern NCURSES_EXPORT(int) menu_spacing (const MENU *,int *,int *,int *); - extern NCURSES_EXPORT(bool) item_value (const ITEM *); extern NCURSES_EXPORT(bool) item_visible (const ITEM *); diff --git a/payloads/libpayload/curses/menu/mf_common.h b/payloads/libpayload/curses/menu/mf_common.h index 681672dc34..d40c7b9806 100644 --- a/payloads/libpayload/curses/menu/mf_common.h +++ b/payloads/libpayload/curses/menu/mf_common.h @@ -66,7 +66,6 @@ extern int errno; #define MODULE_ID(id) /*nothing*/ #endif - /* Maximum regular 8-bit character code */ #define MAX_REGULAR_CHARACTER (0xff) diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index ffd9bd4769..d3bf84efab 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -163,7 +163,6 @@ chtype console_acs_map[128] = // FIXME: Ugly (and insecure!) hack! char sprintf_tmp[1024]; - int curses_flags = (F_ENABLE_CONSOLE | F_ENABLE_SERIAL); /* Return bit mask for clearing color pair number if given ch has color */ diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c index 053802cbd9..22d5312c3a 100644 --- a/payloads/libpayload/drivers/cbmem_console.c +++ b/payloads/libpayload/drivers/cbmem_console.c @@ -38,7 +38,7 @@ struct cbmem_console { #define CURSOR_MASK ((1 << 28) - 1) #define OVERFLOW (1 << 31) -static struct cbmem_console *cbmem_console_p; +static uintptr_t cbmem_console_p; static struct console_output_driver cbmem_console_driver = { @@ -47,27 +47,32 @@ static struct console_output_driver cbmem_console_driver = static void do_write(const void *buffer, size_t count) { - memcpy(cbmem_console_p->body + (cbmem_console_p->cursor & CURSOR_MASK), - buffer, count); - cbmem_console_p->cursor += count; + struct cbmem_console *const cbmem_cons = phys_to_virt(cbmem_console_p); + + memcpy(cbmem_cons->body + (cbmem_cons->cursor & CURSOR_MASK), buffer, count); + cbmem_cons->cursor += count; } void cbmem_console_init(void) { + const struct cbmem_console *const cbmem_cons = phys_to_virt(lib_sysinfo.cbmem_cons); + cbmem_console_p = lib_sysinfo.cbmem_cons; - if (cbmem_console_p && cbmem_console_p->size) + + if (cbmem_console_p && cbmem_cons->size) console_add_output_driver(&cbmem_console_driver); } void cbmem_console_write(const void *buffer, size_t count) { - while ((cbmem_console_p->cursor & CURSOR_MASK) + count >= - cbmem_console_p->size) { - size_t still_fits = cbmem_console_p->size - - (cbmem_console_p->cursor & CURSOR_MASK); + struct cbmem_console *const cbmem_cons = phys_to_virt(cbmem_console_p); + + while ((cbmem_cons->cursor & CURSOR_MASK) + count >= + cbmem_cons->size) { + size_t still_fits = cbmem_cons->size - (cbmem_cons->cursor & CURSOR_MASK); do_write(buffer, still_fits); - cbmem_console_p->cursor &= ~CURSOR_MASK; - cbmem_console_p->cursor |= OVERFLOW; + cbmem_cons->cursor &= ~CURSOR_MASK; + cbmem_cons->cursor |= OVERFLOW; buffer += still_fits; count -= still_fits; } @@ -77,7 +82,7 @@ void cbmem_console_write(const void *buffer, size_t count) char *cbmem_console_snapshot(void) { - const struct cbmem_console *console_p = cbmem_console_p; + const struct cbmem_console *const console_p = phys_to_virt(cbmem_console_p); char *console_c; uint32_t size, cursor, overflow; diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index 40bd2fc882..4794e9b249 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -42,7 +42,6 @@ #include #include - /** * PCs can have either 64 (very old ones), 128, or 256 bytes of CMOS RAM. * diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 3a14d77df9..b6d234222d 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -26,8 +26,11 @@ * SUCH DAMAGE. */ +#define __STDC_FORMAT_MACROS + #include #include +#include u8 *mem_accessor_base; @@ -53,7 +56,7 @@ struct nvram_accessor *use_mem = &(struct nvram_accessor) { struct cb_cmos_option_table *get_system_option_table(void) { - return lib_sysinfo.option_table; + return phys_to_virt(lib_sysinfo.cmos_option_table); } int options_checksum_valid(const struct nvram_accessor *nvram) @@ -325,7 +328,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti /* only works on little endian. 26 bytes is enough for a 64bit value in decimal */ *dest = malloc(26); - sprintf(*dest, "%llu", *(u64*)raw); + sprintf(*dest, "%" PRIu64, *(u64 *)raw); break; case 's': *dest = strdup(raw); diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index b0e9d03c20..1df34c41ea 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -132,9 +132,9 @@ void serial_init(void) void serial_console_init(void) { - if (!lib_sysinfo.serial) + if (!lib_sysinfo.cb_serial) return; - cb_serial = *lib_sysinfo.serial; + cb_serial = *(struct cb_serial *)phys_to_virt(lib_sysinfo.cb_serial); serial_init(); diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 5a9079b46b..bc5ebbbc1b 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -553,9 +553,7 @@ static struct console_output_driver consout = {}; /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; - - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; consin.havekey = serial_havechar; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index ef4ce80849..93e2129185 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -343,9 +343,9 @@ int serial_getchar(void) /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; + struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial); - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; base_uart_addr = (void *) sc_ptr->baseaddr; diff --git a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c index 3d0e6de335..77def46831 100644 --- a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c +++ b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c @@ -27,7 +27,6 @@ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - /* For simplicity sake let's rely on coreboot initializing the UART. */ #include #include @@ -275,7 +274,8 @@ static struct console_output_driver consout = { static struct qup_regs *uart_base_address(void) { - return (void *)(uintptr_t)lib_sysinfo.serial->baseaddr; + const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial); + return phys_to_virt(serial->baseaddr); } static void uart_qupv3_tx_flush(void) @@ -332,7 +332,7 @@ int serial_getchar(void) void serial_console_init(void) { - if (!lib_sysinfo.serial) + if (!lib_sysinfo.cb_serial) return; console_add_output_driver(&consout); diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 1a7b9e901b..2ed6af1749 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -541,9 +541,9 @@ int serial_getchar(void) /* For simplicity's sake, let's rely on coreboot initializing the UART. */ void serial_console_init(void) { - struct cb_serial *sc_ptr = lib_sysinfo.serial; + struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial); - if (!sc_ptr) + if (!lib_sysinfo.cb_serial) return; uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr; diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c index 6ca5dc4717..7a6f0e1c39 100644 --- a/payloads/libpayload/drivers/serial/s5p.c +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -90,10 +90,12 @@ static struct console_input_driver s5p_serial_input = void serial_init(void) { - if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + const struct cb_serial *const serial = phys_to_virt(lib_sysinfo.cb_serial); + + if (!lib_sysinfo.cb_serial || !serial->baseaddr) return; - uart_regs = (struct s5p_uart *)lib_sysinfo.serial->baseaddr; + uart_regs = (struct s5p_uart *)serial->baseaddr; } void serial_console_init(void) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 9f9b9b589a..ff22b19b71 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -39,7 +39,6 @@ #include "ahci_private.h" - #ifdef DEBUG_STATUS static inline u32 _ahci_clear_status(volatile u32 *const reg, const char *const r, @@ -64,7 +63,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg) #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r) #endif - static inline int ahci_port_is_active(const hba_port_t *const port) { return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK)) diff --git a/payloads/libpayload/drivers/storage/ahci_ata.c b/payloads/libpayload/drivers/storage/ahci_ata.c index 514692e39f..062b7ac71b 100644 --- a/payloads/libpayload/drivers/storage/ahci_ata.c +++ b/payloads/libpayload/drivers/storage/ahci_ata.c @@ -37,7 +37,6 @@ #include "ahci_private.h" - ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev, const lba_t start, size_t count, u8 *const buf) diff --git a/payloads/libpayload/drivers/storage/ahci_atapi.c b/payloads/libpayload/drivers/storage/ahci_atapi.c index 9984b4b78d..1a757d7e9b 100644 --- a/payloads/libpayload/drivers/storage/ahci_atapi.c +++ b/payloads/libpayload/drivers/storage/ahci_atapi.c @@ -35,10 +35,8 @@ #include #include - #include "ahci_private.h" - ssize_t ahci_packet_read_cmd(atapi_dev_t *const _dev, const u8 *const cmd, const size_t cmdlen, u8 *const buf, const size_t buflen) diff --git a/payloads/libpayload/drivers/storage/ahci_common.c b/payloads/libpayload/drivers/storage/ahci_common.c index b8fdad202c..f3abc5f7fb 100644 --- a/payloads/libpayload/drivers/storage/ahci_common.c +++ b/payloads/libpayload/drivers/storage/ahci_common.c @@ -37,7 +37,6 @@ #include "ahci_private.h" - #ifdef DEBUG_STATUS static inline u32 _ahci_clear_status(volatile u32 *const reg, const char *const r, @@ -62,7 +61,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg) #define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r) #endif - /** Give a buffer with even address. */ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev, u8 *const user_buf, const size_t len, diff --git a/payloads/libpayload/drivers/storage/ahci_private.h b/payloads/libpayload/drivers/storage/ahci_private.h index 7f7c592048..1e8c85f199 100644 --- a/payloads/libpayload/drivers/storage/ahci_private.h +++ b/payloads/libpayload/drivers/storage/ahci_private.h @@ -120,7 +120,6 @@ typedef volatile struct { #define HBA_CTRL_INTR_EN (1 << 1) #define HBA_CTRL_RESET (1 << 0) - typedef volatile struct { u8 dma_setup_fis[28]; u8 _reserved0[4]; @@ -229,5 +228,4 @@ ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev, const lba_t start, size_t count, u8 *const buf); - #endif /* _AHCI_PRIVATE_H */ diff --git a/payloads/libpayload/drivers/storage/ata.c b/payloads/libpayload/drivers/storage/ata.c index 68f88f6eb7..00f1d88854 100644 --- a/payloads/libpayload/drivers/storage/ata.c +++ b/payloads/libpayload/drivers/storage/ata.c @@ -33,7 +33,6 @@ #include - /** Reads non-sector-aligned blocks of 512 bytes. */ static ssize_t ata_read_unaligned(ata_dev_t *const dev, const lba_t blk_start, size_t blk_count, diff --git a/payloads/libpayload/drivers/storage/atapi.c b/payloads/libpayload/drivers/storage/atapi.c index f42c1f4b80..7f46e9cc3e 100644 --- a/payloads/libpayload/drivers/storage/atapi.c +++ b/payloads/libpayload/drivers/storage/atapi.c @@ -33,7 +33,6 @@ #include #include - static int atapi_request_sense(atapi_dev_t *const dev) { u8 cdb[12] = { 0, }; diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index 3ddafdce07..24b9024a93 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -32,7 +32,6 @@ #endif #include - static storage_dev_t **devices = NULL; static size_t devices_length = 0; static size_t dev_count = 0; diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index dd1601367b..3df7d2409c 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -300,7 +300,6 @@ static void start_setup(struct usbdev_ctrl *this, int ep) udc_handle_setup(this, ep, &dr); } - static void chipidea_enqueue_packet(struct usbdev_ctrl *this, int endpoint, int in_dir, void *data, int len, int zlp, int autofree) { diff --git a/payloads/libpayload/drivers/usb/dwc2_rh.c b/payloads/libpayload/drivers/usb/dwc2_rh.c index ff15e9902d..c0f25f907a 100644 --- a/payloads/libpayload/drivers/usb/dwc2_rh.c +++ b/payloads/libpayload/drivers/usb/dwc2_rh.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ - #include #include "generic_hub.h" #include "dwc2_private.h" diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index cb3c1c543e..97caf202d9 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -426,7 +426,6 @@ oom: return -1; } - /* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, u8 *src) @@ -544,7 +543,6 @@ oom: return -1; } - typedef struct _intr_qtd_t intr_qtd_t; struct _intr_qtd_t { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index e51f332822..edb1b4ad4d 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -171,7 +171,6 @@ ehci_rh_poll (usbdev_t *dev) ehci_rh_scanport (dev, port); } - void ehci_rh_init (usbdev_t *dev) { diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 87674eec6b..ec14144711 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -627,7 +627,6 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) return result; } - struct _intr_queue; struct _intrq_td { diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index b14abb4b35..ec49a5481e 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -275,7 +275,7 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0) bMaxPacketSize0 = 9; } return 1 << bMaxPacketSize0; - default: /* GCC is stupid and cannot deal with enums correctly */ + default: /* GCC is stupid and cannot deal with enums correctly */ return 8; } } diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 921e17608e..87e87411fe 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -131,8 +131,6 @@ const char *countries[36][2] = { /* 36 - 255: Reserved */ }; - - struct layout_maps { const char *country; const short map[4][0x80]; @@ -247,7 +245,6 @@ static const struct layout_maps keyboard_layouts[] = { //#endif }; - static void usb_hid_keyboard_queue(int ch) { /* ignore key presses if buffer full */ if (keycount < KEYBOARD_BUFFER_SIZE) @@ -316,7 +313,6 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst, if (skip) continue; - /* Mask off KB_MOD_CTRL */ keypress = map->map[modifiers & 0x03][current->keys[i]]; @@ -397,7 +393,6 @@ static struct console_input_driver cons = { .input_type = CONSOLE_INPUT_TYPE_USB, }; - static int usb_hid_set_layout (const char *country) { /* FIXME should be per keyboard */ diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c old mode 100755 new mode 100644 index ed91c9938b..96c4946b76 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -613,7 +613,6 @@ usb_msc_init (usbdev_t *dev) usb_debug (" it uses %s protocol\n", msc_protocol_strings[interface->bInterfaceProtocol]); - if (interface->bInterfaceProtocol != 0x50) { usb_debug (" Protocol not supported.\n"); usb_detach_device (dev->controller, dev->address); diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c index d633cc5762..a4078030c6 100644 --- a/payloads/libpayload/drivers/usb/xhci_commands.c +++ b/payloads/libpayload/drivers/usb/xhci_commands.c @@ -75,7 +75,13 @@ xhci_wait_for_command(xhci_t *const xhci, /* Abort command on timeout */ xhci_debug("Aborting command (@%p), CRCR: 0x%"PRIx32"\n", cmd_trb, xhci->opreg->crcr_lo); - xhci->opreg->crcr_lo |= CRCR_CS | CRCR_CA; + /* + * Ref. xHCI Specification Revision 1.2, May 2019. + * Section 5.4.5, Table 5-24. + * + * Abort the command and stop the ring. + */ + xhci->opreg->crcr_lo |= CRCR_CA; xhci->opreg->crcr_hi = 0; cc = xhci_wait_for_command_aborted(xhci, cmd_trb); diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c index 32a43fcfeb..139ea59619 100644 --- a/payloads/libpayload/drivers/usb/xhci_events.c +++ b/payloads/libpayload/drivers/usb/xhci_events.c @@ -226,7 +226,15 @@ xhci_wait_for_event_type(xhci_t *const xhci, return *timeout_us; } -/* returns cc of command in question (pointed to by `address`) */ +/* + * Ref. xHCI Specification Revision 1.2, May 2019. + * Section 4.6.1.2. + * + * Process events from xHCI Abort command. + * + * Returns CC_COMMAND_RING_STOPPED on success and TIMEOUT on failure. + */ + int xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) { @@ -239,12 +247,13 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) int cc = TIMEOUT; /* * Expects two command completion events: - * The first with CC == COMMAND_ABORTED should point to address, + * The first with CC == COMMAND_ABORTED should point to address + * (not present if command was not running), * the second with CC == COMMAND_RING_STOPPED should point to new dq. */ while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if ((xhci->er.cur->ptr_low == virt_to_phys(address)) && - (xhci->er.cur->ptr_high == 0)) { + (xhci->er.cur->ptr_high == 0)) { cc = TRB_GET(CC, xhci->er.cur); xhci_advance_event_ring(xhci); break; @@ -252,20 +261,31 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) xhci_handle_command_completion_event(xhci); } - if (!timeout_us) - xhci_debug("Warning: Timed out waiting for COMMAND_ABORTED.\n"); + if (timeout_us == 0) { + xhci_debug("Warning: Timed out waiting for " + "COMMAND_ABORTED or COMMAND_RING_STOPPED.\n"); + goto update_and_return; + } + if (cc == CC_COMMAND_RING_STOPPED) { + /* There may not have been a command to abort. */ + goto update_and_return; + } + + timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */ while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if (TRB_GET(CC, xhci->er.cur) == CC_COMMAND_RING_STOPPED) { - xhci->cr.cur = phys_to_virt(xhci->er.cur->ptr_low); + cc = CC_COMMAND_RING_STOPPED; xhci_advance_event_ring(xhci); break; } xhci_handle_command_completion_event(xhci); } - if (!timeout_us) + if (timeout_us == 0) xhci_debug("Warning: Timed out " "waiting for COMMAND_RING_STOPPED.\n"); + +update_and_return: xhci_update_event_dq(xhci); return cc; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 8e11937ac5..34d3651daf 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -204,7 +204,7 @@ typedef transfer_ring_t command_ring_t; #define SC_UADDR_LEN 8 #define SC_STATE_FIELD f4 /* STATE - Slot State */ #define SC_STATE_START 27 -#define SC_STATE_LEN 8 +#define SC_STATE_LEN 5 #define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN) #define SC_GET(tok, sc) (((sc)->SC_##tok##_FIELD & SC_MASK(tok)) \ >> SC_##tok##_START) @@ -363,7 +363,7 @@ typedef struct erst_entry { #define CAP_CSZ_LEN 1 #define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN) -#define CAP_GET(tok, cap) (((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \ +#define CAP_GET(tok, cap) ((read32(&(cap)->CAP_##tok##_FIELD) & CAP_MASK(tok)) \ >> CAP_##tok##_START) #define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32) @@ -515,7 +515,6 @@ static inline int xhci_ep_id(const endpoint_t *const ep) { return ((ep->endpoint & 0x7f) * 2) + (ep->direction != OUT); } - #ifdef XHCI_DUMPS void xhci_dump_slotctx(const slotctx_t *); void xhci_dump_epctx(const epctx_t *); diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 9b711c8586..bf4c2bc5c1 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -135,7 +135,6 @@ xhci_rh_enable_port(usbdev_t *const dev, int port) return 0; } - static const generic_hub_ops_t xhci_rh_ops = { .hub_status_changed = xhci_rh_hub_status_changed, .port_status_changed = xhci_rh_port_status_changed, diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index c21665d0c0..51922d9b06 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -60,7 +60,7 @@ static const u32 vga_colors[] = { (0xFF << 16) | (0xFF << 8) | 0xFF, }; -struct cb_framebuffer fbinfo; +static struct cb_framebuffer fbinfo; static unsigned short *chars; /* Shorthand for up-to-date virtual framebuffer address */ @@ -138,7 +138,6 @@ static void corebootfb_putchar(u8 row, u8 col, unsigned int ch) ((((vga_colors[fg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos); } - dst = FB + ((row * font_height) * fbinfo.bytes_per_line); dst += (col * font_width * (fbinfo.bits_per_pixel >> 3)); @@ -223,13 +222,10 @@ static void corebootfb_set_cursor(unsigned int x, unsigned int y) static int corebootfb_init(void) { - if (lib_sysinfo.framebuffer == NULL) + if (!lib_sysinfo.framebuffer.physical_address) return -1; - fbinfo = *lib_sysinfo.framebuffer; - - if (fbinfo.physical_address == 0) - return -1; + fbinfo = lib_sysinfo.framebuffer; font_init(fbinfo.x_resolution); diff --git a/payloads/libpayload/drivers/video/geodelx.c b/payloads/libpayload/drivers/video/geodelx.c index 7c51fc21e6..8799bca669 100644 --- a/payloads/libpayload/drivers/video/geodelx.c +++ b/payloads/libpayload/drivers/video/geodelx.c @@ -176,7 +176,6 @@ static void init_video_mode(void) writel(((vga_mode.hactive - 1) << 16) | (vga_mode.vactive - 1), DC + 0x5C); - /* Write the VG configuration */ writel(0x290000F | vga_mode.synccfg, VG + 0x08); diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 54d3dfa2b2..563f2961c7 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -41,12 +41,17 @@ static struct rect canvas; static struct rect screen; +static uint8_t *gfx_buffer; + /* * Framebuffer is assumed to assign a higher coordinate (larger x, y) to * a higher address */ -static struct cb_framebuffer *fbinfo; -static uint8_t *fbaddr; +static const struct cb_framebuffer *fbinfo; + +/* Shorthand for up-to-date virtual framebuffer address */ +#define REAL_FB ((unsigned char *)phys_to_virt(fbinfo->physical_address)) +#define FB (gfx_buffer ? gfx_buffer : REAL_FB) #define LOG(x...) printf("CBGFX: " x) #define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT) @@ -61,17 +66,53 @@ static const struct vector vzero = { .y = 0, }; +struct color_transformation { + uint8_t base; + int16_t scale; +}; + +struct color_mapping { + struct color_transformation red; + struct color_transformation green; + struct color_transformation blue; + int enabled; +}; + +static struct color_mapping color_map; + +static inline void set_color_trans(struct color_transformation *trans, + uint8_t bg_color, uint8_t fg_color) +{ + trans->base = bg_color; + trans->scale = fg_color - bg_color; +} + +int set_color_map(const struct rgb_color *background, + const struct rgb_color *foreground) +{ + if (background == NULL || foreground == NULL) + return CBGFX_ERROR_INVALID_PARAMETER; + + set_color_trans(&color_map.red, background->red, foreground->red); + set_color_trans(&color_map.green, background->green, + foreground->green); + set_color_trans(&color_map.blue, background->blue, foreground->blue); + color_map.enabled = 1; + + return CBGFX_SUCCESS; +} + +void clear_color_map(void) +{ + color_map.enabled = 0; +} + struct blend_value { uint8_t alpha; struct rgb_color rgb; }; -static struct blend_value blend = { - .alpha = 0, - .rgb.red = 0, - .rgb.green = 0, - .rgb.blue = 0, -}; +static struct blend_value blend; int set_blend(const struct rgb_color *rgb, uint8_t alpha) { @@ -99,6 +140,11 @@ static void add_vectors(struct vector *out, out->y = v1->y + v2->y; } +static int fraction_equal(const struct fraction *f1, const struct fraction *f2) +{ + return (int64_t)f1->n * f2->d == (int64_t)f2->n * f1->d; +} + static int is_valid_fraction(const struct fraction *f) { return f->d != 0; @@ -109,17 +155,31 @@ static int is_valid_scale(const struct scale *s) return is_valid_fraction(&s->x) && is_valid_fraction(&s->y); } +static void reduce_fraction(struct fraction *out, int64_t n, int64_t d) +{ + /* Simplest way to reduce the fraction until fitting in int32_t */ + int shift = log2(MAX(ABS(n), ABS(d)) >> 31) + 1; + out->n = n >> shift; + out->d = d >> shift; +} + +/* out = f1 + f2 */ static void add_fractions(struct fraction *out, const struct fraction *f1, const struct fraction *f2) { - int64_t n, d; - int shift; - n = (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d; - d = (int64_t)f1->d * f2->d; - /* Simplest way to reduce the fraction until fitting in int32_t */ - shift = log2(MAX(ABS(n), ABS(d)) >> 31) + 1; - out->n = n >> shift; - out->d = d >> shift; + reduce_fraction(out, + (int64_t)f1->n * f2->d + (int64_t)f2->n * f1->d, + (int64_t)f1->d * f2->d); +} + +/* out = f1 - f2 */ +static void subtract_fractions(struct fraction *out, + const struct fraction *f1, + const struct fraction *f2) +{ + reduce_fraction(out, + (int64_t)f1->n * f2->d - (int64_t)f2->n * f1->d, + (int64_t)f1->d * f2->d); } static void add_scales(struct scale *out, @@ -166,6 +226,15 @@ static int within_box(const struct vector *v, const struct rect *bound) return -1; } +/* Helper function that applies color_map to the color. */ +static inline uint8_t apply_map(uint8_t color, + const struct color_transformation *trans) +{ + if (!color_map.enabled) + return color; + return trans->base + trans->scale * color / UINT8_MAX; +} + /* * Helper function that applies color and opacity from blend struct * into the color. @@ -184,13 +253,16 @@ static inline uint32_t calculate_color(const struct rgb_color *rgb, { uint32_t color = 0; - color |= (apply_blend(rgb->red, blend.rgb.red) + color |= (apply_blend(apply_map(rgb->red, &color_map.red), + blend.rgb.red) >> (8 - fbinfo->red_mask_size)) << fbinfo->red_mask_pos; - color |= (apply_blend(rgb->green, blend.rgb.green) + color |= (apply_blend(apply_map(rgb->green, &color_map.green), + blend.rgb.green) >> (8 - fbinfo->green_mask_size)) << fbinfo->green_mask_pos; - color |= (apply_blend(rgb->blue, blend.rgb.blue) + color |= (apply_blend(apply_map(rgb->blue, &color_map.blue), + blend.rgb.blue) >> (8 - fbinfo->blue_mask_size)) << fbinfo->blue_mask_pos; if (invert) @@ -229,7 +301,7 @@ static inline void set_pixel(struct vector *coord, uint32_t color) break; } - uint8_t * const pixel = fbaddr + rcoord.y * bpl + rcoord.x * bpp / 8; + uint8_t * const pixel = FB + rcoord.y * bpl + rcoord.x * bpp / 8; for (i = 0; i < bpp / 8; i++) pixel[i] = (color >> (i * 8)); } @@ -243,12 +315,9 @@ static int cbgfx_init(void) if (initialized) return 0; - fbinfo = lib_sysinfo.framebuffer; - if (!fbinfo) - return CBGFX_ERROR_FRAMEBUFFER_INFO; + fbinfo = &lib_sysinfo.framebuffer; - fbaddr = phys_to_virt((uint8_t *)(uintptr_t)(fbinfo->physical_address)); - if (!fbaddr) + if (!fbinfo->physical_address) return CBGFX_ERROR_FRAMEBUFFER_ADDR; switch (fbinfo->orientation) { @@ -477,6 +546,59 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, return CBGFX_SUCCESS; } +int draw_line(const struct scale *pos1, const struct scale *pos2, + const struct fraction *thickness, const struct rgb_color *rgb) +{ + struct fraction len; + struct vector top_left; + struct vector size; + struct vector p, t; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + const uint32_t color = calculate_color(rgb, 0); + + if (!is_valid_fraction(thickness)) + return CBGFX_ERROR_INVALID_PARAMETER; + + transform_vector(&top_left, &canvas.size, pos1, &canvas.offset); + if (fraction_equal(&pos1->y, &pos2->y)) { + /* Horizontal line */ + subtract_fractions(&len, &pos2->x, &pos1->x); + struct scale dim = { + .x = { .n = len.n, .d = len.d }, + .y = { .n = thickness->n, .d = thickness->d }, + }; + transform_vector(&size, &canvas.size, &dim, &vzero); + size.y = MAX(size.y, 1); + } else if (fraction_equal(&pos1->x, &pos2->x)) { + /* Vertical line */ + subtract_fractions(&len, &pos2->y, &pos1->y); + struct scale dim = { + .x = { .n = thickness->n, .d = thickness->d }, + .y = { .n = len.n, .d = len.d }, + }; + transform_vector(&size, &canvas.size, &dim, &vzero); + size.x = MAX(size.x, 1); + } else { + LOG("Only support horizontal and vertical lines\n"); + return CBGFX_ERROR_INVALID_PARAMETER; + } + + add_vectors(&t, &top_left, &size); + if (within_box(&t, &canvas) < 0) { + LOG("Line exceeds canvas boundary\n"); + return CBGFX_ERROR_BOUNDARY; + } + + for (p.y = top_left.y; p.y < t.y; p.y++) + for (p.x = top_left.x; p.x < t.x; p.x++) + set_pixel(&p, color); + + return CBGFX_SUCCESS; +} + int clear_canvas(const struct rgb_color *rgb) { const struct rect box = { @@ -507,7 +629,7 @@ int clear_screen(const struct rgb_color *rgb) * We assume that for 32bpp the high byte gets ignored anyway. */ if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || (((color >> 16) & 0xff) == (color & 0xff)))) { - memset(fbaddr, color & 0xff, fbinfo->y_resolution * bpl); + memset(FB, color & 0xff, fbinfo->y_resolution * bpl); } else { for (p.y = 0; p.y < screen.size.height; p.y++) for (p.x = 0; p.x < screen.size.width; p.x++) @@ -736,24 +858,25 @@ static int draw_bitmap_v3(const struct vector *top_left, } /* - * Initialize the sample array for this line. For pixels to the - * left of S0 there are no corresponding input pixels so just - * copy the S0 values over. - * - * Also initialize the equals counter, which counts how many of - * the latest pixels were exactly equal. We know the columns - * left of S0 must be equal to S0, so start with that number. + * Initialize the sample array for this line, and also + * the equals counter, which counts how many of the latest + * pixels were exactly equal. */ - int equals = S0 * SSZ; + int equals = 0; uint8_t last_equal = ypix[0][0]; - for (sy = 0; sy < SSZ; sy++) { - for (sx = S0; sx < SSZ; sx++) { - if (sx >= dim_org->width) { + for (sx = 0; sx < SSZ; sx++) { + for (sy = 0; sy < SSZ; sy++) { + if (sx - S0 >= dim_org->width) { sample[sx][sy] = sample[sx - 1][sy]; equals++; continue; } - uint8_t i = ypix[sy][sx - S0]; + /* + * For pixels to the left of S0 there are no + * corresponding input pixels so just use + * ypix[sy][0]. + */ + uint8_t i = ypix[sy][MAX(0, sx - S0)]; if (pal_to_rgb(i, pal, header->colors_used, &sample[sx][sy])) goto bitmap_error; @@ -764,8 +887,6 @@ static int draw_bitmap_v3(const struct vector *top_left, equals = 1; } } - for (sx = S0 - 1; sx >= 0; sx--) - sample[sx][sy] = sample[S0][sy]; } ix = 0; @@ -1138,3 +1259,37 @@ int get_bitmap_dimension(const void *bitmap, size_t sz, struct scale *dim_rel) return CBGFX_SUCCESS; } + +int enable_graphics_buffer(void) +{ + if (gfx_buffer) + return CBGFX_SUCCESS; + + if (cbgfx_init()) + return CBGFX_ERROR_INIT; + + size_t buffer_size = fbinfo->y_resolution * fbinfo->bytes_per_line; + gfx_buffer = malloc(buffer_size); + if (!gfx_buffer) { + LOG("%s: Failed to create graphics buffer (%zu bytes).\n", + __func__, buffer_size); + return CBGFX_ERROR_GRAPHICS_BUFFER; + } + + return CBGFX_SUCCESS; +} + +int flush_graphics_buffer(void) +{ + if (!gfx_buffer) + return CBGFX_ERROR_GRAPHICS_BUFFER; + + memcpy(REAL_FB, gfx_buffer, fbinfo->y_resolution * fbinfo->bytes_per_line); + return CBGFX_SUCCESS; +} + +void disable_graphics_buffer(void) +{ + free(gfx_buffer); + gfx_buffer = NULL; +} diff --git a/payloads/libpayload/include/cbgfx.h b/payloads/libpayload/include/cbgfx.h index 84e76f26d1..72e512267a 100644 --- a/payloads/libpayload/include/cbgfx.h +++ b/payloads/libpayload/include/cbgfx.h @@ -56,6 +56,8 @@ #define CBGFX_ERROR_FRAMEBUFFER_ADDR 0x15 /* portrait screen not supported */ #define CBGFX_ERROR_PORTRAIT_SCREEN 0x16 +/* cannot use buffered I/O */ +#define CBGFX_ERROR_GRAPHICS_BUFFER 0x17 struct fraction { int32_t n; @@ -132,6 +134,22 @@ int draw_rounded_box(const struct scale *pos_rel, const struct scale *dim_rel, const struct fraction *thickness, const struct fraction *radius); +/** + * Draw a horizontal or vertical line segment on screen. If horizontal, pos1 + * must be the left endpoint. If vertical, pos1 must be the top endpoint. When + * the specified thickness is zero (or truncated to zero), a line with 1-pixel + * width will be drawn. + * + * @param[in] pos1 Start position of the line relative to the canvas. + * @param[in] pos2 End position of the line relative to the canvas. + * @param[in] thickness Thickness of the line relative to the canvas. + * @param[in] rgb Color of the line. + * + * @return CBGFX_* error codes + */ +int draw_line(const struct scale *pos1, const struct scale *pos2, + const struct fraction *thickness, const struct rgb_color *rgb); + /** * Clear the canvas */ @@ -211,6 +229,24 @@ int draw_bitmap_direct(const void *bitmap, size_t size, */ int get_bitmap_dimension(const void *bitmap, size_t sz, struct scale *dim_rel); +/** + * Setup color mappings of background and foreground colors. Black and white + * pixels will be mapped to the background and foreground colors, respectively. + * Call clear_color_map() to disabled color mapping. + * + * @param[in] background Background color. + * @param[in] foreground Foreground color. + * + * @return CBGFX_* error codes + */ +int set_color_map(const struct rgb_color *background, + const struct rgb_color *foreground); + +/** + * Clear color mappings. + */ +void clear_color_map(void); + /** * Setup alpha and rgb values for alpha blending. When alpha is != 0, * this enables a translucent layer of color (defined by rgb) to be @@ -228,8 +264,6 @@ int set_blend(const struct rgb_color *rgb, uint8_t alpha); /** * Clear alpha and rgb values, thus disabling any alpha blending. - * - * @return CBGFX_* error codes */ void clear_blend(void); @@ -240,3 +274,24 @@ void clear_blend(void); * 0 = min alpha argument, 0% opacity */ #define ALPHA(percentage) MIN(255, (256 * percentage / 100)) + +/** + * Enable buffered I/O. All CBGFX operations will be redirected to a working + * buffer, and only updated (redrawn) when flush_graphics_buffer() is called. + * + * @return CBGFX_* error codes + */ +int enable_graphics_buffer(void); + +/** + * Redraw buffered graphics data to real screen if graphics buffer is already + * enabled. + * + * @return CBGFX_* error codes + */ +int flush_graphics_buffer(void); + +/** + * Stop using buffered I/O and release allocated memory. + */ +void disable_graphics_buffer(void); diff --git a/payloads/libpayload/include/compiler.h b/payloads/libpayload/include/compiler.h index 0d56cbea4b..ee2ff88d10 100644 --- a/payloads/libpayload/include/compiler.h +++ b/payloads/libpayload/include/compiler.h @@ -1,29 +1,39 @@ -/* - * - * Copyright 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ -#ifndef __COMPILER_H__ -#define __COMPILER_H__ +#ifndef _COMMONLIB_BSD_COMPILER_H_ +#define _COMMONLIB_BSD_COMPILER_H_ +#ifndef __packed #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) #else #define __packed __attribute__((packed)) #endif +#endif +#ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) +#endif + +#ifndef __always_unused #define __always_unused __attribute__((unused)) +#endif + +#ifndef __must_check #define __must_check __attribute__((warn_unused_result)) +#endif + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif + +#ifndef __noreturn +#define __noreturn __attribute__((noreturn)) +#endif + +#ifndef __always_inline +#define __always_inline inline __attribute__((always_inline)) +#endif /* This evaluates to the type of the first expression, unless that is constant in which case it evalutates to the type of the second. This is useful when @@ -32,7 +42,7 @@ literals. By using this macro, the promotion can happen at the time the literal is assigned to the temporary variable. If the literal doesn't fit in the chosen type, -Werror=overflow will catch it, so this should be safe. */ -#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) typeof( \ +#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) __typeof__( \ __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) /* This creates a unique local variable name for use in macros. */ diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 91d3520ad5..bf8c0d9303 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -31,6 +31,7 @@ #include #include +#include enum { CB_TAG_UNUSED = 0x0000, @@ -395,5 +396,5 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) + (sizeof((_rec)->map[0]) * (_idx))) /* Helper functions */ -void *get_cbmem_ptr(unsigned char *ptr); +uintptr_t get_cbmem_addr(const void *cbmem_tab_entry); #endif diff --git a/payloads/libpayload/include/ctype.h b/payloads/libpayload/include/ctype.h index c1ca698e1c..98cb306180 100644 --- a/payloads/libpayload/include/ctype.h +++ b/payloads/libpayload/include/ctype.h @@ -50,5 +50,4 @@ int tolower(int c); int toupper(int c); /** @} */ - #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 25080d85ed..01d71b8e61 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -456,7 +456,6 @@ static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ - /** * @defgroup mmio MMIO helper functions * @{ @@ -475,7 +474,6 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, #endif /** @} */ - /** * @defgroup hash Hashing functions * @{ diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index 7d579a7bc4..c9ac701987 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -344,7 +344,6 @@ struct { \ #define XSIMPLEQ_EMPTY(head) (XSIMPLEQ_FIRST(head) == XSIMPLEQ_END(head)) #define XSIMPLEQ_NEXT(head, elm, field) XSIMPLEQ_XOR(head, ((elm)->field.sqx_next)) - #define XSIMPLEQ_FOREACH(var, head, field) \ for ((var) = XSIMPLEQ_FIRST(head); \ (var) != XSIMPLEQ_END(head); \ @@ -398,7 +397,6 @@ struct { \ XSIMPLEQ_XOR(head, &(elm)->field.sqx_next); \ } while (0) - /* * Tail queue definitions. */ @@ -442,7 +440,6 @@ struct { \ ((tvar) = TAILQ_NEXT(var, field), 1); \ (var) = (tvar)) - #define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ for((var) = TAILQ_LAST(head, headname); \ (var) != TAILQ_END(head); \ diff --git a/payloads/libpayload/include/storage/ata.h b/payloads/libpayload/include/storage/ata.h index 39937dbe34..43249e7513 100644 --- a/payloads/libpayload/include/storage/ata.h +++ b/payloads/libpayload/include/storage/ata.h @@ -33,7 +33,6 @@ #include "storage.h" - /* ATA commands */ enum { ATA_READ_DMA = 0xc8, diff --git a/payloads/libpayload/include/storage/atapi.h b/payloads/libpayload/include/storage/atapi.h index eea5c332f8..5a6e244032 100644 --- a/payloads/libpayload/include/storage/atapi.h +++ b/payloads/libpayload/include/storage/atapi.h @@ -34,7 +34,6 @@ #include "storage.h" #include "ata.h" - /* ATAPI commands */ enum { ATAPI_TEST_UNIT_READY = 0x00, diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h index 7a2a84bef7..32933fd97c 100644 --- a/payloads/libpayload/include/storage/storage.h +++ b/payloads/libpayload/include/storage/storage.h @@ -32,14 +32,12 @@ #include #include - #if !CONFIG(LP_STORAGE_64BIT_LBA) typedef u32 lba_t; #else typedef u64 lba_t; #endif - typedef enum { PORT_TYPE_IDE = (1 << 0), PORT_TYPE_SATA = (1 << 1), @@ -54,7 +52,6 @@ typedef enum { POLL_MEDIUM_PRESENT = 1, } storage_poll_t; - struct storage_dev; typedef struct storage_dev { @@ -70,7 +67,6 @@ typedef struct storage_dev { int storage_device_count(void); int storage_attach_device(storage_dev_t *dev); - storage_poll_t storage_probe(size_t dev_num); ssize_t storage_read_blocks512(size_t dev_num, lba_t start, size_t count, unsigned char *buf); diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index ca263e4410..393881d9cc 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -83,5 +83,4 @@ size_t strlcpy(char *d, const char *s, size_t n); size_t strlcat(char *d, const char *s, size_t n); /** @} */ - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 6e83f684df..fe3d3304c4 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -29,6 +29,8 @@ #ifndef _SYSINFO_H #define _SYSINFO_H +#include + /* Maximum number of memory range definitions. */ #define SYSINFO_MAX_MEM_RANGES 32 /* Allow a maximum of 8 GPIOs */ @@ -39,17 +41,16 @@ #include -struct cb_serial; - /* - * All pointers in here shall be virtual. + * This is a collection of information and pointers gathered + * mostly from the coreboot table. * - * If a relocation happens after the last call to lib_get_sysinfo(), - * it is up to the user to call lib_get_sysinfo() again. + * We do not store virtual pointers in here to avoid problems + * with self-relocating payloads. */ struct sysinfo_t { unsigned int cpu_khz; - struct cb_serial *serial; + uintptr_t cb_serial; unsigned short ser_ioport; unsigned long ser_base; // for mmapped serial @@ -61,56 +62,56 @@ struct sysinfo_t { unsigned int type; } memrange[SYSINFO_MAX_MEM_RANGES]; - struct cb_cmos_option_table *option_table; + uintptr_t cmos_option_table; u32 cmos_range_start; u32 cmos_range_end; u32 cmos_checksum_location; u32 vbnv_start; u32 vbnv_size; - char *version; - char *extra_version; - char *build; - char *compile_time; - char *compile_by; - char *compile_host; - char *compile_domain; - char *compiler; - char *linker; - char *assembler; + uintptr_t version; + uintptr_t extra_version; + uintptr_t build; + uintptr_t compile_time; + uintptr_t compile_by; + uintptr_t compile_host; + uintptr_t compile_domain; + uintptr_t compiler; + uintptr_t linker; + uintptr_t assembler; - char *cb_version; + uintptr_t cb_version; - struct cb_framebuffer *framebuffer; + struct cb_framebuffer framebuffer; int num_gpios; struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; int num_macs; struct mac_address macs[SYSINFO_MAX_MACS]; - char *serialno; + uintptr_t serialno; unsigned long *mbtable; /** Pointer to the multiboot table */ - struct cb_header *header; - struct cb_mainboard *mainboard; + uintptr_t cb_header; + uintptr_t cb_mainboard; - void *vboot_workbuf; + uintptr_t vboot_workbuf; #if CONFIG(LP_ARCH_X86) int x86_rom_var_mtrr_index; #endif - void *tstamp_table; - void *cbmem_cons; - void *mrc_cache; - void *acpi_gnvs; + uintptr_t tstamp_table; + uintptr_t cbmem_cons; + uintptr_t mrc_cache; + uintptr_t acpi_gnvs; #define UNDEFINED_STRAPPING_ID (~0) u32 board_id; u32 ram_code; u32 sku_id; - void *wifi_calibration; + uintptr_t wifi_calibration; uint64_t ramoops_buffer; uint32_t ramoops_buffer_size; struct { @@ -124,11 +125,11 @@ struct sysinfo_t { uint64_t boot_media_size; uint64_t mtc_start; uint32_t mtc_size; - void *chromeos_vpd; - int mmc_early_wake_status; + uintptr_t chromeos_vpd; + int mmc_early_wake_status; /* Pointer to FMAP cache in CBMEM */ - void *fmap_cache; + uintptr_t fmap_cache; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index c6fb57fde9..c48b6cffd8 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -41,10 +41,10 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -void *get_cbmem_ptr(unsigned char *ptr) +uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - return phys_to_virt(cbmem->cbmem_tab); + const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry; + return cbmem->cbmem_tab; } static void cb_parse_memory(void *ptr, struct sysinfo_t *info) @@ -80,12 +80,12 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info) static void cb_parse_serial(void *ptr, struct sysinfo_t *info) { - info->serial = ((struct cb_serial *)ptr); + info->cb_serial = virt_to_phys(ptr); } static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) { - info->vboot_workbuf = get_cbmem_ptr(ptr); + info->vboot_workbuf = get_cbmem_addr(ptr); } static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) @@ -130,17 +130,17 @@ static void cb_parse_mac_addresses(unsigned char *ptr, static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { - info->tstamp_table = get_cbmem_ptr(ptr); + info->tstamp_table = get_cbmem_addr(ptr); } static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) { - info->cbmem_cons = get_cbmem_ptr(ptr); + info->cbmem_cons = get_cbmem_addr(ptr); } static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { - info->acpi_gnvs = get_cbmem_ptr(ptr); + info->acpi_gnvs = get_cbmem_addr(ptr); } static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) @@ -164,8 +164,8 @@ static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info) #if CONFIG(LP_NVRAM) static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { - /* ptr points to a coreboot table entry and is already virtual */ - info->option_table = ptr; + /* ptr is already virtual, but we want to keep physical addresses */ + info->cmos_option_table = virt_to_phys(ptr); } static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) @@ -180,19 +180,21 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) #if CONFIG(LP_COREBOOT_VIDEO_CONSOLE) static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { - /* ptr points to a coreboot table entry and is already virtual */ - info->framebuffer = ptr; + info->framebuffer = *(struct cb_framebuffer *)ptr; } #endif -static void cb_parse_string(unsigned char *ptr, char **info) +static void cb_parse_string(const void *const ptr, uintptr_t *const info) { - *info = (char *)((struct cb_string *)ptr)->string; + /* ptr is already virtual (str->string just an offset to that), + but we want to keep physical addresses */ + const struct cb_string *const str = ptr; + *info = virt_to_phys(str->string); } static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) { - info->wifi_calibration = get_cbmem_ptr(ptr); + info->wifi_calibration = get_cbmem_addr(ptr); } static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) @@ -233,12 +235,12 @@ static void cb_parse_boot_media_params(unsigned char *ptr, static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) { - info->chromeos_vpd = get_cbmem_ptr(ptr); + info->chromeos_vpd = get_cbmem_addr(ptr); } static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) { - info->fmap_cache = get_cbmem_ptr(ptr); + info->fmap_cache = get_cbmem_addr(ptr); } #if CONFIG(LP_TIMER_RDTSC) @@ -282,7 +284,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; - info->header = header; + info->cb_header = virt_to_phys(header); /* Initialize IDs as undefined in case they don't show up in table. */ info->board_id = UNDEFINED_STRAPPING_ID; @@ -353,7 +355,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) break; #endif case CB_TAG_MAINBOARD: - info->mainboard = (struct cb_mainboard *)ptr; + info->cb_mainboard = virt_to_phys(ptr); break; case CB_TAG_GPIO: cb_parse_gpios(ptr, info); diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 8b22daa9cc..20f9ef38e1 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -123,7 +123,8 @@ int dma_coherent(void *ptr) return !dma_initialized() || (dma->start <= ptr && dma->end > ptr); } -static void *alloc(int len, struct memory_type *type) +/* Find free block of size >= len */ +static hdrtype_t volatile *find_free_block(int len, struct memory_type *type) { hdrtype_t header; hdrtype_t volatile *ptr = (hdrtype_t volatile *)type->start; @@ -156,37 +157,53 @@ static void *alloc(int len, struct memory_type *type) halt(); } - if (header & FLAG_FREE) { - if (len <= size) { - hdrtype_t volatile *nptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + len); - int nsize = size - (HDRSIZE + len); - - /* If there is still room in this block, - * then mark it as such otherwise account - * the whole space for that block. - */ - - if (nsize > 0) { - /* Mark the block as used. */ - *ptr = USED_BLOCK(len); - - /* Create a new free block. */ - *nptr = FREE_BLOCK(nsize); - } else { - /* Mark the block as used. */ - *ptr = USED_BLOCK(size); - } - - return (void *)((uintptr_t)ptr + HDRSIZE); - } - } + if ((header & FLAG_FREE) && len <= size) + return ptr; ptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + size); } while (ptr < (hdrtype_t *) type->end); /* Nothing available. */ - return (void *)NULL; + return NULL; +} + +/* Mark the block with length 'len' as used */ +static void use_block(hdrtype_t volatile *ptr, int len) +{ + /* Align the size. */ + len = ALIGN_UP(len, HDRSIZE); + + hdrtype_t volatile *nptr = (hdrtype_t volatile *) + ((uintptr_t)ptr + HDRSIZE + len); + int size = SIZE(*ptr); + int nsize = size - (HDRSIZE + len); + + /* + * If there is still room in this block, then mark it as such otherwise + * account the whole space for that block. + */ + if (nsize > 0) { + /* Mark the block as used. */ + *ptr = USED_BLOCK(len); + + /* Create a new free block. */ + *nptr = FREE_BLOCK(nsize); + } else { + /* Mark the block as used. */ + *ptr = USED_BLOCK(size); + } +} + +static void *alloc(int len, struct memory_type *type) +{ + hdrtype_t volatile *ptr = find_free_block(len, type); + + if (ptr == NULL) + return NULL; + + use_block(ptr, len); + return (void *)((uintptr_t)ptr + HDRSIZE); } static void _consolidate(struct memory_type *type) @@ -229,6 +246,10 @@ void free(void *ptr) hdrtype_t hdr; struct memory_type *type = heap; + /* No action occurs on NULL. */ + if (ptr == NULL) + return; + /* Sanity check. */ if (ptr < type->start || ptr >= type->end) { type = dma; @@ -277,6 +298,7 @@ void *calloc(size_t nmemb, size_t size) void *realloc(void *ptr, size_t size) { void *ret, *pptr; + hdrtype_t volatile *block; unsigned int osize; struct memory_type *type = heap; @@ -300,18 +322,23 @@ void *realloc(void *ptr, size_t size) * reallocated the new space. */ free(ptr); - ret = alloc(size, type); + + block = find_free_block(size, type); + if (block == NULL) + return NULL; + + ret = (void *)((uintptr_t)block + HDRSIZE); /* - * if ret == NULL, then doh - failure. - * if ret == ptr then woo-hoo! no copy needed. + * If ret == ptr, then no copy is needed. Otherwise, move the memory to + * the new location, which might be before the old one and overlap since + * the free() above includes a _consolidate(). */ - if (ret == NULL || ret == ptr) - return ret; + if (ret != ptr) + memmove(ret, ptr, osize > size ? size : osize); - /* Move the memory to the new location. Might be before the old location - and overlap since the free() above includes a _consolidate(). */ - memmove(ret, ptr, osize > size ? size : osize); + /* Mark the block as used. */ + use_block(block, size); return ret; } diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index daa53f1bcb..fff295e54c 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -90,7 +90,7 @@ static void *default_memmove(void *dst, const void *src, size_t n) ssize_t i; if (src > dst) - return memcpy(dst, src, n); + return default_memcpy(dst, src, n); if (!IS_ALIGNED((uintptr_t)dst, sizeof(unsigned long)) || !IS_ALIGNED((uintptr_t)src, sizeof(unsigned long))) { @@ -145,7 +145,6 @@ static int default_memcmp(const void *s1, const void *s2, size_t n) int memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("default_memcmp"))); - void *memchr(const void *s, int c, size_t n) { unsigned char *p = (unsigned char *)s; diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index a481fef7eb..46c3c019bd 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -521,7 +521,6 @@ unsigned long int strtoul(const char *ptr, char **endptr, int base) return val; } - /** * Determine the number of leading characters in s that match characters in a * @param s A pointer to the string to analyse diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index c0a3313e86..6780008d4c 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -31,11 +31,14 @@ * General time functions */ +#define __STDC_FORMAT_MACROS + #include #include #if CONFIG(LP_ARCH_X86) && CONFIG(LP_NVRAM) #include #endif +#include extern u32 cpu_khz; @@ -173,7 +176,7 @@ u64 timer_us(u64 base) if (hz == 0) { hz = timer_hz(); if (hz < 1000000) { - printf("Timer frequency %lld is too low, " + printf("Timer frequency %" PRIu64 " is too low, " "must be at least 1MHz.\n", hz); halt(); } diff --git a/payloads/libpayload/liblzma/lzmadecode.c b/payloads/libpayload/liblzma/lzmadecode.c index 1cf647d27b..c8115d308a 100644 --- a/payloads/libpayload/liblzma/lzmadecode.c +++ b/payloads/libpayload/liblzma/lzmadecode.c @@ -33,12 +33,10 @@ #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } #define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) @@ -56,7 +54,6 @@ do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \ res -= (1 << numLevels); } - #define kNumPosBitsMax 4 #define kNumPosStatesMax (1 << kNumPosBitsMax) @@ -74,7 +71,6 @@ #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) #define kNumLenProbs (LenHigh + kLenNumHighSymbols) - #define kNumStates 12 #define kNumLitStates 7 @@ -143,7 +139,6 @@ int LzmaDecode(CLzmaDecoderState *vs, UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; int lc = vs->Properties.lc; - int state = 0; UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; int len = 0; @@ -164,7 +159,6 @@ int LzmaDecode(CLzmaDecoderState *vs, RC_INIT(inStream, inSize); - while(nowPos < outSize) { CProb *prob; @@ -379,7 +373,6 @@ int LzmaDecode(CLzmaDecoderState *vs, if (rep0 > nowPos) return LZMA_RESULT_DATA_ERROR; - do { previousByte = outStream[nowPos - rep0]; @@ -391,7 +384,6 @@ int LzmaDecode(CLzmaDecoderState *vs, } RC_NORMALIZE; - *inSizeProcessed = (SizeT)(Buffer - inStream); *outSizeProcessed = nowPos; return LZMA_RESULT_OK; diff --git a/payloads/libpayload/liblzma/lzmadecode.h b/payloads/libpayload/liblzma/lzmadecode.h index 34c9f14c33..05ff0a3397 100644 --- a/payloads/libpayload/liblzma/lzmadecode.h +++ b/payloads/libpayload/liblzma/lzmadecode.h @@ -32,7 +32,6 @@ typedef UInt32 SizeT; #define LZMA_RESULT_OK 0 #define LZMA_RESULT_DATA_ERROR 1 - #define LZMA_BASE_SIZE 1846 #define LZMA_LIT_SIZE 768 @@ -56,10 +55,8 @@ typedef struct _CLzmaDecoderState CLzmaProperties Properties; CProb *Probs; - } CLzmaDecoderState; - int LzmaDecode(CLzmaDecoderState *vs, const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index bf7053b9a6..269d558d19 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -26,9 +26,9 @@ else endif clean: - rm -f nvramcui.elf + rm -rf build libpayload nvramcui.elf distclean: clean - rm -rf build libpayload .config .config.old + rm -rf .config .config.old .PHONY: all clean distclean diff --git a/src/Kconfig b/src/Kconfig index a4c2fa6010..9cc9d31e64 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -270,6 +270,45 @@ config UBSAN say N because it adds a small performance penalty and may abort on code that happens to work in spite of the UB. +config HAVE_ASAN_IN_ROMSTAGE + bool + default n + +config ASAN_IN_ROMSTAGE + bool + default n + help + Enable address sanitizer in romstage for platform. + +config HAVE_ASAN_IN_RAMSTAGE + bool + default n + +config ASAN_IN_RAMSTAGE + bool + default n + help + Enable address sanitizer in ramstage for platform. + +config ASAN + bool "Address sanitizer support" + default n + select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE + select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE + help + Enable address sanitizer - runtime memory debugger, + designed to find out-of-bounds accesses and use-after-scope bugs. + + This feature consumes up to 1/8 of available memory and brings about + ~1.5x performance slowdown. + + If unsure, say N. + +if ASAN + comment "Before using this feature, make sure that " + comment "asan_shadow_offset_callback patch is applied to GCC." +endif + choice prompt "Stage Cache for ACPI S3 resume" default NO_STAGE_CACHE if !HAVE_ACPI_RESUME @@ -497,6 +536,17 @@ source "src/vendorcode/*/Kconfig" source "src/arch/*/Kconfig" +config CHIPSET_DEVICETREE + string + default "" + help + This symbol allows a chipset to provide a set of default settings in + a devicetree which are common to all mainboards. This may include + devices (including alias names), chip drivers, register settings, + and others. This path is relative to the src/ directory. + + Example: "chipset.cb" + endmenu source "src/device/Kconfig" @@ -839,7 +889,7 @@ config DEBUG_SMI bool "Output verbose SMI debug messages" default n depends on HAVE_SMI_HANDLER - select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH + select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH help This option enables additional SMI related debug messages. @@ -1105,7 +1155,6 @@ config EM100 endmenu - ############################################################################### # Set variables with no prompt - these can be set anywhere, and putting at # the end of this file gives the most flexibility. diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index ccd8d2526d..89f2a46a8d 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -752,7 +752,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->revision = get_acpi_table_revision(HPET); /* Fill out HPET address. */ - addr->space_id = 0; /* Memory */ + addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; addr->bit_width = 64; addr->bit_offset = 0; addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; @@ -1367,7 +1367,8 @@ unsigned long write_acpi_tables(unsigned long start) if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) - || memcmp(slic_file->signature, "SLIC", 4) != 0)) { + || (memcmp(slic_file->signature, "SLIC", 4) != 0 + && memcmp(slic_file->signature, "MSDM", 4) != 0))) { slic_file = 0; } @@ -1626,7 +1627,7 @@ int get_acpi_table_revision(enum acpi_tables table) case VFCT: /* ACPI 2.0/3.0/4.0: 1 */ return 1; case IVRS: - return IVRS_FORMAT_FIXED; + return IVRS_FORMAT_MIXED; case DBG2: return 0; case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index a4a74f65d7..5b45ebd3a8 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -284,7 +284,6 @@ static void acpigen_emit_multi_namestring(const char *name) pathlen[0] = count; } - void acpigen_emit_namestring(const char *namepath) { int dotcount = 0, i; @@ -687,7 +686,7 @@ void acpigen_write_empty_PTC(void) .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 0, .bit_offset = 0, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0, .addrh = 0, }; @@ -833,6 +832,23 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, coreFreq, power, control, status); } +void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries) +{ + size_t pstate; + + acpigen_write_name("_PSS"); + acpigen_write_package(nentries); + for (pstate = 0; pstate < nentries; pstate++) { + acpigen_write_PSS_package( + pstate_values->core_freq, pstate_values->power, + pstate_values->transition_latency, pstate_values->bus_master_latency, + pstate_values->control_value, pstate_values->status_value); + pstate_values++; + } + + acpigen_pop_len(); +} + void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { acpigen_write_name("_PSD"); @@ -851,8 +867,8 @@ void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { acpigen_write_package(4); acpigen_write_register_resource(&cstate->resource); - acpigen_write_dword(cstate->ctype); - acpigen_write_dword(cstate->latency); + acpigen_write_byte(cstate->ctype); + acpigen_write_word(cstate->latency); acpigen_write_dword(cstate->power); acpigen_pop_len(); } @@ -862,7 +878,7 @@ void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) int i; acpigen_write_name("_CST"); acpigen_write_package(nentries+1); - acpigen_write_dword(nentries); + acpigen_write_integer(nentries); for (i = 0; i < nentries; i++) acpigen_write_CST_package_entry(cstate + i); @@ -876,7 +892,7 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, acpigen_write_name("_CSD"); acpigen_write_package(1); acpigen_write_package(6); - acpigen_write_byte(6); // 6 values + acpigen_write_integer(6); // 6 values acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); @@ -930,8 +946,6 @@ void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) acpigen_pop_len(); } - - void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* @@ -1353,6 +1367,13 @@ void acpigen_write_to_integer(uint8_t src, uint8_t dst) acpigen_emit_byte(dst); } +void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op) +{ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_namestring(source); + acpigen_emit_byte(dst_op); +} + void acpigen_write_byte_buffer(uint8_t *arr, size_t size) { size_t i; @@ -1553,7 +1574,7 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) for (i = 0; i < max; ++i) { const acpi_addr_t *reg = &(config->regs[i]); if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY && - reg->bit_width == 32 && reg->access_size == 0) { + reg->bit_width == 32 && reg->access_size == ACPI_ACCESS_SIZE_UNDEFINED) { acpigen_write_dword(reg->addrl); } else { acpigen_write_register_resource(reg); @@ -1772,7 +1793,6 @@ void acpigen_write_rom(void *bios, const size_t length) acpigen_pop_len(); } - /* Soc-implemented functions -- weak definitions. */ int __weak acpigen_soc_read_rx_gpio(unsigned int gpio_num) { @@ -1971,3 +1991,71 @@ void acpigen_notify(const char *namestr, int value) acpigen_emit_namestring(namestr); acpigen_write_integer(value); } + +static void _create_field(uint8_t aml_op, uint8_t srcop, size_t byte_offset, const char *name) +{ + acpigen_emit_byte(aml_op); + acpigen_emit_byte(srcop); + acpigen_write_integer(byte_offset); + acpigen_emit_namestring(name); +} + +void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_BYTE_OP, op, byte_offset, name); +} + +void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_WORD_OP, op, byte_offset, name); +} + +void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_DWORD_OP, op, byte_offset, name); +} + +void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name) +{ + _create_field(CREATE_QWORD_OP, op, byte_offset, name); +} + +void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts) +{ + acpigen_write_name("_PCT"); + acpigen_write_package(0x02); + acpigen_write_register_resource(perf_ctrl); + acpigen_write_register_resource(perf_sts); + + acpigen_pop_len(); +} + +void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value) +{ + acpigen_write_package(0x08); + acpigen_write_dword(pstate_value->core_freq); + acpigen_write_dword(pstate_value->power); + acpigen_write_dword(pstate_value->transition_latency); + acpigen_write_dword(pstate_value->bus_master_latency); + + acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_value, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_value, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_mask, sizeof(uint64_t)); + acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_mask, sizeof(uint64_t)); + + acpigen_pop_len(); +} + +void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, size_t nentries) +{ + size_t pstate; + + acpigen_write_name("XPSS"); + acpigen_write_package(nentries); + for (pstate = 0; pstate < nentries; pstate++) { + acpigen_write_xpss_package(pstate_values); + pstate_values++; + } + + acpigen_pop_len(); +} diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 0c44b8f8ba..3877daa88b 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -2,6 +2,8 @@ #include #include +#include +#include /* Defaults */ #define DEFAULT_RAW_UNIT "ma" @@ -17,6 +19,7 @@ enum { DEFAULT_TRIP_POINT = 0xFFFFFFFFull, DEFAULT_WEIGHT = 100, DPTF_MAX_ART_THRESHOLDS = 10, + FPS_REVISION = 0, PPCC_REVISION = 2, RAPL_PL1_INDEX = 0, RAPL_PL2_INDEX = 1, @@ -353,7 +356,8 @@ void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count) /* _FPS - Fan Performance States */ acpigen_write_name("_FPS"); - pkg_count = acpigen_write_package(0); + pkg_count = acpigen_write_package(1); /* 1 for Revision */ + acpigen_write_integer(FPS_REVISION); /* revision */ for (i = 0; i < max_count; ++i) { /* diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 1379a89c18..be20220e31 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -1,13 +1,12 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include #include +#include +#include #define KEYMAP(scancode, keycode) (((uint32_t)(scancode) << 16) | (keycode & 0xFFFF)) #define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF) diff --git a/src/acpi/device.c b/src/acpi/device.c index b119abd61f..450427d47c 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #if CONFIG(GENERIC_GPIO_LIB) @@ -197,7 +198,6 @@ int acpi_device_status(const struct device *dev) return ACPI_STATUS_DEVICE_ALL_ON; } - /* Write the unique _UID based on ACPI device path. */ void acpi_device_write_uid(const struct device *dev) { diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index eef2650685..3d359148aa 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -119,6 +119,8 @@ ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += clock.c +ramstage-y += boot_linux.S +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c rmodules_arm-y += memset.S rmodules_arm-y += memcpy.S diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 5f34c6049b..0ed11ac8d1 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -5,7 +5,6 @@ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition */ - #include void tlb_invalidate_all(void) diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index e1879c0b30..47813a78f8 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -62,14 +62,43 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop + /* Set stackpointer in internal RAM */ + ldr sp, =_estack + + /* + * For platforms where the flash is memory mapped (qemu), check if the + * bootblock needs to relocate itself. + */ +check_position: + adr r0, check_position + ldr r1, =check_position + + cmp r0, r1 + beq call_bootblock + + /* Calculate source */ + ldr r2, =_program + sub r1, r1, r2 + sub r1, r0, r1 + /* Get destination */ + ldr r0, =_program + /* Get size */ + ldr r2, =_eprogram + sub r2, r2, r0 + + bl memcpy + + /* Get absolute address */ + ldr lr, =call_bootblock + /* Directly modify pc as branch instruction changes the state */ + mov pc, lr + call_bootblock: /* Restore parameter passed in by maskrom/vendor firmware. */ ldr r0, =maskrom_param str r10, [r0] - /* Set stackpointer in internal RAM to call bootblock main() */ - ldr sp, =_estack ldr r0,=0x00000000 /* * The current design of cpu_info places the struct at the top of the diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c index 7267e83948..06ed599c44 100644 --- a/src/arch/arm/armv7/cache_m.c +++ b/src/arch/arm/armv7/cache_m.c @@ -3,7 +3,6 @@ * cache.c: Cache maintenance routines for ARMv7-M */ - #include void tlb_invalidate_all(void) diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 610659243d..c53119c8d1 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -23,6 +23,19 @@ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 */ +#if ENV_USER_SPACE +/* + * Empty macro for code running in userspace. Trying to manipulate the + * cache from userspace hangs the system. To run code at a privileged level, + * the userspace code needs to execute an API call to the privileged mode + * code. + */ +.macro dcache_apply_all crm + bx lr +.endm + +#else + .macro dcache_apply_all crm dsb mov r3, #-2 @ initialize level so that we start at 0 @@ -82,6 +95,8 @@ bx lr .endm +#endif /* ENV_USER_SPACE */ + /* * Bring an ARM processor we just gained control of (e.g. from IROM) into a * known state regarding caches/SCTLR. Completely cleans and invalidates diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 51b4860768..66ce53392d 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -87,9 +87,6 @@ typedef uint32_t pte_t; static pte_t *const ttb_buff = (void *)_ttb; -/* Not all boards want to use subtables and declare them in memlayout.ld. */ -DECLARE_OPTIONAL_REGION(ttb_subtables); - static struct { pte_t value; const char *name; diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 8c876de0b0..b18473b924 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -1,14 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +void boot_linux(void *kernel_ptr, void *fdt_ptr); + void arch_prog_run(struct prog *prog) { void (*doit)(void *); cache_sync_instructions(); - doit = prog_entry(prog); - doit(prog_entry_arg(prog)); + switch (prog_cbfs_type(prog)) { + case CBFS_TYPE_FIT: + /* + * We only load Linux payloads from the ramstage, so provide a hint to + * the linker that the below functions do not need to be included in + * earlier stages. + */ + if (!ENV_RAMSTAGE) + break; + + dcache_mmu_disable(); + boot_linux(prog_entry(prog), prog_entry_arg(prog)); + break; + default: + doit = prog_entry(prog); + doit(prog_entry_arg(prog)); + } } diff --git a/src/arch/arm/boot_linux.S b/src/arch/arm/boot_linux.S new file mode 100644 index 0000000000..e3985eae56 --- /dev/null +++ b/src/arch/arm/boot_linux.S @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Required to jump to kernel in ARM state */ +.arm +/* void boot_linux(void *kernel_ptr, void *fdt_ptr); */ +ENTRY(boot_linux) + /* Save kernel ptr */ + mov r3, r0 + /* Set R2 = fdt */ + mov r2, r1 + /* Set R0 = 0x00000000 as expected by Linux ABI */ + mov r0, #0 + /* Set R1 = 0xffffffff as expected by Linux ABI */ + mov r1, #-1 + /* Linux ABI expects SVC mode (0x13) with IRQ(7) and FIQ(6) disabled. */ + msr cpsr_cxf, #0xd3 + /* Jump to kernel */ + mov pc, r3 +ENDPROC(boot_linux) diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c new file mode 100644 index 0000000000..9777e3c1e5 --- /dev/null +++ b/src/arch/arm/fit_payload.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/** + * Place the region in free memory range. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + void *arg = NULL; + + /** + * The kernel ARM documentation recommends loading the kernel above 32MiB + * in order to avoid the need to need to relocate prior to decompression. + */ + kernel->offset = (uintptr_t)_dram + 32 * MiB; + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + if (!bootmem_walk(fit_place_mem, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * To ensure the fdt is not overwritten by the kernel decompressor, place + * the fdt above the 128 MB from the start of RAM, as recommended by the + * kernel documentation. + */ + fdt->offset = (uintptr_t)_dram + 128 * MiB; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = fdt->offset + fdt->size; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h index 5245bd1a02..0a3a4d4676 100644 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ b/src/arch/arm/include/armv4/arch/smp/spinlock.h @@ -4,12 +4,10 @@ #define _ARCH_SMP_SPINLOCK_H #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #include #define boot_cpu() 1 diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 3b47a5bf0c..0c68fc7c51 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -11,8 +11,6 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { - DECLARE_OPTIONAL_REGION(ttb_subtables); - bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE); bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables), BM_MEM_RAMSTAGE); diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 88e68e759e..f3a075522e 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -63,10 +63,8 @@ static void print_regs(struct exc_state *exc_state) regs->x[30], regs->sp); } - static struct exception_handler *handlers[NUM_EXC_VIDS]; - int exception_handler_register(uint64_t vid, struct exception_handler *h) { if (vid >= NUM_EXC_VIDS) @@ -122,7 +120,6 @@ static void print_exception_and_die(struct exc_state *state, uint64_t idx) die("exception death"); } - static int handle_exception(struct exc_state *state, uint64_t idx) { int ret = EXC_RET_ABORT; diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index 58bedda9c5..72ed772500 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -27,7 +27,6 @@ struct exception_handler { struct exception_handler *next; }; - /* * Register a handler provided with the associated vector id. Returns 0 on * success, < 0 on error. Note that registration is not thread/interrupt safe. diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 321d348602..b97297c1b9 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -5,8 +5,6 @@ #include #include -DECLARE_OPTIONAL_REGION(bl31); - void arch_write_tables(uintptr_t coreboot_table) { } diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index d3d15ff055..f8c1121f1a 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -17,13 +17,11 @@ static inline void outl(uint32_t value, uint16_t port) { } - static inline uint8_t inb(uint16_t port) { return 0; } - static inline uint16_t inw(uint16_t port) { return 0; diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 7e9072b6cd..ad678b7fe5 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 5501a0c710..c1894c70ca 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -12,7 +12,6 @@ void mstatus_init(void); // need to setup mstatus so we know we have virtual memory - #define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \ static inline type name(type *p); \ static inline type name(type *p) \ diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index eff51fc96e..a17b7dd454 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -132,7 +131,6 @@ static struct memory_instruction_info *match_instruction(uintptr_t insn) return NULL; } - static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) { uint16_t ins = mprv_read_mxr_u16((uint16_t *)vaddr); @@ -158,7 +156,6 @@ static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) return -1; } - void handle_misaligned(trapframe *tf) { uintptr_t insn = 0; diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 38fc05e210..654bef03d6 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -49,7 +49,6 @@ static uintptr_t sbi_clear_ipi(void) return 0; } - /* * sbi is triggered by the s-mode ecall * parameter : register a0 a1 a2 diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index b3e13ff9fb..1d58602627 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 4935ef5ece..9fc75f455c 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -5,8 +5,6 @@ #include #include -DECLARE_OPTIONAL_REGION(opensbi); - void arch_write_tables(uintptr_t coreboot_table) { } diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 660ff2d4d2..900c9c1e10 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -4,6 +4,7 @@ config ARCH_X86 bool select PCI select RELOCATABLE_MODULES + select HAVE_ASAN_IN_RAMSTAGE # stage selectors for x86 @@ -27,6 +28,13 @@ config ARCH_RAMSTAGE_X86_32 bool select ARCH_X86 +config ARCH_ALL_STAGES_X86_32 + bool + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + # stage selectors for x64 config ARCH_BOOTBLOCK_X86_64 @@ -49,12 +57,19 @@ config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 +config ARCH_ALL_STAGES_X86_64 + bool + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 + if ARCH_X86 config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 - default 0xfffea000 + default 0xfffe9000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00690ba02e..a5c330905a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -195,7 +195,11 @@ endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 # postcar ############################################################################### +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) $(eval $(call create_class_compiler,postcar,x86_32)) +else +$(eval $(call create_class_compiler,postcar,x86_64)) +endif postcar-generic-ccopts += -D__POSTCAR__ postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c @@ -241,6 +245,7 @@ ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += post.c ramstage-y += c_start.S +ramstage-y += c_exit.S ramstage-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c @@ -255,6 +260,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios_defaults.c ramstage-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 4872c07228..2802bd32ab 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -57,11 +57,6 @@ extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); - return; - } - /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); @@ -76,7 +71,7 @@ void __weak mainboard_suspend_resume(void) { } -void acpi_resume(void *wake_vec) +void __noreturn acpi_resume(void *wake_vec) { /* Restore GNVS pointer in SMM if found. */ apm_control(APM_CNT_GNVS_UPDATE); @@ -86,4 +81,6 @@ void acpi_resume(void *wake_vec) post_code(POST_OS_RESUME); acpi_jump_to_wakeup(wake_vec); + + die("Failed the jump to wakeup vector\n"); } diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index fb48469c55..31670c29b6 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -15,12 +15,22 @@ #define _STACK_TOP _ecar_stack #endif +#ifdef __x86_64__ +.code64 +#else +.code32 +#endif + .section ".text._start", "ax", @progbits .global _start _start: /* Migrate GDT to this text segment */ +#ifdef __x86_64__ + call gdt_init64 +#else call gdt_init +#endif /* reset stack pointer to CAR/EARLYRAM stack */ mov $_STACK_TOP, %esp @@ -49,6 +59,10 @@ debug_spinloop: #if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif + +#if CONFIG(ASAN_IN_ROMSTAGE) + call asan_init +#endif call car_stage_entry /* Expect to never return. */ diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index db9d69e74d..777a0b7d90 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) { @@ -19,6 +21,13 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) void arch_prog_run(struct prog *prog) { +#if ENV_RAMSTAGE && defined(__x86_64__) + const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); + const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); + + /* On x86 coreboot payloads expect to be called in protected mode */ + protected_mode_jump(entry, arg); +#else #ifdef __x86_64__ void (*doit)(void *arg); #else @@ -27,4 +36,5 @@ void arch_prog_run(struct prog *prog) #endif doit = prog_entry(prog); doit(prog_entry_arg(prog)); +#endif } diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413e70..3f41464f87 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -20,12 +20,6 @@ #include #include - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S new file mode 100644 index 0000000000..e5b9bf8d74 --- /dev/null +++ b/src/arch/x86/c_exit.S @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + + +#ifdef __x86_64__ + + /* + * Functions to handle mode switches from long mode to protected + * mode. + */ +.text +.code64 + .section ".text.protected_mode_jump", "ax", @progbits + .globl protected_mode_jump +protected_mode_jump: + + push %rbp + mov %rsp, %rbp + + /* Arguments to stack */ + push %rdi + push %rsi + + #include + + movl -8(%ebp), %eax /* Function to call */ + movl -16(%ebp), %ebx /* Argument 0 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + subl $12, %esp + pushl %ebx /* Argument 0 */ + + jmp *%eax +#endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 4e2ae08a47..c46a45c729 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -91,6 +91,10 @@ _start: andl $0xFFFFFFF0, %esp +#if CONFIG(ASAN_IN_RAMSTAGE) + call asan_init +#endif + #if CONFIG(GDB_WAIT) call gdb_hw_init call gdb_stub_breakpoint diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 17b774845b..eabe87380a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -72,8 +72,12 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; - _car_unallocated_start = .; +#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) + _shadow_size = (_ebss - _car_region_start) >> 3; + REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) +#endif + _car_unallocated_start = .; _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } . = _car_region_end; diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 939a862e3c..d054cfe72c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -287,7 +287,6 @@ void cpu_initialize(unsigned int index) printk(BIOS_DEBUG, "Using generic CPU ops (good)\n"); } - /* Initialize the CPU */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 958ebfc41c..f10c7bf8ba 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -180,8 +180,6 @@ static uint32_t gdb_stub_registers[NUM_REGS]; #define GDB_EXC_SOFTWARE 149 /* Software generated exception */ #define GDB_EXC_BREAKPOINT 150 /* Breakpoint */ - - static unsigned char exception_to_signal[] = { [0] = GDB_SIGFPE, /* divide by zero */ [1] = GDB_SIGTRAP, /* debug exception */ @@ -222,7 +220,6 @@ static const char hexchars[] = "0123456789abcdef"; static char in_buffer[BUFMAX]; static char out_buffer[BUFMAX]; - static inline void stub_putc(int ch) { gdb_tx_byte(ch); @@ -283,7 +280,6 @@ static void copy_to_hex(char *buf, void *addr, unsigned long count) *buf = 0; } - /* convert the hex array pointed to by buf into binary to be placed in mem */ /* return a pointer to the character AFTER the last byte written */ static void copy_from_hex(void *addr, char *buf, unsigned long count) @@ -298,7 +294,6 @@ static void copy_from_hex(void *addr, char *buf, unsigned long count) } } - /* scan for the sequence $# */ static int get_packet(char *buffer) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a921ee5d7d..fae7899e17 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -2,6 +2,7 @@ #include #include +#include .section ".module_parameters", "aw", @progbits /* stack_top indicates the stack to pull MTRR information from. */ @@ -10,6 +11,30 @@ post_car_stack_top: .long 0 .long 0 +#if defined(__x86_64__) +.code64 +.macro pop_eax_edx + pop %rax + mov %rax, %rdx + shr $32, %rdx +.endm +.macro pop_ebx_esi + pop %rbx + mov %rbx, %rsi + shr $32, %rsi +.endm +#else +.code32 +.macro pop_eax_edx + pop %eax + pop %edx +.endm +.macro pop_ebx_esi + pop %ebx + pop %esi +.endm +#endif + .text .global _start _start: @@ -17,7 +42,11 @@ _start: is expected to be implemented in assembly. */ /* Migrate GDT to this text segment */ +#if defined(__x86_64__) + call gdt_init64 +#else call gdt_init +#endif #ifdef __x86_64__ mov %rdi, _cbmem_top_ptr @@ -26,15 +55,27 @@ _start: movl 4(%esp), %eax movl %eax, _cbmem_top_ptr #endif + /* Make sure _cbmem_top_ptr hits dram before invd */ + movl $1, %eax + cpuid + btl $CPUID_FEATURE_CLFLUSH_BIT, %edx + jnc skip_clflush + clflush _cbmem_top_ptr +skip_clflush: /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car /* Enable caching if not already enabled. */ +#ifdef __x86_64__ + mov %cr0, %rax + and $(~(CR0_CD | CR0_NW)), %eax + mov %rax, %cr0 +#else mov %cr0, %eax and $(~(CR0_CD | CR0_NW)), %eax mov %eax, %cr0 - +#endif /* Ensure cache is clean. */ invd @@ -61,8 +102,13 @@ _start: /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp +#if defined(__x86_64__) + mov %rbp, %rdi +#else sub $12, %esp push %ebp +#endif + call soc_set_mtrrs /* Ignore fixing up %esp since we're setting it a new value. */ @@ -73,7 +119,7 @@ _start: call soc_enable_mtrrs #else /* CONFIG_SOC_SETS_MSRS */ /* Clear variable MTRRs. */ - pop %ebx /* Number to clear */ + pop_ebx_esi /* ebx: Number to clear, esi: Number to set */ test %ebx, %ebx jz 2f xor %eax, %eax @@ -89,23 +135,20 @@ _start: 2: /* Set Variable MTRRs based on stack contents. */ - pop %ebx /* Number to set. */ - test %ebx, %ebx + test %esi, %esi jz 2f mov $(MTRR_PHYS_BASE(0)), %ecx 1: /* Write MTRR base. */ - pop %eax - pop %edx + pop_eax_edx wrmsr inc %ecx /* Write MTRR mask. */ - pop %eax - pop %edx + pop_eax_edx wrmsr inc %ecx - dec %ebx + dec %esi jnz 1b 2: diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index d90aba64d3..1558ac62c8 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -15,6 +15,35 @@ gdtptr: .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ +#ifdef __x86_64__ +.code64 +.section ".text._gdt64_", "ax", @progbits + .globl gdt_init64 +gdt_init64: + /* Workaround a bug in the assembler. + * The following code doesn't work: + * lgdt gdtptr64 + * + * The assembler tries to save memory by using 32bit displacement addressing mode. + * Displacements are using signed integers. + * This is fine in protected mode, as the negative address points to the correct + * address > 2GiB, but in long mode this doesn't work at all. + * Tests showed that QEMU can gracefully handle it, but real CPUs can't. + * + * Use the movabs pseudo instruction to force using a 64bit absolute address. + */ + movabs $gdtptr64, %rax + lgdt (%rax) + ret + +.previous + .align 4 +.globl gdtptr64 +gdtptr64: + .word gdt_end - gdt -1 /* compute the table limit */ + .quad gdt /* we know the offset */ +#endif + .align 4 gdt: /* selgdt 0, unused */ diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index c6a2f30408..060e1a43f2 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -82,7 +82,6 @@ static inline acpi_hest_generic_data_v300_t *acpi_hest_generic_data3( /* Find the address of a Generic Data structure's CPER error record section */ #define section_of_acpientry(A, B) ((typeof(A))((u8 *)(B) + sizeof(*(B)))) - /* Add a context to an existing IA32/X64-type error entry */ cper_ia32x64_context_t *new_cper_ia32x64_ctx( acpi_generic_error_status_t *status, diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h index c73591579a..1ef927e0fb 100644 --- a/src/arch/x86/include/arch/boot/boot.h +++ b/src/arch/x86/include/arch/boot/boot.h @@ -7,4 +7,15 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_386 +#include +/* + * Jump to function in protected mode. + * @arg func_ptr Function to jump to in protected mode + * @arg Argument to pass to called function + * + * @noreturn + */ +void protected_mode_jump(uint32_t func_ptr, + uint32_t argument); + #endif /* ASM_I386_BOOT_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 82f470ec2d..b622465a25 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -269,6 +269,12 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) } +/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ +static __always_inline void cpu_relax(void) +{ + __asm__ __volatile__("rep;nop" : : : "memory"); +} + #define asmlinkage __attribute__((regparm(0))) /* diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d01d5f6511..00fb277ec0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -73,7 +73,6 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) ); } - static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 7626206e12..4037e48a7f 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -67,6 +67,4 @@ static __always_inline void atomic_dec(atomic_t *v) : "m" (v->counter)); } - - #endif /* ARCH_SMP_ATOMIC_H */ diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index d6378731ed..25c23e68f5 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -23,7 +23,6 @@ */ #define MAX_APICS 16 - #define SMP_FLOATING_TABLE_LEN sizeof(struct intel_mp_floating) struct intel_mp_floating { @@ -130,7 +129,6 @@ enum mp_irq_source_types { #define MP_IRQ_TRIGGER_LEVEL 0xc #define MP_IRQ_TRIGGER_MASK 0xc - struct mpc_config_lintsrc { u8 mpc_type; u8 mpc_irqtype; diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 41189933d9..799ac2c8b8 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -29,6 +29,7 @@ typedef struct { #define barrier() __asm__ __volatile__("" : : : "memory") #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) #define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) +#undef barrier #define spin_lock_string \ "\n1:\t" \ @@ -62,21 +63,13 @@ static __always_inline void spin_unlock(spinlock_t *lock) : "=m" (lock->lock) : : "memory"); } -/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ -static __always_inline void cpu_relax(void) -{ - __asm__ __volatile__("rep;nop" : : : "memory"); -} - #else #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #endif diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 2f23219de5..1cfdf89175 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include void *memcpy(void *dest, const void *src, size_t n) { unsigned long d0, d1, d2; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)src, n, false, _RET_IP_); + check_memory_region((unsigned long)dest, n, true, _RET_IP_); +#endif + asm volatile( #ifdef __x86_64__ "rep ; movsd\n\t" diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index cdd1e8dc70..3ec50b26ae 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -4,12 +4,20 @@ */ #include +#include +#include void *memmove(void *dest, const void *src, size_t n) { int d0, d1, d2, d3, d4, d5; char *ret = dest; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)src, n, false, _RET_IP_); + check_memory_region((unsigned long)dest, n, true, _RET_IP_); +#endif + __asm__ __volatile__( /* Handle more 16bytes in loop */ "cmp $0x10, %0\n\t" diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 17963426c0..fc09a9bd52 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -4,6 +4,8 @@ #include #include +#include +#include typedef uint32_t op_t; @@ -12,6 +14,11 @@ void *memset(void *dstpp, int c, size_t len) int d0; unsigned long int dstp = (unsigned long int) dstpp; +#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + check_memory_region((unsigned long)dstpp, len, true, _RET_IP_); +#endif + /* This explicit register allocation improves code very much indeed. */ register op_t x asm("ax"); diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 18a36cd3d1..362650dea9 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -28,7 +28,6 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr); - sum = rt->checksum - sum; if (sum != rt->checksum) { @@ -106,8 +105,6 @@ static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap) /* If it's not yet routed, use it */ if (!already_routed) break; - /* But if it was already routed, try the next one */ - continue; } /* Now we got our IRQ */ return irq; diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 3c5799bca8..2995eceb9d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -73,7 +73,6 @@ static u8 smbios_get_device_type_from_dev(struct device *dev) } } - int smbios_add_string(u8 *start, const char *str) { int i = 1; @@ -158,86 +157,53 @@ static int smbios_processor_name(u8 *start) return smbios_add_string(start, str); } -/* this function will fill the corresponding manufacturer */ -void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, - struct smbios_type17 *t) +static const char *get_dimm_manufacturer_name(const uint16_t mod_id) { switch (mod_id) { case 0x9b85: - t->manufacturer = smbios_add_string(t->eos, - "Crucial"); - break; + return "Crucial"; case 0x4304: - t->manufacturer = smbios_add_string(t->eos, - "Ramaxel"); - break; + return "Ramaxel"; case 0x4f01: - t->manufacturer = smbios_add_string(t->eos, - "Transcend"); - break; + return "Transcend"; case 0x9801: - t->manufacturer = smbios_add_string(t->eos, - "Kingston"); - break; + return "Kingston"; case 0x987f: - t->manufacturer = smbios_add_string(t->eos, - "Hynix"); - break; + return "Hynix"; case 0x9e02: - t->manufacturer = smbios_add_string(t->eos, - "Corsair"); - break; + return "Corsair"; case 0xb004: - t->manufacturer = smbios_add_string(t->eos, - "OCZ"); - break; + return "OCZ"; case 0xad80: - t->manufacturer = smbios_add_string(t->eos, - "Hynix/Hyundai"); - break; + return "Hynix/Hyundai"; case 0x3486: - t->manufacturer = smbios_add_string(t->eos, - "Super Talent"); - break; + return "Super Talent"; case 0xcd04: - t->manufacturer = smbios_add_string(t->eos, - "GSkill"); - break; + return "GSkill"; case 0xce80: - t->manufacturer = smbios_add_string(t->eos, - "Samsung"); - break; + return "Samsung"; case 0xfe02: - t->manufacturer = smbios_add_string(t->eos, - "Elpida"); - break; + return "Elpida"; case 0x2c80: - t->manufacturer = smbios_add_string(t->eos, - "Micron"); - break; - default: { - char string_buffer[256]; - - snprintf(string_buffer, sizeof(string_buffer), - "Unknown (%x)", mod_id); - t->manufacturer = smbios_add_string(t->eos, - string_buffer); - break; - } + return "Micron"; + default: + return NULL; } } -/* this function will fill the corresponding locator */ -void __weak smbios_fill_dimm_locator(const struct dimm_info *dimm, - struct smbios_type17 *t) + +/* this function will fill the corresponding manufacturer */ +void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t) { - char locator[40]; + const char *const manufacturer = get_dimm_manufacturer_name(mod_id); - snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", - dimm->channel_num, dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); + if (manufacturer) { + t->manufacturer = smbios_add_string(t->eos, manufacturer); + } else { + char string_buffer[256]; - snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); - t->bank_locator = smbios_add_string(t->eos, locator); + snprintf(string_buffer, sizeof(string_buffer), "Unknown (%x)", mod_id); + t->manufacturer = smbios_add_string(t->eos, string_buffer); + } } static void trim_trailing_whitespace(char *buffer, size_t buffer_size) @@ -256,8 +222,7 @@ static void trim_trailing_whitespace(char *buffer, size_t buffer_size) } /** This function will fill the corresponding part number */ -static void smbios_fill_dimm_part_number(const char *part_number, - struct smbios_type17 *t) +static void smbios_fill_dimm_part_number(const char *part_number, struct smbios_type17 *t) { int invalid; size_t i, len; @@ -303,21 +268,27 @@ static void smbios_fill_dimm_serial_number(const struct dimm_info *dimm, char serial[9]; snprintf(serial, sizeof(serial), "%02hhx%02hhx%02hhx%02hhx", - dimm->serial[0], dimm->serial[1], dimm->serial[2], - dimm->serial[3]); + dimm->serial[0], dimm->serial[1], dimm->serial[2], dimm->serial[3]); t->serial_number = smbios_add_string(t->eos, serial); } static int create_smbios_type17_for_dimm(struct dimm_info *dimm, - unsigned long *current, int *handle) + unsigned long *current, int *handle, + int type16_handle) { struct smbios_type17 *t = (struct smbios_type17 *)*current; memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; - t->clock_speed = dimm->ddr_frequency; - t->speed = dimm->ddr_frequency; + if (dimm->configured_speed_mts != 0) + t->clock_speed = dimm->configured_speed_mts; + else + t->clock_speed = dimm->ddr_frequency; + if (dimm->max_speed_mts != 0) + t->speed = dimm->max_speed_mts; + else + t->speed = dimm->ddr_frequency; t->type = SMBIOS_MEMORY_DEVICE; if (dimm->dimm_size < 0x7fff) { t->size = dimm->dimm_size; @@ -360,11 +331,13 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, t->maximum_voltage = dimm->vdd_voltage; /* Synchronous = 1 */ - t->type_detail = 0x0080; + t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; /* no handle for error information */ t->memory_error_information_handle = 0xFFFE; t->attributes = dimm->rank_per_dimm; t->handle = *handle; + t->phys_memory_array_handle = type16_handle; + *handle += 1; t->length = sizeof(struct smbios_type17) - 2; return t->length + smbios_string_table_len(t->eos); @@ -425,11 +398,6 @@ static const char *get_bios_version(void) return coreboot_version; } -const char *__weak smbios_mainboard_bios_version(void) -{ - return NULL; -} - static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -454,8 +422,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_rom_size = (rom_size / 65535) - 1; if (CONFIG_ROM_SIZE >= 1 * GiB) { - t->extended_bios_rom_size = - DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14); + t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14); } else { t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); } @@ -463,6 +430,8 @@ static int smbios_write_type0(unsigned long *current, int handle) t->system_bios_major_release = coreboot_major_revision; t->system_bios_minor_release = coreboot_minor_revision; + smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release); + t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED | BIOS_CHARACTERISTICS_SELECTABLE_BOOT | @@ -480,121 +449,6 @@ static int smbios_write_type0(unsigned long *current, int handle) return len; } -const char *__weak smbios_mainboard_serial_number(void) -{ - return CONFIG_MAINBOARD_SERIAL_NUMBER; -} - -const char *__weak smbios_mainboard_version(void) -{ - return CONFIG_MAINBOARD_VERSION; -} - -const char *__weak smbios_mainboard_manufacturer(void) -{ - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; -} - -const char *__weak smbios_mainboard_product_name(void) -{ - return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; -} - -const char *__weak smbios_mainboard_asset_tag(void) -{ - return ""; -} - -u8 __weak smbios_mainboard_feature_flags(void) -{ - return 0; -} - -const char *__weak smbios_mainboard_location_in_chassis(void) -{ - return ""; -} - -smbios_board_type __weak smbios_mainboard_board_type(void) -{ - return SMBIOS_BOARD_TYPE_UNKNOWN; -} - -/* - * System Enclosure or Chassis Types as defined in SMBIOS specification. - * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, - * convertible, or tablet enclosure will be used if the appropriate - * system type is selected. - */ -smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) -{ - if (CONFIG(SYSTEM_TYPE_LAPTOP)) - return SMBIOS_ENCLOSURE_LAPTOP; - else if (CONFIG(SYSTEM_TYPE_TABLET)) - return SMBIOS_ENCLOSURE_TABLET; - else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) - return SMBIOS_ENCLOSURE_CONVERTIBLE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) - return SMBIOS_ENCLOSURE_DETACHABLE; - else - return SMBIOS_ENCLOSURE_DESKTOP; -} - -const char *__weak smbios_system_serial_number(void) -{ - return smbios_mainboard_serial_number(); -} - -const char *__weak smbios_system_version(void) -{ - return smbios_mainboard_version(); -} - -const char *__weak smbios_system_manufacturer(void) -{ - return smbios_mainboard_manufacturer(); -} - -const char *__weak smbios_system_product_name(void) -{ - return smbios_mainboard_product_name(); -} - -void __weak smbios_system_set_uuid(u8 *uuid) -{ - /* leave all zero */ -} - -unsigned int __weak smbios_cpu_get_max_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -unsigned int __weak smbios_cpu_get_current_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -const char *__weak smbios_system_sku(void) -{ - return ""; -} - -const char * __weak smbios_chassis_version(void) -{ - return ""; -} - -const char * __weak smbios_chassis_serial_number(void) -{ - return ""; -} - -const char * __weak smbios_processor_serial_number(void) -{ - return ""; -} - static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) @@ -603,10 +457,27 @@ static int get_socket_type(void) return 0x13; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) return 0x15; + if (CONFIG(XEON_SP_COMMON_BASE)) + return 0x36; return 0x02; /* Unknown */ } +unsigned int __weak smbios_processor_external_clock(void) +{ + return 0; /* Unknown */ +} + +unsigned int __weak smbios_processor_characteristics(void) +{ + return 0; +} + +unsigned int __weak smbios_processor_family(struct cpuid_result res) +{ + return (res.eax > 0) ? 0x0c : 0x6; +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -616,12 +487,9 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_system_manufacturer()); - t->product_name = smbios_add_string(t->eos, - smbios_system_product_name()); - t->serial_number = smbios_add_string(t->eos, - smbios_system_serial_number()); + t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer()); + t->product_name = smbios_add_string(t->eos, smbios_system_product_name()); + t->serial_number = smbios_add_string(t->eos, smbios_system_serial_number()); t->sku = smbios_add_string(t->eos, smbios_system_sku()); t->version = smbios_add_string(t->eos, smbios_system_version()); #ifdef CONFIG_MAINBOARD_FAMILY @@ -633,8 +501,7 @@ static int smbios_write_type1(unsigned long *current, int handle) return len; } -static int smbios_write_type2(unsigned long *current, int handle, - const int chassis_handle) +static int smbios_write_type2(unsigned long *current, int handle, const int chassis_handle) { struct smbios_type2 *t = (struct smbios_type2 *)*current; int len = sizeof(struct smbios_type2); @@ -643,12 +510,9 @@ static int smbios_write_type2(unsigned long *current, int handle, t->type = SMBIOS_BOARD_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_mainboard_manufacturer()); - t->product_name = smbios_add_string(t->eos, - smbios_mainboard_product_name()); - t->serial_number = smbios_add_string(t->eos, - smbios_mainboard_serial_number()); + t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer()); + t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); + t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); t->asset_tag = smbios_add_string(t->eos, smbios_mainboard_asset_tag()); t->feature_flags = smbios_mainboard_feature_flags(); @@ -670,8 +534,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, - smbios_system_manufacturer()); + t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer()); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; @@ -690,6 +553,9 @@ static int smbios_write_type4(unsigned long *current, int handle) struct cpuid_result res; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); + uint16_t characteristics = 0; + static unsigned int cnt = 0; + char buf[8]; /* Provide sane defaults even for CPU without CPUID */ res.eax = res.edx = 0; @@ -702,11 +568,15 @@ static int smbios_write_type4(unsigned long *current, int handle) t->type = SMBIOS_PROCESSOR_INFORMATION; t->handle = handle; t->length = len - 2; + + snprintf(buf, sizeof(buf), "CPU%d", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + t->processor_id[0] = res.eax; t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = (res.eax > 0) ? 0x0c : 0x6; + t->processor_family = smbios_processor_family(res); t->processor_type = 3; /* System Processor */ /* * If CPUID leaf 11 is available, calculate "core count" by dividing @@ -724,25 +594,54 @@ static int smbios_write_type4(unsigned long *current, int handle) if (leaf_b_threads == 0) { leaf_b_threads = 1; } - t->core_count = leaf_b_cores / leaf_b_threads; + t->core_count2 = leaf_b_cores / leaf_b_threads; + t->core_count = t->core_count2 > 0xff ? 0xff : t->core_count2; + t->thread_count2 = leaf_b_cores; + t->thread_count = t->thread_count2 > 0xff ? 0xff : t->thread_count2; } else { t->core_count = (res.ebx >> 16) & 0xff; + t->core_count2 = t->core_count; + t->thread_count2 = t->core_count2; + t->thread_count = t->thread_count2; } /* Assume we enable all the cores always, capped only by MAX_CPUS */ t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); + t->core_enabled2 = MIN(t->core_count2, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); + t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED; t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { t->max_speed = cpuid_ebx(0x16); t->current_speed = cpuid_eax(0x16); /* base frequency */ + t->external_clock = cpuid_ecx(0x16); } else { t->max_speed = smbios_cpu_get_max_speed_mhz(); t->current_speed = smbios_cpu_get_current_speed_mhz(); + t->external_clock = smbios_processor_external_clock(); } + + if (cpu_have_cpuid()) { + res = cpuid(1); + + if ((res.ecx) & BIT(5)) + characteristics |= BIT(6); /* BIT6: Enhanced Virtualization */ + + if ((res.edx) & BIT(28)) + characteristics |= BIT(4); /* BIT4: Hardware Thread */ + + if (((cpuid_eax(0x80000000) - 0x80000000) + 1) > 2) { + res = cpuid(0x80000001); + + if ((res.edx) & BIT(20)) + characteristics |= BIT(5); /* BIT5: Execute Protection */ + } + } + t->processor_characteristics = characteristics | smbios_processor_characteristics(); + *current += len; return len; } @@ -752,15 +651,14 @@ static int smbios_write_type4(unsigned long *current, int handle) * Fill in some fields with constant values, as gathering the information * from CPUID is impossible. */ -static int -smbios_write_type7(unsigned long *current, - const int handle, - const u8 level, - const u8 sram_type, - const enum smbios_cache_associativity associativity, - const enum smbios_cache_type type, - const size_t max_cache_size, - const size_t cache_size) +static int smbios_write_type7(unsigned long *current, + const int handle, + const u8 level, + const u8 sram_type, + const enum smbios_cache_associativity associativity, + const enum smbios_cache_type type, + const size_t max_cache_size, + const size_t cache_size) { struct smbios_type7 *t = (struct smbios_type7 *)*current; int len = sizeof(struct smbios_type7); @@ -827,8 +725,7 @@ smbios_write_type7(unsigned long *current, } /* Convert the associativity as integer to the SMBIOS enum if available */ -static enum smbios_cache_associativity -smbios_cache_associativity(const u8 num) +static enum smbios_cache_associativity smbios_cache_associativity(const u8 num) { switch (num) { case 1: @@ -914,8 +811,7 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; - const size_t cache_size = assoc * partitions * cache_line_size * - number_of_sets; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; if (!cache_type) /* No more caches in the system */ @@ -1006,10 +902,7 @@ int smbios_write_type9(unsigned long *current, int *handle, t->type = SMBIOS_SYSTEM_SLOTS; t->handle = *handle; t->length = len - 2; - if (name) - t->slot_designation = smbios_add_string(t->eos, name); - else - t->slot_designation = smbios_add_string(t->eos, "SLOT"); + t->slot_designation = smbios_add_string(t->eos, name ? name : "SLOT"); t->slot_type = type; /* TODO add slot_id supoort, will be "_SUN" for ACPI devices */ t->slot_data_bus_width = bandwidth; @@ -1056,7 +949,53 @@ static int smbios_write_type11(unsigned long *current, int *handle) return len; } -static int smbios_write_type17(unsigned long *current, int *handle) +static int smbios_write_type16(unsigned long *current, int *handle) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + + int len; + int i; + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + printk(BIOS_INFO, "Create SMBIOS type 16\n"); + + if (meminfo->max_capacity_mib == 0 || meminfo->number_of_devices == 0) { + /* Fill in defaults if not provided */ + meminfo->number_of_devices = 0; + meminfo->max_capacity_mib = 0; + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { + meminfo->max_capacity_mib += meminfo->dimm[i].dimm_size; + meminfo->number_of_devices += !!meminfo->dimm[i].dimm_size; + } + } + + memset(t, 0, sizeof(*t)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len = sizeof(*t) - 2; + + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->memory_error_correction = meminfo->ecc_capable ? + MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; + + /* no error information handle available */ + t->memory_error_information_handle = 0xFFFE; + t->maximum_capacity = meminfo->max_capacity_mib * (MiB / KiB); + t->number_of_memory_devices = meminfo->number_of_devices; + + len += smbios_string_table_len(t->eos); + + *current += len; + (*handle)++; + return len; +} + +static int smbios_write_type17(unsigned long *current, int *handle, int type16) { int len = sizeof(struct smbios_type17); int totallen = 0; @@ -1068,17 +1007,72 @@ static int smbios_write_type17(unsigned long *current, int *handle) return 0; /* can't find mem info in cbmem */ printk(BIOS_INFO, "Create SMBIOS type 17\n"); - for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); - i++) { + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { struct dimm_info *dimm; dimm = &meminfo->dimm[i]; - len = create_smbios_type17_for_dimm(dimm, current, handle); + /* + * Windows 10 GetPhysicallyInstalledSystemMemory functions reads SMBIOS tables + * type 16 and type 17. The type 17 tables need to point to a type 16 table. + * Otherwise, the physical installed memory size is guessed from the system + * memory map, which results in a slightly smaller value than the actual size. + */ + len = create_smbios_type17_for_dimm(dimm, current, handle, type16); *current += len; totallen += len; } return totallen; } +static int smbios_write_type19(unsigned long *current, int *handle) +{ + struct smbios_type19 *t = (struct smbios_type19 *)*current; + int len = sizeof(struct smbios_type19); + int i; + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + memset(t, 0, sizeof(struct smbios_type19)); + + t->type = SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS; + t->length = len - 2; + t->handle = *handle; + + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { + if (meminfo->dimm[i].dimm_size > 0) { + t->extended_ending_address += meminfo->dimm[i].dimm_size; + t->partition_width++; + } + } + t->extended_ending_address *= MiB; + + /* Check if it fits into regular address */ + if (t->extended_ending_address >= KiB && + t->extended_ending_address < 0x40000000000ULL) { + /* + * FIXME: The starting address is SoC specific, but SMBIOS tables are only + * exported on x86 where it's always 0. + */ + + t->starting_address = 0; + t->ending_address = t->extended_ending_address / KiB - 1; + t->extended_starting_address = ~0; + t->extended_ending_address = ~0; + } else { + t->starting_address = ~0; + t->ending_address = ~0; + t->extended_starting_address = 0; + t->extended_ending_address--; + } + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + static int smbios_write_type32(unsigned long *current, int handle) { struct smbios_type32 *t = (struct smbios_type32 *)*current; @@ -1160,7 +1154,7 @@ static int smbios_write_type127(unsigned long *current, int handle) /* Generate Type41 entries from devicetree */ static int smbios_walk_device_tree_type41(struct device *dev, int *handle, - unsigned long *current) + unsigned long *current) { static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; @@ -1240,16 +1234,14 @@ static int smbios_walk_device_tree_type9(struct device *dev, int *handle, dev->path.pci.devfn); } -static int smbios_walk_device_tree(struct device *tree, int *handle, - unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { struct device *dev; int len = 0; for (dev = tree; dev; dev = dev->next) { if (dev->enabled && dev->ops && dev->ops->get_smbios_data) { - printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), - dev_name(dev)); + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } len += smbios_walk_device_tree_type9(dev, handle, current); @@ -1261,6 +1253,7 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; + struct smbios_entry30 *se3; unsigned long tables; int len = 0; int max_struct_size = 0; @@ -1273,43 +1266,44 @@ unsigned long smbios_write_tables(unsigned long current) current += sizeof(struct smbios_entry); current = ALIGN_UP(current, 16); + se3 = (struct smbios_entry30 *)current; + current += sizeof(struct smbios_entry30); + current = ALIGN_UP(current, 16); + tables = current; - update_max(len, max_struct_size, smbios_write_type0(¤t, - handle++)); - update_max(len, max_struct_size, smbios_write_type1(¤t, - handle++)); - update_max(len, max_struct_size, smbios_write_type2(¤t, - handle, handle + 1)); /* The chassis handle is the next one */ + update_max(len, max_struct_size, smbios_write_type0(¤t, handle++)); + update_max(len, max_struct_size, smbios_write_type1(¤t, handle++)); + + /* The chassis handle is the next one */ + update_max(len, max_struct_size, smbios_write_type2(¤t, handle, handle + 1)); handle++; - update_max(len, max_struct_size, smbios_write_type3(¤t, - handle++)); + update_max(len, max_struct_size, smbios_write_type3(¤t, handle++)); struct smbios_type4 *type4 = (struct smbios_type4 *)current; - update_max(len, max_struct_size, smbios_write_type4(¤t, - handle++)); - len += smbios_write_type7_cache_parameters(¤t, &handle, - &max_struct_size, type4); - update_max(len, max_struct_size, smbios_write_type11(¤t, - &handle)); + update_max(len, max_struct_size, smbios_write_type4(¤t, handle++)); + len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4); + update_max(len, max_struct_size, smbios_write_type11(¤t, &handle)); if (CONFIG(ELOG)) update_max(len, max_struct_size, - elog_smbios_write_type15(¤t,handle++)); - update_max(len, max_struct_size, smbios_write_type17(¤t, - &handle)); - update_max(len, max_struct_size, smbios_write_type32(¤t, - handle++)); + elog_smbios_write_type15(¤t, handle++)); + + const int type16 = handle; + update_max(len, max_struct_size, smbios_write_type16(¤t, &handle)); + update_max(len, max_struct_size, smbios_write_type17(¤t, &handle, type16)); + update_max(len, max_struct_size, smbios_write_type19(¤t, &handle)); + update_max(len, max_struct_size, smbios_write_type32(¤t, handle++)); update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, - &handle, ¤t)); + &handle, ¤t)); - update_max(len, max_struct_size, smbios_write_type127(¤t, - handle++)); + update_max(len, max_struct_size, smbios_write_type127(¤t, handle++)); + /* Install SMBIOS 2.1 entry point */ memset(se, 0, sizeof(struct smbios_entry)); memcpy(se->anchor, "_SM_", 4); se->length = sizeof(struct smbios_entry); - se->major_version = 2; - se->minor_version = 8; + se->major_version = 3; + se->minor_version = 0; se->max_struct_size = max_struct_size; se->struct_count = handle; memcpy(se->intermediate_anchor_string, "_DMI_", 5); @@ -1318,8 +1312,20 @@ unsigned long smbios_write_tables(unsigned long current) se->struct_table_length = len; se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, - sizeof(struct smbios_entry) - - 0x10); + sizeof(struct smbios_entry) - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); + + /* Install SMBIOS 3.0 entry point */ + memset(se3, 0, sizeof(struct smbios_entry30)); + memcpy(se3->anchor, "_SM3_", 5); + se3->length = sizeof(struct smbios_entry30); + se3->major_version = 3; + se3->minor_version = 0; + + se3->struct_table_address = (u64)tables; + se3->struct_table_length = len; + + se3->checksum = smbios_checksum((u8 *)se3, sizeof(struct smbios_entry30)); + return current; } diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c new file mode 100644 index 0000000000..4d8883f3cd --- /dev/null +++ b/src/arch/x86/smbios_defaults.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* this function will fill the corresponding locator */ +__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char locator[40]; + + snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", + dimm->channel_num, dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); + t->bank_locator = smbios_add_string(t->eos, locator); +} + +__weak const char *smbios_mainboard_bios_version(void) +{ + return NULL; +} + +__weak const char *smbios_mainboard_serial_number(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} + +__weak const char *smbios_mainboard_version(void) +{ + return CONFIG_MAINBOARD_VERSION; +} + +__weak const char *smbios_mainboard_manufacturer(void) +{ + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; +} + +__weak const char *smbios_mainboard_product_name(void) +{ + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +__weak const char *smbios_mainboard_asset_tag(void) +{ + return ""; +} + +__weak u8 smbios_mainboard_feature_flags(void) +{ + return 0; +} + +__weak const char *smbios_mainboard_location_in_chassis(void) +{ + return ""; +} + +__weak smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_UNKNOWN; +} + +__weak void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + *ec_major_revision = 0x0; + *ec_minor_revision = 0x0; +} + +/* + * System Enclosure or Chassis Types as defined in SMBIOS specification. + * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, + * convertible, or tablet enclosure will be used if the appropriate + * system type is selected. + */ +__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (CONFIG(SYSTEM_TYPE_LAPTOP)) + return SMBIOS_ENCLOSURE_LAPTOP; + else if (CONFIG(SYSTEM_TYPE_TABLET)) + return SMBIOS_ENCLOSURE_TABLET; + else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) + return SMBIOS_ENCLOSURE_DETACHABLE; + else + return SMBIOS_ENCLOSURE_DESKTOP; +} + +__weak const char *smbios_system_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +__weak const char *smbios_system_version(void) +{ + return smbios_mainboard_version(); +} + +__weak const char *smbios_system_manufacturer(void) +{ + return smbios_mainboard_manufacturer(); +} + +__weak const char *smbios_system_product_name(void) +{ + return smbios_mainboard_product_name(); +} + +__weak void smbios_system_set_uuid(u8 *uuid) +{ + /* leave all zero */ +} + +__weak unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak const char *smbios_system_sku(void) +{ + return ""; +} + +__weak const char *smbios_chassis_version(void) +{ + return ""; +} + +__weak const char *smbios_chassis_serial_number(void) +{ + return ""; +} + +__weak const char *smbios_processor_serial_number(void) +{ + return ""; +} diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index 087c59b8e7..b8d4fb985a 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -20,6 +20,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) +.code32 .section .text .global walkcbfs_asm diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index af4baf512b..3c76a49f55 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -144,7 +144,6 @@ struct cbfs_file_attr_align { uint32_t alignment; } __packed; - /*** Component sub-headers ***/ /* Following are component sub-headers for the "standard" diff --git a/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h new file mode 100644 index 0000000000..3a87cda1c4 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ +#if defined(__FreeBSD__) +#include +#else +#include +#endif diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index 3822e8c60f..73185a5051 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index b7e59ad35b..6393c01e6e 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -140,7 +140,6 @@ struct lb_record { uint32_t size; /* size of record (in bytes) */ }; - struct lb_memory_range { struct lb_uint64 start; struct lb_uint64 size; @@ -186,7 +185,6 @@ struct lb_timestamp { uint32_t timestamp; }; - /* 0xe is taken by v3 */ struct lb_serial { @@ -306,7 +304,6 @@ struct lb_framebuffer { uint8_t orientation; }; - struct lb_gpio { uint32_t port; uint32_t polarity; @@ -349,7 +346,6 @@ struct lb_x86_rom_mtrr { uint32_t index; }; - struct lb_strapping_id { uint32_t tag; uint32_t size; @@ -448,7 +444,6 @@ struct cmos_entries { variable length int aligned */ }; - /* CMOS enumerations record * This record is variable length. The text field may be * shorter than CMOS_MAX_TEXT_LENGTH. diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index b1e58c9780..dd352adaaa 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -185,7 +185,7 @@ static const struct timestamp_id_to_name { { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" }, { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" }, { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " }, - { TS_DONE_LOADING, "finished loading body (ignore for x86)" }, + { TS_DONE_LOADING, "finished loading body" }, { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, { TS_START_TPMPCR, "starting TPM PCR extend" }, diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 00bfb1e28b..467e8ff629 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -420,7 +420,6 @@ const struct region_device_ops xlate_rdev_rw_ops = { .eraseat = xlate_eraseat, }; - static void *incoherent_mmap(const struct region_device *rd, size_t offset, size_t size) { diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 4ca98dfff7..b27f3425dd 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -265,7 +265,6 @@ int sd_set_bus_width(struct storage_media *media) return 0; } - int sd_set_partition(struct storage_media *media, unsigned int partition_number) { diff --git a/src/console/Kconfig b/src/console/Kconfig index bad6c564fc..283488c27b 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -294,9 +294,9 @@ config CONSOLE_QEMU_DEBUGCON_PORT depends on CONSOLE_QEMU_DEBUGCON default 0x402 -config SPI_CONSOLE - bool "SPI debug console output" - depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH +config EM100PRO_SPI_CONSOLE + bool "EM100Pro SPI debug console output" + depends on HAVE_EM100PRO_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH help Enable support for the debug console on the Dediprog EM100Pro. This is currently working only in ramstage due to how the spi diff --git a/src/console/console.c b/src/console/console.c index 2f544a80f2..67da10794e 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -69,7 +69,6 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) console_tx_byte(*buffer++); } - #if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) void gdb_hw_init(void) { diff --git a/src/console/printk.c b/src/console/printk.c index c5e5f97aab..4a3de47832 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 273bc7ed72..c7bb585181 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -99,7 +99,6 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), return count; } - int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data) { diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 92e47aa3a2..a072a8b232 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,7 +1,6 @@ ################################################################################ ## Subdirectories ################################################################################ -subdirs-y += allwinner subdirs-y += amd subdirs-y += armltd subdirs-y += intel diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b276..1ccfa5d15b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -6,10 +6,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 142afbd27e..4bb289622c 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -97,7 +97,6 @@ static void model_15_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507ed06..e626ef1c74 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -6,10 +6,7 @@ config CPU_AMD_PI default y if CPU_AMD_PI_00730F01 default y if CPU_AMD_PI_00660F01 default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index a955d8c3c7..4b4a4abef3 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 57a5fe602c..df14668095 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -3,7 +3,7 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H -#include +#include void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); @@ -17,6 +17,11 @@ void set_feature_ctrl_lock(void); struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); +/* + * Returns true if CPU supports Hyper-Threading. + */ +bool intel_ht_supported(void); + /* * Returns true if it's not thread 0 on a hyperthreading enabled core. */ diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index f2c386db4c..3e5b578d22 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -103,7 +103,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 8, .bit_offset = 0, - .access_size = 4, + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, .addrl = 0, .addrh = 0, }; @@ -111,7 +111,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) .space_id = ACPI_ADDRESS_SPACE_MEMORY, .bit_width = 0, .bit_offset = 0, - .access_size = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, .addrl = 0, .addrh = 0, }; @@ -259,7 +259,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; msr.bit_width = 32; msr.bit_offset = 0; - msr.access_size = 0; + msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; msr.addrl = 1; config->regs[CPPC_AUTO_SELECT] = msr; } diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 7772171f0d..3d46bbc4b9 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -45,6 +45,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index d68614974f..fce7576673 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -3,6 +3,13 @@ #include #include #include +#include + +bool intel_ht_supported(void) +{ + /* Is HyperThreading supported? */ + return !!(cpuid_edx(1) & CPUID_FEAURE_HTT); +} /* * Return true if running thread does not have the smallest lapic ID @@ -13,8 +20,7 @@ bool intel_ht_sibling(void) struct cpuid_result result; unsigned int core_ids, apic_ids, threads; - /* Is Hyper-Threading supported */ - if (!(cpuid_edx(1) & CPUID_FEAURE_HTT)) + if (!intel_ht_supported()) return false; apic_ids = 1; diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 54cb99fb9e..fbfa71456b 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,11 +6,8 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC @@ -22,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select HAVE_ASAN_IN_ROMSTAGE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1f84b821a9..1832e63967 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -6,4 +6,6 @@ void intel_cpu_haswell_finalize_smm(void) { + /* Lock memory configuration to protect SMM */ + msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638da0..ac5dec6277 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -618,7 +618,7 @@ static void set_max_ratio(void) } wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "haswell: frequency set to %d\n", + printk(BIOS_DEBUG, "CPU: frequency set to %d\n", ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); } @@ -638,8 +638,7 @@ static void set_energy_perf_bias(u8 policy) msr.lo |= policy & 0xf; wrmsr(IA32_ENERGY_PERF_BIAS, msr); - printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", - policy); + printk(BIOS_DEBUG, "CPU: energy policy set to %u\n", policy); } static void configure_mca(void) @@ -778,6 +777,8 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 0f7585ae69..abc005c6f0 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -33,8 +33,6 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) - - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) @@ -111,7 +109,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 329b693140..ef3367d019 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -52,7 +52,6 @@ void intel_sibling_init(struct device *cpu) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 79dda288b6..777eff6180 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index e040e0d698..c130894853 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -9,7 +9,7 @@ #include #include #include -#include + #include "chip.h" static void init_timer(void) @@ -166,6 +166,8 @@ static void configure_emttm_tables(void) wrmsr(MSR_EMTTM_CR_TABLE(5), msr); } +#define IA32_PECI_CTL 0x5a0 + static void configure_misc(const int eist, const int tm2, const int emttm) { msr_t msr; @@ -208,6 +210,13 @@ static void configure_misc(const int eist, const int tm2, const int emttm) msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); } + + /* Enable PECI + WARNING: due to Erratum AW67 described in Intel document #318733 + the microcode must be updated before this MSR is written to. */ + msr = rdmsr(IA32_PECI_CTL); + msr.lo |= 1; + wrmsr(IA32_PECI_CTL, msr); } #define PIC_SENS_CFG 0x1aa @@ -233,7 +242,6 @@ static void model_1067x_init(struct device *cpu) { char processor_name[49]; - /* Gather some information: */ const struct cpuid_result cpuid1 = cpuid(1); @@ -256,7 +264,6 @@ static void model_1067x_init(struct device *cpu) /* Test for TM2 only if EIST is available. */ const char tm2 = eist && (cpuid1.ecx & (1 << 8)); - /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -292,7 +299,7 @@ static struct device_operations cpu_dev_ops = { }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x10676 }, { X86_VENDOR_INTEL, 0x10677 }, { X86_VENDOR_INTEL, 0x1067A }, { 0, 0 }, diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 3404e7fb4a..b56d106922 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -63,7 +63,7 @@ static void per_cpu_smm_trigger(void) } else { if (!CONFIG(SET_IA32_FC_LOCK_BIT)) printk(BIOS_INFO, - "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n"); + "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n"); ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0); wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl); } diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 1ba8894940..bf9256af45 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_106CX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 927bebbbf2..8c462f1874 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 39beb227bd..04b9e6785b 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -5,11 +5,8 @@ if CPU_INTEL_MODEL_2065X config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 3208e10849..ff4a255dfd 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -110,7 +110,6 @@ int cpu_config_tdp_levels(void) return (platform_info.hi >> 1) & 3; } - static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; @@ -158,7 +157,6 @@ static void enable_lapic_tpr(void) wrmsr(MSR_PIC_MSG_CONTROL, msr); } - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -282,7 +280,6 @@ static void post_mp_init(void) smm_lock(); } - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c6a50207c5..5098ac76d5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -5,11 +5,8 @@ if CPU_INTEL_MODEL_206AX config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9ff0673ece..b24f411f00 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -9,23 +8,15 @@ #include #include #include +#include + #include "model_206ax.h" #include "chip.h" -static int get_cores_per_package(void) +static int get_logical_cores_per_package(void) { - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; + msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT); + return msr.lo & 0xffff; } static void generate_cstate_entries(acpi_cstate_t *cstates, @@ -287,7 +278,7 @@ void generate_cpu_entries(const struct device *device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); + int cores_per_package = get_logical_cores_per_package(); int numcpus = totalcores/cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index c7579f1764..37fbefdf13 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -2,7 +2,6 @@ #include #include -#include #include "model_206ax.h" /* MSR Documentation based on diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index e69d4fa8da..cd828e8199 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -534,7 +534,6 @@ static void post_mp_init(void) smm_lock(); } - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 6a1d09c35f..2eaa55e5dc 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_65X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 283927ff60..7fdb67f6c8 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_67X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 4f5d1acd2e..1b57dfc9df 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -2,8 +2,5 @@ config CPU_INTEL_MODEL_68X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index eb4b6751cd..a87228c7f4 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_6BX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 3af52722f3..31897ad7aa 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_6EX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 43d4599fc6..16c6866f45 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index e3d327ca02..1911ebc6c3 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index f1d64b7454..f6f838de39 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,5 @@ subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-y += ../smm/gen1 -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) \ + 3rdparty/intel-microcode/intel-ucode/06-16-01 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index b81eca4cfb..d0987b4a63 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #define HIGHEST_CLEVEL 3 static void configure_c_states(void) @@ -147,7 +146,6 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x10661 }, /* Intel Core 2 Celeron Conroe-L */ - { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */ { 0, 0 }, }; diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index d00fc2436a..18844d13a9 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,7 +1,4 @@ config CPU_INTEL_MODEL_6XX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index dcf94415d0..876be2dd22 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_F2X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1caf..4d5e395d54 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,10 +1,6 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b51cd..d146dd494d 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,8 +1,4 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP + select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index ce3634b667..57d1fd4af0 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -189,7 +189,6 @@ int calculate_l2_latency(void) return 0; } - /* Setup address, data_high:data_low into the L2 * control registers and then issue command with correct cache way */ diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d17fe0ca69..ae2440daab 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -25,7 +25,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index fba5df2f86..9235272002 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -104,7 +104,6 @@ void speedstep_gen_pstates(sst_table_t *const table) /* Gather speedstep limits. */ speedstep_get_limits(¶ms); - /*\ First, find the number of normal states: \*/ /* Calculate with doubled values to work @@ -130,7 +129,6 @@ void speedstep_gen_pstates(sst_table_t *const table) if (states < 2) /* Report at least two normal states. */ states = 2; - /*\ Now, fill the table: \*/ table->num_states = 0; diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 21ada02a5d..87d02fc030 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -2,12 +2,22 @@ config CPU_QEMU_X86 bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SMM_ASEG + +if CPU_QEMU_X86 + +config CPU_QEMU_X86_64 + bool "Experimental 64bit support" + select ARCH_ALL_STAGES_X86_64 + select ARCH_POSTCAR_X86_64 + +config CPU_QEMU_X86_32 + bool + default n if CPU_QEMU_X86_64 + default y + select ARCH_ALL_STAGES_X86_32 + select ARCH_POSTCAR_X86_32 +endif diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 30f9f9ceb2..197e0fd8e8 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -27,13 +27,17 @@ cache_as_ram: /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) - movd %mm1, %rdi - shld %rdi, 32 + movd %mm2, %rdi + shlq $32, %rdi movd %mm1, %rsi or %rsi, %rdi - movd %mm2, %rsi + + movd %mm0, %rsi #else sub $4, %esp diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig deleted file mode 100644 index 119e84bfc1..0000000000 --- a/src/cpu/ti/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/cpu/ti/am335x/Kconfig" diff --git a/src/cpu/ti/Makefile.inc b/src/cpu/ti/Makefile.inc deleted file mode 100644 index 64b22f62f2..0000000000 --- a/src/cpu/ti/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_TI_AM335X) += am335x diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 48837d96a9..6722cfdf3f 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -12,14 +12,22 @@ #include #include +#if defined(__RAMSTAGE__) +#include +#define CODE_SEG RAM_CODE_SEG +#define DATA_SEG RAM_DATA_SEG +#else #include +#define CODE_SEG ROM_CODE_SEG +#define DATA_SEG ROM_DATA_SEG +#endif drop_longmode: /* Ensure cache is clean. */ wbinvd /* Set 32-bit code segment and ss */ - mov $ROM_CODE_SEG, %rcx + mov $CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ call SetCodeSelector32 @@ -54,7 +62,7 @@ __longmode_compatibility: /* Running in 32-bit compatibility mode */ /* Use flat data segment */ - movl $ROM_DATA_SEG, %eax + movl $DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5394cd023d..b3a16bcf63 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -121,6 +121,14 @@ config SMM_STUB_STACK_SIZE endif +config X86_SMM_LOADER_VERSION2 + bool + default n + depends on HAVE_SMI_HANDLER + help + This option enables SMM module loader that works with server + platforms which may contain more than 32 CPU threads. + config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4005..4870529cfe 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -106,7 +106,6 @@ struct saved_msr { uint32_t hi; } __packed; - /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ extern char _binary_sipi_vector_start[]; @@ -726,12 +725,21 @@ static void asmlinkage smm_do_relocation(void *arg) * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ +#if CONFIG(X86_SMM_LOADER_VERSION2) + perm_smbase = smm_get_cpu_smbase(cpu); + mp_state.perm_smbase = perm_smbase; + if (!perm_smbase) { + printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); + return; + } +#else perm_smbase = mp_state.perm_smbase; perm_smbase -= cpu * runtime->save_state_size; - - printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); +#endif /* Setup code checks this callback for validity. */ + printk(BIOS_INFO, "%s : curr_smbase 0x%x perm_smbase 0x%x, cpu = %d\n", + __func__, (int)curr_smbase, (int)perm_smbase, cpu); mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); if (CONFIG(STM)) { @@ -758,9 +766,17 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) static int install_relocation_handler(int num_cpus, size_t save_state_size) { + int cpus = num_cpus; +#if CONFIG(X86_SMM_LOADER_VERSION2) + /* Default SMRAM size is not big enough to concurrently + * handle relocation for more than ~32 CPU threads + * therefore, relocate 1 by 1. */ + cpus = 1; +#endif + struct smm_loader_params smm_params = { .per_cpu_stack_size = CONFIG_SMM_STUB_STACK_SIZE, - .num_concurrent_stacks = num_cpus, + .num_concurrent_stacks = cpus, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = 1, .handler = smm_do_relocation, @@ -770,9 +786,10 @@ static int install_relocation_handler(int num_cpus, size_t save_state_size) if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 0); - if (smm_setup_relocation_handler(&smm_params)) + if (smm_setup_relocation_handler(&smm_params)) { + printk(BIOS_ERR, "%s: smm setup failed\n", __func__); return -1; - + } adjust_smm_apic_id_map(&smm_params); return 0; @@ -781,8 +798,13 @@ static int install_relocation_handler(int num_cpus, size_t save_state_size) static int install_permanent_handler(int num_cpus, uintptr_t smbase, size_t smsize, size_t save_state_size) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to 1KiB. */ + /* + * All the CPUs will relocate to permanaent handler now. Set parameters + * needed for all CPUs. The placement of each CPUs entry point is + * determined by the loader. This code simply provides the beginning of + * SMRAM region, the number of CPUs who will use the handler, the stack + * size and save state size for each CPU. + */ struct smm_loader_params smm_params = { .per_cpu_stack_size = CONFIG_SMM_MODULE_STACK_SIZE, .num_concurrent_stacks = num_cpus, @@ -794,7 +816,7 @@ static int install_permanent_handler(int num_cpus, uintptr_t smbase, if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 1); - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); + printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); if (smm_load_module((void *)smbase, smsize, &smm_params)) return -1; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a8a2..1273a6cf27 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,6 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_X86_SMM_LOADER_VERSION2),y) +ramstage-y += smm_module_loaderv2.c +else ramstage-y += smm_module_loader.c +endif ramstage-y += smi_trigger.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 8fd95bb563..077fa8db8f 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -120,6 +120,32 @@ static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) return (void *)base; } +/* This returns the SMM revision from the savestate of CPU0, + which is assumed to be the same for all CPU's. See the memory + map in smmhandler.S */ +uint32_t smm_revision(void) +{ + return *(uint32_t *)(SMM_BASE + SMM_ENTRY_OFFSET * 2 - SMM_REVISION_OFFSET_FROM_TOP); +} + +void *smm_get_save_state(int cpu) +{ + switch (smm_revision()) { + case 0x00030002: + case 0x00030007: + return smm_save_state(SMM_BASE, SMM_LEGACY_ARCH_OFFSET, cpu); + case 0x00030100: + return smm_save_state(SMM_BASE, SMM_EM64T100_ARCH_OFFSET, cpu); + case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ + return smm_save_state(SMM_BASE, SMM_EM64T101_ARCH_OFFSET, cpu); + case 0x00020064: + case 0x00030064: + return smm_save_state(SMM_BASE, SMM_AMD64_ARCH_OFFSET, cpu); + } + + return NULL; +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {SMM_BASE, SMM_DEFAULT_SIZE}; @@ -133,9 +159,10 @@ bool smm_region_overlaps_handler(const struct region *r) * @param smm_revision revision of the smm state save map */ -void smi_handler(u32 smm_revision) +void smi_handler(void) { unsigned int node; + const uint32_t smm_rev = smm_revision(); smm_state_save_area_t state_save; u32 smm_base = SMM_BASE; /* ASEG */ @@ -163,7 +190,7 @@ void smi_handler(u32 smm_revision) printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_revision) { + switch (smm_rev) { case 0x00030002: case 0x00030007: state_save.type = LEGACY; @@ -191,7 +218,7 @@ void smi_handler(u32 smm_revision) SMM_AMD64_ARCH_OFFSET, node); break; default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); + printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev); printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 02682b4191..3ba5684f35 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -69,7 +69,6 @@ static void smi_set_eos(void) southbridge_smi_set_eos(); } - static u32 pci_orig; /** @@ -88,7 +87,6 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } - static const struct smm_runtime *smm_runtime; struct global_nvs *gnvs; @@ -99,13 +97,20 @@ void *smm_get_save_state(int cpu) /* This function assumes all save states start at top of default * SMRAM size space and are staggered down by save state size. */ - base = (void *)smm_runtime->smbase; + base = (void *)(uintptr_t)smm_runtime->smbase; base += SMM_DEFAULT_SIZE; base -= (cpu + 1) * smm_runtime->save_state_size; return base; } +uint32_t smm_revision(void) +{ + const uintptr_t save_state = (uintptr_t)(smm_get_save_state(0)); + + return *(uint32_t *)(save_state + smm_runtime->save_state_size - SMM_REVISION_OFFSET_FROM_TOP); +} + bool smm_region_overlaps_handler(const struct region *r) { const struct region r_smm = {smm_runtime->smbase, smm_runtime->smm_size}; diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c new file mode 100644 index 0000000000..22f336ec8d --- /dev/null +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -0,0 +1,654 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#define FXSAVE_SIZE 512 +#define SMM_CODE_SEGMENT_SIZE 0x10000 +/* FXSAVE area during relocation. While it may not be strictly needed the + SMM stub code relies on the FXSAVE area being non-zero to enable SSE + instructions within SMM mode. */ +static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] +__attribute__((aligned(16))); + +/* + * Components that make up the SMRAM: + * 1. Save state - the total save state memory used + * 2. Stack - stacks for the CPUs in the SMM handler + * 3. Stub - SMM stub code for calling into handler + * 4. Handler - C-based SMM handler. + * + * The components are assumed to consist of one consecutive region. + */ + +/* These parameters are used by the SMM stub code. A pointer to the params + * is also passed to the C-base handler. */ +struct smm_stub_params { + u32 stack_size; + u32 stack_top; + u32 c_handler; + u32 c_handler_arg; + u32 fxsave_area; + u32 fxsave_area_size; + struct smm_runtime runtime; +} __packed; + +/* + * The stub is the entry point that sets up protected mode and stacks for each + * CPU. It then calls into the SMM handler module. It is encoded as an rmodule. + */ +extern unsigned char _binary_smmstub_start[]; + +/* Per CPU minimum stack size. */ +#define SMM_MINIMUM_STACK_SIZE 32 + +struct cpu_smm_info { + uint8_t active; + uintptr_t smbase; + uintptr_t entry; + uintptr_t ss_start; + uintptr_t code_start; + uintptr_t code_end; +}; +struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; + +/* + * This method creates a map of all the CPU entry points, save state locations + * and the beginning and end of code segments for each CPU. This map is used + * during relocation to properly align as many CPUs that can fit into the SMRAM + * region. For more information on how SMRAM works, refer to the latest Intel + * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the + * following regions: + * +-----------------+ Top of SMRAM + * | | <- MSEG, FXSAVE + * +-----------------+ + * | common | + * | smi handler | 64K + * | | + * +-----------------+ + * | CPU 0 code seg | + * +-----------------+ + * | CPU 1 code seg | + * +-----------------+ + * | CPU x code seg | + * +-----------------+ + * | | + * | | + * +-----------------+ + * | stacks | + * +-----------------+ <- START of SMRAM + * + * The code below checks when a code segment is full and begins placing the remainder + * CPUs in the lower segments. The entry point for each CPU is smbase + 0x8000 + * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state + * area grows downward into the CPUs entry point. Therefore staggering too many + * CPUs in one 32K block will corrupt CPU0's entry code as the save states move + * downward. + * input : smbase of first CPU (all other CPUs + * will go below this address) + * input : num_cpus in the system. The map will + * be created from 0 to num_cpus. + */ +static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, + const struct smm_loader_params *params) +{ + unsigned int i; + struct rmodule smm_stub; + unsigned int ss_size = params->per_cpu_save_state_size, stub_size; + unsigned int smm_entry_offset = params->smm_main_entry_offset; + unsigned int seg_count = 0, segments = 0, available; + unsigned int cpus_in_segment = 0; + unsigned int base = smbase; + + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); + return 0; + } + + stub_size = rmodule_memory_size(&smm_stub); + /* How many CPUs can fit into one 64K segment? */ + available = 0xFFFF - smm_entry_offset - ss_size - stub_size; + if (available > 0) { + cpus_in_segment = available / ss_size; + /* minimum segments needed will always be 1 */ + segments = num_cpus / cpus_in_segment + 1; + printk(BIOS_DEBUG, + "%s: cpus allowed in one segment %d\n", __func__, cpus_in_segment); + printk(BIOS_DEBUG, + "%s: min # of segments needed %d\n", __func__, segments); + } else { + printk(BIOS_ERR, "%s: not enough space in SMM to setup all CPUs\n", __func__); + printk(BIOS_ERR, " save state & stub size need to be reduced\n"); + printk(BIOS_ERR, " or increase SMRAM size\n"); + return 0; + } + + if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) { + printk(BIOS_ERR, + "%s: increase MAX_CPUS in Kconfig\n", __func__); + return 0; + } + + for (i = 0; i < num_cpus; i++) { + cpus[i].smbase = base; + cpus[i].entry = base + smm_entry_offset; + cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); + cpus[i].code_start = cpus[i].entry; + cpus[i].code_end = cpus[i].entry + stub_size; + cpus[i].active = 1; + base -= ss_size; + seg_count++; + if (seg_count >= cpus_in_segment) { + base -= smm_entry_offset; + seg_count = 0; + } + } + + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + seg_count = 0; + for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); + printk(BIOS_DEBUG, + " smbase %zx entry %zx\n", + cpus[i].smbase, cpus[i].entry); + printk(BIOS_DEBUG, + " ss_start %zx code_end %zx\n", + cpus[i].ss_start, cpus[i].code_end); + seg_count++; + if (seg_count >= cpus_in_segment) { + printk(BIOS_DEBUG, + "-------------NEW CODE SEGMENT --------------\n"); + seg_count = 0; + } + } + } + return 1; +} + +/* + * This method expects the smm relocation map to be complete. + * This method does not read any HW registers, it simply uses a + * map that was created during SMM setup. + * input: cpu_num - cpu number which is used as an index into the + * map to return the smbase + */ +u32 smm_get_cpu_smbase(unsigned int cpu_num) +{ + if (cpu_num < CONFIG_MAX_CPUS) { + if (cpus[cpu_num].active) + return cpus[cpu_num].smbase; + } + return 0; +} + +/* + * This method assumes that at least 1 CPU has been set up from + * which it will place other CPUs below its smbase ensuring that + * save state does not clobber the first CPUs init code segment. The init + * code which is the smm stub code is the same for all CPUs. They enter + * smm, setup stacks (based on their apic id), enter protected mode + * and then jump to the common smi handler. The stack is allocated + * at the beginning of smram (aka tseg base, not smbase). The stack + * pointer for each CPU is calculated by using its apic id + * (code is in smm_stub.s) + * Each entry point will now have the same stub code which, sets up the CPU + * stack, enters protected mode and then jumps to the smi handler. It is + * important to enter protected mode before the jump because the "jump to + * address" might be larger than the 20bit address supported by real mode. + * SMI entry right now is in real mode. + * input: smbase - this is the smbase of the first cpu not the smbase + * where tseg starts (aka smram_start). All CPUs code segment + * and stack will be below this point except for the common + * SMI handler which is one segment above + * input: num_cpus - number of cpus that need relocation including + * the first CPU (though its code is already loaded) + * input: top of stack (stacks work downward by default in Intel HW) + * output: return -1, if runtime smi code could not be installed. In + * this case SMM will not work and any SMI's generated will + * cause a CPU shutdown or general protection fault because + * the appropriate smi handling code was not installed + */ + +static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, + unsigned int stack_top, const struct smm_loader_params *params) +{ + unsigned int i; + unsigned int size; + if (smm_create_map(smbase, num_cpus, params)) { + /* + * Ensure there was enough space and the last CPUs smbase + * did not encroach upon the stack. Stack top is smram start + * + size of stack. + */ + if (cpus[num_cpus].active) { + if (cpus[num_cpus - 1].smbase + + params->smm_main_entry_offset < stack_top) { + printk(BIOS_ERR, "%s: stack encroachment\n", __func__); + printk(BIOS_ERR, "%s: smbase %zx, stack_top %x\n", + __func__, cpus[num_cpus].smbase, stack_top); + return 0; + } + } + } else { + printk(BIOS_ERR, "%s: unable to place smm entry code\n", __func__); + return 0; + } + + printk(BIOS_INFO, "%s: smbase %zx, stack_top %x\n", + __func__, cpus[num_cpus-1].smbase, stack_top); + + /* start at 1, the first CPU stub code is already there */ + size = cpus[0].code_end - cpus[0].code_start; + for (i = 1; i < num_cpus; i++) { + memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); + printk(BIOS_DEBUG, + "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", + cpus[i].code_start, i); + printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", + __func__, cpus[0].code_start, cpus[i].code_start, size); + } + return 1; +} + +/* + * Place stacks in base -> base + size region, but ensure the stacks don't + * overlap the staggered entry points. + */ +static void *smm_stub_place_stacks(char *base, size_t size, + struct smm_loader_params *params) +{ + size_t total_stack_size; + char *stacks_top; + + /* If stack space is requested assume the space lives in the lower + * half of SMRAM. */ + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + printk(BIOS_DEBUG, "%s: cpus: %zx : stack space: needed -> %zx\n", + __func__, params->num_concurrent_stacks, + total_stack_size); + printk(BIOS_DEBUG, " available -> %zx : per_cpu_stack_size : %zx\n", + size, params->per_cpu_stack_size); + + /* There has to be at least one stack user. */ + if (params->num_concurrent_stacks < 1) + return NULL; + + /* Total stack size cannot fit. */ + if (total_stack_size > size) + return NULL; + + /* Stacks extend down to SMBASE */ + stacks_top = &base[total_stack_size]; + printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); + + return stacks_top; +} + +/* + * Place the staggered entry points for each CPU. The entry points are + * staggered by the per CPU SMM save state size extending down from + * SMM_ENTRY_OFFSET. + */ +static int smm_stub_place_staggered_entry_points(char *base, + const struct smm_loader_params *params, const struct rmodule *smm_stub) +{ + size_t stub_entry_offset; + int rc = 1; + stub_entry_offset = rmodule_entry_offset(smm_stub); + /* Each CPU now has its own stub code, which enters protected mode, + * sets up the stack, and then jumps to common SMI handler + */ + if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { + rc = smm_place_entry_code((unsigned int)base, + params->num_concurrent_save_states, + (unsigned int)params->stack_top, params); + } + return rc; +} + +/* + * The stub setup code assumes it is completely contained within the + * default SMRAM size (0x10000) for the default SMI handler (entry at + * 0x30000), but no assumption should be made for the permanent SMI handler. + * The placement of CPU entry points for permanent handler are determined + * by the number of CPUs in the system and the amount of SMRAM. + * There are potentially 3 regions to place + * within the default SMRAM size: + * 1. Save state areas + * 2. Stub code + * 3. Stack areas + * + * The save state and smm stack are treated as contiguous for the number of + * concurrent areas requested. The save state always lives at the top of the + * the CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain + * number of CPUs with staggered entry points until the save state area comes + * down far enough to overwrite/corrupt the entry code (stub code). Therefore, + * an SMM map is created to avoid this corruption, see smm_create_map() above. + * This module setup code works for the default (0x30000) SMM handler setup and the + * permanent SMM handler. + */ +static int smm_module_setup_stub(void *smbase, size_t smm_size, + struct smm_loader_params *params, + void *fxsave_area) +{ + size_t total_save_state_size; + size_t smm_stub_size; + size_t stub_entry_offset; + char *smm_stub_loc; + void *stacks_top; + size_t size; + char *base; + size_t i; + struct smm_stub_params *stub_params; + struct rmodule smm_stub; + unsigned int total_size_all; + base = smbase; + size = smm_size; + + /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { + printk(BIOS_ERR, "%s: not enough stacks\n", __func__); + return -1; + } + + /* Fail if can't parse the smm stub rmodule. */ + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s: unable to parse smm stub\n", __func__); + return -1; + } + + /* Adjust remaining size to account for save state. */ + total_save_state_size = params->per_cpu_save_state_size * + params->num_concurrent_save_states; + if (total_save_state_size > size) { + printk(BIOS_ERR, + "%s: more state save space needed:need -> %zx:available->%zx\n", + __func__, total_save_state_size, size); + return -1; + } + + size -= total_save_state_size; + + /* The save state size encroached over the first SMM entry point. */ + if (size <= params->smm_main_entry_offset) { + printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %x\n", + __func__, size, params->smm_main_entry_offset); + return -1; + } + + /* Need a minimum stack size and alignment. */ + if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || + (params->per_cpu_stack_size & 3) != 0) { + printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); + return -1; + } + + smm_stub_loc = NULL; + smm_stub_size = rmodule_memory_size(&smm_stub); + stub_entry_offset = rmodule_entry_offset(&smm_stub); + + /* Put the stub at the main entry point */ + smm_stub_loc = &base[params->smm_main_entry_offset]; + + /* Stub is too big to fit. */ + if (smm_stub_size > (size - params->smm_main_entry_offset)) { + printk(BIOS_ERR, "%s: stub is too big to fit\n", __func__); + return -1; + } + + /* The stacks, if requested, live in the lower half of SMRAM space + * for default handler, but for relocated handler it lives at the beginning + * of SMRAM which is TSEG base + */ + size = params->num_concurrent_stacks * params->per_cpu_stack_size; + stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params); + if (stacks_top == NULL) { + printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__); + printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__, + base, size); + return -1; + } + params->stack_top = stacks_top; + /* Load the stub. */ + if (rmodule_load(smm_stub_loc, &smm_stub)) { + printk(BIOS_ERR, "%s: load module failed\n", __func__); + return -1; + } + + if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { + printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); + return -1; + } + + /* Setup the parameters for the stub code. */ + stub_params = rmodule_parameters(&smm_stub); + stub_params->stack_top = (uintptr_t)stacks_top; + stub_params->stack_size = params->per_cpu_stack_size; + stub_params->c_handler = (uintptr_t)params->handler; + stub_params->c_handler_arg = (uintptr_t)params->handler_arg; + stub_params->fxsave_area = (uintptr_t)fxsave_area; + stub_params->fxsave_area_size = FXSAVE_SIZE; + stub_params->runtime.smbase = (uintptr_t)smbase; + stub_params->runtime.smm_size = smm_size; + stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + stub_params->runtime.num_cpus = params->num_concurrent_stacks; + + printk(BIOS_DEBUG, "%s: stack_end = 0x%x\n", + __func__, stub_params->runtime.smbase); + printk(BIOS_DEBUG, + "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); + printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", + __func__, stub_params->stack_size); + printk(BIOS_DEBUG, "%s: runtime.smbase = 0x%x\n", + __func__, stub_params->runtime.smbase); + printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, + stub_params->runtime.start32_offset); + printk(BIOS_DEBUG, "%s: runtime.smm_size = 0x%zx\n", + __func__, smm_size); + printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", + __func__, stub_params->runtime.save_state_size); + printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", + __func__, (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus)); + total_size_all = stub_params->stack_size + + (stub_params->runtime.save_state_size * + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s: total_size_all = 0x%x\n", __func__, + total_size_all); + + /* Initialize the APIC id to CPU number table to be 1:1 */ + for (i = 0; i < params->num_concurrent_stacks; i++) + stub_params->runtime.apic_id_to_cpu[i] = i; + + /* Allow the initiator to manipulate SMM stub parameters. */ + params->runtime = &stub_params->runtime; + + printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", + smm_stub_loc, params->handler, params->handler_arg); + return 0; +} + +/* + * smm_setup_relocation_handler assumes the callback is already loaded in + * memory. i.e. Another SMM module isn't chained to the stub. The other + * assumption is that the stub will be entered from the default SMRAM + * location: 0x30000 -> 0x40000. + */ +int smm_setup_relocation_handler(struct smm_loader_params *params) +{ + void *smram = (void *)(SMM_DEFAULT_BASE); + printk(BIOS_SPEW, "%s: enter\n", __func__); + /* There can't be more than 1 concurrent save state for the relocation + * handler because all CPUs default to 0x30000 as SMBASE. */ + if (params->num_concurrent_save_states > 1) + return -1; + + /* A handler has to be defined to call for relocation. */ + if (params->handler == NULL) + return -1; + + /* Since the relocation handler always uses stack, adjust the number + * of concurrent stack users to be CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks == 0) + params->num_concurrent_stacks = CONFIG_MAX_CPUS; + + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + params->smram_start = SMM_DEFAULT_BASE; + params->smram_end = SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE; + return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, + params, fxsave_area_relocation); + printk(BIOS_SPEW, "%s: exit\n", __func__); +} + +/* + *The SMM module is placed within the provided region in the following + * manner: + * +-----------------+ <- smram + size + * | BIOS resource | + * | list (STM) | + * +-----------------+ + * | fxsave area | + * +-----------------+ + * | smi handler | + * | ... | + * +-----------------+ <- cpu0 + * | stub code | <- cpu1 + * | stub code | <- cpu2 + * | stub code | <- cpu3, etc + * | | + * | | + * | | + * | stacks | + * +-----------------+ <- smram start + + * It should be noted that this algorithm will not work for + * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm + * expects a region large enough to encompass the handler and stacks + * as well as the SMM_DEFAULT_SIZE. + */ +int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) +{ + struct rmodule smm_mod; + size_t total_stack_size; + size_t handler_size; + size_t module_alignment; + size_t alignment_size; + size_t fxsave_size; + void *fxsave_area; + size_t total_size = 0; + char *base; + + if (size <= SMM_DEFAULT_SIZE) + return -1; + + /* Load main SMI handler at the top of SMRAM + * everything else will go below + */ + base = smram; + base += size; + params->smram_start = (uintptr_t)smram; + params->smram_end = params->smram_start + size; + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + + /* Fail if can't parse the smm rmodule. */ + if (rmodule_parse(&_binary_smm_start, &smm_mod)) + return -1; + + /* Clear SMM region */ + if (CONFIG(DEBUG_SMI)) + memset(smram, 0xcd, size); + + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + total_size += total_stack_size; + /* Stacks are the base of SMRAM */ + params->stack_top = smram + total_stack_size; + + /* MSEG starts at the top of SMRAM and works down */ + if (CONFIG(STM)) { + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + } + + /* FXSAVE goes below MSEG */ + if (CONFIG(SSE)) { + fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; + fxsave_area = base - fxsave_size; + base -= fxsave_size; + total_size += fxsave_size; + } else { + fxsave_size = 0; + fxsave_area = NULL; + } + + handler_size = rmodule_memory_size(&smm_mod); + base -= handler_size; + total_size += handler_size; + module_alignment = rmodule_load_alignment(&smm_mod); + alignment_size = module_alignment - + ((uintptr_t)base % module_alignment); + if (alignment_size != module_alignment) { + handler_size += alignment_size; + base += alignment_size; + } + + printk(BIOS_DEBUG, + "%s: total_smm_space_needed %zx, available -> %zx\n", + __func__, total_size, size); + + /* Does the required amount of memory exceed the SMRAM region size? */ + if (total_size > size) { + printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); + return -1; + } + if (handler_size > SMM_CODE_SEGMENT_SIZE) { + printk(BIOS_ERR, "%s: increase SMM_CODE_SEGMENT_SIZE: handler_size = %zx\n", + __func__, handler_size); + return -1; + } + + if (rmodule_load(base, &smm_mod)) + return -1; + + params->handler = rmodule_entry(&smm_mod); + params->handler_arg = rmodule_parameters(&smm_mod); + + printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", + __func__, smram); + printk(BIOS_DEBUG, "%s: smram_end: %p\n", + __func__, smram + size); + printk(BIOS_DEBUG, "%s: stack_top: %p\n", + __func__, params->stack_top); + printk(BIOS_DEBUG, "%s: handler start %p\n", + __func__, params->handler); + printk(BIOS_DEBUG, "%s: handler_size %zx\n", + __func__, handler_size); + printk(BIOS_DEBUG, "%s: handler_arg %p\n", + __func__, params->handler_arg); + printk(BIOS_DEBUG, "%s: fxsave_area %p\n", + __func__, fxsave_area); + printk(BIOS_DEBUG, "%s: fxsave_size %zx\n", + __func__, fxsave_size); + printk(BIOS_DEBUG, "%s: CONFIG_MSEG_SIZE 0x%x\n", + __func__, CONFIG_MSEG_SIZE); + printk(BIOS_DEBUG, "%s: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x%x\n", + __func__, CONFIG_BIOS_RESOURCE_LIST_SIZE); + + /* CPU 0 smbase goes first, all other CPUs + * will be staggered below + */ + base -= SMM_CODE_SEGMENT_SIZE; + printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", + __func__, base); + params->smm_entry = (uintptr_t)base + params->smm_main_entry_offset; + return smm_module_setup_stub(base, size, params, fxsave_area); +} diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 425724d559..11ea9a71a8 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -10,6 +10,7 @@ */ #include +#include .code32 .section ".module_parameters", "aw", @progbits @@ -148,8 +149,8 @@ smm_trampoline32: pushl $0x0 mov %esp, %ebp - /* Allocate locals (fxsave) */ - subl $0x4, %esp + /* Allocate locals (fxsave, efer_backup) */ + subl $0xc, %esp /* calculate fxsave location */ mov fxsave_area, %edi @@ -177,22 +178,65 @@ smm_trampoline32: /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#ifdef __x86_64__ + mov %ecx, %edi + /* Backup IA32_EFER. Preserves ebx. */ + movl $(IA32_EFER), %ecx + rdmsr + movl %eax, -0x8(%ebp) + movl %edx, -0xc(%ebp) + + /* entry64.inc preserves ebx, esi, edi */ +#include + mov %edi, %ecx + +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ +#ifdef __x86_64__ + push %rbx /* uintptr_t *canary */ + push $(smm_runtime) + push %rcx /* size_t cpu */ + push c_handler_arg /* void *arg */ + + mov %rsp, %rdi /* *arg */ + + movl c_handler, %eax + call *%rax + + /* + * The only reason to go back to protected mode is that RSM doesn't restore + * MSR registers and MSR IA32_EFER was modified by entering long mode. + * Drop to protected mode to safely operate on the IA32_EFER MSR. + */ + + /* Disable long mode. */ + #include + + /* Restore IA32_EFER as RSM doesn't restore MSRs. */ + movl $(IA32_EFER), %ecx + rdmsr + movl -0x8(%ebp), %eax + movl -0xc(%ebp), %edx + + wrmsr + +#else push $0x0 /* Padding */ push $0x0 /* Padding */ push $0x0 /* Padding */ push %ebx /* uintptr_t *canary */ push $(smm_runtime) - push %ecx /* int cpu */ + push %ecx /* size_t cpu */ push c_handler_arg /* void *arg */ push %esp /* smm_module_params *arg (allocated on stack). */ mov c_handler, %eax call *%eax - +#endif /* Retrieve fxsave location. */ mov -4(%ebp), %edi test %edi, %edi diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 340840f685..4cbfbfdfb1 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -46,9 +46,9 @@ #if defined(__x86_64__) .bss ia32efer_backup_eax: -.long +.long 0 ia32efer_backup_edx: -.long +.long 0 #endif /* initially SMM is some sort of real mode. Let gcc know @@ -165,10 +165,6 @@ untampered_lapic: addl $SMM_STACK_SIZE, %ebx movl %ebx, %esp - /* Get SMM revision */ - movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ - subl %ebp, %ebx /* subtract core X offset */ - #if defined(__x86_64__) /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx @@ -179,13 +175,7 @@ untampered_lapic: /* Enable long mode. Preserves ebx. */ #include - mov (%ebx), %rdi - -#else - movl (%ebx), %eax - pushl %eax #endif - /* Call C handler */ call smi_handler diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 893d41dc3b..9607c2c6eb 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include -#include #include #include diff --git a/src/device/Kconfig b/src/device/Kconfig index d0d72f9a77..b69a254b80 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -519,6 +519,19 @@ config PCIEXP_PLUGIN_SUPPORT bool default y +config PCI_ALLOW_BUS_MASTER + bool "Allow PCI bus master bit to be enabled by coreboot" + default y + help + For security reasons, bus mastering should be enabled as late as + possible. In coreboot, it's usually not necessary and payloads + should only enable it for devices they use. Since not all payloads + enable bus mastering properly yet, this option gives some sort of + "backwards compatibility" and is enabled by default to keep the + traditional behaviour for now. This is currently necessary, for + instance, for libpayload based payloads as the drivers don't enable + bus mastering for PCI bridges. + endif # PCI if PCIEXP_PLUGIN_SUPPORT @@ -650,6 +663,9 @@ config SUBSYSTEM_VENDOR_ID This config option will override the devicetree settings for PCI Subsystem Vendor ID. + Note: This option is not meant for a board's Kconfig; use the + devicetree setting `subsystemid` instead. + config SUBSYSTEM_DEVICE_ID hex "Override PCI Subsystem Device ID" depends on PCI @@ -658,6 +674,9 @@ config SUBSYSTEM_DEVICE_ID This config option will override the devicetree settings for PCI Subsystem Device ID. + Note: This option is not meant for a board's Kconfig; use the + devicetree setting `subsystemid` instead. + config VGA_BIOS bool "Add a VGA BIOS image" depends on ARCH_X86 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 1e0cf2f5cb..279f8a1a0a 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -7,10 +7,6 @@ #include #include -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -23,9 +19,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -46,13 +40,13 @@ static int codec_detect(u8 *base) int count; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; - /* clear STATESTS bits (BAR + 0xE)[2:0] */ - reg32 = read32(base + 0x0E); + /* clear STATESTS bits (BAR + 0xe)[2:0] */ + reg32 = read32(base + HDA_STATESTS_REG); reg32 |= 7; - write32(base + 0x0E, reg32); + write32(base + HDA_STATESTS_REG, reg32); /* Wait for readback of register to * match what was just written to it @@ -61,22 +55,22 @@ static int codec_detect(u8 *base) do { /* Wait 1ms based on BKDG wait time */ mdelay(1); - reg32 = read32(base + 0x0E); + reg32 = read32(base + HDA_STATESTS_REG); } while ((reg32 != 0) && --count); /* Timeout occurred */ if (!count) goto no_codec; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -86,7 +80,7 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); return 0; } @@ -112,16 +106,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -134,29 +126,29 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 25; - write32(base + HDA_ICII_REG, - HDA_ICII_VALID | HDA_ICII_BUSY); + /* Send the verb to the codec */ + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); + while (timeout--) { udelay(1); } timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -174,18 +166,21 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; - - reg32 = read32(base + 0x64); + } /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -200,7 +195,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -224,19 +219,18 @@ void azalia_audio_init(struct device *dev) struct resource *res; u32 codec_mask; - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", - codec_mask); + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index cbe0c724fb..b014946144 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -51,23 +51,6 @@ static void cardbus_record_bridge_resource(struct device *dev, resource_t moving resource->size = min_size; } -static void cardbus_size_bridge_resource(struct device *dev, unsigned int index) -{ - struct resource *resource; - resource_t min_size; - - resource = find_resource(dev, index); - if (resource) { - min_size = resource->size; - /* - * Always allocate at least the minimum size to a - * cardbus bridge in case a new card is plugged in. - */ - if (resource->size < min_size) - resource->size = min_size; - } -} - void cardbus_read_resources(struct device *dev) { resource_t moving_base, moving_limit, moving; @@ -88,7 +71,6 @@ void cardbus_read_resources(struct device *dev) /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, PCI_CB_IO_BASE_0, IORESOURCE_IO); - cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); /* See which bridge I/O resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); @@ -118,8 +100,6 @@ void cardbus_read_resources(struct device *dev) type |= IORESOURCE_PREFETCH; cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_0, type); - if (type & IORESOURCE_PREFETCH) - cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); /* See which bridge memory resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); @@ -129,7 +109,6 @@ void cardbus_read_resources(struct device *dev) /* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); - cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); compact_resources(dev); } @@ -140,7 +119,6 @@ void cardbus_enable_resources(struct device *dev) ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link_list->bridge_ctrl & ( - PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); diff --git a/src/device/device_const.c b/src/device/device_const.c index 12d5386d22..2dc583ca27 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -184,7 +184,7 @@ DEVTREE_CONST struct device *find_dev_path( DEVTREE_CONST struct device *child; if (!parent) { - assert(0); + BUG(); /* Return NULL in case asserts are considered non-fatal. */ return NULL; } @@ -196,6 +196,33 @@ DEVTREE_CONST struct device *find_dev_path( return child; } +/** + * Find the device structure given an array of nested device paths, + * + * @param parent The parent bus to start the search on. + * @param nested_path An array of relative paths from the parent bus to the target device. + * @param nested_path_length Number of path elements in nested_path array. + * @return Pointer to a device structure for the device at nested path + * or 0/NULL if no device is found. + */ +DEVTREE_CONST struct device *find_dev_nested_path( + const struct bus *parent, const struct device_path nested_path[], + size_t nested_path_length) +{ + DEVTREE_CONST struct device *child; + + if (!parent || !nested_path || !nested_path_length) + return NULL; + + child = find_dev_path(parent, nested_path); + + /* Terminate recursion at end of nested path or child not found */ + if (nested_path_length == 1 || !child) + return child; + + return find_dev_nested_path(child->link_list, nested_path + 1, nested_path_length - 1); +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -255,7 +282,7 @@ DEVTREE_CONST struct device *pcidev_path_behind_pci2pci_bridge( pci_devfn_t devfn) { if (!bridge || (bridge->path.type != DEVICE_PATH_PCI)) { - assert(0); + BUG(); /* Return NULL in case asserts are non-fatal. */ return NULL; } diff --git a/src/device/device_util.c b/src/device/device_util.c index 22c3db1c44..452a87bf14 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -519,7 +519,7 @@ void report_resource_stored(struct device *dev, struct resource *resource, end = resource_end(resource); buf[0] = '\0'; - if (resource->flags & IORESOURCE_PCI_BRIDGE) { + if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), "bus %02x ", dev->link_list->secondary); } diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index f397a534f2..f7118dbbc2 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,3 @@ romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c + +ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index c6d6442da8..0eba0e384c 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -653,7 +653,7 @@ static void print_us(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 3c433a931e..ab6d828b1d 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -493,7 +493,6 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, return ret; } - /** * Fill cbmem with information for SMBIOS type 17. * @@ -593,7 +592,7 @@ static void print_ns(const char *msg, u32 val) /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is * selected, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 429a9d271a..e670b20f72 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -9,6 +9,69 @@ #include #include +enum ddr4_speed_grade { + DDR4_1600, + DDR4_1866, + DDR4_2133, + DDR4_2400, + DDR4_2666, + DDR4_2933, + DDR4_3200 +}; + +struct ddr4_speed_attr { + uint32_t min_clock_mhz; // inclusive + uint32_t max_clock_mhz; // inclusive + uint32_t reported_mts; +}; + +/** + * DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170 + * + * min_clock_mhz = 1000/max_tCk_avg(ns) + 1 + * Adding 1 to make minimum inclusive + * max_clock_mhz = 1000/min_tCk_avg(ns) + * reported_mts = Standard reported DDR4 speed in MT/s + * May be 1 less than the actual max MT/s + */ +static const struct ddr4_speed_attr ddr4_speeds[] = { + [DDR4_1600] = { + .min_clock_mhz = 668, + .max_clock_mhz = 800, + .reported_mts = 1600 + }, + [DDR4_1866] = { + .min_clock_mhz = 801, + .max_clock_mhz = 934, + .reported_mts = 1866 + }, + [DDR4_2133] = { + .min_clock_mhz = 935, + .max_clock_mhz = 1067, + .reported_mts = 2133 + }, + [DDR4_2400] = { + .min_clock_mhz = 1068, + .max_clock_mhz = 1200, + .reported_mts = 2400 + }, + [DDR4_2666] = { + .min_clock_mhz = 1201, + .max_clock_mhz = 1333, + .reported_mts = 2666 + }, + [DDR4_2933] = { + .min_clock_mhz = 1334, + .max_clock_mhz = 1466, + .reported_mts = 2933 + }, + [DDR4_3200] = { + .min_clock_mhz = 1467, + .max_clock_mhz = 1600, + .reported_mts = 3200 + } +}; + typedef enum { BLOCK_0, /* Base Configuration and DRAM Parameters */ BLOCK_1, @@ -68,6 +131,21 @@ static bool block_exists(spd_block_type type, u8 dimm_type) } } +/** + * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) +{ + for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) { + const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed]; + if (speed_mhz >= speed_attr->min_clock_mhz && + speed_mhz <= speed_attr->max_clock_mhz) { + return speed_attr->reported_mts; + } + } + printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range", speed_mhz); + return 0; +} /** * \brief Decode the raw SPD data diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index a9f922fdf3..068c489b05 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -308,7 +308,6 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int m } } while ((ctrl & (1 << 5)) == 0); - /* Get and setup the device_structure. */ dev = ht_scan_get_devs(&old_devices); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5215934ed5..d230d5cbea 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -130,7 +130,7 @@ static void setup_interrupt_handlers(void) { /* If the mainboard_interrupt_handler isn't called first. */ - if(!intXX_handler[i]) + if (!intXX_handler[i]) { /* Now set the default functions that are actually * needed to initialize the option roms. This is diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index 9e216e9df6..ab55198d23 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -170,7 +170,7 @@ void x86emu_decode_printf (const char *x) void x86emu_decode_printf2 (const char *x, int y) { char temp[100]; - snprintf(temp, sizeof (temp), x,y); + snprintf(temp, sizeof(temp), x,y); strcpy(M.x86.decoded_buf+M.x86.enc_str_pos,temp); M.x86.enc_str_pos += strlen(temp); } diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index 3b7bde727a..06d7f314fe 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -1122,7 +1122,6 @@ unsigned int decode_rm10_address( return 0; /* SHOULD NOT HAPPEN */ } - /**************************************************************************** PARAMETERS: mod - modifier diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index 3c4a8caf5b..d794ecb46c 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -129,7 +129,6 @@ static u32 x86emu_parity_tab[8] = /*----------------------------- Implementation ----------------------------*/ - /*--------- Side effects helper functions -------*/ /**************************************************************************** diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 06f240c5a7..538660894f 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -199,8 +199,6 @@ void X86API wrl(u32 addr, u32 val) DB(if (DEBUG_MEM_TRACE()) printf("%#08x 4 <- %#x\n", addr, val);) - - } /**************************************************************************** diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h index ce910f7e69..8cec44fe97 100644 --- a/src/device/oprom/yabel/compat/of.h +++ b/src/device/oprom/yabel/compat/of.h @@ -31,7 +31,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #ifndef OF_H #define OF_H #define p32 int @@ -48,7 +47,6 @@ typedef struct unsigned int args[16]; } of_arg_t; - phandle_t of_finddevice (const char *); phandle_t of_peer(phandle_t); phandle_t of_child(phandle_t); @@ -56,7 +54,6 @@ phandle_t of_parent(phandle_t); int of_getprop(phandle_t, const char *, void *, int); void *of_call_method_3(const char *, ihandle_t, int); - ihandle_t of_open(const char *); void of_close(ihandle_t); int of_read(ihandle_t, void *, int); diff --git a/src/device/oprom/yabel/compat/rtas.h b/src/device/oprom/yabel/compat/rtas.h index ccad9e958b..021f51e723 100644 --- a/src/device/oprom/yabel/compat/rtas.h +++ b/src/device/oprom/yabel/compat/rtas.h @@ -31,7 +31,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #ifndef RTAS_H #define RTAS_H diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 4a50068faf..2c98578c7d 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -32,7 +32,6 @@ * IBM Corporation - initial implementation *****************************************************************************/ - #include "device.h" #include "compat/rtas.h" #include @@ -150,7 +149,6 @@ biosemu_dev_get_addr_info(void) void translate_address_dev(u64 *, phandle_t); u64 get_puid(phandle_t node); - // scan all addresses assigned to the device ("assigned-addresses" and "reg") // store in translate_address_array for faster translation using dev_translate_address void diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 0fe9e00abe..37440a8051 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -40,7 +40,6 @@ #include "compat/of.h" #include "debug.h" - // a Expansion Header Struct as defined in Plug and Play BIOS Spec 1.0a Chapter 3.2 typedef struct { char signature[4]; // signature diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 338156f8ed..968e471992 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -48,7 +48,6 @@ #include #include - //setup to run the code at the address, that the Interrupt Vector points to... static void setupInt(int intNum) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 3623c3b564..ce3e50967a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -25,7 +25,6 @@ #include #include - u8 pci_moving_config8(struct device *dev, unsigned int reg) { u8 value, ones, zeroes; @@ -1644,3 +1643,21 @@ void pci_dev_disable_bus_master(const struct device *dev) pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0); } #endif + +bool pci_dev_is_wake_source(const struct device *dev) +{ + unsigned int pm_cap; + uint16_t pmcs; + + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (!pm_cap) + return false; + + pmcs = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); + + /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ + return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); +} diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index bb616d91f1..4224c651f3 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -264,8 +264,8 @@ void pci_rom_ssdt(const struct device *device) { static size_t ngfx; - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) return; /* Only handle enabled devices */ diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index cd7adf32bc..afe6948a3a 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -56,7 +56,7 @@ void pnp_set_enable(struct device *dev, int enable) { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; @@ -66,14 +66,14 @@ void pnp_set_enable(struct device *dev, int enable) else tmp &= ~(1 << bitpos); - pnp_write_config(dev, 0x30, tmp); + pnp_write_config(dev, PNP_IDX_EN, tmp); } int pnp_read_enable(struct device *dev) { u8 tmp, bitpos; - tmp = pnp_read_config(dev, 0x30); + tmp = pnp_read_config(dev, PNP_IDX_EN); /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 4ef3f40208..df9876a84a 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c index 8aa1c93120..c1fac0dadb 100644 --- a/src/drivers/amd/agesa/heapmanager.c +++ b/src/drivers/amd/agesa/heapmanager.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 6ae7d999d6..606a66f5cb 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c index a93826551d..b5be31d038 100644 --- a/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c +++ b/src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c @@ -21,6 +21,11 @@ static void i2s_machine_dev_fill_ssdt(const struct device *dev) dmic_select_gpio = &cfg->dmic_select_gpio; + if (scope == NULL) { + printk(BIOS_ERR, "%s: ERROR: ACPI I2S scope not found\n", dev_path(dev)); + return; + } + if (cfg->hid == NULL) { printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); return; diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index ee98fd4df9..9f0b2e1f2c 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -737,7 +737,6 @@ static int anx7625_power_on_init(uint8_t bus) } ANXINFO("Init interface.\n"); - anx7625_disable_pd_protocol(bus); anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version); anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision); diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 460b85801e..924ca57d9d 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -331,7 +331,6 @@ static bool ast_init_dvo(struct drm_device *dev) return true; } - static void ast_init_analog(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; diff --git a/src/drivers/aspeed/common/ast_drv.h b/src/drivers/aspeed/common/ast_drv.h index e275108602..423ba37c28 100644 --- a/src/drivers/aspeed/common/ast_drv.h +++ b/src/drivers/aspeed/common/ast_drv.h @@ -11,7 +11,6 @@ #define PCI_CHIP_AST2100 0x2010 #define PCI_CHIP_AST1180 0x1180 - enum ast_chip { AST2000, AST2100, @@ -64,6 +63,11 @@ struct ast_private { int next_cursor; bool support_wide_screen; + enum { + ast_use_p2a, + ast_use_dt, + ast_use_defaults + } config_mode; enum ast_tx_chip tx_chip_type; u8 dp501_maxclk; diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 5143e6d0eb..89194ad0be 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -4,6 +4,7 @@ */ #include +#include #include "ast_drv.h" #include "ast_dram_tables.h" @@ -36,17 +37,79 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast, return ret; } +static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) +{ + struct ast_private *ast = dev->dev_private; + uint32_t data, jregd0, jregd1; + + /* Defaults */ + ast->config_mode = ast_use_defaults; + *scu_rev = 0xffffffff; + + /* Not all families have a P2A bridge */ + if (dev->pdev->device != PCI_CHIP_AST2000) + return; + + /* + * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge + * is disabled. We force using P2A if VGA only mode bit + * is set D[7] + */ + jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); + jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); + if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Double check it's actually working */ + data = ast_read32(ast, 0xf004); + if (data != 0xFFFFFFFF) { + /* P2A works, grab silicon revision */ + ast->config_mode = ast_use_p2a; + + DRM_INFO("Using P2A bridge for configuration\n"); + + /* Read SCU7c (silicon revision register) */ + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + *scu_rev = ast_read32(ast, 0x1207c); + return; + } + } + + /* We have a P2A bridge but it's disabled */ + DRM_INFO("P2A bridge disabled, using default configuration\n"); +} static int ast_detect_chip(struct drm_device *dev, bool *need_post) { struct ast_private *ast = dev->dev_private; - uint32_t data, jreg; + uint32_t jreg, scu_rev; + + /* + * If VGA isn't enabled, we need to enable now or subsequent + * access to the scratch registers will fail. We also inform + * our caller that it needs to POST the chip + * (Assumption: VGA not enabled -> need to POST) + */ + if (!ast_is_vga_enabled(dev)) { + ast_enable_vga(dev); + DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); + *need_post = true; + } else + *need_post = false; + + + /* Enable extended register access */ + ast_enable_mmio(dev); ast_open_key(ast); + /* Find out whether P2A works or whether to use device-tree */ + ast_detect_config_mode(dev, &scu_rev); + + /* Identify chipset */ if (dev->pdev->device == PCI_CHIP_AST1180) { ast->chip = AST1100; DRM_INFO("AST 1180 detected\n"); } else { + uint32_t data; pci_read_config_dword(ast->dev->pdev, 0x08, &data); uint8_t revision = data & 0xff; if (revision >= 0x40) { @@ -59,11 +122,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->chip = AST2300; DRM_INFO("AST 2300 detected\n"); } else if (revision >= 0x10) { - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - - data = ast_read32(ast, 0x1207c); - switch (data & 0x0300) { + switch (scu_rev & 0x0300) { case 0x0200: ast->chip = AST1100; DRM_INFO("AST 1100 detected\n"); @@ -88,20 +147,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) } } - /* - * If VGA isn't enabled, we need to enable now or subsequent - * access to the scratch registers will fail. We also inform - * our caller that it needs to POST the chip - * (Assumption: VGA not enabled -> need to POST) - */ - if (!ast_is_vga_enabled(dev)) { - ast_enable_vga(dev); - ast_enable_mmio(dev); - DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); - *need_post = true; - } else - *need_post = false; - /* Check if we support wide screen */ switch (ast->chip) { case AST1180: @@ -118,16 +163,14 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->support_wide_screen = true; else { ast->support_wide_screen = false; - /* Read SCU7c (silicon revision register) */ - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - data = ast_read32(ast, 0x1207c); - data &= 0x300; - if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ + if (ast->chip == AST2300 && + (scu_rev & 0x300) == 0x0) /* ast1300 */ ast->support_wide_screen = true; - if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ + if (ast->chip == AST2400 && + (scu_rev & 0x300) == 0x100) /* ast1400 */ ast->support_wide_screen = true; - if (ast->chip == AST2500 && data == 0x100) /* ast2510 */ + if (ast->chip == AST2500 && + scu_rev == 0x100) /* ast2510 */ ast->support_wide_screen = true; } break; @@ -193,34 +236,44 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) static int ast_get_dram_info(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; - uint8_t i; - uint32_t data, data2; - uint32_t denum, num, div, ref_pll; + uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; + uint32_t denum, num, div, ref_pll, dsel; - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - - - ast_write32(ast, 0x10000, 0xfc600309); - - /* Wait up to 2.5 seconds for device initialization / register unlock */ - for (i = 0; i < 250; i++) { - if (ast_read32(ast, 0x10000) == 0x01) - break; - mdelay(10); + switch (ast->config_mode) { + case ast_use_dt: + /* + * If some properties are missing, use reasonable + * defaults for AST2400 + */ + mcr_cfg = 0x00000577; + mcr_scu_mpll = 0x000050C0; + mcr_scu_strap = 0; + break; + case ast_use_p2a: + ast_write32(ast, 0xf004, 0x1e6e0000); + ast_write32(ast, 0xf000, 0x1); + mcr_cfg = ast_read32(ast, 0x10004); + mcr_scu_mpll = ast_read32(ast, 0x10120); + mcr_scu_strap = ast_read32(ast, 0x10170); + break; + case ast_use_defaults: + default: + ast->dram_bus_width = 16; + ast->dram_type = AST_DRAM_1Gx16; + if (ast->chip == AST2500) + ast->mclk = 800; + else + ast->mclk = 396; + return 0; } - if (ast_read32(ast, 0x10000) != 0x01) - dev_err(dev->pdev, "Unable to unlock SDRAM control registers\n"); - data = ast_read32(ast, 0x10004); - - if (data & 0x40) + if (mcr_cfg & 0x40) ast->dram_bus_width = 16; else ast->dram_bus_width = 32; if (ast->chip == AST2500) { - switch (data & 0x03) { + switch (mcr_cfg & 0x03) { case 0: ast->dram_type = AST_DRAM_1Gx16; break; @@ -236,7 +289,7 @@ static int ast_get_dram_info(struct drm_device *dev) break; } } else if (ast->chip == AST2300 || ast->chip == AST2400) { - switch (data & 0x03) { + switch (mcr_cfg & 0x03) { case 0: ast->dram_type = AST_DRAM_512Mx16; break; @@ -252,13 +305,13 @@ static int ast_get_dram_info(struct drm_device *dev) break; } } else { - switch (data & 0x0c) { + switch (mcr_cfg & 0x0c) { case 0: case 4: ast->dram_type = AST_DRAM_512Mx16; break; case 8: - if (data & 0x40) + if (mcr_cfg & 0x40) ast->dram_type = AST_DRAM_1Gx16; else ast->dram_type = AST_DRAM_512Mx32; @@ -269,17 +322,15 @@ static int ast_get_dram_info(struct drm_device *dev) } } - data = ast_read32(ast, 0x10120); - data2 = ast_read32(ast, 0x10170); - if (data2 & 0x2000) + if (mcr_scu_strap & 0x2000) ref_pll = 14318; else ref_pll = 12000; - denum = data & 0x1f; - num = (data & 0x3fe0) >> 5; - data = (data & 0xc000) >> 14; - switch (data) { + denum = mcr_scu_mpll & 0x1f; + num = (mcr_scu_mpll & 0x3fe0) >> 5; + dsel = (mcr_scu_mpll & 0xc000) >> 14; + switch (dsel) { case 3: div = 0x4; break; @@ -311,6 +362,19 @@ static u32 ast_get_vram_info(struct drm_device *dev) case 3: vram_size = AST_VIDMEM_SIZE_64M; break; } + jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); + switch (jreg & 0x03) { + case 1: + vram_size -= 0x100000; + break; + case 2: + vram_size -= 0x200000; + break; + case 3: + vram_size -= 0x400000; + break; + } + return vram_size; } @@ -329,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, 0x14); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -343,7 +407,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, 0x18); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); if (!res) { dev_err(dev->pdev, "BAR2 resource not found.\n"); ret = -EIO; @@ -374,15 +438,19 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast_detect_chip(dev, &need_post); - if (ast->chip != AST1180) { - ast_get_dram_info(dev); - ast->vram_size = ast_get_vram_info(dev); - DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); - } - if (need_post) ast_post_gpu(dev); + if (ast->chip != AST1180) { + ret = ast_get_dram_info(dev); + if (ret) + goto out_free; + ast->vram_size = ast_get_vram_info(dev); + DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", + ast->mclk, ast->dram_type, + ast->dram_bus_width, ast->vram_size); + } + return 0; out_free: kfree(ast); diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c index 465d8866a9..e5832e772e 100644 --- a/src/drivers/aspeed/common/ast_mode.c +++ b/src/drivers/aspeed/common/ast_mode.c @@ -6,7 +6,6 @@ #include "ast_drv.h" #include "ast_tables.h" - static inline void ast_load_palette_index(struct ast_private *ast, u8 index, u8 red, u8 green, u8 blue) diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2a033a028b..b5f794bcb6 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -3,6 +3,7 @@ * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ #include +#include #include "ast_drv.h" @@ -18,7 +19,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) struct drm_framebuffer *fb = crtc->primary->fb; /* PCI BAR 0 */ - struct resource *res = find_resource(crtc->dev->pdev, 0x10); + struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_ERR, "BAR0 resource not found.\n"); return -EIO; @@ -95,7 +96,11 @@ static int ast_select_mode(struct drm_connector *connector, ast_software_i2c_read(ast, raw); if (decode_edid(raw, sizeof(raw), edid) != EDID_CONFORMANT) { - dev_err(dev->pdev, "Failed to decode EDID\n"); + /* + * Servers often run headless, so a missing EDID is not an error. + * We still need to initialize a framebuffer for KVM, though. + */ + dev_info(dev->pdev, "Failed to decode EDID\n"); printk(BIOS_DEBUG, "Assuming VGA for KVM\n"); memset(edid, 0, sizeof(*edid)); diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index b3b7d6196c..b6e8e91d23 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -25,7 +25,6 @@ void ast_enable_mmio(struct drm_device *dev) ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); } - bool ast_is_vga_enabled(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; @@ -208,7 +207,6 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw) return 1; } - static void cbrdlli_ast2150(struct ast_private *ast, int busw) { u32 dll_min[4], dll_max[4], dlli, data, passcnt; @@ -239,8 +237,6 @@ cbr_start: ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); } - - static void ast_init_dram_reg(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; @@ -370,14 +366,20 @@ void ast_post_gpu(struct drm_device *dev) ast_enable_mmio(dev); ast_set_def_ext_reg(dev); - if (ast->chip == AST2500) - ast_post_chip_2500(dev); - else if (ast->chip == AST2300 || ast->chip == AST2400) - ast_post_chip_2300(dev); - else - ast_init_dram_reg(dev); + if (ast->config_mode == ast_use_p2a) { + if (ast->chip == AST2500) + ast_post_chip_2500(dev); + else if (ast->chip == AST2300 || ast->chip == AST2400) + ast_post_chip_2300(dev); + else + ast_init_dram_reg(dev); - ast_init_3rdtx(dev); + ast_init_3rdtx(dev); + } else { + if (ast->tx_chip_type != AST_TX_NONE) + /* Enable DVO */ + ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); + } } /* AST 2300 DRAM settings */ @@ -473,7 +475,6 @@ static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) return data; } - static bool mmc_test_burst(struct ast_private *ast, u32 datagen) { return mmc_test(ast, datagen, 0xc1); @@ -1225,7 +1226,6 @@ ddr3_init_start: ast_moutdwm(ast, 0x1E6E0050, 0x00000000); #endif - } static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) @@ -1240,7 +1240,6 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa trap_AC2 += 0x00110000; trap_MRS = 0x00000040 | (trap << 4); - param->reg_MADJ = 0x00034C4C; param->reg_SADJ = 0x00001800; param->reg_DRV = 0x000000F0; diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index fb13da803f..bfd8f52ce0 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -220,7 +220,6 @@ static const struct ast_vbios_enhtable res_800x600[] = { (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, }; - static const struct ast_vbios_enhtable res_1024x768[] = { {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ (SyncNN | Charx8Dot), 60, 1, 0x31 }, @@ -280,7 +279,6 @@ static const struct ast_vbios_enhtable res_1920x1080[] = { AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; - /* 16:10 */ static const struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index 9d12690def..800d1457f4 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -30,7 +30,6 @@ static const char *tis_get_dev_name(struct tpm2_info *info) return "Unknown"; } - int tis_open(void) { if (tpm_is_open) { @@ -79,7 +78,6 @@ int tis_init(void) return 0; } - int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 6436725d69..476b62b657 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -14,7 +14,6 @@ #include #include -#include #include #include #include @@ -122,7 +121,6 @@ static uint8_t crb_activate_locality(void) if (rc) write8(CRB_REG(locality, CRB_REG_LOC_CTRL), LOC_CTRL_REQ_ACCESS); - rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, LOC_STATE_LOC_ASSIGN, LOC_STATE_LOC_ASSIGN); if (rc) { @@ -138,7 +136,6 @@ static uint8_t crb_activate_locality(void) return 0; } - return locality; } @@ -177,7 +174,6 @@ static int crb_switch_to_ready(void) int tpm2_init(void) { - if (crb_probe()) { printk(BIOS_ERR, "TPM: Probe failed.\n"); return -1; diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index 449d02fb6b..0d683848ae 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -39,7 +39,6 @@ #define CRB_INTF_REG_INTF_SEL (1<<17) #define CRB_INTF_REG_INTF_LOCK (1<<19) - /*REQUEST Register related */ #define CRB_REG_REQUEST_CMD_RDY 0x01 #define CRB_REG_REQUEST_GO_IDLE 0x02 @@ -58,7 +57,6 @@ struct tpm2_info { uint16_t revision; }; - int tpm2_init(void); void tpm2_get_info(struct tpm2_info *tpm2_info); size_t tpm2_process_command(const void *tpm2_command, size_t command_size, diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index bc25d1cebb..19b33318c4 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -23,12 +23,6 @@ config ELOG_CBMEM but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log. -config ELOG_PRERAM - bool - default n - help - This option will enable event logging from the preram stage. - config ELOG_GSMI depends on HAVE_SMI_HANDLER bool "SMI interface to write and clear event log" diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d6d7..370eef44d1 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ -bootblock-$(CONFIG_ELOG_PRERAM) += elog.c -verstage-$(CONFIG_ELOG_PRERAM) += elog.c -romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +bootblock-$(CONFIG_ELOG) += elog.c +verstage-$(CONFIG_ELOG) += elog.c +romstage-$(CONFIG_ELOG) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 01fa9cce65..818355b5b9 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -17,7 +17,6 @@ #include #include "elog_internal.h" - #if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) #else diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c8d373a46e..d63f490603 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -299,7 +299,6 @@ static void cirrus_init_linear_fb(struct device *dev) vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - struct edid edid; edid.mode.ha = width; edid.mode.va = height; diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 2e3e37d1ac..9f8aaa80f9 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -5,7 +5,6 @@ #include #include - #define MAX_SERIAL_LENGTH 0x100 const char *smbios_mainboard_serial_number(void) diff --git a/src/drivers/genesyslogic/gl9755/Kconfig b/src/drivers/genesyslogic/gl9755/Kconfig new file mode 100644 index 0000000000..5bccb9b490 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/Kconfig @@ -0,0 +1,7 @@ +config DRIVERS_GENESYSLOGIC_GL9755 + bool "Genesys Logic GL9755" + help + GL9755 is a PCI Express Rev. 2.1 compliant card reader controller + which integrates PCI Express PHY, UHS-II PHY, memory card access + interface, regulators (3.3V-to-1.8V and 3.3V-to-1.2V) and card + power switch. diff --git a/src/drivers/genesyslogic/gl9755/Makefile.inc b/src/drivers/genesyslogic/gl9755/Makefile.inc new file mode 100644 index 0000000000..995cfd30f6 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9755) += gl9755.c diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c new file mode 100644 index 0000000000..c3cdef11e7 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9755 */ + +#include +#include +#include +#include +#include +#include +#include "gl9755.h" + +static void gl9755_init(struct device *dev) +{ + printk(BIOS_INFO, "GL9755: init\n"); + pci_dev_init(dev); + + /* Set Vendor Config to be configurable */ + pci_or_config32(dev, CFG, CFG_EN); + /* Set LTR value */ + pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); + /* Set Vendor Config to be non-configurable */ + pci_and_config32(dev, CFG, ~CFG_EN); +} + +static struct device_operations gl9755_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = gl9755_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9755, + 0 +}; + +static const struct pci_driver genesyslogic_gl9755 __pci_driver = { + .ops = &gl9755_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_gl9755_ops = { + CHIP_NAME("Genesys Logic GL9755") +}; diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h new file mode 100644 index 0000000000..2d20faf695 --- /dev/null +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Definitions for Genesys Logic GL9755 */ + +#define CFG 0x800 +#define CFG_EN 0x1 +#define LTR 0x5C +#define SNOOP_VALUE 0x25 +#define SNOOP_SCALE (0x3 << 10) +#define NO_SNOOP_VALUE (0x25 << 16) +#define NO_SNOOP_SCALE (0x3 << 26) diff --git a/src/drivers/genesyslogic/gl9763e/Kconfig b/src/drivers/genesyslogic/gl9763e/Kconfig new file mode 100644 index 0000000000..c254707f66 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENESYSLOGIC_GL9763E + bool diff --git a/src/drivers/genesyslogic/gl9763e/Makefile.inc b/src/drivers/genesyslogic/gl9763e/Makefile.inc new file mode 100644 index 0000000000..61a63e6231 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9763E) += gl9763e.c diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c new file mode 100644 index 0000000000..48e520bde2 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9763E */ + +#include +#include +#include +#include +#include +#include +#include "gl9763e.h" + +static void gl9763e_init(struct device *dev) +{ + printk(BIOS_INFO, "GL9763E: init\n"); + pci_dev_init(dev); + + /* Set VHS (Vendor Header Space) to be writable */ + pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_W); + /* Set single AXI request */ + pci_or_config32(dev, SCR, SCR_AXI_REQ); + /* Disable L0s support */ + pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S); + /* Set SSC to 30000 ppm */ + pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); + /* Enable SSC */ + pci_or_config32(dev, PLL_CTL, PLL_CTL_SSC); + /* Set VHS to read-only */ + pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R); +} + +static struct device_operations gl9763e_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .init = gl9763e_init, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9763E, + 0 +}; + +static const struct pci_driver genesyslogic_gl9763e __pci_driver = { + .ops = &gl9763e_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_ops = { + CHIP_NAME("Genesys Logic GL9763E") +}; diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h new file mode 100644 index 0000000000..fd9c6ba5c2 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Definitions for Genesys Logic GL9763E */ + +#include + +#define VHS 0x884 +#define VHS_REV_MASK (0xF << 16) +#define VHS_REV_R (0x0 << 16) +#define VHS_REV_M (0x1 << 16) +#define VHS_REV_W (0x2 << 16) +#define SCR 0x8E0 +#define SCR_AXI_REQ BIT(9) + +#define CFG_REG_2 0x8A4 +#define CFG_REG_2_L0S BIT(11) + +#define PLL_CTL 0x938 +#define PLL_CTL_SSC BIT(19) + +#define PLL_CTL_2 0x93C +#define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16) +#define MAX_SSC_30000PPM (0xF5C3 << 16) diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index afadc6fd53..bc01969b5a 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -45,7 +45,7 @@ static void at24rf08c_read_string_dev(struct device *dev, u8 start, int t = at24rf08c_read_byte(dev, start + i); if (t < 0x20 || t > 0x7f) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } result[i] = t; @@ -60,7 +60,7 @@ static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) dev = at24rf08c_find_bank(bank); if (dev == NULL) { printk(BIOS_WARNING, "EEPROM not found\n"); - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return; } @@ -75,7 +75,7 @@ const char *smbios_mainboard_serial_number(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x2e, 7, result); already_read = 1; @@ -90,7 +90,7 @@ const char *lenovo_mainboard_partnumber(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x27, 7, result); already_read = 1; @@ -113,13 +113,12 @@ void smbios_system_set_uuid(u8 *uuid) 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 }; - if (already_read) { memcpy(uuid, result, 16); return; } - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); dev = dev_find_slot_on_smbus(1, 0x56); if (dev == NULL) { @@ -141,7 +140,7 @@ void smbios_system_set_uuid(u8 *uuid) break; } if (t < 0) { - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); break; } result[remap[i]] = t; @@ -162,17 +161,17 @@ const char *smbios_mainboard_version(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); dev = at24rf08c_find_bank(2); if (dev == NULL) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } len = at24rf08c_read_byte(dev, 0x26) - 2; if (len < 0 || len > sizeof(result) - 1) { - memcpy(result, ERROR_STRING, sizeof (ERROR_STRING)); + memcpy(result, ERROR_STRING, sizeof(ERROR_STRING)); return result; } diff --git a/src/drivers/i2c/ck505/ck505.c b/src/drivers/i2c/ck505/ck505.c index e83d3e35ed..58eaec657a 100644 --- a/src/drivers/i2c/ck505/ck505.c +++ b/src/drivers/i2c/ck505/ck505.c @@ -31,7 +31,6 @@ static void ck505_init(struct device *dev) nregs = MIN(MIN(dev_nregs, config->nregs == 0 ? SMBUS_BLOCK_SIZE : config->nregs), ARRAY_SIZE(config->mask)); - printk(BIOS_DEBUG, "Changing %d of the %d ck505 config bytes.\n", nregs, dev_nregs); diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 00865e3f6e..e01b5a8446 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -698,7 +698,6 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, return 0; } - /* * Initialize this bus controller and set the speed. * diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index 0557f421ca..1f8a4f3b29 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -25,7 +25,7 @@ static void max98373_fill_ssdt(const struct device *dev) struct acpi_dp *dp; if (!dev->enabled || !scope) { - printk(BIOS_ERR, "%s: dev not enabled", __func__); + printk(BIOS_ERR, "%s: dev not enabled\n", __func__); return; } diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 925dca1eae..03c464af82 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -7,6 +7,15 @@ #define NCT7802Y_PECI_CNT 2 #define NCT7802Y_FAN_CNT 3 +#define NCT7802Y_RTD_CNT 3 + +/* Remote temperature diode sensors mode */ +enum nct7802y_rtd_mode { + RTD_CLOSED = 0, + RTD_CURRENT_MODE, + RTD_THERMISTOR_MODE, + RTD_VOLTAGE_MODE, +}; enum nct7802y_peci_mode { PECI_DISABLED = 0, @@ -53,6 +62,11 @@ enum nct7802y_temp_source { TEMP_SOURCE_PROGRAMMABLE_1, }; +struct nct7802y_sensors_config { + bool local_enable; + enum nct7802y_rtd_mode rtd[NCT7802Y_RTD_CNT]; +}; + struct nct7802y_fan_smartconfig { enum nct7802y_fan_smartmode mode; enum nct7802y_fan_speed speed; @@ -76,6 +90,7 @@ struct nct7802y_fan_config { struct drivers_i2c_nct7802y_config { struct nct7802y_peci_config peci[NCT7802Y_PECI_CNT]; struct nct7802y_fan_config fan[NCT7802Y_FAN_CNT]; + struct nct7802y_sensors_config sensors; enum nct7802y_fan_pecierror on_pecierror; u8 pecierror_minduty; }; diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h index aa07e7082e..d9b5878c67 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.h +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -11,6 +11,9 @@ #define BANK_SELECT 0x00 /* Bank 0 */ +#define MODE_SELECTION 0x22 +#define MODE_SELECTION_LTD_EN (1 << 6) +#define MODE_SELECTION_RTDx(x, val) ((val) << (x) * 2) #define PECI_ENABLE 0x23 #define PECI_ENABLE_AGENTx(x) (1 << (x)) diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index 7771b78808..a608802c7b 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -68,7 +68,7 @@ void nct7802y_init_fan(struct device *const dev) { const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; unsigned int i; - u8 set; + u8 value; if (nct7802y_select_bank(dev, 0) != CB_SUCCESS) return; @@ -78,21 +78,27 @@ void nct7802y_init_fan(struct device *const dev) init_fan(dev, &config->fan[i], i); } + value = 0; + for (i = 0; i < NCT7802Y_RTD_CNT; ++i) + value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]); + if (config->sensors.local_enable) + value |= MODE_SELECTION_LTD_EN; + nct7802y_write(dev, MODE_SELECTION, value); + switch (config->on_pecierror) { case PECI_ERROR_KEEP: - set = CLOSE_LOOP_FAN_PECI_ERR_CURR; + value = CLOSE_LOOP_FAN_PECI_ERR_CURR; break; case PECI_ERROR_VALUE: - set = CLOSE_LOOP_FAN_PECI_ERR_VALUE; + value = CLOSE_LOOP_FAN_PECI_ERR_VALUE; break; case PECI_ERROR_FULLSPEED: - set = CLOSE_LOOP_FAN_PECI_ERR_MAX; + value = CLOSE_LOOP_FAN_PECI_ERR_MAX; break; default: - set = 0; + value = 0; break; } - nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, - CLOSE_LOOP_FAN_PECI_ERR_MASK, set); + nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, CLOSE_LOOP_FAN_PECI_ERR_MASK, value); nct7802y_write(dev, FAN_DUTY_ON_PECI_ERROR, config->pecierror_minduty); } diff --git a/src/drivers/i2c/pca9538/chip.h b/src/drivers/i2c/pca9538/chip.h index bde08a6f5c..96fd02f905 100644 --- a/src/drivers/i2c/pca9538/chip.h +++ b/src/drivers/i2c/pca9538/chip.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - struct drivers_i2c_pca9538_config { unsigned char in_out; /* Use bit as input(1) or output (0). */ unsigned char invert; /* If a bit is 1, the input will be inverted. */ diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 3bdcba6eed..98a343228e 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h index e5dee97159..84a73dcc83 100644 --- a/src/drivers/i2c/rt1011/chip.h +++ b/src/drivers/i2c/rt1011/chip.h @@ -4,7 +4,6 @@ * Realtek RT1011 audio codec devicetree bindings */ - struct drivers_i2c_rt1011_config { const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 78ac224eda..4ff3705ad9 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -15,7 +15,6 @@ * Version: 2.1.1 */ - #include #include #include diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c index 6068693675..19aa6dae6f 100644 --- a/src/drivers/i2c/ww_ring/ww_ring.c +++ b/src/drivers/i2c/ww_ring/ww_ring.c @@ -365,7 +365,6 @@ int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern) return -1; } - #define LP55231_I2C_BASE_ADDR 0x32 static void ww_ring_init(unsigned int i2c_bus) diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index 880b32ad9c..c3af32036c 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -1,5 +1,5 @@ config DRIVERS_INTEL_DPTF - bool "Support runtime generation of Intel DPTF ACPI tables" + bool depends on HAVE_ACPI_TABLES default n help @@ -7,10 +7,11 @@ config DRIVERS_INTEL_DPTF Intel DPTF Tables at runtime in the SSDT. config DPTF_USE_EISA_HID - bool "If selected, use 'old' 7 character EISA IDs for DPTF _HID" + bool depends on DRIVERS_INTEL_DPTF default n help - When selected, all DPTF devices will use the "old" style of - _HIDs, which are 7-character EISA IDs. Otherwise, it will use - the "new" style, which are regular 8-character _HIDs. + Prior to Tiger Lake, all DPTF devices used 7-character EISA + IDs. If selected, the 7-character _HIDs will be emitted, + otherwise, it will use the "new" style, which are regular + 8-character _HIDs. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index a13f6d0443..0f1cc9c400 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -209,9 +209,11 @@ static void write_options(const struct drivers_intel_dptf_config *config) int i; /* Fan options */ + dptf_write_scope(DPTF_FAN); dptf_write_fan_options(config->options.fan.fine_grained_control, config->options.fan.step_size, config->options.fan.low_speed_notify); + acpigen_pop_len(); /* Scope */ /* TSR options */ for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 9e7865d968..570648c373 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -174,7 +174,6 @@ struct fsp_runtime { uint32_t hob_list; } __packed; - void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list) { struct fsp_runtime *fspr; diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 23f92899e8..41ffedde1d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -85,7 +85,6 @@ void *get_first_hob(uint16_t type); void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_guid_hob(const EFI_GUID *guid); - asmlinkage void chipset_teardown_car_main(void); #endif /* FSP1_1_UTIL_H */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 46df1c8697..5a59c502a9 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -23,7 +23,7 @@ static void raminit_common(struct romstage_params *params) { bool s3wake; - struct region_device rdev; + size_t mrc_size; post_code(0x32); @@ -45,24 +45,31 @@ static void raminit_common(struct romstage_params *params) /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (CONFIG(CACHE_MRC_SETTINGS) - && (!mrc_cache_get_current(MRC_TRAINING_DATA, - params->fsp_version, - &rdev))) { - /* MRC cache found */ - params->saved_data_size = region_device_sz(&rdev); - params->saved_data = rdev_mmap_full(&rdev); + } else { /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - } else if (s3wake) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - /* FIXME: A "system" reset is likely enough: */ - full_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); + + params->saved_data = NULL; + if (CONFIG(CACHE_MRC_SETTINGS)) + params->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + params->fsp_version, + &mrc_size); + if (params->saved_data) { + /* MRC cache found */ + params->saved_data_size = mrc_size; + + } else if (s3wake) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache " + "found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + } } } @@ -283,13 +290,6 @@ __weak void mainboard_add_dimm_info( { } -/* Get the memory configuration data */ -__weak int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev) -{ - return -1; -} - /* Save the memory configuration data */ __weak int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3caa04ac25..1a1da6c1e9 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -132,12 +132,14 @@ config FSP_USES_CB_STACK config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK help - The amount of anticipated heap usage in CAR by FSP to setup HOB. - This configuration is applicable for FSP specification using shared - stack with coreboot/bootloader. - Sync this value with Platform FSP integration guide recommendation. + The amount of memory coreboot reserves for the FSP to use. In the + case of FSP 2.1 and newer that share the stack with coreboot instead + of having its own stack, this is the amount of anticipated heap usage + in CAR by FSP to setup HOB and needs to be the recommended value from + the Platform FSP integration guide. In the case of the FSP having its + own stack that will be placed in DRAM and not in CAR, this is the + amount of memory the FSP needs for its stack and heap. config FSP2_0_USES_TPM_MRC_HASH bool @@ -211,6 +213,50 @@ config FSP_M_ADDR help The address FSP-M will be relocated to during build time +config FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_4 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + bool + help + FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2 + +config FSP_STATUS_GLOBAL_RESET + hex + default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 + default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + default 0xffffffff + help + If global reset is supported by SoC then select the correct status value for global + reset type from SoC Kconfig based on available Kconfig options + FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported. + if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index e954a462a1..32140f4228 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -14,6 +14,7 @@ romstage-$(CONFIG_MMA) += mma_core.c romstage-y += cbmem.c ramstage-y += debug.c +ramstage-$(CONFIG_USE_INTEL_FSP_MP_INIT) += fsp_mpinit.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462b40..5388b8912a 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,7 +6,14 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; + uint8_t *tolum_base; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum); + + /* + * The TOLUM range may have other memory regions (such as APEI + * BERT region on top of CBMEM (IMD root and IMD small) region. + */ + return tolum_base + cbmem_overhead_size(); } diff --git a/src/drivers/intel/fsp2_0/fsp_mpinit.c b/src/drivers/intel/fsp2_0/fsp_mpinit.c new file mode 100644 index 0000000000..cda9269cb8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/fsp_mpinit.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * As per FSP integration guide: + * If bootloader needs to take control of APs back, a full AP re-initialization is + * required after FSP-S is completed and control has been transferred back to bootloader + */ +void do_mpinit_after_fsp(void) +{ + init_cpus(); +} diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index fdc92a7cbf..60ab7cb3ec 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -207,7 +207,7 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) return NULL; } -static void display_fsp_version_info_hob(const void *hob, size_t size) +static void display_fsp_version_info_hob(const void *hob) { #if CONFIG(DISPLAY_FSP_VERSION_INFO) const FIRMWARE_VERSION_INFO *fvi; @@ -218,8 +218,7 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) fvi = (void *)&fvih[1]; str_ptr = (char *)((uintptr_t)fvi + - (fvih->Count * sizeof (FIRMWARE_VERSION_INFO))); - size -= sizeof(SMBIOS_STRUCTURE); + (fvih->Count * sizeof(FIRMWARE_VERSION_INFO))); for (index = 0; index < fvih->Count; index++) { cnt = strlen(str_ptr); @@ -279,7 +278,7 @@ void fsp_display_fvi_version_hob(void) if (fsp_guid_compare(hob_uuid, uuid_fv_info)) { size = hob->length - (HOB_HEADER_LEN + 16); - display_fsp_version_info_hob(hob, size); + display_fsp_version_info_hob(hob); } } } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e850d..9bfb0f15a9 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,9 +43,16 @@ void fsp_verify_memory_init_hobs(void) die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } + + if (CONFIG(ACPI_BERT) && + range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) { + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n", + range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE); + die("Space between cbmem_top and APEI BERT!\n"); + } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index d2c556f916..97e2fea34d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -31,7 +31,6 @@ enum fsp_notify_phase { END_OF_FIRMWARE = 0xF0 }; - /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); @@ -74,6 +73,13 @@ const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd); void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); +/* + * As per FSP integration guide: + * If bootloader needs to take control of APs back, a full AP re-initialization is + * required after FSP-S is completed and control has been transferred back to bootloader + */ +void do_mpinit_after_fsp(void); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index ccb66cbeb5..e3d19180f0 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -24,7 +24,7 @@ void fsp_verify_memory_init_hobs(void); void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file - * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + * that is conditionally build with CONFIG(DISPLAY_UPD_DATA). */ void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd); @@ -32,7 +32,7 @@ void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd); /* Callbacks for displaying HOBs - place in a separate file that is - * conditionally build with CONFIG_DISPLAY_HOBS. + * conditionally build with CONFIG(DISPLAY_HOBS). */ const char *soc_get_hob_type_name(const struct hob_header *hob); const char *soc_get_guid_name(const uint8_t *guid); diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 93e54b15bc..8781bde8d8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -31,7 +31,6 @@ #include #endif - #pragma pack(pop) #endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389592..1ef9324d40 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -93,8 +93,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) { - struct region_device rdev; void *data; + size_t mrc_size; arch_upd->NvsBufferPtr = NULL; @@ -113,25 +113,22 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) return; } - if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0) - return; - /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - data = rdev_mmap_full(&rdev); + data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, fsp_version, + &mrc_size); if (data == NULL) return; if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && - !mrc_cache_verify_hash(data, region_device_sz(&rdev))) + !mrc_cache_verify_hash(data, mrc_size)) return; /* MRC cache found */ arch_upd->NvsBufferPtr = data; - printk(BIOS_SPEW, "MRC cache found, size %zx\n", - region_device_sz(&rdev)); + printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size); } static enum cb_err check_region_overlap(const struct memranges *ranges, @@ -184,8 +181,9 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, * top and does not reinitialize stack pointer. The parameters passed * as StackBase and StackSize are actually for temporary RAM and HOBs * and are not related to FSP stack at all. + * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. */ - if (CONFIG(FSP_USES_CB_STACK)) { + if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { arch_upd->StackBase = temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { @@ -278,6 +276,21 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + /* + * If ACPI APEI BERT region size is defined, reserve memory for it. + * +------------------------+ range_entry_top(tolum) + * | Other reserved regions | + * | APEI BERT region | + * +------------------------+ cbmem_top() + * | CBMEM IMD ROOT | + * | CBMEM IMD SMALL | + * +------------------------+ range_entry_base(tolum), TOLUM + * | CBMEM FSP MEMORY | + * | Other CBMEM regions... | + */ + if (CONFIG(ACPI_BERT)) + arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; + /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 5b964d51fb..03184e16ca 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -10,6 +10,7 @@ #include #define BSP_CPU_SLOT 0 +#define SINGLE_CHIP_PACKAGE 0 static efi_return_status_t mp_get_number_of_processors(const efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, @@ -31,6 +32,8 @@ static efi_return_status_t mp_get_processor_info(const efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { + unsigned int num_virt_cores, num_phys_cores; + if (cpu_index() < 0) return FSP_DEVICE_ERROR; @@ -48,7 +51,14 @@ static efi_return_status_t mp_get_processor_info(const if (processor_number == BSP_CPU_SLOT) processor_info_buffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; - /* TODO: Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + /* Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + cpu_read_topology(&num_phys_cores, &num_virt_cores); + + /* FSP will add one to the value in this Package field */ + processor_info_buffer->Location.Package = SINGLE_CHIP_PACKAGE; + processor_info_buffer->Location.Core = num_phys_cores; + processor_info_buffer->Location.Thread = num_virt_cores; + return FSP_SUCCESS; } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 663b1d7cfd..0b6540e1de 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -127,6 +127,10 @@ static void do_silicon_init(struct fsp_header *hdr) fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); + /* Reinitialize CPUs if FSP-S has done MP Init */ + if (CONFIG(USE_INTEL_FSP_MP_INIT)) + do_mpinit_after_fsp(); + if (!CONFIG(PLATFORM_USES_FSP2_2)) return; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index cfa83d7e0e..acc3f4b9b3 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 635de1c87a..c515888a1b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -68,6 +68,14 @@ config GFX_GMA_ANALOG_I2C_HDMI_C config GFX_GMA_ANALOG_I2C_HDMI_D bool +config GFX_GMA_IGNORE_PRESENCE_STRAPS + def_bool n + depends on MAINBOARD_HAS_LIBGFXINIT + help + libgfxinit uses the GPU presence straps to determine if a display port + is present/enabled. Select this option if a board doesn't correctly implement + these straps, causing libgfxinit to fail to detect an attached panel. + config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ @@ -127,11 +135,4 @@ config GFX_GMA_ANALOG_I2C_PORT digital displays. In that case, the EDID for a VGA display has to be read over the I2C interface of the coupled digital port. -config GFX_GMA_IGNORE_PRESENCE_STRAPS - def_bool n - help - libgfxinit uses the GPU presence straps to determine if a display port - is present/enabled. Select this option if a board doesn't correctly implement - these straps, causing libgfxinit to fail to detect an attached panel. - endif diff --git a/src/drivers/intel/gma/drm_dp_helper.h b/src/drivers/intel/gma/drm_dp_helper.h deleted file mode 100644 index f2e06c33f3..0000000000 --- a/src/drivers/intel/gma/drm_dp_helper.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -/* From the VESA DisplayPort spec */ - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) - -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) - -/* AUX CH addresses */ -/* DPCD */ -#define DP_DPCD_REV 0x000 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 - -/* link configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_PSR_EN_CFG 0x170 -# define DP_PSR_ENABLE (1 << 0) -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) -# define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_EDP_CONFIGURATION_SET 0x10a - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 670ea6efa1..8e9fc904f2 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -4,7 +4,6 @@ #define INTEL_I915_H 1 #include -#include #include #include diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index b4face49fb..137d7673fb 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -27,7 +27,6 @@ #define IVB_GMCH_GMS_SHIFT 4 #define IVB_GMCH_GMS_MASK 0xf - /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ @@ -296,7 +295,6 @@ #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ - /* * Reset registers */ @@ -791,7 +789,6 @@ #define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21) - /* * Framebuffer compression for Sandybridge * @@ -801,7 +798,6 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104 - /* * GPIO regs */ @@ -1213,7 +1209,6 @@ HSW_CXT_RENDER_SIZE(ctx_reg) + \ GEN7_CXT_VFSTATE_SIZE(ctx_reg)) - /* * Overlay regs */ @@ -1254,7 +1249,6 @@ #define _BCLRPAT_B 0x61020 #define _VSYNCSHIFT_B 0x61028 - #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) @@ -1311,7 +1305,6 @@ #define ADPA_DPMS_STANDBY (2<<10) #define ADPA_DPMS_OFF (3<<10) - /* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 #define HDMIB_HOTPLUG_INT_EN (1 << 29) @@ -1673,6 +1666,33 @@ #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254 +#define UTIL_PIN_CTL 0x48400 +#define UTIL_PIN_ENABLE (1 << 31) + +#define UTIL_PIN_PIPE(x) ((x) << 29) +#define UTIL_PIN_PIPE_MASK (3 << 29) +#define UTIL_PIN_MODE_PWM (1 << 24) +#define UTIL_PIN_MODE_MASK (0xf << 24) +#define UTIL_PIN_POLARITY (1 << 22) + +/* BXT backlight register definition. */ +#define _BXT_BLC_PWM_CTL1 0xC8250 +#define BXT_BLC_PWM_ENABLE (1 << 31) +#define BXT_BLC_PWM_POLARITY (1 << 29) +#define _BXT_BLC_PWM_FREQ1 0xC8254 +#define _BXT_BLC_PWM_DUTY1 0xC8258 + +#define _BXT_BLC_PWM_CTL2 0xC8350 +#define _BXT_BLC_PWM_FREQ2 0xC8354 +#define _BXT_BLC_PWM_DUTY2 0xC8358 + +#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \ + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \ + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \ + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) + /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ @@ -2781,7 +2801,6 @@ #define _PIPEB_FRMCOUNT_GM45 0x71040 #define _PIPEB_FLIPCOUNT_GM45 0x71044 - /* Display B control */ #define _DSPBCNTR 0x71180 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) @@ -2984,7 +3003,6 @@ #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff - #define _PIPEA_DATA_M1 0x60030 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ #define TU_SIZE_MASK 0x7e000000 @@ -3538,7 +3556,6 @@ #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) #define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) - #define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c index ab49604bf1..a7f3fdc18a 100644 --- a/src/drivers/intel/gma/int15.c +++ b/src/drivers/intel/gma/int15.c @@ -98,7 +98,6 @@ int intel_vga_int15_handler(void) return res; } - void install_intel_vga_int15_handler(int active_lfp_, int pfit_, int display_, int panel_type_) { active_lfp = active_lfp_; diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index 559ec22ab1..cddd4ac6b8 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -27,7 +27,6 @@ enum { GMA_INT15_ACTIVE_LFP_EDP = 0x03, }; - #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type); diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 3df72c71fb..558dae6aba 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -396,7 +396,6 @@ struct bdb_sdvo_lvds_options { u8 panel_misc_bits_4; } __packed; - #define BDB_DRIVER_FEATURE_NO_LVDS 0 #define BDB_DRIVER_FEATURE_INT_LVDS 1 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index f1ad265b9f..b42c52d02c 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -15,31 +15,31 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf, { u8 *ptr; - memset(head, 0, sizeof (*head)); + memset(head, 0, sizeof(*head)); - memset(head->signature, ' ', sizeof (head->signature)); + memset(head->signature, ' ', sizeof(head->signature)); memcpy(head->signature, idstr, - MIN(strlen(idstr), sizeof (head->signature))); + MIN(strlen(idstr), sizeof(head->signature))); head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); + head->header_size = sizeof(*head); + head->bdb_offset = sizeof(*head); struct bdb_header *const bdb_head = (struct bdb_header *)(head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); + memset(bdb_head, 0, sizeof(*bdb_head)); memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); + bdb_head->header_size = sizeof(*bdb_head); ptr = (u8 *)(bdb_head + 1); ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (struct bdb_general_features); - ptr[2] = sizeof (struct bdb_general_features) >> 8; + ptr[1] = sizeof(struct bdb_general_features); + ptr[2] = sizeof(struct bdb_general_features) >> 8; ptr += 3; struct bdb_general_features *const genfeat = (struct bdb_general_features *)ptr; - memset(genfeat, 0, sizeof (*genfeat)); + memset(genfeat, 0, sizeof(*genfeat)); genfeat->panel_fitting = 3; genfeat->flexaim = 1; genfeat->download_ext_vbt = 1; @@ -50,7 +50,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf, genfeat->int_crt_support = 1; genfeat->dp_ssc_enb = 1; - ptr += sizeof (*genfeat); + ptr += sizeof(*genfeat); bdb_head->bdb_size = ptr - (u8 *)bdb_head; head->vbt_size = ptr - (u8 *)head; diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index 46e9788905..718992e477 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -16,7 +16,6 @@ #define I210_DONE 0x02 /* command done bit */ #define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum */ - /*define some other useful values here */ #define I210_POLL_TIMEOUT_US 300000 /* 300 ms */ /*Define some error states here*/ diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index f32f744f8f..d4cf33d9fb 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -18,6 +18,59 @@ #define CIO2_PCI_DEV 0x14 #define CIO2_PCI_FN 0x3 #define POWER_RESOURCE_NAME "PRIC" +#define GUARD_VARIABLE_FORMAT "RES%1d" +#define ENABLE_METHOD_FORMAT "ENB%1d" +#define DISABLE_METHOD_FORMAT "DSB%1d" +#define UNKNOWN_METHOD_FORMAT "UNK%1d" +#define CLK_ENABLE_METHOD "MCON" +#define CLK_DISABLE_METHOD "MCOF" + +static struct camera_resource_manager res_mgr; + +static void resource_set_action_type(struct resource_config *res_config, + enum action_type action) +{ + if (res_config) + res_config->action = action; +} + +static enum action_type resource_get_action_type(const struct resource_config *res_config) +{ + return res_config ? res_config->action : UNKNOWN_ACTION; +} + +static enum ctrl_type resource_get_ctrl_type(const struct resource_config *res_config) +{ + return res_config ? res_config->type : UNKNOWN_CTRL; +} + +static void resource_set_clk_config(struct resource_config *res_config, + const struct clk_config *clk_conf) +{ + if (res_config) { + res_config->type = IMGCLK; + res_config->clk_conf = clk_conf; + } +} + +static const struct clk_config *resource_clk_config(const struct resource_config *res_config) +{ + return res_config ? res_config->clk_conf : NULL; +} + +static void resource_set_gpio_config(struct resource_config *res_config, + const struct gpio_config *gpio_conf) +{ + if (res_config) { + res_config->type = GPIO; + res_config->gpio_conf = gpio_conf; + } +} + +static const struct gpio_config *resource_gpio_config(const struct resource_config *res_config) +{ + return res_config ? res_config->gpio_conf : NULL; +} /* * This implementation assumes there is only 1 endpoint at each end of every data port. It also @@ -399,7 +452,12 @@ static void camera_fill_sensor(const struct device *dev) static void camera_fill_nvm(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + struct acpi_dp *dsd; + + if (!config->nvm_compat) + return; + + dsd = acpi_dp_new_table("_DSD"); /* It might be possible to default size or width based on type. */ if (!config->disable_nvm_defaults && !config->nvm_pagesize) @@ -420,6 +478,7 @@ static void camera_fill_nvm(const struct device *dev) if (config->nvm_width) acpi_dp_add_integer(dsd, "address-width", config->nvm_width); + acpi_dp_add_string(dsd, "compatible", config->nvm_compat); acpi_dp_write(dsd); } @@ -436,53 +495,271 @@ static void camera_fill_vcm(const struct device *dev) acpi_dp_write(dsd); } -static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, - struct operation_seq *seq) +static int get_resource_index(const struct resource_config *res_config) +{ + enum ctrl_type type = resource_get_ctrl_type(res_config); + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + unsigned int i; + uint8_t res_id; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + res_id = clk_config->clknum; + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + res_id = gpio_config->gpio_num; + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work", type); + return -1; + } + + for (i = 0; i < res_mgr.cnt; i++) + if (res_mgr.resource[i].type == type && res_mgr.resource[i].id == res_id) + return i; + + return -1; +} + +static void add_guarded_method_namestring(struct resource_config *res_config, int res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + enum action_type action = resource_get_action_type(res_config); + + switch (action) { + case ENABLE: + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + break; + case DISABLE: + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + break; + default: + snprintf(method_name, sizeof(method_name), UNKNOWN_METHOD_FORMAT, res_index); + printk(BIOS_ERR, "Unsupported resource action: %x\n", action); + } + + acpigen_emit_namestring(method_name); +} + +static void call_guarded_method(struct resource_config *res_config) +{ + int res_index; + + if (res_config == NULL) + return; + + res_index = get_resource_index(res_config); + + if (res_index != -1) + add_guarded_method_namestring(res_config, res_index); +} + +static void add_clk_op(const struct clk_config *clk_config, enum action_type action) +{ + if (clk_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_ENABLE_METHOD); + acpigen_emit_namestring(CLK_ENABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_write_integer(clk_config->freq); + acpigen_pop_len(); /* CondRefOf */ + break; + case DISABLE: + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_string(CLK_DISABLE_METHOD); + acpigen_emit_namestring(CLK_DISABLE_METHOD); + acpigen_write_integer(clk_config->clknum); + acpigen_pop_len(); /* CondRefOf */ + break; + default: + acpigen_write_debug_string("Unsupported clock action"); + printk(BIOS_ERR, "Unsupported clock action: %x\n" + "OS camera driver will likely not work", action); + } +} + +static void add_gpio_op(const struct gpio_config *gpio_config, enum action_type action) +{ + if (gpio_config == NULL) + return; + + switch (action) { + case ENABLE: + acpigen_soc_set_tx_gpio(gpio_config->gpio_num); + break; + case DISABLE: + acpigen_soc_clear_tx_gpio(gpio_config->gpio_num); + break; + default: + acpigen_write_debug_string("Unsupported GPIO action"); + printk(BIOS_ERR, "Unsupported GPIO action: %x\n" + "OS camera driver will likely not work\n", action); + } +} + +static void add_power_operation(const struct resource_config *res_config) +{ + const struct clk_config *clk_config; + const struct gpio_config *gpio_config; + enum ctrl_type type = resource_get_ctrl_type(res_config); + enum action_type action = resource_get_action_type(res_config); + + if (res_config == NULL) + return; + + switch (type) { + case IMGCLK: + clk_config = resource_clk_config(res_config); + add_clk_op(clk_config, action); + break; + case GPIO: + gpio_config = resource_gpio_config(res_config); + add_gpio_op(gpio_config, action); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", type); + break; + } +} + +static void write_guard_variable(uint8_t res_index) +{ + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + acpigen_write_name_integer(varname, 0); +} + +static void write_enable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, ENABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* method_name */ +} + +static void write_disable_method(struct resource_config *res_config, uint8_t res_index) +{ + char method_name[ACPI_NAME_BUFFER_SIZE]; + char varname[ACPI_NAME_BUFFER_SIZE]; + + snprintf(varname, sizeof(varname), GUARD_VARIABLE_FORMAT, res_index); + + snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, res_index); + + acpigen_write_method_serialized(method_name, 0); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(varname); + acpigen_write_integer(0x0); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring(varname); + acpigen_pop_len(); /* if */ + + acpigen_write_if_lequal_namestr_int(varname, 0); + resource_set_action_type(res_config, DISABLE); + add_power_operation(res_config); + acpigen_pop_len(); /* if */ + acpigen_pop_len(); /* method_name */ +} + +static void add_guarded_operations(const struct drivers_intel_mipi_camera_config *config, + const struct operation_seq *seq) { unsigned int i; uint8_t index; - uint8_t gpio_num; + uint8_t res_id; + struct resource_config res_config; + int res_index; - for (i = 0; i < seq->ops_cnt; i++) { + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; switch (seq->ops[i].type) { case IMGCLK: - index = seq->ops[i].index; - if (seq->ops[i].action == ENABLE) { - acpigen_emit_namestring("MCON"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - acpigen_write_byte(config->clk_panel.clks[index].freq); - } else if (seq->ops[i].action == DISABLE) { - acpigen_emit_namestring("MCOF"); - acpigen_write_byte(config->clk_panel.clks[index].clknum); - } else { - acpigen_write_debug_string("Unsupported clock action"); - printk(BIOS_ERR, "Unsupported clock action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->clk_panel.clks[index].clknum; + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); break; case GPIO: - index = seq->ops[i].index; - gpio_num = config->gpio_panel.gpio[index].gpio_num; - if (seq->ops[i].action == ENABLE) { - acpigen_soc_set_tx_gpio(gpio_num); - } else if (seq->ops[i].action == DISABLE) { - acpigen_soc_clear_tx_gpio(gpio_num); - } else { - acpigen_write_debug_string("Unsupported GPIO action"); - printk(BIOS_ERR, "Unsupported GPIO action: %x\n", - seq->ops[i].action); - printk(BIOS_ERR, "OS camera driver will likely not work"); - } - + res_id = config->gpio_panel.gpio[index].gpio_num; + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); break; default: - printk(BIOS_ERR, "Unsupported power operation: %x\n", seq->ops[i].type); - printk(BIOS_ERR, "OS camera driver will likely not work"); - break; + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; } + res_index = get_resource_index(&res_config); + + if (res_index == -1) { + if (res_mgr.cnt >= MAX_GUARDED_RESOURCES) { + printk(BIOS_ERR, "Unable to add guarded camera resource\n" + "OS camera driver will likely not work\n"); + return; + } + + res_mgr.resource[res_mgr.cnt].id = res_id; + res_mgr.resource[res_mgr.cnt].type = seq->ops[i].type; + + write_guard_variable(res_mgr.cnt); + write_enable_method(&res_config, res_mgr.cnt); + write_disable_method(&res_config, res_mgr.cnt); + + res_mgr.cnt++; + } + } +} + +static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *config, + struct operation_seq *seq) +{ + struct resource_config res_config; + unsigned int i; + uint8_t index; + + for (i = 0; i < seq->ops_cnt && i < MAX_PWR_OPS; i++) { + index = seq->ops[i].index; + + switch (seq->ops[i].type) { + case IMGCLK: + resource_set_clk_config(&res_config, &config->clk_panel.clks[index]); + break; + case GPIO: + resource_set_gpio_config(&res_config, &config->gpio_panel.gpio[index]); + break; + default: + printk(BIOS_ERR, "Unsupported power operation: %x\n" + "OS camera driver will likely not work\n", + seq->ops[i].type); + return; + } + + resource_set_action_type(&res_config, seq->ops[i].action); + call_guarded_method(&res_config); if (seq->ops[i].delay_ms) acpigen_write_sleep(seq->ops[i].delay_ms); } @@ -490,8 +767,6 @@ static void fill_power_res_sequence(struct drivers_intel_mipi_camera_config *con static void write_pci_camera_device(const struct device *dev) { - struct drivers_intel_mipi_camera_config *config = dev->chip_info; - if (dev->path.type != DEVICE_PATH_PCI) { printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); return; @@ -499,8 +774,7 @@ static void write_pci_camera_device(const struct device *dev) acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR_pci_device(dev); - acpigen_write_name_string("_DDN", config->device_type == INTEL_ACPI_CAMERA_CIO2 ? - "Camera and Imaging Subsystem" : "Imaging Unit"); + acpigen_write_name_string("_DDN", "Camera and Imaging Subsystem"); } static void write_i2c_camera_device(const struct device *dev, const char *scope) @@ -513,11 +787,6 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope) .resource = scope, }; - if (dev->path.type != DEVICE_PATH_I2C) { - printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); - return; - } - acpigen_write_device(acpi_device_name(dev)); /* add power resource */ @@ -559,10 +828,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope) if (config->acpi_hid) acpigen_write_name_string("_HID", config->acpi_hid); - else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + else if (config->device_type == INTEL_ACPI_CAMERA_VCM || + config->device_type == INTEL_ACPI_CAMERA_NVM) acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); - else if (config->device_type == INTEL_ACPI_CAMERA_NVM) - acpigen_write_name_string("_HID", "INT3499"); acpigen_write_name_integer("_UID", config->acpi_uid); acpigen_write_name_string("_DDN", config->chip_name); @@ -638,19 +906,50 @@ static void write_camera_device_common(const struct device *dev) static void camera_fill_ssdt(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + const char *scope = NULL; + const struct device *pdev; - if (!dev->enabled || !scope) + if (!dev->enabled) return; - /* Device */ - acpigen_write_scope(scope); + if (config->has_power_resource) { + pdev = dev->bus->dev; + if (!pdev || !pdev->enabled) + return; - if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || - config->device_type == INTEL_ACPI_CAMERA_IMGU) - write_pci_camera_device(dev); - else + scope = acpi_device_scope(pdev); + if (!scope) + return; + + acpigen_write_scope(scope); + add_guarded_operations(config, &config->on_seq); + add_guarded_operations(config, &config->off_seq); + acpigen_pop_len(); /* Guarded power resource operations scope */ + } + + switch (dev->path.type) { + case DEVICE_PATH_I2C: + scope = acpi_device_scope(dev); + if (!scope) + return; + + acpigen_write_scope(scope); write_i2c_camera_device(dev, scope); + break; + case DEVICE_PATH_GENERIC: + pdev = dev->bus->dev; + scope = acpi_device_scope(pdev); + if (!scope) + return; + + acpigen_write_scope(scope); + write_pci_camera_device(pdev); + break; + default: + printk(BIOS_ERR, "Unsupported device type: %x\n" + "OS camera driver will likely not work\n", dev->path.type); + return; + } write_camera_device_common(dev); @@ -669,7 +968,7 @@ static void camera_fill_ssdt(const struct device *dev) static const char *camera_acpi_name(const struct device *dev) { const char *prefix = NULL; - static char name[5]; + static char name[ACPI_NAME_BUFFER_SIZE]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; if (config->acpi_name) diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index d133f7df86..28f8464ec2 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -13,6 +13,7 @@ #define MAX_CLK_CONFIGS 2 #define MAX_GPIO_CONFIGS 4 #define MAX_PWR_OPS 5 +#define MAX_GUARDED_RESOURCES 10 #define SEQ_OPS_CLK_ENABLE(ind, delay) \ { .type = IMGCLK, .index = (ind), .action = ENABLE, .delay_ms = (delay) } @@ -70,15 +71,36 @@ enum intel_power_action_type { }; enum ctrl_type { - IMGCLK = 1, + UNKNOWN_CTRL, + IMGCLK, GPIO }; enum action_type { - ENABLE = 1, + UNKNOWN_ACTION, + ENABLE, DISABLE }; +struct camera_resource { + uint8_t type; + uint8_t id; +}; + +struct camera_resource_manager { + uint8_t cnt; + struct camera_resource resource[MAX_GUARDED_RESOURCES]; +}; + +struct resource_config { + enum action_type action; + enum ctrl_type type; + union { + const struct clk_config *clk_conf; + const struct gpio_config *gpio_conf; + }; +}; + struct clk_config { /* IMGCLKOUT_x being used for a port */ uint8_t clknum; @@ -219,6 +241,7 @@ struct drivers_intel_mipi_camera_config { uint32_t nvm_pagesize; uint32_t nvm_readonly; uint32_t nvm_width; + const char *nvm_compat; /* Settings specific to vcm */ const char *vcm_compat; diff --git a/src/drivers/intel/soundwire/soundwire.h b/src/drivers/intel/soundwire/soundwire.h index 3e2addfcbf..6ee1fad7c0 100644 --- a/src/drivers/intel/soundwire/soundwire.h +++ b/src/drivers/intel/soundwire/soundwire.h @@ -4,7 +4,7 @@ #define __DRIVERS_INTEL_SOUNDWIRE_H__ #include -#include +#include /** * enum intel_soundwire_quirk - Quirks for controller master links. diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index fb60c6fbe1..83df82233e 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -2,7 +2,7 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on PCI default y if PCIEXP_PLUGIN_SUPPORT - select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES + select DRIVERS_WIFI_GENERIC if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 9fcd7ba8af..3c90dde5d3 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -8,10 +8,7 @@ #include #include #include "chip.h" -#include "drivers/wifi/generic_wifi.h" - -#define PMCS_DR 0xcc -#define PME_STS (1 << 15) +#include "drivers/wifi/generic/chip.h" #if CONFIG(GENERATE_SMBIOS_TABLES) static int smbios_write_wifi(struct device *dev, int *handle, @@ -50,27 +47,19 @@ static int smbios_write_wifi(struct device *dev, int *handle, static void intel_wifi_fill_ssdt(const struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; - struct generic_wifi_config generic_config; + struct drivers_wifi_generic_config generic_config; - if (config) { + if (config) generic_config.wake = config->wake; - /* By default, all intel wifi chips wake from S3 */ - generic_config.maxsleep = 3; - } - generic_wifi_fill_ssdt(dev, config ? &generic_config : NULL); + + wifi_generic_fill_ssdt(dev, config ? &generic_config : NULL); } #endif static void wifi_pci_dev_init(struct device *dev) { - pci_dev_init(dev); - - if (CONFIG(ELOG)) { - uint32_t val; - val = pci_read_config16(dev, PMCS_DR); - if (val & PME_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); - } + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); } struct device_operations device_ops = { @@ -83,7 +72,7 @@ struct device_operations device_ops = { #endif .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = generic_wifi_acpi_name, + .acpi_name = wifi_generic_acpi_name, .acpi_fill_ssdt = intel_wifi_fill_ssdt, #endif }; diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 44ed17e548..1137dcf8d5 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -33,3 +33,12 @@ config BMC_KCS_BASE help The PNP base address of BMC KCS. It must be equal to the pnp port value defined in devicetree for chip drivers/ipmi. + +config IPMI_KCS_TIMEOUT_MS + int + default 5000 + depends on IPMI_KCS + help + The time unit is millisecond for each IPMI KCS transfer. + IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or + greater is recommended. diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 1d6b71cee9..dcad8627ce 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include "ipmi_kcs.h" #define IPMI_KCS_STATE(_x) ((_x) >> 6) @@ -35,30 +35,24 @@ static unsigned char ipmi_kcs_status(int port) static int wait_ibf_timeout(int port) { - int timeout = 1000; - do { - if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF)) - return 0; - udelay(100); - } while (timeout--); - printk(BIOS_ERR, "wait_ibf timeout!\n"); - return timeout; + if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, !(ipmi_kcs_status(port) & IPMI_KCS_IBF))) { + printk(BIOS_ERR, "wait_ibf timeout!\n"); + return 1; + } else { + return 0; + } } static int wait_obf_timeout(int port) { - int timeout = 1000; - do { - if ((ipmi_kcs_status(port) & IPMI_KCS_OBF)) - return 0; - udelay(100); - } while (timeout--); - - printk(BIOS_ERR, "wait_obf timeout!\n"); - return timeout; + if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, (ipmi_kcs_status(port) & IPMI_KCS_OBF))) { + printk(BIOS_ERR, "wait_obf timeout!\n"); + return 1; + } else { + return 0; + } } - static int ipmi_kcs_send_data_byte(int port, const unsigned char byte) { unsigned char status; diff --git a/src/drivers/ipmi/ocp/Kconfig b/src/drivers/ipmi/ocp/Kconfig new file mode 100644 index 0000000000..26503efb8d --- /dev/null +++ b/src/drivers/ipmi/ocp/Kconfig @@ -0,0 +1,10 @@ +config IPMI_OCP + bool + default n + help + This implements OCP specific IPMI command + +config IPMI_OCP_MANU_ID + hex + default 0x0 + depends on IPMI_OCP diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc new file mode 100644 index 0000000000..8291f82677 --- /dev/null +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.c b/src/drivers/ipmi/ocp/ipmi_ocp.c new file mode 100644 index 0000000000..07628ee1ff --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_ocp.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Place in devicetree.cb: + * + * chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + * end + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipmi_ocp.h" + +static int ipmi_set_processor_information_param1(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param1_req req1 = {0}; + struct ipmi_rsp rsp; + int mfid = CONFIG_IPMI_OCP_MANU_ID; + + memcpy(&req1.data.manufacturer_id, &mfid, 3); + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req1.data.manufacturer_id[2], req1.data.manufacturer_id[1], + req1.data.manufacturer_id[0]); + + req1.data.index = 0; + req1.data.parameter_selector = 1; + + /* Get processor name. */ + fill_processor_name(req1.product_name); + printk(BIOS_DEBUG, "IPMI BMC CPU NAME: %s.\n", req1.product_name); + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req1, + sizeof(req1), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI BMC: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static int ipmi_set_processor_information_param2(struct device *dev) +{ + int ret; + struct ipmi_processor_info_param2_req req2 = {0}; + struct ipmi_rsp rsp; + uint8_t stepping_id; + int mfid = CONFIG_IPMI_OCP_MANU_ID; + unsigned int core_count, thread_count; + struct cpuinfo_x86 c; + + memcpy(&req2.data.manufacturer_id, &mfid, 3); + printk(BIOS_DEBUG, "IPMI BMC manufacturer id: %02x%02x%02x\n", + req2.data.manufacturer_id[2], req2.data.manufacturer_id[1], + req2.data.manufacturer_id[0]); + + req2.data.index = 0; + req2.data.parameter_selector = 2; + + /* Get core number and thread number. */ + cpu_read_topology(&core_count, &thread_count); + req2.core_number = core_count; + req2.thread_number = thread_count; + printk(BIOS_DEBUG, "IPMI BMC CPU has %u cores, %u threads enabled.\n", + req2.core_number, req2.thread_number); + + /* Get processor frequency. */ + req2.processor_freq = 100 * cpu_get_max_ratio(); + printk(BIOS_DEBUG, "IPMI BMC CPU frequency is %u MHz.\n", + req2.processor_freq); + + /* Get revision. */ + get_fms(&c, cpuid_eax(1)); + stepping_id = c.x86_mask; + printk(BIOS_DEBUG, "IPMI BMC CPU stepping id is %x.\n", stepping_id); + switch (stepping_id) { + /* TBD */ + case 0x0a: + req2.revision[0] = 'A'; + req2.revision[1] = '0'; + break; + default: + req2.revision[0] = 'X'; + req2.revision[1] = 'X'; + } + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_OEM_COMMON, 0, + IPMI_BMC_SET_PROCESSOR_INFORMATION, (u8 *) &req2, + sizeof(req2), (u8 *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + return CB_SUCCESS; +} + +static void ipmi_set_processor_information(struct device *dev) +{ + if (ipmi_set_processor_information_param1(dev)) + printk(BIOS_ERR, "IPMI BMC set param 1 processor info failed\n"); + + if (ipmi_set_processor_information_param2(dev)) + printk(BIOS_ERR, "IPMI BMC set param 2 processor info failed\n"); +} + +static void ipmi_ocp_init(struct device *dev) +{ + /* Add OCP specific IPMI command */ +} + +static void ipmi_ocp_final(struct device *dev) +{ + /* Add OCP specific IPMI command */ + + /* Send processor information */ + ipmi_set_processor_information(dev); +} + +static void ipmi_set_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +} + +static void ipmi_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, 0); + res->base = dev->path.pnp.port; + res->size = 2; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ops = { + .read_resources = ipmi_read_resources, + .set_resources = ipmi_set_resources, + .init = ipmi_ocp_init, + .final = ipmi_ocp_final, +}; + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + printk(BIOS_ERR, "%s: Unsupported device type\n", + dev_path(dev)); + else if (dev->path.pnp.port & 1) + printk(BIOS_ERR, "%s: Base address needs to be aligned to 2\n", + dev_path(dev)); + else + dev->ops = &ops; +} + +struct chip_operations drivers_ipmi_ocp_ops = { + CHIP_NAME("IPMI OCP") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h new file mode 100644 index 0000000000..96b0086298 --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __IPMI_OCP_H +#define __IPMI_OCP_H + +#include +#include +#include "drivers/ipmi/ipmi_kcs.h" + +#define IPMI_NETFN_OEM_COMMON 0x36 +#define IPMI_BMC_SET_PROCESSOR_INFORMATION 0x10 +#define IPMI_BMC_GET_PROCESSOR_INFORMATION 0x11 + +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce + +struct ipmi_processor_info_req { + uint8_t manufacturer_id[3]; + uint8_t index; + uint8_t parameter_selector; +} __packed; + +struct ipmi_processor_info_param1_req { + struct ipmi_processor_info_req data; + char product_name[48]; +} __packed; + +struct ipmi_processor_info_param2_req { + struct ipmi_processor_info_req data; + uint8_t core_number; + uint16_t thread_number; + uint16_t processor_freq; + char revision[2]; +} __packed; + +#endif diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 79cc205a9d..e09c5d8859 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -35,4 +35,18 @@ config MRC_WRITE_NV_LATE normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY. +config MRC_STASH_TO_CBMEM + bool + default y if MRC_WRITE_NV_LATE || BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + default n + help + Instead of writing back MRC_CACHE training data back to the + MRC_CACHE right away, stash the data into cbmem. This data + will be written back later to MRC_CACHE. This is selected + for platforms which either do not support writes to SPI + flash in early stages + (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) or the platforms + that need to write back the MRC data in late ramstage boot + states (MRC_WRITE_NV_LATE). + endif # CACHE_MRC_SETTINGS diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3a005db357..a083655a2f 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -109,41 +109,6 @@ static const struct cache_region *lookup_region_type(int type) return NULL; } -int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size) -{ - const struct cache_region *cr; - size_t cbmem_size; - struct mrc_metadata *md; - - cr = lookup_region_type(type); - if (cr == NULL) { - printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n", - type); - return -1; - } - - cbmem_size = sizeof(*md) + size; - - md = cbmem_add(cr->cbmem_id, cbmem_size); - - if (md == NULL) { - printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", - cr->name); - return -1; - } - - memset(md, 0, sizeof(*md)); - md->signature = MRC_DATA_SIGNATURE; - md->data_size = size; - md->version = version; - md->data_checksum = compute_ip_checksum(data, size); - md->header_checksum = compute_ip_checksum(md, sizeof(*md)); - memcpy(&md[1], data, size); - - return 0; -} - static const struct cache_region *lookup_region(struct region *r, int type) { const struct cache_region *cr; @@ -152,7 +117,7 @@ static const struct cache_region *lookup_region(struct region *r, int type) if (cr == NULL) { printk(BIOS_ERR, "MRC: failed to locate region type %d.\n", - type); + type); return NULL; } @@ -204,23 +169,16 @@ static int mrc_header_valid(struct region_device *rdev, struct mrc_metadata *md) return 0; } -static int mrc_data_valid(const struct region_device *rdev, - const struct mrc_metadata *md) +static int mrc_data_valid(const struct mrc_metadata *md, + void *data, size_t data_size) { - void *data; uint16_t checksum; - const size_t md_size = sizeof(*md); - const size_t data_size = md->data_size; - data = rdev_mmap(rdev, md_size, data_size); - if (data == NULL) { - printk(BIOS_ERR, "MRC: mmap failure on data verification.\n"); + if (md->data_size != data_size) return -1; - } checksum = compute_ip_checksum(data, data_size); - rdev_munmap(rdev, data); if (md->data_checksum != checksum) { printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", md->data_checksum, checksum); @@ -230,7 +188,7 @@ static int mrc_data_valid(const struct region_device *rdev, return 0; } -static int mrc_cache_latest(const char *name, +static int mrc_cache_get_latest_slot_info(const char *name, const struct region_device *backing_rdev, struct mrc_metadata *md, struct region_file *cache_file, @@ -260,25 +218,19 @@ static int mrc_cache_latest(const char *name, return fail_bad_data ? -1 : 0; } - /* Validate Data */ - if (mrc_data_valid(rdev, md) < 0) { - printk(BIOS_ERR, "MRC: invalid data in '%s'\n", name); - return fail_bad_data ? -1 : 0; - } - return 0; } -int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev) +static int mrc_cache_find_current(int type, uint32_t version, + struct region_device *rdev, + struct mrc_metadata *md) { const struct cache_region *cr; struct region region; struct region_device read_rdev; struct region_file cache_file; - struct mrc_metadata md; size_t data_size; - const size_t md_size = sizeof(md); + const size_t md_size = sizeof(*md); const bool fail_bad_data = true; cr = lookup_region(®ion, type); @@ -289,34 +241,100 @@ int mrc_cache_get_current(int type, uint32_t version, if (boot_device_ro_subregion(®ion, &read_rdev) < 0) return -1; - if (mrc_cache_latest(cr->name, &read_rdev, &md, &cache_file, rdev, - fail_bad_data) < 0) + if (mrc_cache_get_latest_slot_info(cr->name, + &read_rdev, + md, + &cache_file, + rdev, + fail_bad_data) < 0) return -1; - if (version != md.version) { + if (version != md->version) { printk(BIOS_INFO, "MRC: version mismatch: %x vs %x\n", - md.version, version); + md->version, version); return -1; } /* Re-size rdev to only contain the data. i.e. remove metadata. */ - data_size = md.data_size; + data_size = md->data_size; return rdev_chain(rdev, rdev, md_size, data_size); } -static bool mrc_cache_needs_update(const struct region_device *rdev, - const struct cbmem_entry *to_be_updated) +ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer, + size_t buffer_size) { - void *mapping; + struct region_device rdev; + struct mrc_metadata md; + ssize_t data_size; + + if (mrc_cache_find_current(type, version, &rdev, &md) < 0) + return -1; + + data_size = region_device_sz(&rdev); + if (buffer_size < data_size) + return -1; + + if (rdev_readat(&rdev, buffer, 0, data_size) != data_size) + return -1; + + if (mrc_data_valid(&md, buffer, data_size) < 0) + return -1; + + return data_size; +} + +void *mrc_cache_current_mmap_leak(int type, uint32_t version, + size_t *data_size) +{ + struct region_device rdev; + void *data; + size_t region_device_size; + struct mrc_metadata md; + + if (mrc_cache_find_current(type, version, &rdev, &md) < 0) + return NULL; + + region_device_size = region_device_sz(&rdev); + if (data_size) + *data_size = region_device_size; + data = rdev_mmap_full(&rdev); + + if (data == NULL) { + printk(BIOS_INFO, "MRC: mmap failure.\n"); + return NULL; + } + + if (mrc_data_valid(&md, data, region_device_size) < 0) + return NULL; + + return data; +} + +static bool mrc_cache_needs_update(const struct region_device *rdev, + const struct mrc_metadata *new_md, + const void *new_data, size_t new_data_size) +{ + void *mapping, *data_mapping; size_t size = region_device_sz(rdev); bool need_update = false; - if (cbmem_entry_size(to_be_updated) != size) + if (new_data_size != size) return true; mapping = rdev_mmap_full(rdev); + if (mapping == NULL) { + printk(BIOS_ERR, "MRC: cannot mmap existing cache.\n"); + return true; + } + data_mapping = mapping + sizeof(struct mrc_metadata); - if (memcmp(cbmem_entry_start(to_be_updated), mapping, size)) + /* we need to compare the md and the data separately */ + /* check the mrc_metadata */ + if (memcmp(new_md, mapping, sizeof(struct mrc_metadata))) + need_update = true; + + /* check the data */ + if (!need_update && memcmp(new_data, data_mapping, new_data_size)) need_update = true; rdev_munmap(rdev, mapping); @@ -351,7 +369,10 @@ static void log_event_cache_update(uint8_t slot, enum result res) * read and write. The read assumes a memory-mapped boot device that can be used * to quickly locate and compare the up-to-date data. However, when an update * is required it uses the writeable region access to perform the update. */ -static void update_mrc_cache_by_type(int type) +static void update_mrc_cache_by_type(int type, + struct mrc_metadata *new_md, + const void *new_data, + size_t new_data_size) { const struct cache_region *cr; struct region region; @@ -359,7 +380,6 @@ static void update_mrc_cache_by_type(int type) struct region_device write_rdev; struct region_file cache_file; struct mrc_metadata md; - const struct cbmem_entry *to_be_updated; struct incoherent_rdev backing_irdev; const struct region_device *backing_rdev; struct region_device latest_rdev; @@ -370,13 +390,6 @@ static void update_mrc_cache_by_type(int type) if (cr == NULL) return; - to_be_updated = cbmem_entry_find(cr->cbmem_id); - if (to_be_updated == NULL) { - printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", - cr->name); - return; - } - printk(BIOS_DEBUG, "MRC: Checking cached data update for '%s'.\n", cr->name); @@ -392,11 +405,21 @@ static void update_mrc_cache_by_type(int type) if (backing_rdev == NULL) return; - if (mrc_cache_latest(cr->name, backing_rdev, &md, &cache_file, - &latest_rdev, fail_bad_data) < 0) + /* Note that mrc_cache_get_latest_slot_info doesn't check the + * validity of the current slot. If the slot is invalid, + * we'll overwrite it anyway when we update the mrc_cache. + */ + if (mrc_cache_get_latest_slot_info(cr->name, + backing_rdev, + &md, + &cache_file, + &latest_rdev, + fail_bad_data) < 0) + return; - if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) { + if (!mrc_cache_needs_update(&latest_rdev, + new_md, new_data, new_data_size)) { printk(BIOS_DEBUG, "MRC: '%s' does not need update.\n", cr->name); log_event_cache_update(cr->elog_slot, ALREADY_UPTODATE); return; @@ -404,10 +427,18 @@ static void update_mrc_cache_by_type(int type) printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); - if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) { - printk(BIOS_DEBUG, "MRC: failed to update '%s'.\n", cr->name); + struct update_region_file_entry entries[] = { + [0] = { + .size = sizeof(struct mrc_metadata), + .data = new_md, + }, + [1] = { + .size = new_data_size, + .data = new_data, + }, + }; + if (region_file_update_data_arr(&cache_file, entries, ARRAY_SIZE(entries)) < 0) { + printk(BIOS_ERR, "MRC: failed to update '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); @@ -447,15 +478,13 @@ static int nvm_is_write_protected(void) /* Apply protection to a range of flash */ static int nvm_protect(const struct region *r) { - const struct spi_flash *flash = boot_device_spi_flash(); - if (!CONFIG(MRC_SETTINGS_PROTECT)) return 0; if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; - return spi_flash_ctrlr_protect_region(flash, r, WRITE_PROTECT); + return spi_flash_ctrlr_protect_region(boot_device_spi_flash(), r, WRITE_PROTECT); } /* Protect mrc region with a Protected Range Register */ @@ -467,7 +496,7 @@ static int protect_mrc_cache(const char *name) return 0; if (lookup_region_by_name(name, ®ion) < 0) { - printk(BIOS_ERR, "MRC: Could not find region '%s'\n", name); + printk(BIOS_INFO, "MRC: Could not find region '%s'\n", name); return -1; } @@ -535,12 +564,46 @@ static void invalidate_normal_cache(void) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +static void update_mrc_cache_from_cbmem(int type) { - update_mrc_cache_by_type(MRC_TRAINING_DATA); + const struct cache_region *cr; + struct region region; + const struct cbmem_entry *to_be_updated; - if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) - update_mrc_cache_by_type(MRC_VARIABLE_DATA); + cr = lookup_region(®ion, type); + + if (cr == NULL) { + printk(BIOS_ERR, "MRC: could not find cache_region type %d\n", type); + return; + } + + to_be_updated = cbmem_entry_find(cr->cbmem_id); + + if (to_be_updated == NULL) { + printk(BIOS_INFO, "MRC: No data in cbmem for '%s'.\n", + cr->name); + return; + } + + update_mrc_cache_by_type(type, + /* pointer to mrc_cache entry metadata header */ + cbmem_entry_start(to_be_updated), + /* pointer to start of mrc_cache entry data */ + cbmem_entry_start(to_be_updated) + + sizeof(struct mrc_metadata), + /* size of just data portion of the entry */ + cbmem_entry_size(to_be_updated) - + sizeof(struct mrc_metadata)); +} + +static void finalize_mrc_cache(void *unused) +{ + if (CONFIG(MRC_STASH_TO_CBMEM)) { + update_mrc_cache_from_cbmem(MRC_TRAINING_DATA); + + if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) + update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA); + } if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) invalidate_normal_cache(); @@ -548,13 +611,57 @@ static void update_mrc_cache(void *unused) protect_mrc_region(); } +int mrc_cache_stash_data(int type, uint32_t version, const void *data, + size_t size) +{ + const struct cache_region *cr; + + cr = lookup_region_type(type); + if (cr == NULL) { + printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n", + type); + return -1; + } + + struct mrc_metadata md = { + .signature = MRC_DATA_SIGNATURE, + .data_size = size, + .version = version, + .data_checksum = compute_ip_checksum(data, size), + }; + md.header_checksum = + compute_ip_checksum(&md, sizeof(struct mrc_metadata)); + + if (CONFIG(MRC_STASH_TO_CBMEM)) { + /* Store data in cbmem for use in ramstage */ + struct mrc_metadata *cbmem_md; + size_t cbmem_size; + cbmem_size = sizeof(*cbmem_md) + size; + + cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size); + + if (cbmem_md == NULL) { + printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", + cr->name); + return -1; + } + + memcpy(cbmem_md, &md, sizeof(*cbmem_md)); + /* cbmem_md + 1 is the pointer to the mrc_cache data */ + memcpy(cbmem_md + 1, data, size); + } else { + /* Otherwise store to mrc_cache right away */ + update_mrc_cache_by_type(type, &md, data, size); + } + return 0; +} + /* * Ensures MRC training data is stored into SPI after PCI enumeration is done. * Some implementations may require this to be later than others. */ - #if CONFIG(MRC_WRITE_NV_LATE) -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL); #else -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, finalize_mrc_cache, NULL); #endif diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 620dab952e..971f31dd83 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -36,7 +36,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #include "ns8390.h" - #define ETH_ALEN 6 /* Size of Ethernet address */ #define ETH_HLEN 14 /* Size of ethernet header */ #define ETH_ZLEN 60 /* Minimum packet */ @@ -48,7 +47,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #define TX_START 64 #define RX_START (64 + D8390_TXBUF_SIZE) - static unsigned int get_count(unsigned int eth_nic_base) { unsigned int ret; @@ -146,7 +144,6 @@ static void str2mac(const char *str, unsigned char *mac) } while (c != '\0'); } - static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) { unsigned short chksum; diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index b32ac707ad..914c9aed9c 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -77,7 +77,6 @@ unsigned long calibrate_tsc_with_pit(void) if (end.hi) goto bad_ctc; - /* Error: ECPUTOOSLOW */ if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc; diff --git a/src/drivers/pc80/pc/isa-dma.c b/src/drivers/pc80/pc/isa-dma.c index dbb2362836..5c3fe67920 100644 --- a/src/drivers/pc80/pc/isa-dma.c +++ b/src/drivers/pc80/pc/isa-dma.c @@ -32,7 +32,6 @@ #define DMA_AUTOINIT 0x10 - void isa_dma_init(void) { /* slave at 0x00 - 0x0f */ diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index ced544e178..9e457f7166 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -5,7 +5,6 @@ #define SPEAKER_PIT_FREQUENCY 0x1234dd - enum { PIT_COUNTER_0 = 0x40, PIT_COUNTER_1 = 0x41, @@ -14,7 +13,6 @@ enum { PIT_SPEAKER_PORT = 0x61, }; - enum { PIT_SPK_TMR2 = 0x01, PIT_SPK_DATA = 0x02, @@ -44,13 +42,11 @@ enum { PIT_CTRL_HARDSTROBE = 0x0a, - PIT_CTRL_COUNT_MASK = 0x01, PIT_CTRL_COUNT_BINARY = 0x00, PIT_CTRL_COUNT_BCD = 0x01 }; - static void make_tone(uint16_t freq_count, unsigned int duration) { diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index c0dd1275d8..5f6055e872 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -1,29 +1,14 @@ ifeq ($(CONFIG_ARCH_X86),y) -bootblock-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -verstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c +all-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -bootblock-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +all-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -bootblock-$(CONFIG_USE_OPTION_TABLE) += option.c -verstage-$(CONFIG_USE_OPTION_TABLE) += option.c -postcar-$(CONFIG_USE_OPTION_TABLE) += option.c -romstage-$(CONFIG_USE_OPTION_TABLE) += option.c -ramstage-$(CONFIG_USE_OPTION_TABLE) += option.c -smm-$(CONFIG_USE_OPTION_TABLE) += option.c +all-$(CONFIG_USE_OPTION_TABLE) += option.c +smm-$(CONFIG_USE_OPTION_TABLE) += option.c -bootblock-$(CONFIG_CMOS_POST) += post.c -verstage-$(CONFIG_CMOS_POST) += post.c -postcar-$(CONFIG_CMOS_POST) += post.c -romstage-$(CONFIG_CMOS_POST) += post.c -ramstage-$(CONFIG_CMOS_POST) += post.c +all-$(CONFIG_CMOS_POST) += post.c ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3227510941..21d3c009fa 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -144,7 +143,7 @@ static void cmos_init_vbnv(bool invalid) uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE]; /* __cmos_init() will clear vbnv contents when a known rtc failure - occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may + occurred with !CONFIG(USE_OPTION_TABLE). However, __cmos_init() may clear vbnv data for other internal reasons. For that, always back up the vbnv contents and conditionally save them when __cmos_init() indicates CMOS was cleared. */ diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index fbcf387f63..550a6027c0 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 0a73cb3232..d17c025b1f 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -228,7 +228,6 @@ int cmos_lb_cks_valid(void) return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } - void sanitize_cmos(void) { const unsigned char *cmos_default; diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4fce..13a73b8df2 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,20 @@ config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP Provide common implementation of the RW boot device that doesn't provide mmap() operations. +config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For platforms who do not allow writes to SPI flash in early + stages like romstage. Not selecting this config will result + in the auto-selection of + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform. + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help @@ -152,5 +164,5 @@ config SPI_FLASH_HAS_VOLATILE_GROUP endif # SPI_FLASH -config HAVE_SPI_CONSOLE_SUPPORT +config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT def_bool n diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 6dbc43a6d7..56ee44bd47 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,7 +2,7 @@ subdirs-y += tpm -ifeq ($(CONFIG_SPI_CONSOLE),y) +ifeq ($(CONFIG_EM100PRO_SPI_CONSOLE),y) ramstage-y += spiconsole.c smm-y += spiconsole.c endif diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 372575e2d9..f2610a181d 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -373,7 +373,6 @@ static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_i [1] = id[1] & vi->match_id_mask[1], }; - for (i = 0; i < vi->nr_part_ids; i++) { const struct spi_flash_part_id *part = &vi->ids[i]; @@ -666,7 +665,6 @@ void lb_spi_flash(struct lb_header *header) } } - int spi_flash_ctrlr_protect_region(const struct spi_flash *flash, const struct region *region, const enum ctrlr_prot_type type) diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index 5d0a71b4f5..a670111891 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -354,11 +354,12 @@ static int spi_sdcard_do_app_command(const struct spi_sdcard *card, uint32_t *out_register) { /* CMD55 */ - spi_sdcard_do_command(card, APP_CMD, 0, NULL); + if (spi_sdcard_do_command(card, APP_CMD, 0, NULL)) + return -1; + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); } - size_t spi_sdcard_size(const struct spi_sdcard *card) { int wait; diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 6849ea7bf0..2554cf717c 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -75,7 +75,6 @@ int tis_init(void) return 0; } - int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) { diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 24851d1c86..d65decda12 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -31,6 +31,15 @@ #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) +#define CR50_BOARD_CFG (TPM_LOCALITY_0_SPI_BASE + 0xfe0) + +#define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U +#define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU + +#define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U +#define CR50_BOARD_CFG_VALUE \ + (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ + ? CR50_BOARD_CFG_100US_READY_PULSE : 0) #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ @@ -39,12 +48,13 @@ static struct spi_slave spi_slave; /* Cached TPM device identification. */ static struct tpm2_info tpm_info; +static struct cr50_firmware_version cr50_firmware_version; /* - * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of + * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of * debug traces. Right now it is either 0 or 1. */ -static const int debug_level_ = CONFIG_DEBUG_TPM; +static const int debug_level_ = CONFIG(DEBUG_TPM); /* * SPI frame header for TPM transactions is 4 bytes in size, it is described @@ -338,7 +348,7 @@ static int read_tpm_sts(uint32_t *status) return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); } -static int write_tpm_sts(uint32_t status) +static int __must_check write_tpm_sts(uint32_t status) { return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); } @@ -421,12 +431,109 @@ static int tpm2_claim_locality(void) return 0; } +static int cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) +{ + int epoch, major, minor; + + char *number = strstr(version_str, " RW_A:"); + if (!number) + number = strstr(version_str, " RW_B:"); + if (!number) + return -1; + number += 6; /* Skip past the colon. */ + + epoch = skip_atoi(&number); + if (*number++ != '.') + return -2; + major = skip_atoi(&number); + if (*number++ != '.') + return -2; + minor = skip_atoi(&number); + + ver->epoch = epoch; + ver->major = major; + ver->minor = minor; + return 0; +} + +static int cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) +{ + /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 + * and onwards. */ + if (version->epoch > 0 || version->major >= 7 + || (version->major >= 5 && version->minor >= 5)) + return 1; + printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", + version->epoch, version->major, version->minor); + return 0; +} + +/** + * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. + */ +static void cr50_set_board_cfg(void) +{ + uint32_t board_cfg_value; + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return; + /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ + if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return; + } + if ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { + printk(BIOS_INFO, + "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + return; + } + if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) { + /* The high bit is set, meaning that the Cr50 is already locked on a particular + * value for the register, but not the one we wanted. */ + printk(BIOS_ERR, + "ERROR: Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + return; + } + printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", + board_cfg_value, CR50_BOARD_CFG_VALUE); + board_cfg_value = CR50_BOARD_CFG_VALUE; + if (!tpm2_write_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) + printk(BIOS_INFO, "Error writing to cr50\n"); +} + +/* + * Expose method to read the CR50_BOARD_CFG register, will return zero if + * register not supported by Cr50 firmware. + */ +static uint32_t cr50_get_board_cfg(void) +{ + uint32_t board_cfg_value; + if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + return 0; + if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { + printk(BIOS_INFO, "Error reading from cr50\n"); + return 0; + } + return board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK; +} + +bool cr50_is_long_interrupt_pulse_enabled(void) +{ + return cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE; +} + /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { 0x00281ae0, /* H1 based Cr50 security chip. */ 0x0000104a /* ST33HTPH2E32 */ }; +static int first_access_this_boot(void) +{ + return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); +} + int tpm2_init(struct spi_slave *spi_if) { uint32_t did_vid, status; @@ -471,7 +578,7 @@ int tpm2_init(struct spi_slave *spi_if) printk(BIOS_INFO, " done!\n"); // FIXME: Move this to tpm_setup() - if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT)) + if (first_access_this_boot()) /* * Claim locality 0, do it only during the first * initialization after reset. @@ -502,18 +609,10 @@ int tpm2_init(struct spi_slave *spi_if) tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); /* Let's report device FW version if available. */ - if (tpm_info.vendor_id == 0x1ae0) { + if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - size_t chunk_size; - /* - * let's read 50 bytes at a time; leave room for the trailing - * zero. - */ - char vstr[51]; - - chunk_size = sizeof(vstr) - 1; - - printk(BIOS_INFO, "Firmware version: "); + size_t chunk_size = 50; + char version_str[301]; /* * Does not really matter what's written, this just makes sure @@ -521,20 +620,28 @@ int tpm2_init(struct spi_slave *spi_if) */ tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); - /* Print it out in sizeof(vstr) - 1 byte chunks. */ - vstr[chunk_size] = 0; + /* + * Read chunk_size bytes at a time, last chunk will be zero padded. + */ do { - tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); - printk(BIOS_INFO, "%s", vstr); - - /* - * While string is not over, and is no longer than 300 - * characters. - */ - } while (vstr[chunk_size - 1] && - (chunk_count++ < (300 / chunk_size))); - - printk(BIOS_INFO, "\n"); + tpm2_read_reg(TPM_FW_VER, + version_str + chunk_count * chunk_size, + chunk_size); + if (!version_str[++chunk_count * chunk_size - 1]) + /* Zero padding detected: end of string. */ + break; + /* Check if there is enough room for reading one more chunk. */ + } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); + version_str[chunk_count * chunk_size] = '\0'; + printk(BIOS_INFO, "Firmware version: %s\n", version_str); + if (cr50_parse_fw_version(version_str, &cr50_firmware_version)) { + printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); + return -1; + } + if (CR50_BOARD_CFG_VALUE) { + if (first_access_this_boot()) + cr50_set_board_cfg(); + } } return 0; } @@ -581,9 +688,9 @@ union fifo_transfer_buffer { * Transfer requested number of bytes to or from TPM FIFO, accounting for the * current burst count value. */ -static void fifo_transfer(size_t transfer_size, - union fifo_transfer_buffer buffer, - enum fifo_transfer_direction direction) +static int __must_check fifo_transfer(size_t transfer_size, + union fifo_transfer_buffer buffer, + enum fifo_transfer_direction direction) { size_t transaction_size; size_t burst_count; @@ -604,18 +711,23 @@ static void fifo_transfer(size_t transfer_size, */ transaction_size = MIN(transaction_size, 64); - if (direction == fifo_receive) - tpm2_read_reg(TPM_DATA_FIFO_REG, - buffer.rx_buffer + handled_so_far, - transaction_size); - else - tpm2_write_reg(TPM_DATA_FIFO_REG, - buffer.tx_buffer + handled_so_far, - transaction_size); + if (direction == fifo_receive) { + if (!tpm2_read_reg(TPM_DATA_FIFO_REG, + buffer.rx_buffer + handled_so_far, + transaction_size)) + return 0; + } else { + if (!tpm2_write_reg(TPM_DATA_FIFO_REG, + buffer.tx_buffer + handled_so_far, + transaction_size)) + return 0; + } handled_so_far += transaction_size; } while (handled_so_far != transfer_size); + + return 1; } size_t tpm2_process_command(const void *tpm2_command, size_t command_size, @@ -648,7 +760,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, } /* Let the TPM know that the command is coming. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } /* * TPM commands and responses written to and read from the FIFO @@ -662,10 +777,17 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, * burst count or the maximum PDU size, whatever is smaller. */ fifo_buffer.tx_buffer = cmd_body; - fifo_transfer(command_size, fifo_buffer, fifo_transmit); + if (!fifo_transfer(command_size, fifo_buffer, fifo_transmit)) { + printk(BIOS_ERR, "fifo_transfer %zd command bytes failed\n", + command_size); + return 0; + } /* Now tell the TPM it can start processing the command. */ - write_tpm_sts(TPM_STS_GO); + if (!write_tpm_sts(TPM_STS_GO)) { + printk(BIOS_ERR, "TPM_STS_GO failed\n"); + return 0; + } /* Now wait for it to report that the response is ready. */ expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; @@ -708,7 +830,11 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, */ bytes_to_go = payload_size - 1 - HEADER_SIZE; fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; - fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); + if (!fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive)) { + printk(BIOS_ERR, "fifo_transfer %zd receive bytes failed\n", + bytes_to_go); + return 0; + } /* Verify that there is still data to read. */ read_tpm_sts(&status); @@ -733,7 +859,15 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, } /* Move the TPM back to idle state. */ - write_tpm_sts(TPM_STS_COMMAND_READY); + if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { + printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); + return 0; + } return payload_size; } + +void cr50_get_firmware_version(struct cr50_firmware_version *version) +{ + memcpy(version, &cr50_firmware_version, sizeof(*version)); +} diff --git a/src/drivers/spi/tpm/tpm.h b/src/drivers/spi/tpm/tpm.h index be98ed05df..f48943e020 100644 --- a/src/drivers/spi/tpm/tpm.h +++ b/src/drivers/spi/tpm/tpm.h @@ -16,6 +16,13 @@ struct tpm2_info { uint16_t revision; }; +/* Structure describing the elements of Cr50 firmware version. */ +struct cr50_firmware_version { + int epoch; + int major; + int minor; +}; + /* * Initialize a TPM2 device: read its id, claim locality of zero, verify that * this indeed is a TPM2 device. Use the passed in handle to access the right @@ -25,7 +32,6 @@ struct tpm2_info { */ int tpm2_init(struct spi_slave *spi_if); - /* * Each command processing consists of sending the command to the TPM, by * writing it into the FIFO register, then polling the status register until @@ -41,4 +47,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size, /* Get information about previously initialized TPM device. */ void tpm2_get_info(struct tpm2_info *info); +/* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ +bool cr50_is_long_interrupt_pulse_enabled(void); + +/* Get the cr50 firmware version information. */ +void cr50_get_firmware_version(struct cr50_firmware_version *version); + #endif /* ! __COREBOOT_SRC_DRIVERS_SPI_TPM_TPM_H */ diff --git a/src/drivers/ti/sn65dsi86bridge/Kconfig b/src/drivers/ti/sn65dsi86bridge/Kconfig new file mode 100644 index 0000000000..b7abb34231 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Kconfig @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_TI_SN65DSI86BRIDGE + bool + default n + help + TI SN65DSI86 eDP bridge driver diff --git a/src/drivers/ti/sn65dsi86bridge/Makefile.inc b/src/drivers/ti/sn65dsi86bridge/Makefile.inc new file mode 100644 index 0000000000..b146fe363c --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_TI_SN65DSI86BRIDGE) += sn65dsi86bridge.c diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c new file mode 100644 index 0000000000..5a6eb496ea --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sn65dsi86bridge.h" + +#define BRIDGE_GETHIGHERBYTE(x) (uint8_t)((x & 0xff00) >> 8) +#define BRIDGE_GETLOWERBYTE(x) (uint8_t)((x & 0x00ff)) + +/* fudge factor required to account for 8b/10b encoding */ +#define DP_CLK_FUDGE_NUM 10 +#define DP_CLK_FUDGE_DEN 8 + +/* DPCD */ +#define DP_BRIDGE_DPCD_REV 0x700 +#define DP_BRIDGE_11 0x00 +#define DP_BRIDGE_12 0x01 +#define DP_BRIDGE_13 0x02 +#define DP_BRIDGE_14 0x03 +#define DP_BRIDGE_CONFIGURATION_SET 0x10a +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LANE_COUNT 0x002 +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ +#define DP_LANE_COUNT_MASK 0xf + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_1_62 0x06 +#define DP_LINK_BW_2_7 0x0a +#define DP_LINK_BW_5_4 0x14 + +#define AUX_CMD_SEND 0x1 +#define MIN_DSI_CLK_FREQ_MHZ 40 +#define MAX_DSI_CLK_FREQ_MHZ 750 + +enum bridge_regs { + SN_DPPLL_SRC_REG = 0x0A, + SN_PLL_ENABLE_REG = 0x0D, + SN_DSI_LANES_REG = 0x10, + SN_DSIA_CLK_FREQ_REG = 0x12, + SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG = 0x20, + SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG = 0x21, + SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG = 0x24, + SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG = 0x25, + SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG = 0x2C, + SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG = 0x2D, + SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG = 0x30, + SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG = 0x31, + SN_CHA_HORIZONTAL_BACK_PORCH_REG = 0x34, + SN_CHA_VERTICAL_BACK_PORCH_REG = 0x36, + SN_CHA_HORIZONTAL_FRONT_PORCH_REG = 0x38, + SN_CHA_VERTICAL_FRONT_PORCH_REG = 0x3A, + SN_COLOR_BAR_REG = 0x3C, + SN_ENH_FRAME_REG = 0x5A, + SN_DATA_FORMAT_REG = 0x5B, + SN_HPD_DISABLE_REG = 0x5C, + SN_I2C_CLAIM_ADDR_EN1 = 0x60, + SN_AUX_WDATA_REG_0 = 0x64, + SN_AUX_WDATA_REG_1 = 0x65, + SN_AUX_WDATA_REG_2 = 0x66, + SN_AUX_WDATA_REG_3 = 0x67, + SN_AUX_WDATA_REG_4 = 0x68, + SN_AUX_WDATA_REG_5 = 0x69, + SN_AUX_WDATA_REG_6 = 0x6A, + SN_AUX_WDATA_REG_7 = 0x6B, + SN_AUX_WDATA_REG_8 = 0x6C, + SN_AUX_WDATA_REG_9 = 0x6D, + SN_AUX_WDATA_REG_10 = 0x6E, + SN_AUX_WDATA_REG_11 = 0x6F, + SN_AUX_WDATA_REG_12 = 0x70, + SN_AUX_WDATA_REG_13 = 0x71, + SN_AUX_WDATA_REG_14 = 0x72, + SN_AUX_WDATA_REG_15 = 0x73, + SN_AUX_ADDR_19_16_REG = 0x74, + SN_AUX_ADDR_15_8_REG = 0x75, + SN_AUX_ADDR_7_0_REG = 0x76, + SN_AUX_LENGTH_REG = 0x77, + SN_AUX_CMD_REG = 0x78, + SN_AUX_RDATA_REG_0 = 0x79, + SN_AUX_RDATA_REG_1 = 0x7A, + SN_AUX_RDATA_REG_2 = 0x7B, + SN_AUX_RDATA_REG_3 = 0x7C, + SN_AUX_RDATA_REG_4 = 0x7D, + SN_AUX_RDATA_REG_5 = 0x7E, + SN_AUX_RDATA_REG_6 = 0x7F, + SN_AUX_RDATA_REG_7 = 0x80, + SN_AUX_RDATA_REG_8 = 0x81, + SN_AUX_RDATA_REG_9 = 0x82, + SN_AUX_RDATA_REG_10 = 0x83, + SN_AUX_RDATA_REG_11 = 0x84, + SN_AUX_RDATA_REG_12 = 0x85, + SN_AUX_RDATA_REG_13 = 0x86, + SN_AUX_RDATA_REG_14 = 0x87, + SN_AUX_RDATA_REG_15 = 0x88, + SN_SSC_CONFIG_REG = 0x93, + SN_DATARATE_CONFIG_REG = 0x94, + SN_ML_TX_MODE_REG = 0x96, + SN_AUX_CMD_STATUS_REG = 0xF4, +}; + +enum { + HPD_ENABLE = 0x0, + HPD_DISABLE = 0x1, +}; + +enum { + SOT_ERR_TOL_DSI = 0x0, + CHB_DSI_LANES = 0x1, + CHA_DSI_LANES = 0x2, + DSI_CHANNEL_MODE = 0x3, + LEFT_RIGHT_PIXELS = 0x4, +}; + +enum vstream_config { + VSTREAM_DISABLE = 0, + VSTREAM_ENABLE = 1, +}; + +enum i2c_over_aux { + I2C_OVER_AUX_WRITE_MOT_0 = 0x0, + I2C_OVER_AUX_READ_MOT_0 = 0x1, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4, + I2C_OVER_AUX_WRITE_MOT_1 = 0x5, + I2C_OVER_AUX_READ_MOT_1 = 0x6, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7, + NATIVE_AUX_WRITE = 0x8, + NATIVE_AUX_READ = 0x9, +}; + +enum ml_tx_mode { + MAIN_LINK_OFF = 0x0, + NORMAL_MODE = 0x1, + TPS1 = 0x2, + TPS2 = 0x3, + TPS3 = 0x4, + PRBS7 = 0x5, + HBR2_COMPLIANCE_EYE_PATTERN = 0x6, + SYMBOL_ERR_RATE_MEASUREMENT_PATTERN = 0x7, + CUTSOM_PATTERN = 0x8, + FAST_LINK_TRAINING = 0x9, + SEMI_AUTO_LINK_TRAINING = 0xa, + REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, +}; + +enum dpcd_request { + DPCD_READ = 0x0, + DPCD_WRITE = 0x1, +}; + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +/* + * LUT index corresponds to register value and LUT values corresponds + * to dp data rate supported by the bridge in Mbps unit. + */ +static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = { + 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 +}; + +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) +{ + int ret; + u8 edid[EDID_LENGTH * 2]; + int edid_size = EDID_LENGTH; + + /* Send I2C command to claim EDID I2c slave */ + i2c_writeb(bus, chip, SN_I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1); + + /* read EDID */ + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); + return CB_ERR; + } + + if (edid[EDID_EXTENSION_FLAG]) { + edid_size += EDID_LENGTH; + ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH, + &edid[EDID_LENGTH], EDID_LENGTH); + if (ret != 0) { + printk(BIOS_ERR, "Failed to read EDID ext block.\n"); + return CB_ERR; + } + } + + if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { + printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static void sn65dsi86_bridge_dpcd_request(uint8_t bus, + uint8_t chip, + unsigned int dpcd_reg, + unsigned int len, + enum dpcd_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + + while (len) { + length = MIN(len, 16); + + i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF); + i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF); + i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */ + if (request == DPCD_WRITE) { + reg = SN_AUX_WDATA_REG_0; + for (i = 0; i < length; i++) + i2c_writeb(bus, chip, reg++, *data++); + + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4)); + } else { + i2c_writeb(bus, chip, + SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4)); + if (!wait_ms(100, + !i2c_readb(bus, chip, SN_AUX_CMD_REG, + &buf) && !(buf & AUX_CMD_SEND))) { + printk(BIOS_ERR, "ERROR: aux command send failed\n"); + } + + reg = SN_AUX_RDATA_REG_0; + for (i = 0; i < length; i++) { + i2c_readb(bus, chip, reg++, &buf); + *data++ = buf; + } + } + + len -= length; + } +} + +static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[]) +{ + unsigned int rate_per_200khz; + uint8_t dpcd_val; + int i, j; + + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); + if (dpcd_val >= DP_BRIDGE_14) { + /* eDP 1.4 devices must provide a custom table */ + uint8_t sink_rates[DP_MAX_SUPPORTED_RATES * 2]; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, + sizeof(sink_rates), + DPCD_READ, sink_rates); + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + rate_per_200khz = le16_to_cpu(sink_rates[i]); + + if (!rate_per_200khz) + break; + + for (j = 0; + j < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + j++) { + if (sn65dsi86_bridge_dp_rate_lut[j] * (MHz / KHz) == + rate_per_200khz * 200) + rate_valid[j] = true; + } + } + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); i++) { + if (rate_valid[i]) + return; + } + + printk(BIOS_ERR, "No matching eDP rates in table; falling back\n"); + } + + /* On older versions best we can do is use DP_MAX_LINK_RATE */ + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + + switch (dpcd_val) { + default: + printk(BIOS_ERR, + "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); + /* fall through */ + case DP_LINK_BW_5_4: + rate_valid[7] = 1; + /* fall through */ + case DP_LINK_BW_2_7: + rate_valid[4] = 1; + /* fall through */ + case DP_LINK_BW_1_62: + rate_valid[1] = 1; + break; + } +} + +static void sn65dsi86_bridge_set_dsi_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, + uint32_t num_of_lanes, uint32_t bpp) +{ + uint64_t pixel_clk_hz; + uint64_t stream_bit_rate_mhz; + uint64_t min_req_dsi_clk; + + pixel_clk_hz = edid->mode.pixel_clock * KHz; + stream_bit_rate_mhz = (pixel_clk_hz * bpp) / MHz; + + /* For TI the clock frequencies are half the bit rates */ + min_req_dsi_clk = stream_bit_rate_mhz / (num_of_lanes * 2); + + /* for each increment in val, frequency increases by 5MHz */ + min_req_dsi_clk = MAX(MIN_DSI_CLK_FREQ_MHZ, + MIN(MAX_DSI_CLK_FREQ_MHZ, min_req_dsi_clk)) / 5; + i2c_writeb(bus, chip, SN_DSIA_CLK_FREQ_REG, min_req_dsi_clk); +} + +static void sn65dsi86_bridge_set_dp_clock_range(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lanes) +{ + uint64_t stream_bit_rate_khz; + bool rate_valid[ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)] = { }; + uint64_t dp_rate_mhz; + int dp_rate_idx, i; + + stream_bit_rate_khz = edid->mode.pixel_clock * 18; + + /* Calculate minimum DP data rate, taking 80% as per DP spec */ + dp_rate_mhz = DIV_ROUND_UP(stream_bit_rate_khz * DP_CLK_FUDGE_NUM, + KHz * num_of_lanes * DP_CLK_FUDGE_DEN); + + for (i = 0; i < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut) - 1; i++) + if (sn65dsi86_bridge_dp_rate_lut[i] > dp_rate_mhz) + break; + + sn65dsi86_bridge_valid_dp_rates(bus, chip, rate_valid); + + /* Train until we run out of rates */ + for (dp_rate_idx = i; + dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut); + dp_rate_idx++) + if (rate_valid[dp_rate_idx]) + break; + + if (dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)) + i2c_write_field(bus, chip, SN_DATARATE_CONFIG_REG, dp_rate_idx, 8, 5); + else + printk(BIOS_ERR, "ERROR: valid dp rate not found"); +} + +static void sn65dsi86_bridge_set_bridge_active_timing(uint8_t bus, + uint8_t chip, + struct edid *edid) +{ + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.ha)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.va)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.hspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, + BRIDGE_GETLOWERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, + BRIDGE_GETHIGHERBYTE(edid->mode.vspw)); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_BACK_PORCH_REG, + edid->mode.hbl - edid->mode.hso - edid->mode.hspw); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_BACK_PORCH_REG, + edid->mode.vbl - edid->mode.vso - edid->mode.vspw); + i2c_writeb(bus, chip, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, + edid->mode.hso); + i2c_writeb(bus, chip, SN_CHA_VERTICAL_FRONT_PORCH_REG, + edid->mode.vso); +} + +static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip) +{ + uint8_t buf; + + /* enable pll lock */ + i2c_writeb(bus, chip, SN_PLL_ENABLE_REG, 0x1); + + if (!wait_ms(500, + !(i2c_readb(bus, chip, SN_DPPLL_SRC_REG, &buf)) && + (buf & BIT(7)))) { + printk(BIOS_ERR, "ERROR: PLL lock failure\n"); + } + + /* + * The SN65DSI86 only supports ASSR Display Authentication method and + * this method is enabled by default. An eDP panel must support this + * authentication method. We need to enable this method in the eDP panel + * at DisplayPort address 0x0010A prior to link training. + */ + buf = 0x1; + sn65dsi86_bridge_dpcd_request(bus, chip, + DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); + + int i; /* Kernel driver suggests to retry this up to 10 times if it fails. */ + for (i = 0; i < 10; i++) { + i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, SEMI_AUTO_LINK_TRAINING); + + if (!wait_ms(500, !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && + (buf == NORMAL_MODE || buf == MAIN_LINK_OFF))) { + printk(BIOS_ERR, "ERROR: unexpected link training state: %#x\n", buf); + return; + } + if (buf == NORMAL_MODE) + return; + } + + printk(BIOS_ERR, "ERROR: Link training failed 10 times\n"); +} + +static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable) +{ + if (enable) + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1, 3); + else + i2c_write_field(bus, chip, SN_ENH_FRAME_REG, VSTREAM_DISABLE, 1, 3); +} + +static int sn65dsi86_bridge_dp_lane_config(uint8_t bus, uint8_t chip) +{ + uint8_t lane_count; + + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count); + lane_count &= DP_LANE_COUNT_MASK; + i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(lane_count, 3), 3, 4); + + return lane_count; +} + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk) +{ + /* disable HPD */ + i2c_write_field(bus, chip, SN_HPD_DISABLE_REG, HPD_DISABLE, 1, 0); + + /* set refclk to 19.2 MHZ */ + i2c_write_field(bus, chip, SN_DPPLL_SRC_REG, ref_clk, 7, 1); +} + +void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lanes, + uint32_t dsi_bpp) +{ + int dp_lanes; + + /* DSI Lanes config */ + i2c_write_field(bus, chip, SN_DSI_LANES_REG, (4 - num_of_lanes), 3, 3); + + /* DP Lane config */ + dp_lanes = sn65dsi86_bridge_dp_lane_config(bus, chip); + + sn65dsi86_bridge_set_dsi_clock_range(bus, chip, edid, num_of_lanes, dsi_bpp); + + sn65dsi86_bridge_set_dp_clock_range(bus, chip, edid, dp_lanes); + + /* Disable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 0); + sn65dsi86_bridge_link_training(bus, chip); + sn65dsi86_bridge_set_bridge_active_timing(bus, chip, edid); + + /* DP BPP config */ + i2c_writeb(bus, chip, SN_DATA_FORMAT_REG, 0x1); + + /* color bar disabled */ + i2c_writeb(bus, chip, SN_COLOR_BAR_REG, 0x5); + + /* Enable vstream */ + sn65dsi86_bridge_assr_config(bus, chip, 1); +} diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h new file mode 100644 index 0000000000..83b940bbb4 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TI_SN65DSI86BRIDGE_H +#define __TI_SN65DSI86BRIDGE_H + +#include + +enum dp_pll_clk_src { + SN65_SEL_12MHZ = 0x0, + SN65_SEL_19MHZ = 0x1, + SN65_SEL_26MHZ = 0x2, + SN65_SEL_27MHZ = 0x3, + SN65_SEL_38MHZ = 0x4, +}; + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk); +void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lines, + uint32_t dsi_bpp); +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out); + +#endif diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index d8a8b9167e..8ba39efc6d 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - struct resource *res = find_resource(dev, 0x10); + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; @@ -26,7 +26,6 @@ static void oxford_oxpcie_enable(struct device *dev) printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); } - static void oxford_oxpcie_set_resources(struct device *dev) { pci_dev_set_resources(dev); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b012c5a77a..ff7d0cfd8a 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -55,9 +55,9 @@ static int oxpcie_uart_active(void) return oxpcie_present; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { - if ((idx >= 0) && (idx < 8) && oxpcie_uart_active()) + if ((idx < 8) && oxpcie_uart_active()) return uart0_base + idx * 0x200; return 0; } diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2b81e76693..0a73d829ad 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -5,11 +5,11 @@ #include #include -void uart_init(int idx) +void uart_init(unsigned int idx) { } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -17,7 +17,7 @@ void uart_tx_byte(int idx, unsigned char data) uart_tx_flush(idx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); @@ -26,7 +26,7 @@ void uart_tx_flush(int idx) ; } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct pl011_uart *regs = uart_platform_baseptr(idx); diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index d4d54c45f4..1f5f0f721b 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef __DRIVERS_UART_PL011_H #define __DRIVERS_UART_PL011_H diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 0c94c6aeaa..31181aa51f 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -45,7 +45,7 @@ static void sifive_uart_init(struct sifive_uart_registers *regs, int div) write32(®s->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0)); } -void uart_init(int idx) +void uart_init(unsigned int idx) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), @@ -58,7 +58,7 @@ static bool uart_can_tx(struct sifive_uart_registers *regs) return !(read32(®s->txdata) & TXDATA_FULL); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); @@ -68,7 +68,7 @@ void uart_tx_byte(int idx, unsigned char data) write32(®s->txdata, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t ip; @@ -79,7 +79,7 @@ void uart_tx_flush(int idx) } while (!(ip & IP_TXWM)); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t rxdata; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 22b79e8b6b..d0841de39c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -77,14 +77,14 @@ static void uart8250_init(unsigned int base_port, unsigned int divisor) static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < ARRAY_SIZE(bases)) return bases[idx]; return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) { unsigned int div; @@ -94,17 +94,17 @@ void uart_init(int idx) } } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { uart8250_tx_flush(uart_platform_base(idx)); } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 8d73272031..1834095014 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -97,7 +97,7 @@ static void uart8250_mem_init(void *base, unsigned int divisor) uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS); } -void uart_init(int idx) +void uart_init(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -109,7 +109,7 @@ void uart_init(int idx) uart8250_mem_init(base, div); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { void *base = uart_platform_baseptr(idx); if (!base) @@ -117,7 +117,7 @@ void uart_tx_byte(int idx, unsigned char data) uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) @@ -125,7 +125,7 @@ unsigned char uart_rx_byte(int idx) return uart8250_mem_rx_byte(base); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_platform_baseptr(idx); if (!base) diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index 5ab85963f6..9635460bdb 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -40,7 +40,6 @@ struct ehci_caps { u8 portroute[8]; /* nibbles for routing - offset 0xC */ } __packed; - /* Section 2.3 Host Controller Operational Registers */ struct ehci_regs { diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 07d87ae6c5..2fbdf3aff9 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -421,8 +421,6 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) return -1; //-ENOTCONN; } - - static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; @@ -436,7 +434,7 @@ static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_d int playtimes = 3; /* Keep all endpoints disabled before any printk() call. */ - memset(info, 0, sizeof (*info)); + memset(info, 0, sizeof(*info)); info->ehci_base = ehci_bar; info->ehci_debug = ehci_bar + offset; info->ep_pipe[0].status |= DBGP_EP_NOT_PRESENT; @@ -549,7 +547,6 @@ try_next_port: } dprintk(BIOS_INFO, "EHCI done waiting for port.\n"); - /* Enable the debug port */ ctrl = read32(&ehci_debug->control); ctrl |= DBGP_CLAIM; @@ -600,7 +597,7 @@ next_debug_port: goto try_next_time; } - return -10; + return ret; } static int dbgp_enabled(void) diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index b7aad23450..c6a89bf5c0 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -17,7 +17,6 @@ #define USB_HUB_C_PORT_CONNECTION 16 #define USB_HUB_C_PORT_RESET 20 - static int hub_port_status(const char *buf, int feature) { return !!(buf[feature>>3] & (1<<(feature&0x7))); @@ -73,7 +72,6 @@ static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned char hub_a if (ret < 0) goto err; - /* Set PORT_RESET, poll for C_PORT_RESET. */ ret = dbgp_control_msg(ehci_debug, hub_addr, USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER, diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index b787127c2f..6a56ca2293 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -24,7 +24,6 @@ __weak enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) return CB_SUCCESS; } - static void xhci_count_ports(void *context, const struct xhci_supported_protocol *data) { struct port_counts *counts = context; @@ -187,11 +186,16 @@ static void xhci_add_devices(const struct device *dev) static void xhci_fill_ssdt(const struct device *dev) { int gpe; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) + return; printk(BIOS_DEBUG, "xHCI SSDT generation\n"); - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_ADR_pci_device(dev); acpigen_write_name_string("_DDN", "xHC - Extensible Host Controller"); diff --git a/src/drivers/wifi/Makefile.inc b/src/drivers/wifi/Makefile.inc deleted file mode 100644 index d37015c7d3..0000000000 --- a/src/drivers/wifi/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_WIFI) += generic.c diff --git a/src/drivers/wifi/Kconfig b/src/drivers/wifi/generic/Kconfig similarity index 94% rename from src/drivers/wifi/Kconfig rename to src/drivers/wifi/generic/Kconfig index 11ac7c1464..049a952e71 100644 --- a/src/drivers/wifi/Kconfig +++ b/src/drivers/wifi/generic/Kconfig @@ -1,4 +1,4 @@ -config DRIVERS_GENERIC_WIFI +config DRIVERS_WIFI_GENERIC bool default n depends on HAVE_ACPI_TABLES @@ -6,7 +6,7 @@ config DRIVERS_GENERIC_WIFI When enabled, add identifiers in ACPI tables that are common to WiFi chipsets from multiple vendors. -if DRIVERS_GENERIC_WIFI +if DRIVERS_WIFI_GENERIC config USE_SAR bool @@ -54,4 +54,4 @@ config DSAR_SET_NUM help There can be up to 3 optional SAR table sets. -endif # DRIVERS_GENERIC_WIFI +endif # DRIVERS_WIFI_GENERIC diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc new file mode 100644 index 0000000000..6240c7146a --- /dev/null +++ b/src/drivers/wifi/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_WIFI_GENERIC) += generic.c diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h new file mode 100644 index 0000000000..02ab504daf --- /dev/null +++ b/src/drivers/wifi/generic/chip.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _WIFI_GENERIC_H_ +#define _WIFI_GENERIC_H_ + +/** + * struct drivers_wifi_generic_config - Data structure to contain generic wifi config + * @wake: Wake pin for ACPI _PRW + */ +struct drivers_wifi_generic_config { + unsigned int wake; +}; + +/** + * wifi_generic_fill_ssdt() - Fill ACPI SSDT table for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * @config: Generic wifi config required to fill ACPI SSDT table. + * + * This function implements common device operation to help fill ACPI SSDT + * table for WiFi controller. + */ +void wifi_generic_fill_ssdt(const struct device *dev, + const struct drivers_wifi_generic_config *config); + +/** + * wifi_generic_acpi_name() - Get ACPI name for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * + * This function implements common device operation to get the ACPI name for + * WiFi controller. + * + * Return: string representing the ACPI name for WiFi controller. + */ +const char *wifi_generic_acpi_name(const struct device *dev); + +#endif /* _GENERIC_WIFI_H_ */ diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic/generic.c similarity index 85% rename from src/drivers/wifi/generic.c rename to src/drivers/wifi/generic/generic.c index 8858fab097..0705731e58 100644 --- a/src/drivers/wifi/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -4,11 +4,13 @@ #include #include #include +#include #include +#include #include #include #include -#include "generic_wifi.h" +#include "chip.h" /* WRDS Spec Revision */ #define WRDS_REVISION 0x0 @@ -105,7 +107,6 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); acpigen_pop_len(); - if (!CONFIG(GEO_SAR_ENABLE)) return; @@ -159,8 +160,8 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); } -void generic_wifi_fill_ssdt(const struct device *dev, - const struct generic_wifi_config *config) +void wifi_generic_fill_ssdt(const struct device *dev, + const struct drivers_wifi_generic_config *config) { const char *path; u32 address; @@ -188,7 +189,7 @@ void generic_wifi_fill_ssdt(const struct device *dev, /* Wake capabilities */ if (config) - acpigen_write_PRW(config->wake, config->maxsleep); + acpigen_write_PRW(config->wake, ACPI_S3); /* Fill regulatory domain structure */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) { @@ -222,7 +223,7 @@ void generic_wifi_fill_ssdt(const struct device *dev, dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); } -const char *generic_wifi_acpi_name(const struct device *dev) +const char *wifi_generic_acpi_name(const struct device *dev) { static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; @@ -231,3 +232,39 @@ const char *generic_wifi_acpi_name(const struct device *dev) (dev_path_encode(dev) & 0xff)); return wifi_acpi_name; } + +static void wifi_generic_fill_ssdt_generator(const struct device *dev) +{ + wifi_generic_fill_ssdt(dev, dev->chip_info); +} + +static void wifi_pci_dev_init(struct device *dev) +{ + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); +} + +struct device_operations wifi_generic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = wifi_pci_dev_init, + .ops_pci = &pci_dev_ops_pci, + .acpi_name = wifi_generic_acpi_name, + .acpi_fill_ssdt = wifi_generic_fill_ssdt_generator, +}; + +static void wifi_generic_enable(struct device *dev) +{ + struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; + + if (!config) + return; + + dev->ops = &wifi_generic_ops; +} + +struct chip_operations drivers_wifi_generic_ops = { + CHIP_NAME("WIFI Device") + .enable_dev = wifi_generic_enable +}; diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h deleted file mode 100644 index 57209e9547..0000000000 --- a/src/drivers/wifi/generic_wifi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _GENERIC_WIFI_H_ -#define _GENERIC_WIFI_H_ - -/** - * struct generic_wifi_config - Data structure to contain common wifi config - * @wake: Wake pin for ACPI _PRW - * @maxsleep: Maximum sleep state to wake from - */ -struct generic_wifi_config { - unsigned int wake; - unsigned int maxsleep; -}; - -/** - * wifi_fill_ssdt() - Fill ACPI SSDT table for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * @config: Common wifi config required to fill ACPI SSDT table. - * - * This function implements common device operation to help fill ACPI SSDT - * table for WiFi controller. - */ -void generic_wifi_fill_ssdt(const struct device *dev, - const struct generic_wifi_config *config); - -/** - * wifi_acpi_name() - Get ACPI name for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * - * This function implements common device operation to get the ACPI name for - * WiFi controller. - * - * Return: string representing the ACPI name for WiFi controller. - */ -const char *generic_wifi_acpi_name(const struct device *dev); - -#endif /* _GENERIC_WIFI_H_ */ diff --git a/src/ec/51nb/npce985la0dx/npce985la0dx.c b/src/ec/51nb/npce985la0dx/npce985la0dx.c index f435d3222e..06db530c3b 100644 --- a/src/ec/51nb/npce985la0dx/npce985la0dx.c +++ b/src/ec/51nb/npce985la0dx/npce985la0dx.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index cacea96e3b..eb0b5ff5ad 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -25,7 +25,6 @@ static int kbc_input_buffer_empty(void) return !!timeout; } - static int kbc_output_buffer_full(void) { u32 timeout; @@ -58,7 +57,6 @@ int kbc_cleanup_buffers(void) return !!timeout; } - /* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * @@ -88,7 +86,6 @@ void ec_kbc_write_ib(u8 data) outb(data, KBD_DATA); } - /* * These functions are for accessing the ENE932 device space, but are not * currently used. diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index d05bc8f177..a1581b5c8f 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -22,14 +22,12 @@ #define CFG_COMMAND_WRITE_ENABLE (1 << 3) #define CFG_STATUS (1 << 1) - #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 #define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) #define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) - /* Wait 400ms for keyboard controller answers */ #define KBC_TIMEOUT_IN_MS 400 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf828..d12274f8c0 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -10,7 +10,10 @@ #ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) #endif - +/* Enable DPTC interface with AMD ALIB */ +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +External(\_SB.DPTC, MethodObj) +#endif Device (EC0) { @@ -156,6 +159,17 @@ Device (EC0) // Initialize LID switch state Store (LIDS, \LIDS) + +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT + /* + * Per the device mode (clamshell or tablet) to initialize + * the thermal setting on OS startup. + */ + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } +#endif + } /* Read requested temperature and check against EC error values */ @@ -379,6 +393,11 @@ Device (EC0) #endif #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) +#endif +#ifdef EC_ENABLE_AMD_DPTC_SUPPORT + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } #endif } diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 7c3f9661fe..9bfb1c4fd1 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -3,7 +3,6 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H - struct ec_google_chromeec_config { }; diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a97dfb355e..40285dc81d 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -393,7 +392,14 @@ void google_chromeec_log_events(uint64_t mask) return; events = google_chromeec_get_events_b() & mask; - for (i = 0; i < sizeof(events) * 8; i++) { + + /* + * This loop starts at 1 because the EC_HOST_EVENT_MASK macro subtracts + * 1 from its argument before applying the left-shift operator. This + * prevents a left-shift of -1 happening, and covers the entire 64-bit + * range of the event mask. + */ + for (i = 1; i <= sizeof(events) * 8; i++) { if (EC_HOST_EVENT_MASK(i) & events) elog_add_event_byte(ELOG_TYPE_EC_EVENT, i); } @@ -1533,3 +1539,21 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) return 0; } + +int google_chromeec_ap_reset(void) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_AP_RESET, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aead5f7fa8..9d4e58842e 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -337,6 +337,13 @@ int google_chromeec_get_pd_port_caps(int port, */ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); +/** + * Send EC command to perform AP reset + * + * @return 0 on success, -1 on error + */ +int google_chromeec_ap_reset(void); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a29ad..4c3d0bb838 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -414,7 +414,6 @@ extern "C" { /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 - /* * This header file is used in coreboot both in C and ACPI code. The ACPI code * is pre-processed to handle constants but the ASL compiler is unable to @@ -1254,7 +1253,6 @@ struct ec_response_get_protocol_info { uint32_t flags; } __ec_align4; - /*****************************************************************************/ /* Get/Set miscellaneous values */ @@ -1664,7 +1662,6 @@ struct ec_params_flash_erase_v1 { /* Rollback information flash region protected now */ #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) - /** * struct ec_params_flash_protect - Parameters for the flash protect command. * @mask: Bits in flags to apply. @@ -1761,7 +1758,6 @@ struct ec_response_vbnvcontext { uint8_t block[EC_VBNV_BLOCK_SIZE]; } __ec_align4; - /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 @@ -1779,7 +1775,6 @@ struct ec_response_flash_spi_info { uint8_t sr1, sr2; } __ec_align1; - /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 @@ -1791,7 +1786,6 @@ struct ec_params_flash_select { uint8_t select; } __ec_align4; - /** * Request random numbers to be generated and returned. * Can be used to test the random number generator is truly random. @@ -2202,7 +2196,6 @@ struct ec_response_lightbar { struct lightbar_params_v0 get_params_v0; struct lightbar_params_v1 get_params_v1; - struct lightbar_params_v2_timing get_params_v2_timing; struct lightbar_params_v2_tap get_params_v2_tap; struct lightbar_params_v2_oscillation get_params_v2_osc; @@ -2815,7 +2808,6 @@ struct ec_params_motion_sense { uint16_t scale[3]; } sensor_scale; - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -3272,7 +3264,6 @@ struct ec_response_thermal_get_threshold { uint16_t value; } __ec_align2; - /* The version 1 structs are visible. */ enum ec_temp_thresholds { EC_TEMP_THRESH_WARN = 0, @@ -3388,7 +3379,6 @@ struct ec_params_tmp006_set_calibration_v1 { float val[0]; } __ec_align4; - /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 @@ -3786,7 +3776,6 @@ struct ec_response_keyboard_factory_test { #define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 - #define EC_CMD_MKBP_WAKE_MASK 0x0069 enum ec_mkbp_event_mask_action { /* Retrieve the value of a wake mask. */ @@ -3864,7 +3853,6 @@ struct ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ - /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host @@ -4461,7 +4449,6 @@ struct ec_response_charge_state { }; } __ec_align4; - /* * Set maximum battery charging current. */ @@ -4790,7 +4777,6 @@ struct ec_response_i2c_passthru_protect { uint8_t status; /* Status flags (0: unlocked, 1: locked) */ } __ec_align1; - /*****************************************************************************/ /* * HDMI CEC commands @@ -5400,7 +5386,6 @@ struct ec_response_usb_pd_power_info { uint32_t max_power; } __ec_align4; - /* * This command will return the number of USB PD charge port + the number * of dedicated port present. @@ -5602,7 +5587,6 @@ struct ec_params_pd_write_log_entry { uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __ec_align1; - /* Control USB-PD chip */ #define EC_CMD_PD_CONTROL 0x0119 @@ -5886,7 +5870,6 @@ struct ec_response_rollback_info { int32_t rw_rollback_version; } __ec_align4; - /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -5928,7 +5911,6 @@ struct ec_params_locate_chip { }; } __ec_align2; - struct ec_response_locate_chip { uint8_t bus_type; /* enum ec_bus_type */ uint8_t reserved; /* Aligning the following union to 2 bytes */ diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 0f8d4a313b..631f16ebce 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -135,7 +135,7 @@ static void write_is_policy_enabled(bool enabled) * Local1 = 0 * Local2 = 0 * - * While (Local1 < Local) { + * While (Local1 < Local0) { * If (IDSP[Local1] == Arg0 && Arg1 == enabled) { * Local2 = 1 * } @@ -167,8 +167,7 @@ static void write_is_policy_enabled(bool enabled) */ acpigen_emit_byte(WHILE_OP); acpigen_write_len_f(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LLESS_OP); acpigen_emit_byte(LOCAL1_OP); acpigen_emit_byte(LOCAL0_OP); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 5306dcca5b..b9c972834b 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -307,7 +307,6 @@ static int google_chromeec_command_v1(struct chromeec_command *cec_command) args.checksum = csum; write_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL); - /* Issue the command */ write_byte(cmd_code, EC_LPC_ADDR_HOST_CMD); diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index 0bfc9d4dc6..39a1c0be82 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h index 2db8cfe4ab..8a5b69c34c 100644 --- a/src/ec/google/wilco/bootblock.h +++ b/src/ec/google/wilco/bootblock.h @@ -9,7 +9,7 @@ * This function performs early initialization of the EC: * * - Enable EC UART passthru for COM1 if serial console support - * is enabled with CONFIG_DRIVERS_UART_8250IO. + * is enabled with CONFIG(DRIVERS_UART_8250IO). */ void wilco_ec_early_init(void); diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index 924501fbeb..fa2414adbc 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -5,7 +5,12 @@ config EC_HP_KBC1126 help Interface to SMSC KBC1126 embedded controller in HP laptops. -if EC_HP_KBC1126 +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + depends on EC_HP_KBC1126 + default y + +if EC_HP_KBC1126_ECFW_IN_CBFS comment "Please select the following otherwise your laptop cannot be powered on." diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 54e8b2afc3..43e5d3fb0b 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_EC_HP_KBC1126),y) +ifeq ($(CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS),y) KBC1126_EC_INSERT:=$(top)/util/kbc1126/kbc1126_ec_insert INTERMEDIATE+=kbc1126_ec_insert @@ -39,8 +39,8 @@ ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "You can read util/kbc1126/README.md for details.\n\n" endif -ramstage-y += ec.c -bootblock-y += early_init.c -romstage-y += early_init.c - endif + +ramstage-$(CONFIG_EC_HP_KBC1126) += ec.c +bootblock-$(CONFIG_EC_HP_KBC1126) += early_init.c +romstage-$(CONFIG_EC_HP_KBC1126) += early_init.c diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 8ca8d246e9..30f40fe097 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -12,6 +12,13 @@ enum kempld_uart_io { KEMPLD_UART_2E8 = 3, }; +enum kempld_i2c_frequency { + KEMPLD_I2C_FREQ_STANDARD_MODE_100KHZ = 100, + KEMPLD_I2C_FREQ_FAST_MODE_400KHZ = 400, + KEMPLD_I2C_FREQ_FAST_PLUS_MODE_1MHZ = 1000, + KEMPLD_I2C_FREQ_MAX = 2700, +}; + struct kempld_uart { enum kempld_uart_io io; unsigned int irq; @@ -19,6 +26,7 @@ struct kempld_uart { struct ec_kontron_kempld_config { struct kempld_uart uart[KEMPLD_NUM_UARTS]; + unsigned short i2c_frequency; }; #endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c index cb33a8baaf..3cafb1e762 100644 --- a/src/ec/kontron/kempld/early_kempld.c +++ b/src/ec/kontron/kempld/early_kempld.c @@ -43,13 +43,11 @@ void kempld_enable_uart_for_console(void) switch (CONFIG_UART_FOR_CONSOLE) { case 0: kempld_write8(KEMPLD_UART_0, - KEMPLD_UART_ENABLE | - KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); + KEMPLD_UART_ENABLE | KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); break; case 1: kempld_write8(KEMPLD_UART_1, - KEMPLD_UART_ENABLE | - KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); + KEMPLD_UART_ENABLE | KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); break; default: break; diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 19376c7961..f8371a8d82 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -16,21 +16,20 @@ static void kempld_uart_read_resources(struct device *dev) struct resource *const res_io = new_resource(dev, 0); struct resource *const res_irq = new_resource(dev, 1); const unsigned int uart = dev->path.generic.subid; + if (!config || !res_io || !res_irq || uart >= KEMPLD_NUM_UARTS) return; const enum kempld_uart_io io = config->uart[uart].io; if (io >= ARRAY_SIZE(io_addr)) { - printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", - io, uart); + printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", io, uart); dev->enabled = false; return; } const int irq = config->uart[uart].irq; if (irq >= 16) { - printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", - irq, uart); + printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", irq, uart); dev->enabled = false; return; } @@ -49,9 +48,10 @@ static void kempld_uart_read_resources(struct device *dev) const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; const uint8_t val = kempld_read8(reg); - kempld_write8(reg, (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) - | io << KEMPLD_UART_IO_SHIFT - | irq << KEMPLD_UART_IRQ_SHIFT); + kempld_write8(reg, + (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) | + io << KEMPLD_UART_IO_SHIFT | + irq << KEMPLD_UART_IRQ_SHIFT); kempld_release_mutex(); } @@ -90,9 +90,7 @@ static void kempld_enable_dev(struct device *const dev) } /* Fall through. */ default: - printk(BIOS_WARNING, - "KEMPLD: Spurious device %s.\n", - dev_path(dev)); + printk(BIOS_WARNING, "KEMPLD: Spurious device %s.\n", dev_path(dev)); break; } } diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 296cf76ddd..b99c0e48b0 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -13,6 +13,7 @@ #include #include +#include "chip.h" #include "kempld.h" #include "kempld_internal.h" @@ -40,9 +41,6 @@ #define I2C_CMD_READ_NACK 0x29 #define I2C_CMD_IACK 0x01 -#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ -#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ - #define EIO 5 #define ENXIO 6 #define EAGAIN 11 @@ -153,8 +151,7 @@ static int kempld_i2c_process(struct kempld_i2c_data *const i2c) i2c->state = STATE_ADDR; return 0; } - i2c->state = (msg->flags & I2C_M_RD) - ? STATE_READ : STATE_WRITE; + i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; } else { i2c->state = STATE_DONE; kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); @@ -230,7 +227,8 @@ static struct device_operations kempld_i2c_dev_ops = { void kempld_i2c_device_init(struct device *const dev) { - u16 prescale_corr; + const struct ec_kontron_kempld_config *const config = dev->chip_info; + u16 prescale_corr, frequency; long prescale; u8 ctrl; u8 stat; @@ -244,11 +242,23 @@ void kempld_i2c_device_init(struct device *const dev) ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_write8(KEMPLD_I2C_CTRL, ctrl); + frequency = KEMPLD_I2C_FREQ_STANDARD_MODE_100KHZ; + if (config && config->i2c_frequency) { + if (config->i2c_frequency <= KEMPLD_I2C_FREQ_MAX) { + frequency = config->i2c_frequency; + } else { + printk(BIOS_NOTICE, + "kempld_i2c: %d kHz is too high!\n", + config->i2c_frequency); + } + } + printk(BIOS_INFO, "kempld_i2c: Use frequency %d\n", frequency); + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); if (spec_major == 1) - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + prescale = KEMPLD_CLK / (frequency * 5) - 1000; else - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + prescale = KEMPLD_CLK / (frequency * 4) - 3000; if (prescale < 0) prescale = 0; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index aa1877eac6..093a639ed5 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -172,14 +172,14 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) for (i = 0; i < 8; i++) { c = ec_read(0xf0 + i); if (c < 0x20 || c > 0x7f) { - i = snprintf(str, sizeof (str), "*INVALID"); + i = snprintf(str, sizeof(str), "*INVALID"); break; } str[i] = c; } /* EC firmware function specification version */ - i += snprintf(str + i, sizeof (str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); + i += snprintf(str + i, sizeof(str) - i, "-%u.%u", ec_read(0xef), ec_read(0xeb)); i = MIN(buf_len, i); memcpy(buf, str, i); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index c5092c3a29..40816117b1 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -40,7 +40,6 @@ void h8_ssdt_generator(const struct device *dev); */ void h8_mb_init(void); - /* EC registers */ #define H8_CONFIG0 0x00 #define H8_CONFIG0_EVENTS_ENABLE 0x02 @@ -69,16 +68,16 @@ void h8_mb_init(void); #define H8_TRACKPOINT_OFF 0x02 #define H8_TRACKPOINT_ON 0x03 -#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL 0x0c #define H8_LED_CONTROL_OFF 0x00 #define H8_LED_CONTROL_ON 0x80 #define H8_LED_CONTROL_PULSE 0xa0 /* Some models, power LED only*/ #define H8_LED_CONTROL_BLINK 0xc0 #define H8_LED_CONTROL_POWER_LED 0x00 -#define H8_LED_CONTROL_BAT0_LED 0x01 -#define H8_LED_CONTROL_BAT1_LED 0x02 -#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 #define H8_LED_CONTROL_SUSPEND_LED 0x07 #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 @@ -95,51 +94,51 @@ void h8_mb_init(void); #define H8_VOLUME_CONTROL 0x30 #define H8_VOLUME_CONTROL_MUTE 0x40 /* Embedded controller events */ -#define H8_EVENT_FN_F1 0x10 -#define H8_EVENT_FN_F2 0x11 -#define H8_EVENT_FN_F3 0x12 -#define H8_EVENT_FN_F4 0x13 -#define H8_EVENT_FN_HOME 0x14 -#define H8_EVENT_FN_END 0x15 -#define H8_EVENT_FN_F7 0x16 -#define H8_EVENT_FN_F8 0x17 -#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 #define H8_EVENT_FN_THINKVANTAGE 0x19 -#define H8_EVENT_FN_F11 0x1a -#define H8_EVENT_FN_F12 0x1b -#define H8_EVENT_FN_1 0x1c -#define H8_EVENT_FN_2 0x1d -#define H8_EVENT_FN_PGUP 0x1f +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f -#define H8_EVENT_AC_ON 0x26 -#define H8_EVENT_AC_OFF 0x27 +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 -#define H8_EVENT_PWRSW_PRESS 0x28 -#define H8_EVENT_PWRSW_RELEASE 0x29 +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 -#define H8_EVENT_LIDSW_CLOSE 0x2a -#define H8_EVENT_LIDSW_PUSH 0x2b +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b -#define H8_EVENT_UBAY_UNLOCK 0x2c -#define H8_EVENT_UBAY_LOCK 0x2d +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d -#define H8_EVENT_KEYPRESS 0x33 +#define H8_EVENT_KEYPRESS 0x33 -#define H8_EVENT_FN_PRESS 0x39 +#define H8_EVENT_FN_PRESS 0x39 -#define H8_STATUS0 0x46 -#define H8_STATUS0_FN_KEY_DOWN 0x01 -#define H8_STATUS1 0x47 -#define H8_STATUS2 0x48 -#define H8_STATUS3 0x49 +#define H8_STATUS0 0x46 +#define H8_STATUS0_FN_KEY_DOWN 0x01 +#define H8_STATUS1 0x47 +#define H8_STATUS2 0x48 +#define H8_STATUS3 0x49 -#define H8_EVENT_BAT0 0x4a -#define H8_EVENT_BAT0_STATE 0x4b +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b -#define H8_EVENT_BAT1 0x4c -#define H8_EVENT_BAT1_STATE 0x4d +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d -#define H8_EVENT_FN_F5 0x64 -#define H8_EVENT_FN_F6 0x65 +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 #endif /* EC_LENOVO_H8_H */ diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 97abb9de24..b564153331 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -33,7 +33,7 @@ int get_recovery_mode_switch(void) } /** - * Only used if CONFIG_CHROMEOS is set. + * Only used if CONFIG(CHROMEOS) is set. * Always zero as the #WP pin of the flash is tied high. */ int get_write_protect_state(void) diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 532060f8a1..c7b934877c 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -26,7 +26,6 @@ static int ec_input_buffer_empty(u8 status_port) return !!timeout; } - static int ec_output_buffer_full(u8 status_port) { u32 timeout; @@ -41,8 +40,6 @@ static int ec_output_buffer_full(u8 status_port) return !!timeout; } - - /* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index dafafa7992..d354048eb0 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -12,8 +12,6 @@ #define EC_IO_LOW EC_IO + 2 #define EC_IO_DATA EC_IO + 3 - - // 60h/64h Command Interface #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 @@ -192,5 +190,4 @@ void ec_mem_write(u8 addr, u8 data); #define EC_CMD_BURST_DISABLE 0x83 #define EC_CMD_QUERY_EVENT 0x84 - #endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */ diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 949f93dc75..80aaa5dd12 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -26,7 +26,6 @@ static int input_buffer_empty(u16 status_reg) return !!timeout; } - static int output_buffer_full(u16 status_reg) { u32 timeout; @@ -42,8 +41,6 @@ static int output_buffer_full(u16 status_reg) return !!timeout; } - - /* The IT8518 60/64 EC registers are the same command/status IB/OB KBC pair. * Check status from 64 port before each command. * @@ -73,7 +70,6 @@ void ec_kbc_write_ib(u8 data) outb(data, KBD_DATA); } - /* * These functions are for accessing the IT8518 device RAM space via 0x66/0x68 */ @@ -110,7 +106,6 @@ void ec_write(u16 addr, u8 data) ec_write_ib(data); } - u8 ec_it8518_get_event(void) { u8 cmd = 0; diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 4dcf1580c3..5645062bcc 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -58,7 +58,6 @@ void ec_kbc_write_ib(u8 data); #define EC_IF_MAJ_VER 0xEF #define EC_MBAT_STATUS 0x0138 - // EC 0.83b added status bits: // BIT0=EC in RO mode // BIT1=Recovery Key Sequence Detected diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 6e7db17324..7b0f339bc5 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -41,6 +41,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ +#define ACPI_DSDT_REV_2 0x02 /* DSDT revision: ACPI v2.0 and greater */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include @@ -800,6 +801,26 @@ typedef struct acpi_cstate { acpi_addr_t resource; } __packed acpi_cstate_t; +struct acpi_sw_pstate { + u32 core_freq; + u32 power; + u32 transition_latency; + u32 bus_master_latency; + u32 control_value; + u32 status_value; +} __packed; + +struct acpi_xpss_sw_pstate { + u64 core_freq; + u64 power; + u64 transition_latency; + u64 bus_master_latency; + u64 control_value; + u64 status_value; + u64 control_mask; + u64 status_mask; +} __packed; + typedef struct acpi_tstate { u32 percent; u32 power; @@ -987,7 +1008,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); /* For ACPI S3 support. */ -void acpi_resume(void *wake_vec); +void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 6287ba1672..be13bd7ec8 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -4,8 +4,8 @@ #define __ACPI_ACPI_DEVICE_H__ #include -#include #include +#include enum acpi_dp_type { ACPI_DP_TYPE_UNKNOWN, diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index 82748d0f5f..fe0aa408fd 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -11,6 +11,8 @@ #ifndef __ACPI_ACPI_IVRS_H__ #define __ACPI_ACPI_IVRS_H__ +#include + /* I/O Virtualization Reporting Structure (IVRS) */ #define IVHD_BLOCK_TYPE_LEGACY__FIXED 0x10 #define IVHD_BLOCK_TYPE_FULL__FIXED 0x11 @@ -40,6 +42,7 @@ /* Extended Feature Support */ #define IVINFO_EFR_SUPPORTED 0x01 +#define EFR_FEATURE_SUP (1 << 27) /* IVHD Flags Field */ #define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ @@ -61,6 +64,7 @@ #define IOMMU_FEATURE_PN_BANKS_SHIFT 17 #define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 #define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ +#define IOMMU_FEATURE_GLX_SHIFT 3 #define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ #define IOMMU_FEATURE_GA_SUP (1 << 6) /* Type 10h only */ @@ -68,8 +72,9 @@ #define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ -#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */ +#define IOMMU_FEATURE_GT_SUP (1 << 2) /* Type 10h only */ +#define IOMMU_FEATURE_NX_SUP (1 << 1) /* Type 10h only */ +#define IOMMU_FEATURE_XT_SUP (1 << 0) /* IVHD Device Entry Type Codes */ #define IVHD_DEV_4_BYTE_ALL 0x01 @@ -106,6 +111,64 @@ #define IVHD_UID_INT 0x01 #define IVHD_UID_STRING 0x02 +#define IOMMU_CAP_ID 0x0f + +/* MMIO Offset 0x30: IOMMU Extended Feature Register */ +#define MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT 0 +#define MMIO_EXT_FEATURE_PRE_F_SUP (0x1 << MMIO_EXT_FEATURE_PRE_F_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PPR_SUP_SHIFT 1 +#define MMIO_EXT_FEATURE_PPR_SUP (0x1 << MMIO_EXT_FEATURE_PPR_SUP_SHIFT) +#define MMIO_EXT_FEATURE_XT_SUP_SHIFT 2 +#define MMIO_EXT_FEATURE_XT_SUP (0x1 << MMIO_EXT_FEATURE_XT_SUP_SHIFT) +#define MMIO_EXT_FEATURE_NX_SUP_SHIFT 3 +#define MMIO_EXT_FEATURE_NX_SUP (0x1 << MMIO_EXT_FEATURE_NX_SUP_SHIFT) +#define MMIO_EXT_FEATURE_GT_SUP_SHIFT 4 +#define MMIO_EXT_FEATURE_GT_SUP (0x1 << MMIO_EXT_FEATURE_GT_SUP_SHIFT) +#define MMIO_EXT_FEATURE_IA_SUP_SHIFT 6 +#define MMIO_EXT_FEATURE_IA_SUP (0x1 << MMIO_EXT_FEATURE_IA_SUP_SHIFT) +#define MMIO_EXT_FEATURE_GA_SUP_SHIFT 7 +#define MMIO_EXT_FEATURE_GA_SUP (0x1 << MMIO_EXT_FEATURE_GA_SUP_SHIFT) +#define MMIO_EXT_FEATURE_HE_SUP_SHIFT 8 +#define MMIO_EXT_FEATURE_HE_SUP (0x1 << MMIO_EXT_FEATURE_HE_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PC_SUP_SHIFT 9 +#define MMIO_EXT_FEATURE_PC_SUP (0x1 << MMIO_EXT_FEATURE_PC_SUP_SHIFT) +#define MMIO_EXT_FEATURE_HATS_SHIFT 10 +#define MMIO_EXT_FEATURE_HATS_MASK (0x3 << MMIO_EXT_FEATURE_HATS_SHIFT) +#define MMIO_EXT_FEATURE_GATS_SHIFT 12 +#define MMIO_EXT_FEATURE_GATS_MASK (0x3 << MMIO_EXT_FEATURE_GATS_SHIFT) +#define MMIO_EXT_FEATURE_GLX_SHIFT 14 +#define MMIO_EXT_FEATURE_GLX_SUP_MASK (0x3 << MMIO_EXT_FEATURE_GLX_SHIFT) +#define MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT 16 +#define MMIO_EXT_FEATURE_SMI_F_SUP_MASK (0x3 << MMIO_EXT_FEATURE_SMI_F_SUP_SHIFT) +#define MMIO_EXT_FEATURE_SMI_FRC_SHIFT 18 +#define MMIO_EXT_FEATURE_SMI_FRC_MASK (0x7 << MMIO_EXT_FEATURE_SMI_FRC_SHIFT) +#define MMIO_EXT_FEATURE_GAM_SUP_SHIFT 21 +#define MMIO_EXT_FEATURE_GAM_SUP_MASK (0x7 << MMIO_EXT_FEATURE_GAM_SUP_SHIFT) +#define MMIO_EXT_FEATURE_PAS_MAX_SHIFT 32 +#define MMIO_EXT_FEATURE_PAS_MAX_MASK (0x1fULL << MMIO_EXT_FEATURE_PAS_MAX_SHIFT) + +/* MMIO Offset 0x18: IOMMU Control Register */ +#define MMIO_CTRL_IOMMU_EN (1 << 0) +#define MMIO_CTRL_HT_TUN_EN (1 << 1) +#define MMIO_CTRL_PASS_PW (1 << 8) +#define MMIO_CTRL_RES_PASS_PW (1 << 9) +#define MMIO_CTRL_COHERENT (1 << 10) +#define MMIO_CTRL_ISOC (1 << 11) + +/* MMIO Offset 0x4000: Counter Configuration Register */ +#define MMIO_CNT_CFG_N_CNT_BANKS_SHIFT 12 +#define MMIO_CNT_CFG_N_COUNTER_BANKS (0x3f << MMIO_CNT_CFG_N_CNT_BANKS_SHIFT) +#define MMIO_CNT_CFG_N_COUNTER_SHIFT 7 +#define MMIO_CNT_CFG_N_COUNTER (0xf << MMIO_CNT_CFG_N_COUNTER_SHIFT) + +/* Capability offset 0 */ +#define CAP_OFFSET_0_IOTLB_SP_SHIFT 24 +#define CAP_OFFSET_0_IOTLB_SP (1 << CAP_OFFSET_0_IOTLB_SP_SHIFT) + +/// Capability offset 10h +#define CAP_OFFSET_10_MSI_NUM_PPR_SHIFT 27 +#define CAP_OFFSET_10_MSI_NUM_PPR (0x1f << CAP_OFFSET_10_MSI_NUM_PPR_SHIFT) + /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ typedef struct ivrs_ivhd_generic { uint8_t type; @@ -123,6 +186,24 @@ typedef struct ivrs_ivhd_alias { uint8_t reserved2; } __packed ivrs_ivhd_alias_t; +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */ +typedef struct acpi_ivrs_ivhd_40 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + uint32_t iommu_attributes; + uint32_t efr_reg_image_low; + uint32_t efr_reg_image_high; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd40_t; + typedef struct ivrs_ivhd_extended { uint8_t type; uint16_t dev_id; @@ -139,4 +220,14 @@ typedef struct ivrs_ivhd_special { uint8_t variety; } __packed ivrs_ivhd_special_t; +typedef struct ivrs_ivhd_f0_entry { + uint8_t type; + uint16_t dev_id; + uint8_t dte_setting; + uint8_t hardware_id[8]; + uint8_t compatible_id[8]; + uint8_t uuid_format; + uint8_t uuid_length; +} __packed ivrs_ivhd_f0_entry_t; + #endif /* __ACPI_ACPI_IVRS_H__ */ diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 98a9fe474c..c30f8449b6 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -3,6 +3,7 @@ #ifndef __ACPI_ACPIGEN_H__ #define __ACPI_ACPIGEN_H__ +#include #include #include #include @@ -323,6 +324,7 @@ void acpigen_write_STA_ext(const char *namestring); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); +void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries); typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); @@ -330,6 +332,10 @@ void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); +void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts); +void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value); +void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, + size_t nentries); void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); void acpigen_write_processor_package(const char *name, unsigned int first_core, @@ -367,6 +373,7 @@ void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); void acpigen_write_to_integer(uint8_t src, uint8_t dst); +void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op); void acpigen_write_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, size_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); @@ -379,6 +386,10 @@ void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); struct soundwire_address; void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); +void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name); /* * Generate ACPI AML code for _DSM method. * This function takes as input uuid for the device, set of callbacks and diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 1790df77e8..b173bb8214 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -5,6 +5,7 @@ #include #include +#include /* A common idiom is to use a default value if none is provided (i.e., == 0) */ #define DEFAULT_IF_0(thing, default_) ((thing) ? (thing) : (default_)) diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h index 90524c2e5a..858c2ce1c3 100644 --- a/src/include/acpi/acpigen_ps2_keybd.h +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __ACPI_ACPIGEN_PS2_KEYBD_H__ #define __ACPI_ACPIGEN_PS2_KEYBD_H__ diff --git a/src/include/asan.h b/src/include/asan.h new file mode 100644 index 0000000000..103fcc92d2 --- /dev/null +++ b/src/include/asan.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASAN_H +#define __ASAN_H + +#include + +#define ASAN_SHADOW_SCALE_SHIFT 3 + +#define ASAN_SHADOW_SCALE_SIZE (1UL << ASAN_SHADOW_SCALE_SHIFT) +#define ASAN_SHADOW_MASK (ASAN_SHADOW_SCALE_SIZE - 1) + +#define ASAN_GLOBAL_REDZONE 0xFA +#define ASAN_STACK_LEFT 0xF1 +#define ASAN_STACK_MID 0xF2 +#define ASAN_STACK_RIGHT 0xF3 +#define ASAN_STACK_PARTIAL 0xF4 +#define ASAN_USE_AFTER_SCOPE 0xF8 + +#define _RET_IP_ ((unsigned long)__builtin_return_address(0)) +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define WARN_ON(condition) ({ \ + int __ret_warn_on = !!(condition); \ + unlikely(__ret_warn_on); \ +}) + +#ifndef ASAN_ABI_VERSION +#define ASAN_ABI_VERSION 5 +#endif + +/* The layout of struct dictated by compiler */ +struct asan_source_location { + const char *filename; + int line_no; + int column_no; +}; + +/* The layout of struct dictated by compiler */ +struct asan_global { + const void *beg; /* Address of the beginning of the global variable. */ + size_t size; /* Size of the global variable. */ + size_t size_with_redzone; /* Size of the variable + size of the red zone + 32 bytes aligned. */ + const void *name; + const void *module_name; /* Name of the module where the global variable + is declared. */ + unsigned long has_dynamic_init; /* This needed for C++. */ +#if ASAN_ABI_VERSION >= 4 + struct asan_source_location *location; +#endif +#if ASAN_ABI_VERSION >= 5 + char *odr_indicator; +#endif +}; + +void asan_unpoison_shadow(const void *address, size_t size); +void asan_report(unsigned long addr, size_t size, bool is_write, + unsigned long ip); +void asan_init(void); +void check_memory_region(unsigned long addr, size_t size, bool write, + unsigned long ret_ip); + +uintptr_t __asan_shadow_offset(uintptr_t addr); +void __asan_register_globals(struct asan_global *globals, size_t size); +void __asan_unregister_globals(struct asan_global *globals, size_t size); +void __asan_poison_stack_memory(const void *addr, size_t size); +void __asan_unpoison_stack_memory(const void *addr, size_t size); + +void __asan_load1(unsigned long addr); +void __asan_store1(unsigned long addr); +void __asan_load2(unsigned long addr); +void __asan_store2(unsigned long addr); +void __asan_load4(unsigned long addr); +void __asan_store4(unsigned long addr); +void __asan_load8(unsigned long addr); +void __asan_store8(unsigned long addr); +void __asan_load16(unsigned long addr); +void __asan_store16(unsigned long addr); +void __asan_loadN(unsigned long addr, size_t size); +void __asan_storeN(unsigned long addr, size_t size); + +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_load16_noabort(unsigned long addr); +void __asan_store16_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t size); +void __asan_storeN_noabort(unsigned long addr, size_t size); +void __asan_handle_no_return(void); + +void __asan_set_shadow_00(const void *addr, size_t size); +void __asan_set_shadow_f1(const void *addr, size_t size); +void __asan_set_shadow_f2(const void *addr, size_t size); +void __asan_set_shadow_f3(const void *addr, size_t size); +void __asan_set_shadow_f5(const void *addr, size_t size); +void __asan_set_shadow_f8(const void *addr, size_t size); + +void __asan_report_load1_noabort(unsigned long addr); +void __asan_report_store1_noabort(unsigned long addr); +void __asan_report_load2_noabort(unsigned long addr); +void __asan_report_store2_noabort(unsigned long addr); +void __asan_report_load4_noabort(unsigned long addr); +void __asan_report_store4_noabort(unsigned long addr); +void __asan_report_load8_noabort(unsigned long addr); +void __asan_report_store8_noabort(unsigned long addr); +void __asan_report_load16_noabort(unsigned long addr); +void __asan_report_store16_noabort(unsigned long addr); +void __asan_report_load_n_noabort(unsigned long addr, size_t size); +void __asan_report_store_n_noabort(unsigned long addr, size_t size); +#endif diff --git a/src/include/assert.h b/src/include/assert.h index f656d81683..944c67768a 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -5,6 +5,7 @@ #include #include +#include /* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more properly isolated. */ @@ -12,31 +13,48 @@ #undef ASSERT #endif +/* Do not use filenames nor line numbers on timeless builds, to preserve reproducibility */ +#if ENV_TIMELESS +#define __ASSERT_FILE__ "(filenames not available on timeless builds)" +#define __ASSERT_LINE__ 404 +#else +#define __ASSERT_FILE__ __FILE__ +#define __ASSERT_LINE__ __LINE__ +#endif + +#ifndef _PORTING_H_ /* TODO: Isolate AGESA properly. */ +#define __build_time_assert(x) \ + (__builtin_constant_p(x) ? ((x) ? 1 : dead_code_t(int)) : 0) +#else +#define __build_time_assert(x) 0 +#endif + /* GCC and CAR versions */ -#define ASSERT(x) { \ - if (!(x)) { \ - printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ - ", line %d\n", __FILE__, __LINE__); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ - } \ +#define ASSERT(x) { \ + if (!__build_time_assert(x) && !(x)) { \ + printk(BIOS_EMERG, \ + "ASSERTION ERROR: file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ } - -#define ASSERT_MSG(x, msg) { \ - if (!(x)) { \ - printk(BIOS_EMERG, "ASSERTION ERROR: file '%s'" \ - ", line %d\n", __FILE__, __LINE__); \ - printk(BIOS_EMERG, "%s", msg); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ - } \ +#define ASSERT_MSG(x, msg) { \ + if (!__build_time_assert(x) && !(x)) { \ + printk(BIOS_EMERG, \ + "ASSERTION ERROR: file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + printk(BIOS_EMERG, "%s", msg); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ + } \ } - -#define BUG() { \ - printk(BIOS_EMERG, "ERROR: BUG ENCOUNTERED at file '%s'"\ - ", line %d\n", __FILE__, __LINE__); \ - if (CONFIG(FATAL_ASSERTS)) \ - hlt(); \ +#define BUG() { \ + printk(BIOS_EMERG, \ + "ERROR: BUG ENCOUNTERED at file '%s', line %d\n", \ + __ASSERT_FILE__, __ASSERT_LINE__); \ + if (CONFIG(FATAL_ASSERTS)) \ + hlt(); \ } #define assert(statement) ASSERT(statement) @@ -62,4 +80,15 @@ extern void _dead_code_assertion_failed(void) __attribute__((noreturn)); *(type *)(uintptr_t)0; \ }) +#ifdef __x86_64__ +#define pointer_to_uint32_safe(x) ({ \ + if ((uintptr_t)(x) > 0xffffffffUL) \ + die("Cast from pointer to uint32_t overflows"); \ + (uint32_t)(uintptr_t)(x); \ +}) +#else +#define pointer_to_uint32_safe(x) ({ \ + (uint32_t)(uintptr_t)(x); \ +}) +#endif #endif // __ASSERT_H__ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 5bebd4a623..7fd9ac169b 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -3,6 +3,8 @@ #include #include +#include + /* function prototypes for building the coreboot table */ /* diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96629..da627d23d4 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -29,6 +29,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist); asmlinkage void ap_bootblock_c_entry(void); void bootblock_main_with_basetime(uint64_t base_timestamp); +void bootblock_main_with_timestamp(uint64_t base_timestamp, + struct timestamp_entry *timestamps, size_t num_timestamps); /* This is the argument structure passed from decompressor to bootblock. */ struct bootblock_arg { diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 3262b3a5c0..9fac70113e 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -4,7 +4,6 @@ #include #include -#include /* Only declare main() when in ramstage. */ #if ENV_RAMSTAGE #include diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 29621c6680..a35597d5b1 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -5,6 +5,8 @@ #include #include +#include +#include /*********************************************** * Perform CBFS operations on the boot device. * diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b548cd9559..7e1da17b98 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -155,4 +155,18 @@ static inline int cbmem_possibly_online(void) return 1; } +/* Returns 1 after running cbmem init hooks, 0 otherwise. */ +static inline int cbmem_online(void) +{ + extern int cbmem_initialized; + + if (!cbmem_possibly_online()) + return 0; + + if (ENV_ROMSTAGE) + return cbmem_initialized; + + return 1; +} + #endif /* _CBMEM_H_ */ diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 8104e5c485..9a0dc63915 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -27,5 +27,4 @@ static inline void __flashconsole_tx_byte(u8 data) {} static inline void __flashconsole_tx_flush(void) {} #endif /* __CONSOLE_FLASH_ENABLE__ */ - #endif /* CONSOLE_FLASH_H */ diff --git a/src/include/console/spi.h b/src/include/console/spi.h index cb32d7e64c..2eff0a8903 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -8,7 +8,7 @@ void spiconsole_init(void); void spiconsole_tx_byte(unsigned char c); -#define __CONSOLE_SPI_ENABLE__ (CONFIG(SPI_CONSOLE) && \ +#define __CONSOLE_SPI_ENABLE__ (CONFIG(EM100PRO_SPI_CONSOLE) && \ (ENV_RAMSTAGE || (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CONSOLE_SPI_ENABLE__ @@ -52,6 +52,4 @@ struct em100_msg { char data[MAX_MSG_LENGTH]; } __packed; - - #endif /* CONSOLE_SPI_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 9d37886ccd..6126a89d57 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -35,14 +35,14 @@ unsigned int uart_input_clock_divider(void); /* Bitbang out one byte on an 8n1 UART through the output function set_tx(). */ void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state)); -void uart_init(int idx); -void uart_tx_byte(int idx, unsigned char data); -void uart_tx_flush(int idx); -unsigned char uart_rx_byte(int idx); +void uart_init(unsigned int idx); +void uart_tx_byte(unsigned int idx, unsigned char data); +void uart_tx_flush(unsigned int idx); +unsigned char uart_rx_byte(unsigned int idx); -uintptr_t uart_platform_base(int idx); +uintptr_t uart_platform_base(unsigned int idx); -static inline void *uart_platform_baseptr(int idx) +static inline void *uart_platform_baseptr(unsigned int idx) { return (void *)uart_platform_base(idx); } diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 8bc00d1624..f9e7b2033d 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -12,13 +12,16 @@ #define CPUID_EXT_PM 0x80000007 #define CPUID_MODEL 1 +#define CPUID_EBX_CORE_ID 0x8000001E +#define CPUID_EBX_THREADS_SHIFT 8 +#define CPUID_EBX_THREADS_MASK (0xFF << CPUID_EBX_THREADS_SHIFT) #define MC4_MISC0 0x00000413 #define MC4_MISC1 0xC0000408 #define MC4_MISC2 0xC0000409 #define FS_Base 0xC0000100 -#define HWCR_MSR 0xC0010015 +#define HWCR_MSR 0xC0010015 #define SMM_LOCK (1 << 0) -#define NB_CFG_MSR 0xC001001f +#define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC1_CTL_MASK 0xC0010045 #define MC4_CTL_MASK 0xC0010048 @@ -30,6 +33,9 @@ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */ #define PS_MAX_VAL_SHFT 4 +#define PS_LIM_MAX_VAL_MASK (0x7 << PS_MAX_VAL_SHFT) +#define MAX_PSTATES 8 + /* P-state Control Register */ #define PS_CTL_REG 0xC0010062 /* P-state Control Register CMD Mask OFF */ @@ -43,11 +49,15 @@ #define PSTATE_2_MSR 0xC0010066 #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 - +/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ +#define SERIAL_VID_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_MAX_MICROVOLTS 1550000L #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 #define MSR_CSTATE_ADDRESS 0xC0010073 +#define MSR_CSTATE_ADDRESS_MASK 0xFFFF + #define OSVW_ID_Length 0xC0010140 #define OSVW_Status 0xC0010141 diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 906a7c00f0..608a9df1ec 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -41,6 +41,7 @@ #if !defined(__ASSEMBLER__) #include +#include void amd_setup_mtrrs(void); struct device; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index db324b6da9..99249ba629 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -2,6 +2,7 @@ #define CPU_CPU_H #include +#include void cpu_initialize(unsigned int cpu_index); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index 8596ce519d..b656a284b3 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -66,7 +66,6 @@ typedef struct { u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 2e4e0d5748..6884b285b5 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -6,7 +6,6 @@ #include #include - /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: * - Westmere @@ -83,7 +82,6 @@ typedef struct { u64 rsi; u64 rdi; - u64 io_mem_addr; u32 io_misc_info; diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 1c33c24895..ceddf1d150 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -13,6 +13,8 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H +#include + #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 07fe0381a1..126aa2a4e2 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_ bool cpu_has_alternative_smrr(void); - #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index d66b8e2a7e..e085e34230 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -18,7 +18,6 @@ */ #define PMB1_BASE 0x800 - /* Speedstep related MSRs */ #define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h index 9535e69781..eb34c97e34 100644 --- a/src/include/cpu/x86/bist.h +++ b/src/include/cpu/x86/bist.h @@ -2,6 +2,7 @@ #define CPU_X86_BIST_H #include +#include static inline void report_bist_failure(u32 bist) { diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 01b202eb1a..62341104a4 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -8,6 +8,8 @@ #define CR0_CacheDisable (CR0_CD) #define CR0_NoWriteThrough (CR0_NW) +#define CPUID_FEATURE_CLFLUSH_BIT 19 + #if !defined(__ASSEMBLER__) static inline void wbinvd(void) diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 04f7804d74..b2704eb5b0 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -5,6 +5,8 @@ #include #include +#include +#include #define CACHELINE_SIZE 64 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc04b6..3deb133240 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -90,6 +90,9 @@ #define IA32_L3_MASK_1 0xc91 #define IA32_L3_MASK_2 0xc92 +#define IA32_CR_SF_QOS_MASK_1 0x1891 +#define IA32_CR_SF_QOS_MASK_2 0x1892 + #ifndef __ASSEMBLER__ #include @@ -296,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } - /* Helper for setting single MSR bits */ static inline void msr_set_bit(unsigned int reg, unsigned int bit) { @@ -315,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit) wrmsr(reg, msr); } - #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 42964b02ea..3bf8301cfd 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -27,9 +27,9 @@ #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) - #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +#define SMRR_PHYS_MASK_LOCK (1 << 10) /* Specific to model_6fx and model_1067x */ #define MSR_SMRR_PHYS_BASE 0xa0 diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index fce39b774d..077f964335 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -3,7 +3,6 @@ #include - #if CONFIG(POST_IO) #define post_code(value) \ movb $value, %al; \ diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h index d7f3c7fd9e..6213915eee 100644 --- a/src/include/cpu/x86/smi_deprecated.h +++ b/src/include/cpu/x86/smi_deprecated.h @@ -3,6 +3,8 @@ #ifndef __X86_SMI_DEPRECATED_H__ #define __X86_SMI_DEPRECATED_H__ +#include + #if CONFIG(PARALLEL_MP) || !CONFIG(HAVE_SMI_HANDLER) /* Empty stubs for platforms without SMI handlers. */ static inline void smm_init(void) { } @@ -13,6 +15,6 @@ void smm_init_completion(void); #endif /* Entry from smmhandler.S. */ -void smi_handler(u32 smm_revision); +void smi_handler(void); #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a3101e5155..1073d03e49 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -75,7 +75,7 @@ struct smm_runtime { struct smm_module_params { void *arg; - int cpu; + size_t cpu; const struct smm_runtime *runtime; /* A canary value that has been placed at the end of the stack. * If (uintptr_t)canary != *canary then a stack overflow has occurred. @@ -128,6 +128,12 @@ static inline bool smm_points_to_smram(const void *ptr, const size_t len) * into this field so the code doing the loading can manipulate the * runtime's assumptions. e.g. updating the APIC id to CPU map to * handle sparse APIC id space. + * The following parameters are only used when X86_SMM_LOADER_VERSION2 is enabled. + * - smm_entry - entry address of first CPU thread, all others will be tiled + * below this address. + * - smm_main_entry_offset - default entry offset (e.g 0x8000) + * - smram_start - smaram starting address + * - smram_end - smram ending address */ struct smm_loader_params { void *stack_top; @@ -141,12 +147,24 @@ struct smm_loader_params { void *handler_arg; struct smm_runtime *runtime; + + /* The following are only used by X86_SMM_LOADER_VERSION2 */ +#if CONFIG(X86_SMM_LOADER_VERSION2) + unsigned int smm_entry; + unsigned int smm_main_entry_offset; + unsigned int smram_start; + unsigned int smram_end; +#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); +#if CONFIG(X86_SMM_LOADER_VERSION2) +u32 smm_get_cpu_smbase(unsigned int cpu_num); +#endif + /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); @@ -175,4 +193,9 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size); /* Print the SMM memory layout on console. */ void smm_list_regions(void); +#define SMM_REVISION_OFFSET_FROM_TOP (0x8000 - 0x7efc) +/* Return the SMM save state revision. The revision can be fetched from the smm savestate + which is always at the same offset downward from the top of the save state. */ +uint32_t smm_revision(void); + #endif /* CPU_X86_SMM_H */ diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 6943b93018..ddce96bb39 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -41,22 +41,16 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); } -static inline unsigned long long rdtscll(void) -{ - unsigned long long val; - asm volatile ( - TSC_SYNC - "rdtsc" - : "=A" (val) - ); - return val; -} - static inline uint64_t tsc_to_uint64(tsc_t tstamp) { return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; } +static inline unsigned long long rdtscll(void) +{ + return tsc_to_uint64(rdtsc()); +} + /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 2e93fe937a..85b7221053 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -3,6 +3,7 @@ #ifndef CRC_BYTE_H #define CRC_BYTE_H +#include #include /* This function is used to calculate crc7 byte by byte, with polynomial diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 90260913ae..9246d4bc87 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -3,10 +3,20 @@ #ifndef DEVICE_AZALIA_H #define DEVICE_AZALIA_H -#include #include #include #include +#include + +#define HDA_GCAP_REG 0x00 +#define HDA_GCTL_REG 0x08 +#define HDA_GCTL_CRST (1 << 0) +#define HDA_STATESTS_REG 0x0e +#define HDA_IC_REG 0x60 +#define HDA_IR_REG 0x64 +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; @@ -101,7 +111,7 @@ enum azalia_pin_location_2 { ((type) << 16) | \ ((color) << 12) | \ ((no_presence_detect) << 8) | \ - ((sequence) << 4) | \ + ((association) << 4) | \ ((sequence) << 0)) #define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \ @@ -118,6 +128,8 @@ enum azalia_pin_location_2 { (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \ | (((val) >> 24) & 0xff)) +#define AZALIA_PIN_CFG_NC(n) (0x411111f0 | (n & 0xf)) + #define AZALIA_RESET(pin) \ (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00), \ (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00) diff --git a/src/include/device/device.h b/src/include/device/device.h index 082dcbb4d3..031091ab48 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -195,6 +195,11 @@ void disable_children(struct bus *bus); bool dev_is_active_bridge(struct device *dev); void add_more_links(struct device *dev, unsigned int total_links); +static inline bool is_dev_enabled(const struct device *const dev) +{ + return dev && dev->enabled; +} + /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); @@ -202,6 +207,10 @@ void run_bios(struct device *dev, unsigned long addr); DEVTREE_CONST struct device *find_dev_path( const struct bus *parent, const struct device_path *path); +DEVTREE_CONST struct device *find_dev_nested_path( + const struct bus *parent, + const struct device_path nested_path[], + size_t nested_path_length); struct device *alloc_find_dev(struct bus *parent, struct device_path *path); struct device *dev_find_device(u16 vendor, u16 device, struct device *from); struct device *dev_find_class(unsigned int class, struct device *from); @@ -330,6 +339,12 @@ DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const void devtree_bug(const char *func, pci_devfn_t devfn); void __noreturn devtree_die(void); +/* + * Dies if `dev` or `dev->chip_info` are NULL. Returns `dev->chip_info` otherwise. + * + * Only use if missing `chip_info` is fatal and we can't boot. If it's + * not fatal, please handle the NULL case gracefully. + */ static inline DEVTREE_CONST void *config_of(const struct device *dev) { if (dev && dev->chip_info) diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index c1b4f7621b..9475853924 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -33,10 +33,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index a209e48b8b..0814990eb9 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -19,7 +19,6 @@ #include #include - /** * Convenience definitions for SPD offsets * @@ -34,10 +33,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index f258fa9f09..eac8bf8920 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -21,7 +21,6 @@ #define SPD_DDR4_PART_OFF 329 #define SPD_DDR4_PART_LEN 20 - /* * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. @@ -70,4 +69,9 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, const dimm_attr *info); +/** + * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s + */ +uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz); + #endif /* DEVICE_DRAM_DDR4L_H */ diff --git a/src/include/device/drm_dp_helper.h b/src/include/device/drm_dp_helper.h deleted file mode 100644 index f2e06c33f3..0000000000 --- a/src/include/device/drm_dp_helper.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -/* From the VESA DisplayPort spec */ - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) - -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) - -/* AUX CH addresses */ -/* DPCD */ -#define DP_DPCD_REV 0x000 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -/* 00b = DisplayPort */ -/* 01b = Analog */ -/* 10b = TMDS or HDMI */ -/* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 - -/* link configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_PSR_EN_CFG 0x170 -# define DP_PSR_ENABLE (1 << 0) -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) -# define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_EDP_CONFIGURATION_SET 0x10a - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index a0b1a36a21..3cbd90b39c 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -18,7 +18,6 @@ #define HT_FREQ_2600Mhz 14 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ - static inline bool offset_unit_id(bool is_sb_ht_chain) { bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 0e35a61176..b5e77105b5 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -3,6 +3,7 @@ #ifndef _DEVICE_I2C_BUS_H_ #define _DEVICE_I2C_BUS_H_ +#include #include #include #include diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index 03d68281ef..de1c0eb4b8 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -5,6 +5,7 @@ #include #include +#include int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count); diff --git a/src/include/device/path.h b/src/include/device/path.h index 4db83b7b3f..5690badc4c 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -137,7 +137,6 @@ struct device_path { }; }; - #define DEVICE_PATH_MAX 40 #define BUS_PATH_MAX (DEVICE_PATH_MAX+10) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4529074e9b..58f5904996 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -80,6 +80,14 @@ void pci_bus_reset(struct bus *bus); struct device *pci_probe_dev(struct device *dev, struct bus *bus, unsigned int devfn); +/* + * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and + * PME_ENABLE bits in PM control and status register. + * + * Returns true if PCI device is wake source, false otherwise. + */ +bool pci_dev_is_wake_source(const struct device *dev); + void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus)(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn)); @@ -128,6 +136,18 @@ static inline int pci_base_address_is_memory_space(unsigned int attr) } void pci_dev_disable_bus_master(const struct device *dev); + +static __always_inline +#if ENV_PCI_SIMPLE_DEVICE +void pci_dev_request_bus_master(pci_devfn_t dev) +#else +void pci_dev_request_bus_master(struct device *dev) +#endif /* ENV_PCI_SIMPLE_DEVICE */ +{ + if (CONFIG(PCI_ALLOW_BUS_MASTER)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); +} + #endif /* CONFIG_PCI */ void pci_early_bridge_init(void); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 07ba4a2b30..e0d891eeb9 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -136,7 +136,7 @@ /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_PARITY 0x01 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ -#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ @@ -305,7 +305,6 @@ #define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ - /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ @@ -521,7 +520,6 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ - /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index c3bcdc90f8..e7a445d377 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -5,6 +5,7 @@ #include #include +#include #define EHCI_BAR_INDEX 0x10 #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 62220d87e9..d40d867ce2 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -517,7 +517,6 @@ #define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 - #define PCI_VENDOR_ID_TSENG 0x100c #define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 #define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 @@ -1249,6 +1248,7 @@ #define PCI_DEVICE_ID_INTERG_5050 0x5050 #define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_5261 0x5261 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 @@ -1663,7 +1663,6 @@ #define PCI_DEVICE_ID_ATT_L56XMF 0x0440 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 @@ -2032,6 +2031,10 @@ #define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_VENDOR_ID_GLI 0x17a0 +#define PCI_DEVICE_ID_GLI_9763E 0xe763 +#define PCI_DEVICE_ID_GLI_9755 0x9755 + #define PCI_VENDOR_ID_XGI 0x18ca #define PCI_DEVICE_ID_XGI_20 0x0020 #define PCI_DEVICE_ID_XGI_40 0x0040 @@ -2890,7 +2893,71 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 -#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87 +#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0x4d87 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0 0x7a00 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1 0x7a01 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2 0x7a02 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3 0x7a03 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4 0x7a04 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5 0x7a05 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6 0x7a06 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7 0x7a07 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8 0x7a08 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9 0x7a09 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10 0x7a0a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11 0x7a0b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12 0x7a0c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13 0x7a0d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14 0x7a0e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15 0x7a0f +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16 0x7a10 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17 0x7a11 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18 0x7a12 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19 0x7a13 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20 0x7a14 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21 0x7a15 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22 0x7a16 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23 0x7a17 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24 0x7a18 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25 0x7a19 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26 0x7a1a +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27 0x7a1b +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28 0x7a1c +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29 0x7a1d +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3 0x7a83 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4 0x7a84 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5 0x7a85 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6 0x7a86 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7 0x7a87 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8 0x7a88 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9 0x7a89 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10 0x7a8a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11 0x7a8b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12 0x7a8c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13 0x7a8d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14 0x7a8e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15 0x7a8f +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16 0x7a90 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17 0x7a91 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18 0x7a92 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19 0x7a93 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20 0x7a94 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21 0x7a95 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22 0x7a96 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23 0x7a97 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24 0x7a98 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25 0x7a99 +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26 0x7a9a +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27 0x7a9b +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28 0x7a9c +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29 0x7a9d +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30 0x7a9e +#define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3129,6 +3196,48 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP4 0x51bb +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP5 0x51bc +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP6 0x51bd +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP7 0x51be +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP8 0x51bf +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP9 0x51b0 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP10 0x51b1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP11 0x51b2 +#define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP12 0x51b3 + +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP1 0x7ab8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP2 0x7ab9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP3 0x7aba +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP4 0x7abb +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP5 0x7abc +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP6 0x7abd +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP7 0x7abe +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP8 0x7abf +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP9 0x7ab0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP10 0x7ab1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP11 0x7ab2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP12 0x7ab3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP13 0x7ab4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP14 0x7ab5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP15 0x7ab6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP16 0x7ab7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP17 0x7ac0 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP18 0x7ac1 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP19 0x7ac2 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP20 0x7ac3 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP21 0x7ac4 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP22 0x7ac5 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP23 0x7ac6 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP24 0x7ac7 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP25 0x7ac8 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26 0x7ac9 +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27 0x7aca +#define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -3166,6 +3275,18 @@ #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 #define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2 #define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_1 0x7a52 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_2 0x7a53 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_3 0x7a54 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_4 0x7a55 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_5 0x7a56 +#define PCI_DEVICE_ID_INTEL_ADP_P_SATA_6 0x7a57 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_1 0x7ae2 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_2 0x7ae3 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_3 0x7ae4 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_4 0x7ae5 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_5 0x7ae6 +#define PCI_DEVICE_ID_INTEL_ADP_S_SATA_6 0x7ae7 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3183,6 +3304,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 #define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 +#define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 +#define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3261,6 +3384,20 @@ #define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 #define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C0 0x51e8 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C1 0x51e9 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C2 0x51ea +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C3 0x51eb +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C4 0x51c5 +#define PCI_DEVICE_ID_INTEL_ADP_P_I2C5 0x51c6 + +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C0 0x7acc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C1 0x7acd +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C2 0x7ace +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C3 0x7acf +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C4 0x7afc +#define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 @@ -3304,6 +3441,22 @@ #define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 #define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART0 0x51a8 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART1 0x51a9 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART2 0x51c7 +#define PCI_DEVICE_ID_INTEL_ADP_P_UART3 0x51da +#define PCI_DEVICE_ID_INTEL_ADP_P_UART4 0x51db +#define PCI_DEVICE_ID_INTEL_ADP_P_UART5 0x51dc +#define PCI_DEVICE_ID_INTEL_ADP_P_UART6 0x51dd + +#define PCI_DEVICE_ID_INTEL_ADP_S_UART0 0x7aa8 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART1 0x7aa9 +#define PCI_DEVICE_ID_INTEL_ADP_S_UART2 0x7afe +#define PCI_DEVICE_ID_INTEL_ADP_S_UART3 0x7adc +#define PCI_DEVICE_ID_INTEL_ADP_S_UART4 0x7add +#define PCI_DEVICE_ID_INTEL_ADP_S_UART5 0x7ade +#define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 @@ -3354,6 +3507,24 @@ #define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb #define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4 +#define PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI 0x51a4 +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI0 0x51aa +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI1 0x51ab +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI2 0x51fb +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI3 0x51fd +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI4 0x51fe +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI5 0x51de +#define PCI_DEVICE_ID_INTEL_ADP_P_SPI6 0x51df + +#define PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI 0x7aa4 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI0 0x7aaa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI1 0x7aab +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI2 0x7afb +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI3 0x7af9 +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI4 0x7afa +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI5 0x7aee +#define PCI_DEVICE_ID_INTEL_ADP_S_SPI6 0x7aef + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3466,6 +3637,22 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 #define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 #define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 +#define PCI_DEVICE_ID_INTEL_JSL_GT3 0x4E61 +#define PCI_DEVICE_ID_INTEL_JSL_GT4 0x4E55 + +#define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff +#define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_1 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_2 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_3 0x4603 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_4 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_5 0x4611 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_6 0x4612 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_7 0x4613 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 +#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3521,18 +3708,56 @@ #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 -#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 -#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 -#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12 #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_EHL_ID_2 0x4522 +#define PCI_DEVICE_ID_INTEL_EHL_ID_3 0x4524 +#define PCI_DEVICE_ID_INTEL_EHL_ID_4 0x4512 +#define PCI_DEVICE_ID_INTEL_EHL_ID_5 0x4526 +#define PCI_DEVICE_ID_INTEL_EHL_ID_6 0x4514 +#define PCI_DEVICE_ID_INTEL_EHL_ID_7 0x4528 +#define PCI_DEVICE_ID_INTEL_EHL_ID_8 0x452A +#define PCI_DEVICE_ID_INTEL_EHL_ID_9 0x4516 +#define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452C +#define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x452E +#define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 +#define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 #define PCI_DEVICE_ID_INTEL_JSL_ID_4 0x4e14 +#define PCI_DEVICE_ID_INTEL_JSL_ID_5 0x4e24 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_1 0x4660 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_2 0x4664 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_3 0x4668 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_4 0x466c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_5 0x4670 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_6 0x4640 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_7 0x4644 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_8 0x4648 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_9 0x464c +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_10 0x4650 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_11 0x4630 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_12 0x4610 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_13 0x4673 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_14 0x4623 +#define PCI_DEVICE_ID_INTEL_ADL_S_ID_15 0x0060 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_3 0x4641 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_4 0x4649 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_5 0x4621 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_6 0x4609 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f /* Intel SMBUS device Ids */ +#define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 #define PCI_DEVICE_ID_INTEL_LWB_SMBUS 0xa1a3 @@ -3545,6 +3770,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 #define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 +#define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3563,6 +3790,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded +#define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed +#define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3580,6 +3809,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 #define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 +#define PCI_DEVICE_ID_INTEL_ADP_P_P2SB 0x7a20 +#define PCI_DEVICE_ID_INTEL_ADP_S_P2SB 0x7aa0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3592,6 +3823,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def +#define PCI_DEVICE_ID_INTEL_ADP_P_SRAM 0x7a6f +#define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3610,6 +3843,15 @@ #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 #define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1 0x7ad0 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2 0x7ad1 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3 0x7ad2 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4 0x7ad3 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5 0x7ad4 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6 0x7ad5 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7 0x7ad6 +#define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8 0x7ad7 +#define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3635,6 +3877,14 @@ #define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 #define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 #define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE0 0x51e0 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE1 0x51e1 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE2 0x51e4 +#define PCI_DEVICE_ID_INTEL_ADP_P_CSE3 0x51e5 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE0 0x7ae8 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE1 0x7ae9 +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE2 0x7aec +#define PCI_DEVICE_ID_INTEL_ADP_S_CSE3 0x7aed /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3649,6 +3899,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee +#define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee +#define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3717,10 +3969,13 @@ #define PCI_DEVICE_ID_INTEL_TGL_IPU 0x9a19 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 +#define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d /* Intel Dynamic Tuning Technology Device */ +#define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 #define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 +#define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index d3666c241d..234ebb4c2c 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -7,7 +7,6 @@ #include #include - /* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we * prevent some sub-optimal constant folding. */ extern u8 *const pci_mmconf; diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index c49389f396..8b04d09987 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -1,8 +1,9 @@ #ifndef PCI_ROM_H #define PCI_ROM_H + #include -#include #include +#include #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR ((uint32_t) (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index ca482d26ac..def7f6cca2 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,6 +2,9 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +#include +#include + void pcix_scan_bridge(struct device *dev); const char *pcix_speed(u16 sstatus); diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 800bcc0557..635876b902 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -3,6 +3,7 @@ #include #include +/* When is needed, it supposed to provide */ #include #include #include @@ -67,7 +68,6 @@ struct resource *pnp_get_resource(struct device *dev, unsigned int index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); - struct pnp_mode_ops { void (*enter_conf_mode)(struct device *dev); void (*exit_conf_mode)(struct device *dev); @@ -133,4 +133,37 @@ static inline void pnp_write_index(u16 port, u8 reg, u8 value) outb(value, port + 1); } +/* + * void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set) + * Description: + * This routine unsets and sets bits from indexed I/O registers. The + * reg byte is written to the index register at I/O address = port. + * The value byte to update is data register at I/O address = port + 1. + * + * Unlike and-then-or style operations, no bitwise negation is necessary + * to specify the bits to unset. Because the bitwise negation implicitly + * promotes operands to int before operating, one may have to explicitly + * downcast the result if the data width is smaller than that of an int. + * Since warnings are errors in coreboot, explicit casting is necessary. + * + * Performing said negation inside this routine alleviates this problem, + * while allowing the compiler to warn if the input parameters overflow. + * Casting outside this function would silence valid compiler warnings. + * + * Parameters: + * @param[in] u16 port = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register. + * @param[in] u8 set = Bitmask with ones to the bits to set from the data register. + */ +static inline void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set) +{ + outb(reg, port); + + u8 value = inb(port + 1); + value &= (u8)~unset; + value |= set; + outb(value, port + 1); +} + #endif /* DEVICE_PNP_H */ diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 0cfdd61c27..15d31156ed 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -6,7 +6,6 @@ #include #include #include -#include #if ENV_PNP_SIMPLE_DEVICE @@ -22,6 +21,12 @@ static __always_inline uint8_t pnp_read_config( return pnp_read_index(dev >> 8, reg); } +static __always_inline void pnp_unset_and_set_config( + pnp_devfn_t dev, uint8_t reg, uint8_t unset, uint8_t set) +{ + pnp_unset_and_set_index(dev >> 8, reg, unset, set); +} + static __always_inline void pnp_set_logical_device(pnp_devfn_t dev) { @@ -32,13 +37,13 @@ void pnp_set_logical_device(pnp_devfn_t dev) static __always_inline void pnp_set_enable(pnp_devfn_t dev, int enable) { - pnp_write_config(dev, 0x30, enable?0x1:0x0); + pnp_write_config(dev, PNP_IDX_EN, enable?0x1:0x0); } static __always_inline int pnp_read_enable(pnp_devfn_t dev) { - return !!pnp_read_config(dev, 0x30); + return !!pnp_read_config(dev, PNP_IDX_EN); } static __always_inline diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 42c7e6ae45..3a7ccf09e6 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -109,7 +109,6 @@ static inline void *res2mmio(struct resource *res, unsigned long offset, const struct device *largest_resource(struct bus *bus, struct resource **result_res, unsigned long type_mask, unsigned long type); - /* Compute and allocate resources. This is the main resource allocator entry point. */ void allocate_resources(const struct device *root); diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 4bc80092b5..e113aec94a 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -3,6 +3,7 @@ #ifndef __DEVICE_SMBUS_HOST_H__ #define __DEVICE_SMBUS_HOST_H__ +#include #include #include diff --git a/src/include/device/soundwire.h b/src/include/device/soundwire.h index 85e3186219..6f966ae2f4 100644 --- a/src/include/device/soundwire.h +++ b/src/include/device/soundwire.h @@ -16,8 +16,7 @@ #ifndef __DEVICE_SOUNDWIRE_H__ #define __DEVICE_SOUNDWIRE_H__ -#include -#include +#include /** * enum soundwire_limits - Limits on number of SoundWire devices in topology. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index bd0d151508..ae30c59710 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -4,6 +4,7 @@ #ifndef __DEVICE_TREE_H__ #define __DEVICE_TREE_H__ +#include #include #include @@ -42,8 +43,6 @@ struct fdt_property uint32_t size; }; - - /* * Unflattened device tree structures. */ @@ -87,8 +86,6 @@ struct device_tree struct device_tree_node *root; }; - - /* * Flattened device tree functions. These generally return the number of bytes * which were consumed reading the requested value. @@ -108,8 +105,6 @@ int fdt_skip_node(const void *blob, uint32_t offset); invalidates the unflattened one. */ struct device_tree *fdt_unflatten(const void *blob); - - /* * Unflattened device tree functions. */ diff --git a/src/include/elog.h b/src/include/elog.h index ab855448af..8c50e00ba5 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -3,6 +3,8 @@ #ifndef ELOG_H_ #define ELOG_H_ +#include + #define MAX_EVENT_SIZE 0x7F /* End of log */ @@ -77,7 +79,7 @@ #define ELOG_WAKE_SOURCE_PME 0x01 #define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 #define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_GPE 0x04 #define ELOG_WAKE_SOURCE_SMBUS 0x05 #define ELOG_WAKE_SOURCE_PWRBTN 0x06 #define ELOG_WAKE_SOURCE_PME_HDA 0x07 @@ -117,6 +119,7 @@ #define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b +#define ELOG_WAKE_SOURCE_GPIO 0x2c struct elog_event_data_wake { u8 source; @@ -199,7 +202,6 @@ struct elog_event_mem_cache_update { #define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HR 0xb5 - struct elog_event_extended_event { u8 event_type; u32 event_complement; diff --git a/src/include/fit_payload.h b/src/include/fit_payload.h index 8632b05b82..4ebe3ce78e 100644 --- a/src/include/fit_payload.h +++ b/src/include/fit_payload.h @@ -4,7 +4,6 @@ #define __FIT_PAYLOAD_H_ #include -#include void fit_payload(struct prog *payload); diff --git a/src/include/fmap.h b/src/include/fmap.h index a07bae22f5..761e742f56 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -5,6 +5,8 @@ #include #include +#include +#include /* Locate the named area in the fmap and fill in a region device representing * that area. The region is a sub-region of the readonly boot media. Return diff --git a/src/include/fw_config.h b/src/include/fw_config.h index d41afd6c5d..81980b93ae 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -40,6 +40,21 @@ struct fw_config { */ bool fw_config_probe(const struct fw_config *match); +/** + * fw_config_for_each_found() - Call a callback for each fw_config field found + * @cb: The callback function + * @arg: A context argument that is passed to the callback + */ +void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg); + +/** + * fw_config_get_found() - Return a pointer to the fw_config struct for a given field. + * @field_mask: A field mask from static.h, e.g., FW_CONFIG_FIELD_FEATURE_MASK + * + * Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL. +*/ +const struct fw_config *fw_config_get_found(uint32_t field_mask); + #else static inline bool fw_config_probe(const struct fw_config *match) diff --git a/src/include/imd.h b/src/include/imd.h index 314d223341..df669fd366 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -40,11 +40,13 @@ struct imd_entry; struct imd; +static const size_t LIMIT_ALIGN = 4096; + /* * Initialize handle to use for working with an imd. Upper limit is the - * exclusive address to start allocating down from. This function needs - * to be called at least once before any other imd related functions - * can be used. + * exclusive address (aligned down to LIMIT_ALIGN) to start allocating down + * from. This function needs to be called at least once before any other imd + * related functions can be used. */ void imd_handle_init(struct imd *imd, void *upper_limit); @@ -60,7 +62,9 @@ void imd_handle_init_partial_recovery(struct imd *imd); * Create an empty imd with a specified root_size and each entry is aligned to * the provided entry_align. As noted above the root size encompasses the * root pointer and root block leading to the number of imd entries being a - * function of the root_size parameter. + * function of the root_size parameter. Please note, that one entry is allocated + * for covering root region, thus caller should consider this calculating + * root_size. */ int imd_create_empty(struct imd *imd, size_t root_size, size_t entry_align); @@ -101,14 +105,14 @@ const struct imd_entry *imd_entry_find(const struct imd *imd, uint32_t id); const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, uint32_t id, size_t size); -/* Returns size of entry or 0 on failure. */ -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); +/* Returns size of entry. */ +size_t imd_entry_size(const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); /* Returns id for the imd entry. */ -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); +uint32_t imd_entry_id(const struct imd_entry *entry); /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); diff --git a/src/include/input-event-codes.h b/src/include/input-event-codes.h index 006c2627ad..abb1e08a5b 100644 --- a/src/include/input-event-codes.h +++ b/src/include/input-event-codes.h @@ -870,7 +870,6 @@ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) diff --git a/src/include/list.h b/src/include/list.h index a8990354d7..394487831c 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -4,9 +4,6 @@ #ifndef __LIST_H__ #define __LIST_H__ -#include -#include - struct list_node { struct list_node *next; struct list_node *prev; diff --git a/src/include/memory_info.h b/src/include/memory_info.h index a9891189d2..1ba73291a8 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -5,6 +5,7 @@ #define _MEMORY_INFO_H_ #include +#include #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 33 @@ -27,6 +28,10 @@ struct dimm_info { * See the smbios.h smbios_memory_type enum. */ uint16_t ddr_type; + /* + * ddr_frequency is deprecated. + * Use max_speed_mts and configured_speed_mts instead. + */ uint16_t ddr_frequency; uint8_t rank_per_dimm; uint8_t channel_num; @@ -78,11 +83,35 @@ struct dimm_info { * Voltage Level */ uint16_t vdd_voltage; + /* + * Max speed in MT/s + * If the value is 0, ddr_frequency should be used instead. + */ + uint16_t max_speed_mts; + /* + * Configured speed in MT/s + * If the value is 0, ddr_frequency should be used instead. + */ + uint16_t configured_speed_mts; } __packed; struct memory_info { + /* controller specific */ + bool ecc_capable; + /* Maximum capacity the DRAM controller/mainboard supports */ + uint32_t max_capacity_mib; + /* Maximum number of DIMMs the DRAM controller/mainboard supports */ + uint16_t number_of_devices; + + /* active DIMM configuration */ uint8_t dimm_cnt; struct dimm_info dimm[DIMM_INFO_TOTAL]; } __packed; +/* + * mainboard_get_dram_part_num returns a DRAM part number override string + * return NULL = no part number override provided by mainboard + * return non-NULL = pointer to a string terminating in '\0' + */ +const char *mainboard_get_dram_part_num(void); #endif diff --git a/src/include/memrange.h b/src/include/memrange.h index 2b8c00ecf8..80db5985ed 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -4,6 +4,7 @@ #include #include +#include /* A memranges structure consists of a list of range_entry(s). The structure * is exposed so that a memranges can be used on the stack if needed. */ @@ -81,7 +82,6 @@ static inline bool memranges_is_empty(const struct memranges *ranges) #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) - /* Initialize memranges structure providing an optional array of range_entry * to use as the free list. Additionally, it accepts an align parameter that * represents the required alignment(log 2) of addresses. */ diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 5131cbccd2..f1e6b52010 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -14,18 +14,37 @@ enum { /* * It's up to the caller to decide when to retrieve and stash data. There is - * differentiation on recovery mode CONFIG_HAS_RECOVERY_MRC_CACHE, but that's + * differentiation on recovery mode CONFIG(HAS_RECOVERY_MRC_CACHE), but that's * only for locating where to retrieve and save the data. If a platform doesn't * want to update the data then it shouldn't stash the data for saving. * Similarly, if the platform doesn't need the data for booting because of a * policy don't request the data. */ -/* Get and stash data for saving provided the type passed in. The functions - * return < 0 on error, 0 on success. */ -int mrc_cache_get_current(int type, uint32_t version, - struct region_device *rdev); +/* Get and stash data for saving provided the type passed in. */ + +/** + * mrc_cache_load_current + * + * Fill in the buffer with the latest slot data. This will be a + * common entry point for ARM platforms. Returns < 0 on error, size + * of the returned data on success. + */ +ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer, + size_t buffer_size); +/** + * mrc_cache_mmap_leak + * + * Return a pointer to a buffer with the latest slot data. An mmap + * will be executed (without a matching unmap). This will be a common + * entry point for platforms where mmap is considered a noop, like x86 + */ +void *mrc_cache_current_mmap_leak(int type, uint32_t version, + size_t *data_size); +/** + * Returns < 0 on error, 0 on success. + */ int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size); + size_t size); #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 30cb274874..335580144c 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -219,7 +219,6 @@ enum { SPEAKER_TOP_BACK_RIGHT = 1 << 17, }; - /* Supporting structures. Only SoC/chipset and the library code directly should * be manipulating these structures. */ struct sub_format { diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index c3d0a93b5e..9268cd11fa 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -3,6 +3,8 @@ #ifndef PC80_I8259_H #define PC80_I8259_H +#include + /* * IRQ numbers and common usage * If an IRQ does not say it is 'Reserved' diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index a2c65cb4c0..2f94cc0213 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -17,7 +17,6 @@ #define RTC_REG_C 12 #define RTC_REG_D 13 - /********************************************************************** * register details **********************************************************************/ diff --git a/src/include/ramdetect.h b/src/include/ramdetect.h index 93c5db1382..55c81d08c5 100644 --- a/src/include/ramdetect.h +++ b/src/include/ramdetect.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include /* * Used in probe_ramsize(). This is a weak function and it's overridden for diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 59da0cb2ed..aa6bf80fa5 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -355,7 +355,6 @@ struct reg_script_bus_entry { #define REG_RES_XOR32(bar_, reg_, value_) \ REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) - #if CONFIG(SOC_INTEL_BAYTRAIL) /* * IO Sideband Function diff --git a/src/include/region_file.h b/src/include/region_file.h index 0df64e5593..a3cb79d044 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -4,6 +4,7 @@ #define REGION_FILE_H #include +#include #include /* @@ -30,9 +31,22 @@ int region_file_init(struct region_file *f, const struct region_device *p); */ int region_file_data(const struct region_file *f, struct region_device *rdev); +/* + * Create region file entry struct to insert multiple data buffers + * into the same region_file. + */ +struct update_region_file_entry { + /* size of this entry */ + size_t size; + /* data pointer */ + const void *data; +}; + /* Update region file with latest data. Returns < 0 on error, 0 on success. */ -int region_file_update_data(struct region_file *f, const void *buf, - size_t size); +int region_file_update_data_arr(struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries); +int region_file_update_data(struct region_file *f, const void *buf, size_t size); /* Declared here for easy object allocation. */ struct region_file { diff --git a/src/include/rules.h b/src/include/rules.h index 160829efa4..d30b2b896a 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -3,6 +3,12 @@ #ifndef _RULES_H #define _RULES_H +#if defined(__TIMELESS__) +#define ENV_TIMELESS 1 +#else +#define ENV_TIMELESS 0 +#endif + /* Useful helpers to tell whether the code is executing in bootblock, * romstage, ramstage or SMM. */ @@ -72,7 +78,11 @@ #define ENV_RMODULE 0 #define ENV_POSTCAR 0 #define ENV_LIBAGESA 0 +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#define ENV_STRING "verstage-before-bootblock" +#else #define ENV_STRING "verstage" +#endif #elif defined(__RAMSTAGE__) #define ENV_DECOMPRESSOR 0 @@ -261,6 +271,20 @@ /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) +/* Set USER_SPACE in the makefile for the rare code that runs in userspace */ +#if defined(__USER_SPACE__) +#define ENV_USER_SPACE 1 +#else +#define ENV_USER_SPACE 0 +#endif + +/* Define the first stage to run */ +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#define ENV_INITIAL_STAGE ENV_SEPARATE_VERSTAGE +#else +#define ENV_INITIAL_STAGE ENV_BOOTBLOCK +#endif + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/include/smbios.h b/src/include/smbios.h index ed09d642b9..8033d6ca98 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -54,6 +54,13 @@ const char *smbios_chassis_version(void); const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); + +unsigned int smbios_processor_external_clock(void); +unsigned int smbios_processor_characteristics(void); +struct cpuid_result; +unsigned int smbios_processor_family(struct cpuid_result res); + /* Used by mainboard to add port information of type 8 */ struct port_information; int smbios_write_type8(unsigned long *current, int *handle, @@ -247,6 +254,19 @@ struct smbios_entry { u8 smbios_bcd_revision; } __packed; +struct smbios_entry30 { + u8 anchor[5]; + u8 checksum; + u8 length; + u8 major_version; + u8 minor_version; + u8 smbios_doc_rev; + u8 entry_point_rev; + u8 reserved; + u32 struct_table_length; + u64 struct_table_address; +} __packed; + struct smbios_type0 { u8 type; u8 length; @@ -402,9 +422,17 @@ struct smbios_type4 { u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; +/* defines for smbios_type4 */ + +#define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) +#define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) + /* defines for supported_sram_type/current_sram_type */ #define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) @@ -828,6 +856,19 @@ struct smbios_type17 { u8 eos[2]; } __packed; +struct smbios_type19 { + u8 type; + u8 length; + u16 handle; + u32 starting_address; + u32 ending_address; + u16 memory_array_handle; + u8 partition_width; + u64 extended_starting_address; + u64 extended_ending_address; + u8 eos[2]; +} __packed; + struct smbios_type32 { u8 type; u8 length; diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index ed70cb7baa..5e78ae4462 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -31,7 +31,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_set(v, i) (((v)->counter) = (i)) - /** * atomic_inc - increment atomic variable * @param v: pointer of type atomic_t @@ -41,7 +40,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_inc(v) (((v)->counter)++) - /** * atomic_dec - decrement atomic variable * @param v: pointer of type atomic_t @@ -51,7 +49,6 @@ typedef struct { int counter; } atomic_t; */ #define atomic_dec(v) (((v)->counter)--) - #endif /* CONFIG_SMP */ #endif /* SMP_ATOMIC_H */ diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index 98ab3a778a..8554aa0589 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -6,12 +6,10 @@ #else /* !CONFIG_SMP */ #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #endif #endif /* SMP_SPINLOCK_H */ diff --git a/src/include/spd.h b/src/include/spd.h index f46bde6522..9afb706c97 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -136,7 +136,6 @@ /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ #define SPD_tRFC 42 - /* SPD_MEMORY_TYPE values. */ enum spd_memory_type { SPD_MEMORY_TYPE_UNDEFINED = 0x00, diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index f8d7d68622..5465aadda4 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -4,6 +4,8 @@ #define __SPD_CACHE_H #include +#include +#include #define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE" #define SC_SPD_NUMS (CONFIG_DIMM_MAX) diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 35b02dbb3d..1061e9905e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -202,7 +202,7 @@ int chipset_volatile_group_begin(const struct spi_flash *flash); int chipset_volatile_group_end(const struct spi_flash *flash); /* Return spi_flash object reference for the boot device. This is only valid - * if CONFIG_BOOT_DEVICE_SPI_FLASH is enabled. */ + * if CONFIG(BOOT_DEVICE_SPI_FLASH) is enabled. */ const struct spi_flash *boot_device_spi_flash(void); /* Protect a region of spi flash using its controller, if available. Returns diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h index 028f6a351e..8f64e5eea9 100644 --- a/src/include/spi_sdcard.h +++ b/src/include/spi_sdcard.h @@ -3,6 +3,8 @@ #ifndef _SPI_SDCARD_H_ #define _SPI_SDCARD_H_ +#include + struct spi_sdcard { int type; struct spi_slave slave; diff --git a/src/include/stdbool.h b/src/include/stdbool.h index d7f9e643ea..3733527bd2 100644 --- a/src/include/stdbool.h +++ b/src/include/stdbool.h @@ -3,9 +3,6 @@ #ifndef __STDBOOL_H__ #define __STDBOOL_H__ -#include - - typedef _Bool bool; #define true 1 #define false 0 diff --git a/src/include/string.h b/src/include/string.h index 8eef0680cb..3cfa18d33c 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -29,6 +29,7 @@ int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, int maxlen); int strspn(const char *str, const char *spn); int strcspn(const char *str, const char *spn); +char *strstr(const char *haystack, const char *needle); char *strtok_r(char *str, const char *delim, char **ptr); char *strtok(char *str, const char *delim); long atol(const char *str); diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h index 661f3ee430..f26a0171f5 100644 --- a/src/include/superio/hwm5_conf.h +++ b/src/include/superio/hwm5_conf.h @@ -4,6 +4,7 @@ #define DEVICE_PNP_HWM5_CONF_H #include +#include /* The address/data register pair for the indirect/indexed IO space of the * hardware monitor (HWM) that does temperature and voltage sensing and fan @@ -11,14 +12,14 @@ * of the corresponding IO address region, but at offset 5 and 6. */ /* - * u8 pnp_read_hwm5_index(u16 port, u8 reg) + * u8 pnp_read_hwm5_index(u16 base, u8 reg) * Description: * This routine reads indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The result is then - * read from the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The result is then + * read from the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The I/O address of the port index register. + * @param[in] u16 base = The I/O address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[out] u8 result = The value read back from the data register. */ @@ -28,14 +29,14 @@ static inline u8 pnp_read_hwm5_index(u16 base, u8 reg) } /* - * void pnp_write_hwm5_index(u16 port, u8 reg, u8 value) + * void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) * Description: * This routine writes indexed I/O registers. The reg byte is written - * to the index register at I/O address = port + 5. The value byte is then - * written to the data register at I/O address = port + 6. + * to the index register at I/O address = base + 5. The value byte is then + * written to the data register at I/O address = base + 6. * * Parameters: - * @param[in] u16 base = The address of the port index register. + * @param[in] u16 base = The address of the base index register. * @param[in] u8 reg = The offset within the indexed space. * @param[in] u8 value = The value to be written to the data register. */ @@ -44,4 +45,32 @@ static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) pnp_write_index(base + 5, reg, value); } +/* + * void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set) + * Description: + * This routine unsets and sets bits from indexed I/O registers. The + * reg byte is written to the index register at I/O address = base + 5. + * The value byte to update is data register at I/O address = base + 6. + * + * Unlike and-then-or style operations, no bitwise negation is necessary + * to specify the bits to unset. Because the bitwise negation implicitly + * promotes operands to int before operating, one may have to explicitly + * downcast the result if the data width is smaller than that of an int. + * Since warnings are errors in coreboot, explicit casting is necessary. + * + * Performing said negation inside this routine alleviates this problem, + * while allowing the compiler to warn if the input parameters overflow. + * Casting outside this function would silence valid compiler warnings. + * + * Parameters: + * @param[in] u16 base = The address of the base index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register. + * @param[in] u8 set = Bitmask with ones to the bits to set from the data register. + */ +static inline void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set) +{ + pnp_unset_and_set_index(base + 5, reg, unset, set); +} + #endif /* DEVICE_PNP_HWM5_CONF_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index f84672ed22..371d84bf9b 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -13,8 +13,20 @@ extern u8 _dram[]; extern u8 _##name[]; \ extern u8 _e##name[]; +/* + * Regions can be declared optional if not all configurations provide them in + * memlayout and you want code to be able to check for their existence at + * runtime. Not every region that is architecture or platform-specific should + * use this -- only declare regions optional if the code *accessing* them runs + * both on configurations that have the region and those that don't. That code + * should then check (REGION_SIZE(name) != 0) before accessing it. + */ +#define DECLARE_OPTIONAL_REGION(name) \ + __weak extern u8 _##name[]; \ + __weak extern u8 _e##name[]; + DECLARE_REGION(sram) -DECLARE_REGION(timestamp) +DECLARE_OPTIONAL_REGION(timestamp) DECLARE_REGION(preram_cbmem_console) DECLARE_REGION(cbmem_init_hooks) DECLARE_REGION(stack) @@ -24,6 +36,17 @@ DECLARE_REGION(cbfs_cache) DECLARE_REGION(fmap_cache) DECLARE_REGION(tpm_tcpa_log) +#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) +DECLARE_REGION(bss) +DECLARE_REGION(asan_shadow) +#endif + +#if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE) +DECLARE_REGION(data) +DECLARE_REGION(heap) +DECLARE_REGION(asan_shadow) +#endif + /* Regions for execution units. */ DECLARE_REGION(payload) @@ -42,22 +65,14 @@ DECLARE_REGION(ramstage) DECLARE_REGION(pagetables) DECLARE_REGION(ttb) -DECLARE_REGION(ttb_subtables) +DECLARE_OPTIONAL_REGION(ttb_subtables) DECLARE_REGION(dma_coherent) DECLARE_REGION(soc_registers) DECLARE_REGION(framebuffer) DECLARE_REGION(pdpt) -DECLARE_REGION(opensbi) -DECLARE_REGION(bl31) - -/* - * Put this into a .c file accessing a linker script region to mark that region - * as "optional". If it is defined in memlayout.ld (or anywhere else), the - * values from that definition will be used. If not, start, end and size will - * all evaluate to 0. (We can't explicitly assign the symbols to 0 in the - * assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) - */ -#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name) +DECLARE_OPTIONAL_REGION(opensbi) +DECLARE_OPTIONAL_REGION(bl31) +DECLARE_REGION(transfer_buffer) /* Returns true when pre-RAM symbols are known to the linker. * (Does not necessarily mean that the memory is accessible.) */ diff --git a/src/include/thread.h b/src/include/thread.h index df307fa6f8..a2c7ed2085 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -2,7 +2,6 @@ #ifndef THREAD_H_ #define THREAD_H_ -#include #include #include #include diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 06c99acb3c..647cd13897 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -4,6 +4,7 @@ #define __TIMESTAMP_H__ #include +#include #if CONFIG(COLLECT_TIMESTAMPS) /* diff --git a/src/lib/Kconfig b/src/lib/Kconfig index a6fb1f149e..d6e7e51d5c 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -30,12 +30,11 @@ config FLATTENED_DEVICE_TREE Selected by features that require to parse and manipulate a flattened devicetree in ramstage. -config GENERIC_SPD_BIN +config HAVE_SPD_IN_CBFS bool help If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. + and locating it runtime to load SPD. config DIMM_MAX int diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 72d4f2414c..c228f2a9f4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -7,6 +7,27 @@ ramstage-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined endif +# Ensure that asan_shadow_offset_callback patch is applied to GCC before ASan is used. +CFLAGS_asan += -fsanitize=kernel-address --param asan-use-shadow-offset-callback=1 \ + --param asan-stack=1 -fsanitize-address-use-after-scope \ + --param asan-instrumentation-with-call-threshold=0 \ + --param use-after-scope-direct-emission-threshold=0 + +ifeq ($(CONFIG_ASAN_IN_ROMSTAGE),y) +romstage-y += asan.c +CFLAGS_asan += --param asan-globals=0 +CFLAGS_romstage += $(CFLAGS_asan) +# Allow memory access without __asan_load and __asan_store checks. +$(obj)/romstage/lib/asan.o: CFLAGS_asan = +endif + +ifeq ($(CONFIG_ASAN_IN_RAMSTAGE),y) +ramstage-y += asan.c +CFLAGS_asan += --param asan-globals=1 +CFLAGS_ramstage += $(CFLAGS_asan) +$(obj)/ramstage/lib/asan.o: CFLAGS_asan = +endif + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -47,10 +68,7 @@ verstage-y += libgcc.c verstage-y += memcmp.c verstage-y += string.c -# TODO: Remove this when PSP bootblock timestamps are implemented. -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),) verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -endif verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -82,6 +100,7 @@ ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c romstage-y += selfboot.c romstage-y += stack.c +romstage-y += rtc.c ramstage-y += rtc.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -332,20 +351,24 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c -ifeq ($(CONFIG_GENERIC_SPD_BIN),y) +ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y) LIB_SPD_BIN = $(obj)/spd.bin LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) # Include spd ROM data $(LIB_SPD_BIN): $(LIB_SPD_DEPS) + test -n "$(SPD_SOURCES)" || \ + (echo "HAVE_SPD_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) + test -n "$(LIB_SPD_DEPS)" || \ + (echo "SPD_SOURCES is set but no SPD file was found" && exit 1) for f in $(LIB_SPD_DEPS); \ do for c in $$(cat $$f | grep --binary-files=text -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ + do printf $$(printf '\\%o' 0x$$c); \ done; \ done > $@ -cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +cbfs-files-y += spd.bin spd.bin-file := $(LIB_SPD_BIN) spd.bin-type := spd endif diff --git a/src/lib/asan.c b/src/lib/asan.c new file mode 100644 index 0000000000..6de0de1409 --- /dev/null +++ b/src/lib/asan.c @@ -0,0 +1,438 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * Address sanitizer support. + * + * Parts of this file are based on mm/kasan + * from the Linux kernel 4.19.137. + * + */ + +#include +#include +#include +#include + +static inline void *asan_mem_to_shadow(const void *addr) +{ +#if ENV_ROMSTAGE + return (void *)((uintptr_t)&_asan_shadow + (((uintptr_t)addr - + (uintptr_t)&_car_region_start) >> ASAN_SHADOW_SCALE_SHIFT)); +#elif ENV_RAMSTAGE + return (void *)((uintptr_t)&_asan_shadow + (((uintptr_t)addr - + (uintptr_t)&_data) >> ASAN_SHADOW_SCALE_SHIFT)); +#endif +} + +static inline const void *asan_shadow_to_mem(const void *shadow_addr) +{ +#if ENV_ROMSTAGE + return (void *)((uintptr_t)&_car_region_start + (((uintptr_t)shadow_addr - + (uintptr_t)&_asan_shadow) << ASAN_SHADOW_SCALE_SHIFT)); +#elif ENV_RAMSTAGE + return (void *)((uintptr_t)&_data + (((uintptr_t)shadow_addr - + (uintptr_t)&_asan_shadow) << ASAN_SHADOW_SCALE_SHIFT)); +#endif +} + +static void asan_poison_shadow(const void *address, size_t size, u8 value) +{ + void *shadow_start, *shadow_end; + + shadow_start = asan_mem_to_shadow(address); + shadow_end = asan_mem_to_shadow(address + size); + + __builtin_memset(shadow_start, value, shadow_end - shadow_start); +} + +void asan_unpoison_shadow(const void *address, size_t size) +{ + asan_poison_shadow(address, size, 0); + + if (size & ASAN_SHADOW_MASK) { + u8 *shadow = (u8 *)asan_mem_to_shadow(address + size); + *shadow = size & ASAN_SHADOW_MASK; + } +} + +static __always_inline bool memory_is_poisoned_1(unsigned long addr) +{ + s8 shadow_value = *(s8 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(shadow_value)) { + s8 last_accessible_byte = addr & ASAN_SHADOW_MASK; + return unlikely(last_accessible_byte >= shadow_value); + } + + return false; +} + +static __always_inline bool memory_is_poisoned_2_4_8(unsigned long addr, + unsigned long size) +{ + u8 *shadow_addr = (u8 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(((addr + size - 1) & ASAN_SHADOW_MASK) < size - 1)) + return *shadow_addr || memory_is_poisoned_1(addr + size - 1); + + return memory_is_poisoned_1(addr + size - 1); +} + +static __always_inline bool memory_is_poisoned_16(unsigned long addr) +{ + u16 *shadow_addr = (u16 *)asan_mem_to_shadow((void *)addr); + + if (unlikely(!IS_ALIGNED(addr, ASAN_SHADOW_SCALE_SIZE))) + return *shadow_addr || memory_is_poisoned_1(addr + 15); + + return *shadow_addr; +} + +static __always_inline unsigned long bytes_is_nonzero(const u8 *start, + size_t size) +{ + while (size) { + if (unlikely(*start)) + return (unsigned long)start; + start++; + size--; + } + + return 0; +} + +static __always_inline unsigned long memory_is_nonzero(const void *start, + const void *end) +{ + unsigned int words; + unsigned long ret; + unsigned int prefix = (unsigned long)start % 8; + + if (end - start <= 16) + return bytes_is_nonzero(start, end - start); + + if (prefix) { + prefix = 8 - prefix; + ret = bytes_is_nonzero(start, prefix); + if (unlikely(ret)) + return ret; + start += prefix; + } + + words = (end - start) / 8; + while (words) { + if (unlikely(*(u64 *)start)) + return bytes_is_nonzero(start, 8); + start += 8; + words--; + } + + return bytes_is_nonzero(start, (end - start) % 8); +} + +static __always_inline bool memory_is_poisoned_n(unsigned long addr, + size_t size) +{ + unsigned long ret; + + ret = memory_is_nonzero(asan_mem_to_shadow((void *)addr), + asan_mem_to_shadow((void *)addr + size - 1) + 1); + + if (unlikely(ret)) { + unsigned long last_byte = addr + size - 1; + s8 *last_shadow = (s8 *)asan_mem_to_shadow((void *)last_byte); + + if (unlikely(ret != (unsigned long)last_shadow || + ((long)(last_byte & ASAN_SHADOW_MASK) >= *last_shadow))) + return true; + } + return false; +} + +static __always_inline bool memory_is_poisoned(unsigned long addr, size_t size) +{ + if (__builtin_constant_p(size)) { + switch (size) { + case 1: + return memory_is_poisoned_1(addr); + case 2: + case 4: + case 8: + return memory_is_poisoned_2_4_8(addr, size); + case 16: + return memory_is_poisoned_16(addr); + default: + assert(0); + } + } + + return memory_is_poisoned_n(addr, size); +} + +static const void *find_first_bad_addr(const void *addr, size_t size) +{ + u8 shadow_val = *(u8 *)asan_mem_to_shadow(addr); + const void *first_bad_addr = addr; + + while (!shadow_val && first_bad_addr < addr + size) { + first_bad_addr += ASAN_SHADOW_SCALE_SIZE; + shadow_val = *(u8 *)asan_mem_to_shadow(first_bad_addr); + } + return first_bad_addr; +} + +static const char *get_shadow_bug_type(const void *addr, size_t size) +{ + const char *bug_type = "unknown-crash"; + u8 *shadow_addr; + const void *first_bad_addr; + + if (addr < asan_shadow_to_mem((void *) &_asan_shadow)) + return bug_type; + + first_bad_addr = find_first_bad_addr(addr, size); + + shadow_addr = (u8 *)asan_mem_to_shadow(first_bad_addr); + + if (*shadow_addr > 0 && *shadow_addr <= ASAN_SHADOW_SCALE_SIZE - 1) + shadow_addr++; + + switch (*shadow_addr) { + case 0 ... ASAN_SHADOW_SCALE_SIZE - 1: + bug_type = "out-of-bounds"; + break; + case ASAN_GLOBAL_REDZONE: + bug_type = "global-out-of-bounds"; + break; + case ASAN_STACK_LEFT: + case ASAN_STACK_MID: + case ASAN_STACK_RIGHT: + case ASAN_STACK_PARTIAL: + bug_type = "stack-out-of-bounds"; + break; + case ASAN_USE_AFTER_SCOPE: + bug_type = "use-after-scope"; + break; + default: + bug_type = "unknown-crash"; + } + + return bug_type; +} + +void asan_report(unsigned long addr, size_t size, bool is_write, + unsigned long ip) +{ + const char *bug_type = get_shadow_bug_type((void *) addr, size); + printk(BIOS_ERR, "\n"); + printk(BIOS_ERR, "ASan: %s in %p\n", bug_type, (void *) ip); + printk(BIOS_ERR, "%s of %zu byte%s at addr %p\n", + is_write ? "Write" : "Read", size, (size > 1 ? "s" : ""), + (void *) addr); + printk(BIOS_ERR, "\n"); +} + +static __always_inline void check_memory_region_inline(unsigned long addr, + size_t size, bool write, + unsigned long ret_ip) +{ +#if ENV_ROMSTAGE + if (((uintptr_t)addr < (uintptr_t)&_car_region_start) || + ((uintptr_t)addr > (uintptr_t)&_ebss)) + return; +#elif ENV_RAMSTAGE + if (((uintptr_t)addr < (uintptr_t)&_data) || + ((uintptr_t)addr > (uintptr_t)&_eheap)) + return; +#endif + if (unlikely(size == 0)) + return; + + if (unlikely((void *)addr < + asan_shadow_to_mem((void *) &_asan_shadow))) { + asan_report(addr, size, write, ret_ip); + return; + } + + if (likely(!memory_is_poisoned(addr, size))) + return; + + asan_report(addr, size, write, ret_ip); +} + +void check_memory_region(unsigned long addr, size_t size, bool write, + unsigned long ret_ip) +{ + check_memory_region_inline(addr, size, write, ret_ip); +} + +uintptr_t __asan_shadow_offset(uintptr_t addr) +{ +#if ENV_ROMSTAGE + return (uintptr_t)&_asan_shadow - (((uintptr_t)&_car_region_start) >> + ASAN_SHADOW_SCALE_SHIFT); +#elif ENV_RAMSTAGE + return (uintptr_t)&_asan_shadow - (((uintptr_t)&_data) >> + ASAN_SHADOW_SCALE_SHIFT); +#endif +} + +static void register_global(struct asan_global *global) +{ + size_t aligned_size = ALIGN_UP(global->size, ASAN_SHADOW_SCALE_SIZE); + + asan_unpoison_shadow(global->beg, global->size); + + asan_poison_shadow(global->beg + aligned_size, + global->size_with_redzone - aligned_size, + ASAN_GLOBAL_REDZONE); +} + +void __asan_register_globals(struct asan_global *globals, size_t size) +{ + int i; + + for (i = 0; i < size; i++) + register_global(&globals[i]); +} + +void __asan_unregister_globals(struct asan_global *globals, size_t size) +{ +} + +/* + * GCC adds constructors invoking __asan_register_globals() and passes + * information about global variable (address, size, size with redzone ...) + * to it so we could poison variable's redzone. + * This function calls those constructors. + */ +#if ENV_RAMSTAGE +static void asan_ctors(void) +{ + extern long __CTOR_LIST__; + typedef void (*func_ptr)(void); + func_ptr *ctor = (func_ptr *) &__CTOR_LIST__; + if (ctor == NULL) + return; + + for (; *ctor != (func_ptr) 0; ctor++) + (*ctor)(); +} +#endif + +void asan_init(void) +{ +#if ENV_ROMSTAGE + size_t size = (size_t)&_ebss - (size_t)&_car_region_start; + asan_unpoison_shadow((void *)&_car_region_start, size); +#elif ENV_RAMSTAGE + size_t size = (size_t)&_eheap - (size_t)&_data; + asan_unpoison_shadow((void *)&_data, size); + asan_ctors(); +#endif +} + +void __asan_poison_stack_memory(const void *addr, size_t size) +{ + asan_poison_shadow(addr, ALIGN_UP(size, ASAN_SHADOW_SCALE_SIZE), + ASAN_USE_AFTER_SCOPE); +} + +void __asan_unpoison_stack_memory(const void *addr, size_t size) +{ + asan_unpoison_shadow(addr, size); +} + +#define DEFINE_ASAN_LOAD_STORE(size) \ + void __asan_load##size(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, false, _RET_IP_);\ + } \ + void __asan_load##size##_noabort(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, false, _RET_IP_);\ + } \ + void __asan_store##size(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, true, _RET_IP_); \ + } \ + void __asan_store##size##_noabort(unsigned long addr) \ + { \ + check_memory_region_inline(addr, size, true, _RET_IP_); \ + } + +DEFINE_ASAN_LOAD_STORE(1); +DEFINE_ASAN_LOAD_STORE(2); +DEFINE_ASAN_LOAD_STORE(4); +DEFINE_ASAN_LOAD_STORE(8); +DEFINE_ASAN_LOAD_STORE(16); + +void __asan_loadN(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, false, _RET_IP_); +} + +void __asan_storeN(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, true, _RET_IP_); +} + +void __asan_loadN_noabort(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, false, _RET_IP_); +} + +void __asan_storeN_noabort(unsigned long addr, size_t size) +{ + check_memory_region(addr, size, true, _RET_IP_); +} + +void __asan_handle_no_return(void) +{ +} + +#define DEFINE_ASAN_SET_SHADOW(byte) \ + void __asan_set_shadow_##byte(const void *addr, size_t size) \ + { \ + __builtin_memset((void *)addr, 0x##byte, size); \ + } + +DEFINE_ASAN_SET_SHADOW(00); +DEFINE_ASAN_SET_SHADOW(f1); +DEFINE_ASAN_SET_SHADOW(f2); +DEFINE_ASAN_SET_SHADOW(f3); +DEFINE_ASAN_SET_SHADOW(f5); +DEFINE_ASAN_SET_SHADOW(f8); + +#define DEFINE_ASAN_REPORT_LOAD(size) \ +void __asan_report_load##size##_noabort(unsigned long addr) \ +{ \ + asan_report(addr, size, false, _RET_IP_); \ +} + +#define DEFINE_ASAN_REPORT_STORE(size) \ +void __asan_report_store##size##_noabort(unsigned long addr) \ +{ \ + asan_report(addr, size, true, _RET_IP_); \ +} + +DEFINE_ASAN_REPORT_LOAD(1); +DEFINE_ASAN_REPORT_LOAD(2); +DEFINE_ASAN_REPORT_LOAD(4); +DEFINE_ASAN_REPORT_LOAD(8); +DEFINE_ASAN_REPORT_LOAD(16); +DEFINE_ASAN_REPORT_STORE(1); +DEFINE_ASAN_REPORT_STORE(2); +DEFINE_ASAN_REPORT_STORE(4); +DEFINE_ASAN_REPORT_STORE(8); +DEFINE_ASAN_REPORT_STORE(16); + +void __asan_report_load_n_noabort(unsigned long addr, size_t size) +{ + asan_report(addr, size, false, _RET_IP_); +} + +void __asan_report_store_n_noabort(unsigned long addr, size_t size) +{ + asan_report(addr, size, true, _RET_IP_); +} diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 1c433d008e..1509c8cb59 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -10,8 +10,6 @@ #include #include -DECLARE_OPTIONAL_REGION(timestamp); - __weak void bootblock_mainboard_early_init(void) { /* no-op */ } __weak void bootblock_soc_early_init(void) { /* do nothing */ } __weak void bootblock_soc_init(void) { /* do nothing */ } @@ -25,7 +23,7 @@ __weak void bootblock_mainboard_init(void) { /* do nothing */ } * entered from C code. This function assumes that the timer has already been * initialized, so it does not call init_timer(). */ -static void bootblock_main_with_timestamp(uint64_t base_timestamp, +void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index fa1f8bc6fd..1fe23c2828 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -231,15 +231,15 @@ void *bootmem_allocate_buffer(size_t size) size = ALIGN(size, 4096); region = NULL; memranges_each_entry(r, &bootmem) { + if (range_entry_base(r) >= max_addr) + break; + if (range_entry_size(r) < size) continue; if (range_entry_tag(r) != BM_MEM_RAM) continue; - if (range_entry_base(r) >= max_addr) - continue; - end = range_entry_end(r); if (end > max_addr) end = max_addr; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index cb66f81d99..35193d0ecf 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -4,8 +4,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -296,10 +296,16 @@ int cbfs_prog_stage_load(struct prog *pstage) foffset = 0; foffset += sizeof(stage); + /* cbfs_stage fields are written in little endian despite the other + cbfs data types being encoded in big endian. */ + stage.compression = read_le32(&stage.compression); + stage.entry = read_le64(&stage.entry); + stage.load = read_le64(&stage.load); + stage.len = read_le32(&stage.len); + stage.memlen = read_le32(&stage.memlen); + assert(fsize == stage.len); - /* Note: cbfs_stage fields are currently in the endianness of the - * running processor. */ load = (void *)(uintptr_t)stage.load; entry = (void *)(uintptr_t)stage.entry; diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2fb1e9ee90..d498597d13 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -111,7 +111,7 @@ void stage_cache_get_raw(int stage_id, void **base, size_t *size) } *base = imd_entry_at(imd, e); - *size = imd_entry_size(imd, e); + *size = imd_entry_size(e); } void stage_cache_load_stage(int stage_id, struct prog *stage) @@ -141,7 +141,7 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) } c = imd_entry_at(imd, e); - size = imd_entry_size(imd, e); + size = imd_entry_size(e); memcpy((void *)(uintptr_t)meta->load_addr, c, size); diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 671a962c25..377123afdc 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -46,6 +46,10 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) if (CONFIG(NO_FMAP_CACHE)) return; + /* No need to use FMAP cache in SMM */ + if (ENV_SMM) + return; + if (!ENV_ROMSTAGE_OR_BEFORE) { /* We get here if ramstage makes an FMAP access before calling cbmem_initialize(). We should avoid letting it come to that, @@ -56,9 +60,8 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev) } struct fmap *fmap = (struct fmap *)_fmap_cache; - if (!ENV_BOOTBLOCK) { - /* NOTE: This assumes that for all platforms running this code, - the bootblock is the first stage and the bootblock will make + if (!(ENV_INITIAL_STAGE)) { + /* NOTE: This assumes that the first stage will make at least one FMAP access (usually from finding CBFS). */ if (!check_signature(fmap)) goto register_cache; diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index e97cfdc72a..ec3205958d 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include #include +#include #include #include @@ -66,6 +68,40 @@ bool fw_config_probe(const struct fw_config *match) } #if ENV_RAMSTAGE + +/* + * The maximum number of fw_config fields is limited by the 32-bit mask that is used to + * represent them. + */ +#define MAX_CACHE_ELEMENTS (8 * sizeof(uint32_t)) + +static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS]; + +static size_t probe_index(uint32_t mask) +{ + assert(mask); + return __ffs(mask); +} + +const struct fw_config *fw_config_get_found(uint32_t field_mask) +{ + const struct fw_config *config; + config = cached_configs[probe_index(field_mask)]; + if (config && config->mask == field_mask) + return config; + + return NULL; +} + +void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg) +{ + size_t i; + + for (i = 0; i < MAX_CACHE_ELEMENTS; ++i) + if (cached_configs[i]) + cb(cached_configs[i], arg); +} + static void fw_config_init(void *unused) { struct device *dev; @@ -80,6 +116,7 @@ static void fw_config_init(void *unused) for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { if (fw_config_probe(probe)) { match = true; + cached_configs[probe_index(probe->mask)] = probe; break; } } @@ -90,5 +127,5 @@ static void fw_config_init(void *unused) } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 101aec9b7f..14f3e3ec3b 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -82,7 +82,7 @@ static int fseek(FILE *stream, long offset, int whence) static long ftell(FILE *stream) { /* ftell should currently not be called */ - gcc_assert(0); + BUG(); #if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "ftell %s\n", stream->filename); #endif diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 3f3ae60d91..801a3b3b9c 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -114,6 +114,12 @@ uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first) printk(BIOS_DEBUG, "%c ", tristate_char[temp]); result = (result * 3) + temp; + /* Disable pull to avoid wasting power. For HiZ we leave the + pull-down enabled, since letting them float freely back and + forth may waste power in the SoC's GPIO input logic. */ + if (temp != Z) + gpio_input(gpio[index]); + /* * For binary_first we keep track of the normal ternary result * and whether we found any pin that was a Z. We also determine @@ -159,10 +165,6 @@ uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first) printk(BIOS_DEBUG, "= %d (%s base3 number system)\n", result, binary_first ? "binary_first" : "standard"); - /* Disable pull up / pull down to conserve power */ - for (index = 0; index < num_gpio; ++index) - gpio_input(gpio[index]); - return result; } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 4276027a9f..3fe50c9bb6 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -169,9 +169,9 @@ static boot_state_t bs_os_resume(void *wake_vector) if (CONFIG(HAVE_ACPI_RESUME)) { arch_bootstate_coreboot_exit(); acpi_resume(wake_vector); + /* We will not come back. */ } - - return BS_WRITE_TABLES; + die("Failed OS resume\n"); } static boot_state_t bs_write_tables(void *arg) diff --git a/src/lib/imd.c b/src/lib/imd.c index e19c03d0b7..02779651c9 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -13,7 +13,6 @@ static const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; static const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; static const uint32_t SMALL_REGION_ID = CBMEM_ID_IMD_SMALL; -static const size_t LIMIT_ALIGN = 4096; /* In-memory data structures. */ struct imd_root_pointer { @@ -145,10 +144,11 @@ static int imdr_create_empty(struct imdr *imdr, size_t root_size, /* * root_size needs to be large enough to accommodate root pointer and - * root book keeping structure. The caller needs to ensure there's - * enough room for tracking individual allocations. + * root book keeping structure. Furthermore, there needs to be a space + * for at least one entry covering root region. The caller needs to + * ensure there's enough room for tracking individual allocations. */ - if (root_size < (sizeof(*rp) + sizeof(*r))) + if (root_size < (sizeof(*rp) + sizeof(*r) + sizeof(*e))) return -1; /* For simplicity don't allow sizes or alignments to exceed LIMIT_ALIGN. @@ -201,9 +201,8 @@ static int imdr_recover(struct imdr *imdr) r = relative_pointer(rp, rp->root_offset); - /* Confirm the root and root pointer are just under the limit. */ - if (ALIGN_UP((uintptr_t)&r->entries[r->max_entries], LIMIT_ALIGN) != - imdr->limit) + /* Ensure that root is just under the root pointer */ + if ((intptr_t)rp - (intptr_t)&r->entries[r->max_entries] > sizeof(struct imd_entry)) return -1; if (r->num_entries > r->max_entries) @@ -288,8 +287,7 @@ static int imdr_limit_size(struct imdr *imdr, size_t max_size) return 0; } -static size_t imdr_entry_size(const struct imdr *imdr, - const struct imd_entry *e) +static size_t imdr_entry_size(const struct imd_entry *e) { return e->size; } @@ -324,7 +322,7 @@ static struct imd_entry *imd_entry_add_to_root(struct imd_root *r, uint32_t id, last_entry = root_last_entry(r); e_offset = last_entry->start_offset; e_offset -= (ssize_t)used_size; - if (e_offset > last_entry->start_offset) + if (e_offset >= last_entry->start_offset) return NULL; entry = root_last_entry(r) + 1; @@ -409,7 +407,7 @@ void imd_handle_init_partial_recovery(struct imd *imd) return; imd->sm.limit = (uintptr_t)imdr_entry_at(imdr, e); - imd->sm.limit += imdr_entry_size(imdr, e); + imd->sm.limit += imdr_entry_size(e); imdr = &imd->sm; rp = imdr_get_root_pointer(imdr); imdr->r = relative_pointer(rp, rp->root_offset); @@ -467,14 +465,14 @@ int imd_recover(struct imd *imd) if (imdr_recover(imdr) != 0) return -1; - /* Determine if small region is region is present. */ + /* Determine if small region is present. */ e = imdr_entry_find(imdr, SMALL_REGION_ID); if (e == NULL) return 0; small_upper_limit = (uintptr_t)imdr_entry_at(imdr, e); - small_upper_limit += imdr_entry_size(imdr, e); + small_upper_limit += imdr_entry_size(e); imd->sm.limit = small_upper_limit; @@ -592,9 +590,9 @@ const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, return imd_entry_add(imd, id, size); } -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry) +size_t imd_entry_size(const struct imd_entry *entry) { - return imdr_entry_size(NULL, entry); + return imdr_entry_size(entry); } void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) @@ -609,7 +607,7 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) return imdr_entry_at(imdr, entry); } -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +uint32_t imd_entry_id(const struct imd_entry *entry) { return entry->id; } @@ -626,15 +624,16 @@ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) r = imdr_root(imdr); - if (r == NULL) - return -1; - if (root_is_locked(r)) return -1; if (entry != root_last_entry(r)) return -1; + /* Don't remove entry covering root region */ + if (r->num_entries == 1) + return -1; + r->num_entries--; return 0; @@ -671,7 +670,7 @@ static void imdr_print_entries(const struct imdr *imdr, const char *indent, printk(BIOS_DEBUG, "%s", name); printk(BIOS_DEBUG, "%2zu. ", i); printk(BIOS_DEBUG, "%p ", imdr_entry_at(imdr, e)); - printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(imdr, e)); + printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(e)); } } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index cb66c3b219..4b7c4120b0 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -30,6 +30,8 @@ void *cbmem_top(void) dead_code(); } +int cbmem_initialized; + static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; @@ -79,6 +81,8 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) /* Complete migration to CBMEM. */ cbmem_run_init_hooks(no_recovery); + + cbmem_initialized = 1; } int cbmem_initialize(void) @@ -112,6 +116,8 @@ int cbmem_initialize_id_size(u32 id, u64 size) /* Complete migration to CBMEM. */ cbmem_run_init_hooks(recovery); + cbmem_initialized = 1; + /* Recovery successful. */ return 0; } @@ -178,7 +184,7 @@ int cbmem_entry_remove(const struct cbmem_entry *entry) u64 cbmem_entry_size(const struct cbmem_entry *entry) { - return imd_entry_size(&imd, cbmem_to_imd(entry)); + return imd_entry_size(cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) @@ -232,7 +238,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) if (e == NULL) break; - id = imd_entry_id(&imd, e); + id = imd_entry_id(e); /* Don't add these metadata entries. */ if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) continue; @@ -241,7 +247,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header) lbe->tag = LB_TAG_CBMEM_ENTRY; lbe->size = sizeof(*lbe); lbe->address = (uintptr_t)imd_entry_at(&imd, e); - lbe->entry_size = imd_entry_size(&imd, e); + lbe->entry_size = imd_entry_size(e); lbe->id = id; } } diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index 887351aa57..571aa7bb8e 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -25,12 +25,12 @@ permissions described in the GCC Runtime Library Exception, version #ifdef __COREBOOT__ #include #include +#include #include #include typedef s32 pid_t; #define gcc_assert(x) ASSERT(x) #define fprintf(file, x...) printk(BIOS_ERR, x) -#define alloca(size) __builtin_alloca(size) #include "gcov-glue.c" /* Define MACROs to be used by coreboot compilation. */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 88a3126038..3b6aa2ecba 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -51,7 +51,7 @@ _etext = .; } : to_load -#if ENV_RAMSTAGE && CONFIG(COVERAGE) +#if ENV_RAMSTAGE && (CONFIG(COVERAGE) || CONFIG(ASAN_IN_RAMSTAGE)) .ctors . : { . = ALIGN(0x100); __CTOR_LIST__ = .; @@ -126,6 +126,11 @@ } #endif +#if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE) + _shadow_size = (_eheap - _data) >> 3; + REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) +#endif + _eprogram = .; /* Discard the sections we don't need/want */ diff --git a/src/lib/region_file.c b/src/lib/region_file.c index ce2ed30f7a..4fe91b62bf 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -365,12 +365,16 @@ static int commit_data_allocation(struct region_file *f, size_t data_blks) return 0; } -static int commit_data(const struct region_file *f, const void *buf, - size_t size) +static int commit_data(const struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries) { size_t offset = block_to_bytes(region_file_data_begin(f)); - if (rdev_writeat(&f->rdev, buf, offset, size) < 0) - return -1; + for (int i = 0; i < num_entries; i++) { + if (rdev_writeat(&f->rdev, entries[i].data, offset, entries[i].size) < 0) + return -1; + offset += entries[i].size; + } return 0; } @@ -399,8 +403,9 @@ static int handle_need_to_empty(struct region_file *f) return 0; } -static int handle_update(struct region_file *f, size_t blocks, const void *buf, - size_t size) +static int handle_update(struct region_file *f, size_t blocks, + const struct update_region_file_entry *entries, + size_t num_entries) { if (!update_can_fit(f, blocks)) { printk(BIOS_INFO, "REGF update can't fit. Will empty.\n"); @@ -413,7 +418,7 @@ static int handle_update(struct region_file *f, size_t blocks, const void *buf, return -1; } - if (commit_data(f, buf, size)) { + if (commit_data(f, entries, num_entries)) { printk(BIOS_ERR, "REGF failed to commit data.\n"); return -1; } @@ -421,11 +426,16 @@ static int handle_update(struct region_file *f, size_t blocks, const void *buf, return 0; } -int region_file_update_data(struct region_file *f, const void *buf, size_t size) +int region_file_update_data_arr(struct region_file *f, + const struct update_region_file_entry *entries, + size_t num_entries) { int ret; size_t blocks; + size_t size = 0; + for (int i = 0; i < num_entries; i++) + size += entries[i].size; blocks = bytes_to_block(ALIGN_UP(size, REGF_BLOCK_GRANULARITY)); while (1) { @@ -442,7 +452,7 @@ int region_file_update_data(struct region_file *f, const void *buf, size_t size) ret = -1; break; default: - ret = handle_update(f, blocks, buf, size); + ret = handle_update(f, blocks, entries, num_entries); break; } @@ -459,3 +469,12 @@ int region_file_update_data(struct region_file *f, const void *buf, size_t size) return ret; } + +int region_file_update_data(struct region_file *f, const void *buf, size_t size) +{ + struct update_region_file_entry entry = { + .size = size, + .data = buf, + }; + return region_file_update_data_arr(f, &entry, 1); +} diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 38888961b3..38edc5f151 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -17,6 +18,12 @@ void dump_spd_info(struct spd_block *blk) } } +const char * __weak mainboard_get_dram_part_num(void) +{ + /* Default weak implementation, no need to override part number. */ + return NULL; +} + static bool use_ddr4_params(int dram_type) { switch (dram_type) { @@ -136,33 +143,41 @@ static int spd_get_busw(const uint8_t spd[], int dram_type) return spd_busw[index]; } -static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type) +static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, size_t *len) { - switch (dram_type) { + *spd_name = mainboard_get_dram_part_num(); + if (*spd_name != NULL) { + *len = strlen(*spd_name); + return; + } + + switch (type) { case SPD_DRAM_DDR3: - memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); - spd_name[DDR3_SPD_PART_LEN] = 0; + *spd_name = (const char *) &spd[DDR3_SPD_PART_OFF]; + *len = DDR3_SPD_PART_LEN; break; case SPD_DRAM_LPDDR3_INTEL: - memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], - LPDDR3_SPD_PART_LEN); - spd_name[LPDDR3_SPD_PART_LEN] = 0; + *spd_name = (const char *) &spd[LPDDR3_SPD_PART_OFF]; + *len = LPDDR3_SPD_PART_LEN; break; - /* LPDDR3, LPDDR4 and DDR4 have the same part number offset */ + /* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: - memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); - spd_name[DDR4_SPD_PART_LEN] = 0; + case SPD_DRAM_LPDDR4X: + *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; + *len = DDR4_SPD_PART_LEN; break; default: + *len = 0; break; } } void print_spd_info(uint8_t spd[]) { - char spd_name[DDR4_SPD_PART_LEN + 1] = { 0 }; + const char *nameptr = NULL; + size_t len; int type = spd[SPD_DRAM_TYPE]; int banks = spd_get_banks(spd, type); int capmb = spd_get_capmb(spd); @@ -176,9 +191,9 @@ void print_spd_info(uint8_t spd[]) printk(BIOS_INFO, "SPD: module type is %s\n", spd_get_module_type_string(type)); /* Module Part Number */ - spd_get_name(spd, spd_name, type); - - printk(BIOS_INFO, "SPD: module part number is %s\n", spd_name); + spd_get_name(spd, type, &nameptr, &len); + if (nameptr) + printk(BIOS_INFO, "SPD: module part number is %.*s\n", (int) len, nameptr); printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", diff --git a/src/lib/string.c b/src/lib/string.c index e8f72a28e8..9677520137 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -163,6 +163,16 @@ int strcspn(const char *str, const char *spn) return ret; } +char *strstr(const char *haystack, const char *needle) +{ + size_t needle_len = strlen(needle); + for (; *haystack; haystack++) { + if (!strncmp(haystack, needle, needle_len)) + return (char *)haystack; + } + return NULL; +} + char *strtok_r(char *str, const char *delim, char **ptr) { char *start; diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index f368409ef1..badc600d64 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include + #include #define MAX_TIMER_QUEUE_ENTRIES 64 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 24d80ea89a..7347d07b16 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -12,8 +11,6 @@ #define MAX_TIMESTAMPS 192 -DECLARE_OPTIONAL_REGION(timestamp); - /* This points to the active timestamp_table and can change within a stage as CBMEM comes available. */ static struct timestamp_table *glob_ts_table; diff --git a/src/lib/ubsan.c b/src/lib/ubsan.c index 8c1f64d427..1037b1b17a 100644 --- a/src/lib/ubsan.c +++ b/src/lib/ubsan.c @@ -68,7 +68,7 @@ struct ubsan_type_mismatch_data { unsigned char type_check_kind; }; -void __ubsan_handle_type_mismatch(void *data_raw, void *pointer_raw) +void __ubsan_handle_type_mismatch_v1(void *data_raw, void *pointer_raw) { const struct ubsan_type_mismatch_data *data = (struct ubsan_type_mismatch_data *)data_raw; @@ -81,7 +81,7 @@ void __ubsan_handle_type_mismatch(void *data_raw, void *pointer_raw) ubsan_abort(&data->location, violation); } -ABORT_VARIANT_VP_VP(type_mismatch); +ABORT_VARIANT_VP_VP(type_mismatch_v1); struct ubsan_overflow_data { struct ubsan_source_location location; @@ -156,6 +156,23 @@ void __ubsan_handle_divrem_overflow(void *data_raw, void *lhs_raw, ABORT_VARIANT_VP_VP_VP(divrem_overflow); +struct ubsan_pointer_overflow_data { + struct ubsan_source_location location; +}; + +void __ubsan_handle_pointer_overflow(void *data_raw, void *base_raw, void *result_raw) +{ + const struct ubsan_pointer_overflow_data *data = + (struct ubsan_pointer_overflow_data *)data_raw; + ubsan_value_handle_t base = (ubsan_value_handle_t)base_raw; + ubsan_value_handle_t result = (ubsan_value_handle_t)result_raw; + (void)base; + (void)result; + ubsan_abort(&data->location, "pointer overflow"); +} + +ABORT_VARIANT_VP_VP_VP(pointer_overflow); + struct ubsan_shift_out_of_bounds_data { struct ubsan_source_location location; struct ubsan_type_descriptor *lhs_type; @@ -228,15 +245,7 @@ void __ubsan_handle_vla_bound_not_positive(void *data_raw, void *bound_raw) ABORT_VARIANT_VP_VP(vla_bound_not_positive); struct ubsan_float_cast_overflow_data { -/* -* TODO: Remove this GCC 5.x compatibility after switching to GCC 6.x. The -* GCC developers accidentally forgot the source location. Their -* libubsan probes to see if it looks like a path, but we don't need -* to maintain compatibility with multiple gcc releases. See below. -*/ -#if !(defined(__GNUC__) && __GNUC__ < 6) struct ubsan_source_location location; -#endif struct ubsan_type_descriptor *from_type; struct ubsan_type_descriptor *to_type; }; @@ -247,11 +256,7 @@ void __ubsan_handle_float_cast_overflow(void *data_raw, void *from_raw) (struct ubsan_float_cast_overflow_data *)data_raw; ubsan_value_handle_t from = (ubsan_value_handle_t)from_raw; (void) from; -#if !(defined(__GNUC__) && __GNUC__ < 6) ubsan_abort(&data->location, "float cast overflow"); -#else - ubsan_abort(((void) data, &unknown_location), "float cast overflow"); -#endif } ABORT_VARIANT_VP_VP(float_cast_overflow); diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index 33e5aeb889..f9022a4c75 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Device (BAT) { diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index c7a91774d3..78e156c6a2 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Device (EC) { diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl index 3c44c47ca2..e703ba1936 100644 --- a/src/mainboard/51nb/x210/acpi/graphics.asl +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Device (GFX0) { diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl index c8c4f255a9..89df7f4d93 100644 --- a/src/mainboard/51nb/x210/acpi/mainboard.asl +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ Scope (\_SB) { diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl index fc0333511b..6cf3f32f23 100644 --- a/src/mainboard/51nb/x210/acpi/platform.asl +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Enable ACPI _SWS methods */ #include diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl index 6fe3084c5e..ee2eabeb75 100644 --- a/src/mainboard/51nb/x210/acpi/superio.asl +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b610904a9e..294ae44022 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -36,8 +36,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataMode" = "0" @@ -48,19 +46,12 @@ chip soc/intel/skylake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -71,15 +62,6 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - register "PmConfigPciClockRun" = "1" # Enable Root Ports 3, 4 and 9 @@ -138,9 +120,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -159,6 +143,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip ec/51nb/npce985la0dx device pnp 0c09.0 on end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index c648d42568..d56fccbde1 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -1,11 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include DefinitionBlock( "dsdt.aml", "DSDT", - 0x05, // DSDT revision: ACPI v5.0 + 0x02, // DSDT revision: ACPI v5.0 OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index c517b44628..34ee409e00 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H @@ -6,174 +6,186 @@ #include #include +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A7, 1, DEEP), + PAD_NC(GPP_A8, 20K_PU), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A12, 0, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_NC(GPP_B15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), }; #endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c index 6799c38735..730cc443a7 100644 --- a/src/mainboard/51nb/x210/hda_verb.c +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c index 4e6f1d588a..e05331c1ed 100644 --- a/src/mainboard/51nb/x210/mainboard.c +++ b/src/mainboard/51nb/x210/mainboard.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "gpio.h" diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 60f008c20a..2112e2587f 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 77fcba16e6..af685db17a 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -13,10 +13,6 @@ source "src/mainboard/*/Kconfig" config MAINBOARD_VENDOR string "Mainboard vendor name" -config BOARD_ROMSIZE_KB_64 - bool -config BOARD_ROMSIZE_KB_128 - bool config BOARD_ROMSIZE_KB_256 bool config BOARD_ROMSIZE_KB_512 @@ -47,8 +43,6 @@ config BOARD_ROMSIZE_KB_65536 # TODO: No help text possible for choice fields? choice prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 @@ -68,16 +62,6 @@ choice The build system will take care of creating a coreboot.rom file of the matching size. -config COREBOOT_ROMSIZE_KB_64 - bool "64 KB" - help - Choose this option if you have a 64 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_128 - bool "128 KB" - help - Choose this option if you have a 128 KB ROM chip. - config COREBOOT_ROMSIZE_KB_256 bool "256 KB" help @@ -148,8 +132,6 @@ endchoice # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 default 256 if COREBOOT_ROMSIZE_KB_256 default 512 if COREBOOT_ROMSIZE_KB_512 default 1024 if COREBOOT_ROMSIZE_KB_1024 @@ -167,8 +149,6 @@ config COREBOOT_ROMSIZE_KB # Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x00010000 if COREBOOT_ROMSIZE_KB_64 - default 0x00020000 if COREBOOT_ROMSIZE_KB_128 default 0x00040000 if COREBOOT_ROMSIZE_KB_256 default 0x00080000 if COREBOOT_ROMSIZE_KB_512 default 0x00100000 if COREBOOT_ROMSIZE_KB_1024 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000000..1c39839154 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000000..bb177f9e49 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig new file mode 100644 index 0000000000..941070ed2d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ACER_G43T_AM3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_ITE_IT8720F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select DRIVERS_I2C_CK505 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + +config VGA_BIOS_ID + string + default "8086,2e22" + +config MAINBOARD_DIR + string + default "acer/g43t-am3" + +config MAINBOARD_PART_NUMBER + string + default "G43T-AM3" + +endif # BOARD_ACER_G43T_AM3 diff --git a/src/mainboard/acer/g43t-am3/Kconfig.name b/src/mainboard/acer/g43t-am3/Kconfig.name new file mode 100644 index 0000000000..a9b34ff25f --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_G43T_AM3 + bool "G43T-AM3" diff --git a/src/mainboard/acer/g43t-am3/Makefile.inc b/src/mainboard/acer/g43t-am3/Makefile.inc new file mode 100644 index 0000000000..ede8d87e92 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += cstates.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/acer/g43t-am3/acpi/ec.asl b/src/mainboard/acer/g43t-am3/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000000..b7588dcc41 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/ich10_pci_irqs.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0001ffff, 0, 0, 0x14}, + Package() { 0x0001ffff, 1, 0, 0x15}, + Package() { 0x0001ffff, 2, 0, 0x16}, + Package() { 0x0001ffff, 3, 0, 0x17}, + + Package() { 0x0002ffff, 0, 0, 0x15}, + Package() { 0x0002ffff, 1, 0, 0x16}, + Package() { 0x0002ffff, 2, 0, 0x17}, + Package() { 0x0002ffff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/acer/g43t-am3/acpi/superio.asl b/src/mainboard/acer/g43t-am3/acpi/superio.asl new file mode 100644 index 0000000000..9f3900b86c --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi/superio.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#include diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c new file mode 100644 index 0000000000..1485b67439 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ +} diff --git a/src/mainboard/acer/g43t-am3/board_info.txt b/src/mainboard/acer/g43t-am3/board_info.txt new file mode 100644 index 0000000000..aaf657b583 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default new file mode 100644 index 0000000000..706f5dd551 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/acer/g43t-am3/cmos.layout b/src/mainboard/acer/g43t-am3/cmos.layout new file mode 100644 index 0000000000..5f51bb8398 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cmos.layout @@ -0,0 +1,73 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/acer/g43t-am3/cstates.c b/src/mainboard/acer/g43t-am3/cstates.c new file mode 100644 index 0000000000..21b18b9e8d --- /dev/null +++ b/src/mainboard/acer/g43t-am3/cstates.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/acer/g43t-am3/data.vbt b/src/mainboard/acer/g43t-am3/data.vbt new file mode 100644 index 0000000000..646adbae1b Binary files /dev/null and b/src/mainboard/acer/g43t-am3/data.vbt differ diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb new file mode 100644 index 0000000000..4266861bdc --- /dev/null +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end + end + end + device domain 0 on # PCI domain + subsystemid 0x8086 0x0028 inherit + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + + # Enable PCIe ports 0,1 as slots. + register "pcie_slot_implemented" = "0x3" + + # "Additional LPC IO decode ranges": used for SuperIO's + # Environment Controller on 0xa15/0xa16 + register "gen1_dec" = "0x00fc0a01" + + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8720f # Super I/O + register "ec.smbus_en" = "1" + register "ec.smbus_24mhz" = "1" + register "TMPIN1.mode" = "THERMAL_DIODE" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "100" + register "TMPIN3.min" = "0" + register "TMPIN3.max" = "100" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "0" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "90" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "1" + register "FAN1.smart.smoothing" = "0" + register "FAN1.smart.pwm_start" = "30" + register "FAN1.smart.slope" = "0x0d" + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # System fan + register "FAN2.smart.tmpin" = "2" + register "FAN2.smart.tmp_off" = "0" + register "FAN2.smart.tmp_start" = "40" + register "FAN2.smart.tmp_full" = "90" + register "FAN2.smart.tmp_delta" = "2" + register "FAN2.smart.full_lmt" = "0" + register "FAN2.smart.smoothing" = "0" + register "FAN2.smart.pwm_start" = "48" + register "FAN2.smart.slope" = "0x20" + register "FAN3.mode" = "FAN_MODE_OFF" # Not connected + + register "ec.vin_mask" = "VIN_ALL" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM 1 + device pnp 2e.2 off end # COM 2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x60 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 0x1 + io 0x62 = 0x064 + irq 0xf0 = 0x00 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0x0c + irq 0xf0 = 0x00 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa20 + io 0x64 = 0xa30 + irq 0xc0 = 0x01 # Simple IO Set 1 + irq 0xc1 = 0x0c # Simple IO Set 2 + irq 0xc2 = 0x70 # Simple IO Set 3 + irq 0xc3 = 0x00 # Simple IO Set 4 + irq 0xc8 = 0x01 # Simple IO Set 1 Output + irq 0xc9 = 0x0c # Simple IO Set 2 Output + irq 0xca = 0x00 # Simple IO Set 3 Output + irq 0xcb = 0x00 # Simple IO Set 4 Output + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x12 + irq 0xf9 = 0x02 + irq 0xfa = 0x13 + irq 0xfb = 0x02 + #irq 0xfc = 0xef # VID Input + irq 0xfd = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5) + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # IDT CV194 + register "mask" = "{ 0xff, 0xff, 0xff, 0x00, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0xff, 0xff, 0xff, + 0x00, 0xff }" + register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x7d, 0x96, + 0x00, 0x9d }" + device i2c 69 on end + end + end + device pci 1f.4 off end + device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode) + device pci 1f.6 off end # Thermal Subsystem + end + end +end diff --git a/src/mainboard/acer/g43t-am3/dsdt.asl b/src/mainboard/acer/g43t-am3/dsdt.asl new file mode 100644 index 0000000000..cf2395cf9a --- /dev/null +++ b/src/mainboard/acer/g43t-am3/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090811 // OEM revision +) +{ + // global NVS and variables + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include +} diff --git a/src/mainboard/acer/g43t-am3/early_init.c b/src/mainboard/acer/g43t-am3/early_init.c new file mode 100644 index 0000000000..b34ab4651b --- /dev/null +++ b/src/mainboard/acer/g43t-am3/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO set 1 + ite_reg_write(GPIO_DEV, 0x26, 0x0c); // GPIO set 2 + ite_reg_write(GPIO_DEV, 0x27, 0x70); // GPIO set 3 + ite_reg_write(GPIO_DEV, 0x28, 0x40); // GPIO set 4 + ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO set 5 + + /* Enable 3VSB during Suspend-to-RAM */ + ite_enable_3vsbsw(GPIO_DEV); + + /* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */ + ite_delay_pwrgd3(GPIO_DEV); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} diff --git a/src/mainboard/acer/g43t-am3/gma-mainboard.ads b/src/mainboard/acer/g43t-am3/gma-mainboard.ads new file mode 100644 index 0000000000..c9e4326924 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/acer/g43t-am3/gpio.c b/src/mainboard/acer/g43t-am3/gpio.c new file mode 100644 index 0000000000..38239baf79 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/gpio.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, + +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + +}; diff --git a/src/mainboard/acer/g43t-am3/hda_verb.c b/src/mainboard/acer/g43t-am3/hda_verb.c new file mode 100644 index 0000000000..32a9b25874 --- /dev/null +++ b/src/mainboard/acer/g43t-am3/hda_verb.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x1025024c, // Subsystem ID + 14, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x014b7140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19851), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x18567130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* HDMI */ + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(0, 0x03, 0x18560010) +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/amd/gardenia/acpi/routing.asl b/src/mainboard/amd/gardenia/acpi/routing.asl index d4d1c4a7ab..d362ca9a91 100644 --- a/src/mainboard/amd/gardenia/acpi/routing.asl +++ b/src/mainboard/amd/gardenia/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -70,7 +69,6 @@ Name(APR0, Package(){ Package(){0x0011FFFF, 0, 0, 19 }, }) - /* GPP 0 */ Name(PS4, Package(){ Package(){0x0000FFFF, 0, INTA, 0 }, diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index f9cf2ca3f5..0338115439 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/inagua/acpi/sata.asl +++ b/src/mainboard/amd/inagua/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 53427558ad..48afb3f9ad 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -31,7 +31,6 @@ static void init_gpios(void) gpio_100_write8(0x32, 0x48); } - /********************************************** * Enable the dedicated functions of the board. **********************************************/ diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index efbadbb50f..38447ac9b7 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 599e64ab83..8e2bd8ba28 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_AMD_MANDOLIN +if BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,8 +8,11 @@ config BOARD_SPECIFIC_OPTIONS select SOC_AMD_PICASSO select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN + select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME + select DRIVERS_UART_ACPI + select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD config FMDFILE string @@ -29,6 +32,7 @@ config AMD_LPC_DEBUG_CARD config CBFS_SIZE hex default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP config MAINBOARD_DIR string @@ -37,10 +41,12 @@ config MAINBOARD_DIR config VARIANT_DIR string default "mandolin" if BOARD_AMD_MANDOLIN + default "cereme" if BOARD_AMD_CEREME config MAINBOARD_PART_NUMBER string default "MANDOLIN" if BOARD_AMD_MANDOLIN + default "CEREME" if BOARD_AMD_CEREME config DEVICETREE string @@ -57,6 +63,7 @@ config ONBOARD_VGA_IS_PRIMARY config AMD_FWM_POSITION_INDEX int default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs @@ -68,9 +75,10 @@ config MANDOLIN_MCHP_FW_FILE string depends on MANDOLIN_HAVE_MCHP_FW default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_CEREME if !AMD_LPC_DEBUG_CARD -choice MANDOLIN_LPC_IOMUX +choice prompt "State of IOMux for LPC/eMMC signals" default MANDOLIN_IOMUX_USE_EMMC help @@ -104,5 +112,22 @@ config VGA_BIOS_DGPU_ID config VGA_BIOS_DGPU_FILE string default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN + default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME -endif # BOARD_AMD_MANDOLIN +config EFS_SPI_READ_MODE + int + default 0 if EM100 + default 0 if BOARD_AMD_CEREME + default 3 + +config EFS_SPI_SPEED + int + default 3 if EM100 + default 1 if BOARD_AMD_CEREME + default 0 + +config EFS_SPI_MICRON_FLAG + int + default 0 + +endif # BOARD_AMD_MANDOLIN || BOARD_AMD_CEREME diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name index 7dbfc3fd71..6f512337a3 100644 --- a/src/mainboard/amd/mandolin/Kconfig.name +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_AMD_MANDOLIN bool "Mandolin" + +config BOARD_AMD_CEREME + bool "Cereme" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 1865e74dd9..778701834f 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -10,8 +10,11 @@ ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) ramstage-y += emmc_gpio.c endif -# APCB_mandolin.bin -APCB_SOURCES = mandolin +ifeq ($(CONFIG_BOARD_AMD_MANDOLIN),y) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_mandolin.bin +else # CONFIG_BOARD_AMD_CEREME +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin +endif PHONY+=add_mchp_fw INTERMEDIATE+=add_mchp_fw diff --git a/src/mainboard/amd/mandolin/hda_verb.c b/src/mainboard/amd/mandolin/hda_verb.c index 37bb710c7c..0f61f31525 100644 --- a/src/mainboard/amd/mandolin/hda_verb.c +++ b/src/mainboard/amd/mandolin/hda_verb.c @@ -3,7 +3,7 @@ #include const u32 cim_verb_data[] = { - /* Realtek ALC701 */ + /* Realtek ALC701 on mainboard */ 0x10ec0701, 0x00000000, 0x00000016, @@ -35,7 +35,7 @@ const u32 cim_verb_data[] = { 0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1 0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2 - /* Realtek ALC285 */ + /* Realtek ALC285 on extension card */ 0x10ec0285, 0x00000000, 0x00000028, diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index c22ed34849..247616cff7 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -112,7 +112,7 @@ static void mainboard_init(void *chip_info) struct soc_amd_picasso_config *cfg = config_of_soc(); if (!CONFIG(PICASSO_LPC_IOMUX)) - cfg->sd_emmc_config = SD_EMMC_EMMC_HS400; + cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); diff --git a/src/mainboard/amd/mandolin/variants/cereme/board.fmd b/src/mainboard/amd/mandolin/variants/cereme/board.fmd new file mode 100644 index 0000000000..b55b8b506a --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 0x20000 + RW_MRC_CACHE 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb new file mode 100644 index 0000000000..155328871c --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec + + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port4 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port5 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping; all ports share one OC pin + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocessor + device pci 0.3 on end # USB 3.1 + device pci 0.4 off end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 off end # AHCI + device pci 0.1 off end # integrated Ethernet MAC + device pci 0.2 off end # integrated Ethernet MAC + end + device pci 14.0 on end # SMBus + device pci 14.3 on # D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c new file mode 100644 index 0000000000..b4ee5f485a --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/early_gpio.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe Reset 0 */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIe Reset 1 */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/gpio.c b/src/mainboard/amd/mandolin/variants/cereme/gpio.c new file mode 100644 index 0000000000..0ba2580ce1 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/gpio.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* EC SCI# */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* not Blink */ + PAD_GPI(GPIO_11, PULL_UP), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* SD card detect */ + PAD_GPI(GPIO_31, PULL_UP), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* NFC wake output# */ + PAD_GPO(GPIO_89, HIGH), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c new file mode 100644 index 0000000000..8fc94f8c3b --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/cereme/port_descriptors.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const fsp_dxio_descriptor pollock_dxio_descriptors[] = { + { /* NVME SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4 + } +}; + +fsp_ddi_descriptor pollock_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - DP */ + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = pollock_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors); + *ddi_descs = pollock_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); +} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd index 382c03066d..2845e640e5 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd +++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd @@ -1,7 +1,7 @@ -FLASH@0xFF800000 0x800000 { - BIOS@0x0 { - EC@0x0 0x20000 - RW_MRC_CACHE@0x20000 0x10000 +FLASH@0xFF800000 8M { + BIOS { + EC 0x20000 + RW_MRC_CACHE 64K FMAP 0x1000 COREBOOT(CBFS) } diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index f83a634195..3de58129cd 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -5,18 +5,108 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON" + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec - register "sd_emmc_config" = "SD_EMMC_DISABLE" + register "emmc_config" = "{ + .timing = SD_EMMC_DISABLE, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port0 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port1 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping; all ports share one OC pin + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" + register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_33M, /* MHz */ + .tpm_speed = SPI_SPEED_33M, /* MHz */ + .read_mode = SPI_READ_MODE_QUAD114, + }" # eSPI Configuration register "common_config.espi_config" = "{ @@ -36,6 +126,15 @@ chip soc/amd/picasso .flash_ch_en = 0, }" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" + device cpu_cluster 0 on device lapic 0 on end end @@ -76,4 +175,10 @@ chip soc/amd/picasso device pci 18.6 on end device pci 18.7 on end end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c index 326bcaa0e7..5213176a1d 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c +++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c @@ -4,12 +4,12 @@ #include #include -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 15, + .start_logical_lane = 8, + .end_logical_lane = 15, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, @@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* SSD */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WLAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* LAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, @@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WWAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 6, - .end_lane = 6, + .start_logical_lane = 6, + .end_logical_lane = 6, .device_number = 1, .function_number = 4, .link_aspm = ASPM_L1, @@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* WIFI */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 7, - .end_lane = 7, + .start_logical_lane = 7, + .end_logical_lane = 7, .gpio_group_id = 1, .device_number = 1, .function_number = 5, @@ -87,19 +87,19 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = { { /* SATA EXPRESS */ .port_present = true, .engine_type = SATA_ENGINE, - .start_lane = 2, - .end_lane = 3, + .start_logical_lane = 2, + .end_logical_lane = 3, .gpio_group_id = 1, .channel_type = SATA_CHANNEL_LONG, } }; -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { { /* MXM */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 11, + .start_logical_lane = 8, + .end_logical_lane = 11, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, @@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* SSD */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, @@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* WLAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* LAN */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, @@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = { { /* SATA */ .port_present = true, .engine_type = SATA_ENGINE, - .start_lane = 2, - .end_lane = 3, + .start_logical_lane = 2, + .end_logical_lane = 3, .gpio_group_id = 1, .channel_type = SATA_CHANNEL_LONG, } @@ -193,23 +193,23 @@ static const fsp_ddi_descriptor dali_ddi_descriptors[] = { }, { /* DDI2 - DP */ .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, + .aux_index = AUX4, + .hdp_index = HDP4, } }; -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { if (soc_is_reduced_io_sku()) { /* Dali */ - *pcie_descs = dali_pcie_descriptors; - *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *dxio_descs = dali_dxio_descriptors; + *dxio_num = ARRAY_SIZE(dali_dxio_descriptors); *ddi_descs = dali_ddi_descriptors; *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); } else { /* Picasso and default */ - *pcie_descs = pco_pcie_descriptors; - *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *dxio_descs = pco_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pco_dxio_descriptors); *ddi_descs = pco_ddi_descriptors; *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); } diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ b/src/mainboard/amd/olivehill/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c index d1bdd09e26..efdf57d1c2 100644 --- a/src/mainboard/amd/olivehill/bootblock.c +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 428ea84cfe..894df574ea 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select STONEYRIDGE_LEGACY_FREE select ONBOARD_VGA_IS_PRIMARY - select BOOTBLOCK_CONSOLE select SUPERIO_FINTEK_F81803A select SUPERIO_FINTEK_COMMON_PRE_RAM select SUPERIO_FINTEK_FAN_CONTROL @@ -28,7 +27,7 @@ config MAINBOARD_PART_NUMBER string default "Padmelon" -choice PADMELON_SOC +choice prompt "SOC used in padmelon board" default PADMELON_MERLIN_FALCON diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl index 40a1b5b520..de6ff3d92f 100644 --- a/src/mainboard/amd/padmelon/acpi/routing.asl +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c index dbdfa47041..6937429934 100644 --- a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -95,7 +95,6 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { }; - static const PCIe_DDI_DESCRIPTOR DdiList[] = { /* DP0 */ { diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index e10da6f1b7..352ab25b4d 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -5,7 +5,6 @@ #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 726e111ff6..91bcabc52d 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 167a85790f..14fff7da30 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include - static const PCIe_PORT_DESCRIPTOR PortList[] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index 656a0be1ee..b7fd53af8c 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -41,7 +41,6 @@ Scope(\_SB) { /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - /* SB devices */ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/persimmon/acpi/sata.asl +++ b/src/mainboard/amd/persimmon/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 87a5cc48a0..d472ad036b 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 14574f0e1c..339469bb87 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/south_station/acpi/sata.asl +++ b/src/mainboard/amd/south_station/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 1f898d55e4..c873e4e904 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit chip northbridge/amd/agesa/family14 device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -85,5 +85,5 @@ chip northbridge/amd/agesa/family14/root_complex end # agesa northbridge - end #domain + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index efbadbb50f..38447ac9b7 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 1cba1a3cd9..4dddaef54d 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -154,7 +154,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) } } - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index ec1f0ae4dc..23cda27728 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -5,7 +5,6 @@ #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 726e111ff6..91bcabc52d 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -35,7 +35,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index 4fd7b9ff98..16fe45f32b 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl index 7f305fb17f..9344ff1714 100644 --- a/src/mainboard/amd/union_station/acpi/sata.asl +++ b/src/mainboard/amd/union_station/acpi/sata.asl @@ -58,7 +58,6 @@ Device(PMRY) } /* end of PSLA */ } /* end of PMRY */ - Device(SEDY) { Name(_ADR, 1) /* IDE Scondary Channel */ diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 185369a3d5..6c88931d17 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit chip northbridge/amd/agesa/family14 device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -61,5 +61,5 @@ chip northbridge/amd/agesa/family14/root_complex end # agesa northbridge - end #domain + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index efbadbb50f..38447ac9b7 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index eb367fa98b..e8c7da8cff 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -32,27 +32,27 @@ Device(EC) Method(SBPC, 0, NotSerialized) { - Store(1000, Local0) + Local0 = 1000 While(Local0) { - If(LEqual(SPTR, 0x00)) + If(SPTR == 0) { Return() } Sleep(1) - Decrement(Local0) + Local0-- } } Method(SBRW, 2, NotSerialized) { Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x09, SPTR) + SADR = (Arg0 << 1) + SCMD = Arg1 + SPTR = 0x09 SBPC() - Store(SBDW, Local0) + Local0 = SBDW Release(ECLK) Return(Local0) } @@ -60,11 +60,11 @@ Device(EC) Method(SBRB, 2, NotSerialized) { Acquire(ECLK, 0xFFFF) - Store(ShiftLeft(Arg0, 0x01), SADR) - Store(Arg1, SCMD) - Store(0x0B, SPTR) + SADR = (Arg0 << 1) + SCMD = Arg1 + SPTR = 0x0B SBPC() - Store(SBFR, Local0) + Local0 = SBFR Release(ECLK) Return(Local0) } @@ -112,9 +112,9 @@ Device(EC) Method(_PSW, 1, NotSerialized) { if (Arg0) { - Store(1, WKLD) + WKLD = 1 } else { - Store(0, WKLD) + WKLD = 0 } } } @@ -172,19 +172,19 @@ Device(EC) Method(_BIF, 0, NotSerialized) { - Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) - Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) - Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) - Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) - Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) - Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + BATS [0x01] = (SBRW (0x0B, 0x18) * 10) + BATS [0x02] = (SBRW (0x0B, 0x10) * 10) + BATS [0x04] = SBRW (0x0B, 0x19) + BATS [0x09] = SBRB (0x0B, 0x21) + BATS [0x0B] = SBRB (0x0B, 0x22) + BATS [0x0C] = SBRB (0x0B, 0x20) Return(BATS) } Method(_STA, 0, NotSerialized) { - If(And(^^SBRW(0x0A, 0x01), 0x01)) { + If (SBRW(0x0A, 1) & 1) { Return(0x1f) } else { Return(0x0f) @@ -194,7 +194,7 @@ Device(EC) Method(_BST, 0, NotSerialized) { /* Check for battery presence. */ - If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + If (!(SBRW (0x0A, 1) & 1)) { Return(Package(4) { 0, 0xFFFFFFFF, @@ -202,30 +202,30 @@ Device(EC) 0xFFFFFFFF }) } - Store(^^SBRW(0x0B, 0x09), Local1) - Store(Local1, Index(BATI, 0x03)) - Store(^^SBRW(0x0B, 0x0A), Local0) + Local1 = SBRW(0x0B, 0x09) + BATI [3] = Local1 + Local0 = SBRW (0x0B, 0x0A) /* Sign-extend Local0. */ - If(And(Local0, 0x8000)) + If(Local0 & 0x8000) { - Not(Local0, Local0) - And(Increment(Local0), 0xFFFF, Local0) + Local0 = ~Local0 + Local0 = (Local0++ & 0xFFFF) } - Multiply(Local0, Local1, Local0) - Divide(Local0, 1000, , Index(BATI, 1)) - Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + Local0 *= Local1 + BATI [1] = (Local0 / 1000) + BATI [2] = (SBRW (0x0B, 0x0F) * 10) If(HPAC) { - If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { - Store(2, Index(BATI, 0)) + If (!(SBRW (0x0B, 0x16) & 0x40)) { + BATI [0] = 2 } Else { - Store(0, Index(BATI, 0)) + BATI [0] = 0 } } Else { - Store(0x01, Index(BATI, 0)) + BATI [0] = 1 } Return(BATI) diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index 862292403d..abba5abf25 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -10,12 +10,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -46,7 +46,7 @@ Scope(\_SB) * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 6e99b63077..f6b01769c9 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "1" + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "10" register "gpu_panel_power_cycle_delay" = "6" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 678c48b268..2fc7c8844c 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "4" diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc651208f0..844604afc8 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -5,13 +5,13 @@ if BOARD_ASROCK_B85M_PRO4 config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index 0cedcd6e47..7314552767 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -54,6 +54,7 @@ void mainboard_config_superio(void) pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index a044d0a8a3..d257f18bc6 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -27,14 +27,6 @@ chip northbridge/intel/haswell chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x83" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x83" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x8a" register "sata_ahci" = "1" register "sata_port_map" = "0x3f" @@ -111,6 +103,9 @@ chip northbridge/intel/haswell device pnp 2e.16 off end # Deep sleep device pnp 2e.17 off end # GPIOA end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM + end end device pci 1f.2 on end # SATA (AHCI) device pci 1f.3 on end # SMBus diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 6bd2f981a8..391b308941 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -6,7 +6,6 @@ #include #include - static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index fe0d50e71c..81e2bac79d 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include @@ -9,7 +8,6 @@ #include - u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 21ecebe51b..6d3ea82233 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -109,7 +108,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index f90467cdb9..c4f1b08216 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 42555bf7b5..2c9f6347c4 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -32,7 +32,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(1, 0x03, 0x18560010), - /* coreboot specific header */ /* Realtek ALC662 rev1 */ 0x10ec0662, /* Vendor ID */ diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 75020712fc..9d22761a7c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -69,8 +69,8 @@ chip northbridge/intel/x4x # Northbridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + irq 0x70 = 6 + drq 0x74 = 2 end device pnp 2e.1 on # Parallel port # global diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c index 722e4cc7b3..87ace2c933 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c @@ -88,7 +88,6 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, }; - const struct pch_gpio_map mainboard_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 425aff4868..a80b5954df 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H - select GENERIC_SPD_BIN select SUPERIO_NUVOTON_NCT6791D select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 1327a3615f..d6f29a20e9 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -18,9 +18,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Set @0x280-0x2ff I/O Range for SuperIO HWM - register "gen1_dec" = "0x007c0281" - # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -28,31 +25,9 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" - register "SkipExtGfxScan" = "0" register "PrimaryDisplay" = "Display_PEG" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "0" - register "PchHdaVcType" = "Vc1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Set LPC Serial IRQ mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -134,53 +109,6 @@ chip soc/intel/skylake .voltage_limit = 1520 \ }" - register "EnableLan" = "0" - - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - # SATA4 and SATA5 are located in the lower right corner of the board, - # but they are not populated. This is because the same PCB is used to - # make boards with better PCHs, which can have up to six SATA ports. - # However, the H110 PCH only has four SATA ports, which explains why - # two connectors are missing. - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - # PCH UART, SPI, I2C register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ @@ -196,55 +124,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Disable CLKREQ#, since onboard LAN is always present - register "PcieRpClkReqSupport[5]" = "0" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -262,6 +141,13 @@ chip soc/intel/skylake end device pci 01.0 on # PEG subsystemid 0x1849 0x1901 + register "Peg0MaxLinkWidth" = "Peg0_x16" + register "SkipExtGfxScan" = "0" + + # Configure PCIe clockgen in PCH + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" end device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 @@ -270,6 +156,32 @@ chip soc/intel/skylake device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" end device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on # Thermal Subsystem @@ -279,8 +191,11 @@ chip soc/intel/skylake device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -288,6 +203,22 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA subsystemid 0x1849 0xa102 + register "SataSalpSupport" = "1" + # SATA4 and SATA5 are located in the lower right corner of the board, + # but they are not populated. This is because the same PCB is used to + # make boards with better PCHs, which can have up to six SATA ports. + # However, the H110 PCH only has four SATA ports, which explains why + # two connectors are missing. + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" end device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 @@ -296,9 +227,33 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 on # PCI Express Port 5 - PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" + register "PcieRpHotPlug[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 - Onboard LAN + register "PcieRpEnable[5]" = "1" + + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "1" + end + device pci 1c.6 on # PCI Express Port 7 - PCIE slot + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "3" + register "PcieRpHotPlug[6]" = "1" + end device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -311,9 +266,15 @@ chip soc/intel/skylake device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x1a43 + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x007c0281" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/common device pnp 2e.0 on # passes SIO base addr to SSDT gen @@ -421,7 +382,10 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaVcType" = "Vc1" + register "DspEnable" = "0" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 405959601e..457c927397 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 2a3b424b3c..193579c6a1 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -10,37 +10,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A7 - GPIO */ PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), /* GPP_A12 - GPIO */ PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* GPP_A16 - GPIO */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), /* GPP_A17 - GPIO */ @@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B3 - GPIO */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* GPP_B4 - CPU_GP3 */ - PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), /* GPP_B5 - GPIO */ PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), /* GPP_B6 - GPIO */ @@ -88,11 +88,11 @@ static const struct pad_config gpio_table[] = { PAD_BUF(NO_DISABLE), PAD_PULL(NONE)), /* GPP_B12 - SLP_S0# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), /* GPP_B16 - GPIO */ @@ -110,35 +110,31 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, - PAD_FUNC(NF2) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | - PAD_BUF(RX_DISABLE) | 1, - PAD_PULL(20K_PD)), + PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* GPP_C1 - SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* GPP_C2 - GPIO */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPP_C3 - SML0CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 - SML0DATA */ - PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* GPP_C5 - GPIO */ PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - UART0_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), /* GPP_C9 - UART0_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), /* GPP_C10 - UART0_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), /* GPP_C11 - UART0_CTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), /* GPP_C12 - GPIO */ PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), /* GPP_C13 - GPIO */ @@ -156,11 +152,11 @@ static const struct pad_config gpio_table[] = { /* GPP_C19 - GPIO */ PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), /* GPP_C20 - UART2_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), /* GPP_C21 - UART2_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), /* GPP_C22 - UART2_RTS# */ - PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* GPP_C23 - GPIO */ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), @@ -176,13 +172,13 @@ static const struct pad_config gpio_table[] = { /* GPP_D4 - GPIO */ PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), /* GPP_D5 - I2S_SFRM */ - PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), /* GPP_D6 - I2S_TXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), /* GPP_D7 - I2S_RXD */ - PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* GPP_D8 - I2S_SCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* GPP_D9 - GPIO */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), /* GPP_D10 - GPIO */ @@ -204,9 +200,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D18 - GPIO */ PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), /* GPP_D21 - GPIO */ PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), /* GPP_D22 - GPIO */ @@ -216,37 +212,37 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* GPP_E4 - SATA_DEVSLP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E4, NONE, PLTRST, NF1), /* GPP_E5 - SATA_DEVSLP1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* GPP_E6 - SATA_DEVSLP2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E6, NONE, PLTRST, NF1), /* GPP_E7 - GPIO */ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - USB_OC1# */ - PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* GPP_E11 - USB_OC2# */ - PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* GPP_E12 - USB_OC3# */ - PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* GPP_F2 - GPIO */ PAD_NC(GPP_F2, NONE), /* GPP_F3 - GPIO */ @@ -274,11 +270,11 @@ static const struct pad_config gpio_table[] = { /* GPP_F14 - GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), /* GPP_F15 - USB_OC4# */ - PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* GPP_F16 - USB_OC5# */ - PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* GPP_F17 - USB_OC6# */ - PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* GPP_F18 - GPIO */ PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPP_F19 - GPIO */ @@ -344,7 +340,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G18 - GPIO */ PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* GPP_G20 - GPIO */ PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), /* GPP_G21 - GPIO */ @@ -410,13 +406,13 @@ static const struct pad_config gpio_table[] = { /* GPD1 - GPIO */ PAD_CFG_GPO(GPD1, 0, PWROK), /* GPD2 - LAN_WAKE# */ - PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), /* GPD7 - GPIO */ @@ -426,70 +422,70 @@ static const struct pad_config gpio_table[] = { PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPD8 - SUSCLK */ - PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* GPD9 - SLP_WLAN# */ - PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* GPD10 - SLP_S5# */ - PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* GPD11 - GPIO */ PAD_CFG_GPO(GPD11, 0, PWROK), /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - DDPB_HPD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* GPP_I1 - DDPC_HPD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* GPP_I2 - DDPD_HPD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* GPP_I3 - DDPE_HPD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* GPP_I4 - GPIO */ PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), /* GPP_I5 - DDPB_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* GPP_I6 - DDPB_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), /* GPP_I7 - DDPC_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* GPP_I8 - DDPC_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), /* GPP_I9 - DDPD_CTRLCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* GPP_I10 - DDPD_CTRLDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), }; /* Early pad configuration in romstage */ static const struct pad_config early_gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ - PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), }; #endif diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 7a17915534..ca3058fa9f 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -1,71 +1,36 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 200, 81, 162 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[5] = { - 100, 40, 40, 23, 40 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; + const u16 rcomp_resistors[3] = { 121, 75, 100 }; + + const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { - .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + .addr_map = { 0x50, 0x52 }, }; - mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; - mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; - mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; dump_spd_info(&blk); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + /* use virtual channel 1 for the dmi interface of the PCH */ mupd->FspmTestConfig.DmiVc1 = 1; diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 62036108dd..6406417ac0 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -5,7 +5,6 @@ if BOARD_ASROCK_H81M_HDS config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CPU_INTEL_HASWELL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index f08d2d560f..8f368961de 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -35,15 +35,6 @@ chip northbridge/intel/haswell end chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x8a" - register "sata_ahci" = "1" register "sata_port_map" = "0x33" diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index b1e3e88d59..b97be80398 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -5,7 +5,6 @@ #include - static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 20c4b8d781..4761728927 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -7,7 +7,6 @@ #include #include - u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c new file mode 100644 index 0000000000..24a7208e3b --- /dev/null +++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; + +static const CODEC_TBL_LIST CodecTableList[] = { + {0x10ec0887, (CODEC_ENTRY *)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig new file mode 100644 index 0000000000..17fbe28cd5 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASUS_A88XM_E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default "asus/a88xm-e" + +config MAINBOARD_PART_NUMBER + string + default "A88XM-E" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config VGA_BIOS_ID + string + default "1002,990e" + +config HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name new file mode 100644 index 0000000000..492d6109ee --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_A88XM_E + bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc new file mode 100644 index 0000000000..549801d78f --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c new file mode 100644 index 0000000000..aa880e7bee --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OemCustomize.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include +#include + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI, HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/* CUSTOMER OVERRIDES MEMORY TABLE */ +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h similarity index 73% rename from src/mainboard/lippert/toucan-af/OptionsIds.h rename to src/mainboard/asus/a88xm-e/OptionsIds.h index ce3a8a0170..adbb4763ee 100644 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -6,14 +6,12 @@ * IDS Option File * * This file is used to switch on/off IDS features. - * */ #ifndef _OPTION_IDS_H_ #define _OPTION_IDS_H_ /** - * - * This file generates the defaults tables for the Integrated Debug Support + * This file generates the defaults tables for the Integrated Debug Support * Module. The documented build options are imported from a user controlled * file for processing. The build options for the Integrated Debug Support * Module are listed below: @@ -26,13 +24,15 @@ * IDSOPT_ASSERT_ENABLED * IDS_DEBUG_PORT * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * **/ -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE - +//#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW //#define IDSOPT_HOST_SIMNOW FALSE diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl new file mode 100644 index 0000000000..35583de49f --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. + */ + +/* + * P-state support: the maximum number of P-states supported + * by the CPUs that we'll use - is 6. Taken from AMI BIOS. + */ +Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } +}) + +Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} +}) + +Method(_PPC, 0){ + Return(0) +} diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl new file mode 100644 index 0000000000..9f01c7a0ca --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + } + + /* Legacy PM event */ + Method(_L08) { + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + } + + /* USB controller PME# */ + Method(_L0B) { + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl new file mode 100644 index 0000000000..699bc6b031 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) + /* Length of PCIe config space, 1MB each bus */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) + /* Base address of HPET table */ + Name(HPBA, 0xFED00000) + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl new file mode 100644 index 0000000000..99511c5a21 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 PCIe Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl new file mode 100644 index 0000000000..87773378c9 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ +Method(\_PTS, 1) { + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ +Method(\_WAK, 1) { + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl new file mode 100644 index 0000000000..d90fffdd40 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c similarity index 73% rename from src/mainboard/lippert/toucan-af/acpi_tables.c rename to src/mainboard/asus/a88xm-e/acpi_tables.c index f75f823f38..ff4a3b97b6 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/asus/a88xm-e/acpi_tables.c @@ -8,22 +8,21 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); + current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - + current, 0, 9, 9, 0xF); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); /* 1: LINT1 connect to NMI */ return current; diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt new file mode 100644 index 0000000000..579dce634d --- /dev/null +++ b/src/mainboard/asus/a88xm-e/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/bootblock.c b/src/mainboard/asus/a88xm-e/bootblock.c new file mode 100644 index 0000000000..0bc8d2e15e --- /dev/null +++ b/src/mainboard/asus/a88xm-e/bootblock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void sbxxx_enable_48mhzout(void) +{ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + u32 reg32; + reg32 = misc_read32(0x28); + reg32 &= ~(7 << 19); + reg32 |= (2 << 19); + misc_write32(0x28, reg32); + + /* Enable Auxiliary OSCOUT2 */ + misc_write32(0x40, misc_read32(0x40) & ~(1 << 7)); +} + +static void superio_init_m(void) +{ + const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +void bootblock_mainboard_early_init(void) +{ + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + superio_init_m(); +} diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c new file mode 100644 index 0000000000..76fafca604 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Include the files that instantiate the configuration definitions. */ +#include +#include +#include +#include +/* AGESA nonsense: the next two headers depend on heapManager.h */ +#include +#include +/* These tables are optional and may be used to adjust memory timing settings */ +#include +#include + +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type */ +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE + +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE + +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto + +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Customized OEM build configurations for FCH component */ +#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE + +GPIO_CONTROL a88xm_e_gpio[] = { + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (a88xm_e_gpio) + +/* Moving this include up will break AGESA. */ +#include diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout similarity index 86% rename from src/mainboard/lippert/toucan-af/cmos.layout rename to src/mainboard/asus/a88xm-e/cmos.layout index beedaa7930..2355292411 100644 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -1,8 +1,5 @@ -#***************************************************************************** # SPDX-License-Identifier: GPL-2.0-only -#***************************************************************************** - entries 0 384 r 0 reserved_memory @@ -18,14 +15,12 @@ entries 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu -456 1 e 1 ECC_memory +#456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text @@ -35,6 +30,11 @@ enumerations 2 1 Disable 4 0 Fallback 4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning 6 5 Notice 6 6 Info 6 7 Debug diff --git a/src/mainboard/asus/a88xm-e/devicetree.cb b/src/mainboard/asus/a88xm-e/devicetree.cb new file mode 100644 index 0000000000..f427d0d88b --- /dev/null +++ b/src/mainboard/asus/a88xm-e/devicetree.cb @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia (iGPU Audio) + device pci 2.0 on end # PCIEX16 + device pci 3.0 off end # - + device pci 4.0 off end # PCIe x4 (?) + device pci 5.0 off end # PCIe x1 (?) + device pci 6.0 off end # PCIe x1 (?) + device pci 7.0 off end # PCIe x1 (?) + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA AHCI + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on end # SMBUS + device pci 14.1 off end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel Port + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 # SMI + io 0x62 = 0x300 # Simple I/O + io 0x64 = 0 # Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI bridge + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe RP0: PCIEX1_1 + device pci 15.1 off end # PCIe RP1: - + device pci 15.2 on end # PCIe RP2: Onboard Ethernet + device pci 15.3 off end # PCIe RP3: - + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ + { {0xA0, 0x00}, {0xA2, 0x00}, }, + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000000..aac9c84cd5 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Describe the supported Sleep States for this Southbridge */ + #include + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c similarity index 82% rename from src/mainboard/lippert/toucan-af/irq_tables.c rename to src/mainboard/asus/a88xm-e/irq_tables.c index 5d2d253bfc..7ca1c4b951 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -1,15 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include -#include static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -27,24 +25,20 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; - u8 *v; u8 sum = 0; int i; /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + addr = ALIGN_UP(addr, 16); /* This table must be between 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); - v = (u8 *) (addr); pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; @@ -61,30 +55,30 @@ unsigned long write_pirq_routing_table(unsigned long addr) memset(pirq->rfu, 0, sizeof(pirq->rfu)); - pirq_info = (void *)(&pirq->checksum + 1); + pirq_info = (void *)(&pirq->slots); slot_num = 0; /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; pirq->size = 32 + 16 * slot_num; - for (i = 0; i < pirq->size; i++) - sum += v[i]; + { + const u8 *const v = (u8 *)(pirq); + for (i = 0; i < pirq->size; i++) + sum += v[i]; + } sum = pirq->checksum - sum; - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c new file mode 100644 index 0000000000..2e08188d15 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, +}; +static const u8 mainboard_intr_data[84] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* dedicated "enable" function (taken from thatcher) */ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + pirq_setup(); + + msr = rdmsr(LS_CFG_MSR); + /* Enable streaming store functionality. */ + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + /* Enable speculative TLB preloads. */ + msr.lo &= ~(1 << 4); + /* Enable the DC hardware prefetcher. */ + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + /* Disable the L2 way lock. */ + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c new file mode 100644 index 0000000000..b9e743c5f3 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ + bus_isa, (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan */ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /* Local Ints: Type IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c new file mode 100644 index 0000000000..0354513d6b --- /dev/null +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void smbus_setup(void) +{ + post_code(0x30); + + /* turn on secondary smbus at b20 */ + pm_write8(0x28, pm_read8(0x28) | 0x01); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + smbus_setup(); +} diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c index 6590883353..246c93fe2e 100644 --- a/src/mainboard/asus/am1i-a/OemCustomize.c +++ b/src/mainboard/asus/am1i-a/OemCustomize.c @@ -85,7 +85,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; - void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index fe0915b8e5..d143cc3967 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -40,7 +40,7 @@ #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY /* FIXME: Turtle RAM? */ +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_ENABLE_ECC_FEATURE FALSE #define BLDCFG_ECC_SYNC_FLOOD FALSE diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc040..24861c79a6 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 00295be947..1d3d3b9e0e 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -7,7 +7,6 @@ config BASE_ASUS_P2B_D select SDRAMPWR_4DIMM select HAVE_MP_TABLE select IOAPIC - select SMP config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c new file mode 100644 index 0000000000..87838b44c3 --- /dev/null +++ b/src/mainboard/asus/p2b/mainboard.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/** + * Mainboard specific enables. + * + * @param chip_info Ignored + */ +static void mainboard_init(void *chip_info) +{ + const pci_devfn_t px43 = PCI_DEV(0, 4, 3); + u32 reg; + /* + * Set up an 8-byte generic I/O decode block at device 9. + * This will be for W83781D hardware monitor. + * Port 0x290 mask 0x007 + * + * This should enable access to W83781D over the ISA bus. + */ + reg = pci_s_read_config32(px43, DEVRESB); + reg |= (0x290 | (0xe7 << 16)); + pci_s_write_config32(px43, DEVRESB, reg); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init +}; diff --git a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb index 541db02be6..77d3bb0419 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ls/overridetree.cb @@ -3,8 +3,8 @@ chip northbridge/intel/i440bx # Northbridge chip southbridge/intel/i82371eb # Southbridge register "gpo" = "0x7fbfb9ff" register "gpo22_enable" = "1" # GPO22 controls LVD port termination (0=enabled) - # GPO23 controls SCSI-50 port termination (1=enabled) - # SCSI-68 port is always terminated + # GPO23 controls SCSI-50 port termination (1=enabled) + # SCSI-68 port is always terminated device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.a off # ACPI diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 4c26925838..172f65f653 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -25,14 +25,14 @@ chip northbridge/intel/i945 end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x86" - register "pirqd_routing" = "0x85" - register "pirqe_routing" = "0x83" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" + register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x85" + register "pirqh_routing" = "0x80" register "gpe0_en" = "0" diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index 79f7347410..3e8d5f0a77 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -50,7 +50,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index 4905f1d133..b1f6e77558 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 87da010aa4..81eb6f474c 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,15 +85,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 3503e65cef..bea756a1b3 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select GFXUMA select SUPERIO_FINTEK_F81866D + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 5e83e6586f..4e2884aaaa 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -10,22 +10,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex similarity index 100% rename from src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex rename to src/mainboard/bap/ode_e20XX/spd/BAP_Q7_1066.spd.hex diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex similarity index 100% rename from src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex rename to src/mainboard/bap/ode_e20XX/spd/BAP_Q7_800.spd.hex diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 1122c43563..ae502cb9dc 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -11,7 +11,6 @@ endchoice source "src/mainboard/biostar/*/Kconfig" - config MAINBOARD_VENDOR default "Biostar" diff --git a/src/mainboard/biostar/a68n_5200/acpi/routing.asl b/src/mainboard/biostar/a68n_5200/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/routing.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index de8845a977..5803e03783 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -38,7 +38,6 @@ const CODEC_ENTRY Alc662_VerbTbl[] = { 0xff, 0xffffffff } }; - static const CODEC_TBL_LIST CodecTableList[] = { {0x10ec0662, (CODEC_ENTRY*)&Alc662_VerbTbl[0]}, diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index 9de2813f8e..1d94b5bcb4 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -85,7 +85,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; - void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 5c0f1938fc..56f760de40 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -2,7 +2,6 @@ /* No IDE functionality */ - /* Scope (_SB) { Device(PCI0) { diff --git a/src/mainboard/biostar/am1ml/acpi/routing.asl b/src/mainboard/biostar/am1ml/acpi/routing.asl index 106259d0a9..9bce4b2163 100644 --- a/src/mainboard/biostar/am1ml/acpi/routing.asl +++ b/src/mainboard/biostar/am1ml/acpi/routing.asl @@ -10,7 +10,6 @@ Name(PR0, Package(){ Package(){0x0001FFFF, 0, INTB, 0 }, Package(){0x0001FFFF, 1, INTC, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -58,7 +57,6 @@ Name(APR0, Package(){ Package(){0x0002FFFF, 2, 0, 26 }, Package(){0x0002FFFF, 3, 0, 27 }, - /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ Package(){0x0014FFFF, 0, 0, 16 }, diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index a3e8c518ea..d1a4ee72c7 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - - /* Scope (_SB) { Device(PCI0) { diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c index 688f25d129..405271b064 100644 --- a/src/mainboard/biostar/am1ml/bootblock.c +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -14,13 +15,13 @@ static void ite_evc_conf(pnp_devfn_t dev) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); + pnp_write_config(dev, PNP_IDX_MSC1, 0x40); + pnp_write_config(dev, PNP_IDX_MSC4, 0x80); + pnp_write_config(dev, PNP_IDX_MSC5, 0x00); + pnp_write_config(dev, PNP_IDX_MSC6, 0xf0); + pnp_write_config(dev, PNP_IDX_MSC9, 0x48); + pnp_write_config(dev, PNP_IDX_MSCA, 0x00); + pnp_write_config(dev, PNP_IDX_MSCB, 0x00); pnp_exit_conf_state(dev); } @@ -32,7 +33,7 @@ static void ite_gpio_conf(pnp_devfn_t dev) pnp_write_config(dev, 0x26, 0x07); pnp_write_config(dev, 0x28, 0x81); pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, PNP_IDX_IRQ1, 0x00); pnp_write_config(dev, 0x73, 0x00); pnp_write_config(dev, 0xb3, 0x01); pnp_write_config(dev, 0xb8, 0x00); @@ -41,10 +42,10 @@ static void ite_gpio_conf(pnp_devfn_t dev) pnp_write_config(dev, 0xc8, 0x00); pnp_write_config(dev, 0xc9, 0x07); pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); + pnp_write_config(dev, PNP_IDX_MSC0, 0x10); + pnp_write_config(dev, PNP_IDX_MSC4, 0x27); + pnp_write_config(dev, PNP_IDX_MSC8, 0x20); + pnp_write_config(dev, PNP_IDX_MSC9, 0x01); pnp_exit_conf_state(dev); } diff --git a/src/mainboard/biostar/am1ml/irq_tables.c b/src/mainboard/biostar/am1ml/irq_tables.c index a85f71544c..cc5f34f398 100644 --- a/src/mainboard/biostar/am1ml/irq_tables.c +++ b/src/mainboard/biostar/am1ml/irq_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #include const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/biostar/th61-itx/Kconfig b/src/mainboard/biostar/th61-itx/Kconfig new file mode 100644 index 0000000000..2719853449 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Kconfig @@ -0,0 +1,33 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_BIOSTAR_TH61_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8728F + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select NO_UART_ON_SUPERIO + +config MAINBOARD_DIR + string + default "biostar/th61-itx" + +config MAINBOARD_PART_NUMBER + string + default "TH61-ITX" + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif # BOARD_BIOSTAR_TH61_ITX diff --git a/src/mainboard/biostar/th61-itx/Kconfig.name b/src/mainboard/biostar/th61-itx/Kconfig.name new file mode 100644 index 0000000000..fecf255b81 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BIOSTAR_TH61_ITX + bool "TH61-ITX" diff --git a/src/mainboard/biostar/th61-itx/Makefile.inc b/src/mainboard/biostar/th61-itx/Makefile.inc new file mode 100644 index 0000000000..549a84fd12 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/biostar/th61-itx/acpi/ec.asl b/src/mainboard/biostar/th61-itx/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/biostar/th61-itx/acpi/platform.asl b/src/mainboard/biostar/th61-itx/acpi/platform.asl new file mode 100644 index 0000000000..bbee0a2787 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/biostar/th61-itx/acpi/superio.asl b/src/mainboard/biostar/th61-itx/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/biostar/th61-itx/acpi_tables.c b/src/mainboard/biostar/th61-itx/acpi_tables.c new file mode 100644 index 0000000000..852b0b4ae7 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/acpi_tables.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ +} diff --git a/src/mainboard/biostar/th61-itx/board_info.txt b/src/mainboard/biostar/th61-itx/board_info.txt new file mode 100644 index 0000000000..4832134217 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://biostar-usa.com/app/en-us/mb/introduction.php?S_ID=548 +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/biostar/th61-itx/cmos.default b/src/mainboard/biostar/th61-itx/cmos.default new file mode 100644 index 0000000000..6f3cec735e --- /dev/null +++ b/src/mainboard/biostar/th61-itx/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M diff --git a/src/mainboard/biostar/th61-itx/cmos.layout b/src/mainboard/biostar/th61-itx/cmos.layout new file mode 100644 index 0000000000..556b34e29d --- /dev/null +++ b/src/mainboard/biostar/th61-itx/cmos.layout @@ -0,0 +1,66 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- + +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +421 1 e 9 sata_mode + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 439 984 diff --git a/src/mainboard/biostar/th61-itx/data.vbt b/src/mainboard/biostar/th61-itx/data.vbt new file mode 100644 index 0000000000..f2ec2fcfb0 Binary files /dev/null and b/src/mainboard/biostar/th61-itx/data.vbt differ diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb new file mode 100644 index 0000000000..2329bb23e3 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -0,0 +1,79 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1565 0x3108 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: Realtek RTL8111F GbE NIC + device pci 1c.1 on end # RP #2: ASMedia ASM1042 USB3 #1 + device pci 1c.2 on end # RP #3: ASMedia ASM1042 USB3 #2 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on end # Keyboard + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x26 = 0xff + irq 0x27 = 0x30 + irq 0x28 = 0x80 + irq 0x29 = 0x80 + irq 0x2c = 0x02 + io 0x60 = 0x0a10 + io 0x62 = 0x0a00 + irq 0xb1 = 0x03 + irq 0xb3 = 0x80 + irq 0xb8 = 0x00 + irq 0xf5 = 0x27 + irq 0xf8 = 0x20 + irq 0xf9 = 0x01 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA #1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA #2 (IDE mode) + device pci 1f.6 on end # Thermal subsystem + end + end +end diff --git a/src/mainboard/biostar/th61-itx/dsdt.asl b/src/mainboard/biostar/th61-itx/dsdt.asl new file mode 100644 index 0000000000..18908d38a7 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include + #include + + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c new file mode 100644 index 0000000000..b1a99e0ee8 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/early_init.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/biostar/th61-itx/gma-mainboard.ads b/src/mainboard/biostar/th61-itx/gma-mainboard.ads new file mode 100644 index 0000000000..81097a67f7 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + -- TODO: verify this with a CPU that has an IGP + ports : constant Port_List := + (HDMI1, -- DVI + HDMI2, -- HDMI + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/biostar/th61-itx/gpio.c b/src/mainboard/biostar/th61-itx/gpio.c new file mode 100644 index 0000000000..bda5328777 --- /dev/null +++ b/src/mainboard/biostar/th61-itx/gpio.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/biostar/th61-itx/hda_verb.c b/src/mainboard/biostar/th61-itx/hda_verb.c new file mode 100644 index 0000000000..2b6d27604d --- /dev/null +++ b/src/mainboard/biostar/th61-itx/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Realtek ALC892 */ + 0x15658229, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x15658229), + AZALIA_PIN_CFG(2, 0x11, 0x01452130), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x01011412), + AZALIA_PIN_CFG(2, 0x16, 0x01016411), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c40), + AZALIA_PIN_CFG(2, 0x19, 0x02a19850), + AZALIA_PIN_CFG(2, 0x1a, 0x0181344f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/bostentech/Kconfig b/src/mainboard/bostentech/Kconfig new file mode 100644 index 0000000000..15a7657faa --- /dev/null +++ b/src/mainboard/bostentech/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_BOSTENTECH + +choice + prompt "Mainboard model" + +source "src/mainboard/bostentech/*/Kconfig.name" + +endchoice + +source "src/mainboard/bostentech/*/Kconfig" + +config MAINBOARD_VENDOR + default "Shenzhen Bostrontium Teng Technology" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_BOSTENTECH diff --git a/src/mainboard/bostentech/Kconfig.name b/src/mainboard/bostentech/Kconfig.name new file mode 100644 index 0000000000..619b526924 --- /dev/null +++ b/src/mainboard/bostentech/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BOSTENTECH + bool "Shenzhen Bostrontium Teng Technology" diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig new file mode 100644 index 0000000000..a26784062a --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_BOSTENTECH_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "bostentech/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4-4L" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Shenzhen Bostrontium Teng Technology" + +endif # BOARD_BOSTENTECH_GBYT4 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig.name b/src/mainboard/bostentech/gbyt4/Kconfig.name new file mode 100644 index 0000000000..c420d5b201 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BOSTENTECH_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc new file mode 100644 index 0000000000..11a2a4a506 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/bostentech/gbyt4/acpi/ec.asl b/src/mainboard/bostentech/gbyt4/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000000..d679d2e2bb --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NOTE: this has to be here even when the board has no LPE audio, otherwise + * it breaks the SOC specific ACPI code + */ +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () {}) +} diff --git a/src/mainboard/bostentech/gbyt4/acpi/superio.asl b/src/mainboard/bostentech/gbyt4/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c new file mode 100644 index 0000000000..7445fb057e --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM not present */ + gnvs->tpmp = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_DESKTOP; +} diff --git a/src/mainboard/bostentech/gbyt4/board_info.txt b/src/mainboard/bostentech/gbyt4/board_info.txt new file mode 100644 index 0000000000..0fe176f778 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Shenzhen Bostrontium Teng Technology +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/bostentech/gbyt4/cmos.layout b/src/mainboard/bostentech/gbyt4/cmos.layout new file mode 100644 index 0000000000..f0d18dd7ae --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/cmos.layout @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +# coreboot config options: cpu +400 1 e 2 hyper_threading +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb new file mode 100644 index 0000000000..15a5d861da --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -0,0 +1,90 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x3" + register "sata_ahci" = "0x1" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/bostentech/gbyt4/dsdt.asl b/src/mainboard/bostentech/gbyt4/dsdt.asl new file mode 100644 index 0000000000..56e01c4d1e --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + + // global NVS and variables + #include + #include + + Device (\_SB.PCI0) + { + #include + } + + #include + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/bostentech/gbyt4/early_init.c b/src/mainboard/bostentech/gbyt4/early_init.c new file mode 100644 index 0000000000..9b12a3d2fd --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/early_init.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bostentech/gbyt4/gpio.c b/src/mainboard/bostentech/gbyt4/gpio.c new file mode 100644 index 0000000000..e1d5df8bbb --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gpio.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_NC[00] */ + GPIO_INPUT, /* GPIO_S0_NC[01] */ + GPIO_INPUT, /* GPIO_S0_NC[02] */ + GPIO_INPUT, /* GPIO_S0_NC[03] */ + GPIO_INPUT, /* GPIO_S0_NC[04] */ + GPIO_INPUT, /* GPIO_S0_NC[05] */ + GPIO_INPUT, /* GPIO_S0_NC[06] */ + GPIO_INPUT, /* GPIO_S0_NC[07] */ + GPIO_INPUT, /* GPIO_S0_NC[08] */ + GPIO_INPUT, /* GPIO_S0_NC[09] */ + GPIO_INPUT, /* GPIO_S0_NC[10] */ + GPIO_INPUT, /* GPIO_S0_NC[11] */ + GPIO_INPUT, /* GPIO_S0_NC[12] */ + GPIO_INPUT, /* GPIO_S0_NC[13] */ + GPIO_INPUT, /* GPIO_S0_NC[14] */ + GPIO_INPUT, /* GPIO_S0_NC[15] */ + GPIO_INPUT, /* GPIO_S0_NC[16] */ + GPIO_INPUT, /* GPIO_S0_NC[17] */ + GPIO_INPUT, /* GPIO_S0_NC[18] */ + GPIO_INPUT, /* GPIO_S0_NC[19] */ + GPIO_INPUT, /* GPIO_S0_NC[20] */ + GPIO_INPUT, /* GPIO_S0_NC[21] */ + GPIO_INPUT, /* GPIO_S0_NC[22] */ + GPIO_INPUT, /* GPIO_S0_NC[23] */ + GPIO_INPUT, /* GPIO_S0_NC[24] */ + GPIO_INPUT, /* GPIO_S0_NC[25] */ + GPIO_INPUT, /* GPIO_S0_NC[26] */ + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_INPUT, /* GPIO_S0_SC[000] */ + GPIO_INPUT, /* GPIO_S0_SC[001] */ + GPIO_FUNC1, /* SATA_LED# */ + GPIO_FUNC1, /* PCIE_CLKREQ[0]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[1]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[2]# */ + GPIO_FUNC1, /* PCIE_CLKREQ[3]# */ + GPIO_INPUT, /* GPIO_S0_SC[007] */ + GPIO_INPUT, /* GPIO_S0_SC[008] */ + GPIO_INPUT, /* GPIO_S0_SC[009] */ + GPIO_INPUT, /* GPIO_S0_SC[010] */ + GPIO_INPUT, /* GPIO_S0_SC[011] */ + GPIO_INPUT, /* GPIO_S0_SC[012] */ + GPIO_INPUT, /* GPIO_S0_SC[013] */ + GPIO_INPUT, /* GPIO_S0_SC[014] */ + GPIO_INPUT, /* GPIO_S0_SC[015] */ + GPIO_INPUT, /* GPIO_S0_SC[016] */ + GPIO_INPUT, /* GPIO_S0_SC[017] */ + GPIO_INPUT, /* GPIO_S0_SC[018] */ + GPIO_INPUT, /* GPIO_S0_SC[019] */ + GPIO_INPUT, /* GPIO_S0_SC[020] */ + GPIO_INPUT, /* GPIO_S0_SC[021] */ + GPIO_INPUT, /* GPIO_S0_SC[022] */ + GPIO_INPUT, /* GPIO_S0_SC[023] */ + GPIO_INPUT, /* GPIO_S0_SC[024] */ + GPIO_INPUT, /* GPIO_S0_SC[025] */ + GPIO_INPUT, /* GPIO_S0_SC[026] */ + GPIO_INPUT, /* GPIO_S0_SC[027] */ + GPIO_INPUT, /* GPIO_S0_SC[028] */ + GPIO_INPUT, /* GPIO_S0_SC[029] */ + GPIO_INPUT, /* GPIO_S0_SC[030] */ + GPIO_INPUT, /* GPIO_S0_SC[031] */ + GPIO_INPUT, /* GPIO_S0_SC[032] */ + GPIO_INPUT, /* GPIO_S0_SC[033] */ + GPIO_INPUT, /* GPIO_S0_SC[034] */ + GPIO_INPUT, /* GPIO_S0_SC[035] */ + GPIO_INPUT, /* GPIO_S0_SC[036] */ + GPIO_INPUT, /* GPIO_S0_SC[037] */ + GPIO_INPUT, /* GPIO_S0_SC[038] */ + GPIO_INPUT, /* GPIO_S0_SC[039] */ + GPIO_INPUT, /* GPIO_S0_SC[040] */ + GPIO_INPUT, /* GPIO_S0_SC[041] */ + GPIO_FUNC1, /* ILB_LPC_AD[0] */ + GPIO_FUNC1, /* ILB_LPC_AD[1] */ + GPIO_FUNC1, /* ILB_LPC_AD[2] */ + GPIO_FUNC1, /* ILB_LPC_AD[3] */ + GPIO_FUNC1, /* ILB_LPC_FRAME# */ + GPIO_FUNC1, /* ILB_LPC_CLK[0] */ + GPIO_FUNC1, /* ILB_LPC_CLK[1] */ + GPIO_FUNC1, /* ILB_LPC_CLKRUN# */ + GPIO_FUNC1, /* ILB_LPC_SERIRQ */ + GPIO_FUNC1, /* PCU_SMB_DATA */ + GPIO_FUNC1, /* PCU_SMB_CLK */ + GPIO_FUNC1, /* PCU_SMB_ALERT# */ + GPIO_FUNC1, /* ILB_8254_SPKR */ + GPIO_INPUT, /* GPIO_S0_SC[055] */ + GPIO_INPUT, /* GPIO_S0_SC[056] */ + GPIO_INPUT, /* GPIO_S0_SC[057] */ + GPIO_INPUT, /* GPIO_S0_SC[058] */ + GPIO_INPUT, /* GPIO_S0_SC[059] */ + GPIO_INPUT, /* GPIO_S0_SC[060] */ + GPIO_INPUT, /* GPIO_S0_SC[061] */ + GPIO_INPUT, /* GPIO_S0_SC[062] */ + GPIO_INPUT, /* GPIO_S0_SC[063] */ + GPIO_INPUT, /* GPIO_S0_SC[064] */ + GPIO_INPUT, /* GPIO_S0_SC[065] */ + GPIO_INPUT, /* GPIO_S0_SC[066] */ + GPIO_INPUT, /* GPIO_S0_SC[067] */ + GPIO_INPUT, /* GPIO_S0_SC[068] */ + GPIO_INPUT, /* GPIO_S0_SC[069] */ + GPIO_INPUT, /* GPIO_S0_SC[070] */ + GPIO_INPUT, /* GPIO_S0_SC[071] */ + GPIO_INPUT, /* GPIO_S0_SC[072] */ + GPIO_INPUT, /* GPIO_S0_SC[073] */ + GPIO_INPUT, /* GPIO_S0_SC[074] */ + GPIO_INPUT, /* GPIO_S0_SC[075] */ + GPIO_INPUT, /* GPIO_S0_SC[076] */ + GPIO_INPUT, /* GPIO_S0_SC[077] */ + GPIO_INPUT, /* GPIO_S0_SC[078] */ + GPIO_INPUT, /* GPIO_S0_SC[079] */ + GPIO_INPUT, /* GPIO_S0_SC[080] */ + GPIO_INPUT, /* GPIO_S0_SC[081] */ + GPIO_INPUT, /* GPIO_S0_SC[082] */ + GPIO_INPUT, /* GPIO_S0_SC[083] */ + GPIO_INPUT, /* GPIO_S0_SC[084] */ + GPIO_INPUT, /* GPIO_S0_SC[085] */ + GPIO_INPUT, /* GPIO_S0_SC[086] */ + GPIO_INPUT, /* GPIO_S0_SC[087] */ + GPIO_INPUT, /* GPIO_S0_SC[088] */ + GPIO_INPUT, /* GPIO_S0_SC[089] */ + GPIO_INPUT, /* GPIO_S0_SC[090] */ + GPIO_INPUT, /* GPIO_S0_SC[091] */ + GPIO_INPUT, /* GPIO_S0_SC[092] */ + GPIO_INPUT, /* GPIO_S0_SC[093] */ + GPIO_INPUT, /* GPIO_S0_SC[094] */ + GPIO_INPUT, /* GPIO_S0_SC[095] */ + GPIO_INPUT, /* GPIO_S0_SC[096] */ + GPIO_INPUT, /* GPIO_S0_SC[097] */ + GPIO_INPUT, /* GPIO_S0_SC[098] */ + GPIO_INPUT, /* GPIO_S0_SC[099] */ + GPIO_INPUT, /* GPIO_S0_SC[100] */ + GPIO_INPUT, /* GPIO_S0_SC[101] */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_INPUT, /* GPIO_S5[00] */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[1]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[2]# */ + GPIO_FUNC6, /* PMC_WAKE_PCIE[3]# */ + GPIO_INPUT, /* GPIO_S5[04] */ + GPIO_INPUT, /* GPIO_S5[05] */ + GPIO_INPUT, /* GPIO_S5[06] */ + GPIO_INPUT, /* GPIO_S5[07] */ + GPIO_INPUT, /* GPIO_S5[08] */ + GPIO_INPUT, /* GPIO_S5[09] */ + GPIO_INPUT, /* GPIO_S5[10] */ + GPIO_INPUT, /* GPIO_S5[11] */ + GPIO_INPUT, /* GPIO_S5[12] */ + GPIO_INPUT, /* GPIO_S5[13] */ + GPIO_INPUT, /* GPIO_S5[14] */ + GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# */ + GPIO_FUNC(0, PULL_UP, 20K), /* PMC_PWRBTN# */ + GPIO_INPUT, /* GPIO_S5[17] */ + GPIO_INPUT, /* GPIO_S5[18] */ + GPIO_INPUT, /* GPIO_S5[19] */ + GPIO_INPUT, /* GPIO_S5[20] */ + GPIO_INPUT, /* GPIO_S5[21] */ + GPIO_INPUT, /* GPIO_S5[22] */ + GPIO_INPUT, /* GPIO_S5[23] */ + GPIO_INPUT, /* GPIO_S5[24] */ + GPIO_INPUT, /* GPIO_S5[25] */ + GPIO_INPUT, /* GPIO_S5[26] */ + GPIO_INPUT, /* GPIO_S5[27] */ + GPIO_INPUT, /* GPIO_S5[28] */ + GPIO_INPUT, /* GPIO_S5[29] */ + GPIO_INPUT, /* GPIO_S5[30] */ + GPIO_INPUT, /* GPIO_S5[31] */ + GPIO_INPUT, /* GPIO_S5[32] */ + GPIO_INPUT, /* GPIO_S5[33] */ + GPIO_INPUT, /* GPIO_S5[34] */ + GPIO_INPUT, /* GPIO_S5[35] */ + GPIO_INPUT, /* GPIO_S5[36] */ + GPIO_INPUT, /* GPIO_S5[37] */ + GPIO_INPUT, /* GPIO_S5[38] */ + GPIO_INPUT, /* GPIO_S5[39] */ + GPIO_INPUT, /* GPIO_S5[40] */ + GPIO_INPUT, /* GPIO_S5[41] */ + GPIO_INPUT, /* GPIO_S5[42] */ + GPIO_INPUT, /* GPIO_S5[43] */ + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl b/src/mainboard/bostentech/gbyt4/irqroute.c similarity index 51% rename from src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl rename to src/mainboard/bostentech/gbyt4/irqroute.c index 66940633a4..6fa036672e 100644 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl +++ b/src/mainboard/bostentech/gbyt4/irqroute.c @@ -1,3 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/bostentech/gbyt4/irqroute.h b/src/mainboard/bostentech/gbyt4/irqroute.h new file mode 100644 index 0000000000..946062270d --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/irqroute.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/bostentech/gbyt4/mainboard.c b/src/mainboard/bostentech/gbyt4/mainboard.c new file mode 100644 index 0000000000..d0131bc2d1 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/mainboard.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#if CONFIG(VGA_ROM_RUN) +#include +#endif +#include + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bostentech/gbyt4/romstage.c b/src/mainboard/bostentech/gbyt4/romstage.c new file mode 100644 index 0000000000..ec18cfc05b --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_SMBUS; + mp->mainboard.dram_is_slotted = 1; + mp->mainboard.spd_addrs[0] = 0x50; /* Board only has one slot */ +} diff --git a/src/mainboard/clevo/Kconfig b/src/mainboard/clevo/Kconfig new file mode 100644 index 0000000000..d5ae6c1b02 --- /dev/null +++ b/src/mainboard/clevo/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_CLEVO + +choice + prompt "Mainboard model" + +source "src/mainboard/clevo/*/Kconfig.name" + +endchoice + +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + default "Clevo" + +endif diff --git a/src/mainboard/clevo/Kconfig.name b/src/mainboard/clevo/Kconfig.name new file mode 100644 index 0000000000..730b6bc389 --- /dev/null +++ b/src/mainboard/clevo/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CLEVO + bool "Clevo" diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig new file mode 100644 index 0000000000..c08b321630 --- /dev/null +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -0,0 +1,88 @@ +if BOARD_CLEVO_L140CU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "clevo/cml-u" + +config MAINBOARD_PART_NUMBER + string + default "L140CU" if BOARD_CLEVO_L140CU + +config MAINBOARD_VERSION + string + default "2.1A" if BOARD_CLEVO_L140CU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + hex + default 0xc00000 if BOARD_CLEVO_L140CU + +config CONSOLE_POST + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 if BOARD_CLEVO_L140CU + +config DIMM_MAX + int + default 2 if BOARD_CLEVO_L140CU + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,9b41.rom" + +config VGA_BIOS_ID + string + default "8086,9b41" + +config TPM_PIRQ + hex + default 0x10 if BOARD_CLEVO_L140CU # GPP_A7/PIRQA# + +config POST_DEVICE + bool + default n + +config VARIANT_DIR + string + default "l140cu" if BOARD_CLEVO_L140CU + +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 500 + +endif diff --git a/src/mainboard/clevo/cml-u/Kconfig.name b/src/mainboard/clevo/cml-u/Kconfig.name new file mode 100644 index 0000000000..d5f867a475 --- /dev/null +++ b/src/mainboard/clevo/cml-u/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CLEVO_L140CU + bool "L140CU" diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc new file mode 100644 index 0000000000..6a388f27a1 --- /dev/null +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/acpi/gpe.asl b/src/mainboard/clevo/cml-u/acpi/gpe.asl new file mode 100644 index 0000000000..c1bc04dc9a --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/clevo/cml-u/acpi/mainboard.asl b/src/mainboard/clevo/cml-u/acpi/mainboard.asl new file mode 100644 index 0000000000..dfa81d3914 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/mainboard.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x50 /* GPP_E16 */ +#define EC_GPE_SWI 0x29 /* GPP_D9 */ +#define EC_COLOR_KEYBOARD 0 +#include + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/clevo/cml-u/acpi/sleep.asl b/src/mainboard/clevo/cml-u/acpi/sleep.asl new file mode 100644 index 0000000000..48c50e075e --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/clevo/cml-u/board_info.txt b/src/mainboard/clevo/cml-u/board_info.txt new file mode 100644 index 0000000000..67109938da --- /dev/null +++ b/src/mainboard/clevo/cml-u/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl new file mode 100644 index 0000000000..bffb6683ac --- /dev/null +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex similarity index 89% rename from src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex rename to src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex index 390e5a5417..f747f7c34e 100644 --- a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex +++ b/src/mainboard/clevo/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex @@ -1,12 +1,12 @@ -# Samsung K4AAG165WA-BCWE +# Samsung K4AAG165WA-BCTD 23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A 20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B 0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -20,7 +20,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 -35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc new file mode 100644 index 0000000000..bd3e899dc8 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt b/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt new file mode 100644 index 0000000000..86230320af --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/board_info.txt @@ -0,0 +1,2 @@ +Board name: L140CU +Release year: 2020 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c b/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c new file mode 100644 index 0000000000..2b673021b5 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "gpio.h" + +void bootblock_mainboard_init(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt b/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt new file mode 100644 index 0000000000..f14d8073e9 Binary files /dev/null and b/src/mainboard/clevo/cml-u/variants/l140cu/data.vbt differ diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb new file mode 100644 index 0000000000..3ee20e9c4b --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -0,0 +1,205 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + /* Touchpad */ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + #register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + subsystemid 0x1558 0x1401 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 + end + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi # CNVi wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""ELAN040D"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "1" + # Port 2 (J_SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 3 (J_SSD1) + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 Card reader + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 + chip drivers/intel/wifi + device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) + end + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0E01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0F01" + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.h b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.h new file mode 100644 index 0000000000..1f7d119947 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.h @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Name format: / */ + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), +}; + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */ + PAD_NC(GPD2, UP_20K), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */ + PAD_NC(GPD6, UP_20K), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */ + PAD_NC(GPD9, UP_20K), + PAD_NC(GPD10, UP_20K), + PAD_NC(GPD11, UP_20K), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* RCIN# / SB_KBCRST# */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LAD0 / LPC_AD0 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LAD1 / LPC_AD1 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LAD2 / LPC_AD2 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LAD3 / LPC_AD3 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LFRAME# / LPC_FRAME# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PIRQA# / TPM_PIRQ# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# / PM_CLKRUN# + Note: R209 is populated despite being + marked no-stuff in schematic + */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* CLKOUT_LPC0 / PCLK_KBC */ + PAD_NC(GPP_A10, UP_20K), + PAD_NC(GPP_A11, UP_20K), /* INTP_OUT + (Type-C VBUS_SENSE; unused in cb) + */ + PAD_NC(GPP_A12, UP_20K), + PAD_NC(GPP_A13, UP_20K), /* SUSWARN# + (unused due to missing DeepSx support) + */ + PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A15, UP_20K), + PAD_NC(GPP_A16, UP_20K), + PAD_NC(GPP_A17, NONE), /* LEDKB_DET# + (unused in cb; all devices of that + model have KB LED) + */ + PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A19, UP_20K), + PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_A20 / TEST_R */ + PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A22, UP_20K), + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, UP_20K), + PAD_NC(GPP_B1, UP_20K), + PAD_NC(GPP_B2, UP_20K), /* CNVI_WAKE# + (UART_WAKE# in M.2 spec; unused) + */ + PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),/* GPP_B3 (touchpad interrupt) */ + PAD_NC(GPP_B4, UP_20K), + PAD_NC(GPP_B5, UP_20K), + PAD_NC(GPP_B6, UP_20K), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# / WLAN_CLKREQ# */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3# / CARD_CLKREQ# */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# / SSD2_CLKREQ# */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* SRCCLKREQ5# / SSD1_CLKREQ# */ + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */ + PAD_NC(GPP_B15, UP_20K), + PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, UP_20K), + PAD_NC(GPP_B19, UP_20K), + PAD_NC(GPP_B20, UP_20K), + PAD_NC(GPP_B21, UP_20K), + PAD_NC(GPP_B22, UP_20K), + PAD_NC(GPP_B23, UP_20K), + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */ + PAD_NC(GPP_C2, UP_20K), + PAD_NC(GPP_C3, UP_20K), + PAD_NC(GPP_C4, UP_20K), + PAD_NC(GPP_C5, UP_20K), + PAD_NC(GPP_C6, UP_20K), + PAD_NC(GPP_C7, UP_20K), + PAD_NC(GPP_C8, UP_20K), + PAD_NC(GPP_C9, UP_20K), + PAD_NC(GPP_C10, UP_20K), + PAD_NC(GPP_C11, UP_20K), + PAD_NC(GPP_C12, UP_20K), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPP_C13 / SSD1_PWR_DN# */ + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL */ + PAD_NC(GPP_C18, UP_20K), + PAD_NC(GPP_C19, UP_20K), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + PAD_NC(GPP_C22, UP_20K), + PAD_NC(GPP_C23, UP_20K), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, UP_20K), + PAD_NC(GPP_D1, UP_20K), + PAD_NC(GPP_D2, UP_20K), + PAD_NC(GPP_D3, UP_20K), + PAD_NC(GPP_D4, UP_20K), + PAD_NC(GPP_D5, UP_20K), + PAD_NC(GPP_D6, UP_20K), + PAD_NC(GPP_D7, UP_20K), + PAD_CFG_GPO(GPP_D8, 1, DEEP), /* SB_BLON */ + PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), /* EC SWI# */ + PAD_NC(GPP_D10, NONE), /* DDR_TYPE_D10 + (unused; there is only one on-board + ram type/model) + */ + PAD_NC(GPP_D11, NONE), /* BOARD_ID + (unused in cb; we already know the + device model) + */ + PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D13, UP_20K), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* SSD2_PWR_DN# */ + PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D19, UP_20K), + PAD_NC(GPP_D20, UP_20K), + PAD_NC(GPP_D21, NONE), /* TPM_DET# + (currently unused in cb; there seem + to be no devices without TPM) + */ + PAD_NC(GPP_D22, NONE), /* DDR_TYPE_D22 + (unused in cb; there is only one + on-board ram type) + */ + PAD_NC(GPP_D23, UP_20K), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, UP_20K), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 / SATAGP2 */ + PAD_NC(GPP_E3, UP_20K), + PAD_NC(GPP_E4, UP_20K), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* DEVSLP2 */ + PAD_NC(GPP_E7, UP_20K), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPB_HPD0 / MUX_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPC_HPD1 / HDMI_HPD */ + PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */ + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), /* EC SCI# */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ + PAD_NC(GPP_E18, UP_20K), + PAD_NC(GPP_E19, NONE), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DPPC_CTRLCLK / HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DPPC_CTRLDATA / HDMI_CTRLDATA */ + PAD_NC(GPP_E22, UP_20K), + PAD_NC(GPP_E23, UP_20K), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, UP_20K), + PAD_NC(GPP_F1, UP_20K), + PAD_NC(GPP_F2, UP_20K), + PAD_NC(GPP_F3, UP_20K), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */ + PAD_NC(GPP_F8, UP_20K), + PAD_NC(GPP_F9, UP_20K), + PAD_NC(GPP_F10, UP_20K), + PAD_NC(GPP_F11, UP_20K), + PAD_NC(GPP_F12, UP_20K), + PAD_NC(GPP_F13, UP_20K), + PAD_NC(GPP_F14, UP_20K), + PAD_NC(GPP_F15, UP_20K), + PAD_NC(GPP_F16, UP_20K), + PAD_NC(GPP_F17, UP_20K), + PAD_NC(GPP_F18, UP_20K), + PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F22, UP_20K), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, UP_20K), + PAD_NC(GPP_G1, UP_20K), + PAD_NC(GPP_G2, UP_20K), + PAD_NC(GPP_G3, UP_20K), + PAD_NC(GPP_G4, UP_20K), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, UP_20K), + PAD_NC(GPP_G7, UP_20K), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, UP_20K), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# / CNVI_RST# */ + PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), /* MODEM_CLKREQ / CNVI_CLKREQ */ + PAD_NC(GPP_H3, UP_20K), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C2_SDA / SMD_7411 */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C2_SCL / SMC_7411 */ + PAD_NC(GPP_H6, UP_20K), + PAD_NC(GPP_H7, UP_20K), + PAD_NC(GPP_H8, UP_20K), + PAD_NC(GPP_H9, UP_20K), + PAD_NC(GPP_H10, UP_20K), + PAD_NC(GPP_H11, UP_20K), + PAD_NC(GPP_H12, UP_20K), + PAD_NC(GPP_H13, UP_20K), + PAD_NC(GPP_H14, UP_20K), + PAD_NC(GPP_H15, UP_20K), + PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H17, UP_20K), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */ + PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H23, UP_20K), +}; + +#endif + +#endif diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c new file mode 100644 index 0000000000..7bb073698d --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581401, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581401), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel GPU HDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c new file mode 100644 index 0000000000..4b0ddd4823 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c new file mode 100644 index 0000000000..4cad131765 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/romstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = {.spd_index = 0}, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + + /* Values of the resistors connected to the DDR_RCOMP_[2:0] pins of the CPU */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Interleaved ("back-to-back") pin mapping */ + .dq_pins_interleaved = 1, + + /* + * DDR4 Vref mapping + * VREF_CA goes to CH_A and VREF_DQ_B (DDR1_VREF_DQ) goes to CH_B. + */ + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index 5469c94f15..e96ee34aa4 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ void bootblock_mainboard_early_init(void) * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0; sch5545_early_init(0x2e); diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 2719460a9e..8894d8b5d4 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -106,7 +106,6 @@ static const struct ec_val_reg ec_hwm_init_seq[] = { { 0x03, 0x0071 }, }; - static const ec_chassis_tdp_t ec_hwm_chassis3[] = { { 0x33, 0x0005, TDP_COMMON }, { 0x2f, 0x0018, TDP_COMMON }, @@ -336,8 +335,6 @@ static const ec_chassis_tdp_t ec_hwm_chassis6[] = { { 0x03, 0x028d, TDP_COMMON }, }; - - static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) { uint8_t int_sts, int_cond; @@ -424,7 +421,7 @@ static uint8_t ec_read_write_reg(uint8_t ldn, uint16_t reg, uint8_t *value, uint uint16_t sch5545_get_ec_fw_version(void) { - uint8_t val; + uint8_t val = 0; uint16_t ec_fw_version; /* Read the FW version currently loaded used by EC */ @@ -502,7 +499,7 @@ void sch5545_update_ec_firmware(uint16_t ec_version) void sch5545_ec_hwm_early_init(void) { - uint8_t val; + uint8_t val = 0; int i; printk(BIOS_DEBUG, "%s\n", __func__); @@ -608,7 +605,7 @@ static void prepare_for_hwm_ec_sequence(uint8_t write_only, uint8_t *value) void sch5545_ec_hwm_init(void *unused) { - uint8_t val, val_2fc, chassis_type, fan_speed_full = 0; + uint8_t val = 0, val_2fc, chassis_type, fan_speed_full = 0; printk(BIOS_DEBUG, "%s\n", __func__); sch5545_emi_init(0x2e); diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c index 5947b7a361..398594f828 100644 --- a/src/mainboard/elmex/pcm205400/irq_tables.c +++ b/src/mainboard/elmex/pcm205400/irq_tables.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include #include #include - static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -29,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -66,19 +63,14 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) @@ -93,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig index fbb8e9e44f..53e792044b 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig +++ b/src/mainboard/elmex/pcm205401/Kconfig @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +# The code for this board is under elmex/pcm205400 + if BOARD_ELMEX_PCM205401 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name index f70b215abc..eb14caca73 100644 --- a/src/mainboard/elmex/pcm205401/Kconfig.name +++ b/src/mainboard/elmex/pcm205401/Kconfig.name @@ -1,2 +1,4 @@ +# The code for this board is under elmex/pcm205400 + config BOARD_ELMEX_PCM205401 bool "pcm205401" diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 368f7f3a69..06a7ea82a0 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -13,10 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARCH_TIMER select BOARD_ROMSIZE_KB_4096 - select BOOTBLOCK_CONSOLE select BOOTBLOCK_CUSTOM select BOOT_DEVICE_NOT_SPI_FLASH - select CONSOLE_SERIAL select DRIVERS_UART_PL011 select HAVE_LINEAR_FRAMEBUFFER select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S index eb595b9d59..287ddbe281 100644 --- a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S +++ b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Early initialization code for aarch64 (a.k.a. armv8) - * - * - * SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index fee2a36e78..6b6ac720cf 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h index 3025e0a66f..50dd35ebdc 100644 --- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Memory map for QEMU virt machine since diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index e6da3a6cac..7bf9260f8a 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -1,10 +1,5 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c index 5248110c47..755a661601 100644 --- a/src/mainboard/emulation/qemu-aarch64/media.c +++ b/src/mainboard/emulation/qemu-aarch64/media.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index 99f8f22a57..f739ddf4f7 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c index 26fc547a80..0fac64d234 100644 --- a/src/mainboard/emulation/qemu-aarch64/mmio.c +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -1,13 +1,9 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VIRT_UART_BASE; } diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 64e5bb7168..a91299873a 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 - select CONSOLE_SERIAL select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 9d76d9ddd0..4ddc6d2adc 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,14 +28,16 @@ SECTIONS { /* TODO: does this thing emulate SRAM? */ - BOOTBLOCK(0x00000, 64K) - FMAP_CACHE(0x10000, 2K) + REGION(flash, 0, CONFIG_ROM_SIZE, 4K) DRAM_START(0x60000000) STACK(0x60000000, 64K) - ROMSTAGE(0x60010000, 128K) - RAMSTAGE(0x60030000, 16M) - + BOOTBLOCK(0x60010000, 128K) + FMAP_CACHE(0x60030000, 4K) + TIMESTAMP(0x60031000, 1K) /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x61030000, 16K) + TTB(0x60034000, 16K) + ROMSTAGE(0x60038000, 128K) + RAMSTAGE(0x60060000, 16M) + POSTRAM_CBFS_CACHE(0x61060000, 8M) } diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c index 3f239153db..0f07e7f1ef 100644 --- a/src/mainboard/emulation/qemu-armv7/mmio.c +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -4,7 +4,7 @@ #define VEXPRESS_UART0_IO_ADDRESS (0x10009000) -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return VEXPRESS_UART0_IO_ADDRESS; } diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 06ac685d3d..9187b05d22 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_ASAN_IN_ROMSTAGE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2b7d2036e0..d19d6c8207 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -192,10 +192,10 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * t->size = qemu_get_memory_size() / 1024; t->data_width = 64; t->total_width = 64; - t->form_factor = 9; /* DIMM */ + t->form_factor = MEMORY_FORMFACTOR_DIMM; t->device_locator = smbios_add_string(t->eos, "Virtual"); - t->memory_type = 0x12; /* DDR */ - t->type_detail = 0x80; /* Synchronous */ + t->memory_type = MEMORY_TYPE_DDR; + t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; t->speed = 200; t->clock_speed = 200; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index c6d7e40fef..4b1bf3287e 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -5,26 +5,26 @@ #include static uint8_t *buf = (void *)0; -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) buf; } -void uart_init(int idx) +void uart_init(unsigned int idx) { } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { } diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index fafa03b45d..efb3a4f7e1 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,12 +16,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 47d26bf7dd..fcf50a9bd0 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 5b556fc190..ee0f337f6d 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -57,8 +57,6 @@ config OPENSBI_PLATFORM # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 default 0x80040000 if COREBOOT_ROMSIZE_KB_256 default 0x80080000 if COREBOOT_ROMSIZE_KB_512 default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 4eee12b933..19a2b0016c 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -4,7 +4,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) QEMU_VIRT_UART0; } diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index d6e0510274..efefc52d62 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -3,7 +3,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t) 0x02100000; } diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index ca19e0582c..0f23ed2a0a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select DISABLE_HPET select INTEL_GMA_HAVE_VBT - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select USE_VENDORCODE_ELTAN config ONBOARD_SAMSUNG_MEM diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index 8aff5417e0..e729e0140b 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -36,8 +36,8 @@ Device (EC0) Method (TSRD, 1, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) + Local0 = Arg0 + Arg0 = Local0 Return (\_SB.DPTF.CTOK (CPUT)) } @@ -45,27 +45,27 @@ Device (EC0) Method (PAT0, 2, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) - Store(Arg1, Local0) - Store(Local0, Arg1) + Local0 = Arg0 + Arg0 = Local0 + Local0 = Arg1 + Arg1 = Local0 } /* Set Aux Trip Point 1 */ Method (PAT1, 2, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) - Store(Arg1, Local0) - Store(Local0, Arg1) + Local0 = Arg0 + Arg0 = Local0 + Local0 = Arg1 + Arg1 = Local0 } /* Disable Aux Trip Point */ Method (PATD, 1, Serialized) { /* Prevent iasl remarks about unused parameters */ - Store(Arg0, Local0) - Store(Local0, Arg0) + Local0 = Arg0 + Arg0 = Local0 } } diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 102450a77a..95e2565a80 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,40 +36,23 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" - register "SaImguEnable" = "0" - register "Cio2Enable" = "0" register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" - register "EnableLan" = "1" - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s @@ -209,21 +192,13 @@ chip soc/intel/skylake register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled register "SsicPortEnable" = "0" @@ -254,10 +229,12 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # Thermal Subsystem + device pci 05.0 off end # SA IMGU device pci 08.0 on end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 238e87b071..2fd7851638 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index f90467cdb9..c4f1b08216 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 7924edfb45..d7b642aab5 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -79,9 +79,9 @@ Scope(\_SB) { Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, , Local0) Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) + Divide(Local3, 0x64, , Local0) Increment(Local0) Store(Local0, Index(PBST, 2)) @@ -184,9 +184,9 @@ Scope(\_SB) { Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) + Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, , Local0) Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) + Divide(Local3, 0x64, , Local0) Increment(Local0) Store(Local0, Index(PBST, 2)) diff --git a/src/mainboard/getac/p470/acpi/gpe.asl b/src/mainboard/getac/p470/acpi/gpe.asl index e72b980183..b9e4056ee7 100644 --- a/src/mainboard/getac/p470/acpi/gpe.asl +++ b/src/mainboard/getac/p470/acpi/gpe.asl @@ -15,7 +15,7 @@ Scope (_GPE) // Software GPE Method (_L02, 0) { - Store (0, GPEC) + GPEC = 0 } // USB1 @@ -42,7 +42,7 @@ Scope (_GPE) // SMBus (Reserved!) Method (_L07, 0) { - // Store (0x20, \_SB.PCI0.SBUS.HSTS) + // \_SB.PCI0.SBUS.HSTS = 0x20 } // COM1/COM2 (RI) diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index b5b5223a5f..1e8d64eac5 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -44,7 +44,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) ecdt->ec_control.addrl = 0x66; ecdt->ec_control.addrh = 0; - ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ + ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; ecdt->ec_data.bit_width = 8; ecdt->ec_data.bit_offset = 0; ecdt->ec_data.addrl = 0x62; diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index e6865dd7f2..3fdc1581ec 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #define ENABLE_TPM -#undef ENABLE_FDC // There is no Floppy for this laptop #include DefinitionBlock( diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 8550f69d03..087e279ac4 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index d6f1f5329b..c0f198f4e7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -27,14 +27,14 @@ chip northbridge/intel/i945 end chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x8c" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x83" - register "pirqd_routing" = "0x8b" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x85" + register "pirqh_routing" = "0x80" # GPI routing # 0 No effect (default) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 79094e6009..46940bd91f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -53,7 +53,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 7c667b527d..0d07bdba06 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 1ae2f7b31e..2d5aa7552d 100644 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -15,22 +15,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Elpida_EDJ2116DEBG - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 8046be6477..f24c9e9ead 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -40,7 +40,7 @@ static void mainboard_final(void *chip_info) ABAR &= 0xFFFFFC00; memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ *memptr = 0x21; /* force to GEN2 and start re-negotiate */ - mdelay (1); + mdelay(1); *memptr = 0x20; } diff --git a/src/mainboard/gizmosphere/gizmo/Elpida_EDJ2116DEBG.spd.hex b/src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex similarity index 100% rename from src/mainboard/gizmosphere/gizmo/Elpida_EDJ2116DEBG.spd.hex rename to src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 7a02ec851b..6375bc4982 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select GFXUMA select HUDSON_IMC_ENABLE + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc index 653dcc3529..0f808f076f 100644 --- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc @@ -10,22 +10,5 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_MT41J128M16JT - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex b/src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex similarity index 100% rename from src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex rename to src/mainboard/gizmosphere/gizmo2/spd/Micron_MT41J128M16JT.spd.hex diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig new file mode 100644 index 0000000000..894d5666b5 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_ASURADA_COMMON + def_bool n + +if BOARD_GOOGLE_ASURADA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8192 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + +config MAINBOARD_DIR + string + default "google/asurada" + +config MAINBOARD_PART_NUMBER + string + default "Asurada" if BOARD_GOOGLE_ASURADA + default "Hayato" if BOARD_GOOGLE_HAYATO + +config DRIVER_TPM_SPI_BUS + hex + default 0x0 + +# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 9 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x2 + +endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name new file mode 100644 index 0000000000..6f287e50f9 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig.name @@ -0,0 +1,9 @@ +comment "Asurada" + +config BOARD_GOOGLE_ASURADA + bool "-> Asurada" + select BOARD_GOOGLE_ASURADA_COMMON + +config BOARD_GOOGLE_HAYATO + bool "-> Hayato" + select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc new file mode 100644 index 0000000000..8395e4a35b --- /dev/null +++ b/src/mainboard/google/asurada/Makefile.inc @@ -0,0 +1,17 @@ +subdirs-y += sdram_params/ + +bootblock-y += memlayout.ld +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += boardid.c +romstage-y += sdram_configs.c + +ramstage-y += memlayout.ld +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/asurada/board_info.txt b/src/mainboard/google/asurada/board_info.txt new file mode 100644 index 0000000000..b8059ad8f2 --- /dev/null +++ b/src/mainboard/google/asurada/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Asurada MediaTek MT8192 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c new file mode 100644 index 0000000000..2c8efcddd8 --- /dev/null +++ b/src/mainboard/google/asurada/boardid.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +uint32_t sku_id(void) +{ + return 0; +} + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c new file mode 100644 index 0000000000..5dcae8c79b --- /dev/null +++ b/src/mainboard/google/asurada/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c new file mode 100644 index 0000000000..8f9fa5334c --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_write_protect_state(void) +{ + return 0; +} + +int tis_plat_irq_status(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd new file mode 100644 index 0000000000..2635854866 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb new file mode 100644 index 0000000000..0bdeec2b5f --- /dev/null +++ b/src/mainboard/google/asurada/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8192 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c new file mode 100644 index 0000000000..9146d7bc1d --- /dev/null +++ b/src/mainboard/google/asurada/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_init(struct device *dev) +{ + setup_usb_host(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/asurada/memlayout.ld similarity index 60% rename from src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl rename to src/mainboard/google/asurada/memlayout.ld index 66940633a4..0f1fcec9a0 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/asurada/memlayout.ld @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c new file mode 100644 index 0000000000..3a97ee5393 --- /dev/null +++ b/src/mainboard/google/asurada/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void do_board_reset(void) +{ +} diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c new file mode 100644 index 0000000000..9efcb32dae --- /dev/null +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const char *const sdram_configs[] = { + [0] = "sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB", + [1] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB", +}; + +static struct sdram_info params; + +const struct sdram_info *get_sdram_config(void) +{ + uint32_t ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) || + cbfs_boot_load_file(sdram_configs[ramcode], ¶ms, sizeof(params), + CBFS_TYPE_STRUCT) != sizeof(params)) + die("Cannot load SDRAM parameter file for RAM code: %#x", ramcode); + + return ¶ms; +} diff --git a/src/mainboard/google/asurada/sdram_params/Makefile.inc b/src/mainboard/google/asurada/sdram_params/Makefile.inc new file mode 100644 index 0000000000..acc8b5822f --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/Makefile.inc @@ -0,0 +1,10 @@ +sdram-params := +sdram-params += sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB + +$(foreach params,$(sdram-params), \ + $(eval cbfs-files-y += $(params)) \ + $(eval $(params)-file := $(params).c:struct) \ + $(eval $(params)-type := struct) \ + $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ +) diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c new file mode 100644 index 0000000000..8ae9b69bb1 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c new file mode 100644 index 0000000000..36fc0a29ce --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_6GB_3_3, +}; diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index c5e00fd148..8e492556a7 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON select MAINBOARD_HAS_TPM1 select INTEL_INT15 select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_BUDDY + select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_BUDDY if BOARD_GOOGLE_BASEBOARD_AURON diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a84aa98eeb..a3097624fe 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,15 +15,6 @@ chip soc/intel/broadwell # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 371d91e8af..050d9cd54d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -5,7 +5,6 @@ #include "ec.h" #include "variant.h" - __weak void lan_init(void) { } diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 70b1ebd552..60aef30a58 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc index a446268132..69f8fd8fae 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_paine/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Micron_4KTF25664HZ # 0b0000 SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 67b9131c65..da80fecba8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc index a446268132..69f8fd8fae 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Micron_4KTF25664HZ # 0b0000 SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f814280b15..f14896425a 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index e35d3a5529..75c202d663 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc index a6a8232f48..18b1062bb5 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/gandof/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13 } SPD_SOURCES = Samsung_M471B5674EB0-YK0 # 0b0000 SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0001 @@ -14,16 +12,4 @@ SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0101 SPD_SOURCES += empty # 0b0110 SPD_SOURCES += empty # 0b0111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 70b1ebd552..60aef30a58 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/broadwell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc index c136955d4c..e4ffcf8f6a 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO47, GPIO9, GPIO13, GPIO8} SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 # 0b0000 2GB SPD_SOURCES += empty # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 # 0b1101 4GB SPD_SOURCES += samsung_4GiB_dimm_K4B8G1646Q-MYK0 # 0b1110 8GB SPD_SOURCES += empty # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 0daf308922..750470e89c 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -104,7 +104,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) if (spd_file_len < SPD_LEN) die("Missing SPD data."); - /* CH0 */ memcpy(pei_data->spd_data[0][0], spd_file + (spd_index * SPD_LEN), SPD_LEN); diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 93e96cac3f..c5d27476c7 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -3,8 +3,7 @@ chip soc/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc index aaf9b36b3a..cc1542fce2 100644 --- a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # { GPIO65, GPIO67, GPIO68, GPIO69 } SPD_SOURCES = empty # 0b0000 SPD_SOURCES += empty # 0b0001 @@ -22,16 +20,4 @@ SPD_SOURCES += hynix_16 # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += elpida_16 # 0b1111 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 0c9311f70c..cbf9dc40dc 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -1,6 +1,5 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO def_bool n - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP @@ -60,4 +59,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER config ENABLE_DDR_2X_REFRESH default y +config PCIEXP_AER + def_bool n + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 304f3cf38f..8fdfbd79a0 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -36,15 +36,6 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e87f431494..7eba3c2c2f 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -14,8 +14,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_FINALIZE); } - - static void mainboard_init(struct device *dev) { lan_init(); diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 7ac37b2d46..315fd6d7bb 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -15,7 +15,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // TODO: MLR // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 0c63305bf1..94e5a2151a 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/sandybridge # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index df51f66518..2ffa3aa5e9 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,15 +79,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index fc38136015..d2e2aa552a 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -153,7 +153,6 @@ static void program_keyboard_type(u32 search_address, u32 search_length) } else printk(BIOS_DEBUG, "Error: Could not locate VPD area\n"); - printk(BIOS_DEBUG, "Setting Keyboard type in EC to "); printk(BIOS_DEBUG, (kbd_type == EC_KBD_JP) ? "Japanese" : "English"); printk(BIOS_DEBUG, ".\n"); diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index a3db6d78d8..1e8f8c23ff 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN select SYSTEM_TYPE_LAPTOP select USE_GOOGLE_FSP + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 240baca958..e85e93775c 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -88,7 +88,6 @@ Scope (\_SB.PCI0.I2C2) } } - Scope (\_SB.PCI0.LPEA) { Name (GBUF, ResourceTemplate () diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 17f14a29a1..b8266b31dc 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -19,7 +19,6 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc index 5e3cf38f90..8a9cee84db 100644 --- a/src/mainboard/google/cyan/variants/banon/Makefile.inc +++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc @@ -5,8 +5,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += empty @@ -14,17 +12,3 @@ SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index 6bc9e82dd3..b2d1cbe355 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl index 2cb4bf392d..e9d7524305 100644 --- a/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 46 #define DPTF_TSR0_CRITICAL 60 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR1_PASSIVE 48 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 68 #define DPTF_TSR2_CRITICAL 80 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 11f918b79a..2f21fd93d5 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -5,21 +5,5 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE # Index0 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # Index1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 62ee365ef4..b385ad7c8d 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -66,7 +66,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index a1521d4234..a5e9dbab3d 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 @@ -14,17 +12,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 8eee5cbf7b..9491c25d99 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 3482e95ede..06c61f21e7 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -39,7 +39,6 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 0 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 - /* SD CARD gpio */ #define SDCARD_CD 81 diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index b3651eac90..91c0d97a40 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -5,8 +5,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE @@ -19,17 +17,3 @@ SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index f327e159dd..c1b43b88ec 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl index bbdcfc7d34..b261570ca8 100644 --- a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 45 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "R4303_CPU" #define DPTF_TSR1_PASSIVE 49 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index ff707b4dee..14db7537eb 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 @@ -16,17 +14,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 1f121048f5..4e4b01a5c1 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl index ca3415182e..5bf3322906 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 55 #define DPTF_TSR0_CRITICAL 68 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 55 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 53 #define DPTF_TSR2_CRITICAL 66 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index b45a2b229e..8b4a77645b 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -6,24 +6,8 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index ecc5c54d95..ece6c8058d 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl index 554e129905..df393b95e4 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Charger" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 48 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/relm/Makefile.inc b/src/mainboard/google/cyan/variants/relm/Makefile.inc index 3de47937e6..47e32bb32b 100644 --- a/src/mainboard/google/cyan/variants/relm/Makefile.inc +++ b/src/mainboard/google/cyan/variants/relm/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF @@ -15,17 +13,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index fca36bbaef..5a0c13a6a3 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl index 554e129905..df393b95e4 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Charger" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 48 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/setzer/Makefile.inc b/src/mainboard/google/cyan/variants/setzer/Makefile.inc index d99926b203..1735907d8e 100644 --- a/src/mainboard/google/cyan/variants/setzer/Makefile.inc +++ b/src/mainboard/google/cyan/variants/setzer/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD @@ -18,17 +16,3 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 7938855d75..cdf57a447b 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl index dbc3d42f31..bebc11dfcc 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 58 #define DPTF_TSR0_CRITICAL 66 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 57 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 59 #define DPTF_TSR2_CRITICAL 66 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc index af07a93bc7..6358081d66 100644 --- a/src/mainboard/google/cyan/variants/terra/Makefile.inc +++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc @@ -6,23 +6,7 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-GD-F-R SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF-107WT - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 4b970b2631..11071eb560 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/ultima/Makefile.inc b/src/mainboard/google/cyan/variants/ultima/Makefile.inc index 10500c43c2..7cb457ef6c 100644 --- a/src/mainboard/google/cyan/variants/ultima/Makefile.inc +++ b/src/mainboard/google/cyan/variants/ultima/Makefile.inc @@ -5,23 +5,7 @@ romstage-y += spd_util.c ramstage-y += gpio.c ramstage-y += ramstage.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCF SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 741b73e986..cef45aa609 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl index 095a538d9e..40230f09e2 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 60 #define DPTF_TSR0_CRITICAL 70 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_DDR" #define DPTF_TSR1_PASSIVE 55 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 42 #define DPTF_TSR2_CRITICAL 70 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc index aa1621addb..b6ff0d058f 100644 --- a/src/mainboard/google/cyan/variants/wizpig/Makefile.inc +++ b/src/mainboard/google/cyan/variants/wizpig/Makefile.inc @@ -4,24 +4,8 @@ romstage-y += spd_util.c ramstage-y += gpio.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_2GiB_dimm_K4E8E304EE-EGCE SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-JD-F SPD_SOURCES += samsung_2GiB_dimm_K4E8E324EB-EGCF SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 300f7d6acc..6e993305bb 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -130,7 +129,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -200,7 +198,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -230,7 +227,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl index 273020cd34..c5914976b4 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 75 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index a5b7d3c147..5dc9c3efb3 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -5,7 +5,6 @@ #include #include #include -#include const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e8b7cf5f88..2892dd16f0 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -11,6 +12,8 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,6 +23,10 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU + select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_DEDEDE + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU if BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -30,6 +37,8 @@ config BASEBOARD_DEDEDE_LAPTOP config CHROMEOS bool default y + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -40,6 +49,14 @@ config CHROMEOS select VBOOT_EARLY_EC_SYNC select VBOOT_LID_SWITCH +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DEVICETREE string default "variants/baseboard/devicetree.cb" @@ -53,8 +70,8 @@ config DRIVER_TPM_SPI_BUS config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 config MAINBOARD_DIR string @@ -71,9 +88,11 @@ config MAINBOARD_PART_NUMBER default "Dedede" if BOARD_GOOGLE_DEDEDE default "Drawcia" if BOARD_GOOGLE_DRAWCIA default "Drawcia" if BOARD_GOOGLE_DRAWCIA_LEGACY + default "Madoo" if BOARD_GOOGLE_MADOO default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE + default "Magolor" if BOARD_GOOGLE_MAGOLOR config MAX_CPUS int @@ -98,14 +117,10 @@ config VARIANT_DIR default "dedede" if BOARD_GOOGLE_DEDEDE default "drawcia" if BOARD_GOOGLE_DRAWCIA default "drawcia" if BOARD_GOOGLE_DRAWCIA_LEGACY + default "madoo" if BOARD_GOOGLE_MADOO default "waddledoo" if BOARD_GOOGLE_WADDLEDOO default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE - -config VARIANT_HAS_CAMERA_ACPI - bool - default n - help - Select this option to enable camera ACPI support on the variant. + default "magolor" if BOARD_GOOGLE_MAGOLOR endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 071ae5b64b..563a309c45 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -20,6 +20,7 @@ config BOARD_GOOGLE_DRAWCIA select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" @@ -28,6 +29,13 @@ config BOARD_GOOGLE_DRAWCIA_LEGACY select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A +config BOARD_GOOGLE_MADOO + bool "-> Madoo" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + config BOARD_GOOGLE_WADDLEDOO bool "Waddledoo" select BOARD_GOOGLE_BASEBOARD_DEDEDE @@ -35,7 +43,8 @@ config BOARD_GOOGLE_WADDLEDOO select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" @@ -47,3 +56,10 @@ config BOARD_GOOGLE_WHEELIE bool "Wheelie" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_MAGOLOR + bool "-> Magolor" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl index e7a8bf4ee5..0fa27da0a5 100644 --- a/src/mainboard/google/dedede/acpi/mainboard.asl +++ b/src/mainboard/google/dedede/acpi/mainboard.asl @@ -1,8 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 933ca1a503..bbdbd3bc00 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -37,7 +37,6 @@ DefinitionBlock( #include #endif - /* Include Low power idle table for a short term workaround to enable S0ix. Once cr50 pulse width is fixed, this can be removed. */ #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f400..45b25809cd 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,9 +4,31 @@ #include #include #include +#include #include +#include +#include #include +static void mainboard_update_soc_chip_config(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + int ret; + + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + __weak void variant_isst_override(void) { /* @@ -31,6 +53,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + mainboard_update_soc_chip_config(); } static void mainboard_dev_init(struct device *dev) diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c index af79c809a8..02ebfac426 100644 --- a/src/mainboard/google/dedede/romstage.c +++ b/src/mainboard/google/dedede/romstage.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -21,19 +21,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } - -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - return false; - } - - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store); - return true; -} diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 0254810ef3..20f0207edb 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -36,3 +36,8 @@ void elog_gsmi_cb_mainboard_log_wake_source(void) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); } + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index d2bed28dbc..ebc11e5d8a 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -1,19 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/lp4x/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd -endif +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/$(f)) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e126129f11..2b7a5139c6 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,3 +1,10 @@ +fw_config + field TABLETMODE 10 + option TABLETMODE_DISABLED 0 + option TABLETMODE_ENABLED 1 + end +end + chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end @@ -16,9 +23,9 @@ chip soc/intel/jasperlake # - GPP_D0 - WWAN_HOST_WAKE # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_C" - register "pmc_gpe0_dw2" = "GPP_D" + register "pmc_gpe0_dw0" = "PMC_GPP_B" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -32,16 +39,12 @@ chip soc/intel/jasperlake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -126,14 +129,6 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" @@ -152,9 +147,6 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - # Enable processor thermal control - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C # chipset_lockdown configuration @@ -163,31 +155,73 @@ chip soc/intel/jasperlake # register "common_soc_config." = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR config settings + # Imon Slope correction specified in 1/100 increment values. Range is 0-200. + # Eg: 125 = 1.25 + register "ImonSlope" = "100" + + # Imon offset correction. Value is a 2's complement signed integer. + # Units 1/1000, Range 0-63999. + # For an offset = 12.580, use 12580 + register "ImonOffset" = "0" + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on + # Default DPTF Policy for all Dedede boards if not overridden chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 10000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000) + }" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 99, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + }" - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 6000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 6000, - .max_power = 20000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 1000,}" + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 1284bc5e34..1d8d21d788 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { /* B2 : PROCHOT_ODL */ PAD_NC(GPP_B2, NONE), /* B3 : TRACKPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, LEVEL, INVERT), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), /* B5 : PCIE_CLKREQ0_N */ @@ -224,9 +224,9 @@ static const struct pad_config gpio_table[] = { /* E16 : GPP_E16/DDI1_DDC_SDA */ PAD_NC(GPP_E16, NONE), /* E17 : HDMI_DDC_SCL */ - PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : HDMI_DDC_SDA */ - PAD_NC(GPP_E18, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ @@ -238,7 +238,6 @@ static const struct pad_config gpio_table[] = { /* E23 : CNV_RGI_RSP */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), - /* F4 : CNV_RF_RST_L */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F7 : EMMC_CMD */ @@ -341,7 +340,6 @@ static const struct pad_config gpio_table[] = { /* R7 : I2S_SPK_AUDIO */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1), - /* S0 : RAM_STRAP_4 */ PAD_CFG_GPI(GPP_S0, NONE, DEEP), /* S1 : RSVD_STRAP */ @@ -359,7 +357,6 @@ static const struct pad_config gpio_table[] = { /* S7 : DMIC0_DATA */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - /* GPD0 : AP_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 : GPP_GPD1/ACPRESENT */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl deleted file mode 100644 index aca7d04cb5..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam0.asl +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C3) -{ - Name (STA0, Zero) - - /* Method to turn off Power Rails */ - Method (POFF, 0) - { - /* Disable PP1200 lane */ - CTXS(GPP_D14) - /* Disable PP2800 lane */ - CTXS(GPP_D13) - } - - Method (PON, 0) - { - /* Enable PP2800 lane */ - STXS(GPP_D13) - /* Enable PP1200 lane */ - STXS(GPP_D14) - } - - PowerResource (FCPR, 0x00, 0x0000) - { - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - MCON(0, 1) /* Clock 0, 19.2MHz */ - IF(!STA1) - { - /* Other sensor is OFF, so turn on power signals. */ - PON() - } - /* Assert Reset */ - CTXS(GPP_D15) - Sleep(5) /* 5 us */ - /* Deassert Reset */ - STXS(GPP_D15) - Sleep(5) /* 5 us */ - STA0 = 1 - } - - Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ - { - MCOF(0) /* Clock 0 */ - /* Assert Reset */ - CTXS(GPP_D15) - IF(!STA1) - { - /* Other sensor is OFF, so turn off power signals. */ - POFF() - } - STA0 = 0 - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA0) - } - } - - Device (CAM0) - { - Name (_HID, "OVTI9734") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x01) - { - One - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 180000000 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - Zero, - Zero - } - } - } - }) - } -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl deleted file mode 100644 index ef2a2a0f2c..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ /dev/null @@ -1,308 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C3) -{ - Name (STA1, Zero) - - PowerResource (RCPR, 0x00, 0x0000) - { - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - MCON(1, 1) /* Clock 1, 19.2MHz */ - /* Check if another sensor is ON */ - IF(!STA0) - { - /* Other sensor is OFF, so turn on power signals. */ - PON() - } - /* Assert Reset */ - CTXS(GPP_D12) - Sleep(5) /* 5 us */ - /* DeAssert Reset */ - STXS(GPP_D12) - Sleep(5) /* 5 us */ - STA1 = 1 - } - - Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ - { - MCOF(1) /* Clock 1 */ - /* Assert Reset */ - CTXS(GPP_D12) - IF(!STA0) - { - /* Other sensor is OFF, so turn off power signals. */ - POFF() - } - STA1 = 0 - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA1) - } - } - - Device(CAM1) - { - Name (_HID, "OVTI8856") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x04) - { - One, - 0x02, - 0x03, - 0x04, - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x02) - { - 0x15752A00, - 0xABA9500 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } - - Device(VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - - Name (_UID, 0x00) /* _UID: Unique ID */ - - Name (_DDN, "DW9768 VCM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package (0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9768" - } - } - }) - } - - Device (NVM0) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - - Name (_UID, 0x01) /* _UID: Unique ID */ - - Name (_DDN, "AT24 EEPROM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status*/ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package (0x05) - { - Package (0x02) - { - "size", - 0x2800 - }, - - Package (0x02) - { - "pagesize", - One - }, - - Package (0x02) - { - "read-only", - One - }, - - Package (0x02) - { - "address-width", - 0x0E - }, - - Package (0x02) - { - "compatible", - "atmel,24c1024" - } - } - }) - } -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl deleted file mode 100644 index 51b4ebc046..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/camera.asl +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam0.asl" -#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl deleted file mode 100644 index 81cbf61b8c..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (_SB.PCI0.IPU0) -{ - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x01) - { - One, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C3.CAM0, - Zero, - Zero - } - } - } - }) - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x04) - { - One, - 0x02, - 0x03, - 0x04, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C3.CAM1, - Zero, - Zero - } - } - } - }) -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl deleted file mode 100644 index 34c3d4b906..0000000000 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) /* _ADR: Address */ - - Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ - } -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x02) - { - Package (0x02) - { - "port0", - "PRT0" - }, - - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index 1074f15dd3..d9b031eb40 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_EC_H__ #define __BASEBOARD_EC_H__ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h index e99aa42011..855ab6d869 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 1f4044366d..bd94ef4df3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c index dc43ea59b5..aa52636233 100644 --- a/src/mainboard/google/dedede/variants/baseboard/memory.c +++ b/src/mainboard/google/dedede/variants/baseboard/memory.c @@ -36,12 +36,6 @@ static const struct mb_cfg baseboard_memcfg_cfg = { .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6}, .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6}, - /* WaddleDoo uses 100, 100 and 100 rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* WaddleDoo Rcomp target values */ - .rcomp_targets = {80, 40, 40, 40, 30}, - /* Disable Early Command Training */ .ect = 1, diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc new file mode 100644 index 0000000000..a3527099b9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c new file mode 100644 index 0000000000..05a567f65c --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* D23 : AP_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_INT(GPP_E11, NONE, PLTRST, EDGE_BOTH), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h b/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/boten/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc b/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc index 2c50412765..d0960c7768 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 1e75864922..2ba6d9d665 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -11,7 +11,6 @@ chip soc/intel/jasperlake #| I2C0 | Trackpad | #| I2C1 | Digitizer | #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -28,12 +27,129 @@ chip soc/intel/jasperlake .i2c[2] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" - device domain 0 on end + + # USB Port Configuration + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + end end diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc new file mode 100644 index 0000000000..24c75d1d9a --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h index 08870e0627..27c930d4f2 100644 --- a/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/drawcia/include/variant/ec.h @@ -5,4 +5,7 @@ #include +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index 573213b877..f6282bf04c 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index a825c3ae8c..856d016914 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -1,2 +1,4 @@ DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt index 20887c1b63..26c06b6f40 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_list_variant.txt @@ -1 +1,3 @@ MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index bc10e1ff2b..044ff08c2f 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -24,22 +24,101 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "20" # TCC of 85C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + # Default DPTF Policy for all drawcia boards if not overridden + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 119, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -74,6 +153,50 @@ chip soc/intel/jasperlake register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end end # I2C 2 device pci 19.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c new file mode 100644 index 0000000000..88e9de7eb9 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + filename = "wifi_sar-drawcia.hex"; + + return filename; +} diff --git a/src/mainboard/google/dedede/variants/madoo/Makefile.inc b/src/mainboard/google/dedede/variants/madoo/Makefile.inc new file mode 100644 index 0000000000..04eb9a4877 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/madoo/gpio.c b/src/mainboard/google/dedede/variants/madoo/gpio.c new file mode 100644 index 0000000000..314d39eb06 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/gpio.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* E0 : CLK_24M_UCAM */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h new file mode 100644 index 0000000000..d6c3859c91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc new file mode 100644 index 0000000000..693240ebaf --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2a158ee9ec --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt new file mode 100644 index 0000000000..2b339b6e07 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +H9HCNNNBKMMLXR-NEE +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb new file mode 100644 index 0000000000..257f91722e --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -0,0 +1,131 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 270, + .fall_time_ns = 270, + .data_hold_time_ns = 350, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 200, + .fall_time_ns = 200, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + }, + }, + }" + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/madoo/variant.c b/src/mainboard/google/dedede/variants/madoo/variant.c new file mode 100644 index 0000000000..b8c3654ab0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/madoo/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + filename = "wifi_sar-madoo.hex"; + + return filename; +} diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h b/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc new file mode 100644 index 0000000000..285df73c2e --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt new file mode 100644 index 0000000000..100c322e91 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt new file mode 100644 index 0000000000..f05a5af118 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb new file mode 100644 index 0000000000..f41e9fab6b --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -0,0 +1,294 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | TBD | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #| I2C5 | TBD | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + end # I2C 2 + device pci 15.3 on # I2C 3 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + end +end diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc index 37f25e0769..c6683e2e94 100644 --- a/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E -SPD_SOURCES += spd-7.hex # ID = 1(0b0001) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-7.hex # ID = 1(0b0001) Parts = NT6AP256T32AV-J2 diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index f070fa1b67..22a08a060e 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -21,22 +21,41 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" device domain 0 on + device pci 05.0 on end # IPU - MIPI Camera device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -84,6 +103,21 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x00" device i2c 5c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end end # I2C 2 device pci 19.0 on chip drivers/i2c/generic @@ -110,6 +144,12 @@ chip soc/intel/jasperlake device i2c 29 on end end end + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl deleted file mode 100644 index 318b0dea04..0000000000 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/camera.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc index 8552e95b45..be4a11895b 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-7.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 -SPD_SOURCES += spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-7.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:E diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 2936cddf6b..969bebba53 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -50,6 +50,21 @@ chip soc/intel/jasperlake }, }" device domain 0 on + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{1,4}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -91,9 +106,9 @@ chip soc/intel/jasperlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "100" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "100" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "generic.enable_delay_ms" = "7" @@ -122,6 +137,115 @@ chip soc/intel/jasperlake device i2c 10 on end end end # I2C 2 + device pci 15.3 on #I2C #3 CAM0 CAM1 and VCM0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 58 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI9734"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 9734 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "180000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D15" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end device pci 1c.7 on chip drivers/intel/wifi register "wake" = "GPE0_DW2_03" @@ -147,12 +271,12 @@ chip soc/intel/jasperlake device i2c 1a on end end end #I2C 4 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98360A"" + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" - device generic 0 on end - end - end # Intel HDA + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc index 2c50412765..d0960c7768 100644 --- a/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index fac58bdf42..8666ec7f7e 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index faca003ab7..e1cdb96959 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -7,7 +7,6 @@ #include #include - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 1af83259be..52e689c177 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -32,23 +32,19 @@ chip soc/intel/tigerlake register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" - register "SmbusEnable" = "1" # TODO: the lengths are all MID for right now. register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right) register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left) - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN) register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN # PCIe root port 7 (Card Reader), clock 4 diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h index b1abeb9eba..9ef6624cd2 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index ce79ebce3b..aadbbec56b 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 5bbcea604a..f5e5fb6b6d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/deltaur/variants/baseboard/sku.c b/src/mainboard/google/deltaur/variants/baseboard/sku.c index fb19e3c67f..3cd279ec10 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/sku.c +++ b/src/mainboard/google/deltaur/variants/baseboard/sku.c @@ -6,12 +6,12 @@ #include #include -static const uint32_t get_sku_index(void) +static uint32_t get_sku_index(void) { return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1)); } -const uint32_t sku_id(void) +uint32_t sku_id(void) { return skus[get_sku_index()].id; } diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h index e9dfb7431f..56873c02bd 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h index ac2ff9b622..60eb5aa447 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h index 46756990c4..d1c72ef360 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/variant.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h index e9dfb7431f..56873c02bd 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h index ac2ff9b622..60eb5aa447 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h index 50f5380046..27d8df849c 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h +++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/variant.h @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_H #define VARIANT_H diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index df67a8d18b..d535d141e1 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -16,12 +16,13 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ef2a94e1bd..2fbff26c00 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -12,7 +12,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -40,7 +40,7 @@ DefinitionBlock( #include /* Low power idle table */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc index 99aea9c827..125413a1f3 100644 --- a/src/mainboard/google/drallion/spd/Makefile.inc +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -1,21 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - ifeq ($(SPD_SOURCES),) SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) endif - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e9daf0d00d..ed7eb95d0d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -153,9 +152,6 @@ chip soc/intel/cannonlake register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port @@ -163,7 +159,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -418,7 +413,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -445,12 +440,14 @@ chip soc/intel/cannonlake device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b383ba..f7e82959ce 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE + select HAVE_SPD_IN_CBFS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 3b1f22c8c1..d9415212d7 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,24 +36,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -62,15 +53,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -171,12 +153,9 @@ chip soc/intel/skylake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -262,6 +241,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -311,6 +291,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index b73dcb5129..0009d9540a 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/eve/spd/Makefile.inc b/src/mainboard/google/eve/spd/Makefile.inc index 767281504d..8c4f005465 100644 --- a/src/mainboard/google/eve/spd/Makefile.inc +++ b/src/mainboard/google/eve/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = empty # 0b0000 SPD_SOURCES += samsung_dimm_K4E8E324EB # 0b0001 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b0010 @@ -11,17 +9,3 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB # 0b0011 SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b0100 SPD_SOURCES += samsung_dimm_K4EBE304EB # 0b0101 SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0110 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 90a3dc4e62..48d04e791b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -22,7 +22,6 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD select RT8168_SUPPORT_LEGACY_VPD_MAC select RT8168_SET_LED_MODE diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 83c77183a3..965770c583 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index b8455fe9e9..bc29dc63af 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,26 +65,17 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -98,15 +89,6 @@ chip soc/intel/skylake # send VR mailbox command for IA/GT/SA rails register "IslVrCmd" = "2" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -266,7 +248,6 @@ chip soc/intel/skylake register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear @@ -337,6 +318,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -392,6 +374,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 on end # I2C #2 diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 432a180362..d4be35fed3 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -14,15 +14,13 @@ static const struct pad_config gpio_table[] = { /* ESPI_IO3 */ /* ESPI_CS# */ /* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, EDGE), /* SD_CDZ */ /* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ /* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ /* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, - DEEP), /* eSPI mode */ +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), @@ -39,30 +37,20 @@ static const struct pad_config gpio_table[] = { /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ /* CPU_GP2 */ PAD_CFG_NC(GPP_B3), /* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, - NF1), /* CLK_PCIE_LAN_REQ# */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, - NF1), /* PCIE_CLKREQ_SSD# */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU# */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, - NF1), /* PCIE_CLKREQ_POE# */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, - NF1), /* PCIE_CLKREQ_TPU1# */ -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, - NF1), /* PCIE_CLKREQ_WLAN# */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* PCIE_CLKREQ_POE# */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU1# */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), @@ -75,21 +63,16 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_NC(GPP_C3), /* SML0DATA */ PAD_CFG_NC(GPP_C4), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, - DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ /* UART0_RXD */ PAD_CFG_NC(GPP_C8), /* UART0_TXD */ PAD_CFG_NC(GPP_C9), /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), -/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, - DEEP), /* SKU_ID0 */ -/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, - DEEP), /* SKU_ID1 */ -/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, - DEEP), /* SKU_ID2 */ -/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, - DEEP), /* SKU_ID3 */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */ @@ -97,8 +80,7 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, - DEEP), /* SCREW_SPI_WP_STATUS */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ /* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ /* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ @@ -109,14 +91,10 @@ static const struct pad_config gpio_table[] = { /* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), /* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), /* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ -/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, - DEEP), /* OEM_ID1 */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, - DEEP), /* OEM_ID2 */ -/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, - DEEP), /* OEM_ID3 */ +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ /* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), /* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), @@ -129,10 +107,8 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, - NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, NONE), /* TPU_RST_PIN40 */ @@ -144,14 +120,10 @@ static const struct pad_config gpio_table[] = { /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, - NF1), /* Rear Dual-Stack USB Ports */ -/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, - NF1), /* Rear Single USB Port */ -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, - NF1), /* DDI1_HDMI_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, - NF1), /* DDI2_HDMI_HPD */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ /* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), @@ -172,10 +144,8 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ /* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ /* EMMC_CMD */ PAD_CFG_NC(GPP_F12), /* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), /* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 1d837934ac..3ca1648e0f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -49,15 +49,12 @@ chip soc/intel/skylake register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # None - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # None register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 90d8c6578f..040b662f24 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -29,7 +29,6 @@ #endif - #if IPQ40XX_I2C1_PINGROUP_1 #define SCL_GPIO_I2C1 34 diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index d1cf1b3f15..9bdd307bc1 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -4,7 +4,6 @@ #include #include - #define TPM_RESET_GPIO 19 static void ipq_setup_tpm(void) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 9790552229..50e56ce9e7 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index 5162e48784..5b1c383ce7 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -10,7 +10,6 @@ config BOARD_GOOGLE_ASUKA config BOARD_GOOGLE_CAROLINE bool "-> Caroline (Samsung Chromebook Pro)" select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_INTEL_WIFI select DSAR_ENABLE select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS select SAR_ENABLE diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index f7be80d460..98b678a5cf 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -38,24 +38,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -64,15 +55,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# @@ -117,9 +99,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 040c960ea0..707c84cec8 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index b065cdd57e..9a968b16d4 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -10,7 +10,6 @@ #include "spd/spd_util.h" #include "spd/spd.h" - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; diff --git a/src/mainboard/google/glados/variants/asuka/Makefile.inc b/src/mainboard/google/glados/variants/asuka/Makefile.inc index ee3447823f..d1b4d16ba0 100644 --- a/src/mainboard/google/glados/variants/asuka/Makefile.inc +++ b/src/mainboard/google/glados/variants/asuka/Makefile.inc @@ -3,25 +3,9 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Single Channel 2GB SPD_SOURCES += hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0001 Dual Channel 4GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0010 Single Channel 2GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0011 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0100 Single Channel 2GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0101 Dual Channel 4GB - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index a2545fcf08..6a942ee456 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -4,23 +4,7 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index SPD_SOURCES = samsung_dimm_K4E8E324EB-EGCF # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0001 SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0010 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index 7bee2e2a48..967a95a2c1 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms @@ -15,14 +13,10 @@ chip soc/intel/skylake register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # PL2 override 15W register "power_limits_config" = "{ diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index 2f19b3fbd2..88e450ed6f 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = micron_4GiB_dimm_MT52L256M32D1PF # 0b0000 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 @@ -13,17 +11,3 @@ SPD_SOURCES += micron_8GiB_dimm_MT52L512M32D2PF # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 SPD_SOURCES += micron_16GiB_dimm_MT52L1G32D4PG # 0b0100 SPD_SOURCES += hynix_dimm_H9CCNNNCLTMLAR # 0b0101 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index 9aeb78afa7..e77a2b4755 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -1,21 +1,15 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board) register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1 register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex) - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 # PL2 override 15W register "power_limits_config" = "{ diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index b820684b7c..53861e9839 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -4,8 +4,6 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCF # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 @@ -18,17 +16,3 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0111 SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1000 SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR # 0b1001 SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR # 0b1010 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index 3cf91e8f03..8858453cfc 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -4,24 +4,8 @@ romstage-y += variant.c ramstage-y += variant.c smm-y += variant.c -SPD_BIN = $(obj)/spd.bin - # SPD data by index. No method for board identification yet SPD_SOURCES = empty # 0b0000 SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR # 0b0010 SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index c510e920a0..3a0fdd4418 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/lars/Makefile.inc b/src/mainboard/google/glados/variants/lars/Makefile.inc index e7ab2511f2..f295a360c2 100644 --- a/src/mainboard/google/glados/variants/lars/Makefile.inc +++ b/src/mainboard/google/glados/variants/lars/Makefile.inc @@ -3,8 +3,6 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 Single Channel 2GB SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 Dual Channel 8GB SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 Dual Channel 4GB @@ -21,17 +19,3 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b1100 Single Channel SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR # 0b1101 Dual Channel 8GB SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc index 019820a4b2..4de16c951a 100644 --- a/src/mainboard/google/glados/variants/sentry/Makefile.inc +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -3,8 +3,6 @@ romstage-y += variant.c ramstage-y += variant.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0001 Dual Channel 4GB SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB @@ -21,18 +19,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb index 08d3dd3aba..36575f8856 100644 --- a/src/mainboard/google/glados/variants/sentry/overridetree.cb +++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb @@ -1,7 +1,5 @@ chip soc/intel/skylake - register "ScsSdCardEnabled" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3f0e83b426..257ad77a42 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,8 @@ config BOARD_GOOGLE_BASEBOARD_PUFF select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_INTEL_DPTF + select DPTF_USE_EISA_HID config BOARD_GOOGLE_HATCH_COMMON def_bool n @@ -28,6 +30,7 @@ config BOARD_GOOGLE_HATCH_COMMON select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -36,13 +39,15 @@ config BOARD_GOOGLE_HATCH_COMMON select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_DTT if BOARD_GOOGLE_HATCH_COMMON config CHROMEOS bool default y + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -51,6 +56,7 @@ config CHROMEOS select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" @@ -76,6 +82,7 @@ config DIMM_SPD_SIZE config ROMSTAGE_SPD_CBFS bool default y if !ROMSTAGE_SPD_SMBUS + select HAVE_SPD_IN_CBFS config ROMSTAGE_SPD_SMBUS bool @@ -134,8 +141,8 @@ config MAINBOARD_PART_NUMBER default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE - default "Sushi" if BOARD_GOOGLE_SUSHI default "Wyvern" if BOARD_GOOGLE_WYVERN + default "Dooly" if BOARD_GOOGLE_DOOLY config OVERRIDE_DEVICETREE string @@ -167,8 +174,8 @@ config VARIANT_DIR default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE - default "sushi" if BOARD_GOOGLE_SUSHI default "wyvern" if BOARD_GOOGLE_WYVERN + default "dooly" if BOARD_GOOGLE_DOOLY config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 3f803c5efc..69bb28ac00 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -90,10 +90,10 @@ config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH -config BOARD_GOOGLE_SUSHI - bool "-> Sushi" - select BOARD_GOOGLE_BASEBOARD_HATCH - config BOARD_GOOGLE_WYVERN bool "-> Wyvern" select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + bool "-> Dooly" + select BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index ffb7cfef66..3ca98ab028 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -37,7 +37,7 @@ DefinitionBlock( #include /* Low power idle table */ - #include + #include /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) @@ -48,6 +48,7 @@ DefinitionBlock( #include } +#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) /* Dynamic Platform Thermal Framework */ Scope (\_SB) { @@ -56,4 +57,5 @@ DefinitionBlock( /* Include common dptf ASL files */ #include } +#endif } diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a9a65e90af..f3c38bbf4f 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c @@ -56,29 +56,3 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } - -void mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - static enum { - PART_NUM_NOT_READ, - PART_NUM_AVAILABLE, - PART_NUM_NOT_IN_CBI, - } part_num_state = PART_NUM_NOT_READ; - - if (part_num_state == PART_NUM_NOT_READ) { - if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "No DRAM part number in CBI!\n"); - part_num_state = PART_NUM_NOT_IN_CBI; - } else { - part_num_state = PART_NUM_AVAILABLE; - } - } - - if (part_num_state == PART_NUM_NOT_IN_CBI) - return; - - *part_num = &part_num_store[0]; - *len = strlen(part_num_store) + 1; -} diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc deleted file mode 100644 index dc1c9978a0..0000000000 --- a/src/mainboard/google/hatch/spd/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd -endif diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 0e3972813a..2d60271d01 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -22,20 +22,12 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Unused - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # WWAN register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Unused - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cb314ab6a2..a4e07e9556 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -29,8 +29,6 @@ chip soc/intel/cannonlake register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable heci communication - register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix @@ -159,11 +157,8 @@ chip soc/intel/cannonlake register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 @@ -171,7 +166,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" @@ -312,7 +306,7 @@ chip soc/intel/cannonlake device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -331,7 +325,9 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) + device pci 1d.0 on # PCI Express Port 9 (X4 NVME) + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -341,6 +337,7 @@ chip soc/intel/cannonlake register "wake" = "GPE0_DW1_01" device pci 00.0 on end end + register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl deleted file mode 100644 index 86bd8fc866..0000000000 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 85 -#define DPTF_CPU_ACTIVE_AC2 80 -#define DPTF_CPU_ACTIVE_AC3 75 -#define DPTF_CPU_ACTIVE_AC4 70 -#define DPTF_CPU_ACTIVE_AC5 65 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 15000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 64000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 537e3df102..3b247e9fad 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -35,10 +35,10 @@ static void wait_for_hpd(gpio_t gpio, long timeout) } /* - * For type-C chargers, set PL2 to 90% of max power to account for + * For type-C chargers, set PL2 to 97% of max power to account for * cable loss and FET Rdson loss in the path from the source. */ -#define SET_PSYSPL2(w) (9 * (w) / 10) +#define SET_PSYSPL2(w) (97 * (w) / 100) #define PUFF_U22_PL2 (35) #define PUFF_U62_U42_PL2 (51) #define PUFF_CELERON_PENTIUM_PSYSPL2 (65) @@ -65,7 +65,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout) * +-------------+-----------------+---------+---------+-------+ * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | + * | n | min(0.97n, PL2) | 0.97n | 0.97n | 0.97n | * +-------------+-----+-----------+---------+---------+-------+ */ diff --git a/src/mainboard/google/hatch/variants/dooly/Makefile.inc b/src/mainboard/google/hatch/variants/dooly/Makefile.inc new file mode 100644 index 0000000000..3b5b7d000d --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c new file mode 100644 index 0000000000..4406c060eb --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A17 : SD_VDD1_PWR_EN */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 */ + PAD_NC(GPP_A18, NONE), + /* A19 : GPP_A19 */ + PAD_NC(GPP_A19, NONE), + /* A20 : TOUCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A21 : FPMCU_PCH_BOOT0 */ + PAD_NC(GPP_A21, NONE), + /* A22 : FPMCU_PCH_INT_L */ + PAD_NC(GPP_A22, NONE), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : GPP_C3 */ + PAD_NC(GPP_C3, NONE), + /* C4 : GPP_C4 */ + PAD_NC(GPP_C4, NONE), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_NC(GPP_C7, NONE), + /* C11 : GPP_C11 */ + PAD_NC(GPP_C11, NONE), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C18 : GPP_C18 */ + PAD_NC(GPP_C18, NONE), + /* C19 : GPP_C19 */ + PAD_NC(GPP_C19, NONE), + + /* D16 : DMIC_ON_OFF MIC_SWITCH_L */ + PAD_CFG_GPI(GPP_D16, NONE, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + + /* F0 : GPP_F0 */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 */ + PAD_NC(GPP_F1, NONE), + /* F8 : GPP_F8 */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 */ + PAD_NC(GPP_F9, NONE), + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + + /* H3 : SPK_AMP_ON */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4: LVDS_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: LVDS_SDL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C_TOUCH_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TOUCH_SDL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h similarity index 78% rename from src/mainboard/google/hatch/variants/sushi/include/variant/ec.h rename to src/mainboard/google/hatch/variants/dooly/include/variant/ec.h index ce6fbfe1a4..59fb3783c5 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -3,6 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include +#include #endif diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h new file mode 100644 index 0000000000..79a141008f --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb new file mode 100644 index 0000000000..ee91dd3653 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -0,0 +1,413 @@ +chip soc/intel/cannonlake + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 0 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(3)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2)" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | ALC 1015 | + #| I2C2 | Lvds | + #| I2C3 | Touchscreen | + #| I2C4 | RT5682 | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.3 on end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + chip drivers/usb/acpi + device usb 3.5 off end + end + end + end + end # USB xHCI + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end # I2C #0 ALC1015 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2 LVDS + device pci 15.3 on end # I2C #3 Touchscreen + device pci 16.0 on end # Management Engine Interface 1 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end + device pci 1e.3 off end # GSPI #1 + end + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + +end diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 2bfcc26c89..c5e2aeb2bd 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -29,16 +29,16 @@ chip soc/intel/cannonlake # Intel Common SoC Config #+-------------------+---------------------------+ - #| Field | Value | + #| Field | Value | #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | FP MCU | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -47,18 +47,18 @@ chip soc/intel/cannonlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 50, - .fall_time_ns = 15, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 25, + .rise_time_ns = 60, + .fall_time_ns = 25, }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, + .rise_time_ns = 60, + .fall_time_ns = 60, }, }" @@ -169,6 +169,25 @@ chip soc/intel/cannonlake device spi 1 on end end # FPMCU end # GSPI #1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "5" + device generic 0 on + chip drivers/i2c/generic + register "hid" = ""ACPI_DT_NAMESPACE_HID"" + register "name" = ""SBS0"" + register "uid" = "1" + register "compat_string" = ""sbs,sbs-battery"" + device i2c 0b on end + end + end + end + end + end + end # eSPI Interface device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl deleted file mode 100644 index 66940633a4..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index 2f2b643951..25778f92cb 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -62,9 +66,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -268,6 +269,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(61, 80), + TEMP_PCT(57, 70), + TEMP_PCT(53, 60), + TEMP_PCT(49, 50), + TEMP_PCT(45, 40), + TEMP_PCT(41, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -369,6 +433,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -395,8 +460,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl deleted file mode 100644 index 2a94f94a85..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 90 -#define DPTF_CPU_CRITICAL 100 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 60 -#define DPTF_TSR0_CRITICAL 85 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 85 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 10000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 8aff8d192d..1ac9414c6a 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -70,8 +74,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # PL2303 - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -275,6 +277,35 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 73, 60000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 10000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -376,6 +407,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -402,8 +434,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c index 38bca41bef..8282d1d398 100644 --- a/src/mainboard/google/hatch/variants/hatch/ramstage.c +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 34d235856e..4241a46640 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -36,7 +36,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 6accd0cc92..6fbe95058f 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -52,7 +52,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h index 7eb6f11c13..593f89e942 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/sku.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __JINLON_SKU_H__ #define __JINLON_SKU_H__ diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6fde60278a..564c18c76b 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,8 +1,5 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include #include #include diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index 01691ff16c..50c6d0b1b1 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -62,9 +66,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -268,6 +269,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(61, 80), + TEMP_PCT(57, 70), + TEMP_PCT(53, 60), + TEMP_PCT(49, 50), + TEMP_PCT(45, 40), + TEMP_PCT(41, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -369,6 +433,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -395,8 +460,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6720ffce79..1b91e8f5ed 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -27,21 +27,14 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c index 38bca41bef..8282d1d398 100644 --- a/src/mainboard/google/hatch/variants/mushu/ramstage.c +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 3c184eb139..d6be1fb6fc 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -27,21 +27,11 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c index d5a57af6e1..0e6eae644e 100644 --- a/src/mainboard/google/hatch/variants/nightfury/ramstage.c +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index cac7516000..cf6046224c 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,6 +1,8 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -46,7 +48,6 @@ chip soc/intel/cannonlake .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "{ .enable = 1, .ocpin = OC0, @@ -55,9 +56,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -72,7 +70,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ @@ -195,6 +192,69 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(52, 80), + TEMP_PCT(50, 70), + TEMP_PCT(48, 60), + TEMP_PCT(46, 50), + TEMP_PCT(44, 40), + TEMP_PCT(42, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -284,6 +344,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -310,8 +371,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 115a593c85..3675375b28 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl index 13e251f576..1a704b3b15 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #define DPTF_CPU_PASSIVE 0 #define DPTF_CPU_CRITICAL 105 diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h index 34986c650a..978c738782 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_EC_H #define VARIANT_EC_H diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h index 50b23f4fb5..a479a8c97e 100644 --- a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c index c68c40cb72..5b802033b6 100644 --- a/src/mainboard/google/hatch/variants/palkia/memory.c +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 73cf0f21b9..8cdb2a9fb3 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -29,7 +29,7 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| I2C0 | Trackpad | #| I2C1 | Touchscreen | - #| I2C2 | 2nd Touchscreen | + #| I2C2 | 2nd Touchscreen | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -37,7 +37,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, - .data_hold_time_ns = 330, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl deleted file mode 100644 index 66940633a4..0000000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index c78364dc9e..0d9bf7237e 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -65,9 +63,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -207,6 +202,71 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -308,6 +368,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -334,8 +395,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 329efa3b2a..536cd43de8 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -18,20 +18,12 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_EMPTY" register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/hatch/variants/sushi/Makefile.inc b/src/mainboard/google/hatch/variants/sushi/Makefile.inc deleted file mode 100644 index a115aa9c89..0000000000 --- a/src/mainboard/google/hatch/variants/sushi/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -SPD_SOURCES = diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl deleted file mode 100644 index fd3b5cfb4e..0000000000 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl deleted file mode 100644 index 66940633a4..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index c394977f6e..8ca9ce4683 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -1,10 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" + register "SataPortsEnable[0]" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -62,9 +62,6 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -202,6 +199,71 @@ chip soc/intel/cannonlake register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on @@ -303,6 +365,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -329,8 +392,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7065081317..4851bd7a68 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -56,4 +56,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config PCIEXP_AER + def_bool n + endif diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 19d0c48e07..c4707e0c00 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,15 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 1f03aed319..612901123e 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -11,7 +11,6 @@ #include #include "onboard.h" - void mainboard_pre_raminit(struct romstage_params *rp) { /* Fill out PEI DATA */ diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index a9ba0f5717..8e2639c2a4 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -14,7 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index d67cdec6fd..b33fb69e89 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -160,7 +160,6 @@ static void kahlee_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - static void mainboard_final(void *chip_info) { struct global_nvs *gnvs; diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index 72996cee68..4ed052cca4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -13,7 +13,6 @@ Name (PR0, Package() Package() { 0x0001FFFF, 2, INTE, 0 }, Package() { 0x0001FFFF, 3, INTF, 0 }, - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ Package() { 0x0002FFFF, 0, INTH, 0 }, Package() { 0x0002FFFF, 1, INTA, 0 }, @@ -74,7 +73,6 @@ Name (APR0, Package() Package() { 0x0011FFFF, 0, 0, 19 }, }) - /* GPP 0 */ Name (PS4, Package() { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index a3be62a3b8..a55e7a304d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 868253043a..95f0a8d642 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -78,7 +78,6 @@ void board_bh720(struct device *dev) write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc index 482fdec085..1ec3342891 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc index ca459d270a..4c1da68f3d 100644 --- a/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c index 3f20bc8881..df31c6f42f 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c @@ -90,7 +90,6 @@ void board_bh720(struct device *dev) BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; diff --git a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc index 2d3cd88581..e72c9e6d7a 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index 3f20bc8881..df31c6f42f 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -90,7 +90,6 @@ void board_bh720(struct device *dev) BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); } - const char *smbios_mainboard_manufacturer(void) { static char oem_bin_data[11]; diff --git a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc index 2d3cd88581..e72c9e6d7a 100644 --- a/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000 SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001 SPD_SOURCES += micron-MT40A512M16JY-083E-B # 0b0010 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index f3901470f3..4e308ef873 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -4,6 +4,13 @@ config BOARD_GOOGLE_KUKUI_COMMON def_bool n +config BOARD_GOOGLE_JACUZZI_COMMON + def_bool n + select BOARD_GOOGLE_KUKUI_COMMON + select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI + # All Jacuzzi followers are using ANX7625 except the reference board. + select DRIVER_ANALOGIX_ANX7625 if !BOARD_GOOGLE_JACUZZI + if BOARD_GOOGLE_KUKUI_COMMON config VBOOT @@ -28,8 +35,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_JACUZZI - select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_DAMU || BOARD_GOOGLE_KAPPA || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_WILLOW select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE config MAINBOARD_DIR @@ -50,6 +55,9 @@ config MAINBOARD_PART_NUMBER default "Cerise" if BOARD_GOOGLE_CERISE default "Stern" if BOARD_GOOGLE_STERN default "Willow" if BOARD_GOOGLE_WILLOW + default "Esche" if BOARD_GOOGLE_ESCHE + default "Burnet" if BOARD_GOOGLE_BURNET + default "Fennel" if BOARD_GOOGLE_FENNEL config DRIVER_TPM_SPI_BUS hex @@ -63,4 +71,9 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x2 +config BOARD_SDRAM_TABLE_OFFSET + hex + default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN + default 0x0 + endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 55e0101ca0..63cd3e74ac 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -20,30 +20,44 @@ config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON +comment "Jacuzzi" + config BOARD_GOOGLE_JACUZZI bool "-> Jacuzzi" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_JUNIPER bool "-> Juniper" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_KAPPA bool "-> Kappa" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_DAMU bool "-> Damu" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_CERISE bool "-> Cerise" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_STERN bool "-> Stern" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_WILLOW bool "-> Willow" - select BOARD_GOOGLE_KUKUI_COMMON + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_ESCHE + bool "-> Esche" + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_BURNET + bool "-> Burnet" + select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_FENNEL + bool "-> Fennel" + select BOARD_GOOGLE_JACUZZI_COMMON diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index c6865d1a67..548f36bc9d 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -110,7 +110,10 @@ uint32_t ram_code(void) { static uint32_t cached_ram_code = BOARD_ID_INIT; - if (cached_ram_code == BOARD_ID_INIT) + if (cached_ram_code == BOARD_ID_INIT) { cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + /* Model-specific offset - see sdram_configs.c for details. */ + cached_ram_code += CONFIG_BOARD_SDRAM_TABLE_OFFSET; + } return cached_ram_code; } diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 6622286135..268b7caf65 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -55,6 +56,13 @@ static void configure_audio(void) gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); } +static void configure_ec(void) +{ + /* EC may need SKU ID to identify if it is clamshell or convertible. */ + if (CONFIG(BOARD_GOOGLE_JACUZZI_COMMON)) + google_chromeec_set_sku_id(sku_id()); +} + /* Default implementation for boards without panels defined yet. */ struct panel_description __weak *get_panel_description(int panel_id) { @@ -191,6 +199,7 @@ static void mainboard_init(struct device *dev) configure_emmc(); configure_usb(); configure_audio(); + configure_ec(); if (spm_init()) printk(BIOS_ERR, "SPM initialization failed, suspend/resume may fail.\n"); diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index cae9edc041..cc41c86e63 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -9,7 +9,6 @@ #include "panel.h" - static void power_on_anx7625(void) { /* Disable backlight before turning on bridge */ diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 6b8015108b..f758e749ce 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -9,7 +9,6 @@ #include "panel.h" - static void power_on_ps8640(void) { /* Disable backlight before turning on bridge */ diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1a2127d735..b9c0d2c834 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -57,7 +57,7 @@ void platform_romstage_main(void) mt6358_init(); /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); - mt_pll_raise_ca53_freq(1989 * MHz); + mt_pll_raise_little_cpu_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(&dparam_ops); diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index c1e75ef6f6..523958788b 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -5,16 +5,32 @@ #include #include +/* + * The RAM_CODE ADC on Kukui can support only 12 different levels. Each model + * can create its own mapping if needed, with an offset (0x10, 0x20, ..., + * defined as CONFIG_BOARD_SDRAM_TABLE_OFFSET) applied in ram_code(). + */ static const char *const sdram_configs[] = { - [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", - [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", - [3] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", - [4] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", - [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", - [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", - [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", - [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", - [10] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + /* Standard table. */ + [0x00] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x01] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x02] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x03] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", + [0x04] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [0x05] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [0x06] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [0x07] = "sdram-lpddr4x-SDADA4CR-128G-4GB", + [0x08] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x09] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + [0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + + /* Table shared by Burnet and its variants, offset = 0x10 */ + [0x10] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", }; static struct sdram_params params; @@ -22,11 +38,15 @@ static struct sdram_params params; const struct sdram_params *get_sdram_config(void) { uint32_t ramcode = ram_code(); + const char *name = NULL; - if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], ¶ms, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) - die("Cannot load SDRAM parameter file!"); + if (ramcode < ARRAY_SIZE(sdram_configs)) + name = sdram_configs[ramcode]; + + if (!name || cbfs_boot_load_file(name, ¶ms, sizeof(params), + CBFS_TYPE_STRUCT) != sizeof(params)) + die("Cannot load SDRAM parameter file for RAM code %#02x: %s!", + ramcode, name ? name : "unknown"); return ¶ms; } diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index af13aa1d79..719b3c29e9 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,13 +1,15 @@ sdram-params := -sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB -sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB -sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB +sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-MT53E2G32D4NQ-046-8GB sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB -sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index cf5c4d2b16..767fa4af12 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c index cf5c4d2b16..05cd6df89d 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .frequency = 1600, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index e95df6c613..1734797042 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c new file mode 100644 index 0000000000..1734797042 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, + [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x6, 0x5}, + [CHANNEL_B] = {0x6, 0x6} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x58}, + [CHANNEL_B] = {0x58, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index a9844780b2..a7f2123faf 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 95e909195e..8141d2aafe 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 3792182dfb..74e8187654 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 301128383c..53028b067e 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 81887b5a96..26b12bfea3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c new file mode 100644 index 0000000000..20f0c4a30d --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .frequency = 1600, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index eaebc752bd..1dd5d94a21 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 2c3076dadc..427e99de9c 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 477cd47c32..6ce51a3961 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 8360f2ac24..f3da77cd6b 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -86,15 +86,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/link/hda_verb.c b/src/mainboard/google/link/hda_verb.c index 8cd84f0417..1f54222ae0 100644 --- a/src/mainboard/google/link/hda_verb.c +++ b/src/mainboard/google/link/hda_verb.c @@ -110,7 +110,6 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(3, 0x07, 0x18560030), }; - const u32 pc_beep_verbs[] = { 0x00170500, /* power up codec */ 0x00270500, /* power up DAC */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 1438c7f720..c4b621ac7a 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -105,8 +105,6 @@ static int int15_handler(void) } #endif - - static void mainboard_init(struct device *dev) { uint32_t board_version = 0; diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index e1d3747686..2d62980420 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -28,9 +28,9 @@ void platform_romstage_main(void) /* Set to maximum frequency */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) - mt_pll_raise_ca53_freq(1600 * MHz); + mt_pll_raise_little_cpu_freq(1600 * MHz); else - mt_pll_raise_ca53_freq(1700 * MHz); + mt_pll_raise_little_cpu_freq(1700 * MHz); mtk_mmu_after_dram(); } diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d01d95f7fc..b9c6a1ba34 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -1,7 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS def_bool n - select SOC_INTEL_GLK + select SOC_INTEL_GEMINILAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -97,10 +97,6 @@ config MAINBOARD_FAMILY string default "Google_Octopus" -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 2c68045685..488ba07cc4 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -3,15 +3,22 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include #include +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + void mainboard_smi_gpi_handler(const struct gpi_status *sts) { if (gpi_status_get(sts, EC_SMI_GPI)) @@ -54,3 +61,27 @@ void __weak variant_smi_sleep(u8 slp_typ) { /* Leave for the variant to implement if necessary. */ } + +void power_off_lte_module(void) +{ + + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 80e4873694..3fef757dc9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -273,8 +273,8 @@ chip soc/intel/apollolake # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff); + # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); + # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field @@ -285,4 +285,8 @@ chip soc/intel/apollolake # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # 101=50ms, 110=75ms, 111=100ms (default) register "PmicPmcIpcCtrl" = "0x5e4302f8" + + # FSP UPD to modify the Integrated Filter (IF) value + # Set it to default value: 0x12 + register "ModPhyIfValue" = "0x12" end diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index ecc9355138..fa86170f78 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -54,9 +54,6 @@ * ACPI related definitions for ASL code. */ -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 206ce8bd90..f39a786f11 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -50,4 +50,8 @@ bool no_touchscreen_sku(uint32_t sku_id); /* allow each variants to customize smi sleep flow. */ void variant_smi_sleep(u8 slp_typ); +/* LTE power off sequence: + * GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 */ +void power_off_lte_module(void); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 0212bea46d..6c2aa95747 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -41,44 +41,44 @@ chip soc/intel/apollolake # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. register "emmc_rx_strobe_cntl" = "0x0b0b" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C5 | Audio | - #| I2C6 | Trackpad | - #| I2C7 | Touchscreen | - #+-------------------+---------------------------+ + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "10" - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - .i2c[6] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 66, - .fall_time_ns = 90, - .data_hold_time_ns = 350, - }, - .i2c[7] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 44, - .fall_time_ns = 90, - }, + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, - }" + }" device domain 0 on device pci 16.0 off end # - I2C 0 @@ -124,34 +124,34 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 10 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "generic.has_power_resource" = "1" - register "generic.enable_delay_ms" = "10" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" - register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "generic.reset_delay_ms" = "50" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 40 on end - end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.has_power_resource" = "1" + register "generic.enable_delay_ms" = "10" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 97c77a95dc..96806a0b24 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -16,34 +16,6 @@ enum { SKU_40_DROID = 40, /* LTE + Touch + KB backlight*/ }; -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} - const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; @@ -68,14 +40,13 @@ void variant_smi_sleep(u8 slp_typ) case SKU_38_DROID: case SKU_39_DROID: case SKU_40_DROID: - power_off_lte_module(slp_typ); + power_off_lte_module(); return; default: return; } } - void variant_update_devtree(struct device *dev) { struct soc_intel_apollolake_config *cfg = NULL; diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 2f2f80bd28..3f2a88477e 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -139,4 +139,7 @@ chip soc/intel/apollolake end end # - I2C 6 end + + # Disable compliance mode + register "DisableComplianceMode" = "1" end diff --git a/src/mainboard/google/octopus/variants/dood/variant.c b/src/mainboard/google/octopus/variants/dood/variant.c index dda24f8330..1a8a37164a 100644 --- a/src/mainboard/google/octopus/variants/dood/variant.c +++ b/src/mainboard/google/octopus/variants/dood/variant.c @@ -16,35 +16,6 @@ enum { SKU_4_WIFI_2CAM = 4, /* Wifi + dual camera */ }; -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} - - void variant_smi_sleep(u8 slp_typ) { /* Currently use cases here all target to S5 therefore we do early return @@ -55,7 +26,7 @@ void variant_smi_sleep(u8 slp_typ) switch (google_chromeec_get_board_sku()) { case SKU_1_LTE: case SKU_3_LTE_2CAM: - power_off_lte_module(slp_typ); + power_off_lte_module(); return; default: return; diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index 9fb63f5f43..51c9d39021 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 4d92630cac..8148dcef2d 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -10,8 +10,10 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), - PAD_NC(GPIO_67, UP_20K), - PAD_NC(GPIO_117, UP_20K), + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), @@ -21,7 +23,8 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), - PAD_NC(GPIO_161, UP_20K), + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), PAD_NC(GPIO_213, DN_20K), PAD_NC(GPIO_214, DN_20K), @@ -33,3 +36,21 @@ const struct pad_config *variant_override_gpio_table(size_t *num) return default_override_table; } + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; +} diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h index 60c53dc649..29aee4f5ff 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/ec.h @@ -5,4 +5,9 @@ #include +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)) + #endif diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 1d1a67ad33..0b81752f72 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -156,6 +156,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c new file mode 100644 index 0000000000..f1ec818bb3 --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define LTE_SKU 4 + +static bool is_lte_sku(void) +{ + return (google_chromeec_get_board_sku() == LTE_SKU); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + if (is_lte_sku()) + power_off_lte_module(); +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (!is_lte_sku()) + filename = "wifi_sar-fleex.hex"; + + return filename; +} diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index dca07f609a..67e105649a 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -66,6 +66,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num) case SKU_9_HDMI: case SKU_19_HDMI_TS: case SKU_50_HDMI: + case SKU_52_HDMI_TS: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; case SKU_17_LTE: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 3ab69881a1..8fc63cca21 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -14,6 +14,8 @@ enum { SKU_38_2A2C_360_TS_NO_STYLUES = 38, SKU_49_2A2C_TS = 49, SKU_50_HDMI = 50, + SKU_51_2A2C = 51, + SKU_52_HDMI_TS = 52, }; #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 5188be6433..7c84f2696b 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -9,34 +9,6 @@ #include #include -struct gpio_with_delay { - gpio_t gpio; - unsigned int delay_msecs; -}; - -static void power_off_lte_module(u8 slp_typ) -{ - const struct gpio_with_delay lte_power_off_gpios[] = { - { - GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ - 30, - }, - { - GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ - 100 - }, - { - GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - 0 - } - }; - - for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { - gpio_output(lte_power_off_gpios[i].gpio, 0); - mdelay(lte_power_off_gpios[i].delay_msecs); - } -} - const char *mainboard_vbt_filename(void) { uint32_t sku_id; @@ -47,6 +19,7 @@ const char *mainboard_vbt_filename(void) case SKU_9_HDMI: case SKU_19_HDMI_TS: case SKU_50_HDMI: + case SKU_52_HDMI_TS: return "vbt_garg_hdmi.bin"; default: return "vbt.bin"; @@ -63,7 +36,7 @@ void variant_smi_sleep(u8 slp_typ) switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: - power_off_lte_module(slp_typ); + power_off_lte_module(); return; default: return; diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index 3ade35402f..af6711a5fc 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -52,7 +52,7 @@ chip soc/intel/apollolake #| I2C5 | Audio | #| I2C6 | Trackpad | #+-------------------+---------------------------+ - register "tcc_offset" = "15" + register "tcc_offset" = "15" register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index b80d0317c8..9ce2a0b2cf 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -159,18 +159,18 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" - register "enable_delay_ms" = "50" - register "has_power_resource" = "1" - device i2c 39 on end - end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl index 2265c82bbb..d13b0bd5c5 100644 --- a/src/mainboard/google/parrot/acpi/superio.asl +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -3,7 +3,6 @@ /* mainboard configuration */ #include "../ec.h" - #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 3332286a29..62e52c483f 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -22,7 +22,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - #if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index c39a399f0c..61e51d0df3 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "500" # 50ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 3c5c36369b..f0ffc9fe4c 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,15 +54,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index d98edecb01..3aa58c35a6 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -7,7 +7,6 @@ #include #include "ec.h" - void parrot_ec_init(void) { printk(BIOS_DEBUG, "Parrot EC Init\n"); @@ -53,7 +52,6 @@ void parrot_ec_init(void) ec_kbc_write_ib(0xA2); } - /* Parrot Hardware Revision */ u8 parrot_rev(void) { diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index 9d58a0e46d..1c838a390b 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -23,7 +23,6 @@ const u32 cim_verb_data[] = { 0x10250742, // Subsystem ID 0x0000000E, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10250742 */ AZALIA_SUBVENDOR(0, 0x10250742), diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 4e031d3dfb..16695dbeb8 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -18,7 +18,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_ACPI_ENABLE); } - static void mainboard_init(struct device *dev) { /* Initialize the Embedded Controller */ diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index a359e06af3..22e372dead 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -54,13 +54,10 @@ void mainboard_smi_sleep(u8 slp_typ) printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); /* Disable SCI and SMI events */ - /* Clear pending events that may trigger immediate wake */ - /* Enable wake events */ - /* Tell the EC to Disable USB power */ if (gnvs->s3u0 == 0 && gnvs->s3u1 == 0) { ec_kbc_write_cmd(0x45); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 8b54b9977a..85c0407e81 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -231,7 +231,6 @@ static void parade_dp_bridge_setup(void) udelay(10); gpio_set_value(dp_rst_l, 1); - gpio_set_pull(dp_hpd, GPIO_PULL_NONE); gpio_cfg_pin(dp_hpd, GPIO_INPUT); @@ -254,7 +253,7 @@ static void parade_dp_bridge_setup(void) * we're out of here. * If it's not ready after a second, then we're in big trouble. */ - for(i = 0; i < 1000; i++){ + for (i = 0; i < 1000; i++){ if (gpio_get_value(dp_hpd)) break; mdelay(1); diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index d99db809ef..83d38fa142 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -129,13 +129,13 @@ static unsigned long primitive_mem_test(void) unsigned long *l = (void *)0x40000000; int bad = 0; unsigned long i; - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); l[i] = 0xffffffff - i; } - for(i = 0; i < 256*1048576; i++){ + for (i = 0; i < 256*1048576; i++){ if (! (i%1048576)) printk(BIOS_SPEW, "%lu ...", i); if (l[i] != (0xffffffff - i)){ @@ -176,8 +176,7 @@ static void simple_spi_test(void) return; } - - for(i = 0; i < amt; i += 4){ + for (i = 0; i < amt; i += 4){ if (rdev_readat(boot_dev, &in, i, 4) < 4) { printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 74b4da6fbc..bda2ca0a18 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index a51207e990..5dd1e9877e 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -9,7 +9,6 @@ #include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 29dbb5890b..ed25bebdd9 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include /* global NVS and variables */ #include diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index dd57835739..997352cd0c 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -1,5 +1,4 @@ -SPD_BIN = $(obj)/spd.bin SEC_SPD_BIN = $(obj)/sec-spd.bin define gen_spd_bin @@ -17,16 +16,8 @@ add_spd_to_cbfs= \ ifeq ($(SPD_SOURCES),) SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) -else - SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) endif -# Include SPD ROM data -$(SPD_BIN): $(SPD_DEPS) - $(call gen_spd_bin, $@, $+) - -$(call add_spd_to_cbfs, spd.bin, $(SPD_BIN)) - # Add optional secondary SPD ROM data if present ifneq ($(SEC_SPD_SOURCES),) diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex new file mode 100644 index 0000000000..168f15e37b --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 08 00 50 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 08 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ce943c486c..4496dd9af6 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -42,25 +42,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -77,15 +67,6 @@ chip soc/intel/skylake }" register "tcc_offset" = "10" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -168,17 +149,12 @@ chip soc/intel/skylake # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty # USB 3.0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -263,6 +239,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi @@ -290,6 +268,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index c459bad90a..3a15023894 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -388,7 +388,6 @@ static const struct pad_config ish_enabled_gpio_table[] = { PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1), }; - static const struct pad_config ish_disabled_gpio_table[] = { /* A19 : GPP_A19 ==> TRACKPAD_INT_L * trackpad interrupt to PCH diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl index ddd05f1273..b973200ffe 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl @@ -65,7 +65,6 @@ Scope (\_SB.PCI0.I2C3) Name (_PR0, Package (0x01) { FCPR }) Name (_PR3, Package (0x01) { FCPR }) - /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d57070e61a..14b8b09923 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,25 +32,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -59,15 +49,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -167,7 +148,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -283,9 +263,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index a4dcad0d85..57444a92a5 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,24 +32,14 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "SaImguEnable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -62,15 +52,6 @@ chip soc/intel/skylake # send VR mailbox command for IA/GT/SA rails register "IslVrCmd" = "2" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -298,9 +279,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -381,19 +365,19 @@ chip soc/intel/skylake end end # I2C #1 device pci 15.2 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM005C"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" + chip drivers/i2c/hid + register "generic.hid" = ""WCOM005C"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "generic.wake" = "GPE0_DW2_01" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_E8)" diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 158f0d1a8c..5486670adf 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -22,15 +22,15 @@ #define SKU_0_SYNDRA 0x2BC63 #define SKU_1_SYNDRA 0x2BC62 #define SKU_2_SYNDRA 0x2BC61 -#define SKU_3_SYNDRA 0X2BC60 -#define SKU_4_SYNDRA 0X6BC63 -#define SKU_5_SYNDRA 0X6BC62 -#define SKU_6_SYNDRA 0X6BC61 -#define SKU_7_SYNDRA 0X6BC60 +#define SKU_3_SYNDRA 0x2BC60 +#define SKU_4_SYNDRA 0x6BC63 +#define SKU_5_SYNDRA 0x6BC62 +#define SKU_6_SYNDRA 0x6BC61 +#define SKU_7_SYNDRA 0x6BC60 #define SKU_0_EKKO 0x10118E3 #define SKU_1_EKKO 0x10018E3 #define SKU_2_EKKO 0x10118E1 -#define SKU_3_EKKO 0X10018E1 +#define SKU_3_EKKO 0x10018E1 #define SKU_4_EKKO 0x10118E2 #define SKU_5_EKKO 0x10018E2 #define SKU_6_EKKO 0x10118E0 @@ -38,9 +38,9 @@ #define SKU_0_BARD 0x1019CE3 #define SKU_1_BARD 0x1009CE3 #define SKU_2_BARD 0x1019CE1 -#define SKU_3_BARD 0X1009CE1 -#define SKU_4_BARD 0X1009CE0 -#define SKU_5_BARD 0X1009CE2 +#define SKU_3_BARD 0x1009CE1 +#define SKU_4_BARD 0x1009CE0 +#define SKU_5_BARD 0x1009CE2 #define SKU_6_BARD 0x1019CE0 #define SKU_7_BARD 0x1019CE2 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index a5f997a427..025b82b70a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -32,25 +32,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -59,15 +49,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Slew rate setting for improving audible noise register "AcousticNoiseMitigation" = "1" register "FastPkgCRampDisableIa" = "1" @@ -159,8 +140,8 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" + # RP 1 uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism @@ -304,9 +285,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""SYTS7813"" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 8819350dce..21f0b80274 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,25 +37,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -73,15 +63,6 @@ chip soc/intel/skylake }" register "tcc_offset" = "10" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -162,34 +143,29 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" - # Root port 9 (x2) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + # Root port 9 (x2) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ2# + # PcieRpClkSrcNumber: Uses 3 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Empty - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty # USB 3.0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -283,7 +259,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -315,18 +292,19 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST_PLUS" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0a on end diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 0d835cbe88..2baeb52494 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -4,6 +4,8 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 +SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 bootblock-y += gpio.c diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index de7023dacb..0d31bca856 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -42,25 +42,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "SaImguEnable" = "0" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -69,15 +59,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -172,7 +153,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -262,6 +242,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -298,6 +280,7 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8c22adea2f..477166a422 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,25 +32,15 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -59,15 +49,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -167,7 +148,6 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # Intel Common SoC Config #+-------------------+---------------------------+ @@ -284,9 +264,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 on end # SA IMGU device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 on end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOMCOHO"" diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index aa1c977f2a..4748d45d83 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -14,6 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_NINJA && !BOARD_GOOGLE_SUMO + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index a9a0885507..dedec21122 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -2,11 +2,8 @@ #include #include -#include -#include #include #include -#include void acpi_create_gnvs(struct global_nvs *gnvs) { @@ -27,20 +24,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->dpte = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - current = acpi_madt_irq_overrides(current); - - return current; -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 0f729bf87a..41d9795c5e 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -5,7 +5,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include #include #include "ec.h" @@ -14,10 +13,6 @@ #include #include -void mainboard_suspend_resume(void) -{ -} - #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) { diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc index 1d6619bf8f..6711c2e760 100644 --- a/src/mainboard/google/rambi/variants/banjo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -16,17 +14,3 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc index 4630519b4e..4e8c9017ef 100644 --- a/src/mainboard/google/rambi/variants/candy/Makefile.inc +++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -29,17 +27,3 @@ SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc index 2a641ba881..91d23af976 100644 --- a/src/mainboard/google/rambi/variants/clapper/Makefile.inc +++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c index db313c07ea..1386ae1369 100644 --- a/src/mainboard/google/rambi/variants/clapper/gpio.c +++ b/src/mainboard/google/rambi/variants/clapper/gpio.c @@ -197,7 +197,6 @@ static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, }; - static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, }; diff --git a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc index 5b7d58b8e3..57f72800a5 100644 --- a/src/mainboard/google/rambi/variants/enguarde/Makefile.inc +++ b/src/mainboard/google/rambi/variants/enguarde/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc index da99edce4c..c54f901f49 100644 --- a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc +++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -26,17 +24,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc index eb87d0c619..f17db16e68 100644 --- a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc +++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc index 8a9adf3d81..eacc7b5a09 100644 --- a/src/mainboard/google/rambi/variants/heli/Makefile.inc +++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # RAM_ID Vendor Vendor_PN Freq Size Total_size channel @@ -26,17 +24,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc index bf95c739e8..d9c872ab56 100644 --- a/src/mainboard/google/rambi/variants/kip/Makefile.inc +++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125a SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/ninja/Makefile.inc b/src/mainboard/google/rambi/variants/ninja/Makefile.inc index 723a5e592d..739eb7ea7a 100644 --- a/src/mainboard/google/rambi/variants/ninja/Makefile.inc +++ b/src/mainboard/google/rambi/variants/ninja/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc index 2c2496ebc9..0412c537c5 100644 --- a/src/mainboard/google/rambi/variants/orco/Makefile.inc +++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc index 2c0127cbef..d729475686 100644 --- a/src/mainboard/google/rambi/variants/quawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/rambi/Makefile.inc b/src/mainboard/google/rambi/variants/rambi/Makefile.inc index 5bddd5c15a..012206eb18 100644 --- a/src/mainboard/google/rambi/variants/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/variants/rambi/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -16,17 +14,3 @@ SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc index 2c0127cbef..d729475686 100644 --- a/src/mainboard/google/rambi/variants/squawks/Makefile.inc +++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc index 723a5e592d..739eb7ea7a 100644 --- a/src/mainboard/google/rambi/variants/sumo/Makefile.inc +++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz @@ -20,17 +18,3 @@ SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc index 7269afd299..94702622ce 100644 --- a/src/mainboard/google/rambi/variants/swanky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -12,17 +10,3 @@ SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc index 105684f7eb..27b8a6a42a 100644 --- a/src/mainboard/google/rambi/variants/winky/Makefile.inc +++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. # 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb @@ -16,17 +14,3 @@ SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA SPD_SOURCES += HT_micron_HTTC4G63CFR-PBA_x16_4Gb SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 2455101171..76a864062f 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -18,7 +18,6 @@ config BOARD_GOOGLE_BASEBOARD_REEF select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION - select DRIVERS_INTEL_WIFI select USE_SAR select SAR_ENABLE select DSAR_ENABLE @@ -82,10 +81,6 @@ config MAINBOARD_FAMILY default "Google_Coral" if BOARD_GOOGLE_CORAL default "Google_Reef" -config MAX_CPUS - int - default 8 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 4c35bd25da..da80b8ea9a 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -139,6 +139,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index f987e1da02..f2fc3a61fa 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -139,6 +139,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 1282edb9ba..920431b8d2 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -148,6 +148,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index dfe936faaf..1cc9b99361 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -5,7 +5,6 @@ #include #include - static const struct lpddr4_sku skus[] = { /* * K4F6E304HB-MGCJ - both logical channels While the parts diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index ad76a9194d..aba1227de1 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -135,6 +135,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/mainboard/google/reef/variants/sand/include/variant/ec.h b/src/mainboard/google/reef/variants/sand/include/variant/ec.h index 8d0105f15e..87d2887135 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/ec.h @@ -60,7 +60,6 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index a82400ff60..ad8c808d88 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -144,6 +144,7 @@ chip soc/intel/apollolake device generic 0 on end end end + device pci 0f.0 on end # - CSE device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index df5e5b8420..5b580724bb 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -2,13 +2,13 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BH720 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -22,7 +22,6 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_SARIEN select SYSTEM_TYPE_CONVERTIBLE if BOARD_GOOGLE_ARCADA - select TPM2 select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_SARIEN select USE_SAR diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index eea7f472e6..e7bfc53aa0 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += bootblock.c +ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-y += sku.c diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index b666fbc4f6..aafade4f44 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -12,7 +12,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -40,7 +40,7 @@ DefinitionBlock( #include /* Low power idle table */ - #include + #include #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/sarien/mainboard.c b/src/mainboard/google/sarien/mainboard.c new file mode 100644 index 0000000000..5399e6cd78 --- /dev/null +++ b/src/mainboard/google/sarien/mainboard.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + printk(BIOS_DEBUG, "mainboard: %s init\n", __func__); + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +} diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a84e73a826..9a4c6dda10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" @@ -133,8 +132,6 @@ chip soc/intel/cannonlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "{ .enable = 1, \ @@ -152,8 +149,6 @@ chip soc/intel/cannonlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -340,7 +335,7 @@ chip soc/intel/cannonlake device i2c 2c on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" @@ -350,7 +345,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -378,11 +373,19 @@ chip soc/intel/cannonlake device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[9]" = "1" end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.2 on # PCI Express Port 11 + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240993..a76e2ed2e9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,7 +15,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" @@ -140,7 +139,6 @@ chip soc/intel/cannonlake register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 - register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH @@ -152,7 +150,6 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -369,7 +366,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection @@ -386,22 +383,38 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 (USB) + device pci 1c.0 on # PCI Express Port 1 (USB) + register "PcieRpSlotImplemented[0]" = "1" + end device pci 1c.1 off end # PCI Express Port 2 (USB) device pci 1c.2 off end # PCI Express Port 3 (USB) device pci 1c.3 off end # PCI Express Port 4 (USB) device pci 1c.4 off end # PCI Express Port 5 (USB) device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 + device pci 1c.7 on # PCI Express Port 8 + register "PcieRpSlotImplemented[7]" = "1" + end device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.1 on # PCI Express Port 10 + register "PcieRpSlotImplemented[9]" = "1" + end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 37c11e047f..c9ca334a8d 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY def_bool n select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select INTEL_LYNXPOINT_LP @@ -18,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select DRIVERS_I2C_RTD2132 if BOARD_GOOGLE_LEON + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 3435c28111..666143cbe1 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -23,7 +23,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - #if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index e22a41ebc2..200721b8ef 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -40,15 +40,6 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 2a819d3a35..90f28e7ec2 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -16,8 +16,6 @@ void mainboard_suspend_resume(void) apm_control(APM_CNT_FINALIZE); } - - static void mainboard_init(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc index 6d1ee81ec7..d8d748b726 100644 --- a/src/mainboard/google/slippy/variants/falco/Makefile.inc +++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) @@ -13,16 +10,4 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index c163202e99..7df0ca1a6f 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) diff --git a/src/mainboard/google/slippy/variants/leon/Makefile.inc b/src/mainboard/google/slippy/variants/leon/Makefile.inc index 3dab895e9c..213dadb006 100644 --- a/src/mainboard/google/slippy/variants/leon/Makefile.inc +++ b/src/mainboard/google/slippy/variants/leon/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -12,16 +9,4 @@ SPD_SOURCES += Micron_4KTF25664HZ # 4: space holder SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 SPD_SOURCES += Samsung_K4B4G1646Q # 6: 2GB / CH0 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index f3b5c4a257..6dee38e36e 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc index c19326e0c5..f8c5b0d88f 100644 --- a/src/mainboard/google/slippy/variants/peppy/Makefile.inc +++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -13,16 +10,4 @@ SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1 SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6CFR6A # 7: 2GB / CH0 + CH1 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index cd6a0df9ad..689fee4cf3 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_down_delay" = "150" # 15ms diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc index 3306b797f0..cd38d98051 100644 --- a/src/mainboard/google/slippy/variants/wolf/Makefile.inc +++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - # Order of names in SPD_SOURCES is important! SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 @@ -11,16 +8,4 @@ SPD_SOURCES += Micron_4KTF25664HZ # 3: 2GB / CH0 SPD_SOURCES += Hynix_HMT425S6AFR6A # 4: 2GB / CH0 SPD_SOURCES += Samsung_K4B4G1646B # 4: 2GB / CH0 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index 5ccca1d821..de61839cc7 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,7 +1,6 @@ chip northbridge/intel/haswell - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) register "gpu_panel_power_down_delay" = "500" # 50ms (T10) diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 27b6eca1f6..f994e57912 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -23,7 +23,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - #if CONFIG(CHROMEOS) gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index a03a0a6dc7..bd91506b39 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms register "gpu_panel_power_down_delay" = "150" # T3: 15ms diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e71d0eec78..f2f21bc0d2 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,15 +91,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 6e9b490917..05ff973a47 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -55,14 +55,12 @@ void stout_ec_finalize_smm(void) critical_shutdown = 1; } - /* Thermal Device Error : Peripheral Status 3 (0x35) bit 8 */ if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; } - /* Critical Battery Error */ ec_reg = ec_read(EC_MBAT_STATUS); @@ -75,7 +73,6 @@ void stout_ec_finalize_smm(void) printk(BIOS_ERR, " EC Read Battery Error\n"); } - if (critical_shutdown) { printk(BIOS_ERR, "EC critical_shutdown"); diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 29a6923726..7f4e29d2e8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -17,8 +17,6 @@ void mainboard_suspend_resume(void) ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER); } - - static void mainboard_init(struct device *dev) { struct device *ethernet_dev = NULL; diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 6a0f912c00..b3ec4b59a4 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC_SPI if !BOARD_GOOGLE_BUBS select RTC if !BOARD_GOOGLE_BUBS select MISSING_BOARD_RESET if BOARD_GOOGLE_BUBS + select DRIVERS_TI_SN65DSI86BRIDGE select SOC_QUALCOMM_SC7180 select SPI_FLASH select SPI_FLASH_WINBOND @@ -51,6 +52,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config MAINBOARD_PART_NUMBER string default "Bubs" if BOARD_GOOGLE_BUBS + default "Coachz" if BOARD_GOOGLE_COACHZ default "Lazor" if BOARD_GOOGLE_LAZOR default "Pompom" if BOARD_GOOGLE_POMPOM default "Trogdor" if BOARD_GOOGLE_TROGDOR diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index b7c03f92e5..ea1230716a 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -4,6 +4,10 @@ config BOARD_GOOGLE_BUBS bool "Bubs" select BOARD_GOOGLE_TROGDOR_COMMON +config BOARD_GOOGLE_COACHZ + bool "Coachz" + select BOARD_GOOGLE_TROGDOR_COMMON + config BOARD_GOOGLE_LAZOR bool "Lazor" select BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index cab44032eb..4d38378aa0 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -9,11 +9,16 @@ #define GPIO_EC_IN_RW GPIO(118) #define GPIO_AP_EC_INT GPIO(94) -#define GPIO_WP_STATE GPIO(42) #define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) #define GPIO_SD_CD_L GPIO(69) #define GPIO_AMP_ENABLE GPIO(23) +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : \ + (CONFIG(BOARD_GOOGLE_COACHZ) ? GPIO(52) : GPIO(30))) + void setup_chromeos_gpios(void); #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c index c1a48925fa..edde164746 100644 --- a/src/mainboard/google/trogdor/boardid.c +++ b/src/mainboard/google/trogdor/boardid.c @@ -2,6 +2,7 @@ #include #include +#include uint32_t board_id(void) { @@ -15,14 +16,28 @@ uint32_t board_id(void) return id; } +/* Some boards/revisions use one GPIO mapping and others use another. There's no real rhyme or + reason to it. Don't try to think about it too much... */ +static bool use_old_pins(void) +{ + return ((CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() < 2) || + CONFIG(BOARD_GOOGLE_LAZOR) || + (CONFIG(BOARD_GOOGLE_POMPOM) && board_id() < 1)); +} + uint32_t ram_code(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t old_pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + const gpio_t pins[] = {[2] = GPIO(5), [1] = GPIO(3), [0] = GPIO(1)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } @@ -31,10 +46,15 @@ uint32_t sku_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t old_pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + const gpio_t pins[] = {[2] = GPIO(2), [1] = GPIO(90), [0] = GPIO(58)}; - if (id == UNDEFINED_STRAPPING_ID) - id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + if (id == UNDEFINED_STRAPPING_ID) { + if (use_old_pins()) + id = gpio_base2_value(old_pins, ARRAY_SIZE(old_pins)); + else + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + } return id; } diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 9c45dfe71e..989bf6902e 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -5,16 +5,10 @@ #include "board.h" #include -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); gpio_input_pullup(GPIO_AP_EC_INT); - gpio_input(GPIO_WP_STATE); gpio_input_pullup(GPIO_SD_CD_L); gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); gpio_output(GPIO_AMP_ENABLE, 0); diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 3aa047309f..d5324eee49 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -2,22 +2,19 @@ FLASH@0x0 8M { WP_RO 4M { - RO_SECTION 0x3c4000 { + RO_SECTION 0x3e4000 { BOOTBLOCK 96K COREBOOT(CBFS) - FMAP@0x3c0000 0x1000 + FMAP@0x3e0000 0x1000 GBB 0x2f00 RO_FRID 0x100 } - RO_VPD(PRESERVE) 228K - RO_DDR_TRAINING(PRESERVE) 8K - RO_LIMITS_CFG(PRESERVE) 4K + RO_VPD(PRESERVE) } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_LIMITS_CFG(PRESERVE) 4K + RW_MRC_CACHE(PRESERVE) 8K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index c82eaa0e02..57f3a3ba0f 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,9 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +#include +#include +#include +#include #include +#include #include +#include "board.h" + +#define BRIDGE_BUS 0x2 +#define BRIDGE_CHIP 0x2d + static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, .imp_ctrl1 = 0x08, @@ -12,26 +24,27 @@ static struct usb_board_data usb0_board_data = { static void setup_usb(void) { + /* Assert EN_PP3300_HUB for those board variants that use it. */ + gpio_output(GPIO(84), 1); + setup_usb_host0(&usb0_board_data); } static void qi2s_configure_gpios(void) { - gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(50), GPIO50_FUNC_MI2S_1_WS, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); gpio_configure(GPIO(51), GPIO51_FUNC_MI2S_1_DATA0, - GPIO_PULL_UP, GPIO_8MA, GPIO_OUTPUT); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); } static void load_qup_fw(void) { qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_SPI, MIXED); /* ESIM SPI */ - qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* EDP Bridge I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_UART, FIFO); /* BT UART */ qupv3_se_fw_load_and_init(QUPV3_0_SE4, SE_PROTOCOL_I2C, MIXED); /* Pen Detect I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* SAR I2C */ @@ -48,11 +61,60 @@ static void load_qup_fw(void) qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */ } +static void configure_display(void) +{ + printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); + + /* Bridge Enable GPIO */ + gpio_output(GPIO_EDP_BRIDGE_ENABLE, 1); + + /* PP3300 EDP power supply */ + gpio_output(GPIO_EN_PP3300_DX_EDP, 1); +} + +static void display_init(struct edid *edid) +{ + uint32_t dsi_bpp = 24; + uint32_t lanes = 4; + + if (mdss_dsi_config(edid, lanes, dsi_bpp)) + return; + + sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp); + mdp_dsi_video_config(edid); + mdss_dsi_video_mode_config(edid, dsi_bpp); + mdp_dsi_video_on(); +} + +static void display_startup(void) +{ + static struct edid ed; + enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; + + i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */ + if (display_init_required()) { + configure_display(); + mdelay(250); /* Delay for the panel to be up */ + sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); + if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0) + return; + + printk(BIOS_INFO, "display init!\n"); + + /* Configure backlight */ + gpio_output(GPIO_BACKLIGHT_ENABLE, 1); + display_init(&ed); + set_vbe_mode_info_valid(&ed, (uintptr_t)0); + } else + printk(BIOS_INFO, "Skipping display init.\n"); +} + static void mainboard_init(struct device *dev) { setup_usb(); qi2s_configure_gpios(); load_qup_fw(); + display_startup(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 562e329d0e..8b6f1dec8d 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -3,6 +3,7 @@ #include #include #include +#include static void prepare_usb(void) { @@ -17,6 +18,8 @@ void platform_romstage_main(void) { prepare_usb(); + check_wdog(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 4c9587abc0..95158bf9ee 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -11,7 +11,6 @@ #define GPIO_RECOVERY_SERVO GPIO(0, B, 1) #define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1) - void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 16834ae199..58ff4eb270 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -26,12 +27,15 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE + select HAVE_SPD_IN_CBFS if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS bool default y + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -42,6 +46,15 @@ config CHROMEOS select VBOOT_LID_SWITCH select VBOOT_EARLY_EC_SYNC +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select GEO_SAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DIMM_SPD_SIZE int default 512 @@ -67,14 +80,18 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string + default "Delbin" if BOARD_GOOGLE_DELBIN + default "Eldrid" if BOARD_GOOGLE_ELDRID default "Halvor" if BOARD_GOOGLE_HALVOR + default "Lindar" if BOARD_GOOGLE_LINDAR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Terrador" if BOARD_GOOGLE_TERRADOR + default "Todor" if BOARD_GOOGLE_TODOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Voxel" if BOARD_GOOGLE_VOXEL - default "Delbin" if BOARD_GOOGLE_DELBIN + default "Boldar" if BOARD_GOOGLE_BOLDAR config MAX_CPUS int @@ -100,14 +117,18 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string + default "delbin" if BOARD_GOOGLE_DELBIN + default "eldrid" if BOARD_GOOGLE_ELDRID default "halvor" if BOARD_GOOGLE_HALVOR + default "lindar" if BOARD_GOOGLE_LINDAR default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR + default "todor" if BOARD_GOOGLE_TODOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "voxel" if BOARD_GOOGLE_VOXEL - default "delbin" if BOARD_GOOGLE_DELBIN + default "boldar" if BOARD_GOOGLE_BOLDAR config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 06bbc58f59..2817448452 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,10 +1,28 @@ comment "Volteer" +config BOARD_GOOGLE_DELBIN + bool "-> Delbin" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 + select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_ELDRID + bool "-> Eldrid" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 + config BOARD_GOOGLE_HALVOR bool "-> Halvor" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU +config BOARD_GOOGLE_LINDAR + bool "-> Lindar" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + config BOARD_GOOGLE_MALEFOR bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -13,7 +31,12 @@ config BOARD_GOOGLE_MALEFOR config BOARD_GOOGLE_TERRADOR bool "-> Terrador" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS + select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 + +config BOARD_GOOGLE_TODOR + bool "-> Todor" + select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_TRONDO @@ -32,13 +55,15 @@ config BOARD_GOOGLE_VOLTEER2 select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 + select DRIVERS_GENESYSLOGIC_GL9755 config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select USE_CAR_NEM_ENHANCED_V2 -config BOARD_GOOGLE_DELBIN - bool "-> Delbin" +config BOARD_GOOGLE_BOLDAR + bool "-> Boldar" select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c index ff9c5ed9f5..328480e3bc 100644 --- a/src/mainboard/google/volteer/bootblock.c +++ b/src/mainboard/google/volteer/bootblock.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 09642a05ba..abd50c57ba 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 60ea3ded64..07a5464068 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -7,16 +7,16 @@ FLASH@0xfe000000 0x2000000 { # Place RW_LEGACY at the start of BIOS region such that the rest # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xf00000 - RW_SECTION_A@0xf00000 0x3e0000 { + RW_LEGACY(CBFS)@0x0 0xb00000 + RW_SECTION_A@0xb00000 0x5e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x5cffc0 + RW_FWID_A@0x5dffc0 0x40 } - RW_SECTION_B@0x12e0000 0x3e0000 { + RW_SECTION_B@0x10e0000 0x5e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x5cffc0 + RW_FWID_B@0x5dffc0 0x40 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index ddbc10f4e4..18c975e483 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include "variant/ec.h" @@ -17,7 +13,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -31,6 +27,9 @@ DefinitionBlock( #include #include #include +#if CONFIG(VARIANT_HAS_MIPI_CAMERA) + #include +#endif } /* Mainboard hooks */ #include "mainboard.asl" @@ -56,7 +55,6 @@ DefinitionBlock( #if CONFIG(VARIANT_HAS_MIPI_CAMERA) /* Camera */ - #include #include #endif /* VARIANT_HAS_MIPI_CAMERA */ } diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c index b47e49756b..92fb9442ce 100644 --- a/src/mainboard/google/volteer/ec.c +++ b/src/mainboard/google/volteer/ec.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4cf8..0538e7403e 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -33,7 +33,7 @@ static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S3, NONE), }; -static const struct pad_config i2s_enable_pads[] = { +static const struct pad_config i2s_up3_enable_pads[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SCLK */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ @@ -45,6 +45,15 @@ static const struct pad_config i2s_enable_pads[] = { PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SFRM */ }; +static const struct pad_config i2s_up4_enable_pads[] = { + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SCLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ +}; + static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_A23, NONE), PAD_NC(GPP_D19, NONE), @@ -73,8 +82,14 @@ static void fw_config_handle(void *unused) } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { - printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); + gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + } + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_UP4))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP4.\n"); + gpio_configure_pads(i2s_up4_enable_pads, ARRAY_SIZE(i2s_up4_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl index c360fcfb76..e2f6d11aa9 100644 --- a/src/mainboard/google/volteer/mainboard.asl +++ b/src/mainboard/google/volteer/mainboard.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1ede7f2b49..1fcd5eb5ac 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,28 +1,68 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include +#include #include -#include +#include +#include #include +#include #include #include +#include static void mainboard_init(struct device *dev) { mainboard_ec_init(); } +static void add_fw_config_oem_string(const struct fw_config *config, void *arg) +{ + struct smbios_type11 *t; + char buffer[64]; + + t = (struct smbios_type11 *)arg; + + snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name); + t->count = smbios_add_string(t->eos, buffer); +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + fw_config_for_each_found(add_fw_config_oem_string, t); +} + static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->get_smbios_strings = mainboard_smbios_strings; +} + +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) +{ + int ret; + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (cr50_is_long_interrupt_pulse_enabled()) { + printk(BIOS_INFO, "Enabling S0i3.4\n"); + } else { + /* + * Disable S0i3.4, preventing the GPIO block from switching to + * slow clock. + */ + printk(BIOS_INFO, "Not enabling S0i3.4\n"); + cfg->LpmStateDisableMask |= LPM_S0i3_4; + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } } static void mainboard_chip_init(void *chip_info) @@ -38,6 +78,21 @@ static void mainboard_chip_init(void *chip_info) override_pads, override_num); } +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + bool has_usb4; + + /* If device doesn't have USB4 hardware, disable tbt */ + has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + + if (!has_usb4) + memset(params->ITbtPcieRootPortEn, + 0, + ARRAY_SIZE(params->ITbtPcieRootPortEn) * + sizeof(*params->ITbtPcieRootPortEn)); +} + struct chip_operations mainboard_ops = { .init = mainboard_chip_init, .enable_dev = mainboard_enable, diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index d35bbb5bea..315ec2004a 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -15,11 +11,10 @@ #include #include - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct ddr_memory_cfg *board_cfg = variant_memory_params(); const struct spd_info spd_info = { .topology = MEMORY_DOWN, .md_spd_loc = SPD_CBFS, @@ -31,19 +26,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) mem_cfg->PchHdaEnable = 0; - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); -} + meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); -bool mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; - - if (google_chromeec_cbi_get_dram_part_num(part_num_store, - sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); - return false; + /* Disable TBT if no USB4 hardware */ + if (!(fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)))) { + mem_cfg->TcssDma0En = 0; + mem_cfg->TcssItbtPcie0En = 0; + mem_cfg->TcssItbtPcie1En = 0; } - *part_num = part_num_store; - *len = strlen(part_num_store); - return true; } diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index 58e038eb87..5b3e38ca70 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc index e12599420f..eb8e6ff355 100644 --- a/src/mainboard/google/volteer/spd/Makefile.inc +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -2,19 +2,10 @@ ## ifneq ($(SPD_SOURCES),) -SPD_BIN = $(obj)/spd.bin - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/tigerlake/spd/lp4x/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +ifeq ($(SPD_SOURCE_PATH),) +SPD_SOURCE_PATH := src/soc/intel/tigerlake/spd +endif + +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SPD_SOURCE_PATH)/$(f)) + endif diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e0d3beaaa2..898b5ae271 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -13,6 +13,7 @@ fw_config option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 + option MAX98373_ALC5682I_I2S_UP4 4 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 @@ -22,6 +23,14 @@ fw_config option LTE_ABSENT 0 option LTE_PRESENT 1 end + field KB_BL 14 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field NUMPAD 15 + option NUMPAD_ABSENT 0 + option NUMPAD_PRESENT 1 + end field DB_SD 16 19 option SD_ABSENT 0 option SD_GL9755S 1 @@ -55,9 +64,6 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth @@ -136,8 +142,8 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -148,6 +154,40 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Set the minimum assertion width + # PchPmSlpS3MinAssert: + # - 1: 60us + # - 2: 1ms + # - 3: 50ms + # - 4: 2s + register "PchPmSlpS3MinAssert" = "3" # 50ms + # PchPmSlpS4MinAssert: + # - 1 = 1s + # - 2 = 2s + # - 3 = 3s + # - 4 = 4s + register "PchPmSlpS4MinAssert" = "1" # 1s + # PchPmSlpSusMinAssert: + # - 1 = 0ms + # - 2 = 500ms + # - 3 = 1s + # - 4 = 4s + register "PchPmSlpSusMinAssert" = "3" # 1s + # PchPmSlpAMinAssert + # - 1 = 0ms + # - 2 = 4s + # - 3 = 98ms + # - 4 = 2s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" @@ -160,9 +200,9 @@ chip soc/intel/tigerlake # TCSS USB3 register "TcssXhciEn" = "1" - register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "TcssAuxOri" = "0" + register "IomTypeCPortPadCfg[0]" = "0x09000000" + register "IomTypeCPortPadCfg[1]" = "0x09000000" register "IomTypeCPortPadCfg[2]" = "0x09000000" register "IomTypeCPortPadCfg[3]" = "0x09000000" register "IomTypeCPortPadCfg[4]" = "0x09000000" @@ -170,10 +210,6 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[6]" = "0x09000000" register "IomTypeCPortPadCfg[7]" = "0x09000000" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "0" - # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" @@ -194,14 +230,6 @@ chip soc/intel/tigerlake register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -211,21 +239,33 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 60, - .tdp_pl4 = 105, - }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 38, .tdp_pl4 = 71, }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" register "Device4Enable" = "1" register "tcc_offset" = "10" # TCC of 90 + register "CnviBtAudioOffload" = "FORCE_ENABLE" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -280,91 +320,93 @@ chip soc/intel/tigerlake }" device domain 0 on - #From EDS(575683) - device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y - device pci 02.0 on end # Graphics - device pci 04.0 on + device ref igpu on end + device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(85, 90), - TEMP_PCT(80, 69), - TEMP_PCT(75, 56), - TEMP_PCT(70, 46), - TEMP_PCT(65, 36),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" - register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, - .thresholds={TEMP_PCT(50, 90), - TEMP_PCT(47, 69), - TEMP_PCT(45, 56), - TEMP_PCT(42, 46), - TEMP_PCT(39, 36),}}" + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" - register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" - register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" - register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" - register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" ## Power Limits Control - # 10-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is fixed at 64W, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 60000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 15 to 60W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" # Fan options register "options.fan.fine_grained_control" = "1" @@ -373,81 +415,44 @@ chip soc/intel/tigerlake device generic 0 on end end end # DPTF 0x9A03 - device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 08.0 on end # GNA 0x9A11 - device pci 09.0 off end # NPK 0x9A33 - device pci 0a.0 off end # Crash-log SRAM 0x9A0D - device pci 0d.0 on end # USB xHCI 0x9A13 - device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D - device pci 0e.0 off end # VMD 0x9A0B - - # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 - device pci 10.6 off end # THC0 0xA0D0 - device pci 10.7 off end # THC1 0xA0D1 - - device pci 12.0 off end # SensorHUB 0xA0FC - device pci 12.6 off end # GSPI2 0x34FB - - device pci 13.0 off end # GSPI3 0xA0FD - - device pci 14.0 on end # USB3.1 xHCI 0xA0ED - device pci 14.1 off end # USB3.1 xDCI 0xA0EE - device pci 14.2 on end # Shared RAM 0xA0EF + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref tbt_dma0 on + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device ref gna on end + device ref north_xhci on end + device ref cnvi_bt on end + device ref south_xhci on end + device ref shared_ram on end chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + device ref cnvi_wifi on end end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on end # I2C1 0xA0E9 - device pci 15.2 on end # I2C2 0xA0EA - device pci 15.3 on end # I2C3 0xA0EB - - device pci 16.0 on end # HECI1 0xA0E0 - device pci 16.1 off end # HECI2 0xA0E1 - device pci 16.2 off end # CSME 0xA0E2 - device pci 16.3 off end # CSME 0xA0E3 - device pci 16.4 off end # HECI3 0xA0E4 - device pci 16.5 off end # HECI4 0xA0E5 - - device pci 17.0 on end # SATA 0xA0D3 - - device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on end # I2C5 0xA0C6 - device pci 19.2 off end # UART2 0xA0C7 - - device pci 1c.0 on end # RP1 0xA0B8 - device pci 1c.1 off end # RP2 0xA0B9 - device pci 1c.2 off end # RP3 0xA0BA - device pci 1c.3 off end # RP4 0xA0BB - device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 off end # WWAN RP6 0xA0BD - device pci 1c.6 on end # RP7 0xA0BE - device pci 1c.7 on end # SD Card RP8 0xA0BF - - device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 on end # RP11 0xA0B2 - device pci 1d.3 off end # RP12 0xA0B3 - - device pci 1e.0 on end # UART0 0xA0A8 - device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 on + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp11 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" device spi 0 on end end - end # GSPI0 0xA0AA - device pci 1e.3 on + end + device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" @@ -456,18 +461,12 @@ chip soc/intel/tigerlake register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" device spi 0 on end end # FPMCU - end # GSPI1 0xA0AB - device pci 1f.0 on + end + device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # eSPI 0xA080 - A09F - device pci 1f.1 off end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 - device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF - device pci 1f.4 off end # SMBus 0xA0A3 - device pci 1f.5 on end # SPI 0xA0A4 - device pci 1f.6 off end # GbE 0x15E1/0x15E2 - device pci 1f.7 off end # TH 0xA0A6 + end + device ref hda on end end end diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index fde4017c6d..5d367e79de 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -264,6 +260,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F9, NONE), /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> NC */ PAD_NC(GPP_F12, NONE), /* F13 : GSXDOUT ==> NC */ @@ -424,9 +422,6 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index dad762affb..51034c3d73 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -247,7 +247,7 @@ Scope (\_SB.PCI0.I2C3) } }, ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) + Package (0x03) { Package (0x02) { @@ -261,7 +261,12 @@ Scope (\_SB.PCI0.I2C3) { VCM0 } - } + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } } }) Name (PRT0, Package (0x04) @@ -365,13 +370,18 @@ Scope (\_SB.PCI0.I2C3) Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) + Package (0x02) { Package (0x02) { "compatible", "dongwoon,dw9768" - } + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } } }) } @@ -406,7 +416,7 @@ Scope (\_SB.PCI0.I2C3) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, - Package (0x05) + Package (0x06) { Package (0x02) { @@ -432,6 +442,11 @@ Scope (\_SB.PCI0.I2C3) { "compatible", "atmel,24c1024" + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 } } }) @@ -529,13 +544,18 @@ Scope (\_SB.PCI0.I2C2) } }, ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) + Package (0x02) { Package (0x02) { "clock-frequency", 0x0124F800 - } + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } } }) Name (PRT0, Package (0x04) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 2d04380e6f..1428ec8a32 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __MAINBOARD_EC_H__ #define __MAINBOARD_EC_H__ @@ -38,7 +34,9 @@ /* EC can wake from S3 with lid, power button or mode change event */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h index 3c2999294c..4e2733eb50 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 44dcd5b3b5..84081983c3 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ @@ -22,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct ddr_memory_cfg *variant_memory_params(void); int variant_memory_sku(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index f9c544fb2b..dafeb3b3a6 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -1,14 +1,10 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include -static const struct lpddr4x_cfg baseboard_memcfg = { +static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { /* DQ CPU<>DRAM map */ .dq_map = { [0] = { @@ -60,7 +56,12 @@ static const struct lpddr4x_cfg baseboard_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &baseboard_lpddr4x_memcfg +}; + +const struct ddr_memory_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h b/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h similarity index 51% rename from src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h rename to src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h index d08b33bca2..b5fa8c5485 100644 --- a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/boldar/include/variant/gpio.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H @@ -7,9 +7,9 @@ /* Memory configuration board straps */ /* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 #endif diff --git a/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc new file mode 100644 index 0000000000..ed894fee62 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) Parts = EMPTY diff --git a/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2e3fcbc4b5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +EMPTY 0 (0000) diff --git a/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt new file mode 100644 index 0000000000..7f7204cf5f --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +EMPTY diff --git a/src/mainboard/google/hatch/variants/sushi/overridetree.cb b/src/mainboard/google/volteer/variants/boldar/overridetree.cb similarity index 54% rename from src/mainboard/google/hatch/variants/sushi/overridetree.cb rename to src/mainboard/google/volteer/variants/boldar/overridetree.cb index abbcaaa08c..32204c58e7 100644 --- a/src/mainboard/google/hatch/variants/sushi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/boldar/overridetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/cannonlake +chip soc/intel/tigerlake device domain 0 on end diff --git a/src/mainboard/google/volteer/variants/delbin/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c new file mode 100644 index 0000000000..5748bb3a2c --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_NC(GPP_A20, NONE), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h b/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h index 5839395456..b5fa8c5485 100644 --- a/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/delbin/include/variant/gpio.h @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c new file mode 100644 index 0000000000..9d8ad405ce --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg delbin_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &delbin_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc new file mode 100644 index 0000000000..c0e2fffb6b --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt new file mode 100644 index 0000000000..b5bd3ef2b6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b99b811053 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 9b5ae62bba..21b1f0761e 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -1,5 +1,85 @@ chip soc/intel/tigerlake - device domain 0 on - end + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end + end end diff --git a/src/mainboard/google/volteer/variants/eldrid/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc new file mode 100644 index 0000000000..343c7dbb95 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c new file mode 100644 index 0000000000..4f6650b2f9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP_0 */ + PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ + PAD_CFG_GPI(GPP_D4, NONE, DEEP), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_CFG_GPO(GPP_E23, 1, DEEP), + + /* F7 : GPPF7_STRAP ==> GPP_F7_STRAP */ + PAD_CFG_GPI(GPP_F7, NONE, DEEP), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F10 : GPPF10_STRAP ==> GPP_F10_STRAP */ + PAD_CFG_GPI(GPP_F10, NONE, DEEP), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_CFG_GPI(GPP_H1, NONE, DEEP), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_CFG_GPI(GPP_H2, NONE, DEEP), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H10 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> PCH_DMIC_CAM_SCL_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> PCH_DMIC_CAM_SDA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> NC */ + PAD_NC(GPP_E12, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/delbin/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/eldrid/include/variant/acpi/dptf.asl similarity index 100% rename from src/mainboard/google/volteer/variants/delbin/include/variant/acpi/dptf.asl rename to src/mainboard/google/volteer/variants/eldrid/include/variant/acpi/dptf.asl diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h b/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h new file mode 100644 index 0000000000..5839395456 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c new file mode 100644 index 0000000000..577734dbcf --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg eldrid_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &eldrid_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc new file mode 100644 index 0000000000..b966612076 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = H5AN8G6NDJR-XNC, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-2.hex # ID = 2(0b0010) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE, MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt new file mode 100644 index 0000000000..3e298dc618 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +DRAM Part Name ID to assign +H5AN8G6NDJR-XNC 0 (0000) +MT40A512M16TB-062E:J 1 (0001) +H5ANAG6NCMR-XNC 2 (0010) +K4A8G165WC-BCWE 0 (0000) +K4AAG165WA-BCWE 3 (0011) +MT40A1G16KD-062E:E 3 (0011) +H5ANAG6NCJR-XNC 4 (0100) diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt new file mode 100644 index 0000000000..dbe7ecb967 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt @@ -0,0 +1,7 @@ +H5AN8G6NDJR-XNC,0 +MT40A512M16TB-062E:J,1 +H5ANAG6NCMR-XNC,2 +K4A8G165WC-BCWE +K4AAG165WA-BCWE +MT40A1G16KD-062E:E +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb new file mode 100644 index 0000000000..5fcd456d40 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -0,0 +1,149 @@ +chip soc/intel/tigerlake + + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + #These settings improve the USB2 Port1 eye diagram + register "usb2_ports[4]" = "{ + .enable = 1, + .tx_bias = 7, + .tx_emp_enable = 7, + .pre_emp_bias = 3, + .pre_emp_bit = 0, + }" + + device domain 0 on + device ref dptf off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end +end diff --git a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc new file mode 100644 index 0000000000..2685fcddd1 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE diff --git a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt new file mode 100644 index 0000000000..c892d9b58a --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +H5ANAG6NCMR-XNC 0 (0000) +MT40A1G16KD-062E:E 1 (0001) +K4AAG165WA-BCWE 1 (0001) +H5AN8G6NDJR-XNC 2 (0010) +MT40A512M16TB-062E:J 2 (0010) +K4A8G165WC-BCWE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt new file mode 100644 index 0000000000..939d85fd06 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt @@ -0,0 +1,6 @@ +H5ANAG6NCMR-XNC +MT40A1G16KD-062E:E +K4AAG165WA-BCWE +H5AN8G6NDJR-XNC +MT40A512M16TB-062E:J +K4A8G165WC-BCWE diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db5ec..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -2,4 +2,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 2a986882e6..8b5a192c9e 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -23,8 +23,20 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* A10 : I2S2_RXD ==> I2S1_RXD */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : DDSP_HPD3 ==> USB_C2_DP_HPD */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), + /* A16 : USB_OC3# ==> USB_C0_OC_OD# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> NC */ PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), /* A23 : I2S1_SCLK ==> HP_INT_L */ @@ -42,6 +54,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> I2C_SENSOR_SCL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* C1 : SMBDATA ==> FPMCU_BOOT1 */ PAD_CFG_GPO(GPP_C1, 0, DEEP), @@ -53,9 +75,17 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C11, NONE), /* C13 : UART1_TXD ==> NC */ PAD_NC(GPP_C13, NONE), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> TBT_LSX2_TXD */ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), /* D10 : ISH_SPI_CLK ==> TBT_LSX2_RXD */ @@ -64,6 +94,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ PAD_NC(GPP_D12, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -75,10 +107,14 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E5, NONE), /* E10 : SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* E12 : SPI1_MISO_IO1 ==> NC */ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> NC */ PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), /* E16 : ISH_GP7 ==> SD_PRSNT# */ PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> NC */ @@ -96,6 +132,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F11, NONE), /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> NC */ PAD_NC(GPP_F14, NONE), /* F15 : GSXSRESET# ==> NC */ @@ -109,6 +147,8 @@ static const struct pad_config gpio_table[] = { /* F19 : SRCCLKREQ6# ==> NC */ PAD_NC(GPP_F19, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H6 : I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C3_SCL */ @@ -125,6 +165,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H16, NONE), /* H17 : DDPB_CTRLDATA ==> NC */ PAD_NC(GPP_H17, NONE), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H23 : IMGCLKOUT4 ==> NC */ PAD_NC(GPP_H23, NONE), @@ -184,6 +226,9 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000000..edbb681a4e --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &halvor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc index be3cfc8d35..d4c7d0c6ca 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = H9HKNNNCRMBVAR-NEH -SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G64D4SQ-046 WT:A +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HKNNNCRMBVAR-NEH +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G64D4SQ-046 WT:A diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c100..f8b29212f8 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -1,24 +1,17 @@ chip soc/intel/tigerlake - register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" # Type-A / Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A / Type-C Port 2 - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 2 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT register "SaGv" = "SaGv_Disabled" device domain 0 on - device pci 15.0 on + # Baseboard does not have these on, so they must be enabled here. + device ref tbt_pcie_rp2 on end # TBT_PCIe2 + device ref tbt_dma1 on end # TBT DMA1 0x9A1D + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -37,7 +30,9 @@ chip soc/intel/tigerlake register "uid" = "0" register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" - device i2c 31 on end + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end end chip drivers/i2c/max98373 register "vmon_slot_no" = "2" @@ -45,10 +40,12 @@ chip soc/intel/tigerlake register "uid" = "1" register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" - device i2c 32 on end + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end end - end # I2C #0 0xA0E8 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -78,8 +75,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -110,8 +107,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -120,14 +117,7 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HD audio 0xA0C8-A0CF + end + device ref hda on end end end diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c new file mode 100644 index 0000000000..4f3d5f769b --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> NOT USED */ + PAD_NC(GPP_B22, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> SPKR_INT_R */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L_CAP_SITE */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c new file mode 100644 index 0000000000..11bcf4ca89 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg lindar_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &lindar_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc new file mode 100644 index 0000000000..8c96e06187 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt new file mode 100644 index 0000000000..9bf0bd9af0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt new file mode 100644 index 0000000000..a226d2f741 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb new file mode 100644 index 0000000000..5f0f290a5b --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/tigerlake + # USB Port Config + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + + register "SaGv" = "SaGv_Disabled" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + # Baseboard has these on, so they must be disabled here. + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_dma0 off end + + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms + register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index cdffb60dd9..90ad3548f7 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -183,8 +183,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 5444c6fdd3..2c879e09b4 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -54,7 +54,12 @@ static const struct lpddr4x_cfg malefor_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &malefor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) { - return &malefor_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc index 4c95819cb9..8c96e06187 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/malefor/memory/Makefile.inc @@ -2,4 +2,4 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index c84ed833c5..64b15b3dcc 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -2,23 +2,19 @@ chip soc/intel/tigerlake # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used register "SaGv" = "SaGv_Disabled" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -30,11 +26,12 @@ chip soc/intel/tigerlake }" device domain 0 on - device pci 07.0 off end # TBT_PCIe0 0x9A23 - device pci 07.1 off end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 - device pci 15.0 on + # Baseboard has these on, so they must be disabled here. + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_dma0 off end + + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -47,8 +44,8 @@ chip soc/intel/tigerlake register "property_list[0].integer" = "1" device i2c 1a on end end - end # I2C0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -65,8 +62,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - end # I2C1 - device pci 15.2 on + end + device ref i2c3 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -97,8 +94,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -107,14 +104,14 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HD audio + end end end diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index e49e2dccf5..a0267cc7b1 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -20,17 +20,13 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ @@ -54,10 +50,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), - /* C3 : SML0CLK ==> USB4_SMB_SCL */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : SML0DATA ==> USB4_SMB_SDA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ PAD_NC(GPP_C5, DN_20K), /* C7 : SML1DATA ==> EN_USI_CHARGE */ @@ -200,6 +192,8 @@ static const struct pad_config early_gpio_table[] = { /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ @@ -218,6 +212,9 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 773e88561d..7d95658891 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -54,7 +54,12 @@ static const struct lpddr4x_cfg terrador_memcfg = { .ect = 1, /* Enable Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &terrador_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) { - return &terrador_memcfg; + return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc index fc2631cab7..3c8ea4876f 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/memory/Makefile.inc @@ -2,5 +2,5 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index c1c386a621..1ccdb87ab5 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -10,17 +10,14 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used register "SaGv" = "SaGv_Disabled" device domain 0 on - device pci 15.0 on + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -41,6 +38,7 @@ chip soc/intel/tigerlake register "desc" = ""Right Speaker Amp"" register "name" = ""MAXR"" device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end chip drivers/i2c/max98373 @@ -50,10 +48,11 @@ chip soc/intel/tigerlake register "desc" = ""Left Speaker Amp"" register "name" = ""MAXL"" device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 end end - end # I2C #0 0xA0E8 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -83,8 +82,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -115,16 +114,39 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" - register "wake" = "GPE0_DW2_15" - register "probed" = "1" + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2700"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end - end # I2C5 0xA0C6 + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end end end diff --git a/src/mainboard/google/volteer/variants/todor/Makefile.inc b/src/mainboard/google/volteer/variants/todor/Makefile.inc new file mode 100644 index 0000000000..b0bfc567ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c new file mode 100644 index 0000000000..f202543cf6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/ec.h b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h new file mode 100644 index 0000000000..4a9a461191 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h new file mode 100644 index 0000000000..fe512d8c4a --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 + +#endif diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c new file mode 100644 index 0000000000..c8b4ab4e3c --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg todor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &todor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc new file mode 100644 index 0000000000..3c8ea4876f --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt new file mode 100644 index 0000000000..02e7443467 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) diff --git a/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt new file mode 100644 index 0000000000..b74da4a5f0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb new file mode 100644 index 0000000000..1ccdb87ab5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -0,0 +1,152 @@ +chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + + register "SaGv" = "SaGv_Disabled" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2700"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/volteer/variants/trondo/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/Makefile.inc index c9a128d72a..13269db5ec 100644 --- a/src/mainboard/google/volteer/variants/trondo/Makefile.inc +++ b/src/mainboard/google/volteer/variants/trondo/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = - bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc b/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc new file mode 100644 index 0000000000..f40fba6751 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..8d472df850 --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt new file mode 100644 index 0000000000..5ddd52ebba --- /dev/null +++ b/src/mainboard/google/volteer/variants/trondo/memory/mem_list_variant.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index 0932b6484c..d18bb10ff2 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -1,7 +1,8 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + device domain 0 on - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -31,8 +32,8 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -63,8 +64,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -73,6 +74,6 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 + end end end diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 2b99e52029..1077fa13cb 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -30,7 +30,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST), /* B5 : ISH_I2C0_CVF_SDA */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* B6 : ISH_I2C0_CVF_SCL */ @@ -91,18 +91,18 @@ static const struct pad_config override_gpio_table[] = { /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, NONE), /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ @@ -125,7 +125,7 @@ static const struct pad_config override_gpio_table[] = { /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ @@ -154,7 +154,7 @@ static const struct pad_config override_gpio_table[] = { /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -164,7 +164,7 @@ static const struct pad_config override_gpio_table[] = { /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), + PAD_CFG_GPO(GPP_H20, 0, DEEP), /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ @@ -231,8 +231,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h index 6e12175130..08870e0627 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_EC_H #define MAINBOARD_EC_H diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h index c7e4605856..9078664608 100644 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H diff --git a/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc index c2abb9ef0d..37e4c227f5 100644 --- a/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL -SPD_SOURCES += spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 094476525f..5079493437 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,7 +1,55 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on - device pci 15.0 on + device ref ipu on end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -38,7 +86,7 @@ chip soc/intel/tigerlake end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -46,10 +94,16 @@ chip soc/intel/tigerlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 14 on end @@ -68,8 +122,21 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -100,8 +167,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -110,8 +177,8 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -141,7 +208,7 @@ chip soc/intel/tigerlake end end end - device pci 1f.2 hidden + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -174,6 +241,6 @@ chip soc/intel/tigerlake end end end - end # PMC + end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 2b99e52029..6c67fc216e 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -19,9 +19,9 @@ static const struct pad_config override_gpio_table[] = { /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ @@ -91,18 +91,18 @@ static const struct pad_config override_gpio_table[] = { /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_NC(GPP_D16, UP_20K), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ @@ -125,7 +125,7 @@ static const struct pad_config override_gpio_table[] = { /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE), /* F15 : GSXSRESET# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_F15, 1, DEEP), /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ @@ -154,7 +154,7 @@ static const struct pad_config override_gpio_table[] = { /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ - PAD_CFG_GPO(GPP_H14, 1, DEEP), + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -164,7 +164,7 @@ static const struct pad_config override_gpio_table[] = { /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), + PAD_CFG_GPO(GPP_H20, 0, DEEP), /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ @@ -231,8 +231,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), diff --git a/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc index c2abb9ef0d..37e4c227f5 100644 --- a/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL -SPD_SOURCES += spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index c32b80e9ec..f8dcd58cc2 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -1,6 +1,50 @@ chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + device domain 0 on - device pci 15.0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}, + [1] = {.target = DPTF_TEMP_SENSOR_0, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [2] = {.target = DPTF_TEMP_SENSOR_1, + .thresholds = {TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}, + [3] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}, + [4] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(53, 90), + TEMP_PCT(50, 69), + TEMP_PCT(48, 56), + TEMP_PCT(45, 46), + TEMP_PCT(42, 36),}}}" + device generic 0 on end + end + end # DPTF 0x9A03 + device ref ipu on end # IPU 0x9A19 + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -37,7 +81,7 @@ chip soc/intel/tigerlake end end end - device pci 15.1 on + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -45,10 +89,16 @@ chip soc/intel/tigerlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + # Parameter T3 >= 10ms register "generic.reset_delay_ms" = "120" + # Parameter T2 >= 1ms register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + # Parameter T1 >= 10ms register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 14 on end @@ -67,8 +117,21 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_B3 is the IRQ source, and GPP_E1 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" + register "key.wake_gpe" = "GPE0_DW2_01" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -99,8 +162,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -109,8 +172,8 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.3 on + end + device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" @@ -140,7 +203,7 @@ chip soc/intel/tigerlake end end end - device pci 1f.2 hidden + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -156,10 +219,23 @@ chip soc/intel/tigerlake register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 on + probe DB_USB USB4_GEN2 + probe DB_USB USB3_ACTIVE + probe DB_USB USB4_GEN3 + probe DB_USB USB3_NO_A + end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU & HSL follow CC + device generic 1 on + probe DB_USB USB3_PASSIVE + end end end end - end # PMC + end end end diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index 13269db5ec..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -2,4 +2,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index a460ffff8f..b5d070baf0 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -18,10 +18,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ @@ -29,8 +25,8 @@ static const struct pad_config override_gpio_table[] = { /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC(TP18) */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B5 : ISH_I2C0_CVF_SDA */ @@ -58,20 +54,20 @@ static const struct pad_config override_gpio_table[] = { /* C0 : SMBCLK ==> EN_PP3300_WLAN */ PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> EN_USB_CAM_PWR */ - PAD_CFG_GPO(GPP_C1, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), /* C3 : SML0CLK ==> USB4_SMB_SCL */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* C4 : SML0DATA ==> USB4_SMB_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C5 : SML0ALERT# ==> NC(TP93) */ + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ PAD_NC(GPP_C5, DN_20K), - /* C7 : SML1DATA ==> EN_USI_CHARGE */ + /* C7 : SML1DATA ==> EN_PP5000_PEN */ PAD_CFG_GPO(GPP_C7, 1, DEEP), /* C10 : UART0_RTS# ==> USI_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ @@ -87,6 +83,16 @@ static const struct pad_config override_gpio_table[] = { /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ @@ -107,8 +113,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* D17 : ISH_GP4 ==> EN_CVF_PWR */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), @@ -117,21 +123,19 @@ static const struct pad_config override_gpio_table[] = { /* E3 : CPU_GP0 ==> USI_REPORT_EN */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E7 : CPU_GP1 ==> USI_INT */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), /* E8 : SPI1_CS1# ==> SLP_S0IX */ PAD_CFG_GPO(GPP_E8, 0, DEEP), - /* E10 : SPI1_CS# ==> NC(TP94508) */ - PAD_NC(GPP_E10, NONE), /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E11, NONE, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), - /* E13 : SPI1_MOSI_IO0 ==> NC(TP94507) */ - PAD_NC(GPP_E13, NONE), + /* E12 : SPI1_MISO_IO1 ==> PEN_OC_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ - PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP), + PAD_CFG_GPO(GPP_E17, 1, DEEP), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), @@ -143,10 +147,16 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> SAR0_INT_L */ PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ @@ -164,9 +174,13 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), - /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), @@ -174,8 +188,14 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */ + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), @@ -222,6 +242,8 @@ static const struct pad_config early_gpio_table[] = { /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ @@ -240,8 +262,8 @@ static const struct pad_config early_gpio_table[] = { /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), - /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_E12, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c new file mode 100644 index 0000000000..40b108660d --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct lpddr4x_cfg voxel_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &voxel_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc index d18a906b34..f40fba6751 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/memory/Makefile.inc @@ -2,6 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR -SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0e38..d7a265b010 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,6 +1,70 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "tcc_offset" = "5" # TCC of 95 + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on - device pci 15.0 on + device ref dptf on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(94, 100),}}, + [1] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(64, 100), + TEMP_PCT(60, 90), + TEMP_PCT(56, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end + device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" register "name" = ""RT58"" @@ -32,8 +96,8 @@ chip soc/intel/tigerlake device i2c 32 on end end - end # I2C #0 0xA0E8 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -63,8 +127,22 @@ chip soc/intel/tigerlake register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end # I2C1 0xA0E9 - device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + end + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" @@ -95,8 +173,8 @@ chip soc/intel/tigerlake register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end - end # I2C2 0xA0EA - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -105,8 +183,8 @@ chip soc/intel/tigerlake register "probed" = "1" device i2c 15 on end end - end # I2C5 0xA0C6 - device pci 1f.2 hidden + end + device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux @@ -127,6 +205,6 @@ chip soc/intel/tigerlake end end end - end # PMC + end end end diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 75b3e01345..c4f6bf73c4 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO + select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select VGA_BIOS select BOARD_ROMSIZE_KB_16384 select DRIVERS_AMD_I2S_MACHINE_DEV @@ -69,6 +70,7 @@ config VARIANT_DIR default "berknip" if BOARD_GOOGLE_BERKNIP default "vilboz" if BOARD_GOOGLE_VILBOZ default "woomax" if BOARD_GOOGLE_WOOMAX + default "dirinboz" if BOARD_GOOGLE_DIRINBOZ config MAINBOARD_PART_NUMBER string @@ -79,6 +81,7 @@ config MAINBOARD_PART_NUMBER default "Berknip" if BOARD_GOOGLE_BERKNIP default "Vilboz" if BOARD_GOOGLE_VILBOZ default "Woomax" if BOARD_GOOGLE_WOOMAX + default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ config DEVICETREE string @@ -127,7 +130,7 @@ config DRIVER_TPM_I2C_ADDR config PICASSO_FW_A_POSITION hex - default 0xFF031040 + default 0xFF012040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_A region. This is the @@ -135,24 +138,12 @@ config PICASSO_FW_A_POSITION config PICASSO_FW_B_POSITION hex - default 0xFF3CF040 + default 0xFF312040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_B region. This is the start of the RW-A region + 64 bytes for the cbfs header. -config VARIANT_HAS_FW_CONFIG - bool - help - Honor FW_CONFIG in CBI. - -config VARIANT_BOARD_VER_FW_CONFIG_VALID - int - default 256 - depends on VARIANT_HAS_FW_CONFIG - help - Which board version did FW_CONFIG become valid in CBI. - config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS bool default y if BOARD_GOOGLE_TREMBYLE @@ -167,6 +158,34 @@ config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS longer has to support pre-v3 schematics, `default y` entry for it can be dropped. +config VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + bool + default y if BOARD_GOOGLE_TREMBYLE + default y if BOARD_GOOGLE_EZKINIL + default y if BOARD_GOOGLE_MORPHIUS + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_DALBOZ + default y if BOARD_GOOGLE_WOOMAX + default y if BOARD_GOOGLE_VILBOZ + default y if BOARD_GOOGLE_DIRINBOZ + default n + +config VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS + int + depends on VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS + default 4 if BOARD_GOOGLE_TREMBYLE + default 3 if BOARD_GOOGLE_EZKINIL + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 3 if BOARD_GOOGLE_DALBOZ + default 1 if BOARD_GOOGLE_WOOMAX + default 2 if BOARD_GOOGLE_VILBOZ + default 2 if BOARD_GOOGLE_DIRINBOZ + default 256 + help + Minimum board version where the variant starts supporting + v3.6+ version of reference schematics. + config VARIANT_MIN_BOARD_ID_V3_SCHEMATICS int depends on VARIANT_SUPPORTS_PRE_V3_SCHEMATICS @@ -224,4 +243,27 @@ config VBOOT_STARTS_IN_BOOTBLOCK bootblock. This implies that a static VBOOT2_WORK() buffer must be allocated in memlayout. +config EFS_SPI_READ_MODE + int + default 0 if EM100 # Normal read mode + default 2 # Dual IO (1-1-2) + +config EFS_SPI_SPEED + int + default 3 if EM100 # 16.66 MHz + default 0 # 66.66 MHz + +config EFS_SPI_MICRON_FLAG + int + default 0 + +config CHROMEOS_WIFI_SAR + bool + default y if CHROMEOS + select DRIVERS_WIFI_GENERIC + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select GEO_SAR_ENABLE + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 801c1b7b39..6f9a90c682 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -27,3 +27,7 @@ config BOARD_GOOGLE_BERKNIP config BOARD_GOOGLE_WOOMAX bool "-> Woomax" select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_DIRINBOZ + bool "-> Dirinboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 90cd2d7f90..7c2b95b6ec 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,37 +1,32 @@ -FLASH@0xFF000000 0x1000000 { - SI_BIOS@0x0 0x1000000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RW_MRC_CACHE@0x0 0x10000 - MRC_CACHE_HOLE@0x10000 0x11000 +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 } - RW_SECTION_A@0x21000 0x39E000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x38DFC0 - RW_FWID_A@0x39DFC0 0x40 + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 } - RW_SECTION_B@0x3BF000 0x39E000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x38DFC0 - RW_FWID_B@0x39DFC0 0x40 + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K } - RW_ELOG(PRESERVE)@0x75D000 0x4000 - RW_SHARED@0x761000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x765000 0x2000 - RW_NVRAM(PRESERVE)@0x767000 0x5000 - RW_UNUSED@0x76C000 0x14000 - SMMSTORE(PRESERVE)@0x780000 0x20000 - RW_LEGACY(CBFS)@0x7A0000 0x460000 - WP_RO@0xC00000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3FC000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7C0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x38B000 + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) } } } diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c index d770d27040..f4f441c7a1 100644 --- a/src/mainboard/google/zork/ec.c +++ b/src/mainboard/google/zork/ec.c @@ -11,6 +11,7 @@ void mainboard_ec_init(void) .log_events = MAINBOARD_EC_LOG_EVENTS, .sci_events = MAINBOARD_EC_SCI_EVENTS, .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s3_device_events = MAINBOARD_EC_S3_DEVICE_EVENTS, .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index f3ef5c5a98..f0d9a2869d 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -135,6 +135,8 @@ static void mainboard_configure_gpios(void) static void mainboard_devtree_update(void) { variant_audio_update(); + variant_bluetooth_update(); + variant_touchscreen_update(); variant_devtree_update(); } @@ -165,12 +167,12 @@ static void mainboard_init(void *chip_info) gpe_configure_sci(gpes, num); } -void mainboard_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - variant_get_pcie_ddi_descriptors(pcie_descs, pcie_num, ddi_descs, ddi_num); + variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num); } /************************************************* @@ -186,25 +188,12 @@ static void zork_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } -static const struct soc_amd_gpio gpio_set_bl[] = { - PAD_GPO(GPIO_85, LOW), -}; - -static void reset_backlight_gpio(void *unused) -{ - printk(BIOS_DEBUG, "Reset backlight GPIO\n"); - /* Re-Enable backlight - GPIO 85 active low */ - /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ - program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ -} - static void mainboard_final(void *chip_info) { struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); - reset_backlight_gpio(NULL); if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; @@ -229,5 +218,3 @@ __weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) *size = 0; return NULL; } - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 12a3b64c20..6ef2704de1 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -33,5 +33,11 @@ int mainboard_smi_apmc(u8 apmc) if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + /* Temporary fix - Needs to go into ACPI instead */ + /* Turn on the backlight when we go to ACPI mode */ + if (apmc == APM_CNT_ACPI_ENABLE) + gpio_set(GPIO_85, 0); + return 0; } diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index 7ae89df525..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B4 EF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex deleted file mode 100644 index 8d9fd4d9bf..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 EF F6 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex deleted file mode 100644 index af9ba32181..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 10 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 E7 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex deleted file mode 100644 index 56677fa37a..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 85 21 10 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 55 24 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index cc1ca7384b..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B3 E1 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex deleted file mode 100644 index 3b1a73e7b8..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 3C 41 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex deleted file mode 100644 index 07342ab8fc..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 4C 24 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-template.spd.hex b/src/mainboard/google/zork/spd/DDR4-template.spd.hex deleted file mode 100644 index 6198f3daf1..0000000000 --- a/src/mainboard/google/zork/spd/DDR4-template.spd.hex +++ /dev/null @@ -1,336 +0,0 @@ -# Generic DDR4 SPD template -# Fields that are not required should be set to zero -# CRC will be calculated when generating SPDs from this template, so no need -# to update here - -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization -01 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -00 - -# Connector to SDRAM Bit Mapping (DQ4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ8-11) -00 - -# Connector to SDRAM Bit Mapping (DQ12-15) -00 - -# Connector to SDRAM Bit Mapping (DQ16-19) -00 - -# Connector to SDRAM Bit Mapping (DQ20-23) -00 - -# Connector to SDRAM Bit Mapping (DQ24-27) -00 - -# Connector to SDRAM Bit Mapping (DQ28-31) -00 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -00 - -# Connector to SDRAM Bit Mapping (DQ36-39) -00 - -# Connector to SDRAM Bit Mapping (DQ40-43) -00 - -# Connector to SDRAM Bit Mapping (DQ44-47) -00 - -# Connector to SDRAM Bit Mapping (DQ48-51) -00 - -# Connector to SDRAM Bit Mapping (DQ52-55) -00 - -# Connector to SDRAM Bit Mapping (DQ56-59) -00 - -# Connector to SDRAM Bit Mapping (DQ60-63) -00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (blank) -00 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -00 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -00 - -# RC Extension, Module Nominal Height -00 - -# Module Maximum Thickness -00 - -# Reference Raw Card Used -00 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -00 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (blank) -00 - -# Module Manufacturer's ID Code, MSB (blank) -00 - -# Module Manufacturing Location (blank) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (blank) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (blank) -00 - -# DRAM Manufacturer's ID code, MSB (blank) -00 - -# DRAM Stepping (Undefined) -00 - -# Module Manufacturer's Specific Data (blank) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index e401fa6fdc..1042d9101d 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -3,27 +3,22 @@ # This directory SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# TODO: Remove channel suffix when b:141434940 is fixed -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001 -APCB_SOURCES += empty # 0b0010 -APCB_SOURCES += empty # 0b0011 -APCB_SOURCES += empty # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/mainboard/google/zork/spd/ddr4-spd-1.hex b/src/mainboard/google/zork/spd/ddr4-spd-1.hex new file mode 100644 index 0000000000..32d141f21f --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-1.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-2.hex b/src/mainboard/google/zork/spd/ddr4-spd-2.hex new file mode 100644 index 0000000000..85b203599b --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-2.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-3.hex b/src/mainboard/google/zork/spd/ddr4-spd-3.hex new file mode 100644 index 0000000000..d2869eab1b --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-3.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-4.hex b/src/mainboard/google/zork/spd/ddr4-spd-4.hex new file mode 100644 index 0000000000..b6769928da --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-4.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 FC 3F 00 00 6D 6D 6D 11 00 6D F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-5.hex b/src/mainboard/google/zork/spd/ddr4-spd-5.hex new file mode 100644 index 0000000000..d72bf1ed05 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-5.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 A8 18 2B 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 B5 00 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-6.hex b/src/mainboard/google/zork/spd/ddr4-spd-6.hex new file mode 100644 index 0000000000..71cfff96d5 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-6.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-7.hex b/src/mainboard/google/zork/spd/ddr4-spd-7.hex new file mode 100644 index 0000000000..7f92cd8529 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-7.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-8.hex b/src/mainboard/google/zork/spd/ddr4-spd-8.hex new file mode 100644 index 0000000000..aca688e99d --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-8.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-empty.hex b/src/mainboard/google/zork/spd/ddr4-spd-empty.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt new file mode 100644 index 0000000000..202f1734d4 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -0,0 +1,15 @@ +H5AN8G6NDJR-XNC,ddr4-spd-1.hex +MT40A512M16TB-062E:J,ddr4-spd-1.hex +H5ANAG6NCMR-XNC,ddr4-spd-2.hex +HMA851S6CJR6N-VK,ddr4-spd-3.hex +K4A8G165WC-BCTD,ddr4-spd-3.hex +H5AN8G6NCJR-VKC,ddr4-spd-3.hex +MT40A1G16KNR-075:E,ddr4-spd-4.hex +K4AAG165WB-MCTD,ddr4-spd-5.hex +H5ANAG6NCMR-VKC,ddr4-spd-6.hex +K4A8G165WC-BCWE,ddr4-spd-1.hex +MT40A1G16KD-062E:E,ddr4-spd-7.hex +K4AAG165WA-BCWE,ddr4-spd-7.hex +H5AN8G6NCJR-XNC,ddr4-spd-1.hex +K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex diff --git a/src/mainboard/google/zork/spd/empty.spd.hex b/src/mainboard/google/zork/spd/empty.spd.hex deleted file mode 100644 index 0d22dd0cf0..0000000000 --- a/src/mainboard/google/zork/spd/empty.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -#Empty SPD - placeholder file -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex deleted file mode 100644 index 1c5e87f9d4..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx16) -02 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -87 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -2E - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (C0) -02 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -C0 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -E2 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (H5AN8G6NCJR-VKC ) -48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20 -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex deleted file mode 100644 index 144c8e3f08..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5AN8G6NDJR-XNC -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 -0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 -4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex deleted file mode 100644 index e75e4c12d9..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5ANAG6NCMR-VKC -23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 -36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex deleted file mode 100644 index 3cfb32cfc8..0000000000 --- a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Hynix H5ANAG6NCMR-XNC -23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 -4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex deleted file mode 100644 index 7ad9466cf4..0000000000 --- a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (Flipchip SDP) -00 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx16) -02 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -87 - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -2E - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (C0) -02 - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -C0 - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -E2 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (HMA851S6CJR6N-VK ) -48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex deleted file mode 100644 index ff166d6e75..0000000000 --- a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex +++ /dev/null @@ -1,331 +0,0 @@ -# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) -23 - -# SPD Revision (Rev. 1.1) -11 - -# Key Byte / DRAM Device Type (DDR4 SDRAM) -0C - -# Key Byte / Module Type (nECC SO-DIMM) -03 - -# SDRAM Density and Banks (2BG/4BK/8Gb) -45 - -# SDRAM Addressing (16/10) -21 - -# Primary SDRAM Package Type (DDP) -91 - -# SDRAM Optional Features (Unlimited MAC) -08 - -# SDRAM Thermal and Refresh Options (Reserved) -00 - -# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) -60 - -# Secondary SDRAM Package Type -00 - -# Module Nominal Volatage, VDD (1.2V) -03 - -# Module Organization (1Rx8) -01 - -# Module Memory Bus Width (LP/x64) -03 - -# Module Thermal Sensor (Termal sensor not incorporated) -00 - -# Extended Module Type (Reserved) -00 - -# Reserved -00 - -# Timebases (MTB : 125ps, FTB : 1ps) -00 - -# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) -06 - -# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) -0D - -# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) -F8 - -# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) -3F - -# CAS Latencies Supported, Third Byte -00 - -# CAS Latencies Supported, Fourth Byte -00 - -# Minimum CAS Latency Time (tAAmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) -6E - -# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) -6E - -# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) -11 - -# tRASmin, Least Significant Byte (32ns) -00 - -# tRCmin, Least Significant Byte (45.75ns) -6E - -# tRFC1min, LSB (350ns) -F0 - -# tRFC1min, MSB (350ns) -0A - -# tRFC2min, LSB (260ns) -20 - -# tRFC2min, MSB (260ns) -08 - -# tRFC4min, LSB (160ns) -00 - -# tRFC4min, MSB (160ns) -05 - -# Upper Nibble for tFAW (30ns) -00 - -# tFAWmin LSB (30ns) -F0 - -# tRRD_Smin (5.3ns) -2B - -# tRRD_L min (6.40ns) -34 - -# tCCD_Lmin, same bank group (5ns) -28 - -# tWRmin Upper Nibbles (15ns) -00 - -# tWRmin (15ns) -78 - -# tWTRmin Upper Nibbles (2.5ns/7.5ns) -00 - -# tWTR_Smin (2.5ns) -14 - -# tWTR_Lmin (7.5ns) -3C - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Connector to SDRAM Bit Mapping (DQ0-3) -16 - -# Connector to SDRAM Bit Mapping (DQ4-7) -36 - -# Connector to SDRAM Bit Mapping (DQ8-11) -0B - -# Connector to SDRAM Bit Mapping (DQ12-15) -35 - -# Connector to SDRAM Bit Mapping (DQ16-19) -16 - -# Connector to SDRAM Bit Mapping (DQ20-23) -36 - -# Connector to SDRAM Bit Mapping (DQ24-27) -0B - -# Connector to SDRAM Bit Mapping (DQ28-31) -35 - -# Connector to SDRAM Bit Mapping (CB0-3) -00 - -# Connector to SDRAM Bit Mapping (CB4-7) -00 - -# Connector to SDRAM Bit Mapping (DQ32-35) -16 - -# Connector to SDRAM Bit Mapping (DQ36-39) -36 - -# Connector to SDRAM Bit Mapping (DQ40-43) -0B - -# Connector to SDRAM Bit Mapping (DQ44-47) -35 - -# Connector to SDRAM Bit Mapping (DQ48-51) -16 - -# Connector to SDRAM Bit Mapping (DQ52-55) -36 - -# Connector to SDRAM Bit Mapping (DQ56-59) -0B - -# Connector to SDRAM Bit Mapping (DQ60-63) -35 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 - -# Fine offset for tCCD_Lmin, same bank group (5ns) -00 - -# tRRD_L min offset (6.40ns) -9C - -# tRRD_Smin offset (5.3ns) -B5 - -# Fine offset for tRCmin (45.75ns) -00 - -# Fine offset for tRPmin (13.75ns) -00 - -# Fine offset for tRCDmin (13.75ns) -00 - -# Fine offset for tAAmin (13.75ns) -00 - -# Fine offset for tCKAVGmax (1.6ns) -E7 - -# Fine offset for tCKAVGmin (0.75ns) -00 - -# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) -FD - -# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) -EE - -# RC Extention, Module Nominal Height (30.00) -0F - -# Module Maximum Thickness (1.0/1.2) -01 - -# Reference Raw Card Used (ZZ0) -1F - -# Address Mapping from Edge Connector to DRAM (Standard) -00 - -# Reserved -00 00 00 00 00 00 00 00 - -# Reserved (Must be coded as 0x00) -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 - -# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) -7D - -# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) -21 - -# Reserved -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# Module Manufacturer's ID Code, LSB (SK hynix) -80 - -# Module Manufacturer's ID Code, MSB (SK hynix) -AD - -# Module Manufacturing Location (SK hynix (Icheon)) -01 - -# Module Manufacturing Date (Variable) -00 - -# Module Manufacturing Date (Variable) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Serial Number (Undefined) -00 - -# Module Part Number (HMAA1GS6CMR6N-VK ) -48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B -20 20 20 20 - -# Module Revision Code (Revision 0) -00 - -# DRAM Manufacturer's ID code, LSB (SK hynix) -80 - -# DRAM Manufacturer's ID code, MSB (SK hynix) -AD - -# DRAM Stepping (Undefined) -FF - -# Module Manufacturer's Specific Data -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 DD - -# Reserved -00 00 - -# End User Programmable -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex deleted file mode 100644 index 17778473af..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Micron MT40A1G16KD-062E:E -23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 -31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C -45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex deleted file mode 100644 index 988ea54b23..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Micron MT40A1G16KNR-075:E -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60 -0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 -31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C -45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex deleted file mode 100644 index 67640fe849..0000000000 --- a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# MT40A512M16TB-062E:J -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 -0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 -32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex deleted file mode 100644 index e16d2f729b..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4A8G165WC-BCTD -23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e -0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 -35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex deleted file mode 100644 index 4fb1561c6a..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4A8G165WC-BCWE -23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 -00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 -16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 -0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 -35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex deleted file mode 100644 index ede001a4d5..0000000000 --- a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex +++ /dev/null @@ -1,33 +0,0 @@ -# Samsung K4AAG165WB-MCTD -23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A -20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B -34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index c9e3657f4b..c8d57ff9b5 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -44,11 +44,15 @@ endif #($(CONFIG_USE_OEM_BIN),y) # GPIO_NUMBER: FCH GPIO number # GPIO_IO_MUX: Value write to IOMUX to configure this GPIO # GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. +# Trembyle based boards select 1 or 2 channels based on AGPIO84 +# Dalboz based boards only support 1 channel ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) APCB_BOARD_ID_GPIO0 = 121 1 0 APCB_BOARD_ID_GPIO1 = 120 1 0 APCB_BOARD_ID_GPIO2 = 131 3 0 APCB_BOARD_ID_GPIO3 = 116 1 0 +APCB_POPULATE_2ND_CHANNEL = true else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y) APCB_BOARD_ID_GPIO0 = 132 1 0 APCB_BOARD_ID_GPIO1 = 90 1 0 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index e355b5b14a..cbb812d220 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -3,19 +3,12 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_REMOTE_POWER_ON" + # See table 5-34 ACPI 6.3 spec + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) @@ -47,12 +40,24 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" - register "xhci0_force_gen1" = "0" + register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default - register "usb_2_port_0_tune_params" = "{ + register "usb_2_port_tune_params[0]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -65,7 +70,7 @@ chip soc/amd/picasso }" # Controller0 Port1 Default - register "usb_2_port_1_tune_params" = "{ + register "usb_2_port_tune_params[1]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -78,7 +83,7 @@ chip soc/amd/picasso }" # Controller0 Port2 Default - register "usb_2_port_2_tune_params" = "{ + register "usb_2_port_tune_params[2]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -91,7 +96,7 @@ chip soc/amd/picasso }" # Controller0 Port3 Default - register "usb_2_port_3_tune_params" = "{ + register "usb_2_port_tune_params[3]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -104,7 +109,7 @@ chip soc/amd/picasso }" # Controller1 Port0 Default - register "usb_2_port_4_tune_params" = "{ + register "usb_2_port_tune_params[4]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -117,7 +122,7 @@ chip soc/amd/picasso }" # Controller1 Port1 Default - register "usb_2_port_5_tune_params" = "{ + register "usb_2_port_tune_params[5]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -129,6 +134,14 @@ chip soc/amd/picasso .tx_res_tune = 0x01, }" + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_33M, /* MHz */ @@ -177,6 +190,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end @@ -234,6 +256,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" device usb 2.5 on end end chip drivers/usb/acpi @@ -279,11 +302,11 @@ chip soc/amd/picasso device generic 0.0 on end end end # Audio - device pci 0.6 on end # HDA + device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Internal GPP Bridge 0 to Bus B - device pci 0.0 on end # AHCI + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI end device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge @@ -298,11 +321,14 @@ chip soc/amd/picasso register "name" = ""RT58"" register "uid" = "1" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" - register "property_count" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" device i2c 1a on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 283e7a07a4..7288d6e32d 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -3,19 +3,12 @@ chip soc/amd/picasso # Set FADT Configuration register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_REMOTE_POWER_ON" + # See table 5-34 ACPI 6.3 spec + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acp_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) @@ -47,12 +40,24 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" - register "xhci0_force_gen1" = "0" + register "has_usb2_phy_tune_params" = "1" # Controller0 Port0 Default - register "usb_2_port_0_tune_params" = "{ + register "usb_2_port_tune_params[0]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -65,7 +70,7 @@ chip soc/amd/picasso }" # Controller0 Port1 Default - register "usb_2_port_1_tune_params" = "{ + register "usb_2_port_tune_params[1]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -78,7 +83,7 @@ chip soc/amd/picasso }" # Controller0 Port2 Default - register "usb_2_port_2_tune_params" = "{ + register "usb_2_port_tune_params[2]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -91,7 +96,7 @@ chip soc/amd/picasso }" # Controller0 Port3 Default - register "usb_2_port_3_tune_params" = "{ + register "usb_2_port_tune_params[3]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -104,7 +109,7 @@ chip soc/amd/picasso }" # Controller1 Port0 Default - register "usb_2_port_4_tune_params" = "{ + register "usb_2_port_tune_params[4]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -117,7 +122,7 @@ chip soc/amd/picasso }" # Controller1 Port1 Default - register "usb_2_port_5_tune_params" = "{ + register "usb_2_port_tune_params[5]" = "{ .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, @@ -138,6 +143,14 @@ chip soc/amd/picasso .read_mode = SPI_READ_MODE_DUAL122, }" + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + # eSPI Configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, @@ -177,6 +190,15 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end @@ -262,6 +284,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.5 on end end end @@ -281,6 +304,7 @@ chip soc/amd/picasso chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.1 on end end chip drivers/usb/acpi @@ -307,11 +331,11 @@ chip soc/amd/picasso device generic 0.0 on end end end # Audio - device pci 0.6 on end # HDA + device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Internal GPP Bridge 0 to Bus B - device pci 0.0 on end # AHCI + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI end device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge @@ -326,11 +350,14 @@ chip soc/amd/picasso register "name" = ""RT58"" register "uid" = "1" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" - register "property_count" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_29)" + register "property_count" = "2" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" device i2c 1a on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index b0037090c7..4be866d6bc 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -4,66 +4,64 @@ #include #include -void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); } -static const fsp_pcie_descriptor pcie_descriptors[] = { +static const fsp_dxio_descriptor dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = NVME_START_LANE, - .end_lane = NVME_END_LANE, + .start_logical_lane = 4, + .end_logical_lane = 5, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ2, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = WLAN_START_LANE, - .end_lane = WLAN_END_LANE, + .start_logical_lane = 0, + .end_logical_lane = 0, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = SD_START_LANE, - .end_lane = SD_END_LANE, + .start_logical_lane = 1, + .end_logical_lane = 1, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) { - *num = ARRAY_SIZE(pcie_descriptors); - return pcie_descriptors; + *num = ARRAY_SIZE(dxio_descriptors); + return dxio_descriptors; } const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index df42f6b87e..49d8ade7f4 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -5,12 +5,12 @@ #include #include -void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); } @@ -18,109 +18,106 @@ void __weak variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_de * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. * Those parts need to be configured as Type 2. */ -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 3, + .start_logical_lane = 0, + .end_logical_lane = 3, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, + .clk_req = CLK_REQ4, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = NVME_START_LANE, - .end_lane = NVME_END_LANE, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ4, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = WLAN_START_LANE, - .end_lane = WLAN_END_LANE, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, - .clk_pm_support = true, + .clk_req = CLK_REQ0, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_lane = SD_START_LANE, - .end_lane = SD_END_LANE, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) { /* Type 2 or Type 1 fused like Type 2. */ if (soc_is_reduced_io_sku()) { - *num = ARRAY_SIZE(dali_pcie_descriptors); - return dali_pcie_descriptors; + *num = ARRAY_SIZE(dali_dxio_descriptors); + return dali_dxio_descriptors; } else { /* Type 1 */ - *num = ARRAY_SIZE(pco_pcie_descriptors); - return pco_pcie_descriptors; + *num = ARRAY_SIZE(pco_dxio_descriptors); + return pco_dxio_descriptors; } } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index a4e86487bd..0b658a4129 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -8,17 +8,17 @@ static const struct soc_amd_gpio early_gpio_table[] = { /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* PCIE_RST0_L - Fixed timings */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L (may be unused) */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), /* UART0_RXD - DEBUG */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* UART0_TXD - DEBUG */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 3ab3e10add..696c733189 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -16,6 +16,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* PCIE_WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ @@ -34,12 +36,17 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), + /* GPIO_13 - GPIO_15: Not available */ /* USB_OC0_L - USB C0/A0 */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), /* USB_OC1_L - USB C1 */ PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), /* WIFI_DISABLE */ PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* EMMC_CMD */ PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), /* EC_FCH_SCI_ODL */ @@ -48,30 +55,46 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* EC_FCH_WAKE_L */ PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* GPIO_27: Configured in bootblock. */ + /* GPIO_28: Not available */ + /* GPIO_29: Handled in bootblock for wifi power/reset control. */ + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* TP */ - PAD_NC(GPIO_32), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, LOW), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ /* DMIC_SEL */ /* * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash * access will be very slow. */ PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET */ - PAD_GPO(GPIO_68, LOW), - /* RAM ID 3*/ + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* RAM ID 3 */ PAD_GPI(GPIO_69, PULL_NONE), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ /* EMMC_DATA4 */ PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), /* EMMC_DATA6 */ PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, HIGH), - /* UNUSED */ - PAD_GPO(GPIO_84, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* HP_INT_ODL */ + PAD_GPI(GPIO_84, PULL_NONE), /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ PAD_GPO(GPIO_85, HIGH), /* RAM ID 2 */ @@ -80,12 +103,15 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* EN_DEV_BEEP_L */ - PAD_GPO(GPIO_89, HIGH), + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), /* RAM ID 1 */ PAD_GPI(GPIO_90, PULL_NONE), - /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ /* EMMC_DATA0 */ PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), /* EMMC_DATA1 */ @@ -94,33 +120,46 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), /* EMMC_DATA3 */ PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), /* EMMC_DS */ PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ /* I2C2_SCL - USI/Touchpad */ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), /* I2C2_SDA - USI/Touchpad */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_128: Not available */ /* KBRST_L */ PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* GPIO_130 - GPIO_131: Not available */ /* RAM ID 0 */ PAD_GPI(GPIO_132, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* BIOS_FLASH_WP_ODL */ PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET */ - PAD_GPO(GPIO_140, HIGH), + /* USI_RESET_L */ + PAD_GPO(GPIO_140, LOW), /* USB_HUB_RST_L */ PAD_GPO(GPIO_141, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), /* BT_DISABLE */ PAD_GPO(GPIO_143, LOW), - /* - * USI_REPORT_EN - TODO: Driver resets this later. - * Do we want it high or low initially? - */ - PAD_GPO(GPIO_144, HIGH), + /* USI_REPORT_EN */ + PAD_GPO(GPIO_144, LOW), }; const __weak diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index c2d290ad91..549cc589bb 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -16,12 +16,14 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* PCIE_WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ - PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW), + PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), /* I2S_SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S_LRCLK - Bit banged in depthcharge */ @@ -38,12 +40,17 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_13, HIGH), /* BT_DISABLE */ PAD_GPO(GPIO_14, LOW), + /* GPIO_15: Not available */ /* USB_OC0_L - USB C0 + USB A0 */ PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), /* USB_OC1_L - USB C1 + USB A1 */ PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), /* WIFI_DISABLE */ PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* EMMC_CMD */ PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), /* EC_FCH_SCI_ODL */ @@ -52,40 +59,65 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* EC_FCH_WAKE_L */ PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L (unused) */ + PAD_NC(GPIO_27), + /* GPIO_28: Not available */ + /* GPIO_29: HP_INT_ODL */ + PAD_GPI(GPIO_29, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), /* EN_PWR_FP */ PAD_GPO(GPIO_32, HIGH), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ /* DMIC SEL */ /* * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash * access will be very slow. */ PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET */ - PAD_GPO(GPIO_68, LOW), + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), /* FPMCU_BOOT0 - TODO: Check this */ PAD_GPO(GPIO_69, LOW), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ /* EMMC_DATA4 */ PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), /* EMMC_DATA6 */ PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), /* EN_PWR_CAMERA */ PAD_GPO(GPIO_76, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ PAD_GPO(GPIO_85, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* EN_DEV_BEEP_L */ - PAD_GPO(GPIO_89, HIGH), - /* Testpoint */ - PAD_NC(GPIO_90), - /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, LOW), + /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ /* EMMC_DATA0 */ PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), /* EMMC_DATA1 */ @@ -94,31 +126,54 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), /* EMMC_DATA3 */ PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), /* EMMC_DS */ PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ /* I2C2_SCL - USI/Touchpad */ PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), /* I2C2_SDA - USI/Touchpad */ PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* GPIO_117 - GPIO_119: Not available */ + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* GPIO_122 - GPIO_128: Not available */ /* KBRST_L */ PAD_NF(GPIO_129, KBRST_L, PULL_NONE), /* EC_IN_RW_OD */ PAD_GPI(GPIO_130, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* BIOS_FLASH_WP_ODL */ PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET */ - PAD_GPO(GPIO_140, HIGH), + /* USI_RESET_L */ + PAD_GPO(GPIO_140, LOW), /* UART1_RXD - FPMCU */ PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), /* UART1_TXD - FPMCU */ PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), /* USI_REPORT_EN */ - /* TODO: Driver resets this later. Do we want it high or low initially? */ - PAD_GPO(GPIO_144, HIGH), + PAD_GPO(GPIO_144, LOW), }; const __weak diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 0a1cf5ccd1..d95ab823f6 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -48,36 +48,10 @@ enum { FW_CONFIG_SHIFT_FAN = 27, }; -int variant_fw_config_valid(void) -{ - static uint32_t board_version; - const uint32_t bv_valid = CONFIG_VARIANT_BOARD_VER_FW_CONFIG_VALID; - - if (!CONFIG(VARIANT_HAS_FW_CONFIG)) - return 0; - - /* Fast path for non-zero board version. */ - if (board_version >= bv_valid) - return 1; - - if (google_chromeec_cbi_get_board_version(&board_version)) { - printk(BIOS_ERR, "Unable to obtain board version for FW_CONFIG\n"); - return 0; - } - - if (board_version >= bv_valid) - return 1; - - return 0; -} - static int get_fw_config(uint32_t *val) { static uint32_t known_value; - if (!variant_fw_config_valid()) - return -1; - if (known_value) { *val = known_value; return 0; @@ -130,6 +104,31 @@ bool variant_uses_v3_schematics(void) return true; } +bool variant_uses_v3_6_schematics(void) +{ + uint32_t board_version; + + if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS)) + return true; + + if (google_chromeec_cbi_get_board_version(&board_version)) + return false; + + if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS) + return false; + + return true; +} + +/* + * pre-v3.6, CODEC_GPI was used as headphone jack interrupt. + * Starting v3.6 this was changed to a separate GPIO. + */ +bool variant_uses_codec_gpi(void) +{ + return !variant_uses_v3_6_schematics(); +} + bool variant_has_active_low_wifi_power(void) { uint32_t board_version; @@ -145,3 +144,8 @@ bool variant_has_active_low_wifi_power(void) return true; } + +int variant_get_daughterboard_id(void) +{ + return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index ff42989286..dc06a7843f 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -46,6 +46,9 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* EC device events to enable and log in S3 */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS 0 + /* Enable LID switch */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN EC_WAKE_GPI diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h index 84433e0622..389f0e832a 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -7,31 +7,10 @@ #include #include -#define WLAN_CLKREQ CLK_REQ0 -#define SD_CLKREQ CLK_REQ1 - -#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) -#define NVME_START_LANE 4 -#define NVME_END_LANE 5 -#define WLAN_START_LANE 0 -#define WLAN_END_LANE 0 -#define SD_START_LANE 1 -#define SD_END_LANE 1 -#else -#define NVME_START_LANE 0 -#define NVME_END_LANE 1 -#define WLAN_START_LANE 4 -#define WLAN_END_LANE 4 -#define SD_START_LANE 5 -#define SD_END_LANE 5 -#endif - #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) #define EC_IN_RW_OD GPIO_130 -#define NVME_CLKREQ CLK_REQ4 #else #define EC_IN_RW_OD GPIO_11 -#define NVME_CLKREQ CLK_REQ2 #endif /* SPI Write protect */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 90e8b04212..338b918623 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ @@ -35,25 +34,27 @@ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ void variant_audio_update(void); +/* Update bluetooth configuration in devicetree during ramstage. */ +void variant_bluetooth_update(void); +/* Update touchscreen configuration in devicetree during ramstage. */ +void variant_touchscreen_update(void); /* Configure PCIe GPIOs as per variant sequencing requirements. */ void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and * overrideable by the variant. */ -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); /* Provide the descriptors for the associated baseboard for the variant. These functions * can be used for obtaining the baseboard's descriptors if the variant followed the * baseboard. */ -const fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num); +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num); const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); /* Retrieve attributes from FW_CONFIG in CBI. */ -/* Return 1 if FW_CONFIG expected to be valid, else 0. */ -int variant_fw_config_valid(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_emmc(void); /* Return 0 if non-existent, 1 if present. */ @@ -64,7 +65,13 @@ int boot_is_factory_unprovisioned(void); /* Return true if variant uses v3 version of reference schematics. */ bool variant_uses_v3_schematics(void); +/* Return true if variant uses v3.6 version of reference schematics. */ +bool variant_uses_v3_6_schematics(void); +/* Return true if variant uses CODEC_GPI pin for headphone jack interrupt. */ +bool variant_uses_codec_gpi(void); /* Return true if variant has active low power enable fow WiFi. */ bool variant_has_active_low_wifi_power(void); +/* Return value of daughterboard ID */ +int variant_get_daughterboard_id(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 511d60d0b8..a9414b92e0 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -2,48 +2,261 @@ #include #include +#include +#include #include +#include +#include +#include #include #include +#include #include extern struct chip_operations drivers_amd_i2s_machine_dev_ops; +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_hid_ops; -void variant_audio_update(void) +static void update_hp_int_odl(void) { - const struct device *gpp_a_dev; - const struct device *acp_dev; - struct device *machine_dev = NULL; + static const struct device_path rt5682_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = LPC_DEVFN + }, + { + .type = DEVICE_PATH_PNP, + .pnp.port = 0xc09, + .pnp.device = 0x0 + }, + { + .type = DEVICE_PATH_GENERIC, + .generic.id = 0, + .generic.subid = 0 + }, + { + .type = DEVICE_PATH_I2C, + .i2c.device = 0x1a + } + }; + + const struct device *rt5682_dev; + struct drivers_i2c_generic_config *cfg; + struct acpi_gpio *gpio; + struct soc_amd_picasso_config *soc_cfg; + + if (!variant_uses_codec_gpi()) + return; + + rt5682_dev = find_dev_nested_path( + pci_root_bus(), rt5682_path, ARRAY_SIZE(rt5682_path)); + if (!rt5682_dev) { + printk(BIOS_ERR, "%s: Failed to find audio device\n", + __func__); + return; + } + + if (rt5682_dev->chip_ops != &drivers_i2c_generic_ops) { + printk(BIOS_ERR, "%s: Incorrect device found\n", __func__); + return; + } + + cfg = config_of(rt5682_dev); + gpio = &cfg->irq_gpio; + gpio->pins[0] = 62; + + /* + * When using CODEC_GPI for headphone jack interrupt, ACP_PME_EN and ACP_I2S_WAKE_EN + * need to be set to trigger I2S_WAKE event for headphone jack. + */ + soc_cfg = config_of_soc(); + soc_cfg->acp_i2s_wake_enable = 1; + soc_cfg->acp_pme_enable = 1; +} + +static void update_dmic_gpio(void) +{ + static const struct device_path acp_machine_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = AUDIO_DEVFN + }, + { + .type = DEVICE_PATH_GENERIC, + .generic.id = 0, + .generic.subid = 0 + } + }; + + const struct device *machine_dev; + struct drivers_amd_i2s_machine_dev_config *cfg; + struct acpi_gpio *gpio; if (variant_uses_v3_schematics()) return; - gpp_a_dev = pcidev_path_on_root(PCIE_GPP_A_DEVFN); - if (gpp_a_dev == NULL) + machine_dev = find_dev_nested_path( + pci_root_bus(), acp_machine_path, ARRAY_SIZE(acp_machine_path)); + if (!machine_dev) { + printk(BIOS_ERR, "%s: Failed to find ACP machine device\n", __func__); + return; + } + + if (machine_dev->chip_ops != &drivers_amd_i2s_machine_dev_ops) { + printk(BIOS_ERR, "%s: Incorrect device found\n", __func__); + return; + } + + cfg = config_of(machine_dev); + gpio = &cfg->dmic_select_gpio; + + if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) + gpio->pins[0] = GPIO_13; + else + gpio->pins[0] = GPIO_6; + +} + +void variant_audio_update(void) +{ + update_dmic_gpio(); + update_hp_int_odl(); +} + +/* + * Removes reset_gpio from usb device in device tree. + * + * debug_device_name is used for debug messaging only. + */ +static void remove_usb_device_reset_gpio(const struct device_path usb_path[], + size_t path_length, const char *debug_device_name) +{ + + const struct device *usb_dev; + struct drivers_usb_acpi_config *usb_cfg; + + usb_dev = find_dev_nested_path(pci_root_bus(), usb_path, path_length); + if (!usb_dev) { + printk(BIOS_ERR, "%s: Failed to find %s!", __func__, debug_device_name); + return; + } + /* config_of dies on failure, so a NULL check is not required */ + usb_cfg = config_of(usb_dev); + usb_cfg->reset_gpio.pin_count = 0; +} + +/* + * The bluetooth device may be on XHCI0 or XHCI1 depending on SOC. + * There's no harm in removing reset_gpio from both here. + */ +static void baseboard_trembyle_remove_bluetooth_reset_gpio(void) +{ + static const struct device_path xhci0_bt_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = XHCI0_DEVFN + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 0, + .usb.port_id = 0 + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 2, + .usb.port_id = 5 + } + }; + static const struct device_path xhci1_bt_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = XHCI1_DEVFN + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 0, + .usb.port_id = 0 + }, + { + .type = DEVICE_PATH_USB, + .usb.port_type = 2, + .usb.port_id = 1 + } + }; + + remove_usb_device_reset_gpio(xhci0_bt_path, ARRAY_SIZE(xhci0_bt_path), + "XHCI0 Bluetoth USB Device"); + remove_usb_device_reset_gpio(xhci1_bt_path, ARRAY_SIZE(xhci1_bt_path), + "XHCI1 Bluetoth USB Device"); +} + +void variant_bluetooth_update(void) +{ + if (CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) || variant_uses_v3_schematics()) return; - acp_dev = pcidev_path_behind(gpp_a_dev->link_list, AUDIO_DEVFN); - if (acp_dev == NULL) + baseboard_trembyle_remove_bluetooth_reset_gpio(); +} + +void variant_touchscreen_update(void) +{ + DEVTREE_CONST struct device *mmio_dev = NULL; + struct device *child = NULL; + + /* + * By default, devicetree/overridetree entries for touchscreen device are configured to + * match v3.6 of reference schematics. So, if the board is using v3.6+ schematics, no + * additional work is required here. For maintaining support for pre-v3.6 boards, rest + * of the code in this function finds all entries that correspond to touchscreen + * devices (identified by reset_gpio being set to GPIO_140) and updates them as per + * pre-v3.6 version of schematics: + * 1. reset_gpio is marked as active high. + */ + if (variant_uses_v3_6_schematics()) return; - while ((machine_dev = dev_bus_each_child(acp_dev->link_list, machine_dev)) != NULL) { - struct drivers_amd_i2s_machine_dev_config *cfg; - struct acpi_gpio *gpio; + while (1) { + mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO); + if (mmio_dev == NULL) + break; + if (mmio_dev->path.mmio.addr == APU_I2C2_BASE) + break; + } - if (machine_dev->chip_info == NULL) + if (mmio_dev == NULL) + return; + + while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + struct drivers_i2c_generic_config *cfg; + + if (child->chip_ops == &drivers_i2c_generic_ops) { + cfg = config_of(child); + } else if (child->chip_ops == &drivers_i2c_hid_ops) { + struct drivers_i2c_hid_config *hid_cfg; + hid_cfg = config_of(child); + cfg = &hid_cfg->generic; + } else { + continue; + } + + /* If reset_gpio is set to GPIO_140, assume that this is touchscreen device. */ + if (cfg->reset_gpio.pins[0] != GPIO_140) continue; - if (machine_dev->chip_ops != &drivers_amd_i2s_machine_dev_ops) - continue; - - cfg = machine_dev->chip_info; - gpio = &cfg->dmic_select_gpio; - - if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) - gpio->pins[0] = GPIO_13; - else - gpio->pins[0] = GPIO_6; - - break; + cfg->reset_gpio.active_low = 0; + cfg->enable_gpio.pin_count = 0; + cfg->enable_gpio.pins[0] = 0; } } diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index 2a50d74b8b..c8cb10fa71 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -8,18 +8,48 @@ #include static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio berknip_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -37,8 +67,11 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) if (board_version <= 1) { *size = ARRAY_SIZE(berknip_bid1_gpio_set_stage_ram); return berknip_bid1_gpio_set_stage_ram; + } else if (board_version <= 2) { + *size = ARRAY_SIZE(berknip_bid2_gpio_set_stage_ram); + return berknip_bid2_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(berknip_gpio_set_stage_ram); + return berknip_gpio_set_stage_ram; } diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index ead39cb8bd..674d5574be 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -9,15 +9,15 @@ chip soc/amd/picasso register "system_config" = "3" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_limit" = "20000" #mw + register "fast_ppt_limit" = "24000" #mw register "slow_ppt_time_constant" = "5" #second register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "25000" #mw + register "sustained_power_limit" = "12000" #mw - register "telemetry_vddcr_vdd_slope" = "62451" #mA + register "telemetry_vddcr_vdd_slope" = "65599" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "27301" #mA + register "telemetry_vddcr_soc_slope" = "29788" #mA register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration @@ -27,6 +27,7 @@ chip soc/amd/picasso .speed = I2C_SPEED_FAST, .rise_time_ns = 3, .fall_time_ns = 2, + .data_hold_time_ns = 400, }" # Enable I2C3 for H1 400kHz @@ -37,6 +38,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -65,9 +72,14 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -75,7 +87,9 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -85,7 +99,9 @@ chip soc/amd/picasso register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" @@ -99,7 +115,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index f53e66294d..1f871a983b 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -1,26 +1,13 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = samsung-K4A8G165WC-BCTD_x2 # 0b0000 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b0001 -# b/149596178: We can't use dual channel channel until the PSP supports missing -# channels. -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0101 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0110 -APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b0111 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-8.hex # ID = 1(0b0001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt new file mode 100644 index 0000000000..2522cdb3de --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt @@ -0,0 +1,9 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCTD 0 (0000) +MT40A512M16TB-062E:J 2 (0010) +H5AN8G6NDJR-XNC 3 (0011) +K4A8G165WC-BCWE 5 (0101) +MT40A1G16KD-062E:E 6 (0110) +H5ANAG6NCMR-XNC 7 (0111) +K4AAG165WA-BCWE 8 (1000) +K4AAG165WA-BCTD 1 (0001) diff --git a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt new file mode 100644 index 0000000000..1e5ee8a961 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCTD, 0 +MT40A512M16TB-062E:J, 2 +H5AN8G6NDJR-XNC, 3 +K4A8G165WC-BCWE, 5 +MT40A1G16KD-062E:E, 6 +H5ANAG6NCMR-XNC, 7 +K4AAG165WA-BCWE, 8 +K4AAG165WA-BCTD diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index a4813e90fb..7600d4c8ce 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -12,18 +12,30 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC /* USB_OC2_L - USB A0 & A1 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* TP */ + PAD_NC(GPIO_32), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), /* Unused */ - PAD_GPI(GPIO_143, PULL_DOWN), + PAD_NC(GPIO_143), }; static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC + /* TP */ + PAD_NC(GPIO_32), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 98a93eda0c..e5608d9091 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -37,6 +37,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -48,9 +54,12 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -58,7 +67,7 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -68,7 +77,7 @@ chip soc/amd/picasso register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -80,8 +89,11 @@ chip soc/amd/picasso register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end diff --git a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc index 7baf8be205..e8ed39da29 100644 --- a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc @@ -1,25 +1,9 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 -APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010 -APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = HMA851S6CJR6N-VK +SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-5.hex # ID = 3(0b0011) Parts = K4AAG165WB-MCTD +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE diff --git a/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..f70d7f34d4 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +HMA851S6CJR6N-VK 0 (0000) +H5ANAG6NCMR-VKC 1 (0001) +K4A8G165WC-BCTD 2 (0010) +K4AAG165WB-MCTD 3 (0011) +K4A8G165WC-BCWE 4 (0100) diff --git a/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..5a104d7bf1 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt @@ -0,0 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +HMA851S6CJR6N-VK, 0 +H5ANAG6NCMR-VKC, 1 +K4A8G165WC-BCTD, 2 +K4AAG165WB-MCTD, 3 +K4A8G165WC-BCWE, 4 diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c index ceef2895a0..21aaec829a 100644 --- a/src/mainboard/google/zork/variants/dalboz/variant.c +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -10,6 +10,8 @@ #include #define EC_PNP_ID 0x0c09 +#define DALBOZ_DB_USBC 0x0 +#define DALBOZ_DB_HDMI 0x1 /* Look for an EC device of type PNP with id 0x0c09 */ static bool match_ec_dev(DEVTREE_CONST struct device *dev) @@ -104,34 +106,38 @@ static void update_audio_configuration(void) cfg->remote_bus = 5; } -static int sku_has_emmc(void) -{ - uint32_t board_sku = sku_id(); - - /* Factory flow requires all OS boot media to be enabled. */ - if (boot_is_factory_unprovisioned()) - return 1; - - /* FIXME: This needs to be fw_config controlled. */ - /* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */ - if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN) - return 1; - - return 0; -} - void variant_devtree_update(void) { + uint32_t board_version; struct soc_amd_picasso_config *cfg; cfg = config_of_soc(); - if (sku_has_emmc()) { - if (sku_id() == 0x5A800003) - /* rev0 boards have issues with HS400 */ - cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + /* + * If CBI board version cannot be read, assume this is an older revision + * of hardware. + */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (variant_has_emmc() || boot_is_factory_unprovisioned()) { + if (board_version <= 2) { + /* + * rev0 and rev1 boards have issues with HS400 + * + * There is a tuning fix with ES which shows promise + * for some boards, and a HW fix with stitching vias. + * There were also concerns that these boards did not + * have good margins for certain skus. + * + * But these original boards have none of these fixes. + * So we keep the speed low here, with the intent that + * other variants implement these corrections. + */ + cfg->emmc_config.timing = SD_EMMC_EMMC_HS200; + } } else { - cfg->sd_emmc_config = SD_EMMC_DISABLE; + cfg->emmc_config.timing = SD_EMMC_DISABLE; } update_audio_configuration(); @@ -179,19 +185,20 @@ static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { } }; -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - uint32_t board_sku = sku_id(); + uint32_t daughterboard_id = variant_get_daughterboard_id(); - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); - /* SKU 1, A, and D DB have HDMI, as well as unknown */ - /* FIXME: this needs to be fw_config controlled. */ - if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001) - || (board_sku == CROS_SKU_UNKNOWN)) { + /* + * Get daughterboard id from FW_CONFIG and configure descriptors accordingly. + * For unprovisioned boards use DB_HDMI as default. + */ + if ((daughterboard_id == DALBOZ_DB_HDMI) || boot_is_factory_unprovisioned()) { *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } else { diff --git a/src/mainboard/google/zork/variants/dirinboz/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc new file mode 100644 index 0000000000..51d19fe9ba --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c new file mode 100644 index 0000000000..8da85b6720 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), + /* TP */ + PAD_NC(GPIO_32), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl similarity index 56% rename from src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl index 189cafea4c..7a793d8102 100644 --- a/src/mainboard/google/volteer/variants/voxel/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/thermal.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h similarity index 58% rename from util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h index 189cafea4c..9e61a440cf 100644 --- a/util/mainboard/google/volteer/template/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/ec.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h similarity index 58% rename from src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h index 189cafea4c..dfaeec3ae1 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/gpio.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h similarity index 58% rename from src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl rename to src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h index 189cafea4c..2af647973d 100644 --- a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/thermal.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include +#include diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb new file mode 100644 index 0000000000..a11fa5e4c7 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "6000" #mw + register "fast_ppt_limit" = "9000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "2500" #second + register "sustained_power_limit" = "4800" #mw + + register "telemetry_vddcr_vdd_slope" = "42465" #mA + register "telemetry_vddcr_vdd_offset" = "69" + register "telemetry_vddcr_soc_slope" = "42667" #mA + register "telemetry_vddcr_soc_offset" = "167" + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc new file mode 100644 index 0000000000..5e0983695e --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-2.hex # ID = 6(0b0110) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 7(0b0111) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-8.hex # ID = 9(0b1001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..8c8ee39dff --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt @@ -0,0 +1,9 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCTD 2 (0010) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +H5ANAG6NCMR-XNC 6 (0110) +MT40A512M16TB-062E:J 7 (0111) +MT40A1G16KD-062E:E 8 (1000) +K4AAG165WA-BCTD 9 (1001) +K4AAG165WA-BCWE 10 (1010) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..ba70da3ed3 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCTD, 2 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +H5ANAG6NCMR-XNC, 6 +MT40A512M16TB-062E:J, 7 +MT40A1G16KD-062E:E, 8 +K4AAG165WA-BCTD, 9 +K4AAG165WA-BCWE, 10 diff --git a/src/mainboard/google/zork/variants/dirinboz/variant.c b/src/mainboard/google/zork/variants/dirinboz/variant.c new file mode 100644 index 0000000000..ff57f503a5 --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/variant.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index d8c8edd1c0..0ec1ab23da 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -8,38 +8,68 @@ #include static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* FPMCU_RST_L Change NC */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_NC(GPIO_11), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* FPMCU_BOOT0 Change NC */ - PAD_GPI(GPIO_69, PULL_UP), + PAD_NC(GPIO_69), /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ - PAD_GPI(GPIO_86, PULL_UP), + PAD_NC(GPIO_86), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - Not connected */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - Not connected */ + PAD_NC(GPIO_5), /* FPMCU_RST_L Change NC */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_NC(GPIO_11), /* FPMCU_BOOT0 Change NC */ - PAD_GPI(GPIO_69, PULL_UP), + PAD_NC(GPIO_69), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index a4cdac6c4b..5ef2f0ac77 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -22,7 +22,12 @@ chip soc/amd/picasso # End : OPN Performance Configuration - register "xhci0_force_gen1" = "1" + register "usb3_port_force_gen1" = "{ + .ports.xhci0_port0 = 1, + .ports.xhci0_port1 = 1, + .ports.xhci0_port2 = 1, + .ports.xhci0_port3 = 1, + }" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ @@ -39,6 +44,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -67,9 +78,14 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/hid @@ -77,9 +93,16 @@ chip soc/amd/picasso register "generic.desc" = ""ELAN Touchscreen"" register "generic.probed" = "1" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "10" + register "generic.stop_delay_ms" = "300" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc index cd912726c4..10dea1cd35 100644 --- a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -1,25 +1,9 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x2 # 0b0000 -APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 -APCB_SOURCES += micron-MT40A1G16KNR-075-E_x2 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCTD_x2 # 0b0100 -APCB_SOURCES += empty # 0b0101 -APCB_SOURCES += empty # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-3.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCTD diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt new file mode 100644 index 0000000000..7e54cc1b08 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/dram_id.generated.txt @@ -0,0 +1,5 @@ +DRAM Part Name ID to assign +H5AN8G6NCJR-VKC 0 (0000) +MT40A512M16TB-062E:J 2 (0010) +MT40A1G16KD-062E:E 3 (0011) +K4A8G165WC-BCTD 4 (0100) diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt new file mode 100644 index 0000000000..b4b16015fb --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +H5AN8G6NCJR-VKC,0 +MT40A512M16TB-062E:J,2 +MT40A1G16KD-062E:E,3 +K4A8G165WC-BCTD,4 diff --git a/src/mainboard/google/zork/variants/ezkinil/variant.c b/src/mainboard/google/zork/variants/ezkinil/variant.c index d7cf5a8803..f76ab62035 100644 --- a/src/mainboard/google/zork/variants/ezkinil/variant.c +++ b/src/mainboard/google/zork/variants/ezkinil/variant.c @@ -5,30 +5,15 @@ #include #include -static int sku_has_emmc(void) -{ - uint32_t board_sku = sku_id(); - - /* Factory flow requires all OS boot media to be enabled. */ - if (boot_is_factory_unprovisioned()) - return 1; - - if ((board_sku == 0x5A020000) || - (board_sku == 0x5A020001) || (board_sku == 0x5A020002) || - (board_sku == 0x5A020005) || (board_sku == 0x5A020006) || - (board_sku == 0x5A020009) || (board_sku == 0x5A02000A) || - (board_sku == 0x5A02000D) || (board_sku == 0x5A02000E)) - return 1; - - return 0; -} - void variant_devtree_update(void) { struct soc_amd_picasso_config *cfg; cfg = config_of_soc(); - if (!sku_has_emmc()) - cfg->sd_emmc_config = SD_EMMC_DISABLE; + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; } diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc index 57e7136ddc..51d19fe9ba 100644 --- a/src/mainboard/google/zork/variants/morphius/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 4cb98a3481..8da0de4f60 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -11,32 +11,53 @@ static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* DMIC_AD_EN */ PAD_GPO(GPIO_84, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = { + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -57,6 +78,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) } else if (board_version <= 2) { *size = ARRAY_SIZE(morphius_bid2_gpio_set_stage_ram); return morphius_bid2_gpio_set_stage_ram; + } else if (board_version <= 3) { + *size = ARRAY_SIZE(morphius_bid3_gpio_set_stage_ram); + return morphius_bid3_gpio_set_stage_ram; } *size = 0; diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index e177507e22..3afa327935 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -4,3 +4,17 @@ /* Enable PS/2 Mouse */ #define SIO_EC_ENABLE_PS2M + +/* Enable DPTC support */ +#define EC_ENABLE_AMD_DPTC_SUPPORT + +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#undef MAINBOARD_EC_S3_DEVICE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +/* Enable trackpoint S3 wakeups */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS \ + (EC_DEVICE_EVENT_MASK(EC_DEVICE_EVENT_TRACKPAD)) diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index eaabd588cf..43a94390a3 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -14,14 +14,27 @@ chip soc/amd/picasso register "slow_ppt_time_constant" = "5" #second register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "12000" #mw + register "thermctl_limit" = "100" #degrees C register "telemetry_vddcr_vdd_slope" = "78709" #mA register "telemetry_vddcr_vdd_offset" = "0" register "telemetry_vddcr_soc_slope" = "29035" #mA register "telemetry_vddcr_soc_offset" = "0" + # Set STAPM confiuration for tablet mode + register "dptc_enable" = "1" + register "slow_ppt_limit_tablet_mode" = "20000" #mw + register "fast_ppt_limit_tablet_mode" = "24000" #mw + register "sustained_power_limit_tablet_mode" = "12000" #mw + register "thermctl_limit_tablet_mode" = "70" #degrees C + # End : OPN Performance Configuration + register "usb3_port_force_gen1" = "{ + .ports.xhci0_port1 = 1, /* Left USB3A port 1 */ + .ports.xhci0_port2 = 1, /* Left USB3A port 2 */ + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -37,6 +50,12 @@ chip soc/amd/picasso .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -61,12 +80,17 @@ chip soc/amd/picasso device i2c 2c on end end chip drivers/i2c/hid - register "generic.hid" = ""GTCH7375L"" - register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" @@ -92,7 +116,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 080d468e91..2eb864df2b 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -1,26 +1,14 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# Alternatively, generated APCBs stored at -# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. -APCB_SOURCES = samsung-K4AAG165WA-BCWE_x2 # 0b0000 -APCB_SOURCES += empty # 0b0001 -# b/149596178: We can't use dual channel channel until the PSP supports missing -# channels. -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0010 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0011 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111 -APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-7.hex # ID = 0(0b0000) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 6(0b0110) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 7(0b0111) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-2.hex # ID = 8(0b1000) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = K4A8G165WC-BCWE diff --git a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt new file mode 100644 index 0000000000..7210071bd1 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt @@ -0,0 +1,10 @@ +DRAM Part Name ID to assign +K4AAG165WA-BCWE 0 (0000) +MT40A512M16TB-062E:J 2 (0010) +MT40A1G16KD-062E:E 3 (0011) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +MT40A512M16TB-062E:J 6 (0110) +K4AAG165WA-BCWE 7 (0111) +H5ANAG6NCMR-XNC 8 (1000) +K4A8G165WC-BCWE 9 (1001) diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt new file mode 100644 index 0000000000..329763962e --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -0,0 +1,18 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4AAG165WA-BCWE, 0 +MT40A512M16TB-062E:J, 2 +MT40A1G16KD-062E:E, 3 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +MT40A512M16TB-062E:J, 6 +K4AAG165WA-BCWE, 7 +H5ANAG6NCMR-XNC, 8 +K4A8G165WC-BCWE, 9 diff --git a/src/mainboard/google/zork/variants/morphius/variant.c b/src/mainboard/google/zork/variants/morphius/variant.c new file mode 100644 index 0000000000..092ff260b3 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; +} diff --git a/src/mainboard/google/zork/variants/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/Makefile.inc index 0b6bc4b349..57e7136ddc 100644 --- a/src/mainboard/google/zork/variants/trembyle/Makefile.inc +++ b/src/mainboard/google/zork/variants/trembyle/Makefile.inc @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index ce7e5dd5c6..9931479cc0 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -11,32 +11,44 @@ static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* DMIC_AD_EN */ PAD_GPO(GPIO_84, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = { /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ - PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), /* USB_OC2_L - USB A0 */ - PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), /* EN_PWR_TOUCHPAD_PS2 */ PAD_GPO(GPIO_67, HIGH), /* MST_GPIO_2 (Fw Update HDMI hub) */ PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), /* MST_GPIO_3 (Fw Update HDMI hub) */ PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 4cd53eea45..f06f03d8d6 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -22,6 +22,10 @@ chip soc/amd/picasso # End : OPN Performance Configuration + # USB OC pin mapping: existing trembyle boards are based on old schematics version + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1 + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -65,9 +69,14 @@ chip soc/amd/picasso register "desc" = ""Raydium Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -75,7 +84,7 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchscreen"" register "probed" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" device i2c 10 on end @@ -88,7 +97,7 @@ chip soc/amd/picasso register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPIO_6)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" register "wake" = "GEVENT_10" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc new file mode 100644 index 0000000000..6508c26b28 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC +SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC diff --git a/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt new file mode 100644 index 0000000000..20232a3378 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +H5AN8G6NCJR-VKC 0 (0000) +H5ANAG6NCMR-VKC 1 (0001) diff --git a/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt new file mode 100644 index 0000000000..7316ee04a0 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/spd/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +H5AN8G6NCJR-VKC, 0 +H5ANAG6NCMR-VKC, 1 diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index dc1e4117f9..af38c8828d 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c new file mode 100644 index 0000000000..12b303a9c5 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* TP */ + PAD_NC(GPIO_32), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 49d21d569a..b75beafa34 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -18,6 +18,14 @@ chip soc/amd/picasso # End : OPN Performance Configuration + register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_offset" = "208" + register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_offset" = "-83" + + # USB OC pin mapping + register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, @@ -28,11 +36,17 @@ chip soc/amd/picasso # I2C3 for H1 register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 110, + .fall_time_ns = 5, .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit @@ -88,12 +102,29 @@ chip soc/amd/picasso register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_off_delay_ms" = "1" register "generic.reset_delay_ms" = "120" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index c9a91083d8..c7890d0e1a 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -1,26 +1,12 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! -# Ordered List of APCB entries, up to 16. -# Entries should match this pattern {NAME}_x{1,2} -# There should be a matching SPD hex file in SPD_SOURCES_DIR -# matching the pattern {NAME}.spd.hex -# The _x{1,2} suffix denotes single or dual channel -# TODO: Remove channel suffix when b:141434940 is fixed -# Alternatively, generated APCBs stored at -# CONFIG_APCB_BLOB_DIR/APCB_{NAME}.bin can be included. -APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 -APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 -APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0010 -APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 -APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0100 -APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b0101 -APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b0110 -APCB_SOURCES += empty # 0b0111 -APCB_SOURCES += empty # 0b1000 -APCB_SOURCES += empty # 0b1001 -APCB_SOURCES += empty # 0b1010 -APCB_SOURCES += empty # 0b1011 -APCB_SOURCES += empty # 0b1100 -APCB_SOURCES += empty # 0b1101 -APCB_SOURCES += empty # 0b1110 -APCB_SOURCES += empty # 0b1111 +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 5(0b0101) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..8afd9563ad --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +K4A8G165WC-BCWE 2 (0010) +H5AN8G6NDJR-XNC 3 (0011) +MT40A512M16TB-062E:J 4 (0100) +K4AAG165WA-BCWE 5 (0101) +MT40A1G16KD-062E:E 6 (0110) +H5ANAG6NDMR-XNC 7 (0111) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..2b8d6df374 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +K4A8G165WC-BCWE, 2 +H5AN8G6NDJR-XNC, 3 +MT40A512M16TB-062E:J, 4 +K4AAG165WA-BCWE, 5 +MT40A1G16KD-062E:E, 6 +H5ANAG6NDMR-XNC, 7 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 5573837f9d..cbc160e5c7 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -21,12 +21,12 @@ static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { } }; -void variant_get_pcie_ddi_descriptors(const fsp_pcie_descriptor **pcie_descs, - size_t *pcie_num, +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); diff --git a/src/mainboard/google/zork/variants/woomax/Makefile.inc b/src/mainboard/google/zork/variants/woomax/Makefile.inc index 9dc5159c53..57e7136ddc 100644 --- a/src/mainboard/google/zork/variants/woomax/Makefile.inc +++ b/src/mainboard/google/zork/variants/woomax/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += ../baseboard/spd +subdirs-y += ./spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c new file mode 100644 index 0000000000..ebbcbea624 --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_NC(GPIO_4), + /* GPIO_5 NC */ + PAD_NC(GPIO_5), + /* GPIO_6 NC */ + PAD_NC(GPIO_6), + /* GPIO_11 NC */ + PAD_NC(GPIO_11), + /* GPIO_32 NC */ + PAD_NC(GPIO_32), + /* GPIO_69 NC */ + PAD_NC(GPIO_69), + /* RAM_ID_4 */ + PAD_NC(GPIO_84), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* TP */ + PAD_NC(GPIO_90), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), + /* GPIO_141 NC */ + PAD_NC(GPIO_141), + /* GPIO_143 NC */ + PAD_NC(GPIO_143), +}; + +static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_NC(GPIO_4), + /* GPIO_5 NC */ + PAD_NC(GPIO_5), + /* GPIO_6 NC */ + PAD_NC(GPIO_6), + /* GPIO_11 NC */ + PAD_NC(GPIO_11), + /* GPIO_32 NC */ + PAD_NC(GPIO_32), + /* GPIO_69 NC */ + PAD_NC(GPIO_69), + /* RAM_ID_4 */ + PAD_NC(GPIO_84), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), + /* GPIO_141 NC */ + PAD_NC(GPIO_141), + /* GPIO_143 NC */ + PAD_NC(GPIO_143), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* If board version cannot be read, assume it is board_version 0. */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 0; + + if (board_version == 0) { + *size = ARRAY_SIZE(woomax_bid0_gpio_set_stage_ram); + return woomax_bid0_gpio_set_stage_ram; + } + *size = ARRAY_SIZE(woomax_gpio_set_stage_ram); + return woomax_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 077e983f85..19d66fcfbd 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -16,12 +16,39 @@ chip soc/amd/picasso register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "15000" #mw - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope" = "102586" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope" = "26967" #mA register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB OC pin mapping + register "usb_port_overcurrent_pin[2]" = "USB_OC_NONE" # NC # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ @@ -33,16 +60,54 @@ chip soc/amd/picasso # Enable I2C3 for H1 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 37, /* 1.26v to 0 */ + .rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 34, /* 1.26v to 0 */ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + device usb 3.2 off end + end end # domain - device mmio 0xfedc4000 on end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc new file mode 100644 index 0000000000..91ef5e5bae --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/Makefile.inc @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 2(0b0010) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 5(0b0101) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 6(0b0110) +SPD_SOURCES += ddr4-spd-empty.hex # ID = 7(0b0111) +SPD_SOURCES += ddr4-spd-1.hex # ID = 8(0b1000) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = H5AN8G6NCJR-XNC +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-7.hex # ID = 11(0b1011) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt new file mode 100644 index 0000000000..c0583f495a --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/dram_id.generated.txt @@ -0,0 +1,7 @@ +DRAM Part Name ID to assign +MT40A512M16TB-062E:J 0 (0000) +H5AN8G6NCJR-XNC 1 (0001) +MT40A512M16TB-062E:J 8 (1000) +H5AN8G6NCJR-XNC 9 (1001) +MT40A1G16KD-062E:E 10 (1010) +K4AAG165WA-BCWE 11 (1011) diff --git a/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt new file mode 100644 index 0000000000..65988e95da --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/spd/mem_parts_used.txt @@ -0,0 +1,15 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +MT40A512M16TB-062E:J, 0 +H5AN8G6NCJR-XNC, 1 +MT40A512M16TB-062E:J, 8 +H5AN8G6NCJR-XNC, 9 +MT40A1G16KD-062E:E, 10 +K4AAG165WA-BCWE, 11 diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 2409348115..812c630b13 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -11,6 +11,8 @@ config BOARD_HP_SNB_IVB_LAPTOPS select SERIRQ_CONTINUOUS_MODE select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 if BOARD_HP_SNB_IVB_LAPTOPS @@ -20,22 +22,26 @@ config MAINBOARD_DIR config VARIANT_DIR string + default "2560p" if BOARD_HP_2560P default "2570p" if BOARD_HP_2570P default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M + default "probook_6360b" if BOARD_HP_PROBOOK_6360B default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 config MAINBOARD_PART_NUMBER string + default "EliteBook 2560p" if BOARD_HP_2560P default "EliteBook 2570p" if BOARD_HP_2570P default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M + default "ProBook 6360b" if BOARD_HP_PROBOOK_6360B default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 config OVERRIDE_DEVICETREE @@ -54,12 +60,14 @@ config VGA_BIOS_ID config USBDEBUG_HCD_INDEX int + default 1 if BOARD_HP_2560P default 2 if BOARD_HP_2570P default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M + default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this endif diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c01555fd13..85f95b27bf 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -1,5 +1,17 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_HP_2560P + bool "EliteBook 2560p" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_HP_2570P bool "EliteBook 2570p" @@ -30,8 +42,6 @@ config BOARD_HP_8460P select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_LPC47N217 @@ -66,21 +76,33 @@ config BOARD_HP_FOLIO_9470M select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_C216 +config BOARD_HP_PROBOOK_6360B + bool "ProBook 6360b" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_4096 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + config BOARD_HP_REVOLVE_810_G1 bool "EliteBook Revolve 810 G1" select BOARD_HP_SNB_IVB_LAPTOPS select BOARD_ROMSIZE_KB_16384 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 4c291a8bd1..acdd4b3496 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" @@ -47,7 +47,11 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # HD Audio controller device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt new file mode 100644 index 0000000000..a3e8a7be06 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt new file mode 100644 index 0000000000..ee23b34f79 Binary files /dev/null and b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/data.vbt differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c new file mode 100644 index 0000000000..29e9e0f827 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* back bottom USB port, USB debug */ + { 1, 1, 0 }, /* back upper USB port */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* webcam */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 1, 0, 3 }, + { 1, 0, 3 }, /* smartcard */ + { 1, 1, 4 }, /* fingerprint reader */ + { 1, 1, 4 }, /* WWAN */ + { 0, 0, 5 }, + { 1, 0, 5 }, /* docking */ + { 0, 0, 6 }, + { 0, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); + kbc1126_disable4e(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads new file mode 100644 index 0000000000..21de0db952 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- both on board and dock DP are DP1/HDMI1 + HDMI1, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c new file mode 100644 index 0000000000..30fd1f76e9 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c new file mode 100644 index 0000000000..eba1fb9729 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162b, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c162b), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x103c3066), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb new file mode 100644 index 0000000000..d69a21e9a1 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000155" + register "gpu_pch_backlight" = "0x02880288" + + device domain 0 on + subsystemid 0x103c 0x162b inherit + + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # mailbox at 0x200/0x201 and PM1 at 0x220 + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 0, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4), dock eSATA(5) + register "sata_port_map" = "0x33" + + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on # PCIe Port #2, ExpressCard + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end + device pci 1c.2 on end # PCIe Port #3, SD/MMC Host Controller + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7, WWAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + end + end +end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index e7e5dec181..357e24ad90 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -49,9 +49,6 @@ chip northbridge/intel/sandybridge end device pnp 4e.5 off end # COM2 end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 7c12fd3fbb..b8ddd698f2 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -40,9 +40,6 @@ chip northbridge/intel/sandybridge register "ec_fan_ctrl_value" = "0x44" device pnp ff.1 off end end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt new file mode 100644 index 0000000000..9f32b2703f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-probook-6360b-notebook-pc/5045581 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt new file mode 100644 index 0000000000..14ed640d2a Binary files /dev/null and b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c new file mode 100644 index 0000000000..95243016e6 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* left front */ + { 1, 1, 0 }, /* left rear, debug */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* webcam */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, /* fingerprint reader */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, /* right */ + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads new file mode 100644 index 0000000000..3df1e37f3e --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c new file mode 100644 index 0000000000..c281dcd5b9 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c new file mode 100644 index 0000000000..40de8bc56b --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1620, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1620), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x103c3066), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb new file mode 100644 index 0000000000..3289588132 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x0000014a" + + device domain 0 on + subsystemid 0x103c 0x1621 inherit + + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), docking(3, 5), eSATA(4) + # FIXME: ports 3, 5 are untested + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on # PCIe Port #2, ExpressCard + smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" + "ExpressCard Slot" "SlotDataBusWidth1X" + end + device pci 1c.2 on end # PCIe Port #3, SD/MMC and FireWire + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6e" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index cdf7ff3dea..af43af7c97 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -40,9 +40,6 @@ chip northbridge/intel/sandybridge register "ec_fan_ctrl_value" = "0x70" device pnp ff.1 off end end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end end end end diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 263d595d0e..bfabacce6c 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/intel/sandybridge register "c2_battery" = "3" register "c3_acpower" = "5" register "c3_battery" = "5" - device lapic 0x0 on end + device lapic 0x0 on end device lapic 0xacac off end end end diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c index 0d62faed7c..75dc3302a5 100644 --- a/src/mainboard/hp/z220_sff_workstation/mainboard.c +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include #include #include diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 94c4e23781..66d85f396b 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG - select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 30e4d2c6b8..cf73fc1d6a 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -20,12 +20,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 88a569993f..1799f9a2df 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -41,7 +41,7 @@ void bootblock_mainboard_early_init(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + // pnp_write_config(dev, PNP_IDX_MSC1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard @@ -49,7 +49,7 @@ void bootblock_mainboard_early_init(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); + //pnp_write_config(dev, PNP_IDX_MSC0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_GPIO2); @@ -59,9 +59,10 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, PNP_IDX_MSC1, 0x00); // GPIO bit 2 is 0 + // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, PNP_IDX_EN, 0x03); dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig new file mode 100644 index 0000000000..97b4bf7a2b --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -0,0 +1,87 @@ +if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select SOC_INTEL_ALDERLAKE + select HAVE_SPD_IN_CBFS + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config MAINBOARD_DIR + string + default "intel/adlrvp" + +config VARIANT_DIR + string + default "adlrvp_p" + +config GBB_HWID + string + depends on CHROMEOS + default "ADLRVPP" + +config MAINBOARD_PART_NUMBER + string + default "adlrvp" + +config MAINBOARD_FAMILY + string + default "Intel_adlrvp" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +choice + prompt "ON BOARD EC" + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config ADL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + +config ADL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config UART_FOR_CONSOLE + int + default 0 +endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000000..0d54bb9a27 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_P_EXT_EC + bool "Alderlake-P RVP with Chrome EC" + select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc new file mode 100644 index 0000000000..e8a0eca790 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -0,0 +1,19 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c new file mode 100644 index 0000000000..332ba1b7ae --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + } + } + } + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/intel/adlrvp/board_id.h b/src/mainboard/intel/adlrvp/board_id.h new file mode 100644 index 0000000000..2988127e9b --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/adlrvp/board_info.txt b/src/mainboard/intel/adlrvp/board_info.txt new file mode 100644 index 0000000000..be99df80a3 --- /dev/null +++ b/src/mainboard/intel/adlrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c new file mode 100644 index 0000000000..95f7497c2d --- /dev/null +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_init(void) +{ + variant_configure_early_gpio_pads(); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c new file mode 100644 index 0000000000..d963c73651 --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd new file mode 100644 index 0000000000..48666629db --- /dev/null +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xfe000000 32M { + SI_ALL 0x1081000 { + SI_DESC 0x1000 + SI_EC 0x80000 + SI_ME + } + SI_BIOS@0x1400000 0xc00000 { + RW_SECTION_A 0x368000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x357fc0 + RW_FWID_A 0x40 + } + RW_SECTION_B 0x368000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x357fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 0x100000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl new file mode 100644 index 0000000000..6163d01d3c --- /dev/null +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + +} diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c new file mode 100644 index 0000000000..9d7cc9118f --- /dev/null +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board_id.h" + +#define SPD_ID_MASK 0x7 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + int board_id = get_board_id(); + const bool half_populated = false; + + const struct spd_info lpddr4_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = get_spd_index(), + }; + + const struct spd_info ddr4_spd_info = { + .read_type = READ_SMBUS, + .spd_spec = { + .spd_smbus_address = { + [0] = 0xa0, + [1] = 0xa2, + [8] = 0xa4, + [9] = 0xa6, + }, + }, + }; + + switch (board_id) { + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + mupd->FspmConfig.DqPinsInterleaved = 1; + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + break; + case ADL_P_LP4_1: + case ADL_P_LP4_2: + mupd->FspmConfig.DqPinsInterleaved = 0; + memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +} diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc new file mode 100644 index 0000000000..1218a76690 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = adlrvp_lp4 #0b000 +SPD_SOURCES += empty # 0b001 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex new file mode 100644 index 0000000000..17f270d0ec --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -0,0 +1,32 @@ +23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/empty.spd.hex b/src/mainboard/intel/adlrvp/spd/empty.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc new file mode 100644 index 0000000000..8c0572163b --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb new file mode 100644 index 0000000000..a6b0039d0e --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -0,0 +1,141 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 2 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcUsage[2]" = "0x4" + register "PcieRpClkReqDetect[4]" = "1" + + # Enable PCH PCIE RP 6 using CLK 5 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcUsage[5]" = "0x5" + register "PcieRpClkReqDetect[5]" = "1" + + # Enable PCH PCIE RP 9 using CLK 1 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcUsage[1]" = "0x8" + register "PcieRpClkReqDetect[8]" = "1" + + # Enable CPU PCIE RP 1 using PEG CLK 0 + register "PcieClkSrcUsage[0]" = "0x40" + + # Enable PCU PCIE PEG Slot 1 and 2 + register "PcieClkSrcUsage[3]" = "0x41" + register "PcieClkSrcUsage[4]" = "0x42" + + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below + register "PcieClkSrcUsage[6]" = "0xff" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi + end + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 off end # RP2 + device pci 1c.2 off end # RP3 + device pci 1c.3 off end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 off end # RP7 + device pci 1c.7 off end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 off end # RP10 + device pci 1d.2 off end # RP11 + device pci 1d.3 off end # RP12 + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c new file mode 100644 index 0000000000..d45bf8e067 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c new file mode 100644 index 0000000000..f8b366049f --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../board_id.h" +#include +#include + +static const struct mb_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ + 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ + { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ + 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ + { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ + 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ + { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ + 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ + { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ + 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ + { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ + 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ + { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ + 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ + { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ + 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + }, + + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &mem_config; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..b61276c0c1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..5288b6f832 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include +#include + +enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + ADL_P_LP4_1 = 0x10, + ADL_P_LP4_2 = 0x11, + /* ADL-P DDR4 RVPs */ + ADL_P_DDR4_1 = 0x14, + ADL_P_DDR4_2 = 0x3F, +}; + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index f7e82a06ca..dd12a5b8c3 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 8268891186..b2d06539da 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index fe44d08ff4..c0c488a33f 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -25,7 +25,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - #if CONFIG(CHROMEOS) /* Emerald Lake has no EC (?) */ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 157f393454..6345090c7a 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -32,15 +32,6 @@ chip northbridge/intel/haswell device pci 02.0 on end # vga controller chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 32c9487052..c0647e11bd 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -3,11 +3,11 @@ if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 5a06a45ddd..280844d64a 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc index 48e6375819..f052142431 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = empty # 0b000 SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index d5449b077f..7201186168 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -280,8 +280,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e5f867cbdc..f24e191256 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -124,12 +124,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 53c677b64e..1bd4bfec28 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -14,9 +14,6 @@ chip soc/intel/cannonlake register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" @@ -140,12 +137,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/cedarisland_crb/Makefile.inc b/src/mainboard/intel/cedarisland_crb/Makefile.inc index 9bd017393c..3da456e436 100644 --- a/src/mainboard/intel/cedarisland_crb/Makefile.inc +++ b/src/mainboard/intel/cedarisland_crb/Makefile.inc @@ -1,2 +1,3 @@ bootblock-y += bootblock.c romstage-y += romstage.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 6f408b36da..72a0ec1d04 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -21,12 +21,11 @@ DefinitionBlock( { Device (PCI0) { - #include + #include #include } - Device (UNC0) { Name (_HID, EisaId ("PNP0A03")) diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index e005913393..cd15fed084 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -10,27 +10,27 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - ESPI_ALERT1# */ - PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), /* GPP_A1 - ESPI_IO0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), /* GPP_A2 - ESPI_IO1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), /* GPP_A3 - ESPI_IO2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), /* GPP_A4 - ESPI_IO3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), /* GPP_A5 - ESPI_CS0# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, 20K_PU, DEEP, NF3), /* GPP_A6 - ESPI_CS1# */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), /* GPP_A7 - ESPI_ALERT0# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF3), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - ESPI_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { /* GPP_A13 - GPIO */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* GPP_A14 - ESPI_RESET# */ - PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), /* GPP_A15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ @@ -59,9 +59,9 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, RSMRST, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, RSMRST, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPP_B3 - GPIO */ @@ -84,9 +84,9 @@ static const struct pad_config gpio_table[] = { /* GPP_B12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, RSMRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPP_B16 - GPIO */ @@ -104,19 +104,19 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - SATAXPCIE3 */ - PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F0, NONE, RSMRST, NF1), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F1, NONE, RSMRST, NF1), /* GPP_F2 - SATAXPCIE5 */ - PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F2, NONE, RSMRST, NF1), /* GPP_F3 - SATAXPCIE6 */ - PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F3, NONE, RSMRST, NF1), /* GPP_F4 - SATAXPCIE7 */ - PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F4, NONE, RSMRST, NF1), /* GPP_F5 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPP_F6 - GPIO */ @@ -128,33 +128,33 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, RSMRST, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, RSMRST, NF1), /* GPP_F12 - SATA_SDATAOUT1 */ - PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F12, NONE, RSMRST, NF1), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, RSMRST, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, RSMRST, NF3), /* GPP_F15 - USB_OC4# */ - PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F15, NONE, RSMRST, NF1), /* GPP_F16 - USB_OC5# */ - PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F16, NONE, RSMRST, NF1), /* GPP_F17 - USB_OC6# */ - PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F17, NONE, RSMRST, NF1), /* GPP_F18 - USB_OC7# */ - PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F18, NONE, RSMRST, NF1), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, RSMRST, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, RSMRST, NF1), /* GPP_F21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, RSMRST, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, RSMRST, NF3), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ @@ -165,7 +165,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - SML0ALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_C5, NONE, RSMRST, NF1), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ @@ -225,17 +225,17 @@ static const struct pad_config gpio_table[] = { /* GPP_D9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPP_D10 - SSATA_DEVSLP4 */ - PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D10, NONE, RSMRST, NF3), /* GPP_D11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI), /* GPP_D12 - SSATA_SDATAOUT1 */ - PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF3), /* GPP_D13 - SML0BCLK_IE */ - PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D13, NONE, RSMRST, NF3), /* GPP_D14 - SML0BDATA_IE */ - PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF3), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, RSMRST, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - GPIO */ @@ -255,13 +255,13 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E0, NONE, RSMRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E1, NONE, RSMRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI), /* GPP_E5 - GPIO */ @@ -271,31 +271,31 @@ static const struct pad_config gpio_table[] = { /* GPP_E7 - GPIO */ PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, RSMRST, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1), /* GPP_E10 - USB_OC1# */ - PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E10, NONE, RSMRST, NF1), /* GPP_E11 - USB_OC2# */ - PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E11, NONE, RSMRST, NF1), /* GPP_E12 - USB_OC3# */ - PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E12, NONE, RSMRST, NF1), /* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - ACPRESENT */ - PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* GPD2 - GBE_WAKE# */ - PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - SLP_A# */ - PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* GPD7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ @@ -303,20 +303,20 @@ static const struct pad_config gpio_table[] = { /* GPD9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - SLP_S5# */ - PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, RSMRST, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, RSMRST, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, RSMRST, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2), /* GPP_I4 - GPIO */ _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | @@ -327,11 +327,11 @@ static const struct pad_config gpio_table[] = { /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, RSMRST, NF2), /* GPP_I8 - PCI_DIS */ - PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I8, NONE, RSMRST, NF2), /* GPP_I9 - LAN_DIS */ - PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I9, NONE, RSMRST, NF2), /* GPP_I10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI), @@ -394,27 +394,27 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - LAN_NCSI_CLK_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_K0, NONE, RSMRST, NF1), /* GPP_K1 - LAN_NCSI_TXD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K1, NONE, RSMRST, NF1), /* GPP_K2 - LAN_NCSI_TXD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K2, NONE, RSMRST, NF1), /* GPP_K3 - LAN_NCSI_TX_EN */ - PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K3, NONE, RSMRST, NF1), /* GPP_K4 - LAN_NCSI_CRS_DV */ - PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K4, NONE, RSMRST, NF1), /* GPP_K5 - LAN_NCSI_RXD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K5, NONE, RSMRST, NF1), /* GPP_K6 - LAN_NCSI_RXD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K6, NONE, RSMRST, NF1), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, RSMRST, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, RSMRST, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, RSMRST, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -453,16 +453,16 @@ static const struct pad_config gpio_table[] = { /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, RSMRST, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, RSMRST, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, RSMRST, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPP_G22 - n/a */ - PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G22, NONE, RSMRST, NF3), /* GPP_G23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI), @@ -491,14 +491,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ - PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1), /* GPP_H7 - GPIO */ _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H8 - SRCCLKREQ14# */ - PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1), /* GPP_H9 - GPIO */ _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | @@ -519,54 +519,54 @@ static const struct pad_config gpio_table[] = { /* GPP_H19 - GPIO */ PAD_CFG_GPO(GPP_H19, 0, RSMRST), /* GPP_H20 - SSATAXPCIE2 */ - PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2), /* GPP_H21 - GPIO */ PAD_CFG_GPO(GPP_H21, 0, RSMRST), /* GPP_H22 - SSATAXPCIE4 */ - PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_H22, NONE, RSMRST, NF2), /* GPP_H23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI), /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - TESTCH0_D0 */ - PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L2, NONE, RSMRST, NF1), /* GPP_L3 - TESTCH0_D1 */ - PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L3, NONE, RSMRST, NF1), /* GPP_L4 - TESTCH0_D2 */ - PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L4, NONE, RSMRST, NF1), /* GPP_L5 - TESTCH0_D3 */ - PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L5, NONE, RSMRST, NF1), /* GPP_L6 - TESTCH0_D4 */ - PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L6, NONE, RSMRST, NF1), /* GPP_L7 - TESTCH0_D5 */ - PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L7, NONE, RSMRST, NF1), /* GPP_L8 - TESTCH0_D6 */ - PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L8, NONE, RSMRST, NF1), /* GPP_L9 - TESTCH0_D7 */ - PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L9, NONE, RSMRST, NF1), /* GPP_L10 - TESTCH0_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L10, NONE, RSMRST, NF1), /* GPP_L11 - TESTCH1_D0 */ - PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L11, NONE, RSMRST, NF1), /* GPP_L12 - TESTCH1_D1 */ - PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L12, NONE, RSMRST, NF1), /* GPP_L13 - TESTCH1_D2 */ - PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L13, NONE, RSMRST, NF1), /* GPP_L14 - TESTCH1_D3 */ - PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L14, NONE, RSMRST, NF1), /* GPP_L15 - TESTCH1_D4 */ - PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L15, NONE, RSMRST, NF1), /* GPP_L16 - TESTCH1_D5 */ - PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L16, NONE, RSMRST, NF1), /* GPP_L17 - TESTCH1_D6 */ - PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L17, NONE, RSMRST, NF1), /* GPP_L18 - TESTCH1_D7 */ - PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L18, NONE, RSMRST, NF1), /* GPP_L19 - TESTCH1_CLK */ - PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L19, NONE, RSMRST, NF1), }; #endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index e82d26b1e1..03e28a1678 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,25 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - void *start = (void *) m_cfg; - // BoardId - write8(start + 140, 0x1d); - - // BoardTypeBitmask - write32(start + 104, 0x11111111); - - // DebugPrintLevel - write8(start + 45, 8); - - // KtiLinkSpeedMode - write8(start + 64, 0); - - // KtiPrefetchEn - write8(start + 53, 2); + m_cfg->KtiLinkSpeedMode = 0; } diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 81bfc93bc1..b1d8ebab95 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 519cd50dc1..e03e862636 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -14,4 +14,4 @@ config BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COFFEELAKE config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 121012e888..5dd84cf8e5 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 01d970ca56..0b40a5c359 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" - # HECI - register "HeciEnabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 3c753915f9..5700f064b0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -579,8 +579,6 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 989b5cd4ea..a1455848e9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -99,12 +99,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index a63d4c0364..37b86c6be0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -15,12 +15,10 @@ chip soc/intel/cannonlake register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" register "usb2_ports[10]" = "USB2_PORT_MID(OC3)" register "usb2_ports[11]" = "USB2_PORT_MID(OC6)" register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" - register "usb2_ports[13]" = "USB2_PORT_EMPTY" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" @@ -107,12 +105,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 x4 SLOT 1 + device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -120,11 +124,21 @@ chip soc/intel/cannonlake device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on end # PCI Express Port 17 - device pci 1b.1 on end # PCI Express Port 18 - device pci 1b.2 on end # PCI Express Port 19 - device pci 1b.3 on end # PCI Express Port 20 - device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 + device pci 1b.0 on # PCI Express Port 17 + register "PcieRpSlotImplemented[16]" = "1" + end + device pci 1b.1 on # PCI Express Port 18 + register "PcieRpSlotImplemented[17]" = "1" + end + device pci 1b.2 on # PCI Express Port 19 + register "PcieRpSlotImplemented[18]" = "1" + end + device pci 1b.3 on # PCI Express Port 20 + register "PcieRpSlotImplemented[19]" = "1" + end + device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2 + register "PcieRpSlotImplemented[20]" = "1" + end device pci 1e.1 off end # UART #1 device pci 1f.6 on end # GbE end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index c5c291df9f..f48c9b49a8 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -84,12 +84,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 93b5af9394..28b33cf5f4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -86,7 +86,7 @@ chip soc/intel/cannonlake end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 17.0 on end # SATA @@ -94,12 +94,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 1e388240a6..89d60366a7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -78,12 +78,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 30e4d2c6b8..cf73fc1d6a 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -20,12 +20,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } diff --git a/src/mainboard/intel/d945gclf/acpi/superio.asl b/src/mainboard/intel/d945gclf/acpi/superio.asl index bd70025c66..84dd30dcab 100644 --- a/src/mainboard/intel/d945gclf/acpi/superio.asl +++ b/src/mainboard/intel/d945gclf/acpi/superio.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Device (SIO1) { Name (_HID, EISAID("PNP0A05")) diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index e81b4b66b4..391d1f23b2 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,15 +14,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index 4905f1d133..b1f6e77558 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 79bb1b8956..2174ecd097 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index de2d71dd29..bb2456f537 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -22,7 +22,6 @@ chip northbridge/intel/x4x # Northbridge # Set AHCI mode. register "sata_port_map" = "0x1f" register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0xb" diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 119346efb7..a2aaf33bb0 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 8ed2afff3a..7b1b564e52 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -1,7 +1,7 @@ config BOARD_INTEL_BASEBOARD_GLKRVP def_bool n - select SOC_INTEL_GLK + select SOC_INTEL_GEMINILAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -68,10 +68,6 @@ config MAINBOARD_FAMILY string default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP -config MAX_CPUS - int - default 4 - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig index d110c281a2..05a8d2d405 100644 --- a/src/mainboard/intel/harcuvar/Kconfig +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -19,6 +19,7 @@ config MAINBOARD_PART_NUMBER config ENABLE_FSP_MEMORY_DOWN bool "Enable Memory Down" default n + select HAVE_SPD_IN_CBFS help Select this option to enable Memory Down function. diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index c51bd69872..821de5f5ec 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -8,8 +8,6 @@ #include #include -extern const unsigned char AmlCode[]; - void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index fbad79836f..0373c01c60 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -12,7 +12,7 @@ /* * Define platform specific Memory Down Configure structure. * - * If CONFIG_ENABLE_FSP_MEMORY_DOWN is enabled, the MEMORY_DOWN_CONFIG + * If CONFIG(ENABLE_FSP_MEMORY_DOWN) is enabled, the MEMORY_DOWN_CONFIG * structure should be customized to match the design. * * .SlotState indicates the memory down state of the specific channel/DIMM. diff --git a/src/mainboard/intel/harcuvar/spd/Makefile.inc b/src/mainboard/intel/harcuvar/spd/Makefile.inc index 55a6aef7a8..ec07cfb845 100644 --- a/src/mainboard/intel/harcuvar/spd/Makefile.inc +++ b/src/mainboard/intel/harcuvar/spd/Makefile.inc @@ -2,23 +2,8 @@ romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - # Order matters for SPD sources. The following indices # define the SPD data to use. SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do echo -e -n "\\x$$c"; \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) spd.bin-position := $(CONFIG_SPD_LOC) -spd.bin-type := spd diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 2743384967..69559edcea 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -4,11 +4,11 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select EC_ACPI - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index a3c93e2c5f..861ccb13b2 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -46,8 +46,4 @@ DefinitionBlock( #endif #include - - // Mainboard specific - #include "acpi/mainboard.asl" - } diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc index 3114eebaf5..8e3ce25085 100644 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = empty # 0b000 SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 SPD_SOURCES += empty # 2b010 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index c00df81863..286753a820 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index c00df81863..286753a820 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -86,8 +86,6 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index b56e22a35c..1125a9b7f2 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -3,18 +3,24 @@ if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DPTF_USE_EISA_HID select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_JASPERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU config MAINBOARD_DIR string diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index a1cd12c136..2ac1b07bef 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -17,7 +17,6 @@ ramstage-y += board_id.c smm-y += smihandler.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl b/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.h b/src/mainboard/intel/jasperlake_rvp/board_id.h index 55b4f52d53..85c7c85f40 100644 --- a/src/mainboard/intel/jasperlake_rvp/board_id.h +++ b/src/mainboard/intel/jasperlake_rvp/board_id.h @@ -3,7 +3,6 @@ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ - /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 827e4484ca..05f45922e2 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -28,15 +28,15 @@ FLASH@0xff000000 0x1000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x100000 - WP_RO@0x6d0000 0x330000 { + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x32c000 { + RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x23c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index f47424f996..5da2c1221c 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -45,12 +45,5 @@ DefinitionBlock( } #endif - /* Camera */ - #include - #include - - /* Mainboard specific */ - #include "acpi/mainboard.asl" - } diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 3b9dff990a..315d47d2b0 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -3,10 +3,14 @@ #include #include #include +#include #include +#include #include #include +#define SERIAL_IO_PCR_GPPRVRW4 0x60C + static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -14,6 +18,9 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA)) + pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index 3c8040c7c2..ef1eaabd90 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,5 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = jslrvp # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl deleted file mode 100644 index 14139981a9..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C5) -{ - PowerResource (FCPR, 0x00, 0x0000) - { - Name (STA, Zero) - Method (_ON, 0, Serialized) /* _ON_: Power On */ - { - If ((STA == Zero)) - { - /* Enable CLK1 */ - MCON(1, 1) // Clock 1, 19.2MHz - /* Pull PWREN(GPIO R6) high */ - STXS(GPP_D4) - Sleep(5) /* 5 us */ - /* Pull RST(GPIO H12) low */ - CTXS(GPP_C19) - Sleep(5) /* 5 us */ - /* Pull RST high */ - STXS(GPP_C19) - Sleep(5) /* 5 us */ - STA = 1 - } - } - - Method (_OFF, 0, Serialized) /* _OFF: Power Off */ - { - If ((STA == One)) - { - /* Pull RST low */ - CTXS(GPP_C19) - /* Pull PWREN low */ - CTXS(GPP_D4) - /* Disable CLK0 */ - MCOF(1) /* Clock 1 */ - STA = 0 - } - } - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA) - } - } - - Device (CAM1) - { - Name (_HID, "OVTI5675") /* _HID: Hardware ID */ - - Name (_UID, Zero) /* _UID: Unique ID */ - - Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02 - } - }, - - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 0x1AD27480 - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } - - Device (VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hadware ID */ - - Name (_UID, 0x03) /* _UID: Unique ID */ - - Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ - { - I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , Exclusive, - ) - }) - - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM1 - }) - - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ - { - FCPR - }) - - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ - Package(0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9714" - } - } - }) - } -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl deleted file mode 100644 index 48650c9360..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl deleted file mode 100644 index cebf15e753..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (_SB.PCI0.IPU0) -{ - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - - Package (0x02) - { - "clock-lanes", - Zero - }, - - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02, - } - }, - - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C5.CAM1, - Zero, - Zero - } - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl deleted file mode 100644 index 013b26f3c6..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) // _ADR: Address - - Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name - } -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 14ca4a5abd..fc96719643 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -55,6 +55,9 @@ chip soc/intel/jasperlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" @@ -91,7 +94,7 @@ chip soc/intel/jasperlake [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" @@ -125,6 +128,12 @@ chip soc/intel/jasperlake # Enable DPTF register "dptf_enable" = "1" + # Add PL1 and PL2 values + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + # Enable S0ix register "s0ix_enable" = "1" @@ -146,16 +155,67 @@ chip soc/intel/jasperlake .sda_hold = 36, } }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, + .speed = I2C_SPEED_FAST, + }, }" + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 05.0 on end #IPU + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device + + device pci 05.0 on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 @@ -245,39 +305,39 @@ chip soc/intel/jasperlake end device pci 14.5 on end # SDCard device pci 15.0 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end end # I2C #0 Audio device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 @@ -289,18 +349,110 @@ chip soc/intel/jasperlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 Cam 0 - device pci 19.1 on end # I2C #5 Cam 1 and VCM + device pci 19.0 on # I2C #4 Cam 0 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI2740"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 2740 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 10 on end + end + end + device pci 19.1 on # I2C #5 Cam 1 and VCM + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + device i2c 0C on end + end + end + device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 - WLAN + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 - NVMe + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -314,7 +466,7 @@ chip soc/intel/jasperlake end # GSPI #1 device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index d67f4a44e4..21e25ab896 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -31,6 +31,9 @@ static const struct pad_config gpio_table[] = { /* PMC_PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), @@ -76,9 +79,18 @@ static const struct pad_config gpio_table[] = { /* CAM2_PWREN */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* CAM1_PWREN */ + PAD_CFG_GPO(GPP_D5, 0, PLTRST), + /*LAN_RST_N*/ PAD_CFG_GPO(GPP_D6, 1, PLTRST), + /* I2C4B_SDA */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF3), + + /* I2C4B_SCL */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* AVS_I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), @@ -97,6 +109,9 @@ static const struct pad_config gpio_table[] = { /* I2C5_SCL */ PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + /* IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2), + /* IMGCLKOUT_1 */ PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl deleted file mode 100644 index 318b0dea04..0000000000 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 434e9dd86a..46499f48f1 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -42,7 +42,7 @@ static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = { /* Baseboard Rcomp target values */ .rcomp_targets = {0, 0, 0, 0, 0}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ @@ -87,7 +87,7 @@ static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = { */ .rcomp_targets = {80, 40, 40, 40, 30}, - /* Disable Early Command Training */ + /* Enable Early Command Training */ .ect = 1, /* Set Board Type */ diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index d7209c58da..f1db3dac3f 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index 763163afe7..af3ae57c8d 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -8,8 +8,6 @@ #define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC4 50 - - Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index fa55794139..26108a2592 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -23,46 +23,45 @@ Scope (\_SB.PCI0.I2C2) Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP1) + AVP1 = 1 } Else { - Store (0, AVP1) + AVP1 = 0 } } @@ -163,9 +162,9 @@ Scope (\_SB.PCI0.I2C2) Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -197,9 +196,9 @@ Scope (\_SB.PCI0.I2C2) Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -220,26 +219,26 @@ Scope (\_SB.PCI0.I2C2) Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 2 */ - If (LLess (VSIC, 2)) { + If (VSIC < 2) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { VSIO = 3 } - Increment (VSIC) + VSIC++ } } @@ -251,18 +250,18 @@ Scope (\_SB.PCI0.I2C2) PowerResource (OVTH, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -270,7 +269,7 @@ Scope (\_SB.PCI0.I2C2) Sleep(3) VACT = 1 - if (LNotEqual (ACVA, 109)) { + if (ACVA != 109) { /* Set ANA at 2.8152V */ ACVA = 109 } @@ -279,7 +278,7 @@ Scope (\_SB.PCI0.I2C2) \_SB.PCI0.I2C2.PMIC.CLKE() VDCT = 1 - if (LNotEqual (DCVA, 12)) { + if (DCVA != 12) { /* Set CORE at 1.2V */ DCVA = 12 } @@ -293,8 +292,8 @@ Scope (\_SB.PCI0.I2C2) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) @@ -319,17 +318,17 @@ Scope (\_SB.PCI0.I2C2) PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -338,7 +337,7 @@ Scope (\_SB.PCI0.I2C2) /* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { + if (VCMV != 109) { /* Set VCM value at 2.8152 V */ VCMV = 109 @@ -351,8 +350,8 @@ Scope (\_SB.PCI0.I2C2) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -522,46 +521,45 @@ Scope (\_SB.PCI0.I2C3) Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP2) + AVP2 = 1 } Else { - Store (0, AVP2) + AVP2 = 0 } } @@ -669,9 +667,9 @@ Scope (\_SB.PCI0.I2C3) Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -703,9 +701,9 @@ Scope (\_SB.PCI0.I2C3) Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -726,13 +724,13 @@ Scope (\_SB.PCI0.I2C3) Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { VSIO = 0 - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { VSIO = 3 } Release (MUTV) @@ -743,15 +741,15 @@ Scope (\_SB.PCI0.I2C3) PowerResource (OVFI, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 0)) { + If (AVP2 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { + if (AX2V != 52) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 @@ -761,7 +759,7 @@ Scope (\_SB.PCI0.I2C3) \_SB.PCI0.I2C3.PMIC.CLKE() VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { + if (AX1V != 19) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } @@ -778,8 +776,8 @@ Scope (\_SB.PCI0.I2C3) } Method (_OFF, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 1)) { + If (AVP2 == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C3.PMIC.CLKD() Sleep(2) diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 354f488736..256dda039a 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -41,7 +41,4 @@ DefinitionBlock( #endif #include - - // Mainboard specific - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index a3fb285d54..79206e00c8 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -10,7 +10,6 @@ #include #include "board_id.h" - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index d04269969a..887e4f16fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = rvp3 # 0b000 Dual Channel 4GB SPD_SOURCES += empty # 0b001 SPD_SOURCES += empty # 0b010 diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b14fe31db6..8de089de90 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -23,24 +23,13 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" + register "HeciEnabled" = "0" + register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PchHdaVcType" = "Vc1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "2" @@ -130,6 +119,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem @@ -168,7 +158,7 @@ chip soc/intel/skylake device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fa502834af..fbf08cde3f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,14 +1,8 @@ chip soc/intel/skylake # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" - register "IoBufferOwnership" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -50,8 +44,6 @@ chip soc/intel/skylake # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1" @@ -84,7 +76,6 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -124,6 +115,7 @@ chip soc/intel/skylake }" device domain 0 on + device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA device pci 19.1 on end # I2C #5 device pci 1e.1 on end # UART #1 @@ -131,6 +123,7 @@ chip soc/intel/skylake device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard + device pci 1f.3 on end # Intel HDA device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01458..0754c0735e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,13 +7,8 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0201" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "0" - register "HeciEnabled" = "0" + register "DspEnable" = "1" register "PmTimerDisabled" = "1" - register "Cio2Enable" = "1" - register "SaImguEnable" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -98,8 +93,6 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -124,6 +117,8 @@ chip soc/intel/skylake }" device domain 0 on + device pci 05.0 on end # SA IMGU + device pci 14.3 on end # Camera device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 @@ -134,5 +129,6 @@ chip soc/intel/skylake device pnp 0c31.0 on end end end # LPC Interface + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index a658b91545..4ead52c282 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -17,7 +17,6 @@ #define IO_EXPANDER_P2DOUT 0x06 #define IO_EXPANDER_1_ADDR 0x23 - /* GPE_EC_WAKE */ #define GPE_EC_WAKE GPE0_LAN_WAK @@ -200,7 +199,6 @@ static const struct pad_config early_gpio_table[] = { /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), }; - #endif #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 07d7385943..11f9c01501 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake # SATA port 0 - register "EnableSata" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" @@ -14,7 +13,6 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0201" # FSP Configuration - register "HeciEnabled" = "0" register "PmTimerDisabled" = "1" # VR Settings Configuration for 4 Domains @@ -118,25 +116,25 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index efa9d67aa0..b2d72c6c9c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -165,6 +165,5 @@ static const struct pad_config early_gpio_table[] = { /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), }; - #endif #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 91abfe6f03..78552fcdd5 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -5,10 +5,7 @@ chip soc/intel/skylake register "deep_s3_enable_dc" = "0" # FSP Configuration - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -127,7 +124,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "1" # Enable SSIC for WWAN - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -174,6 +170,7 @@ chip soc/intel/skylake device pci 1e.2 on end # GSPI #0 device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC + device pci 1e.6 off end # SDXC device pci 1f.0 on #chip drivers/pc80/tpm # device pnp 0c31.0 on end diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d7706d16a0..6e745d947a 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE + select HAVE_SPD_IN_CBFS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl deleted file mode 100644 index d9fdd023f1..0000000000 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index acd197bff4..2b7a0e3482 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -24,28 +24,14 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02" @@ -187,6 +173,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 90a559471a..17d4165256 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include @@ -33,7 +33,4 @@ DefinitionBlock( #include #include - - // Mainboard specific - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index b7c4d5551c..4136c368fd 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -44,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables( if (nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - /* 4 Channel DMIC array. */ if (nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 9ecf28d1fe..6a14c293a5 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -2,8 +2,6 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0000 Dual Channel 4GB SPD_SOURCES += hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0001 Single Channel 2GB SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF-1G-1866 # 0b0010 Dual Channel 4GB @@ -20,18 +18,3 @@ SPD_SOURCES += empty # 0b1100 SPD_SOURCES += empty # 0b1101 SPD_SOURCES += empty # 0b1110 SPD_SOURCES += empty # 0b1111 - - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index a1faf7e7e2..71643bed05 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -49,7 +49,6 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) static const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 }; - if (mem_cfg_id == K4E6E304EE_MEM_ID) { memcpy(rcomp_strength_ptr, StrengthendRcompTarget, sizeof(StrengthendRcompTarget)); diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 6c872b186e..e2f2f8e559 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 6c872b186e..e2f2f8e559 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 0 diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f94cd54fd5..f81dbee976 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -5,9 +5,7 @@ if BOARD_INTEL_SKLSDLBRK config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - select CONSOLE_SERIAL select DRIVERS_UART - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7c2a7d7f35..a25cb8c579 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -18,16 +18,10 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" @@ -140,8 +134,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1" @@ -175,16 +167,6 @@ chip soc/intel/skylake # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0a" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -227,6 +209,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index f705b5488c..d8690764bf 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index f96add75b7..0d055ab0d2 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -8,7 +8,6 @@ #include "spd/spd.h" #include - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index d2dacd5eaf..6965066ab0 100644 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -5,7 +5,6 @@ #define DPTF_TSR0_PASSIVE 49 #define DPTF_TSR0_CRITICAL 75 - #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_PASSIVE 65 @@ -16,7 +15,6 @@ #define DPTF_TSR2_PASSIVE 49 #define DPTF_TSR2_CRITICAL 75 - #define DPTF_ENABLE_CHARGER /* Charger performance states, board-specific values from charger and EC */ diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index 0f4cdfaf6b..06229ede4b 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -12,8 +12,6 @@ * by pad number and which community it is in. */ - - /* family number in high byte and inner pad number in lowest byte */ void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index fb82091b62..d3d6168d15 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -68,7 +68,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_END }; - /* South West Community */ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_NC, /* 00 FST_SPI_D2 */ @@ -135,7 +134,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_END }; - /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 00 GPIO_DFX0 */ @@ -205,7 +203,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_END }; - /* East Community */ static const struct soc_gpio_map gpe_gpio_map[] = { Native_M1, /* 00 PMU_SLP_S3_B */ @@ -235,7 +232,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_END }; - static struct soc_gpio_config gpio_config = { /* BSW */ .north = gpn_gpio_map, diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index dd40848948..82f46294cb 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -20,7 +20,6 @@ static void mainboard_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 35bc012d17..bc2e7a278a 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -25,7 +25,6 @@ #define BOARD_TOUCH_IRQ 184 - /* Audio: Gpio index in SW bank */ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ @@ -43,8 +42,6 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 0 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ - - /* SD CARD gpio */ #define SDCARD_CD 81 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 867c88eb14..4d43e23454 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -7,17 +7,23 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI - select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_DTT select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI select PCIEXP_HOTPLUG + select HAVE_SPD_IN_CBFS + select SOC_INTEL_CSE_LITE_SKU + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 + select SPI_TPM config CHROMEOS bool @@ -28,6 +34,7 @@ config CHROMEOS select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB + select VBOOT_EARLY_EC_SYNC config MAINBOARD_DIR string @@ -46,7 +53,8 @@ config GBB_HWID config MAINBOARD_PART_NUMBER string - default "tglrvp" + default "tglrvpu" if BOARD_INTEL_TGLRVP_UP3 + default "tglrvpy" if BOARD_INTEL_TGLRVP_UP4 config MAINBOARD_FAMILY string @@ -76,7 +84,7 @@ config DIMM_SPD_SIZE int default 512 -choice TGL_EC +choice prompt "ON BOARD EC" default TGL_CHROME_EC help @@ -98,9 +106,16 @@ endchoice config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA config UART_FOR_CONSOLE int default 2 + +config DRIVER_TPM_SPI_BUS + default 0x2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 54 # GPE0_DW1_22 (GPP_C22) + endif diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 065bd4c3a2..2ca32f3760 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -14,10 +14,10 @@ romstage-y += board_id.c smm-y += smihandler.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c -subdirs-y += ../common subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl deleted file mode 100644 index 4670015928..0000000000 --- a/src/mainboard/intel/tglrvp/acpi/mainboard.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(EC_GOOGLE_CHROMEEC) -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} -#endif diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b053de..ffecfd2256 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -154,7 +154,7 @@ Scope (\_SB.PCI0.I2C3) Name (STA, Zero) Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(0,1) /* Clock 0, 19.2MHz */ @@ -170,12 +170,12 @@ Scope (\_SB.PCI0.I2C3) STXS(GPP_C15) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -187,7 +187,7 @@ Scope (\_SB.PCI0.I2C3) /* Pull PWREN low */ CTXS(GPP_B23) - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -369,7 +369,7 @@ Scope (\_SB.PCI0.I2C5) Name (STA, Zero) Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(1,1) /* Clock 1, 19.2MHz */ @@ -389,12 +389,12 @@ Scope (\_SB.PCI0.I2C5) STXS(GPP_H12) Sleep(1) /* t2 */ - Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -410,7 +410,7 @@ Scope (\_SB.PCI0.I2C5) CTXS(GPP_R6) #endif - Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index c8d6cd2c07..f3dee88627 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -3,7 +3,6 @@ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ - /* Board/FAB ID Command */ #define EC_FAB_ID_CMD 0x0D diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index e34fd58cc7..5b76bd49ba 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include /* global NVS and variables */ #include @@ -27,6 +27,7 @@ DefinitionBlock( #include #include #include + #include } } @@ -48,10 +49,6 @@ DefinitionBlock( #include - /* Mainboard specific */ - #include "acpi/mainboard.asl" - /* Camera */ - #include #include "acpi/mipi_camera.asl" } diff --git a/src/mainboard/intel/tglrvp/ec.c b/src/mainboard/intel/tglrvp/ec.c new file mode 100644 index 0000000000..14760017ef --- /dev/null +++ b/src/mainboard/intel/tglrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 7708b85188..82877ed28e 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,8 @@ static void mainboard_init(void *chip_info) pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + mainboard_ec_init(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c index 8c9444cb59..3d8107fed8 100644 --- a/src/mainboard/intel/tglrvp/smihandler.c +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex index 2ff9ed382e..4bf724e827 100644 --- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc index 8dd1507544..df52042e07 100644 --- a/src/mainboard/intel/tglrvp/spd/Makefile.inc +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -1,21 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = Micron-MT53D1G64D8SQ-046 SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex index 40fccaa76d..946bcc0015 100644 --- a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -1,11 +1,13 @@ -23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +20,6 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex index 945b2e8e06..946bcc0015 100644 --- a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -1,11 +1,13 @@ 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 -48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +20,6 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index 52db2afcf3..4303faf0d2 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -41,6 +41,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ @@ -54,6 +56,9 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index de0adf6cff..b61276c0c1 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,7 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a95a..384bc1bb6e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -9,11 +9,14 @@ chip soc/intel/tigerlake # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" + + # Enable heci1 communication + register "HeciEnabled" = "1" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 @@ -29,11 +32,9 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector - # CPU replacement check - register "CpuReplacementCheck" = "1" + # CPU replacement check + register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -85,14 +86,14 @@ chip soc/intel/tigerlake register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -114,12 +115,29 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" #HD Audio register "PchHdaDspEnable" = "1" @@ -134,6 +152,10 @@ chip soc/intel/tigerlake # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -142,7 +164,7 @@ chip soc/intel/tigerlake }, .i2c[2] = { .speed = I2C_SPEED_FAST, - }, + }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, @@ -155,7 +177,29 @@ chip soc/intel/tigerlake #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up3 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A04:U22/0x9A14:U42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 @@ -254,9 +298,20 @@ chip soc/intel/tigerlake device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 off end # GSPI0 0xA0AA - device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1e.2 on end # GSPI0 0xA0AA + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" + device spi 0 on end + end + end # GSPI1 0xA0AB + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden # PMC 0xA0A1 # The pmc_mux chip driver is a placeholder for the diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 44575067dc..c9de9c602c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,6 +54,11 @@ static const struct pad_config gpio_table[] = { /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + + /* EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */ + + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* AUDIO_PWREN */ }; /* Early pad configuration in bootblock */ @@ -89,6 +94,16 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* TPM */ + /* B19 : GSPI1_CS0B */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c119..410d06b38a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -9,8 +9,11 @@ chip soc/intel/tigerlake # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" + + # Enable heci1 communication + register "HeciEnabled" = "1" # FSP configuration register "SaGv" = "SaGv_Disabled" @@ -18,22 +21,21 @@ chip soc/intel/tigerlake register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector - # CPU replacement check - register "CpuReplacementCheck" = "1" + # CPU replacement check + register "CpuReplacementCheck" = "1" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -66,9 +68,16 @@ chip soc/intel/tigerlake # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + register "DdiPortCHpd" = "0" + register "DdiPortCDdc" = "0" register "DdiPort1Hpd" = "1" - register "DdiPort1Ddc" = "1" + register "DdiPort1Ddc" = "0" + register "DdiPort2Hpd" = "1" + register "DdiPort2Ddc" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -81,14 +90,14 @@ chip soc/intel/tigerlake register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -110,12 +119,29 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Processor Thermal Control + register "Device4Enable" = "1" + + # Add PL1 and PL2 values + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, + }" #HD Audio register "PchHdaDspEnable" = "1" @@ -130,6 +156,10 @@ chip soc/intel/tigerlake # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -151,13 +181,35 @@ chip soc/intel/tigerlake #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all tglrvp_up4 boards if not overridden + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + + # Power Limits Control + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # DPTF 0x9A02:Y22/0x9A12:Y42 + device pci 05.0 on end # IPU 0x9A19 device pci 06.0 on end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 off end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D @@ -250,11 +302,43 @@ chip soc/intel/tigerlake device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9 - device pci 1e.2 off end # GSPI0 0xA0AA - device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1e.2 on end # GSPI0 0xA0AA + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)" + device spi 0 on end + end + end # GSPI1 0xA0AB + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 + device pci 1f.2 hidden # PMC 0xA0A1 + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "6" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 679933a004..303350be27 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -51,6 +51,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* MECC_HPD2 */ + + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* AUDIO_PWREN */ }; /* Early pad configuration in bootblock */ @@ -86,6 +90,16 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* TPM */ + /* B19 : GSPI1_CS0B */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04d54..bff39b72eb 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ chip soc/intel/broadwell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000400" register "gpe0_en_2" = "0x00000000" diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 1ef94778a3..e83c0874e5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 006837aaf7..1a527d6178 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG - select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c index 37bb96828f..90221981dd 100644 --- a/src/mainboard/kontron/986lcd-m/early_init.c +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -63,7 +63,7 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ + pnp_write_config(dev, PNP_IDX_MSC5, 0xff); /* invert all GPIOs */ pnp_set_enable(dev, 1); dev = PNP_DEV(0x2e, W83627THG_GPIO2); @@ -73,9 +73,10 @@ void bootblock_mainboard_early_init(void) dev = PNP_DEV(0x2e, W83627THG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ - pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_MSC0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, PNP_IDX_MSC1, 0x00); /* GPIO bit 2 is 0 */ + /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + pnp_write_config(dev, PNP_IDX_EN, 0x03); dev = PNP_DEV(0x2e, W83627THG_FDC); pnp_set_logical_device(dev); diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index a5062e45b4..26a800aa5a 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -16,10 +16,8 @@ static u16 hwm_base = 0xa00; #define FAN_CRUISE_CONTROL_DISABLED 0 #define FAN_CRUISE_CONTROL_SPEED 1 #define FAN_CRUISE_CONTROL_THERMAL 2 - #define FAN_SPEED_5625 0 - struct fan_speed { u8 fan_in; u16 fan_speed; diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig new file mode 100644 index 0000000000..437c5a3e52 --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_KONTRON_BSL6 || BOARD_SIEMENS_BOXER26 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select EXCLUDE_NATIVE_SD_INTERFACE + select NO_FADT_8042 + select HAVE_ACPI_RESUME if BOARD_KONTRON_BSL6 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select EC_KONTRON_KEMPLD + select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_I2C_NCT7802Y + select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_BOXER26 + select SECUNET_DMI if BOARD_SIEMENS_BOXER26 + +config MAINBOARD_DIR + string + default "kontron/bsl6" + +config MAINBOARD_VENDOR + string + default "Siemens" if BOARD_SIEMENS_BOXER26 + +config MAINBOARD_PART_NUMBER + string + default "bSL6" if BOARD_KONTRON_BSL6 + default "Boxer26" if BOARD_SIEMENS_BOXER26 + +config VARIANT_DIR + string + default "bsl6" if BOARD_KONTRON_BSL6 + default "boxer26" if BOARD_SIEMENS_BOXER26 + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config CBFS_SIZE + hex + default 0x600000 if BOARD_SIEMENS_BOXER26 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name new file mode 100644 index 0000000000..0f0577e5db --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_KONTRON_BSL6 + bool "COMe-bSL6" + +config BOARD_SIEMENS_BOXER26 + bool "COMe-bSL6 on Siemens/Boxer26" diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc new file mode 100644 index 0000000000..1e12ee479b --- /dev/null +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/kontron/bsl6/acpi/ec.asl b/src/mainboard/kontron/bsl6/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/kontron/bsl6/acpi/superio.asl b/src/mainboard/kontron/bsl6/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/kontron/bsl6/board_info.txt b/src/mainboard/kontron/bsl6/board_info.txt new file mode 100644 index 0000000000..b1c4635055 --- /dev/null +++ b/src/mainboard/kontron/bsl6/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Board name: COMe-bSL6 +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/kontron/bsl6/bootblock.c b/src/mainboard/kontron/bsl6/bootblock.c new file mode 100644 index 0000000000..7dacd4aa8c --- /dev/null +++ b/src/mainboard/kontron/bsl6/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + kempld_enable_uart_for_console(); +} diff --git a/src/mainboard/kontron/bsl6/cmos.default b/src/mainboard/kontron/bsl6/cmos.default new file mode 100644 index 0000000000..2b66561959 --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.default @@ -0,0 +1,10 @@ +debug_level=Debug + +hyper_threading=Enable + +power_on_after_fail=Enable + +boot_devices=(hd0,0);(hd1,0) +boot_default=0xff + +cmos_defaults_loaded=No diff --git a/src/mainboard/kontron/bsl6/cmos.layout b/src/mainboard/kontron/bsl6/cmos.layout new file mode 100644 index 0000000000..e4bd05c43c --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 +442 1 e 2 ethernet3 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb new file mode 100644 index 0000000000..357f8fa1fa --- /dev/null +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "speed_shift_enable" = "1" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + register "PmConfigPciClockRun" = "1" + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + # VR Settings Configuration for 2 Domains + #+----------------+-------+-------+ + #| Domain/Setting | VCC | VCCGT | + #+----------------+-------+-------+ + #| Psi1Threshold | 20A | 20A | + #| Psi2Threshold | 5A | 5A | + #| Psi3Threshold | 1A | 1A | + #| Psi3Enable | 1 | 1 | + #| Psi4Enable | 1 | 1 | + #| ImonSlope | 0 | 0 | + #| ImonOffset | 0 | 0 | + #| IccMax | 55A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | + #| AcLoadline | 2.1 | 3.1 | + #| DcLoadline | 2.1 | 3.1 | + #+----------------+-------+-------+ + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(55), + .voltage_limit = 1520, + .ac_loadline = 210, + .dc_loadline = 210, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Vendor set Psys Pmax to 30W + register "power_limits_config" = "{ + .psys_pmax = 30, + }" + + # TODO + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on # USB xHCI + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + # SataPortsDevSlp not supported + end + device pci 19.0 off end # UART #2 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (COMe 0) + register "PcieRpEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 (COMe 1) + register "PcieRpEnable[9]" = "1" + end + device pci 1d.2 on # PCI Express Port 11 (COMe 2) + register "PcieRpEnable[10]" = "1" + end + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # EC/kempld at 0xa80/0xa81 + register "gen1_dec" = "0x00000a81" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/kontron/kempld + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + device generic 0.0 on end # UART #0 + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on # SMBus + chip drivers/i2c/nct7802y + device i2c 0x2e on end + end + end + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl new file mode 100644 index 0000000000..225c8a5ec9 --- /dev/null +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/kontron/bsl6/gpio.h b/src/mainboard/kontron/bsl6/gpio.h new file mode 100644 index 0000000000..a76c9679b9 --- /dev/null +++ b/src/mainboard/kontron/bsl6/gpio.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A21, 1, DEEP), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B6, 1, DEEP), + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PU, DEEP), + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_C2, NONE, DEEP, YES), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* XXX: C6 not readable */ + /* XXX: C7 not readable */ + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), + + PAD_CFG_GPO(GPP_D0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), + PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D19, 0, DEEP), + PAD_CFG_GPO(GPP_D20, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), + PAD_CFG_GPO(GPP_D22, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), + PAD_CFG_GPI_ACPI_SCI(GPP_E7, NONE, DEEP, YES), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, NONE), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + PAD_CFG_GPO(GPP_G0, 1, PLTRST), + PAD_CFG_GPO(GPP_G1, 1, PLTRST), + PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), + PAD_CFG_GPO(GPP_G4, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_G5, NONE, PLTRST), + PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, PLTRST, YES), + PAD_CFG_GPO(GPP_G7, 1, DEEP), + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, PLTRST, YES), + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, PLTRST, YES), + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), + PAD_CFG_GPO(GPP_G22, 1, PLTRST), + PAD_CFG_GPO(GPP_G23, 1, PLTRST), + + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO(GPP_H1, 1, DEEP), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), + PAD_CFG_GPO(GPP_H4, 1, DEEP), + PAD_CFG_GPO(GPP_H5, 1, DEEP), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 1, DEEP), + PAD_CFG_GPO(GPP_H8, 1, DEEP), + PAD_CFG_GPO(GPP_H9, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPD1, 0, PWROK), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c new file mode 100644 index 0000000000..2664a4ff82 --- /dev/null +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c new file mode 100644 index 0000000000..9d9169c0d2 --- /dev/null +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "variant.h" + +/* Rcomp resistor */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp target */ +static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; + + get_option(&memory_params->HyperThreading, "hyper_threading"); + + variant_memory_init_params(mupd); +} diff --git a/src/mainboard/kontron/bsl6/variant.h b/src/mainboard/kontron/bsl6/variant.h new file mode 100644 index 0000000000..4f65da5fb1 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variant.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include + +void variant_memory_init_params(FSPM_UPD *); + +#endif diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads new file mode 100644 index 0000000000..ea4750aa13 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP2, HDMI2, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb new file mode 100644 index 0000000000..9dd57e1987 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "SkipExtGfxScan" = "1" + + device domain 0 on + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/kontron/kempld + device generic 1.0 on # I2C + chip drivers/i2c/lm96000 + register "vin[1].low" = "1140*100/116" + register "vin[1].high" = "1260*100/116" + register "vin[0].low" = "1810" + register "vin[0].high" = "2000" + register "vin[2].low" = "3140" + register "vin[2].high" = "3470" + register "vin[3].low" = "4750" + register "vin[3].high" = "5250" + register "vin[4].low" = "11400" + register "vin[4].high" = "12600" + + register "fan_in[0].low" = "3240" + register "fan_in[1].low" = "3240" + + register "fan[0].mode" = "LM96000_FAN_MANUAL" + register "fan[0].spinup" = "LM96000_SPINUP_250MS" + register "fan[0].freq" = "LM96000_PWM_25_7KHZ" + register "fan[0].duty_cycle" = "100" + + register "fan[1].mode" = "LM96000_FAN_MANUAL" + register "fan[1].spinup" = "LM96000_SPINUP_250MS" + register "fan[1].freq" = "LM96000_PWM_25_7KHZ" + register "fan[1].duty_cycle" = "100" + + device i2c 0x2c on end + end + chip drivers/secunet/dmi + device i2c 0x57 on end # Serial EEPROM + end + end + end + end # LPC Interface + device pci 1f.4 on + chip drivers/i2c/nct7802y + register "fan[1].mode" = "FAN_MANUAL" + register "fan[1].duty_cycle" = "100" + end + end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE # Debug + end +end diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c new file mode 100644 index 0000000000..9c14d84ea7 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "../../variant.h" + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ + char nvram_var[] = "ethernetx"; + unsigned int i; + + for (i = 0; i < 3; ++i) { + u8 eth_enable = 1; + nvram_var[sizeof(nvram_var) - 2] = '1' + i; + get_option(ð_enable, nvram_var); + if (!eth_enable) { + printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i); + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8)); + } + } +} diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads new file mode 100644 index 0000000000..0cf02cd3b2 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb new file mode 100644 index 0000000000..718eff7f00 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3) + register "PcieRpEnable[ 0]" = "1" + register "PcieRpEnable[ 1]" = "1" + register "PcieRpEnable[ 2]" = "1" + register "PcieRpEnable[ 3]" = "1" + register "PcieRpEnable[11]" = "1" + + register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "SataPortsEnable[3]" = "1" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1f.4 on + chip drivers/i2c/nct7802y + register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_DUTY" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_PECI_0" + register "fan[1].smart.table" = "{ { 30, 40 }, + { 40, 48 }, + { 50, 60 }, + { 60, 76 } }" + register "fan[1].smart.critical_temp" = "80" + end + end # SMBus + end +end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c new file mode 100644 index 0000000000..8b32bf5bf6 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "../../variant.h" + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ +} diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 669577ef0d..d1aa9d5dc8 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -35,7 +36,7 @@ void bootblock_mainboard_early_init(void) const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_conf_state(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ + pnp_write_config(dev, PNP_IDX_EN, 0x03); /* Enable GPIO2+3 */ pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are GPIO27, 26, 25, 24 */ pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32, @@ -46,7 +47,8 @@ void bootblock_mainboard_early_init(void) /* Values can only be changed, when devices are enabled. */ pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */ pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ - pnp_write_config(dev, 0xf3, 0x40); /* Disable suspend LED during normal operation */ + /* Disable suspend LED during normal operation */ + pnp_write_config(dev, PNP_IDX_MSC3, 0x40); pnp_exit_conf_state(dev); } @@ -54,15 +56,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 2cca51e0a5..21a0941ccd 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -6,7 +6,6 @@ #include #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index 9ec85a07f0..910d2e66a8 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index 8339626b9f..d900c94069 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -26,7 +26,6 @@ static void mainboard_enable(struct device *dev) if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); - } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 9028555c1e..40b9a535b6 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -1,5 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + Method(_WAK,1) { /* ME may not be up yet. */ @@ -12,10 +25,3 @@ Method(_WAK,1) /* Not implemented. */ Return(Package(){0,0}) } - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/l520/acpi/superio.asl +++ b/src/mainboard/lenovo/l520/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 6f69102dbc..0f32e9f90c 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 93390c9112..bab1d54f39 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "0" register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "0" register "gpu_panel_power_backlight_on_delay" = "0" register "gpu_panel_power_cycle_delay" = "0" diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index 68e682fdbc..b5c6395f51 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -21,7 +21,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index f1e575f0a6..fde744ff4d 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/s230u/acpi/superio.asl b/src/mainboard/lenovo/s230u/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/s230u/acpi/superio.asl +++ b/src/mainboard/lenovo/s230u/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 6f4e6082d5..f3b8c27784 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "2000" register "gpu_panel_power_cycle_delay" = "5" diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 14b5a8bbe9..b26996e438 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -46,6 +46,5 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 5414f8b628..b8163e710b 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ static int poll_clk_stable(pnp_devfn_t dev, int timeout) { /* Enable 14.318MHz CLK on CLKIN */ pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) return 1; diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t410/acpi/superio.asl +++ b/src/mainboard/lenovo/t410/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 2de774d4b7..af770dc01c 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "1" register "gpu_panel_power_down_delay" = "600" diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 6856f5b3d9..445ef7afc0 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -32,7 +32,7 @@ static void hybrid_graphics_init(void) early_hybrid_graphics(&igd, &peg); /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); if (peg) @@ -42,9 +42,9 @@ static void hybrid_graphics_init(void) reg32 |= DEVEN_IGD; else /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } void mainboard_pre_raminit(void) diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index ade22ff980..08b5d2f909 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -23,7 +23,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { case 0x18: diff --git a/src/mainboard/lenovo/t420/acpi/superio.asl b/src/mainboard/lenovo/t420/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t420/acpi/superio.asl +++ b/src/mainboard/lenovo/t420/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5a96..ef40fc4dde 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index b04691dcc2..3df1e37f3e 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index b974f2a757..e72ef43617 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ b/src/mainboard/lenovo/t420s/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b3399c32a3..71068d0005 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "1" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index b974f2a757..e72ef43617 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index c9a48ad345..40b9a535b6 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -1,5 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + Method(_WAK,1) { /* ME may not be up yet. */ @@ -9,12 +22,6 @@ Method(_WAK,1) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + /* Not implemented. */ Return(Package(){0,0}) } - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t430/acpi/superio.asl +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 95eaa99337..f3524cd999 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/t430/gma-mainboard.ads b/src/mainboard/lenovo/t430/gma-mainboard.ads index b04691dcc2..3df1e37f3e 100644 --- a/src/mainboard/lenovo/t430/gma-mainboard.ads +++ b/src/mainboard/lenovo/t430/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 6b34105826..6f1568d16c 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T431S + select HAVE_SPD_IN_CBFS if BOARD_LENOVO_T431S # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/acpi/superio.asl b/src/mainboard/lenovo/t430s/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t430s/acpi/superio.asl +++ b/src/mainboard/lenovo/t430s/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 40c706eb0c..4bdb923b12 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index ae95e6c8d6..41bef2f70e 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 923e379dcd..60a1b01556 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc index 38d83d6be8..3926956fb7 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc +++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc @@ -1,18 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES = samsung_4gb # 0b0010 4GiB -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 32dde6fdcc..b84576de5e 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -3,7 +3,6 @@ if BOARD_LENOVO_THINKPAD_T440P config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 - select CPU_INTEL_HASWELL select EC_LENOVO_H8 select H8_HAS_PRIMARY_FN_KEYS select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 58f0ca82a1..8c356816ab 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" register "gpu_panel_power_backlight_off_delay" = "1" register "gpu_panel_power_backlight_on_delay" = "1" register "gpu_panel_power_cycle_delay" = "6" @@ -38,14 +37,6 @@ chip northbridge/intel/haswell register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8a" - register "pirqd_routing" = "0x89" - register "pirqe_routing" = "0x86" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x87" register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c index e0c19dc316..fac8400223 100644 --- a/src/mainboard/lenovo/t440p/hda_verb.c +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -5,8 +5,9 @@ const u32 cim_verb_data[] = { 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ 0x17aa220e, /* Subsystem ID */ - 12, /* Number of 4 dword sets */ + 32, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x17aa220e), + AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), @@ -18,6 +19,26 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x05350000, 0x0534601a, 0x05450000, 0x05442000, + 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, + 0x05350016, 0x05341ee1, 0x05450016, 0x05441ee1, + 0x05350023, 0x05341f7b, 0x05450023, 0x05441f7b, + 0x05350030, 0x05341fbd, 0x05450030, 0x05441fbd, + 0x05350000, 0x0534e01a, 0x05450030, 0x05441fbd, + 0x02050020, 0x02048014, 0x02050020, 0x02040014, + 0x05350000, 0x0534e01a, 0x05450000, 0x0544e01a, + 0x0205001c, 0x02046800, 0x0205006d, 0x0204aa10, + 0x02050076, 0x02040009, 0x0205006b, 0x02045029, + 0x0205006c, 0x0204a400, 0x02050018, 0x02047208, + 0x0205001a, 0x02049ad2, 0x02050014, 0x02040710, + 0x02050079, 0x02040b40, 0x02050070, 0x02048800, + 0x00b3f410, 0x00c3f11f, 0x00c3f001, 0x015707c0, + 0x0153b080, 0x01470740, 0x0143b000, 0x02050004, + 0x02040080, 0x01470c02, 0x000f0000, 0x000f0000, + 0x02050029, 0x02040050, 0x02050025, 0x0204ebc2, + 0x02050026, 0x02044028, 0x02050029, 0x02040250, + 0x000f0000, 0x000f0000, 0x02050005, 0x0204ff1f, }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index dce3ebd427..8cc5135e6f 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #define GPE_EC_SCI 1 @@ -20,7 +19,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t520/acpi/superio.asl +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 5128d06e4b..cc1e7f2999 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t530/acpi/superio.asl b/src/mainboard/lenovo/t530/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/t530/acpi/superio.asl +++ b/src/mainboard/lenovo/t530/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 1b16ca3b2c..e4655b2f29 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 378d673c25..363a43a8ba 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -75,7 +75,7 @@ int dlpc_init(void) /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -102,7 +102,7 @@ static int dock_superio_init(void) /* startup 14.318MHz Clock */ dock_write_register(0x29, 0xa0); /* wait until clock is settled */ - while(!(dock_read_register(0x29) & 0x10) && timeout--) + while (!(dock_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -147,7 +147,6 @@ static int dock_superio_init(void) dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP, 0x00); - /* no GPIO events enabled for PORT0 */ outb(0x00, 0x1622); /* clear GPIO events on PORT0 */ @@ -171,7 +170,7 @@ int dock_connect(void) timeout = 1000; - while(!(inb(DLPC_CONTROL) & 8) && timeout--) + while (!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c index ad2c58e26a..0a1ae53b72 100644 --- a/src/mainboard/lenovo/t60/early_init.c +++ b/src/mainboard/lenovo/t60/early_init.c @@ -25,7 +25,7 @@ static void early_superio_config(void) pnp_write_config(dev, 0x29, 0xa0); - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) udelay(1000); /* Enable COM1 */ diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 013c9b0a9d..69ffe33209 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -16,24 +17,32 @@ static void mainboard_smi_brightness_down(void) { - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; - if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) - *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; - } + uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf; + u8 *bar = (void *)(uintptr_t)reg32; + + /* Validate pointer before using it */ + if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t))) + return; + + printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; + if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) + *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; } static void mainboard_smi_brightness_up(void) { - u8 *bar; - if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); - *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; - if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) - *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; - } + uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf; + u8 *bar = (void *)(uintptr_t)reg32; + + /* Validate pointer before using it */ + if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t))) + return; + + printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; + if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) + *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; } int mainboard_io_trap_handler(int smif) @@ -90,7 +99,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { /* brightness up */ diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index 4905f1d133..b1f6e77558 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -52,7 +52,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl index 55b1db5b11..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x131e/acpi/superio.asl +++ b/src/mainboard/lenovo/x131e/acpi/superio.asl @@ -1,3 +1,3 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index c84d7ea87d..ddbfd98491 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "4" register "gpu_panel_power_up_delay" = "100" register "gpu_panel_power_down_delay" = "100" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index adb999430c..0bec670a2b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_PANEL_1_ON_LVDS select INTEL_GMA_HAVE_VBT + select HAVE_SPD_IN_CBFS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b3c11ea450..34eaa75c13 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_backlight_off_delay" = "2000" register "gpu_panel_power_backlight_on_delay" = "3000" register "gpu_panel_power_cycle_delay" = "6" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index e047c6ee58..d3244d1a9c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -1,20 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = elpida.hex # 0b0000 Single Channel 2GB -SPD_SOURCES += hynix.hex # 0b0001 2GiB -SPD_SOURCES += samsung.hex # 0b0010 4GiB -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f)) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +SPD_SOURCES = elpida # 0b0000 Single Channel 2GB +SPD_SOURCES += hynix # 0b0001 2GiB +SPD_SOURCES += samsung # 0b0010 4GiB diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.spd.hex diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.spd.hex diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex rename to src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.spd.hex diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 14b5a8bbe9..b26996e438 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -46,6 +46,5 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d374cec1a0..6b6543dee3 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "3" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_down_delay" = "250" diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index ade22ff980..08b5d2f909 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -23,7 +23,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { case 0x18: diff --git a/src/mainboard/lenovo/x220/acpi/superio.asl b/src/mainboard/lenovo/x220/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x220/acpi/superio.asl +++ b/src/mainboard/lenovo/x220/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index bfb9da355d..609036d61c 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index e4c854c734..bb120bfa0e 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,15 +12,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 5a3cf35346..03c899e0d9 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x230/acpi/superio.asl b/src/mainboard/lenovo/x230/acpi/superio.asl index f2b35ba9c1..ee2eabeb75 100644 --- a/src/mainboard/lenovo/x230/acpi/superio.asl +++ b/src/mainboard/lenovo/x230/acpi/superio.asl @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + #include diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 085b4e137b..27d42b68be 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index df01686190..81cbc487f6 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -20,7 +20,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 6d37aabc01..b2d0cf20a5 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -5,10 +5,10 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "4" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_backlight_off_delay" = "1" # 0.1ms register "gpu_panel_power_backlight_on_delay" = "1" # 0.1ms - register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_down_delay" = "500" # 50ms register "gpu_panel_power_up_delay" = "2000" # 200ms device domain 0 on diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 25c1aace8e..3abe5c1151 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -72,7 +72,7 @@ int dlpc_init(void) /* Enable 14.318MHz CLK on CLKIN */ dlpc_write_register(0x29, 0xa0); - while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + while (!(dlpc_read_register(0x29) & 0x10) && timeout--) udelay(1000); if (!timeout) @@ -99,7 +99,7 @@ int dock_connect(void) timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while (!(inb(0x164c) & 8) && timeout--) udelay(1000); if (!timeout) { @@ -121,7 +121,7 @@ int dock_connect(void) dock_write_register(0x29, 0x06); /* wait until clock is settled */ timeout = 1000; - while(!(dock_read_register(0x29) & 0x08) && timeout--) + while (!(dock_read_register(0x29) & 0x08) && timeout--) udelay(1000); if (!timeout) diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c index fc7394617b..3add1952cd 100644 --- a/src/mainboard/lenovo/x60/early_init.c +++ b/src/mainboard/lenovo/x60/early_init.c @@ -79,7 +79,6 @@ void mainboard_late_rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } - void mainboard_get_spd_map(u8 spd_map[4]) { spd_map[0] = 0x50; diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index f239b4cf1a..b5889db406 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -92,7 +92,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); switch (event) { /* brightness up */ diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 95874bb5fa..d47eca8a48 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,8 +38,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" @@ -49,18 +47,11 @@ chip soc/intel/skylake register "SataPortsDevSlp[1]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -69,15 +60,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------------+-------+ #| Domain/Setting | SA | IA | GT-Unsliced | GT | @@ -189,9 +171,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -216,6 +200,7 @@ chip soc/intel/skylake device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 on end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl index 5b3a5dfc8d..2a3876bd79 100644 --- a/src/mainboard/libretrend/lt1000/dsdt.asl +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 0021cfb668..55157eda52 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -1,13 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_LIPPERT_FRONTRUNNER_AF +if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_SMSC_SMSCSUPERIO + select SUPERIO_SMSC_SMSCSUPERIO if BOARD_LIPPERT_FRONTRUNNER_AF + # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. + # The ADLINK ExpressBase-6 baseboard happens to use this SIO: + select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -22,9 +25,19 @@ config MAINBOARD_DIR string default "lippert/frontrunner-af" +config VARIANT_DIR + string + default "frontrunner-af" if BOARD_LIPPERT_FRONTRUNNER_AF + default "toucan-af" if BOARD_LIPPERT_TOUCAN_AF + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "FrontRunner-AF" + default "FrontRunner-AF" if BOARD_LIPPERT_FRONTRUNNER_AF + default "Toucan-AF" if BOARD_LIPPERT_TOUCAN_AF config HW_MEM_HOLE_SIZEK hex @@ -54,4 +67,4 @@ config SB800_AHCI_ROM bool default n -endif # BOARD_LIPPERT_FRONTRUNNER_AF +endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name index 2a8cba52ab..caf65d1e65 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig.name +++ b/src/mainboard/lippert/frontrunner-af/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LIPPERT_FRONTRUNNER_AF bool "FrontRunner-AF aka ADLINK CoreModule2-GF" + +config BOARD_LIPPERT_TOUCAN_AF + bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 9b9e5aeb11..b05b4e8bcb 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -7,15 +7,16 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif -bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/bootblock.c romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c +romstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c +romstage-y += variants/$(VARIANT_DIR)/OemCustomize.c ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c +ramstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c +ramstage-y += variants/$(VARIANT_DIR)/OemCustomize.c +ramstage-y += variants/$(VARIANT_DIR)/mainboard.c # Minimal SEMA watchdog support romstage-y += sema.c diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl index 7b73e5db9c..f8b62fa0be 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl @@ -365,6 +365,7 @@ Scope(\_SB) { }) Name(PCIB, Package(){ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) /* PCI slots: slot 0, slot 1, slot 2, slot 3 behind Dev14, Fun4. */ Package(){0x0004FFFF, 0, 0, 0x14 }, Package(){0x0004FFFF, 1, 0, 0x15 }, @@ -382,5 +383,20 @@ Scope(\_SB) { Package(){0x0007FFFF, 1, 0, 0x14 }, Package(){0x0007FFFF, 2, 0, 0x15 }, Package(){0x0007FFFF, 3, 0, 0x16 }, +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0003FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 1, 0, 0x15 }, + Package(){0x0003FFFF, 2, 0, 0x16 }, + Package(){0x0003FFFF, 3, 0, 0x17 }, + Package(){0x0004FFFF, 0, 0, 0x15 }, + Package(){0x0004FFFF, 1, 0, 0x16 }, + Package(){0x0004FFFF, 2, 0, 0x17 }, + Package(){0x0004FFFF, 3, 0, 0x14 }, + Package(){0x0005FFFF, 0, 0, 0x16 }, + Package(){0x0005FFFF, 1, 0, 0x17 }, + Package(){0x0005FFFF, 2, 0, 0x14 }, + Package(){0x0005FFFF, 3, 0, 0x15 }, +#endif }) } diff --git a/src/mainboard/lippert/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/board_info.txt index 9246cdbc34..4a443cdaf0 100644 --- a/src/mainboard/lippert/frontrunner-af/board_info.txt +++ b/src/mainboard/lippert/frontrunner-af/board_info.txt @@ -1,5 +1,4 @@ Category: half -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 ROM package: SOIC8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 2b7c11a871..8c9a6b57f0 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1174,7 +1174,9 @@ DefinitionBlock ( ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) IO(Decode16, 0x0E00, 0x0E00, 1, 0x80) /* SIO runtime regs */ +#endif IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 7d4f1f944d..9f51c40462 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -45,7 +45,11 @@ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define USB_CONFIG 0x3F +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define USB_CONFIG 0x0F +#endif /** * @def PCI_CLOCK_CTRL @@ -58,7 +62,11 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define PCI_CLOCK_CTRL 0x1F +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define PCI_CLOCK_CTRL 0x1E +#endif /** * @def SATA_CONTROLLER @@ -148,12 +156,20 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define AZALIA_SDIN_PIN 0x02 +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define AZALIA_SDIN_PIN 0x2A +#endif /** * @def GPP_CONTROLLER */ +#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define GPP_CONTROLLER CIMX_OPTION_DISABLED +#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF) +#define GPP_CONTROLLER CIMX_OPTION_ENABLED +#endif /** * @def GPP_CFGMODE diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/BiosCallOuts.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/OemCustomize.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt new file mode 100644 index 0000000000..4a443cdaf0 --- /dev/null +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt @@ -0,0 +1,5 @@ +Category: half +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lippert/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/bootblock.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/frontrunner-af/devicetree.cb rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/mainboard.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c similarity index 100% rename from src/mainboard/lippert/toucan-af/BiosCallOuts.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c similarity index 100% rename from src/mainboard/lippert/toucan-af/OemCustomize.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c diff --git a/src/mainboard/lippert/toucan-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt similarity index 100% rename from src/mainboard/lippert/toucan-af/board_info.txt rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt diff --git a/src/mainboard/lippert/toucan-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c similarity index 100% rename from src/mainboard/lippert/toucan-af/bootblock.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb similarity index 100% rename from src/mainboard/lippert/toucan-af/devicetree.cb rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/toucan-af/mainboard.c rename to src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig deleted file mode 100644 index 102b1d7bc7..0000000000 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_LIPPERT_TOUCAN_AF - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. - # The ADLINK ExpressBase-6 baseboard happens to use this SIO: - select SUPERIO_WINBOND_W83627DHG - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - # This erases 28 KB and writes 10 KB register dumps to SPI flash on every - # boot, wasting 3 s and causing wear! Therefore disable S3 for now. - #select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - string - default "lippert/toucan-af" - -config MAINBOARD_PART_NUMBER - string - default "Toucan-AF" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 2 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config VGA_BIOS - bool - default n - -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - -config VGA_BIOS_ID - string - default "1002,9802" - -config SB800_AHCI_ROM - bool - default n - -endif # BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/toucan-af/Kconfig.name b/src/mainboard/lippert/toucan-af/Kconfig.name deleted file mode 100644 index 3481f92fba..0000000000 --- a/src/mainboard/lippert/toucan-af/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc deleted file mode 100644 index caabc74565..0000000000 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_AHCI_BIOS),y) -stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID)) -cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom -pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE)) -pci$(stripped_ahcibios_id).rom-type := optionrom -endif - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c - -# Minimal SEMA watchdog support -romstage-y += ../frontrunner-af/sema.c -ramstage-y += ../frontrunner-af/sema.c diff --git a/src/mainboard/lippert/toucan-af/acpi/routing.asl b/src/mainboard/lippert/toucan-af/acpi/routing.asl deleted file mode 100644 index 987ba225c9..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/routing.asl +++ /dev/null @@ -1,382 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Scope(\_SB) { - Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, INTC, 0 }, - Package(){0x0001FFFF, 1, INTD, 0 }, - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, INTB, 0 }, - Package(){0x0005FFFF, 1, INTC, 0 }, - Package(){0x0005FFFF, 2, INTD, 0 }, - Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, - }) - - Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - RS780 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - Package(){0x0001FFFF, 0, 0, 18 }, - Package(){0x0001FFFF, 1, 0, 19 }, - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - Package(){0x0004FFFF, 1, 0, 17 }, - Package(){0x0004FFFF, 2, 0, 18 }, - Package(){0x0004FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - Package(){0x0005FFFF, 1, 0, 18 }, - Package(){0x0005FFFF, 2, 0, 19 }, - Package(){0x0005FFFF, 3, 0, 16 }, - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 16 }, - Package(){0x0009FFFF, 2, 0, 17 }, - Package(){0x0009FFFF, 3, 0, 18 }, - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 16 }, - Package(){0x000AFFFF, 2, 0, 17 }, - Package(){0x000AFFFF, 3, 0, 18 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ - - /* TODO: pcie */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - }) - - Name(PR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, - }) - Name(APR1, Package(){ - /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, 0, 18 }, - Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ - }) - - Name(PS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS2, Package(){ - /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0003FFFF, 0, 0, 0x14 }, - Package(){0x0003FFFF, 1, 0, 0x15 }, - Package(){0x0003FFFF, 2, 0, 0x16 }, - Package(){0x0003FFFF, 3, 0, 0x17 }, - Package(){0x0004FFFF, 0, 0, 0x15 }, - Package(){0x0004FFFF, 1, 0, 0x16 }, - Package(){0x0004FFFF, 2, 0, 0x17 }, - Package(){0x0004FFFF, 3, 0, 0x14 }, - Package(){0x0005FFFF, 0, 0, 0x16 }, - Package(){0x0005FFFF, 1, 0, 0x17 }, - Package(){0x0005FFFF, 2, 0, 0x14 }, - Package(){0x0005FFFF, 3, 0, 0x15 }, - }) -} diff --git a/src/mainboard/lippert/toucan-af/acpi/sata.asl b/src/mainboard/lippert/toucan-af/acpi/sata.asl deleted file mode 100644 index 7f305fb17f..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/sata.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00110000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} diff --git a/src/mainboard/lippert/toucan-af/acpi/superio.asl b/src/mainboard/lippert/toucan-af/acpi/superio.asl deleted file mode 100644 index 490d8c49d5..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/superio.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * SuperI/O devices - */ - -/* PS/2 Keyboard */ -Device(KBC) { - Name(_HID, EISAID("PNP0303")) - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0060, 0x0060, 1, 1) - IO(Decode16, 0x0064, 0x0064, 1, 1) - IRQNoFlags(){1} - }) -} - -/* PS/2 Mouse */ -Device(PS2M) { - Name(_HID, EISAID("PNP0F13")) - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){12} - }) -} diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl deleted file mode 100644 index ca9e002a36..0000000000 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c deleted file mode 100644 index d8d46d499e..0000000000 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Select the CPU family */ -#define INSTALL_FAMILY_14_SUPPORT TRUE - -/* Select the CPU socket type */ -#define INSTALL_FT1_SOCKET_SUPPORT TRUE - -/* Agesa optional capabilities selection */ -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_WHEA FALSE - -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE - -/* Agesa configuration values selection */ -#include - -/* Include the files that instantiate the configuration definitions */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/* Instantiate all solution relevant data */ -#include diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl deleted file mode 100644 index 5b54b8c90e..0000000000 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ /dev/null @@ -1,1246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_SB) { /* define processor scope */ - Device (C000) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - } - Device (C001) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - } - Device (C002) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - } - Device (C003) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - } - } /* End _SB scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(OSFL, 0){ - - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - - if(CondRefOf(\_OSI)) - { - Store(1, OSVR) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSVR) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ - } Else { - Store(4, OSVR) /* Gotta be WinCE */ - } - } - Return(OSVR) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - /* Contains the supported sleep states for this chipset */ - #include - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) - - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - } - - /* USB controller PME# */ - Method(_L0B) { - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - #include /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method (_OSC, 4) - { - /* Check for PCI/PCI-X/PCIe GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } - } /* End _OSC */ - - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - #include "acpi/superio.asl" - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */ - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* Determine the OS we're running on */ - OSFL() - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - } - } /* End Scope SI */ -} -/* End of ASL file */ diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c deleted file mode 100644 index 5196caf33f..0000000000 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - u8 byte; - - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - /* Southbridge HD Audio: */ - PCI_INT(0x0, 0x14, 0x2, 0x12); - - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h deleted file mode 100644 index b029efb069..0000000000 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - -#ifndef _PLATFORM_CFG_H_ -#define _PLATFORM_CFG_H_ - -/** - * @def BIOS_SIZE - * BIOS_SIZE_{1,2,4,8,16}M - * - * In SB800, default ROM size is 1M Bytes, if your platform ROM - * bigger than 1M you have to set the ROM size outside CIMx module and - * before AGESA module get call. - */ -#ifndef BIOS_SIZE -#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) -#endif /* BIOS_SIZE */ - -/** - * @def SPREAD_SPECTRUM - * @brief - * 0 - Disable Spread Spectrum function - * 1 - Enable Spread Spectrum function - */ -#define SPREAD_SPECTRUM 0 - -/** - * @def SB_HPET_TIMER - * @brief - * 0 - Disable hpet - * 1 - Enable hpet - */ -#define HPET_TIMER 1 - -/** - * @def USB_CONFIG - * @brief bit[0-6] used to control USB - * 0 - Disable - * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 - */ -#define USB_CONFIG 0x0F - -/** - * @def PCI_CLOCK_CTRL - * @brief bit[0-4] used for PCI Slots Clock Control, - * 0 - disable - * 1 - enable - * PCI SLOT 0 define at BIT0 - * PCI SLOT 1 define at BIT1 - * PCI SLOT 2 define at BIT2 - * PCI SLOT 3 define at BIT3 - * PCI SLOT 4 define at BIT4 - */ -#define PCI_CLOCK_CTRL 0x1E - -/** - * @def SATA_CONTROLLER - * @brief INCHIP Sata Controller - */ -#define SATA_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def SATA_MODE - * @brief INCHIP Sata Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_MODE CONFIG_SB800_SATA_MODE - -/** - * @brief INCHIP Sata IDE Controller Mode - */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 - -/** - * @def SATA_IDE_MODE - * @brief INCHIP Sata IDE Controller Mode - * NOTE: DO NOT ALLOW SATA & IDE use same mode - */ -#define SATA_IDE_MODE IDE_LEGACY_MODE - -/** - * @def EXTERNAL_CLOCK - * @brief 00/10: Reference clock from crystal oscillator via - * PAD_XTALI and PAD_XTALO - * - * @def INTERNAL_CLOCK - * @brief 01/11: Reference clock from internal clock through - * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL - */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 - -/* NOTE: inagua have to using internal clock, - * otherwise can not detect sata drive - */ -#define SATA_CLOCK_SOURCE INTERNAL_CLOCK - -/** - * @def SATA_PORT_MULT_CAP_RESERVED - * @brief 1 ON, 0 0FF - */ -#define SATA_PORT_MULT_CAP_RESERVED 1 - - -/** - * @def AZALIA_AUTO - * @brief Detect Azalia controller automatically. - * - * @def AZALIA_DISABLE - * @brief Disable Azalia controller. - - * @def AZALIA_ENABLE - * @brief Enable Azalia controller. - */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @brief INCHIP HDA controller - */ -#define AZALIA_CONTROLLER AZALIA_AUTO - -/** - * @def AZALIA_PIN_CONFIG - * @brief - * 0 - disable - * 1 - enable - */ -#define AZALIA_PIN_CONFIG 1 - -/** - * @def AZALIA_SDIN_PIN - * @brief - * SDIN0 is define at BIT0 & BIT1 - * 00 - GPIO PIN - * 01 - Reserved - * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 - */ -#define AZALIA_SDIN_PIN 0x2A - -/** - * @def GPP_CONTROLLER - */ -#define GPP_CONTROLLER CIMX_OPTION_ENABLED - -/** - * @def GPP_CFGMODE - * @brief GPP Link Configuration - * four possible configuration: - * GPP_CFGMODE_X4000 - * GPP_CFGMODE_X2200 - * GPP_CFGMODE_X2110 - * GPP_CFGMODE_X1111 - */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 - -/** - * @def NB_SB_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define NB_SB_GEN2 TRUE - -/** - * @def SB_GPP_GEN2 - * 0 - Disable - * 1 - Enable - */ -#define SB_GPP_GEN2 TRUE - -/** - * @def SB_GPP_UNHIDE_PORTS - * TRUE - ports visible always, even port empty - * FALSE - ports invisible if port empty - */ -#define SB_GPP_UNHIDE_PORTS FALSE - -/** - * @def GEC_CONFIG - * 0 - Enable - * 1 - Disable - */ -#define GEC_CONFIG 1 - -static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */ -{ - /* NID, PinConfig (Verbs 71F..C) */ - {0x11, 0x411111F0}, /* NPC */ - {0x12, 0x411111F0}, /* DMIC */ - {0x14, 0x01214110}, /* FRONT (Port-D) */ - {0x15, 0x01011112}, /* SURR (Port-A) */ - {0x16, 0x01016111}, /* CEN/LFE (Port-G) */ - {0x17, 0x411111F0}, /* SIDESURR (Port-H) */ - {0x18, 0x01A19930}, /* MIC1 (Port-B) */ - {0x19, 0x411111F0}, /* MIC2 (Port-F) */ - {0x1A, 0x0181313F}, /* LINE1 (Port-C) */ - {0x1B, 0x411111F0}, /* LINE2 (Port-E) */ - {0x1C, 0x411111F0}, /* CD-IN */ - {0x1D, 0x40132601}, /* BEEP-IN */ - {0x1E, 0x01441120}, /* S/PDIF-OUT */ - {0x1F, 0x01C46140}, /* S/PDIF-IN */ - {0xff, 0xffffffff} /* end of table */ -}; - -static const CODECTBLLIST codec_tablelist[] = -{ - {0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]}, - {0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL} -}; - -/** - * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific codec verb table list - */ -#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) - -#endif diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 1df5b8c7ba..ae7a945921 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -6,7 +6,6 @@ #include #include - /* * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * @@ -170,7 +169,6 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { PSO_END }; - void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; diff --git a/src/mainboard/msi/ms7721/bootblock.c b/src/mainboard/msi/ms7721/bootblock.c index e60353c925..0de0c58f3d 100644 --- a/src/mainboard/msi/ms7721/bootblock.c +++ b/src/mainboard/msi/ms7721/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -20,7 +21,7 @@ static void gpio_init(pnp_devfn_t dev) pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0x60, 0x0a); //Base addr high + pnp_write_config(dev, PNP_IDX_IO0, 0x0a); //Base addr high pnp_write_config(dev, 0x61, 0x00); //Base addr low pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 8a1cc03a0e..6f96ed8f0f 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index b4e88b51ed..ff5599c007 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,7 +3,6 @@ if BOARD_OCP_DELTALAKE config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select FSP_CAR select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP @@ -13,6 +12,16 @@ config BOARD_SPECIFIC_OPTIONS select OCP_DMI select VPD select VPD_SMBIOS_VERSION + select IPMI_OCP + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 1 + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + default n config IPMI_KCS_REGISTER_SPACING int @@ -36,6 +45,15 @@ config MAX_SOCKET config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +# Deltalake is single socket server, the platform design has 1 DIMM per channel +config DIMM_MAX + int + default 6 + +config CONSOLE_POST + bool + default y endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 4fb50b2e2c..be6af246ed 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -8,5 +8,5 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c index 8004170a5e..402b572873 100644 --- a/src/mainboard/ocp/deltalake/bootblock.c +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include #define ASPEED_SIO_PORT 0x2E @@ -52,6 +52,9 @@ static uint8_t com_to_ast_sio(uint8_t com) void bootblock_mainboard_early_init(void) { + /* pre-configure Lewisburg PCH GPIO pads */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + /* Open IO windows */ enable_espi_lpc_io_windows(); diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index cc17e06f6c..d51391da42 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -33,8 +33,9 @@ chip soc/intel/xeon_sp/cpx # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL register "pstate_req_ratio" = "0xa" - register "coherency_support" = "0" - register "ats_support" = "0" + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS @@ -85,6 +86,12 @@ chip soc/intel/xeon_sp/cpx register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" end + chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end end # ISA bridge: Intel Device a245 device pci 1f.1 on end # p2sb device pci 1f.2 on end # Memory controller: Intel Device a221 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c74b5fecb8..9fff558c46 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -14,10 +14,16 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include #include // CPX-SP ACPI tables - #include + #include + + // LPC related entries + Scope (\_SB.PC00) + { + #include + } } diff --git a/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h new file mode 100644 index 0000000000..6a31c74058 --- /dev/null +++ b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, NONE, RSMRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, RSMRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, RSMRST, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A7, NONE, RSMRST, NF1), /* PIRQA# */ + PAD_CFG_NF(GPP_A8, NONE, RSMRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, NONE, RSMRST, NF1), /* CLKOUT_LPC0 */ + PAD_NC(GPP_A10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A11, NONE, RSMRST, NF1), /* PME# */ + PAD_CFG_GPI_SCI(GPP_A12, NONE, RSMRST, OFF, NONE), /* GPIO */ + PAD_NC(GPP_A13, NONE), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_NC(GPP_A17, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_NC(GPP_A21, NONE), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_NC(GPP_A23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, NONE), /* GPIO */ + PAD_NC(GPP_B1, NONE), /* GPIO */ + PAD_NC(GPP_B2, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_B11 - RESERVED */ + PAD_CFG_NF(GPP_B12, NONE, RSMRST, NF1), /* GLB_RST_WARN_N# */ + PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, RSMRST, NF1), /* SPKR */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 0, RSMRST), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* PCHHOT# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), /* GPIO */ + PAD_NC(GPP_F1, NONE), /* GPIO */ + PAD_NC(GPP_F2, NONE), /* GPIO */ + PAD_NC(GPP_F3, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_NC(GPP_F7, NONE), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_NC(GPP_F9, NONE), /* GPIO */ + PAD_NC(GPP_F10, NONE), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_NC(GPP_F20, NONE), /* GPIO */ + PAD_NC(GPP_F21, NONE), /* GPIO */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, RSMRST, LEVEL, ACPI), /* GPIO */ + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_NF(GPP_C5, NONE, RSMRST, NF1), /* SML0ALERT# */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + /* GPP_C20 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_SMI(GPP_C22, NONE, RSMRST, LEVEL, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D4, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_D5, NONE), /* GPIO */ + PAD_NC(GPP_D6, NONE), /* GPIO */ + PAD_NC(GPP_D7, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D9, NONE), /* GPIO */ + PAD_NC(GPP_D10, NONE), /* GPIO */ + PAD_NC(GPP_D11, NONE), /* GPIO */ + PAD_NC(GPP_D12, NONE), /* GPIO */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPIO */ + PAD_NC(GPP_D20, NONE), /* GPIO */ + PAD_NC(GPP_D21, NONE), /* GPIO */ + PAD_NC(GPP_D22, NONE), /* GPIO */ + PAD_NC(GPP_D23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* CPU_GP0 */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_NC(GPP_E6, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1), /* USB_OC0# */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + + /* ------- GPIO Community 2 ------- */ + /* -------- GPIO Group GPD -------- */ + /* GPD0 - RESERVED */ + PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* ACPRESENT */ + PAD_NC(GPD2, NONE), /* GPIO */ + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */ + PAD_NC(GPD6, NONE), /* GPIO */ + PAD_NC(GPD7, NONE), /* GPIO */ + PAD_NC(GPD8, NONE), /* GPIO */ + PAD_NC(GPD9, NONE), /* GPIO */ + PAD_NC(GPD10, NONE), /* GPIO */ + PAD_NC(GPD11, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_NC(GPP_I7, NONE), /* GPIO */ + PAD_NC(GPP_I8, NONE), /* GPIO */ + PAD_NC(GPP_I9, NONE), /* GPIO */ + PAD_NC(GPP_I10, NONE), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_J ------- */ + PAD_NC(GPP_J0, NONE), /* GPIO */ + PAD_NC(GPP_J1, NONE), /* GPIO */ + PAD_NC(GPP_J2, NONE), /* GPIO */ + PAD_NC(GPP_J3, NONE), /* GPIO */ + PAD_NC(GPP_J4, NONE), /* GPIO */ + PAD_NC(GPP_J5, NONE), /* GPIO */ + PAD_NC(GPP_J6, NONE), /* GPIO */ + PAD_NC(GPP_J7, NONE), /* GPIO */ + PAD_NC(GPP_J8, NONE), /* GPIO */ + PAD_NC(GPP_J9, NONE), /* GPIO */ + PAD_NC(GPP_J10, NONE), /* GPIO */ + PAD_NC(GPP_J11, NONE), /* GPIO */ + PAD_NC(GPP_J12, NONE), /* GPIO */ + PAD_NC(GPP_J13, NONE), /* GPIO */ + PAD_NC(GPP_J14, NONE), /* GPIO */ + PAD_NC(GPP_J15, NONE), /* GPIO */ + PAD_NC(GPP_J16, NONE), /* GPIO */ + PAD_NC(GPP_J17, NONE), /* GPIO */ + PAD_NC(GPP_J18, NONE), /* GPIO */ + PAD_NC(GPP_J19, NONE), /* GPIO */ + PAD_NC(GPP_J20, NONE), /* GPIO */ + PAD_NC(GPP_J21, NONE), /* GPIO */ + PAD_NC(GPP_J22, NONE), /* GPIO */ + PAD_NC(GPP_J23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), /* GPIO */ + PAD_NC(GPP_K1, NONE), /* GPIO */ + PAD_NC(GPP_K2, NONE), /* GPIO */ + PAD_NC(GPP_K3, NONE), /* GPIO */ + PAD_NC(GPP_K4, NONE), /* GPIO */ + PAD_NC(GPP_K5, NONE), /* GPIO */ + PAD_NC(GPP_K6, NONE), /* GPIO */ + PAD_NC(GPP_K7, NONE), /* GPIO */ + PAD_NC(GPP_K8, NONE), /* GPIO */ + PAD_NC(GPP_K9, NONE), /* GPIO */ + PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1), /* PE_RST# */ + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), /* GPIO */ + PAD_NC(GPP_G1, NONE), /* GPIO */ + PAD_NC(GPP_G2, NONE), /* GPIO */ + PAD_NC(GPP_G3, NONE), /* GPIO */ + PAD_NC(GPP_G4, NONE), /* GPIO */ + PAD_NC(GPP_G5, NONE), /* GPIO */ + PAD_NC(GPP_G6, NONE), /* GPIO */ + PAD_NC(GPP_G7, NONE), /* GPIO */ + PAD_NC(GPP_G8, NONE), /* GPIO */ + PAD_NC(GPP_G9, NONE), /* GPIO */ + PAD_NC(GPP_G10, NONE), /* GPIO */ + PAD_NC(GPP_G11, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_G17, NONE, RSMRST, NF1), /* ADR_COMPLETE */ + PAD_CFG_NF(GPP_G18, NONE, RSMRST, NF1), /* NMI# */ + PAD_CFG_NF(GPP_G19, NONE, RSMRST, NF1), /* SMI# */ + /* GPP_G20 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_G22, NONE), /* GPIO */ + PAD_NC(GPP_G23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_H2, NONE), /* GPIO */ + PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_H19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2), /* SSATAXPCIE2 */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* CSME_INTR_OUT */ + PAD_CFG_NF(GPP_L2, NONE, RSMRST, NF1), /* TESTCH0_D0 */ + PAD_CFG_NF(GPP_L3, NONE, RSMRST, NF1), /* TESTCH0_D1 */ + PAD_CFG_NF(GPP_L4, NONE, RSMRST, NF1), /* TESTCH0_D2 */ + PAD_CFG_NF(GPP_L5, NONE, RSMRST, NF1), /* TESTCH0_D3 */ + PAD_CFG_NF(GPP_L6, NONE, RSMRST, NF1), /* TESTCH0_D4 */ + PAD_CFG_NF(GPP_L7, NONE, RSMRST, NF1), /* TESTCH0_D5 */ + PAD_CFG_NF(GPP_L8, NONE, RSMRST, NF1), /* TESTCH0_D6 */ + PAD_CFG_NF(GPP_L9, NONE, RSMRST, NF1), /* TESTCH0_D7 */ + PAD_CFG_NF(GPP_L10, NONE, RSMRST, NF1), /* TESTCH0_CLK */ + PAD_NC(GPP_L11, NONE), /* GPIO */ + PAD_NC(GPP_L12, NONE), /* GPIO */ + PAD_NC(GPP_L13, NONE), /* GPIO */ + PAD_NC(GPP_L14, NONE), /* GPIO */ + PAD_NC(GPP_L15, NONE), /* GPIO */ + PAD_NC(GPP_L16, NONE), /* GPIO */ + PAD_NC(GPP_L17, NONE), /* GPIO */ + PAD_NC(GPP_L18, NONE), /* GPIO */ + PAD_NC(GPP_L19, NONE), /* GPIO */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ + PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ + PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ + PAD_CFG_NF(GPP_A4, NONE, RSMRST, NF1), /* LAD3 */ + PAD_CFG_NF(GPP_A5, NONE, RSMRST, NF1), /* LFRAME# */ + PAD_CFG_NF(GPP_A6, NONE, RSMRST, NF1), /* SERIRQ */ + PAD_CFG_NF(GPP_A8, NONE, RSMRST, NF1), /* CLKRUN# */ + PAD_CFG_NF(GPP_A9, NONE, RSMRST, NF1), /* CLKOUT_LPC0 */ + PAD_NC(GPP_A10, NONE), /* GPIO */ + PAD_NC(GPP_A13, NONE), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_NC(GPP_A15, NONE), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index 19a85d567c..415b26d5d8 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -75,21 +75,43 @@ enum cb_err ipmi_get_slot_id(uint8_t *slot_id) return CB_SUCCESS; } +enum cb_err ipmi_set_post_start(const int port) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(port, IPMI_NETFN_OEM, 0x0, + IPMI_BMC_SET_POST_START, NULL, 0, (u8 *) &rsp, + sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d rsp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + if (ret != sizeof(rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return CB_ERR; + } + + printk(BIOS_DEBUG, "IPMI BMC POST is started\n"); + return CB_SUCCESS; +} + void init_frb2_wdt(void) { - char val[VPD_LEN]; - /* Enable FRB2 timer by default. */ - u8 enable = 1; + uint8_t enable, action; uint16_t countdown; if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { - if (!enable) { - printk(BIOS_DEBUG, "Disable FRB2 timer\n"); - ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); - return; - } + printk(BIOS_DEBUG, "Got VPD %s value: %d\n", FRB2_TIMER, enable); + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set to %d\n", FRB2_TIMER, + FRB2_TIMER_DEFAULT); + enable = FRB2_TIMER_DEFAULT; } + if (enable) { if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { countdown = (uint16_t)atol(val); @@ -97,10 +119,69 @@ void init_frb2_wdt(void) countdown * 100); } else { printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", - DEFAULT_COUNTDOWN * 100); - countdown = DEFAULT_COUNTDOWN; + FRB2_COUNTDOWN_DEFAULT * 100); + countdown = FRB2_COUNTDOWN_DEFAULT; } - ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, - TIMEOUT_HARD_RESET); + + if (vpd_gets(FRB2_ACTION, val, VPD_LEN, VPD_RW_THEN_RO)) { + action = (uint8_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer action set to: %d\n", action); + } else { + printk(BIOS_DEBUG, "FRB2 timer action use default value: %d\n", + FRB2_ACTION_DEFAULT); + action = FRB2_ACTION_DEFAULT; + } + ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, action); + } else { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); } } + +enum cb_err ipmi_set_cmos_clear(void) +{ + int ret; + + struct ipmi_oem_rsp { + struct ipmi_rsp resp; + struct boot_order data; + } __packed; + + struct ipmi_oem_rsp rsp; + struct boot_order req; + + /* IPMI OEM get bios boot order command to check if the valid bit and + the CMOS clear bit are both set from the response BootMode byte. */ + + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_GET_BIOS_BOOT_ORDER, + NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (read ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + if (!IS_CMOS_AND_VALID_BIT(rsp.data.boot_mode)) { + req = rsp.data; + SET_CMOS_AND_VALID_BIT(req.boot_mode); + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_SET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (sent ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + printk(BIOS_INFO, "IPMI CMOS clear requested because CMOS data is invalid.\n"); + + return CB_SUCCESS; + } + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index 840f999990..440a5056ba 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -9,6 +9,15 @@ #define IPMI_OEM_SET_PPIN 0x77 #define IPMI_OEM_GET_PCIE_CONFIG 0xf4 #define IPMI_OEM_GET_BOARD_ID 0x37 +#define IPMI_BMC_SET_POST_START 0x73 +#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 +#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 + +#define CMOS_BIT (1 << 1) +#define VALID_BIT (1 << 7) +#define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= ~(CMOS_BIT | VALID_BIT)) +#define SET_CMOS_AND_VALID_BIT(x) ((x) |= (CMOS_BIT | VALID_BIT)) +#define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) enum config_type { PCIE_CONFIG_UNKNOWN = 0x0, @@ -25,8 +34,19 @@ struct ppin_req { uint32_t cpu1_hi; } __packed; +struct boot_order { + uint8_t boot_mode; + uint8_t boot_dev0; + uint8_t boot_dev1; + uint8_t boot_dev2; + uint8_t boot_dev3; + uint8_t boot_dev4; +} __packed; + enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); enum cb_err ipmi_get_slot_id(uint8_t *slot_id); +enum cb_err ipmi_set_post_start(const int port); void init_frb2_wdt(void); +enum cb_err ipmi_set_cmos_clear(void); #endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 88f89b5817..74a4468626 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,7 +8,16 @@ #include #include #include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include #include "ipmi.h" @@ -34,15 +44,63 @@ const char *smbios_mainboard_location_in_chassis(void) return slot_id_str; } +/* System Slot Socket, Stack, Type and Data bus width Information */ +typedef struct { + u8 stack; + u8 slot_type; + u8 slot_data_bus_width; + u8 dev_func; + const char *slot_designator; +} slot_info; + +slot_info slotinfo[] = { + {CSTACK, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "SSD1_M2_Data_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "SSD0_M2_Boot_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "BB_OCP_NIC"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1OU_JD2_M2_3"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1OU_JD1_M2_1"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD1_M2_1"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2OU_JD3_M2_4"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2OU_JD3_M2_5"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD2_M2_3"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "1OU_OCP_NIC"}, +}; + +#define SPD_REGVID_LEN 6 +/* A 4-digit long number plus a space */ +static void write_oem_word(uint16_t val, char *str) +{ + snprintf(str, SPD_REGVID_LEN, "%04x ", val); +} + static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { uint8_t pcie_config = 0; + const struct SystemMemoryMapHob *hob; + char spd_reg_vid[SPD_REGVID_LEN]; + char empty[1] = ""; + char *oem_str7 = empty; /* OEM string 1 to 6 */ ocp_oem_smbios_strings(dev, t); - /* TODO: Add real OEM string 7, add TBF for now */ - t->count = smbios_add_oem_string(t->eos, TBF); + /* OEM string 7 is the register vendor ID in SPD for each DIMM strung together */ + hob = get_system_memory_map(); + assert(hob != NULL); + /* There are at most 6 channels and 2 DIMMs per channel, but Delta Lake has 6 DIMMs, + e.g. b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + write_oem_word(hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm].SPDRegVen, + spd_reg_vid); + oem_str7 = strconcat(oem_str7, spd_reg_vid); + } + } + t->count = smbios_add_oem_string(t->eos, oem_str7); /* Add OEM string 8 */ if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { @@ -70,14 +128,145 @@ static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) } } +static int create_smbios_type9(int *handle, unsigned long *current) +{ + int index; + int length = 0; + uint8_t slot_length; + uint8_t sec_bus; + uint8_t slot_usage; + uint8_t pcie_config = 0; + uint8_t characteristics_1 = 0; + uint8_t characteristics_2 = 0; + uint32_t vendor_device_id; + uint32_t stack_busnos[6]; + pci_devfn_t pci_dev; + unsigned int cap; + uint16_t sltcap; + + if (ipmi_get_pcie_config(&pcie_config) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); + + get_stack_busnos(stack_busnos); + + for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { + if (pcie_config == PCIE_CONFIG_A) { + if (index == 0 || index == 1 || index == 2) + printk(BIOS_INFO, "Find Config-A slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_B) { + if (index == 0 || index == 1 || index == 2 || index == 3 || index == 4 + || index == 5 || index == 6) + printk(BIOS_INFO, "Find Config-B slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_C) { + if (index == 0 || index == 1 || index == 7 || index == 8 || index == 9 + || index == 10 || index == 11 || index == 12 || index == 13) + printk(BIOS_INFO, "Find Config-C slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + if (pcie_config == PCIE_CONFIG_D) { + if (index != 13) + printk(BIOS_INFO, "Find Config-D slot: %s\n", + slotinfo[index].slot_designator); + else + continue; + } + + if (slotinfo[index].slot_data_bus_width == SlotDataBusWidth16X) + slot_length = SlotLengthLong; + else + slot_length = SlotLengthShort; + + pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack], + slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7); + sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + + if (sec_bus == 0xFF) { + slot_usage = SlotUsageUnknown; + } else { + /* Checking for Slot device availability */ + pci_dev = PCI_DEV(sec_bus, 0, 0); + vendor_device_id = pci_s_read_config32(pci_dev, 0); + if (vendor_device_id == 0xFFFFFFFF) + slot_usage = SlotUsageAvailable; + else + slot_usage = SlotUsageInUse; + } + + characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts + characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported + + cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) + characteristics_2 |= SMBIOS_SLOT_HOTPLUG; + + length += smbios_write_type9(current, handle, + slotinfo[index].slot_designator, + slotinfo[index].slot_type, + slotinfo[index].slot_data_bus_width, + slot_usage, + slot_length, + characteristics_1, + characteristics_2, + stack_busnos[slotinfo[index].stack], + slotinfo[index].dev_func); + } + + return length; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + len += create_smbios_type9(handle, current); + + return len; +} + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char buf[40]; + + snprintf(buf, sizeof(buf), "DIMM %c0", 'A' + dimm->channel_num); + t->device_locator = smbios_add_string(t->eos, buf); + + snprintf(buf, sizeof(buf), "_Node0_Channel%d_Dimm0", dimm->channel_num); + t->bank_locator = smbios_add_string(t->eos, buf); +} + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return 0xb3; /* Xeon */ +} + +unsigned int smbios_processor_characteristics(void) +{ + /* 64-bit Capable, Multi-Core, Power/Performance Control */ + return 0x8c; /* BIT2 + BIT3 + BIT7 */ +} + static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings, read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); + dev->ops->get_smbios_data = mainboard_smbios_data; } void mainboard_silicon_init_params(FSPS_UPD *params) { + /* configure Lewisburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } static void mainboard_final(void *chip_info) diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2c8dc5efa2..71a26c8789 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "chip.h" #include "ipmi.h" @@ -18,16 +19,46 @@ static void mainboard_config_upd(FSPM_UPD *mupd) { uint8_t val; + char val_str[VPD_LEN]; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) mupd->FspmConfig.SerialIoUartDebugEnable = val; else { printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to 1\n", FSP_LOG); - mupd->FspmConfig.SerialIoUartDebugEnable = 1; + "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; } mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + /* FSP debug log level */ + if (vpd_gets(FSP_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 0x0f) { + printk(BIOS_DEBUG, "Invalid DebugPrintLevel value from VPD: " + "%d\n", val); + val = FSP_LOG_LEVEL_DEFAULT; + } + printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val); + mupd->FspmConfig.DebugPrintLevel = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DebugPrintLevel to %d\n", FSP_LOG_LEVEL, + FSP_LOG_LEVEL_DEFAULT); + mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT; + } + } + + /* Enable DCI */ + if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) { + printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val); + mupd->FspmConfig.PchDciEn = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); + mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; + } } /* Update bifurcation settings according to different Configs */ @@ -96,10 +127,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ - if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { + ipmi_set_post_start(CONFIG_BMC_KCS_BASE); init_frb2_wdt(); + } mainboard_config_gpios(mupd); mainboard_config_iio(mupd); mainboard_config_upd(mupd); } + +void mainboard_rtc_failed(void) +{ + if (ipmi_set_cmos_clear() == CB_SUCCESS) + printk(BIOS_DEBUG, "%s: IPMI set cmos clear successful\n", __func__); + else + printk(BIOS_ERR, "%s: IPMI set cmos clear failed\n", __func__); +} diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 9e17bb9b80..ae2099d025 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -3,15 +3,33 @@ #ifndef DELTALAKE_VPD_H #define DELTALAKE_VPD_H -/* VPD variable for enabling/disabling FRB2 timer. */ -#define FRB2_TIMER "frb2_timer" +/* VPD variable maximum length */ +#define VPD_LEN 10 + +/* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */ +#define FRB2_TIMER "frb2_timer_enable" +#define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */ + /* VPD variable for setting FRB2 timer countdown value. */ #define FRB2_COUNTDOWN "frb2_countdown" -#define VPD_LEN 10 -/* Default countdown is 15 minutes. */ -#define DEFAULT_COUNTDOWN 9000 +/* Default countdown is 15 minutes when the VPD variable is not found */ +#define FRB2_COUNTDOWN_DEFAULT 9000 + +/* VPD variable for setting FRB2 timer action. + 0: No action, 1: hard reset, 2: power down, 3: power cycle */ +#define FRB2_ACTION "frb2_action" +#define FRB2_ACTION_DEFAULT 0 /* Default no action when the VPD variable is not found */ /* Define the VPD keys for UPD variables that can be overwritten */ #define FSP_LOG "fsp_log_enable" /* 1 or 0: enable or disable FSP SOL log */ +#define FSP_LOG_DEFAULT 1 /* Default value when the VPD variable is not found */ + +/* FSP debug print level: 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All */ +#define FSP_LOG_LEVEL "fsp_log_level" +#define FSP_LOG_LEVEL_DEFAULT 8 /* Default value when the VPD variable is not found */ + +/* DCI enable */ +#define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ +#define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ #endif diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 421d4009ea..67c1fa9d52 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -6,10 +6,14 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select MAINBOARD_USES_FSP2_0 select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select MAINBOARD_USES_FSP2_0 + select OCP_DMI + select PARALLEL_MP_AP_WORK select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 + select VPD config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index ca4e4637d2..2f7f327960 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c -ramstage-y += ramstage.c +romstage-y += ipmi.c +ramstage-y += ramstage.c ipmi.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index f6947a20b8..300e8f6278 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include -#include - -extern const unsigned char AmlCode[]; void acpi_create_gnvs(struct global_nvs *gnvs) { diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd index 1e3fda7e8b..2ecce06570 100644 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ b/src/mainboard/ocp/tiogapass/board.fmd @@ -5,7 +5,15 @@ FLASH 32M { PLATFORM_DATA@0xa26000 0x10000 } SI_BIOS@0x1000000 0x1000000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x800 0xfff800 + MISC_RW@0x0 0x10000 { + RW_VPD(PRESERVE)@0x0 0x4000 + } + WP_RO@0x10000 0xff0000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0xfec000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfeb800 + } + } } } diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index 9fc34d77e8..b5c2aa1567 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251cf3..769396f454 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,12 +15,12 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include #include // Xeon-SP ACPI tables Scope (\_SB) { - #include + #include } } diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index 43b207e4d5..b66d7735d1 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -39,51 +39,48 @@ static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ }; +#define CFG_UPD_PORT(port, hide) \ + { \ + .PortIndex = port, \ + .HidePort = hide, \ + .DeEmphasis = 0x00, \ + .PortLinkSpeed = PcieAuto, \ + .MaxPayload = 0x00, \ + .DfxDnTxPreset = 0xFF, \ + .DfxRxPreset = 0xFF, \ + .DfxUpTxPreset = 0xFF, \ + .Sris = 0x00, \ + .PcieCommonClock = 0x00, \ + .NtbPpd = NTB_PORT_TRANSPARENT, \ + .NtbSplitBar = 0x00, \ + .NtbBarSizePBar23 = 0x16, \ + .NtbBarSizePBar4 = 0x16, \ + .NtbBarSizePBar5 = 0x16, \ + .NtbBarSizePBar45 = 0x16, \ + .NtbBarSizeSBar23 = 0x16, \ + .NtbBarSizeSBar4 = 0x16, \ + .NtbBarSizeSBar5 = 0x16, \ + .NtbBarSizeSBar45 = 0x16, \ + .NtbSBar01Prefetch = 0x00, \ + .NtbXlinkCtlOverride = 0x03, \ + } + /* * Standard Tioga Pass Iio PCIe Port Table */ static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, + CFG_UPD_PORT(PORT_1A, NOT_HIDE), + CFG_UPD_PORT(PORT_1B, HIDE), + CFG_UPD_PORT(PORT_1C, HIDE), + CFG_UPD_PORT(PORT_1D, HIDE), + CFG_UPD_PORT(PORT_2A, NOT_HIDE), + CFG_UPD_PORT(PORT_2B, HIDE), + CFG_UPD_PORT(PORT_2C, HIDE), + CFG_UPD_PORT(PORT_2D, HIDE), + CFG_UPD_PORT(PORT_3A, NOT_HIDE), + CFG_UPD_PORT(PORT_3B, HIDE), + CFG_UPD_PORT(PORT_3C, NOT_HIDE), + CFG_UPD_PORT(PORT_3D, HIDE), }; /* diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 1c26564e34..97ab7cb39e 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -12,23 +12,23 @@ static const struct pad_config gpio_table[] = { /* GPP_A0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - PIRQA# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* GPP_A10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ @@ -59,9 +59,9 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ @@ -83,11 +83,11 @@ static const struct pad_config gpio_table[] = { /* GPP_B11 - GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ @@ -105,7 +105,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ @@ -129,15 +129,15 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* GPP_F12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), /* GPP_F15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ @@ -147,22 +147,22 @@ static const struct pad_config gpio_table[] = { /* GPP_F18 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3), /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ @@ -233,7 +233,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D14 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ @@ -259,7 +259,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ @@ -269,9 +269,9 @@ static const struct pad_config gpio_table[] = { /* GPP_E7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ @@ -287,11 +287,11 @@ static const struct pad_config gpio_table[] = { /* GPD2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ @@ -303,18 +303,18 @@ static const struct pad_config gpio_table[] = { /* GPD10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), /* GPP_I4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ @@ -322,7 +322,7 @@ static const struct pad_config gpio_table[] = { /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), /* GPP_I8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ @@ -333,51 +333,51 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), /* GPP_J17 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), /* GPP_J19 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), /* GPP_J21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), /* GPP_J23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), @@ -397,13 +397,13 @@ static const struct pad_config gpio_table[] = { /* GPP_K6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1), /* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -442,11 +442,11 @@ static const struct pad_config gpio_table[] = { /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), @@ -501,7 +501,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c new file mode 100644 index 0000000000..0cdf110bd8 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "ipmi.h" +#include "vpd.h" + +void ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n"); +} + +void init_frb2_wdt(void) +{ + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); + return; + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", + countdown * 100); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", + DEFAULT_COUNTDOWN * 100); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h new file mode 100644 index 0000000000..798f3125ef --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TIOGAPASS_IPMI_H +#define TIOGAPASS_IPMI_H +#include + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 + +/* PPIN for 2 CPU IPMI request */ +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; +/* Send CPU0 and CPU1 PPIN to BMC */ +void ipmi_set_ppin(struct ppin_req *req); +void init_frb2_wdt(void); +#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 82b260d5b2..0e520f015d 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,9 +1,140 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + #include #include +#include +#include #include +#include #include +#include "ipmi.h" + +extern struct fru_info_str fru_strings; + +static const struct port_information SMBIOS_type8_info[] = { + /* + * Port Information fields: + * Internal Reference Designator, + * Internal Connector Type, + * External Reference Designator, + * External Connector_Type, + * Port Type + */ + { + "J7F5 - BMC JTAG HEADER", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8A1 - MINISAS1", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8A2 - MINISAS2", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8A3 - SATA CONBINE1", + CONN_SAS_SATA, + NULL, + CONN_NONE, + TYPE_SAS + }, + { + "J8B1 - ME_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8D1 - VR_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8E1 - TPM_MODULE", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J8F1 - M.2 CONNECTOR", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + "J9A1 - SATA RAID KEY", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9A2 - DEBUG 80 PORT", + CONN_OTHER, + TYPE_OTHER_PORT + }, + { + "J9A3 - CPU & PCH XDP", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9A5 - USB conn", + CONN_ACCESS_BUS_USB, + TYPE_USB + }, + { + "J9B1 - BMC_DBG", + CONN_OTHER, + NULL, + CONN_NONE, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "J9D1 - USB3.0 TYPE C", + CONN_ACCESS_BUS_USB, + TYPE_USB + }, + { + NULL, + CONN_NONE, + "J9E1 - VGA", + CONN_OTHER, + TYPE_OTHER_PORT + }, + { + NULL, + CONN_NONE, + "JA9G1 - ETH0", + CONN_RJ_45, + TYPE_NETWORK_PORT + }, +}; + void mainboard_silicon_init_params(FSPS_UPD *params) { } @@ -14,4 +145,60 @@ static void pull_post_complete_pin(void *unused) gpio_output(GPP_B20, 0); } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) +{ + int len = 0; + + // add port information + len += smbios_write_type8( + current, handle, + SMBIOS_type8_info, + ARRAY_SIZE(SMBIOS_type8_info) + ); + + return len; +} +#endif + +static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + /* OEM string 1 to 6 */ + ocp_oem_smbios_strings(dev, t); + + /* OEM string 7 */ + if (fru_strings.board_info.custom_count > 1 && + *(fru_strings.board_info.board_custom + 1) != NULL) + t->count = smbios_add_oem_string(t->eos, + *(fru_strings.board_info.board_custom + 1)); + else + t->count = smbios_add_oem_string(t->eos, TBF); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = tp_oem_smbios_strings, + read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif +} + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + req.cpu1_lo = xeon_sp_ppin[1].lo; + req.cpu1_hi = xeon_sp_ppin[1].hi; + /* Set PPIN to BMC */ + ipmi_set_ppin(&req); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index b728c3a5c5..fb2ce0217a 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -2,12 +2,15 @@ #include #include +#include #include #include #include #include #include +#include "ipmi.h" + static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; static void oem_update_iio(FSPM_UPD *mupd) @@ -49,6 +52,9 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* It's better to run get BMC selftest result first */ + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + init_frb2_wdt(); mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ diff --git a/src/mainboard/ocp/tiogapass/vpd.h b/src/mainboard/ocp/tiogapass/vpd.h new file mode 100644 index 0000000000..63a92f68b2 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/vpd.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef TIOGAPASS_VPD_H +#define TIOGAPASS_VPD_H + +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "frb2_timer" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "frb2_countdown" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 + +#endif /* TIOGAPASS_VPD_H */ diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 94d677bd27..06c2a49413 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -72,8 +72,4 @@ config MAINBOARD_PART_NUMBER string default "Elgon" -config MAINBOARD_FIT_DTS - string - default "gbcv2.dts" - endif diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index 2f46f571b2..1a775bb45e 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -8,35 +8,35 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) - Store(0, Local0) + Local0 = 0 - Store(0, PAGE) + PAGE = 0 - Store(BAPR, Local2) + Local2 = BAPR if (Arg2) // charging { - Or(2, Local0, Local0) + Local0 |= 2 - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) + If (Local2 == 0x8000) { + Local2 = 0 } } if (Arg3) // discharging { - Or(1, Local0, Local0) - Subtract(0x10000, Local2, Local2) + Local0 |= 1 + Local2 = 0x10000 - Local2 } - Store(Local0, Index(Arg1, 0x00)) + Arg1[0] = Local0 - Store(0, PAGE) - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) + PAGE = 0 + Arg1[2] = BARC + Arg1[1] = Local2 - Store(0, PAGE) - Store(BAVO, Index(Arg1, 3)) + PAGE = 0 + Arg1[3] = BAVO Release(ECLK) Return (Arg1) } @@ -44,37 +44,39 @@ Method(BSTA, 4, NotSerialized) Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) - Store(0, PAGE) - Store(BAFC, Local2) - Store(1, PAGE) - Store(BADC, Local1) + PAGE = 0 + Local2 = BAFC + PAGE = 1 + Local1 = BADC - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(1, PAGE) - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + Arg0[1] = Local1 // Design Capacity + Arg0[2] = Local2 // Last full charge capacity + PAGE = 1 + Arg0[4] = BADV // Design Voltage + Arg0[5] = Local2 / 20 // Warning capacity - Store(1, PAGE) - Store (BASN, Local0) + PAGE = 1 + Local0 = BASN Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) + Local1 = 4 While (Local0) { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) + Local2 = Local0 + Local0 /= 0x0A + Local2 -= (Local0 * 0x0A) + SERN[Local1] = Local2 + 48 + Local1-- } - Store (SERN, Index (Arg0, 10)) // Serial Number + Arg0[10] = SERN // Serial Number Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(4, PAGE) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - Store(5, PAGE) - Store(BAOE, Index (Arg0, 12)) // OEM information - Store(2, PAGE) - Store(BANA, Index (Arg0, 9)) // Model number + PAGE = 4 + TYPE = BATY + Arg0[11] = TYPE // Battery type + PAGE = 5 + Arg0[12] = BAOE // OEM information + PAGE = 2 + Arg0[9] = BANA // Model number Release(ECLK) Return (Arg0) } diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 50e648f28f..b57b3feba8 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/intel/ironlake register "gpu_dp_d_hotplug" = "0x04" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_up_delay" = "300" register "gpu_panel_power_down_delay" = "300" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index f2f3b08d84..bbcef27b4d 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index dcc81c9f8a..d6edf03e8b 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/mainboard/pcengines/apu1/acpi/mainboard.asl b/src/mainboard/pcengines/apu1/acpi/mainboard.asl index 9283191c95..5c0929a3f1 100644 --- a/src/mainboard/pcengines/apu1/acpi/mainboard.asl +++ b/src/mainboard/pcengines/apu1/acpi/mainboard.asl @@ -18,20 +18,20 @@ Name(PMOD, One) /* Assume APIC */ Scope(\_SB) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if(CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } Return(OSVR) diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl index 7f305fb17f..6d9ff03005 100644 --- a/src/mainboard/pcengines/apu1/acpi/sata.asl +++ b/src/mainboard/pcengines/apu1/acpi/sata.asl @@ -35,7 +35,7 @@ Device(PMRY) Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -48,7 +48,7 @@ Device(PMRY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -71,7 +71,7 @@ Device(SEDY) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -84,7 +84,7 @@ Device(SEDY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -98,35 +98,35 @@ Device(SEDY) Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl index 76b5f9edc6..3b6fd02055 100644 --- a/src/mainboard/pcengines/apu1/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu1/acpi/sleep.asl @@ -26,23 +26,23 @@ Method(\_PTS, 1) { /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) + if (Arg0 == 3){ + URRE = 0 } /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 } /* End Method(\_PTS) */ /* @@ -67,21 +67,21 @@ Method(\_WAK, 1) { /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,HPDE) + HPDE = 1 /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) + if (Arg0 == 3){ + URRE = 1 } /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) + Local1 = PWST + PWST = Local1 - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) + /* if (DeRefOf(WKST [0])) { + * WKST [1] = 0 * } else { - * Store(Arg0, Index(WKST,1)) + * WKST [1] = Arg0 * } */ Return(WKST) diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl index 4ecc52ade9..e4ed275617 100644 --- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl +++ b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl @@ -14,134 +14,134 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c index 5d2d253bfc..398594f828 100644 --- a/src/mainboard/pcengines/apu1/irq_tables.c +++ b/src/mainboard/pcengines/apu1/irq_tables.c @@ -27,7 +27,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; u32 slot_num; @@ -86,5 +85,4 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "%s done.\n", __func__); return (unsigned long)pirq_info; - } diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 45d326a818..7e3ef08b48 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -301,7 +301,7 @@ const char *smbios_mainboard_serial_number(void) return serial; /* Read in the last 3 bytes of NIC's MAC address. */ - bar18 = pci_read_config32(dev, 0x18); + bar18 = pci_read_config32(dev, PCI_BASE_ADDRESS_2); bar18 &= 0xFFFFFFF0; for (i = 3; i < 6; i++) { mac_addr <<= 8; diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 6087b1504a..ef6f5baeaa 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_ @@ -112,7 +111,6 @@ */ #define SATA_PORT_MULT_CAP_RESERVED 1 - /** * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index a2065ae355..d17dc36617 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -27,7 +27,6 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); //{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported } - /* * Hardware Monitor Fan Control * Hardware limitation: @@ -58,7 +57,6 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) { printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; /* Fan Control */ diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 25cc277927..fde73405c4 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_LPC_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select PCIEXP_ASPM diff --git a/src/mainboard/pcengines/apu2/acpi/sleep.asl b/src/mainboard/pcengines/apu2/acpi/sleep.asl index 39fe610fa7..377f0de5f8 100644 --- a/src/mainboard/pcengines/apu2/acpi/sleep.asl +++ b/src/mainboard/pcengines/apu2/acpi/sleep.asl @@ -30,9 +30,9 @@ Method(_PTS, 1) { /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -58,7 +58,7 @@ Method(\_WAK, 1) { /* DBGO(" to S0\n") */ /* clear USB wake up signal */ - Store(1, USBS) + USBS = 1 \_SB.AWAK(Arg0) diff --git a/src/mainboard/pcengines/apu2/irq_tables.c b/src/mainboard/pcengines/apu2/irq_tables.c index a16c247259..6c2b05c02b 100644 --- a/src/mainboard/pcengines/apu2/irq_tables.c +++ b/src/mainboard/pcengines/apu2/irq_tables.c @@ -25,7 +25,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } - unsigned long write_pirq_routing_table(unsigned long addr) { struct irq_routing_table *pirq; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index aa8c4bcf5e..40941db69e 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -22,7 +22,6 @@ #define PM_RTC_CONTROL 0x56 #define PM_S_STATE_CONTROL 0xBA - /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and @@ -293,7 +292,7 @@ const char *smbios_mainboard_serial_number(void) return serial; /* Read in the last 3 bytes of NIC's MAC address. */ - bar10 = pci_read_config32(dev, 0x10); + bar10 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); bar10 &= 0xFFFE0000; bar10 += 0x5400; for (i = 3; i < 6; i++) { diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 8cfec5d63d..b52c8ccf49 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -62,7 +62,6 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - /* SMBUS / ACPI */ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); @@ -85,7 +84,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - /* GPP0 */ PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 /* GPP1 */ diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index f813b8e500..bc06151633 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_FSP_BIN select CACHE_MRC_SETTINGS select DISABLE_HPET - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS choice prompt "Onboard memory manufacturer" diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 6a79f5be6e..d4b57fa49a 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -2,7 +2,6 @@ config BOARD_PRODRIVE_HERMES_BASEBOARD def_bool n select SOC_INTEL_COFFEELAKE select BOARD_ROMSIZE_KB_32768 - select GENERIC_SPD_BIN select HAVE_ACPI_TABLES select SOC_INTEL_CANNONLAKE_PCH_H select SUPERIO_ASPEED_COMMON_PRE_RAM diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 532254bdf0..5615554208 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -17,7 +17,6 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X" end device pci 04.0 on end # SA Thermal device - device pci 04.0 on end # Intel Xeon E3 device pci 08.0 on end # Gaussian Mixture device pci 12.0 on end # Thermal Subsystem device pci 14.0 on end # USB xHCI @@ -25,15 +24,18 @@ chip soc/intel/cannonlake device pci 14.2 on end # RAM controller device pci 14.5 off end # SDCard - device pci 16.0 on end # Management Engine Interface - device pci 16.1 on end # Management Engine Interface - device pci 16.4 on end # Management Engine Interface + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 1d.6 on + device pci 1d.6 on # PCIe root port 15 device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end - end # PCIe + register "PcieRpSlotImplemented[14]" = "1" + end device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 4d8d1709e8..ef84928231 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt b/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt index 64bc4fee08..66c5f6ee5c 100644 Binary files a/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt and b/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt differ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 6c6fe2d941..01b9537e13 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -54,13 +54,13 @@ chip soc/intel/cannonlake register "PcieRpEnable[15]" = "1" # M2 Slot E x1 register "PcieRpEnable[20]" = "1" # Slot 1 x4 # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[20]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[20]" = "1" - # Disable Aspm - register "PcieRpAspm[20]" = "AspmDisabled" + register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[20]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[20]" = "1" + # Disable Aspm + register "PcieRpAspm[20]" = "AspmDisabled" # Controls the CLKREQ, not the output directly. # Depends on the CLKREQ to CLK gen mapping below @@ -118,8 +118,6 @@ chip soc/intel/cannonlake # USB OC5-7: not connected # BMC register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" - # unused - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # piggy-back register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" # M2 key E @@ -131,12 +129,6 @@ chip soc/intel/cannonlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # HECI - register "HeciEnabled" = "1" - - # Internal GFX - register "InternalGfx" = "1" - # Disable S0ix register "s0ix_enable" = "0" @@ -171,30 +163,53 @@ chip soc/intel/cannonlake device domain 0 on - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on # Integrated Graphics Device + register "InternalGfx" = "1" + end chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end - device pci 19.2 on end # UART #2 - - device pci 1b.4 on + # This device does not have any function on CNP-H, but it needs + # to be here so that the resource allocator is aware of UART 2. + device pci 19.0 hidden end + chip soc/intel/common/block/uart + device pci 19.2 hidden + register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" + end # UART #2, in ACPI mode + end + device pci 1b.4 on # PCIe root port 21 (Slot 1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" - end # PCIe Slot 1 - device pci 1c.0 on + register "PcieRpSlotImplemented[20]" = "1" + end + device pci 1c.0 on # PCIe root port 1 (Slot 3) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" - end # PCIe Slot 3 - device pci 1c.4 on end # PHY 3 - device pci 1c.5 on end # PHY 4 - device pci 1c.6 on end # PHY 2 - device pci 1c.7 on end # PHY 1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCIe root port 5 (PHY 3) + register "PcieRpSlotImplemented[4]" = "1" + end + device pci 1c.5 on # PCIe root port 6 (PHY 4) + register "PcieRpSlotImplemented[5]" = "1" + end + device pci 1c.6 on # PCIe root port 7 (PHY 2) + register "PcieRpSlotImplemented[6]" = "1" + end + device pci 1c.7 on # PCIe root port 8 (PHY 1) + register "PcieRpSlotImplemented[7]" = "1" + end - device pci 1d.0 on + device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" - end # M2 M - device pci 1d.5 on end # PHY 0 - device pci 1d.6 on end # BMC + register "PcieRpSlotImplemented[8]" = "1" + end + device pci 1d.5 on # PCIe root port 14 (PHY 0) + register "PcieRpSlotImplemented[13]" = "1" + end + device pci 1d.6 on # PCIe root port 15 (BMC) + register "PcieRpSlotImplemented[14]" = "1" + end device pci 1e.0 on end # UART #0 device pci 1e.1 on end # UART #1 diff --git a/src/mainboard/protectli/vault_bsw/onboard.h b/src/mainboard/protectli/vault_bsw/onboard.h index d97801e86e..1704b68f97 100644 --- a/src/mainboard/protectli/vault_bsw/onboard.h +++ b/src/mainboard/protectli/vault_bsw/onboard.h @@ -14,7 +14,6 @@ * GPSE_SIZE = 86 */ - /* Audio: Gpio index in SW bank */ #define JACK_DETECT_GPIO_INDEX 77 diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index bb408a4351..2a4b1e9ffd 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,41 +34,22 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" - register "SaImguEnable" = "0" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -196,18 +177,12 @@ chip soc/intel/skylake register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled # USB 3.0 enable ports 1-4, disable ports 5-6 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ @@ -234,6 +209,8 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl index 5b3a5dfc8d..2a3876bd79 100644 --- a/src/mainboard/protectli/vault_kbl/dsdt.asl +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { - #include + #include #include #include diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0d44cd734f..b7c6fe58ae 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -9,8 +9,7 @@ chip soc/intel/broadwell # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP + # Set panel power delays register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index d44d2ada73..23c57120f1 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -45,8 +45,6 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" @@ -54,19 +52,12 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -78,15 +69,6 @@ chip soc/intel/skylake # EC/KBC requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -186,9 +168,11 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -207,6 +191,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.6 off end # SDXC device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index dacfefff21..0039e6bdd0 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index de493b0da9..7be8325176 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -64,4 +64,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; } diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb index ab46cd3cd1..c8e728c59d 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake - # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "1" + # Disable CLKREQ# for RP9 + register "PcieRpClkReqSupport[8]" = "0" # SRCCLKREQ2# for NVMe per schematic register "PcieRpClkReqNumber[8]" = "2" diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig new file mode 100644 index 0000000000..bc25fb5b3b --- /dev/null +++ b/src/mainboard/purism/librem_whl/Kconfig @@ -0,0 +1,62 @@ +config BOARD_PURISM_BASEBOARD_LIBREM_WHL + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + select SPD_READ_BY_WORD + select USE_LEGACY_8254_TIMER + +if BOARD_PURISM_BASEBOARD_LIBREM_WHL + +config MAINBOARD_DIR + string + default "purism/librem_whl" + +config MAINBOARD_FAMILY + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + +config MAINBOARD_PART_NUMBER + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + +config VARIANT_DIR + string + default "librem_mini" if BOARD_PURISM_LIBREM_MINI + +config CBFS_SIZE + hex + default 0x800000 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config PXE_ROM_ID + string + default "10ec,8168" + +# This platform has limited means to display POST codes +config NO_POST + default y + +endif diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_whl/Kconfig.name new file mode 100644 index 0000000000..41a4003102 --- /dev/null +++ b/src/mainboard/purism/librem_whl/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PURISM_LIBREM_MINI + bool "Librem Mini" + select BOARD_PURISM_BASEBOARD_LIBREM_WHL diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc new file mode 100644 index 0000000000..ba157dfd05 --- /dev/null +++ b/src/mainboard/purism/librem_whl/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_whl/acpi/mainboard.asl new file mode 100644 index 0000000000..0c9a76b168 --- /dev/null +++ b/src/mainboard/purism/librem_whl/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) +{ + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { LPCB }) + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) + { + Return (ACFG) + } + } +} diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_whl/board_info.txt new file mode 100644 index 0000000000..e72dcdf2b7 --- /dev/null +++ b/src/mainboard/purism/librem_whl/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: librem_whl +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb new file mode 100644 index 0000000000..497a4cca4d --- /dev/null +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -0,0 +1,308 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Disable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 28, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "0" + register "PchHdaAudioLinkDmic1" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper + + # All SRCCLKREQ pins mapped directly + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Set all SRCCLKREQ pins as free-use + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + + # PCI Express Root Port #8 x1, Clock 2 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + + # PCI Express Root Port #10 x1, Clock 3 (LAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + + # PCI Express Root port #13 x4, Clock 1 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + + # Misc + register "AcousticNoiseMitigation" = "1" + register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# PMC (soc/intel/cannonlake/pmc.c) + # Disable deep Sx states + register "deep_sx_config" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.5 on end + end + end + end + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off # Management Engine Interface 1 + # HECI must be enabled w/HAP disable else S3 issues + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on # PCI Express Port 10 (LAN) + register "PcieRpSlotImplemented[9]" = "1" + end + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 (NVMe) + register "PcieRpSlotImplemented[12]" = "1" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Bridge + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl new file mode 100644 index 0000000000..fdef72df66 --- /dev/null +++ b/src/mainboard/purism/librem_whl/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } + + #include + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c new file mode 100644 index 0000000000..56ed1b7844 --- /dev/null +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + size_t num_gpios; + const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); +} diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c new file mode 100644 index 0000000000..3a3ca6b491 --- /dev/null +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct cnl_mb_cfg memcfg = { + + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; +} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt new file mode 100644 index 0000000000..2e657d1a9f Binary files /dev/null and b/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt differ diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c new file mode 100644 index 0000000000..254510ead5 --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c @@ -0,0 +1,791 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 0, DEEP), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + /* GPP_A11 - GPIO */ + /* DW0: 0x80880201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + + /* GPP_A12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + + /* GPP_A13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - SUS_STAT# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + /* GPP_A15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + + /* GPP_A16 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), + + /* GPP_A17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A18, UP_20K), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A19, UP_20K), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A20, UP_20K), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A21, UP_20K), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A22, UP_20K), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + + /* GPP_B3 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B3, 1, PLTRST), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* GPP_B15 - GSPI0_CS0# */ + /* DW0: 0x00000701, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), + + /* GPP_B16 - GSPI0_CLK */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), + + /* GPP_B17 - GSPI0_MISO */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* GPP_B18 - GSPI0_MOSI */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + + /* GPP_B19 - GSPI1_CS0# */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + + /* GPP_B20 - GSPI1_CLK */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), + + /* GPP_B21 - GSPI1_MISO */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), + + /* GPP_B22 - GSPI1_MOSI */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B23, 1, DEEP), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00001000 */ + PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), + + /* GPP_G1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G2, NONE), + + /* GPP_G3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G3, NONE), + + /* GPP_G4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G4, NONE), + + /* GPP_G5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_G5, UP_20K), + + /* GPP_G6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G6, NONE), + + /* GPP_G7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00001000 */ + PAD_NC(GPP_G7, DN_20K), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - ISH_I2C0_SDA */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - ISH_I2C0_SCL */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D7, 1, PLTRST), + + /* GPP_D8 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 0, PLTRST), + + /* GPP_D9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + /* GPP_D10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D10, 1, PLTRST), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), + + /* GPP_D12 - GPIO */ + /* DW0: 0x42100102, DW1: 0x00003000 */ + PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), + + /* GPP_D13 - GPIO */ + /* DW0: 0x04000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D13, 1, RSMRST), + + /* GPP_D14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + + /* GPP_D16 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 0, RSMRST), + + /* GPP_D17 - DMIC_CLK1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + + /* GPP_D18 - DMIC_DATA1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* GPP_D19 - DMIC_CLK0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* GPP_D20 - DMIC_DATA0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_D21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D21, NONE), + + /* GPP_D22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D22, NONE), + + /* GPP_D23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + /* DW0: 0x00000301, DW1: 0x00000000 */ + PAD_NC(GPP_F0, NONE), + + /* GPP_F1 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F1, 0, RSMRST), + + /* GPP_F2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + + /* GPP_F3 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), + + /* GPP_F4 - CNV_BRI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + + /* GPP_F5 - CNV_BRI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + + /* GPP_F6 - CNV_RGI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + + /* GPP_F7 - CNV_RGI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* GPP_F11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - A4WP_PRESENT */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H0, UP_20K), + + /* GPP_H1 - CNV_RF_RESET# */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + + /* GPP_H2 - MODEM_CLKREQ */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H3, UP_20K), + + /* GPP_H4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - I2C3_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C3_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - I2C4_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - I2C5_SDA */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), + + /* GPP_H11 - I2C5_SCL */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), + + /* GPP_H12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + + /* GPP_H13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + + /* GPP_H14 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + + /* GPP_H15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + + /* GPP_H16 - GPIO */ + /* DW0: 0x04000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H16, 1, RSMRST), + + /* GPP_H17 - GPIO */ + /* DW0: 0x04000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 1, RSMRST), + + /* GPP_H18 - CPU_C10_GATE# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + + /* GPP_H20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* GPP_H22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x04000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + + /* GPD2 - LAN_WAKE# */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + + /* GPD3 - PRWBTN# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, RSMRST), + + /* GPD8 - SUSCLK */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + + /* GPD9 - SLP_WLAN# */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + + /* GPD11 - LANPHYPC */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + + /* GPP_C6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C8, 1, PLTRST), + + /* GPP_C9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C9, 1, PLTRST), + + /* GPP_C10 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + + /* GPP_C11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), + + /* GPP_C12 - UART1_RXD */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + + /* GPP_C13 - UART1_TXD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + + /* GPP_C14 - UART1_RTS# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + + /* GPP_C15 - UART1_CTS# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + + /* GPP_C16 - I2C0_SDA */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + + /* GPP_C17 - I2C0_SCL */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + + /* GPP_C18 - I2C1_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + /* DW0: 0x40100102, DW1: 0x00001000 */ + PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - SATAXPCIE2 */ + /* DW0: 0x84000502, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + + /* GPP_E3 - GPIO */ + /* DW0: 0x82040102, DW1: 0x00000000 */ + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + + /* GPP_E4 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + /* DW0: 0x82000102, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), + + /* GPP_E8 - SATALED# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), + + /* GPP_E10 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), + + /* GPP_E11 - USB2_OC2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - USB2_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPP_E13 - DDPB_HPD0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* GPP_E14 - DDPC_HPD1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + + /* GPP_E16 - GPIO */ + /* DW0: 0x80880102, DW1: 0x00003000 */ + PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), + + /* GPP_E17 - EDP_HPD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* GPP_E18 - DPPB_CTRLCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* GPP_E19 - DPPB_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + + /* GPP_E20 - DPPC_CTRLCLK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* GPP_E21 - DPPC_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* GPP_E22 - DPPD_CTRLCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + + /* GPP_E23 - DPPD_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c new file mode 100644 index 0000000000..c3daf3c5ed --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x01214010), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19130), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40422201), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h new file mode 100644 index 0000000000..9094b0419d --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include +#include + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 532bd76c45..31c29cd31b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LIBGFXINIT - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select DRIVERS_I2C_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 7d54d33d8e..edf13335a2 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,26 +27,17 @@ chip soc/intel/skylake # FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -57,15 +48,6 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -204,11 +186,12 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # Thermal Subsystem + device pci 04.0 on end # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera device pci 15.0 on end # I2C Controller #0 device pci 15.1 on chip drivers/i2c/hid @@ -244,6 +227,7 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # Serial IO UART0 + device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index ec3ca791ae..001eae99d0 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -5,13 +5,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x05, // DSDT revision: ACPI v5.0 + 0x02, // DSDT revision: ACPI v5.0 "COREv4", // OEM id "COREBOOT", // OEM table id 0x20110725 // OEM revision ){ //Platform - #include + #include // global NVS and variables #include diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266ddebf3..1ba1ad9e2a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -10,158 +10,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), +/* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), +/* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* GPP_C6 - RESERVED */ +/* GPP_C7 - RESERVED */ +/* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), +/* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), +/* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), +/* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(20K_PD)), +/* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), +/* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), +/* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), +/* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), }; #endif diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc index 27c289bd2a..f1fdd6ffe8 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc +++ b/src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc @@ -2,7 +2,5 @@ romstage-y += spd_util.c -SPD_BIN = $(obj)/spd.bin - SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0000 8GB SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b0001 16GB diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 6756e0e9b3..b54e10043a 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -83,7 +83,6 @@ static u8 function_ram[] = { 0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79, /* (0xfc-0xff) */ }; - #define KBD_DATA 0x60 #define KBD_SC 0x64 @@ -129,7 +128,6 @@ static int send_kbd_data(u8 data) return 0; } - static u8 recv_kbd_data(void) { int timeout; @@ -153,7 +151,6 @@ static u8 recv_kbd_data(void) return data; } - static u8 m3885_get_variable(u8 index) { u8 ret; @@ -251,7 +248,7 @@ void m3885_configure_multikey(void) maxvars = m3885_get_variable(0x00); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); for (i = 0; i < ARRAY_SIZE(variables); i+=3) { - if(variables[i + 0] > maxvars) + if (variables[i + 0] > maxvars) continue; reg8 = m3885_get_variable(variables[i + 0]); reg8 &= ~(variables[i + 1]); diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 0a96edf609..f3108dbed9 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000100, }" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index ada4b9f1e8..5b55873eb1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -10,15 +10,15 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 988c2a64d5..a1edcaa3f4 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000301, 0x80000100, }" # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_port_select" = "PANEL_PORT_DP_A" register "gpu_panel_power_cycle_delay" = "6" # 500ms register "gpu_panel_power_up_delay" = "2000" # 200ms register "gpu_panel_power_down_delay" = "500" # 50ms diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index f56a5e41d0..7076eb7358 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,15 +40,15 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index b938945fa2..7d73bc7b99 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select SANDYBRIDGE_VBOOT_IN_ROMSTAGE + select HAVE_SPD_IN_CBFS config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 74a635767e..1fd9498c47 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -5,18 +5,11 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -SPD_BIN = $(obj)/spd.bin - -# Include spd ROM data -$(SPD_BIN): - xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c + +SPD_SOURCES = lumpy diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 15bff4bcc9..06efaf8ff9 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms register "gpu_panel_power_down_delay" = "150" # T3: 15ms diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 091cbc5064..ad4ddb91ee 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -117,15 +117,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index fbb74804e1..cdeaf72de0 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -19,8 +19,6 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } - - static void mainboard_init(struct device *dev) { /* Initialize the Embedded Controller */ diff --git a/src/mainboard/samsung/lumpy/spd.hex b/src/mainboard/samsung/lumpy/spd.hex deleted file mode 100644 index 8690886207..0000000000 --- a/src/mainboard/samsung/lumpy/spd.hex +++ /dev/null @@ -1,96 +0,0 @@ -0000000: 92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00 .........R....>. -0000010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01 ixi0i. .p.<<.... -0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00 ..............!. -0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000070: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 d3 0d ................ -0000080: 4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 48 39 M471B2873FHS-CH9 -0000090: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00 .............. -00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000100: 92 10 0b 03 02 11 00 01 03 52 01 08 0f 00 1e 00 .........R...... -0000110: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01 ixi. -0000310: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01 ixi0i. .p.<<.... -0000320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000330: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00 ..............A. -0000340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000370: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 cf 74 ...............t -0000380: 4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 48 39 M471B2873GB0-CH9 -0000390: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00 .............. -00003a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00003b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00003c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00003d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00003e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00003f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000400: 92 11 0b 03 02 11 00 01 03 11 01 08 0f 00 1e 00 ................ -0000410: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01 ixi. -0000510: 69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 01 ixi0i. ...<<.... -0000520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000530: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00 ..............!. -0000540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -0000570: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 4c db ..............L. -0000580: 4d 34 37 31 42 35 37 37 33 43 48 53 2d 43 48 39 M471B5773CHS-CH9 -0000590: 20 20 00 00 80 ce 00 00 00 53 30 58 44 30 30 30 .......S0XD000 -00005a0: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00005b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00005c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00005d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00005e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ -00005f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ diff --git a/src/mainboard/samsung/lumpy/spd/lumpy.spd.hex b/src/mainboard/samsung/lumpy/spd/lumpy.spd.hex new file mode 100644 index 0000000000..abd3ebf290 --- /dev/null +++ b/src/mainboard/samsung/lumpy/spd/lumpy.spd.hex @@ -0,0 +1,96 @@ +92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00 +69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 01 00 00 00 00 00 00 d3 0d +4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 48 39 +20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +92 10 0b 03 02 11 00 01 03 52 01 08 0f 00 1e 00 +69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 02 10 31 81 1d 77 ce 91 a4 +4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 46 38 +20 20 00 00 80 ce 00 00 00 53 47 30 44 35 31 31 +01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 7e 00 +69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 fe 00 00 00 00 00 00 00 29 2b +45 42 4a 32 30 55 46 38 42 44 55 30 2d 44 4a 2d +46 20 30 20 02 fe 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +92 11 0b 03 02 11 00 01 03 11 01 08 0c 00 3e 00 +69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 01 00 00 00 00 00 00 cf 74 +4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 48 39 +20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +92 11 0b 03 02 11 00 01 03 11 01 08 0f 00 1e 00 +69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 01 00 00 00 00 00 00 8d dd +4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 46 38 +20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 3e 00 +69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 01 00 00 00 00 00 00 4c db +4d 34 37 31 42 35 37 37 33 43 48 53 2d 43 48 39 +20 20 00 00 80 ce 00 00 00 53 30 58 44 30 30 30 +01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index f07948291f..7d4a9a4411 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -101,15 +101,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, + .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index c51bd69872..a251d22546 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,14 +2,8 @@ #include #include -#include - -#include -#include #include -extern const unsigned char AmlCode[]; - void acpi_create_gnvs(struct global_nvs *gnvs) { acpi_init_gnvs(gnvs); diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c index 0be5532e38..099d37e337 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ b/src/mainboard/scaleway/tagada/bmcinfo.c @@ -26,7 +26,6 @@ typedef struct { #define BIOSBMCINFO_MAGIC0 0x49434d42 #define BIOSBMCINFO_MAGIC1 0x306f666e - #define BMC_INFO ((biosBmcInfo_t *)CONFIG_BMC_INFO_LOC) enum biosBmcInfoValidFlag_e { @@ -106,7 +105,6 @@ u8 *bmcinfo_uuid(void) return NULL; } - int bmcinfo_slot(void) { if (IS_BMC_INFO_FIELD_VALID(slot)) diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 0fe4a25a01..ac85670644 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -40,8 +40,4 @@ config MAINBOARD_PART_NUMBER config UART_FOR_CONSOLE default 2 -config MAX_CPUS - int - default 8 - endif # BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 0e72fcf743..2e43648dd7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -69,6 +69,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index bee531f2fa..1ac551a373 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -61,6 +61,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index aa4a906c5a..4bf4bb5235 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -53,11 +53,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE(GPIO_171, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* SDCARD_D1 */ PAD_CFG_NF_IOSSTATE(GPIO_174, UP_20K, DEEP, NF1, HIZCRx1), /* SDCARD_D2 */ @@ -67,54 +65,42 @@ static const struct pad_config gpio_table[] = { /* SDCARD_CD_1V8# */ PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* Not connected */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_WP_1V8 */ PAD_CFG_GPI_GPIO_DRIVER(GPIO_186, DN_20K, DEEP), /* SD_PWR_EN_1V8 - Always enabled SDCard. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_183, 0, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_183, 0, UP_20K, DEEP), /* West Community */ /* I2C_PM_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_PM_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM0_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_CAM1_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_GP_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_DATA_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* I2C_LCD_CLK_1V8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, - MASK), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* GPIO_PWRBTN# */ - PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, - TxDRxE, SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* HDA_BCLK_1V8 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, DN_20K, DEEP, NF3, MASK, SAME), @@ -147,19 +133,15 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(OSC_CLK_OUT_4, DN_20K, DEEP, OFF), /* PM_CHARGER_PRSNT */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, SAME), /* PM_BATLOW# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, SAME), /* PMU_PLTRST# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PLTRST_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_PWRBTN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, SAME), /* SYS_RESET# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S0# */ PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S0_B, NONE, DEEP, NF1, MASK, SAME), /* PMU_SLP_S3# */ @@ -198,25 +180,22 @@ static const struct pad_config gpio_table[] = { /* Not connected */ PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1), PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* EDP_VDD_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_VDD_EN. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_196, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_196, 1, UP_20K, DEEP), /* EDP_BKLT_EN_1V8 (DNI) - Alternative stuffing option for * PTN3460 LVDS_BKLT_EN */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_197, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_197, 1, UP_20K, DEEP), /* EDP_BKLT_CTRL_1V8 - Alternative stuffing option for * PTN3460 LVDS_BKLT_CTRL */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_198, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_198, 1, UP_20K, DEEP), /* DDI1_HPD# - Connect to DP1_HPD Hot plug detection signal of SMARC * Connector. @@ -228,10 +207,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME), /* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]), * (USB1_OC#:USB1), (USB2_OC#:USB2) @@ -243,34 +220,26 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, MASK, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* EDP_HPD# - from HPDRX pin of PTN3460 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, SAME), /* Not connected */ PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), - PAD_CFG_GPO_GPIO_DRIVER(GPIO_214, 1, DEEP, DN_20K), - PAD_CFG_GPO_GPIO_DRIVER(GPIO_215, 1, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_214, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPIO_215, 1, DN_20K, DEEP), /* THERMTRIP_1V8# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, - TxLASTRxE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, TxLASTRxE, SAME), /* PROCHOT_CPU# - Connected to CPLD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* Not connected */ PAD_CFG_GPI_INT(PMIC_I2C_SCL, DN_20K, DEEP, OFF), @@ -342,8 +311,7 @@ static const struct pad_config gpio_table[] = { /* FST_SPI_CLK_1V8. Goes to both module SPI chip and carrier board. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), /* FST_SPI_CLK_FB */ - PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, SAME), /* SIO_SPI_CLK_1V8 - Connected to ESPI_CK of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), @@ -390,15 +358,15 @@ static const struct pad_config gpio_table[] = { /* OTG_SEL_1V8 - Connected to a USB MUX to select between USB2_DP0 (OTG) * and USB2_DP6. 1:OTG, 0:USB */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_9, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_9, 1, UP_20K, DEEP), /* EN_I2CPM_EXT_1V8 - Connected to OE pin of I2C Re-driver. * Allow/Disallow I2C signal to pass through to SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_10, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_10, 1, UP_20K, DEEP), /* EN_SMB_EXT_1V8 - Connected to OE pin of I2C Re-driver. * Allow/Disallow SMBUS signal to pass through to SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_11, 0, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_11, 0, UP_20K, DEEP), /* BOOT_SEL2_1V8# - Three Module pins allow the Carrier board user to * select from eight possible boot devices. */ @@ -413,13 +381,13 @@ static const struct pad_config gpio_table[] = { */ PAD_CFG_GPI_INT(GPIO_14, UP_20K, DEEP, OFF), /* GPIO_CPLD_TCK_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_15, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_15, 0, DN_20K, DEEP), /* GPIO_CPLD_TMS_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_16, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_16, 0, DN_20K, DEEP), /* GPIO_CPLD_TDI_1V8 */ PAD_CFG_GPI_INT(GPIO_17, DN_20K, DEEP, OFF), /* GPIO_CPLD_TDO_1V8 */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_18, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_18, 0, DN_20K, DEEP), /* PM_TEST_1V8# connect to the SMARC Connector TEST# pin. * Held low by Carrier to invoke Module vendor specific test function. * Pulled up on Module. Driven by OD part on Carrier. @@ -436,8 +404,7 @@ static const struct pad_config gpio_table[] = { * Module. Pulled up on Module. Driven by Open Drain (OD) part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), /* LID_CPU_1V8# - Connect to the SMARC Connector LID# pin. * Lid open/close indication to Module. Low indicates lid closure * (which system may use to initiate a sleep state). Carrier to float @@ -445,8 +412,7 @@ static const struct pad_config gpio_table[] = { * de-bounced on the Module Pulled up on Module. Driven by OD part on * Carrier. */ - PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, - SAME), + PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, SAME), /* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled * and timeout. */ @@ -464,9 +430,9 @@ static const struct pad_config gpio_table[] = { /* SMB_ALERT_GPIO# */ PAD_CFG_GPI_INT(GPIO_27, UP_20K, DEEP, OFF), /* GPIO_28_DEBUG - Connect to HOOK5 (ClkOut#) pin of XDP connector */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_28, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_28, 1, UP_20K, DEEP), /* GPIO_29_DEBUG - Connect to HOOK4 (ClkOut) pin of XDP connector */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_29, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_29, 0, DN_20K, DEEP), /* Not connected */ PAD_CFG_GPI_INT(GPIO_30, DN_20K, DEEP, OFF), @@ -484,31 +450,29 @@ static const struct pad_config gpio_table[] = { /* STRAP_GPIO_36 (int. PD) */ PAD_CFG_GPI_INT(GPIO_36, DN_20K, DEEP, OFF), /* Not connected */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_37, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_37, 0, DN_20K, DEEP), /* GPIO_VALID (CPLD=gpio_valid/pi_gpio_en)- This pin Enable the CPLD * GPIO to the SMARC Connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_62, 1, DEEP, UP_20K), + PAD_CFG_TERM_GPO(GPIO_62, 1, UP_20K, DEEP), /* LVDS_ENABLE_1V8# connect to PTN3460 DP to LVDS converter chip. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_63, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_63, 0, DN_20K, DEEP), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_64, DN_20K, DEEP, HIZCRx0, SAME), /* Not connected */ PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_65, DN_20K, DEEP, HIZCRx0, SAME), /* CAM_CS0_CS1_SEL - Serial Cameras interfaces Select - to select * between the two MIPI CSI camera interfaces on the SMARC connector. */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_66, 0, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_66, 0, DN_20K, DEEP), /* MCSI0_RST_1V8# - Reset the MIPI CSI camera interfaces 0 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, HIZCRx0, SAME), /* MCSI1_RST_1V8# - Reset the MIPI CSI camera interfaces 1 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, DN_20K, HIZCRx0, SAME), /* MCSI0_PWR_1V8# - Power for the MIPI CSI camera interfaces 0 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* MCSI1_PWR_1V8# - Power for the MIPI CSI camera interfaces 1 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, - SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, SAME), /* Not connected */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, DN_20K, HIZCRx0, SAME), /* Not connected */ @@ -577,41 +541,29 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, DN_20K, PWROK, NF1, HIZCRx0, SAME), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* STRAP_GPIO_39 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* STRAP_GPIO_40 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* Not connected */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_RX to SMARC Connector SER0_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART1_TX to SMARC Connector SER0_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_RTS_1V8# to SMARC Connector SER0_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART1_CTS_1V8# to SMARC Connector SER0_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* CPU_UART2_RX_1V8 to SMARC Connector SER2_RX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* CPU_UART2_TX_1V8 to SMARC Connector SER2_TX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_RTS_1V8# to SMARC Connector SER2_RTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* CPU_UART2_CTS_1V8# to SMARC Connector SER2_CTS# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* Board ID - GPIO_223 */ PAD_CFG_GPI_INT(PMIC_RESET_B, DN_20K, DEEP, OFF), @@ -635,32 +587,23 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_DATA, UP_20K, DEEP, NF1, MASK, SAME), /* LPC_SERIRQ_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, - SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, SAME), /* CLK_25M_LPC_TPM_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* CLK_25M_LPC_CPLD_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD1_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD2_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3_CPU */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKRUN# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_FRAME_CPU# */ - PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index e1e79b44ae..bc5a9cf6a7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -57,6 +57,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index be50408820..7e5166650c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -58,6 +58,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 33664fe937..b5fb33b1a4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -60,6 +60,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index a865f9fa5c..024f2c5e07 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "1" + # Enable Vtd feature register "enable_vtd" = "1" @@ -28,6 +31,7 @@ chip soc/intel/apollolake device pci 0d.2 on end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - RP 2 - PCIe A 0 @@ -69,7 +73,7 @@ chip soc/intel/apollolake device pci 19.2 off end # - SPI 2 device pci 1a.0 off end # - PWM device pci 1b.0 on end # - SDCARD - device pci 1c.0 off end # - eMMC + device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on # - LPC diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index b4991daf85..38492acb87 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -47,7 +47,6 @@ static void do_fixup_memory(struct device_tree_node *node) dt_add_reg_prop(node, addrs, sizes, 1, 2, 2); } - static void fixup_memory(struct device_tree_node *parent) { struct device_tree_property *prop; diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 2ba6d2b870..2ff375ae29 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -41,7 +41,6 @@ static const struct region_device_ops unleashed_sd_ops = { .readat = unleashed_sd_readat, }; - static struct mmap_helper_region_device sd_mdev = MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index dde9bc16f7..598fbbeb1a 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -5,7 +5,6 @@ if BOARD_SUPERMICRO_X10SLM_PLUS_F config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select CPU_INTEL_HASWELL select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index a2514ad03c..ffcc56d15c 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -26,15 +26,6 @@ chip northbridge/intel/haswell device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x85" - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e23da4322a..a446835a75 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -10,7 +10,6 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES select MAINBOARD_HAS_LPC_TPM select DRIVERS_ASPEED_AST2050 select SUPERIO_ASPEED_AST2400 - select GENERATE_SMBIOS_TABLES select IPMI_KCS select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 94eeee7540..3e5751c3d7 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -5,7 +5,6 @@ #include #include #include -#include #include static void early_config_gpio(void) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 0dd37eeafa..dd0e520365 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -7,26 +7,12 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - # SATA configuration register "SataMode" = "KBLFSP_SATA_MODE_AHCI" - register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ [0] = 1, \ @@ -53,36 +39,6 @@ chip soc/intel/skylake # superspeed_inter-chip_supplement (SSIC) disabled register "SsicPortEnable" = "0" - # USB - register "usb2_ports" = "{ - [0] = USB2_PORT_EMPTY, - [1] = USB2_PORT_EMPTY, - [2] = USB2_PORT_EMPTY, - [3] = USB2_PORT_EMPTY, - [4] = USB2_PORT_EMPTY, - [5] = USB2_PORT_EMPTY, - [6] = USB2_PORT_EMPTY, - [7] = USB2_PORT_EMPTY, - [8] = USB2_PORT_EMPTY, - [9] = USB2_PORT_EMPTY, - [10] = USB2_PORT_EMPTY, - [11] = USB2_PORT_EMPTY, - [12] = USB2_PORT_EMPTY, - [13] = USB2_PORT_EMPTY, - }" - register "usb3_ports" = "{ - [0] = USB3_PORT_EMPTY, - [1] = USB3_PORT_EMPTY, - [2] = USB3_PORT_EMPTY, - [3] = USB3_PORT_EMPTY, - [4] = USB3_PORT_EMPTY, - [5] = USB3_PORT_EMPTY, - [6] = USB3_PORT_EMPTY, - [7] = USB3_PORT_EMPTY, - [8] = USB3_PORT_EMPTY, - [9] = USB3_PORT_EMPTY, - }" - # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -153,6 +109,7 @@ chip soc/intel/skylake device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # SPI #0 + device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC Interface chip superio/common device pnp 2e.0 on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index f705b5488c..d8690764bf 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include // global NVS and variables #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index bc2d5ce2f4..bbaad7d8c6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -7,227 +7,237 @@ #include static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), -/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), -/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), -/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), -/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), -/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), -/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), -/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), -/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), -/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), -/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), -/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), -/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), -/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), -/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), -/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), -/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), -/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), -/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), -/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), -/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), -/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), -/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), -/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), -/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), -/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), -/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), -/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), -/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), -/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), -/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), -/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), -/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), -/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), -/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), -/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; - /*** XXX TODO XXX */ -/* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* LPC */ - -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), }; #endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 074e61bfbc..7996791a69 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,19 +14,15 @@ chip soc/intel/skylake # PCIe configuration # Enable JPCIE1 register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "0" # Enable ASpeed PCI bridge register "PcieRpEnable[2]" = "1" - register "PcieRpClkReqSupport[2]" = "0" # Enable X550T (10GbE) register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0" # Enable M.2 register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "0" # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -112,13 +108,17 @@ chip soc/intel/skylake io 0x62 = 0xa10 io 0x64 = 0xa20 io 0x66 = 0xa30 - irq 0x70 = 0xb + irq 0x70 = 0x00 end device pnp 2e.5 off end # KBC - device pnp 2e.7 on end # GPIO + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end device pnp 2e.b off end # SUART3 device pnp 2e.c off end # SUART4 - device pnp 2e.d on end # iLPC2AHB + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end device pnp 2e.e on # Mailbox io 0x60 = 0xa40 irq 0x70 = 0x00 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 0c47a9d5eb..f5e71ad45e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -8,249 +8,241 @@ static const struct pad_config gpio_table[] = { /* GPIO Group GPP_A */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), /* GPIO Group GPP_B */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ - _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), /* GPIO Group GPP_C */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ - //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ - //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ - //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ - _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + // PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), + // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_NC(GPP_C23, NONE), /* GPIO Group GPP_D */ - _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), /* GPIO Group GPP_E */ - _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* GPIO Group GPP_F */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPIO Group GPP_G */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ - _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), /* GPIO Group GPP_H */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ - _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ - _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ - _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ - _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), /* GPIO Group GPP_I */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ - _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* GPIO Group GPD */ - _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ - _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ - _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ - _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ - _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ - _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ - _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - /* LPC */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ - - /* Serial interrupt */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), }; #endif /* _GPIO_X11SSM_F_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 80d2305590..8b0a2a0bd1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -99,13 +99,17 @@ chip soc/intel/skylake io 0x62 = 0xa10 io 0x64 = 0xa20 io 0x66 = 0xa30 - irq 0x70 = 0xb + irq 0x70 = 0x00 end device pnp 2e.5 off end # KBC - device pnp 2e.7 on end # GPIO + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end device pnp 2e.b off end # SUART3 device pnp 2e.c off end # SUART4 - device pnp 2e.d on end # iLPC2AHB + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end device pnp 2e.e on # Mailbox io 0x60 = 0xa40 irq 0x70 = 0x00 diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c index be0b3cde01..9438a51420 100644 --- a/src/mainboard/supermicro/x9scl/early_init.c +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -72,7 +72,6 @@ static const uint8_t superio_initvals[][2] = { SUPERIO_INITVAL(0x30, 0x80), }; - static void superio_init(void) { const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0); diff --git a/src/mainboard/system76/kbl-u/acpi/ec.asl b/src/mainboard/system76/kbl-u/acpi/ec.asl index e0792d3c9e..5989f6d285 100644 --- a/src/mainboard/system76/kbl-u/acpi/ec.asl +++ b/src/mainboard/system76/kbl-u/acpi/ec.asl @@ -1,9 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (EC0) +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" +} + +Device (\_SB.PCI0.LPCB.EC0) { Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID - Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, @@ -20,7 +29,7 @@ Device (EC0) ) }) - #include "acpi/ec_ram.asl" + #include "ec_ram.asl" Name (ECOK, Zero) Method (_REG, 2, Serialized) // _REG: Region Availability @@ -39,6 +48,10 @@ Device (EC0) ^^^^BAT0.UPBI() ^^^^BAT0.UPBS() + // Notify of changes + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + PNOT () // EC is now available @@ -71,8 +84,6 @@ Device (EC0) Notify(^^^^AC, Zero) Notify(^^^^BAT0, Zero) - Sleep (1000) - // Reset System76 Device ^^^^S76D.RSET() } @@ -154,13 +165,10 @@ Device (EC0) Debug = "EC: AC Detect" ^^^^AC.ACFG = ADP Notify (AC, 0x80) // Status Change - Sleep (0x01F4) If (BAT0) { Notify (^^^^BAT0, 0x81) // Information Change - Sleep (0x32) Notify (^^^^BAT0, 0x80) // Status Change - Sleep (0x32) } } diff --git a/src/mainboard/system76/kbl-u/acpi/s76.asl b/src/mainboard/system76/kbl-u/acpi/s76.asl index 399e569734..7beb50b813 100644 --- a/src/mainboard/system76/kbl-u/acpi/s76.asl +++ b/src/mainboard/system76/kbl-u/acpi/s76.asl @@ -14,6 +14,9 @@ Device (S76D) { Debug = "S76D: RSET" SAPL(0) SKBL(0) +#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) + SKBC(0xFFFFFF) +#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) } Method (INIT, 0, Serialized) { @@ -61,6 +64,32 @@ Device (S76D) { } } +#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) + // Set KB LED Brightness + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 6 + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FBF1 = 0 + ^^PCI0.LPCB.EC0.FBF2 = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 0x3 + ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) + ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) + ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Return (Arg0) + } Else { + Return (0) + } + } +#else // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) // Get KB LED Method (GKBL, 0, Serialized) { Local0 = 0 @@ -81,4 +110,5 @@ Device (S76D) { ^^PCI0.LPCB.EC0.FCMD = 0xCA } } +#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) } diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index 14b7967e5b..790a55ebf3 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -9,13 +9,13 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER - select GENERIC_SPD_BIN + select HAVE_SPD_IN_CBFS select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD @@ -47,10 +47,6 @@ config CONSOLE_POST bool default y -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index eac27b56f1..bffb6683ac 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( 0x20110725 // OEM revision ) { - #include + #include #include #include diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 7399f22693..5be310cf80 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -4,7 +4,7 @@ if BOARD_TI_BEAGLEBONE config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_TI_AM335X + select SOC_TI_AM335X select BOARD_ROMSIZE_KB_4096 select MISSING_BOARD_RESET diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 6e9538b229..b7b0ee9806 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -3,13 +3,13 @@ #include #include #include -#include -#include -#include +#include +#include +#include #include "leds.h" -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { write32(&am335x_cm_wkup->wkup_gpio0, CM_ST_SW_WKUP | CM_FCLK_EN); write32(&am335x_cm_per->gpio1, CM_ST_SW_WKUP | CM_FCLK_EN); diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone/devicetree.cb index dd999b4870..217a20175b 100644 --- a/src/mainboard/ti/beaglebone/devicetree.cb +++ b/src/mainboard/ti/beaglebone/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -chip cpu/ti/am335x +chip soc/ti/am335x device cpu_cluster 0 on end end diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index 99ae6d934a..df58feaa1b 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include +#include #include "leds.h" diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index cc8f98e2ef..63b9be91af 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -44,14 +44,6 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB -config SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - -config SUBSYSTEM_DEVICE_ID - hex - default 0x7270 - config VGA_BIOS_ID string default "8086,5a85" @@ -60,10 +52,6 @@ config PXE_ROM_ID string default "10ec,8168" -config MAX_CPUS - int - default 2 - config LINUX_COMMAND_LINE string default "console=ttyS4,115200 earlyprintk=ttyS4,115200,keep" if PAYLOAD_LINUXBOOT && UART_FOR_CONSOLE=0 diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index da2ff06f6a..9ed9985870 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -24,6 +24,7 @@ chip soc/intel/apollolake device lapic 0 on end end device domain 0 on + subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF device pci 00.2 off end # - NPK @@ -34,7 +35,7 @@ chip soc/intel/apollolake device pci 0d.2 off end # - SPI device pci 0d.3 off end # - Shared SRAM device pci 0e.0 on end # - Audio - device pci 0f.0 on end # - TXE + device pci 0f.0 on end # - TXE device pci 11.0 off end # - ISH device pci 12.0 on end # - SATA device pci 13.0 on end # - PCIe-A 1 - PcieRootPort[2] diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 894df8cafd..3182675052 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -2,759 +2,755 @@ #include -#ifndef GPIO_H -#define GPIO_H +#ifndef CFG_GPIO_H +#define CFG_GPIO_H +/* + * Pad configuration was generated automatically using intelp2m utility. + * + * todo: check HOSTSW_OWN_{NORTH, NORTHWEST, SOUTHWEST, WEST} to set DRIVER + * mode for the corresponding pads. + */ static const struct pad_config gpio_table[] = { - // ******************************** - // ******* GPIO Group North ******* - // ******************************** - // *GPIO - _PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000), + /* ------- GPIO Group North ------- */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000), + /* GPIO_0 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_0, NONE, PWROK, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000), + /* GPIO_1 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_1, NONE, PWROK, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000), + /* GPIO_2 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_2, NONE, PWROK, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000), + /* GPIO_3 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_3, NONE, PWROK, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000), + /* GPIO_4 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_4, NONE, PWROK, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000), + /* GPIO_5 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_5, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000), + /* GPIO_6 - *GPIO */ + PAD_CFG_GPO(GPIO_6, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000), + /* GPIO_7 - *GPIO */ + PAD_CFG_GPO(GPIO_7, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000), + /* GPIO_8 - *GPIO */ + PAD_CFG_GPO(GPIO_8, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000), + /* GPIO_9 - *GPIO */ + PAD_CFG_GPO(GPIO_9, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000), + /* GPIO_10 - *GPIO */ + PAD_CFG_GPO(GPIO_10, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000), + /* GPIO_11 - *GPIO */ + PAD_CFG_GPO(GPIO_11, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000), + /* GPIO_12 - *GPIO */ + PAD_CFG_GPO(GPIO_12, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000), + /* GPIO_13 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_13, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000), + /* GPIO_14 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_14, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000), + /* GPIO_15 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_15, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000), + /* GPIO_16 - *GPIO */ + PAD_CFG_GPI_SCI_IOS(GPIO_16, NONE, DEEP, LEVEL, INVERT, TxDRxE, SAME), - // *GPIO - _PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000), + /* GPIO_17 - *GPIO */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000), + /* GPIO_18 - *GPIO */ + PAD_CFG_GPO(GPIO_18, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000), + /* GPIO_19 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_19, 1, UP_20K, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000), + /* GPIO_20 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_20, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000), + /* GPIO_21 - *GPIO */ + PAD_CFG_GPO(GPIO_21, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000), + /* GPIO_22 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_22, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000), + /* GPIO_23 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_23, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000), + /* GPIO_24 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_24, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000), + /* GPIO_25 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_25, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000), + /* GPIO_26 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_26, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000), + /* GPIO_27 - *GPIO */ + PAD_CFG_GPO(GPIO_27, 1, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000), + /* GPIO_28 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_28, UP_20K, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000), + /* GPIO_29 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_29, UP_20K, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000), + /* GPIO_30 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_30, UP_20K, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000), + /* GPIO_31 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_31, UP_20K, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000), + /* GPIO_32 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_32, NONE, DEEP, OFF, ACPI), - // PWM0 - _PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000), + /* GPIO_33 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_33, NONE, DEEP, OFF, ACPI), - // PWM1 - _PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000), + /* GPIO_34 - PWM0 */ + PAD_CFG_NF(GPIO_34, DN_20K, DEEP, NF1), - // *GPIO - _PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000), + /* GPIO_35 - PWM1 */ + PAD_CFG_NF(GPIO_35, DN_20K, DEEP, NF1), - // PWM3 - _PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000), + /* GPIO_36 - *GPIO */ + PAD_CFG_GPO(GPIO_36, 1, DEEP), - // LPSS_UART0_RXD - _PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100), + /* GPIO_37 - PWM3 */ + PAD_CFG_NF(GPIO_37, DN_20K, PWROK, NF1), - // LPSS_UART0_TXD - _PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100), + /* GPIO_38 - LPSS_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPSS_UART0_RTS_N - _PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100), + /* GPIO_39 - LPSS_UART0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), - // LPSS_UART0_CTS_N - _PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100), + /* GPIO_40 - LPSS_UART0_RTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), - // LPSS_UART1_RXD - _PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100), + /* GPIO_41 - LPSS_UART0_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPSS_UART1_TXD - _PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100), + /* GPIO_42 - LPSS_UART1_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPSS_UART1_RTS_N - _PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100), + /* GPIO_43 - LPSS_UART1_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), - // LPSS_UART1_CTS_N - _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100), + /* GPIO_44 - LPSS_UART1_RTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), - // *GPIO - _PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000), + /* GPIO_45 - LPSS_UART1_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, NONE, DEEP, NF1, HIZCRx0, DISPUPD), - // *GPIO - _PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000), + /* GPIO_46 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_46, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000), + /* GPIO_47 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_47, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000), + /* GPIO_48 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_48, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000), + /* GPIO_49 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_49, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000), + /* GPIO_62 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_62, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000), + /* GPIO_63 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_63, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000), + /* GPIO_64 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_64, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000), + /* GPIO_65 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_65, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000), + /* GPIO_66 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_66, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000), + /* GPIO_67 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_67, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000), + /* GPIO_68 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_68, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000), + /* GPIO_69 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_69, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000), + /* GPIO_70 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_70, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000), + /* GPIO_71 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_71, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000), + /* GPIO_72 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_72, 0, DN_20K, DEEP), - // *JTAG_TCK - _PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000), + /* GPIO_73 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_73, 0, DN_20K, DEEP), - // *JTAG_TRST_N - _PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000), + /* TCK - *JTAG_TCK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(TCK, DN_20K, DEEP, NF1), - // *JTAG_TMS - _PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000), + /* TRST_B - *JTAG_TRST_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(TRST_B, DN_20K, DEEP, NF1), - // *JTAG_TDI - _PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000), + /* TMS - *JTAG_TMS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(TMS, UP_20K, DEEP, NF1), - // *JTAG_PMODE - _PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000), + /* TDI - *JTAG_TDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(TDI, UP_20K, DEEP, NF1), - // *JTAG_PREQ_N - _PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000), + /* CX_PMODE - *JTAG_PMODE */ + PAD_CFG_NF_IOSTANDBY_IGNORE(CX_PMODE, NONE, DEEP, NF1), - // *JTAGX - _PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000), + /* CX_PREQ_B - *JTAG_PREQ_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(CX_PREQ_B, UP_20K, DEEP, NF1), - // *JTAG_PRDY_N - _PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000), + /* JTAGX - *JTAGX */ + PAD_CFG_NF_IOSTANDBY_IGNORE(JTAGX, UP_20K, DEEP, NF1), - // *JTAG_TDO - _PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000), + /* CX_PRDY_B - *JTAG_PRDY_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(CX_PRDY_B, UP_20K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000), + /* TDO - *JTAG_TDO */ + PAD_CFG_NF_IOSTANDBY_IGNORE(TDO, UP_20K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400), + /* CNV_BRI_DT - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(CNV_BRI_DT, 1, DEEP, DN_20K, IGNORE, SAME), - // GPIO - _PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000), + /* CNV_BRI_RSP - GPIO */ + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_1K, DEEP), - // RESERVED -// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff), + /* CNV_RGI_DT - GPIO */ + PAD_CFG_GPO(CNV_RGI_DT, 1, DEEP), - // GPIO - _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000), + /* CNV_RGI_RSP - RESERVED */ - // GPIO - _PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000), + /* SVID0_ALERT_B - GPIO */ + PAD_CFG_GPI_TRIG_OWN(SVID0_ALERT_B, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000), + /* SVID0_DATA - GPIO */ + PAD_CFG_GPI_TRIG_OWN(SVID0_DATA, NONE, DEEP, OFF, ACPI), + /* SVID0_CLK - GPIO */ + PAD_CFG_GPI_TRIG_OWN(SVID0_CLK, NONE, DEEP, OFF, ACPI), - // ************************************ - // ******* GPIO Group NorthWest ******* - // ************************************ - // *DDI0_DDC_SDA - _PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000), + /* ------- GPIO Group North-West ------- */ - // *DDI0_DDC_SCL - _PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000), + /* GPIO_187 - *DDI0_DDC_SDA */ + PAD_CFG_NF_IOSSTATE(GPIO_187, UP_20K, DEEP, NF1, HIZCRx0), - // *DDI1_DDC_SDA - _PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00), + /* GPIO_188 - *DDI0_DDC_SCL */ + PAD_CFG_NF_IOSSTATE(GPIO_188, UP_20K, DEEP, NF1, HIZCRx0), - // *DDI1_DDC_SCL - _PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00), + /* GPIO_189 - *DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_189, UP_2K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000), + /* GPIO_190 - *DDI1_DDC_SCL */ + PAD_CFG_NF(GPIO_190, UP_2K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000), + /* GPIO_191 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_191, NONE, DEEP, OFF, ACPI), - // *PNL0_VDDEN - _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000), + /* GPIO_192 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_192, NONE, DEEP, OFF, ACPI), - // *PNL0_BKLTEN - _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000), + /* GPIO_193 - *PNL0_VDDEN */ + PAD_CFG_NF_IOSSTATE(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0), - // *PNL0_BKLTCTL - _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000), + /* GPIO_194 - *PNL0_BKLTEN */ + PAD_CFG_NF_IOSSTATE(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0), - // GPIO - _PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000), + /* GPIO_195 - *PNL0_BKLTCTL */ + PAD_CFG_NF_IOSSTATE(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0), - // GPIO - _PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000), + /* GPIO_196 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_196, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000), + /* GPIO_197 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_197, NONE, DEEP, OFF, ACPI), - // DDI1_HPD - _PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000), + /* GPIO_198 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_198, NONE, DEEP, OFF, ACPI), - // DDI0_HPD - _PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000), + /* GPIO_199 - DDI1_HPD */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), - // GPIO - _PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000), + /* GPIO_200 - DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), - // GPIO - _PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000), + /* GPIO_201 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_201, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000), + /* GPIO_202 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_202, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000), + /* GPIO_203 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_203, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000), + /* GPIO_204 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_204, NONE, DEEP, OFF, ACPI), - // DDI2_HPD - _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000), + /* PMC_SPI_FS0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMC_SPI_FS0, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000), + /* PMC_SPI_FS1 - DDI2_HPD */ + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000), + /* PMC_SPI_FS2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMC_SPI_FS2, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000), + /* PMC_SPI_RXD - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMC_SPI_RXD, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000), + /* PMC_SPI_TXD - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMC_SPI_TXD, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400), + /* PMC_SPI_CLK - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMC_SPI_CLK, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000), + /* PMIC_PWRGOOD - GPIO */ + PAD_CFG_TERM_GPO(PMIC_PWRGOOD, 1, UP_1K, DEEP), - // GPIO - _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), + /* PMIC_RESET_B - GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(PMIC_RESET_B, NONE, DEEP, OFF, IGNORE, ACPI), - // GPIO - _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00003300), + /* GPIO_213 - GPIO */ + PAD_CFG_TERM_GPO(GPIO_213, 1, UP_20K, DEEP), - // GPIO - _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00003300), + /* GPIO_214 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_214, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, ACPI), - // *THERMTRIP_N - _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), + /* GPIO_215 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_215, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000), + /* PMIC_THERMTRIP_B - *THERMTRIP_N */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), - // *PROCHOT_N - _PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000), + /* PMIC_STDBY - GPIO */ + PAD_CFG_TERM_GPO(PMIC_STDBY, 1, DN_20K, DEEP), - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff), + /* PROCHOT_B - *PROCHOT_N */ + PAD_CFG_NF_IOSSTATE(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1), - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff), + /* PMIC_I2C_SCL - RESERVED */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000), + /* PMIC_I2C_SDA - RESERVED */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000), + /* GPIO_74 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_74, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000), + /* GPIO_75 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_75, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000), + /* GPIO_76 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_76, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000), + /* GPIO_77 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_77, NONE, DEEP, OFF, ACPI), - // AVS_DMIC_CLK_A1 - _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000), + /* GPIO_78 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_78, NONE, DEEP, OFF, ACPI), - // AVS_DMIC_CLK_B1 - _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000), + /* GPIO_79 - AVS_DMIC_CLK_A1 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, DN_20K, DEEP, NF1), - // AVS_DMIC_DATA_1 - _PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200), + /* GPIO_80 - AVS_DMIC_CLK_B1 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, DN_20K, DEEP, NF1), - // AVS_DMIC_CLK_AB2 - _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000), + /* GPIO_81 - AVS_DMIC_DATA_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_81, DN_20K, DEEP, NF1, TxDRxE, ENPD), - // AVS_DMIC_DATA_2 - _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200), + /* GPIO_82 - AVS_DMIC_CLK_AB2 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, DN_20K, DEEP, NF1), - // AVS_I2S2_MCLK - _PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000), + /* GPIO_83 - AVS_DMIC_DATA_2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, TxDRxE, ENPD), - // AVS_I2S2_BCLK - _PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200), + /* GPIO_84 - AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF1), - // AVS_I2S2_WS_SYNC - _PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200), + /* GPIO_85 - AVS_I2S2_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_85, DN_20K, DEEP, NF1, HIZCRx0, ENPD), - // AVS_I2S2_SDI - _PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200), + /* GPIO_86 - AVS_I2S2_WS_SYNC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_86, DN_20K, DEEP, NF1, HIZCRx0, ENPD), - // AVS_I2S2_SDO - _PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200), + /* GPIO_87 - AVS_I2S2_SDI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_87, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // *GPIO - _PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000), + /* GPIO_88 - AVS_I2S2_SDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_88, NONE, DEEP, NF1, HIZCRx0, ENPD), - // *GPIO - _PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000), + /* GPIO_89 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_89, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000), + /* GPIO_90 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_90, NONE, DEEP, OFF, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000), + /* GPIO_91 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_91, NONE, DEEP, OFF, ACPI), - // *FST_SPI_CS0_N - _PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00), + /* GPIO_92 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_92, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000), + /* GPIO_97 - *FST_SPI_CS0_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_97, NATIVE, DEEP, NF1), - // *FST_SPI_MOSI_IO0 - _PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00), + /* GPIO_98 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_98, NONE, DEEP, OFF, ACPI), - // *FST_SPI_MISO_IO1 - _PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00), + /* GPIO_99 - *FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, NATIVE, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000), + /* GPIO_100 - *FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NATIVE, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000), + /* GPIO_101 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_101, NONE, DEEP, OFF, ACPI), - // *FST_SPI_CLK - _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00), + /* GPIO_102 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_102, NONE, DEEP, OFF, ACPI), - // *n/a - _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000), + /* GPIO_103 - *FST_SPI_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NATIVE, DEEP, NF1), - // SIO_SPI_0_CLK - _PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200), + /* FST_SPI_CLK_FB - *n/a */ + PAD_CFG_NF_IOSTANDBY_IGNORE(FST_SPI_CLK_FB, NONE, DEEP, NF1), - // SIO_SPI_0_FS0 - _PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200), + /* GPIO_104 - SIO_SPI_0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), - // SIO_SPI_0_FS1 - _PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200), + /* GPIO_105 - SIO_SPI_0_FS0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // SIO_SPI_0_RXD - _PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200), + /* GPIO_106 - SIO_SPI_0_FS1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // SIO_SPI_0_TXD - _PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200), + /* GPIO_109 - SIO_SPI_0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // SIO_SPI_1_CLK - _PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000), + /* GPIO_110 - SIO_SPI_0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // SIO_SPI_1_FS0 - _PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000), + /* GPIO_111 - SIO_SPI_1_CLK */ + PAD_CFG_NF(GPIO_111, DN_20K, DEEP, NF1), - // SIO_SPI_1_FS1 - _PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000), + /* GPIO_112 - SIO_SPI_1_FS0 */ + PAD_CFG_NF(GPIO_112, DN_20K, DEEP, NF1), - // SIO_SPI_1_RXD - _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000), + /* GPIO_113 - SIO_SPI_1_FS1 */ + PAD_CFG_NF(GPIO_113, DN_20K, DEEP, NF1), - // SIO_SPI_1_TXD - _PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000), + /* GPIO_116 - SIO_SPI_1_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_116, DN_20K, DEEP, NF1, HIZCRx0), - // SIO_SPI_2_CLK - _PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000), + /* GPIO_117 - SIO_SPI_1_TXD */ + PAD_CFG_NF(GPIO_117, DN_20K, DEEP, NF1), - // SIO_SPI_2_FS0 - _PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000), + /* GPIO_118 - SIO_SPI_2_CLK */ + PAD_CFG_NF(GPIO_118, DN_20K, DEEP, NF1), - // SIO_SPI_2_FS1 - _PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000), + /* GPIO_119 - SIO_SPI_2_FS0 */ + PAD_CFG_NF(GPIO_119, DN_20K, DEEP, NF1), - // SIO_SPI_2_FS2 - _PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000), + /* GPIO_120 - SIO_SPI_2_FS1 */ + PAD_CFG_NF(GPIO_120, DN_20K, DEEP, NF1), - // SIO_SPI_2_RXD - _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000), + /* GPIO_121 - SIO_SPI_2_FS2 */ + PAD_CFG_NF(GPIO_121, DN_20K, DEEP, NF1), - // SIO_SPI_2_TXD - _PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000), + /* GPIO_122 - SIO_SPI_2_RXD */ + PAD_CFG_NF(GPIO_122, DN_20K, DEEP, NF1), + /* GPIO_123 - SIO_SPI_2_TXD */ + PAD_CFG_NF(GPIO_123, DN_20K, DEEP, NF1), - // ******************************* - // ******* GPIO Group West ******* - // ******************************* - // LPSS_I2C0_SDA - _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700), + /* ------- GPIO Group West ------- */ - // LPSS_I2C0_SCL - _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700), + /* GPIO_124 - LPSS_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C1_SDA - _PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700), + /* GPIO_125 - LPSS_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C1_SCL - _PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700), + /* GPIO_126 - LPSS_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C2_SDA - _PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700), + /* GPIO_127 - LPSS_I2C1_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C2_SCL - _PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700), + /* GPIO_128 - LPSS_I2C2_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C3_SDA - _PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700), + /* GPIO_129 - LPSS_I2C2_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C3_SCL - _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700), + /* GPIO_130 - LPSS_I2C3_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C4_SDA - _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700), + /* GPIO_131 - LPSS_I2C3_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C4_SCL - _PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700), + /* GPIO_132 - LPSS_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C5_SDA - _PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200), + /* GPIO_133 - LPSS_I2C4_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, ENPU), - // LPSS_I2C5_SCL - _PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200), + /* GPIO_134 - LPSS_I2C5_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_134, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // LPSS_I2C6_SDA - _PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200), + /* GPIO_135 - LPSS_I2C5_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_135, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // LPSS_I2C6_SCL - _PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200), + /* GPIO_136 - LPSS_I2C6_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_136, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // LPSS_I2C7_SDA - _PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700), + /* GPIO_137 - LPSS_I2C6_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_137, UP_20K, DEEP, NF1, HIZCRx0, ENPD), - // LPSS_I2C7_SCL - _PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700), + /* GPIO_138 - LPSS_I2C7_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), - // AVS_I2S6_BCLK - _PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000), + /* GPIO_139 - LPSS_I2C7_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_1K, DEEP, NF1, Tx0RxDCRx0, ENPU), - // AVS_I2S6_WS_SYNC - _PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000), + /* GPIO_146 - AVS_I2S6_BCLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_146, DN_20K, DEEP, NF2), - // AVS_I2S6_SDI - _PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000), + /* GPIO_147 - AVS_I2S6_WS_SYNC */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_147, DN_20K, DEEP, NF2), - // AVS_I2S6_SDO - _PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000), + /* GPIO_148 - AVS_I2S6_SDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_148, DN_20K, DEEP, NF2), - // AVS_I2S5_BCLK - _PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200), + /* GPIO_149 - AVS_I2S6_SDO */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_149, DN_20K, DEEP, NF2), - // AVS_I2S5_WS_SYNC - _PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200), + /* GPIO_150 - AVS_I2S5_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, DN_20K, DEEP, NF2, HIZCRx0, ENPD), - // AVS_I2S5_SDI - _PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200), + /* GPIO_151 - AVS_I2S5_WS_SYNC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, DN_20K, DEEP, NF2, HIZCRx0, ENPD), - // AVS_I2S5_SDO - _PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200), + /* GPIO_152 - AVS_I2S5_SDI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, DN_20K, DEEP, NF2, HIZCRx0, ENPD), - // *GPIO - _PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000), + /* GPIO_153 - AVS_I2S5_SDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, NONE, DEEP, NF2, HIZCRx0, ENPD), - // SPKR - _PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000), + /* GPIO_154 - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_154, NONE, DEEP, OFF, ACPI), - // *PCIE_CLKREQ0_N - _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000), + /* GPIO_155 - SPKR */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_155, DN_20K, DEEP, NF2), - // *PCIE_CLKREQ1_N - _PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000), + /* GPIO_209 - *PCIE_CLKREQ0_N */ + PAD_CFG_NF(GPIO_209, DN_20K, DEEP, NF1), - // *PCIE_CLKREQ2_N - _PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000), + /* GPIO_210 - *PCIE_CLKREQ1_N */ + PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1), - // *PCIE_CLKREQ3_N - _PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000), + /* GPIO_211 - *PCIE_CLKREQ2_N */ + PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1), - // *OSC_CLK_OUT_0 - _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000), + /* GPIO_212 - *PCIE_CLKREQ3_N */ + PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1), - // *OSC_CLK_OUT_1 - _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_0 - *OSC_CLK_OUT_0 */ + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), - // *OSC_CLK_OUT_2 - _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_1 - *OSC_CLK_OUT_1 */ + PAD_CFG_NF(OSC_CLK_OUT_1, DN_20K, DEEP, NF1), - // *OSC_CLK_OUT_3 - _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_2 - *OSC_CLK_OUT_2 */ + PAD_CFG_NF(OSC_CLK_OUT_2, DN_20K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000), + /* OSC_CLK_OUT_3 - *OSC_CLK_OUT_3 */ + PAD_CFG_NF(OSC_CLK_OUT_3, DN_20K, DEEP, NF1), - // *GPIO - _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000), + /* OSC_CLK_OUT_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(OSC_CLK_OUT_4, NONE, DEEP, OFF, ACPI), - // GPIO - _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000), + /* PMU_AC_PRESENT - *GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMU_AC_PRESENT, NONE, DEEP, OFF, ACPI), - // *PMU_PLTRST_N - _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000), + /* PMU_BATLOW_B - GPIO */ + PAD_CFG_GPI_TRIG_OWN(PMU_BATLOW_B, NONE, DEEP, OFF, ACPI), - // *PMU_PWRBTN_N - _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000), + /* PMU_PLTRST_B - *PMU_PLTRST_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PLTRST_B, NONE, DEEP, NF1), - // *PMU_RSTBTN_N - _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000), + /* PMU_PWRBTN_B - *PMU_PWRBTN_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PWRBTN_B, UP_20K, DEEP, NF1), - // *PMU_SLP_S0_N - _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000), + /* PMU_RESETBUTTON_B - *PMU_RSTBTN_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), - // *PMU_SLP_S3_N - _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000), + /* PMU_SLP_S0_B - *PMU_SLP_S0_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), - // *PMU_SLP_S4_N - _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000), + /* PMU_SLP_S3_B - *PMU_SLP_S3_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S3_B, NONE, DEEP, NF1), - // *PMU_SUSCLK - _PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000), + /* PMU_SLP_S4_B - *PMU_SLP_S4_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S4_B, NONE, DEEP, NF1), - // *GPIO - _PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000), + /* PMU_SUSCLK - *PMU_SUSCLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SUSCLK, NONE, DEEP, NF1), - // *SUS_STAT_B - _PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000), + /* PMU_WAKE_B - *GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 1, DEEP, UP_20K, IGNORE, SAME), - // GPIO - _PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000), + /* SUS_STAT_B - *SUS_STAT_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SUS_STAT_B, NONE, DEEP, NF1), + /* SUSPWRDNACK - GPIO */ + PAD_CFG_GPI_TRIG_OWN(SUSPWRDNACK, NONE, DEEP, OFF, ACPI), - // ************************************ - // ******* GPIO Group SouthWest ******* - // ************************************ - // PCIE_WAKE0_N - _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000), + /* ------- GPIO Group South-West ------- */ - // PCIE_WAKE1_N - _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000), + /* GPIO_205 - PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), - // PCIE_WAKE2_N - _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000), + /* GPIO_206 - PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), - // PCIE_WAKE3_N - _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000), + /* GPIO_207 - PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), - // *EMMC_CLK - _PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000), + /* GPIO_208 - PCIE_WAKE3_N */ + PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), - // *EMMC_D0 - _PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000), + /* GPIO_156 - *EMMC_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), - // *EMMC_D1 - _PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000), + /* GPIO_157 - *EMMC_D0 */ + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D2 - _PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000), + /* GPIO_158 - *EMMC_D1 */ + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D3 - _PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000), + /* GPIO_159 - *EMMC_D2 */ + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D4 - _PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000), + /* GPIO_160 - *EMMC_D3 */ + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D5 - _PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000), + /* GPIO_161 - *EMMC_D4 */ + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D6 - _PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000), + /* GPIO_162 - *EMMC_D5 */ + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_D7 - _PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000), + /* GPIO_163 - *EMMC_D6 */ + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), - // *EMMC_CMD - _PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000), + /* GPIO_164 - *EMMC_D7 */ + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), - // *GPIO - _PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000), + /* GPIO_165 - *EMMC_CMD */ + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), - // *GPIO - _PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000), + /* GPIO_166 - *GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_166, DN_20K, DEEP, TxLASTRxE, SAME), - // *GPIO - _PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000), + /* GPIO_167 - *GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_167, UP_20K, DEEP, OFF, HIZCRx1, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000), + /* GPIO_168 - *GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_168, UP_20K, DEEP, OFF, HIZCRx1, ACPI), - // *GPIO - _PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000), + /* GPIO_169 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_169, 0, UP_20K, DEEP), - // *GPIO - _PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000), + /* GPIO_170 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_170, 1, UP_20K, DEEP), - // SDCARD_CLK - _PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100), + /* GPIO_171 - *GPIO */ + PAD_CFG_TERM_GPO(GPIO_171, 1, UP_20K, DEEP), - // n/a - _PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000), + /* GPIO_172 - SDCARD_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // SDCARD_D0 - _PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100), + /* GPIO_179 - n/a */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), - // SDCARD_D1 - _PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000), + /* GPIO_173 - SDCARD_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // SDCARD_D2 - _PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000), + /* GPIO_174 - SDCARD_D1 */ + PAD_CFG_NF_IOSSTATE(GPIO_174, UP_20K, DEEP, NF1, HIZCRx1), - // SDCARD_D3 - _PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000), + /* GPIO_175 - SDCARD_D2 */ + PAD_CFG_NF_IOSSTATE(GPIO_175, UP_20K, DEEP, NF1, HIZCRx1), - // SDCARD_CD_B - _PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000), + /* GPIO_176 - SDCARD_D3 */ + PAD_CFG_NF_IOSSTATE(GPIO_176, UP_20K, DEEP, NF1, HIZCRx1), - // SDCARD_CMD - _PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100), + /* GPIO_177 - SDCARD_CD_B */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), - // SDCARD_LVL_WP - _PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000), + /* GPIO_178 - SDCARD_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // *EMMC_RCLK - _PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000), + /* GPIO_186 - SDCARD_LVL_WP */ + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), - // GPIO - _PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000), + /* GPIO_182 - *EMMC_RCLK */ + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), - // SMB_ALERT_N - _PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000), + /* GPIO_183 - GPIO */ + PAD_CFG_TERM_GPO(GPIO_183, 0, DN_20K, DEEP), - // SMB_CLK - _PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000), + /* SMB_ALERTB - SMB_ALERT_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, UP_20K, DEEP, NF1), - // SMB_DATA - _PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000), + /* SMB_CLK - SMB_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), - // LPC_ILB_SERIRQ - _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000), + /* SMB_DATA - SMB_DATA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), - // LPC_CLKOUT0 - _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100), + /* LPC_ILB_SERIRQ - LPC_ILB_SERIRQ */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), - // LPC_CLKOUT1 - _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100), + /* LPC_CLKOUT0 - LPC_CLKOUT0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_AD0 - _PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100), + /* LPC_CLKOUT1 - LPC_CLKOUT1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_AD1 - _PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100), + /* LPC_AD0 - LPC_AD0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_AD2 - _PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100), + /* LPC_AD1 - LPC_AD1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_AD3 - _PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100), + /* LPC_AD2 - LPC_AD2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_CLKRUNB - _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100), + /* LPC_AD3 - LPC_AD3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), - // LPC_FRAMEB - _PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100), + /* LPC_CLKRUNB - LPC_CLKRUNB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_FRAMEB - LPC_FRAMEB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), }; -#endif +#endif /* CFG_GPIO_H */ diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index ac6a38d355..3ce84a46f6 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -40,7 +40,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR if (spdAddress == 0) return AGESA_ERROR; - int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = smbus_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7c5ecdc8f4..c1e342cde9 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -27,7 +27,6 @@ static struct device *__f2_dev[FX_DEVS]; static struct device *__f4_dev[FX_DEVS]; static unsigned int fx_devs = 0; - struct dram_base_mask_t { u32 base; //[47:27] at [28:8] u32 mask; //[47:27] at [28:8] and enable at bit 0 diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 17e8aa8cca..70a7b92be0 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -39,7 +39,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9d41e7a1f1..207bec2d37 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -543,7 +543,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, return current; } - static struct device_operations northbridge_operations = { .read_resources = nb_read_resources, .set_resources = nb_set_resources, diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index b0cac6f0e6..58b35e09fd 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -39,7 +39,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 556e6fca4f..75e1f02c16 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index a97faeb8ea..af1198a001 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -37,7 +37,6 @@ void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); } - void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) { EmptyHeap(); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index a5280830ea..4822ead662 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -243,7 +243,6 @@ static void mchtest_control(mchtst_cc cmd) pci_write_config32(MCHDEV, MCHTST, dword); } - /** * */ diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 7a5d0b1ce5..4a8696d45a 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -12,40 +13,12 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - dev = dev_find_device(0x8086, 0x2a40, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e74354ebdb..a0e8fc0631 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 1be351890b..e362841fb3 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -9,10 +9,10 @@ void gm45_early_init(void) const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ - pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1); /* Setup EPBAR. */ pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 44917465d6..17838809fa 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -40,12 +40,12 @@ void gm45_early_reset(void/*const timings_t *const timings*/) CxDRBy_BOUND_MB(r+1, 128); } /* Set DCC mode to no operation and do magic 0xf0 thing. */ - MCHBAR32(DCC_MCHBAR) = - (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; + + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + /* Normally, we would set this after successful raminit. */ MCHBAR32(DCC_MCHBAR) |= (1 << 19); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index d9cfbf7090..95457fb4b7 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -10,13 +10,13 @@ #include typedef enum { - FSB_CLOCK_1067MHz = 0, - FSB_CLOCK_800MHz = 1, - FSB_CLOCK_667MHz = 2, + FSB_CLOCK_1067MHz = 0, + FSB_CLOCK_800MHz = 1, + FSB_CLOCK_667MHz = 2, } fsb_clock_t; typedef enum { /* Steppings below B1 were pre-production, - conversion stepping A1 is... ? + conversion stepping A1 is a newer GL40 with support for 800 MT/s on FSB/DDR. We'll support B1, B2, B3, and conversion stepping A1. */ STEPPING_A0 = 0, STEPPING_A1 = 1, @@ -43,12 +43,12 @@ typedef enum { } gmch_gfx_t; typedef enum { - MEM_CLOCK_533MHz = 0, - MEM_CLOCK_400MHz = 1, - MEM_CLOCK_333MHz = 2, - MEM_CLOCK_1067MT = 0, - MEM_CLOCK_800MT = 1, - MEM_CLOCK_667MT = 2, + MEM_CLOCK_533MHz = 0, + MEM_CLOCK_400MHz = 1, + MEM_CLOCK_333MHz = 2, + MEM_CLOCK_1067MT = 0, + MEM_CLOCK_800MT = 1, + MEM_CLOCK_667MT = 2, } mem_clock_t; typedef enum { @@ -132,6 +132,7 @@ typedef struct { int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ int sff; /* small form factor option (soldered down DIMM) */ } sysinfo_t; + #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) #define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf) @@ -167,59 +168,50 @@ enum { /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ -#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes - (could be reduced to 10 bytes) */ +#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ - -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) -#else #define DEFAULT_MCHBAR 0xfed14000 #define DEFAULT_DMIBAR 0xfed18000 -#endif #define DEFAULT_EPBAR 0xfed19000 -#define DEFAULT_HECIBAR ((u8 *)0xfed1a000) - -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 /* * D1:F0 PEG */ -#define PEG_CAP 0xa2 -#define SLOTCAP 0xb4 -#define PEGLC 0xec -#define D1F0_VCCAP 0x104 -#define D1F0_VC0RCTL 0x114 +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 /* * Graphics frequencies @@ -239,7 +231,7 @@ enum { * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) @@ -294,7 +286,7 @@ enum { * Every two ranks share one register and must be programmed at the same time. * All registers (4 ranks per channel) have to be set. */ -#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4)) +#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4)) #define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16) #define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r)) #define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \ @@ -352,46 +344,45 @@ enum { /* Write Training registers. */ #define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4)) -#define CxGTEW(x) (0x1270+(x*0x100)) -#define CxGTC(x) (0x1274+(x*0x100)) -#define CxDTPEW(x) (0x1278+(x*0x100)) -#define CxDTAEW(x) (0x1280+(x*0x100)) -#define CxDTC(x) (0x1288+(x*0x100)) +#define CxGTEW(x) (0x1270 + (x * 0x100)) +#define CxGTC(x) (0x1274 + (x * 0x100)) +#define CxDTPEW(x) (0x1278 + (x * 0x100)) +#define CxDTAEW(x) (0x1280 + (x * 0x100)) +#define CxDTC(x) (0x1288 + (x * 0x100)) /* * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 - +#define DMIVC0RCTL 0x14 +#define DMIVC1RCTL 0x20 +#define DMIVC1RSTS 0x26 +#define DMIESD 0x44 +#define DMILE1D 0x50 +#define DMILE1A 0x58 +#define DMILE2D 0x60 +#define DMILE2A 0x68 /* * EPBAR */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 - +#define EPESD 0x44 +#define EPLE1D 0x50 +#define EPLE1A 0x58 +#define EPLE2D 0x60 #ifndef __ACPI__ + void gm45_early_init(void); void gm45_early_reset(void); @@ -433,6 +424,7 @@ struct blc_pwm_t { int get_blc_values(const struct blc_pwm_t **entries); u16 get_blc_pwm_freq_value(const char *edid_ascii_string); +int decode_pcie_bar(u32 *const base, u32 *const len); #include diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3d48ca2c2b..c771ea2deb 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -31,8 +31,8 @@ void gtt_write(u32 reg, u32 data) static u32 get_cdclk(struct device *const dev) { - const u16 cdclk_sel = - pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: case VCO_4000: diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 24633cf96e..102af1c4c3 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -19,9 +19,6 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0); - u16 reg16; - u32 reg32; - printk(BIOS_DEBUG, "Enabling IGD.\n"); /* HSync/VSync */ @@ -35,15 +32,10 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) }; const int f0_12 = (pci_read_config16(igd_dev, 0xf0) >> 12) & 1; const int vco = raminit_read_vco_index(); - reg16 = pci_read_config16(igd_dev, 0xcc); - reg16 &= 0xfc00; - reg16 |= display_clock_from_f0_and_vco[f0_12][vco]; - pci_write_config16(igd_dev, 0xcc, reg16); - reg16 = pci_read_config16(mch_dev, D0F0_GGC); - reg16 &= 0xf00f; - reg16 |= sysinfo->ggc; - pci_write_config16(mch_dev, D0F0_GGC, reg16); + pci_update_config16(igd_dev, 0xcc, 0xfc00, display_clock_from_f0_and_vco[f0_12][vco]); + + pci_update_config16(mch_dev, D0F0_GGC, 0xf00f, sysinfo->ggc); if ((sysinfo->gfx_type != GMCH_GL40) && (sysinfo->gfx_type != GMCH_GS40) && @@ -54,21 +46,13 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) pci_write_config32(mch_dev, D0F0_DEVEN, deven | 2); /* Some IGD related settings on D1:F0. */ - reg16 = pci_read_config16(peg_dev, 0xa08); - reg16 &= ~(1 << 15); - pci_write_config16(peg_dev, 0xa08, reg16); + pci_and_config16(peg_dev, 0xa08, (u16)~(1 << 15)); - reg16 = pci_read_config16(peg_dev, 0xa84); - reg16 |= (1 << 8); - pci_write_config16(peg_dev, 0xa84, reg16); + pci_or_config16(peg_dev, 0xa84, 1 << 8); - reg16 = pci_read_config16(peg_dev, 0xb00); - reg16 |= (3 << 8) | (7 << 3); - pci_write_config16(peg_dev, 0xb00, reg16); + pci_or_config16(peg_dev, 0xb00, (3 << 8) | (7 << 3)); - reg32 = pci_read_config32(peg_dev, 0xb14); - reg32 &= ~(1 << 17); - pci_write_config32(peg_dev, 0xb14, reg32); + pci_and_config32(peg_dev, 0xb14, ~(1 << 17)); if (!(deven & 2) || no_peg) { /* Disable PEG finally. */ @@ -76,16 +60,14 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) "PEG in favor of IGD.\n"); MCHBAR8(0xc14) |= (1 << 5) | (1 << 0); - reg32 = pci_read_config32(peg_dev, 0x200); - reg32 |= (1 << 18); - pci_write_config32(peg_dev, 0x200, reg32); - reg16 = pci_read_config16(peg_dev, 0x224); - reg16 |= (1 << 8); - pci_write_config16(peg_dev, 0x224, reg16); - reg32 = pci_read_config32(peg_dev, 0x200); - reg32 &= ~(1 << 18); - pci_write_config32(peg_dev, 0x200, reg32); - while (pci_read_config32(peg_dev, 0x214) & 0x000f0000); + pci_or_config32(peg_dev, 0x200, 1 << 18); + + pci_or_config16(peg_dev, 0x224, 1 << 8); + + pci_and_config32(peg_dev, 0x200, ~(1 << 18)); + + while (pci_read_config32(peg_dev, 0x214) & (0xf << 16)) + ; pci_write_config32(mch_dev, D0F0_DEVEN, deven & ~2); MCHBAR8(0xc14) &= ~((1 << 5) | (1 << 0)); @@ -99,12 +81,9 @@ static void disable_igd(const sysinfo_t *const sysinfo) printk(BIOS_DEBUG, "Disabling IGD.\n"); - u16 reg16; + /* Disable Graphics Stolen Memory. */ + pci_update_config16(mch_dev, D0F0_GGC, 0xff0f, 0x0002); - reg16 = pci_read_config16(mch_dev, D0F0_GGC); - reg16 &= 0xff0f; /* Disable Graphics Stolen Memory. */ - reg16 |= 0x0002; /* Disable IGD. */ - pci_write_config16(mch_dev, D0F0_GGC, reg16); MCHBAR8(0xf10) |= (1 << 0); if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) { @@ -114,9 +93,7 @@ static void disable_igd(const sysinfo_t *const sysinfo) } /* Hide IGD. */ - u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN); - deven &= ~(3 << 3); - pci_write_config32(mch_dev, D0F0_DEVEN, deven); + pci_and_config32(mch_dev, D0F0_DEVEN, ~(3 << 3)); } void init_igd(const sysinfo_t *const sysinfo) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 439127d17d..09df12d18a 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -50,11 +50,10 @@ void init_iommu() if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; const pci_devfn_t peg = PCI_DEV(0, 1, 0); + /* FIXME: proper test? */ - if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { - int val = pci_read_config32(peg, 0xfc) | (1 << 15); - pci_write_config32(peg, 0xfc, val); - } + if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) + pci_or_config32(peg, 0xfc, 1 << 15); } /* final */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index b3dbe16b75..8c27d50eb6 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -20,7 +21,7 @@ static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 128; -static int decode_pcie_bar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; @@ -37,15 +38,15 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ *base = pciexbar_reg & (0x0f << 28); - *len = 256 * 1024 * 1024; + *len = 256 * MiB; return 1; case 1: /* 128M */ *base = pciexbar_reg & (0x1f << 27); - *len = 128 * 1024 * 1024; + *len = 128 * MiB; return 1; case 2: /* 64M */ *base = pciexbar_reg & (0x3f << 26); - *len = 64 * 1024 * 1024; + *len = 64 * MiB; return 1; } @@ -259,12 +260,12 @@ static void gm45_init(void *const chip_info) break; } for (; fn >= 0; --fn) { - const struct device *const d = - pcidev_on_root(dev, fn); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + const struct device *const d = pcidev_on_root(dev, fn); + if (!d || d->enabled) + continue; + /* FIXME: Using bitwise ops changes the binary */ pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); + pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); } } diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index e4d11e335c..0eb1287f3b 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -92,9 +92,6 @@ static void init_pcie(const int peg_enabled, const int sdvo_enabled, const int peg_x16) { - u8 tmp8; - u16 tmp16; - u32 tmp; const pci_devfn_t mch = PCI_DEV(0, 0, 0); const pci_devfn_t pciex = PCI_DEV(0, 1, 0); @@ -103,20 +100,17 @@ static void init_pcie(const int peg_enabled, sdvo_enabled?"enabled":"disabled"); if (peg_enabled) { - tmp8 = pci_read_config8(mch, D0F0_DEVEN) | (1 << 1); - pci_write_config8(mch, D0F0_DEVEN, tmp8); + pci_or_config8(mch, D0F0_DEVEN, 1 << 1); - tmp8 = pci_read_config8(pciex, 0x224) & ~31; - pci_write_config8(pciex, 0x224, tmp8 | (peg_x16?16:0) | 1); + pci_write_config8(pciex, 0x224, + (pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1); - tmp16 = pci_read_config16(pciex, 0x224) & ~(1 << 8); - pci_write_config16(pciex, 0x224, tmp16); + pci_and_config16(pciex, 0x224, ~(1 << 8)); /* FIXME: fill in: slot or fixed? -> devicetree */ int peg_is_slot = 0; if (peg_is_slot) { - tmp16 = pci_read_config16(pciex, PEG_CAP) | (1 << 8); - pci_write_config16(pciex, PEG_CAP, tmp16); + pci_or_config16(pciex, PEG_CAP, 1 << 8); } /* FIXME: fill in: slot number, slot power -> devicetree */ @@ -125,20 +119,16 @@ static void init_pcie(const int peg_enabled, /* peg_power := val * 10^-exp */ int peg_power_val = 75; int peg_power_exp = 0; /* 0..3 */ - tmp = (peg_slot << 17) | (peg_power_exp << 15) | - (peg_power_val << 7); + const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7); pci_write_config32(pciex, SLOTCAP, tmp); /* GPEs */ - tmp8 = pci_read_config8(pciex, PEGLC) | 7; - pci_write_config8(pciex, PEGLC, tmp8); + pci_or_config8(pciex, PEGLC, 7); /* VC0: TC0 only, VC0 only */ - tmp8 = pci_read_config8(pciex, D1F0_VC0RCTL); - pci_write_config8(pciex, D1F0_VC0RCTL, tmp8 & 1); + pci_and_config8(pciex, D1F0_VC0RCTL, 1); - tmp8 = pci_read_config8(pciex, D1F0_VCCAP); - pci_write_config8(pciex, D1F0_VCCAP, tmp8 & ~7); + pci_and_config8(pciex, D1F0_VCCAP, ~7); } } @@ -149,37 +139,26 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) /* Prerequisites for ASPM: */ if (peg_enabled) { - tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13); - pci_write_config32(pciex, 0x200, tmp32); + pci_or_config32(pciex, 0x200, 3 << 13); - tmp32 = pci_read_config32(pciex, 0x0f0); - tmp32 &= ~((1 << 27) | (1 << 26)); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26))); - tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_or_config32(pciex, 0x0f0, 3 << 24); - tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4); - pci_write_config32(pciex, 0x0f4, tmp32); + pci_and_config32(pciex, 0x0f4, ~(1 << 4)); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 0); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 1); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 4); - tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_and_config32(pciex, 0x0fc, ~(7 << 5)); /* Set L0s, L1 supported in LCTL? */ - tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0); - pci_write_config32(pciex, 0x0b0, tmp32); + pci_or_config32(pciex, 0x0b0, 3 << 0); - tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_or_config32(pciex, 0x0f0, 3 << 24); tmp32 = pci_read_config32(pciex, 0x0f0); if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) @@ -217,41 +196,27 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) DMIBAR32(0x0e2c) = 0x88d07333; } if (peg_enabled) { - tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15); - pci_write_config32(pciex, 0xa08, tmp32); + pci_and_config32(pciex, 0xa08, ~(1 << 15)); - tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_or_config32(pciex, 0xa84, 1 << 8); - tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17); - pci_write_config32(pciex, 0xb14, tmp32); + pci_and_config32(pciex, 0xb14, ~(1 << 17)); - tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8); - pci_write_config32(pciex, 0xb00, tmp32); + pci_or_config32(pciex, 0xb00, 3 << 8); - tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3); - pci_write_config32(pciex, 0xb00, tmp32); + pci_or_config32(pciex, 0xb00, 7 << 3); - tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_and_config32(pciex, 0xa84, ~(1 << 8)); - tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_or_config32(pciex, 0xa84, 1 << 8); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23); - pci_write_config32(pciex, 0xb04, tmp32); + pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 |= (1 << 31); - pci_write_config32(pciex, 0xb04, tmp32); + pci_or_config32(pciex, 0xb04, 1 << 31); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29); - pci_write_config32(pciex, 0xb04, tmp32); + pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29); } - /*\ Setup ASPM on DMI \*/ /* Exit latencies should be checked to be supported by @@ -266,7 +231,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); - /*\ Setup ASPM on PEG \*/ /* * Maybe we just have to advertise ASPM through LCAP[11:10] @@ -286,13 +250,12 @@ static void setup_rcrb(const int peg_enabled) /* Link1: component ID 1, link valid. */ EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = DEFAULT_DMIBAR; if (peg_enabled) /* Link2: link_valid. */ EPBAR8(EPLE2D) |= (1 << 0); /* link valid */ - /*\ RCRB setup: DMI Port \*/ /* Set component ID of MCH (1). */ @@ -305,7 +268,7 @@ static void setup_rcrb(const int peg_enabled) /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = DEFAULT_MCHBAR; } void gm45_late_init(const stepping_t stepping) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 86c7ace983..7fc97f01a1 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -216,7 +216,6 @@ void enter_raminit_or_reset(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); } - /* For a detected DIMM, test the value of an SPD byte to match the expected value after masking some bits. */ static int test_dimm(sysinfo_t *const sysinfo, @@ -281,7 +280,6 @@ static void verify_ddr3(sysinfo_t *const sysinfo, int mask) } } - typedef struct { int dimm_mask; struct { @@ -808,8 +806,7 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); /* Clear update bit. */ - pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, - pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE); + pci_and_config16(GCFGC_PCIDEV, GCFGC_OFFSET, ~GCFGC_UPDATE); /* Set display clock select bit. */ pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, @@ -1229,10 +1226,7 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode } /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); - reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ - pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); + pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); uma_sizem += 2; } @@ -1560,10 +1554,9 @@ static void jedec_init(const timings_t *const timings, MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); udelay(2); /* 5 6 7 8 9 10 11 12 */ @@ -1701,7 +1694,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) const timings_t *const timings = &sysinfo->selected_timings; int ch; - u8 reg8; timestamp_add_now(TS_BEFORE_INITRAM); @@ -1716,7 +1708,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Check for bad warm boot. */ reset_on_bad_warmboot(); - /***** From now on, program according to collected infos: *****/ /* Program DRAM type. */ @@ -1773,15 +1764,13 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Announce normal operation, initialization completed. */ MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); /* Take a breath (the reader). */ - /* Perform ZQ calibration for DDR3. */ if (sysinfo->spd_type == DDR3) ddr3_calibrate_zq(); @@ -1811,8 +1800,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) dram_optimizations(timings, dimms); /* Mark raminit being finished. :-) */ - u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); raminit_thermal(sysinfo); init_igd(sysinfo); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index d51061267f..22aaee62d8 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -80,9 +80,8 @@ void mainboard_romstage_entry(void) mb_post_raminit_setup(); - const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ - pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); + pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000); init_pm(&sysinfo, 0); diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 952cc7b039..84be33df4e 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -6,7 +6,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc4d1..cc4487c43c 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -10,44 +11,12 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - u32 mask; + u32 length, pciexbar; - dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & mask; - max_buses = 256; - break; - case 1: /* 128M */ - mask |= (1 << 27); - pciexbar = pciexbar_reg & mask; - max_buses = 128; - break; - case 2: /* 64M */ - mask |= (1 << 27) | (1 << 26); - pciexbar = pciexbar_reg & mask; - max_buses = 64; - break; - default: /* RSVD */ - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index b8a1af8878..1d4eba69ff 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -173,12 +173,12 @@ Device (MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ CTCS = CTCD @@ -214,7 +214,7 @@ Device (MCHC) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ PL1V = CTDN diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be337..59c31aa672 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent * non-explicit config accesses use MCFG. This code also assumes that * bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 28c082838d..73375d788d 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,7 +17,6 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff359..5a6bb8e1de 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -108,6 +108,11 @@ u32 map_oprom_vendev(u32 vendev) case 0x8086042a: /* GT3 Server */ case 0x80860a26: /* GT3 ULT */ + case 0x80860d22: /* GT3e Desktop */ + case 0x80860d16: /* GT1 Mobile 4+3 */ + case 0x80860d26: /* GT2 Mobile 4+3, GT3e Mobile */ + case 0x80860d36: /* GT3 Mobile 4+3 */ + new_vendev = 0x80860406; /* GT1 Mobile */ break; } @@ -299,7 +304,6 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PCH_PP_ON_DELAYS, reg32); @@ -515,11 +519,12 @@ static const unsigned short pci_device_ids[] = { 0x0402, /* Desktop GT1 */ 0x0412, /* Desktop GT2 */ 0x0422, /* Desktop GT3 */ + 0x0d22, /* Desktop GT3e */ 0x0406, /* Mobile GT1 */ 0x0416, /* Mobile GT2 */ 0x0426, /* Mobile GT3 */ 0x0d16, /* Mobile 4+3 GT1 */ - 0x0d26, /* Mobile 4+3 GT2 */ + 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ 0x0d36, /* Mobile 4+3 GT3 */ 0x0a06, /* ULT GT1 */ 0x0a16, /* ULT GT2 */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index baa4f32614..4bcaaa7728 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -8,19 +8,7 @@ #define HASWELL_DESKTOP 1 #define HASWELL_SERVER 2 -/* Intel Enhanced Debug region */ -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - -#define GFXVT_BASE_ADDRESS 0xfed90000ULL -#define GFXVT_BASE_SIZE 0x1000 - -#define VTVC0_BASE_ADDRESS 0xfed91000ULL -#define VTVC0_BASE_SIZE 0x1000 +#include "memmap.h" #include @@ -30,67 +18,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 - -#define GGC 0x50 /* GMCH Graphics Control */ -#define GGC_DISABLE_VGA_IO_DECODE (1 << 1) -#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) -#define GGC_GTT_0MB (0 << 8) -#define GGC_GTT_1MB (1 << 8) -#define GGC_GTT_2MB (2 << 8) - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define LAC 0x87 /* Legacy Access Control */ -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -#define MESEG_BASE 0x70 /* Management Engine Base */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit */ -#define REMAPBASE 0x90 /* Remap base */ -#define REMAPLIMIT 0x98 /* Remap limit */ -#define TOM 0xa0 /* Top of DRAM in memory controller space */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ - -#define SKPAD 0xdc /* Scratchpad Data */ - -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define SPCAPCTRL (1 << 25) -#define L3HIT2PEND_DIS (1 << 20) -#define PRSCAPDIS (1 << 2) -#define GLBIOTLBINV (1 << 1) -#define GLBCTXTINV (1 << 0) - +#include "registers/host_bridge.h" /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -114,76 +42,35 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" + +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define SPCAPCTRL (1 << 25) +#define L3HIT2PEND_DIS (1 << 20) +#define PRSCAPDIS (1 << 2) +#define GLBIOTLBINV (1 << 1) +#define GLBCTXTINV (1 << 0) /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCAP2 0x008 /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define PORTARB 0x100 /* 256bit */ +#include "registers/epbar.h" /* * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ -#define DMIPVCCAP2 0x008 /* 32bit */ - -#define DMIPVCCCTL 0x00c /* 16bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ - -#define DMICC 0x208 /* 32bit */ - -#define DMIDRCCFG 0xeb4 /* 32bit */ +#include "registers/dmibar.h" #ifndef __ASSEMBLER__ @@ -198,6 +85,8 @@ void haswell_unhide_peg(void); void report_platform_info(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include struct acpi_rsdp; diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb788..807ee2a358 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,7 +18,7 @@ static uintptr_t smm_region_start(void) * 1 MiB alignment. */ uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return tom & ~((1 << 20) - 1); + return ALIGN_DOWN(tom, 1 * MiB); } void *cbmem_top_chipset(void) diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h new file mode 100644 index 0000000000..ac3b1dbef0 --- /dev/null +++ b/src/northbridge/intel/haswell/memmap.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ + +/* Intel Enhanced Debug region */ +#define IED_SIZE CONFIG_IED_REGION_SIZE + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + +#endif /* __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ */ diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index de2ce06410..1bfbfe5ca0 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -92,7 +92,7 @@ static struct device_operations minihd_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; +static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 }; static const struct pci_driver haswell_minihd __pci_driver = { .ops = &minihd_ops, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ef7742e523..e1c26d162c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -51,6 +51,11 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * return 0; } +int decode_pcie_bar(u32 *const base, u32 *const len) +{ + return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len); +} + static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -418,10 +423,69 @@ static void disable_devices(void) pci_write_config32(host_dev, DEVEN, deven); } +static void init_egress(void) +{ + /* VC0: Enable, ID0, TC0 */ + EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); + + /* No Low Priority Extended VCs, one Extended VC */ + EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); + + /* VC1: Enable, ID1, TC1 */ + EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); + + /* Poll the VC1 Negotiation Pending bit */ + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) + ; +} + +static void northbridge_dmi_init(void) +{ + const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); + + u16 reg16; + u32 reg32; + + /* Steps prior to DMI ASPM */ + if (is_haswell_h) { + /* Configure DMI De-Emphasis */ + reg16 = DMIBAR16(DMILCTL2); + reg16 |= (1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */ + DMIBAR16(DMILCTL2) = reg16; + + reg32 = DMIBAR32(DMIL0SLAT); + reg32 |= (1 << 31); + DMIBAR32(DMIL0SLAT) = reg32; + + reg32 = DMIBAR32(DMILLTC); + reg32 |= (1 << 29); + DMIBAR32(DMILLTC) = reg32; + + reg32 = DMIBAR32(DMI_AFE_PM_TMR); + reg32 &= ~0x1f; + reg32 |= 0x13; + DMIBAR32(DMI_AFE_PM_TMR) = reg32; + } + + /* Clear error status bits */ + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; + + if (is_haswell_h) { + /* Enable ASPM L0s and L1 on SA link, should happen before PCH link */ + reg16 = DMIBAR16(DMILCTL); + reg16 |= (1 << 1) | (1 << 0); + DMIBAR16(DMILCTL) = reg16; + } +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; + init_egress(); + northbridge_dmi_init(); + /* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ @@ -461,6 +525,9 @@ static const unsigned short mc_pci_device_ids[] = { 0x0c04, /* Mobile */ 0x0a04, /* ULT */ 0x0c08, /* Server */ + 0x0d00, /* Crystal Well Desktop */ + 0x0d04, /* Crystal Well Mobile */ + 0x0d08, /* Crystal Well Server (by extrapolation) */ 0 }; diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index a47a2f507c..d9e77a787a 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -61,7 +61,10 @@ static struct device_operations device_ops = { #endif }; -static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 }; +static const unsigned short pci_device_ids[] = { + 0x0c01, 0x0c05, 0x0c09, 0x0c0d, + 0x0d01, 0x0d05, 0x0d09, /* Crystal Well */ + 0 }; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8cd9e77aee..9c6c00ff16 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -30,21 +31,24 @@ void save_mrc_data(struct pei_data *pei_data) static void prepare_mrc_cache(struct pei_data *pei_data) { - struct region_device rdev; + size_t mrc_size; /* Preset just in case there is an error */ pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; - if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) + pei_data->mrc_input = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); + if (!pei_data->mrc_input) /* Error message printed in find_current_mrc_cache */ return; - pei_data->mrc_input = rdev_mmap_full(&rdev); - pei_data->mrc_input_len = region_device_sz(&rdev); + pei_data->mrc_input_len = mrc_size; - printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, - pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, + pei_data->mrc_input, mrc_size); } static const char *ecc_decoder[] = { @@ -170,6 +174,45 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } +static bool nb_supports_ecc(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_ECCDIS); +} + +static uint16_t nb_slots_per_channel(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_DDPCD) + 1; +} + +static uint16_t nb_number_of_channels(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_PDCD) + 1; +} + +static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) +{ + uint32_t ddrsz; + + /* Values from documentation, which assume two DIMMs per channel */ + switch (CAPID_DDRSZ(capid0_a)) { + case 1: + ddrsz = 8192; + break; + case 2: + ddrsz = 2048; + break; + case 3: + ddrsz = 512; + break; + default: + ddrsz = 16384; + break; + } + + /* Account for the maximum number of DIMMs per channel */ + return (ddrsz / 2) * nb_slots_per_channel(capid0_a); +} + void setup_sdram_meminfo(struct pei_data *pei_data) { u32 addr_decode_ch[2]; @@ -215,10 +258,18 @@ void setup_sdram_meminfo(struct pei_data *pei_data) (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); dimm->mod_type = SPD_SODIMM; - dimm->bus_width = 0x3; /* 64-bit */ + dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } } } mem_info->dimm_cnt = dimm_cnt; + + const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + + const uint16_t channels = nb_number_of_channels(capid0_a); + + mem_info->ecc_capable = nb_supports_ecc(capid0_a); + mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); + mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); } diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h new file mode 100644 index 0000000000..9d523825a7 --- /dev/null +++ b/src/northbridge/intel/haswell/registers/dmibar.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __HASWELL_REGISTERS_DMIBAR_H__ +#define __HASWELL_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIRCLDECH 0x040 /* 32bit */ +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMILCTL2 0x098 /* 16bit */ +#define DMILSTS2 0x09c /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMIL0SLAT 0x22c /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ + +#define DMI_AFE_PM_TMR 0xc28 /* 32bit */ + +#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h new file mode 100644 index 0000000000..963ceaddf4 --- /dev/null +++ b/src/northbridge/intel/haswell/registers/epbar.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __HASWELL_REGISTERS_EPBAR_H__ +#define __HASWELL_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#endif /* __HASWELL_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h new file mode 100644 index 0000000000..d348fd4a61 --- /dev/null +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#define __HASWELL_REGISTERS_HOST_BRIDGE_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 + +#define GGC 0x50 /* GMCH Graphics Control */ +#define GGC_DISABLE_VGA_IO_DECODE (1 << 1) +#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) +#define GGC_GTT_0MB (0 << 8) +#define GGC_GTT_1MB (1 << 8) +#define GGC_GTT_2MB (2 << 8) + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D1F0EN (1 << 3) +#define DEVEN_D1F1EN (1 << 2) +#define DEVEN_D1F2EN (1 << 1) +#define DEVEN_D0EN (1 << 0) + +#define PAVPC 0x58 +#define DPR 0x5c + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#define CAPID0_A 0xe4 +#define CAPID_ECCDIS (1 << 25) +#define VTD_DISABLE (1 << 23) +#define CAPID_DDPCD (1 << 14) +#define CAPID_PDCD (1 << 12) +#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) + +#define CAPID0_B 0xe8 + +#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/registers/mchbar.h similarity index 92% rename from src/northbridge/intel/haswell/mchbar_regs.h rename to src/northbridge/intel/haswell/registers/mchbar.h index 5fe15567e5..d6e59abe02 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_MCHBAR_REGS_H__ -#define __HASWELL_MCHBAR_REGS_H__ +#ifndef __HASWELL_REGISTERS_MCHBAR_H__ +#define __HASWELL_REGISTERS_MCHBAR_H__ /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ @@ -44,4 +44,4 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc -#endif /* __HASWELL_MCHBAR_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8ea4175c36..0b5319bdde 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -14,7 +15,6 @@ static void report_cpu_info(void) u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; const char *mode[] = {"NOT ", ""}; index = 0x80000000; @@ -35,13 +35,9 @@ static void report_cpu_info(void) while (cpu_name[0] == ' ') cpu_name++; - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpu_id, - microcode_ver.hi, cpu_name); + get_current_microcode_rev(), cpu_name); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; @@ -82,7 +78,6 @@ static void report_pch_info(void) int i; u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); - const char *pch_type = "Unknown"; for (i = 0; i < ARRAY_SIZE(pch_table); i++) { if (pch_table[i].dev_id == dev_id) { diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 39babf5336..5b025eba24 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -51,7 +51,7 @@ void mainboard_romstage_entry(void) .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 98d06fb8e1..a396a8835d 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -62,6 +62,7 @@ Method(_CRS, 0) { */ MM1B = \_SB.PCI0.NB.TOM1 Local0 = 0x10000000 << 4 + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B Return(TMP) diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 75a6da5175..232575f586 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -3,46 +3,19 @@ #include #include #include +#include #include #include #include "i945.h" unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - dev = pcidev_on_root(0, 0); - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225ca71..cdc77b5fa7 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -8,13 +8,13 @@ Method (_OSC, 4) { /* Check for proper PCI/PCIe UUID */ - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return(Arg3) } Else { CreateDWordField(Arg3, 0, CDW1) - Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 + CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } } @@ -52,22 +52,22 @@ Device (PDRC) Method (_CRS, 0, Serialized) { //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) + //RBR0 = \_SB.PCI0.LPCB.RCBA << 14 //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) + //MBR0 = \_SB.PCI0.MCHC.MHBR << 14 //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) + //DBR0 = \_SB.PCI0.MCHC.DMBR << 12 //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) + //EBR0 = \_SB.PCI0.MCHC.EPBR << 12 //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) + //PBR0 = \_SB.PCI0.MCHC.PXBR << 26 //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) + //PSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ Return(PDRS) } diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 9a1444365a..60051babd3 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -10,13 +10,13 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit + * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final assumption is that - * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a8c160a22d..b04a2f5940 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -15,7 +15,7 @@ int i945_silicon_revision(void) { - return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); + return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION); } static void i945m_detect_chipset(void) @@ -23,7 +23,7 @@ static void i945m_detect_chipset(void) u8 reg8; printk(BIOS_INFO, "\n"); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; switch (reg8) { case 1: printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); @@ -46,7 +46,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5; switch (reg8) { case 2: printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ @@ -63,7 +63,7 @@ static void i945m_detect_chipset(void) printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 2: printk(BIOS_DEBUG, "up to DDR2-667"); @@ -89,8 +89,8 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "\nIntel(R) "); - reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) - | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); + reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4) + | ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3); switch (reg8) { case 0: case 1: @@ -116,7 +116,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 0: case 2: @@ -144,10 +144,10 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) @@ -155,25 +155,25 @@ static void i945_setup_bars(void) /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; - pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4)); /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -245,7 +245,7 @@ static void i945_setup_egress_port(void) } /* Is internal graphics enabled? */ - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) MCHBAR32(MMARB1) |= (1 << 17); /* Assign Virtual Channel ID 1 to VC1 */ @@ -405,7 +405,7 @@ static void i945_setup_dmi_rcrb(void) #endif DMIBAR32(0x204) = reg32; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { printk(BIOS_DEBUG, "Internal graphics: enabled\n"); DMIBAR32(0x200) |= (1 << 21); } else { @@ -501,7 +501,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); - pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0); + pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0); pci_and_config32(p2peg, PEGCC, ~(1 << 8)); @@ -600,9 +600,9 @@ static void i945_setup_pci_express_x16(void) if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); + pci_write_config16(HOST_BRIDGE, GGC, reg16); - pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); + pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); } /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ @@ -698,7 +698,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "ok\n"); /* Finally: Disable the PCI config header */ - pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0); + pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0); } static void i945_setup_root_complex_topology(void) @@ -738,7 +738,7 @@ static void i945_setup_root_complex_topology(void) DMIBAR32(DMILE2A) = DEFAULT_EPBAR; /* PCI Express x16 Port Root Topology */ - if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); pci_or_config32(p2peg, LE1D, 1 << 0); } @@ -777,7 +777,7 @@ static void ich7_setup_pci_express(void) void i945_early_initialization(void) { /* Print some chipset specific information */ - switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { + switch (pci_read_config32(HOST_BRIDGE, 0)) { case 0x27708086: /* 82945G/GZ/GC/P/PL */ i945_detect_chipset(); break; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 929968e384..118d02c32c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -360,13 +360,12 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, set_vbe_mode_info_valid(&edid, pgfx); } else { - vga_misc_write(0x67); + vga_misc_write(0x67); - write32(mmiobase + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); - write32(mmiobase + VGACNTRL, 0x02c4008e - | VGA_PIPE_B_SELECT); + write32(mmiobase + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); + write32(mmiobase + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT); - vga_textmode_init(); + vga_textmode_init(); } return 0; } @@ -585,7 +584,6 @@ static u32 freq_to_blc_pwm_ctl(struct device *const dev, u16 pwm_freq) return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); } - static void panel_setup(u8 *mmiobase, struct device *const dev) { const struct northbridge_intel_i945_config *const conf = dev->chip_info; @@ -750,7 +748,6 @@ static struct device_operations gma_func0_ops = { .acpi_name = gma_acpi_name, }; - static struct device_operations gma_func1_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 20558b31cb..4b79b2b145 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -31,6 +31,7 @@ #define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x44 @@ -86,15 +87,14 @@ #define PEGCC 0x208 /* 32bit */ #define PEGSTS 0x214 /* 32bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ +#define IGD_DEV PCI_DEV(0, 2, 0) #define GMADR 0x18 #define GTTADR 0x1c #define BSM 0x5c #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ - /* * MCHBAR */ @@ -362,6 +362,8 @@ void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +int decode_pcie_bar(u32 *const base, u32 *const len); + /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 07aea98d17..c92e4662d6 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -36,20 +36,20 @@ static uintptr_t northbridge_get_tseg_base(void) { uintptr_t tom; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); + tom = pci_read_config32(IGD_DEV, BSM); else - tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; + tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24; /* subtract TSEG size */ - tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); + tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC)); return tom; } static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); return decode_tseg_size(esmramc); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 0e8ea7e77e..cfa527f4cc 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -11,32 +12,33 @@ #include #include "i945.h" -static int get_pcie_bar(u32 *base) +int decode_pcie_bar(u32 *const base, u32 *const len) { - struct device *dev; - u32 pciexbar_reg; - *base = 0; + *len = 0; - dev = pcidev_on_root(0, 0); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - return 256; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - return 128; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - return 64; + case 0: /* 256MB */ + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } return 0; @@ -97,7 +99,6 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem); - /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -162,13 +163,12 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(struct device *dev) { - u32 pcie_config_base; - int buses; + u32 pcie_config_base, pcie_config_len; pci_dev_read_resources(dev); - buses = get_pcie_bar(&pcie_config_base); - if (buses) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { + const int buses = pcie_config_len / MiB; struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cfe4d8f1c8..a1a9a9c0b6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -137,7 +137,7 @@ static int sdram_capabilities_max_supported_memory_frequency(void) return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY; #endif - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 &= (7 << 0); switch (reg32) { @@ -161,7 +161,7 @@ static int sdram_capabilities_interleave(void) { u32 reg32; - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 >>= 25; reg32 &= 1; @@ -177,7 +177,7 @@ static int sdram_capabilities_dual_channel(void) { u32 reg32; - reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */ + reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ reg32 >>= 24; reg32 &= 1; @@ -188,7 +188,7 @@ static int sdram_capabilities_enhanced_addressing_xor(void) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ + reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ reg8 &= (1 << 7); return (!reg8); @@ -203,7 +203,7 @@ static int sdram_capabilities_core_frequencies(void) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */ + reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ reg8 &= (1 << 3) | (1 << 2) | (1 << 1); reg8 >>= 1; @@ -318,7 +318,6 @@ static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved printk(BIOS_DEBUG, "only Single Channel Operation.\n"); } - for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i), bytes_read; struct dimm_attr_ddr2_st dimm_info; @@ -432,7 +431,6 @@ static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved i, sysinfo->banksize[(i * 2) + 1] * 32); } - sysinfo->rows[i] = dimm_info.row_bits; sysinfo->cols[i] = dimm_info.col_bits; sysinfo->banks[i] = dimm_info.banks; @@ -1186,13 +1184,13 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); - pci_write_config8(PCI_DEV(0, 0, 0), TOLUD, tolud); + pci_write_config8(HOST_BRIDGE, TOLUD, tolud); printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0)); printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0)); - printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0, 0, 0), TOLUD)); + printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(HOST_BRIDGE, TOLUD)); - pci_write_config16(PCI_DEV(0, 0, 0), TOM, tom); + pci_write_config16(HOST_BRIDGE, TOM, tom); return 0; } @@ -1625,7 +1623,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) /* Gate graphics hardware for frequency change */ reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */ - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); /* Get graphics frequency capabilities */ reg8 = sdram_capabilities_core_frequencies(); @@ -1651,7 +1649,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) if (freq != CRCLK_400MHz) { /* What chipset are we? Force 166MHz for GMS */ - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; if (reg8 == 2) freq = CRCLK_166MHz; } @@ -1701,10 +1699,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) sysinfo->clkcfg_bit7 = 0; /* Graphics Core Render Clock */ - pci_update_config16(PCI_DEV(0, 2, 0), GCFC, ~((7 << 0) | (1 << 13)), freq); + pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq); /* Graphics Core Display Clock */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC); + reg8 = pci_read_config8(IGD_DEV, GCFC); reg8 &= ~((1 << 7) | (7 << 4)); if (voltage == VOLTAGE_1_05) { @@ -1714,19 +1712,19 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) reg8 |= CDCLK_320MHz; printk(BIOS_DEBUG, " Display: 320MHz\n"); } - pci_write_config8(PCI_DEV(0, 2, 0), GCFC, reg8); + pci_write_config8(IGD_DEV, GCFC, reg8); - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1); + reg8 = pci_read_config8(IGD_DEV, GCFC + 1); reg8 |= (1 << 3) | (1 << 1); - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); reg8 |= 0x0f; - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); /* Ungate core render and display clocks */ reg8 &= 0xf0; - pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); + pci_write_config8(IGD_DEV, GCFC + 1, reg8); } static void sdram_program_memory_frequency(struct sys_info *sysinfo) @@ -2185,7 +2183,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg16 |= (4 << 11); MCHBAR16(CPCTL) = reg16; +#if 0 + if ((MCHBAR32(ECO) & (1 << 16)) != 0) { +#else if (i945_silicon_revision() != 0) { +#endif switch (sysinfo->fsb_frequency) { case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; @@ -2260,9 +2262,9 @@ static void sdram_power_management(struct sys_info *sysinfo) MCHBAR32(FSBPMC4) |= (1 << 4); } - pci_or_config8(PCI_DEV(0, 0x0, 0), 0xfc, 1 << 4); + pci_or_config8(HOST_BRIDGE, 0xfc, 1 << 4); - pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2); + pci_or_config8(IGD_DEV, 0xc1, 1 << 2); if (integrated_graphics) { MCHBAR16(MIPMC4) = 0x04f8; @@ -2702,7 +2704,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) sdram_program_graphics_frequency(&sysinfo); else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + pci_write_config16(IGD_DEV, GCFC, 0x0534); /* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 7289e9219a..688dd5fd81 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -3,48 +3,48 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include #include "ironlake.h" -unsigned long acpi_fill_mcfg(unsigned long current) +static int decode_pcie_bar(u32 *const base, u32 *const len) { - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + *base = 0; + *len = 0; - pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50); + const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); - // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) - return current; + return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; + case 0: /* 256MB */ + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } - if (!pciexbar) + return 0; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + u32 length, pciexbar; + + if (!decode_pcie_bar(&pciexbar, &length)) return current; + const int max_buses = length / MiB; + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 6a59fb546d..d6a2cf8d2f 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -92,17 +91,16 @@ Device (MCHC) External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -114,31 +112,31 @@ Device (MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100 /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -150,31 +148,31 @@ Device (MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100 /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -305,20 +303,20 @@ Method (_CRS, 0, Serialized) // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - ShiftRight (Local0, 4, Local0) - Store (^MCHC.TUUD, Local1) + Local0 = ^MCHC.TLUD + Local0 >>= 4 + Local1 = ^MCHC.TUUD // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) - ShiftRight (Local0, 6, Local0) + Local0 = ^MCHC.TOM + Local0 >>= 6 } - ShiftLeft (Local0, 20, Local0) - Store (Local0, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) + Local0 <<= 20 + PMIN = Local0 + PLEN = PMAX - PMIN + 1 Return (MCRS) } diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5d54..89eb81339e 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@ #include #include +#include "ironlake.h" void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index c437b724a4..b2976bced5 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -17,7 +17,13 @@ struct northbridge_intel_ironlake_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + enum { + PANEL_PORT_LVDS = 0, + PANEL_PORT_DP_A = 1, /* Also known as eDP */ + PANEL_PORT_DP_C = 2, + PANEL_PORT_DP_D = 3, + } gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index e6e9ace211..fa89bd9e45 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -15,25 +15,6 @@ static void ironlake_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - /* No reset */ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); - /* halt timer */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); - /* halt timer */ - outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); @@ -44,13 +25,13 @@ static void ironlake_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); + pci_write_config8(QPI_SAD, QPD0F1_PAM(1), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(2), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(3), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(4), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(5), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(6), 0x33); printk(BIOS_DEBUG, " done.\n"); } @@ -62,7 +43,7 @@ static void early_cpu_init(void) /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); + pci_update_config32(QPI_NON_CORE, DESIRED_CORES, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; @@ -112,6 +93,7 @@ void ironlake_early_initialization(int chipset_type) } /* Setup all BARs required for early PCIe and raminit */ + ibexpeak_setup_bars(); ironlake_setup_bars(); s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && @@ -120,7 +102,7 @@ void ironlake_early_initialization(int chipset_type) elog_boot_notify(s3_resume); /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); early_cpu_init(); diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 92ee76ca4e..93653c9658 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -5,43 +5,11 @@ #define DEFAULT_HECIBAR ((u8 *)0xfed17000) - #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 #define IOMMU_BASE3 0xfed92000 #define IOMMU_BASE4 0xfed93000 -/* - * D0:F0 - */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ - -#define D0F0_CAPID0 0xe0 - -#define TSEG 0xac /* TSEG base */ - /* * D1:F0 PEG */ @@ -65,7 +33,6 @@ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) #define QUICKPATH_BUS 0xff @@ -76,17 +43,54 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define X60BAR 0x60 +#include "registers/host_bridge.h" -#define LAC 0x87 /* Legacy Access Control */ +/* + * Generic Non-Core Registers + */ +#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) + +#define MAX_RTIDS 0x60 +#define DESIRED_CORES 0x80 +#define MIRROR_PORT_CTL 0xd0 + +/* + * SAD - System Address Decoder + */ +#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) + +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ -#define SKPAD 0xdc /* Scratchpad Data */ +#define SAD_PCIEXBAR 0x50 +#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ +#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ + +/* + * QPI Link 0 + */ +#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) + +#define QPI_QPILCP 0x40 /* QPI Link Capability */ +#define QPI_QPILCL 0x48 /* QPI Link Control */ +#define QPI_QPILS 0x50 /* QPI Link Status */ +#define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ + +/* + * QPI Physical Layer 0 + */ +#define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) + +#define QPI_PLL_STATUS 0x50 +#define QPI_PLL_RATIO 0x54 +#define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ +#define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ +#define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ +#define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ +#define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ +#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ +#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -127,9 +131,6 @@ #define EPVC1RCTL 0x020 /* 32bit */ #define EPVC1RSTS 0x026 /* 16bit */ -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - #define EPESD 0x044 /* 32bit */ #define EPLE1D 0x050 /* 32bit */ @@ -137,8 +138,6 @@ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ -#define PORTARB 0x100 /* 256bit */ - /* * DMIBAR */ @@ -156,10 +155,22 @@ #define DMIVC0RCAP 0x010 /* 32bit */ #define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -170,12 +181,12 @@ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ #define DMICC 0x208 /* 32bit */ -#define DMIDRCCFG 0xeb4 /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ #ifndef __ASSEMBLER__ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 406b9a90fe..78fbae85fe 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -7,20 +7,14 @@ #include #include #include -#include -#include -#include "ironlake.h" +#include -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom; -} +#include "ironlake.h" static uintptr_t northbridge_get_tseg_base(void) { - return smm_region_start(); + /* Base of TSEG is top of usable DRAM */ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); } static size_t northbridge_get_tseg_size(void) @@ -30,7 +24,7 @@ static size_t northbridge_get_tseg_size(void) void *cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return (void *)northbridge_get_tseg_base(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index c1a2840bda..2cffa29abf 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -93,28 +92,30 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(struct device *dev) { - uint32_t tseg_base; - uint64_t TOUUD; + uint32_t tseg_base, tseg_end; + uint64_t touud; uint16_t reg16; + int index = 3; pci_dev_read_resources(dev); mmconf_resource(dev, 0x50); tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); - TOUUD = pci_read_config16(pcidev_on_root(0, 0), - D0F0_TOUUD); + tseg_end = tseg_base + CONFIG_SMM_TSEG_SIZE; + touud = pci_read_config16(pcidev_on_root(0, 0), + TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); - printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD); + printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); /* Report the memory regions */ - ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); + ram_resource(dev, index++, 0, 640); + ram_resource(dev, index++, 768, ((tseg_base >> 10) - 768)); - mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); + mmio_resource(dev, index++, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); - reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; /* Igd memory */ @@ -128,20 +129,25 @@ static void mc_read_resources(struct device *dev) uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; igd_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); + pci_read_config32(pcidev_on_root(0, 0), IGD_BASE); gtt_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); - mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); - mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); + pci_read_config32(pcidev_on_root(0, 0), GTT_BASE); + if (gtt_base > tseg_end) { + /* Reserve the gap. MMIO doesn't work in this range. Keep + it uncacheable, though, for easier MTRR allocation. */ + mmio_resource(dev, index++, tseg_end >> 10, (gtt_base - tseg_end) >> 10); + } + mmio_resource(dev, index++, gtt_base >> 10, uma_size_gtt << 10); + mmio_resource(dev, index++, igd_base >> 10, uma_size_igd << 10); - if (TOUUD > 4096) - ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); + if (touud > 4096) + ram_resource(dev, index++, (4096 << 10), ((touud - 4096) << 10)); /* This memory is not DMA-capable. */ - if (TOUUD >= 8192 - 64) - bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); + if (touud >= 8192 - 64) + bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 0x004000000 >> 10); - add_fixed_resources(dev, 10); + add_fixed_resources(dev, index); } static void northbridge_init(struct device *dev) @@ -149,20 +155,20 @@ static void northbridge_init(struct device *dev) u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; reg32 = DMIBAR32(0x1f8); reg32 |= (1 << 16); DMIBAR32(0x1f8) = reg32; - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree before PCI enumeration */ @@ -183,7 +189,7 @@ static void ironlake_init(void *const chip_info) } const struct device *const d0f0 = pcidev_on_root(0, 0); if (d0f0) - pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + pci_update_config32(d0f0, DEVEN, deven_mask, 0); } diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f1f8aa5e9a..05323f1ca4 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -61,7 +61,7 @@ typedef struct { u8 largest; } timing_bounds_t[2][2][2][9]; -#define MRC_CACHE_VERSION 1 +#define MRC_CACHE_VERSION 3 struct ram_training { /* [TM][CHANNEL][SLOT][RANK][LANE] */ @@ -192,8 +192,6 @@ struct raminfo { unsigned int interleaved_part_mb; unsigned int non_interleaved_part_mb; - u32 heci_bar; - u64 heci_uma_addr; unsigned int memory_reserved_for_heci_mb; struct ram_training training; @@ -1337,9 +1335,9 @@ static void program_board_delay(struct raminfo *info) MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } @@ -1362,13 +1360,11 @@ static unsigned int get_mmio_size(void) return cfg->pci_mmio_size; } -#define BETTER_MEMORY_MAP 0 - static void program_total_memory_map(struct raminfo *info) { - unsigned int TOM, TOLUD, TOUUD; + unsigned int tom, tolud, touud; unsigned int quickpath_reserved; - unsigned int REMAPbase; + unsigned int remap_base; unsigned int uma_base_igd; unsigned int uma_base_gtt; unsigned int mmio_size; @@ -1382,7 +1378,7 @@ static void program_total_memory_map(struct raminfo *info) memset(memory_map, 0, sizeof(memory_map)); if (info->uma_enabled) { - u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); + u16 t = pci_read_config16(NORTHBRIDGE, GGC); gav(t); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; @@ -1398,23 +1394,23 @@ static void program_total_memory_map(struct raminfo *info) mmio_size = get_mmio_size(); - TOM = info->total_memory_mb; - if (TOM == 4096) - TOM = 4032; - TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) - , TOUUD), 64); + tom = info->total_memory_mb; + if (tom == 4096) + tom = 4032; + touud = ALIGN_DOWN(tom - info->memory_reserved_for_heci_mb, 64); + tolud = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + , touud), 64); memory_remap = 0; - if (TOUUD - TOLUD > 64) { + if (touud - tolud > 64) { memory_remap = 1; - REMAPbase = MAX(4096, TOUUD); - TOUUD = TOUUD - TOLUD + 4096; + remap_base = MAX(4096, touud); + touud = touud - tolud + 4096; } - if (TOUUD > 4096) - memory_map[2] = TOUUD | 1; + if (touud > 4096) + memory_map[2] = touud | 1; quickpath_reserved = 0; - u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); + u32 t = pci_read_config32(QPI_SAD, 0x68); gav(t); @@ -1426,26 +1422,26 @@ static void program_total_memory_map(struct raminfo *info) } if (memory_remap) - TOUUD -= quickpath_reserved; + touud -= quickpath_reserved; - uma_base_igd = TOLUD - uma_size_igd; + uma_base_igd = tolud - uma_size_igd; uma_base_gtt = uma_base_igd - uma_size_gtt; tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20); if (!memory_remap) tseg_base -= quickpath_reserved; tseg_base = ALIGN_DOWN(tseg_base, 8); - pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4); - pci_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6); + pci_write_config16(NORTHBRIDGE, TOLUD, tolud << 4); + pci_write_config16(NORTHBRIDGE, TOM, tom >> 6); if (memory_remap) { - pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6); - pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6); + pci_write_config16(NORTHBRIDGE, REMAPBASE, remap_base >> 6); + pci_write_config16(NORTHBRIDGE, REMAPLIMIT, (touud - 64) >> 6); } - pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD); + pci_write_config16(NORTHBRIDGE, TOUUD, touud); if (info->uma_enabled) { - pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); - pci_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); + pci_write_config32(NORTHBRIDGE, IGD_BASE, uma_base_igd << 20); + pci_write_config32(NORTHBRIDGE, GTT_BASE, uma_base_gtt << 20); } pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); @@ -1454,10 +1450,10 @@ static void program_total_memory_map(struct raminfo *info) memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } @@ -1471,9 +1467,6 @@ static void collect_system_info(struct raminfo *info) while (!(read8((u8 *)0xfed40000) & (1 << 7))) ; - if (!info->heci_bar) - gav(info->heci_bar = - pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8); if (!info->memory_reserved_for_heci_mb) { /* Wait for ME to be ready */ intel_early_me_init(); @@ -1482,7 +1475,7 @@ static void collect_system_info(struct raminfo *info) for (i = 0; i < 3; i++) gav(capid0[i] = - pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); + pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2))); gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); info->max_supported_clock_speed_index = (~capid0[1] & 7); @@ -1490,7 +1483,7 @@ static void collect_system_info(struct raminfo *info) info->uma_enabled = 0; else gav(info->uma_enabled = - pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8); + pci_read_config8(NORTHBRIDGE, DEVEN) & 8); /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ info->silicon_revision = 0; @@ -1620,11 +1613,9 @@ static void save_timings(struct raminfo *info) static const struct ram_training *get_cached_training(void) { - struct region_device rdev; - if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - &rdev)) - return 0; - return (void *)rdev_mmap_full(&rdev); + return mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + NULL); } /* FIXME: add timeout. */ @@ -1632,8 +1623,8 @@ static void wait_heci_ready(void) { while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c ; - write32((DEFAULT_HECIBAR + 0x4), - (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); + + write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); } /* FIXME: add timeout. */ @@ -1647,12 +1638,10 @@ static void wait_heci_cb_avail(int len) while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; - do + do { csr.raw = read32(DEFAULT_HECIBAR + 0x4); - while (len > - csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - - csr.csr.buffer_read_ptr)) - ; + } while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - + csr.csr.buffer_read_ptr)); } static void send_heci_packet(struct mei_header *head, u32 *payload) @@ -1671,8 +1660,7 @@ static void send_heci_packet(struct mei_header *head, u32 *payload) write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4); } -static void -send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) +static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) { struct mei_header head; int maxlen; @@ -1698,9 +1686,7 @@ send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) } /* FIXME: Add timeout. */ -static int -recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet, - u32 *packet_size) +static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size) { union { struct mei_csr csr; @@ -1711,27 +1697,23 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet, write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); do { csr.raw = read32(DEFAULT_HECIBAR + 0xc); - } - while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr) - ; + } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); + *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); if (!head->length) { - write32(DEFAULT_HECIBAR + 0x4, - read32(DEFAULT_HECIBAR + 0x4) | 2); + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); *packet_size = 0; return 0; } - if (head->length + 4 > 4 * csr.csr.buffer_depth - || head->length > *packet_size) { + if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { *packet_size = 0; return -1; } - do + do { csr.raw = read32(DEFAULT_HECIBAR + 0xc); - while (((head->length + 3) >> 2) > - (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)) - ; + } while (((head->length + 3) >> 2) > + (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)); for (i = 0; i < (head->length + 3) >> 2; i++) packet[i++] = read32(DEFAULT_HECIBAR + 0x8); @@ -1743,8 +1725,7 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet, } /* FIXME: Add timeout. */ -static int -recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size) +static int recv_heci_message(u32 *message, u32 *message_size) { struct mei_header head; int current_position; @@ -1754,7 +1735,7 @@ recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size) u32 current_size; current_size = *message_size - current_position; if (recv_heci_packet - (info, &head, message + (current_position >> 2), + (&head, message + (current_position >> 2), ¤t_size) == -1) break; if (!current_size) @@ -1772,9 +1753,9 @@ recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size) return -1; } -static void send_heci_uma_message(struct raminfo *info) +static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) { - struct uma_reply { + volatile struct uma_reply { u8 group_id; u8 command; u8 reserved; @@ -1782,6 +1763,10 @@ static void send_heci_uma_message(struct raminfo *info) u8 field2; u8 unk3[0x48 - 4 - 1]; } __packed reply; + + /* FIXME: recv_heci_message() does not always initialize 'reply' */ + reply.command = 0; + struct uma_message { u8 group_id; u8 cmd; @@ -1789,18 +1774,24 @@ static void send_heci_uma_message(struct raminfo *info) u8 result; u32 c2; u64 heci_uma_addr; - u32 memory_reserved_for_heci_mb; + u32 heci_uma_size; u16 c3; } __packed msg = { - 0, MKHI_SET_UMA, 0, 0, - 0x82, - info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; + .group_id = 0, + .cmd = MKHI_SET_UMA, + .reserved = 0, + .result = 0, + .c2 = 0x82, + .heci_uma_addr = heci_uma_addr, + .heci_uma_size = heci_uma_size, + .c3 = 0, + }; u32 reply_size; - send_heci_message((u8 *) & msg, sizeof(msg), 0, 7); + send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); reply_size = sizeof(reply); - if (recv_heci_message(info, (u32 *) & reply, &reply_size) == -1) + if (recv_heci_message((u32 *) &reply, &reply_size) == -1) return; if (reply.command != (MKHI_SET_UMA | (1 << 7))) @@ -1809,54 +1800,39 @@ static void send_heci_uma_message(struct raminfo *info) static void setup_heci_uma(struct raminfo *info) { - u32 reg44; - - reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020 - info->memory_reserved_for_heci_mb = 0; - info->heci_uma_addr = 0; - if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20))) + if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20)) return; - info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0; - info->memory_reserved_for_heci_mb = reg44 & 0x3f; - info->heci_uma_addr = + const u64 heci_uma_addr = ((u64) - ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) - + ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; pci_read_config32(NORTHBRIDGE, DMIBAR); if (info->memory_reserved_for_heci_mb) { - write32(DEFAULT_DMIBAR + 0x14, - read32(DEFAULT_DMIBAR + 0x14) & ~0x80); - write32(DEFAULT_RCBA + 0x14, - read32(DEFAULT_RCBA + 0x14) & ~0x80); - write32(DEFAULT_DMIBAR + 0x20, - read32(DEFAULT_DMIBAR + 0x20) & ~0x80); - write32(DEFAULT_RCBA + 0x20, - read32(DEFAULT_RCBA + 0x20) & ~0x80); - write32(DEFAULT_DMIBAR + 0x2c, - read32(DEFAULT_DMIBAR + 0x2c) & ~0x80); - write32(DEFAULT_RCBA + 0x30, - read32(DEFAULT_RCBA + 0x30) & ~0x80); - write32(DEFAULT_DMIBAR + 0x38, - read32(DEFAULT_DMIBAR + 0x38) & ~0x80); - write32(DEFAULT_RCBA + 0x40, - read32(DEFAULT_RCBA + 0x40) & ~0x80); + DMIBAR32(DMIVC0RCTL) &= ~0x80; + write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80); + DMIBAR32(DMIVC1RCTL) &= ~0x80; + write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80); + DMIBAR32(DMIVCPRCTL) &= ~0x80; + write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80); + DMIBAR32(DMIVCMRCTL) &= ~0x80; + write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80); + + write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK + DMIBAR32(DMIVCMRCTL) = 0x87000080; // OK - write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK - write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK while ((read16(DEFAULT_RCBA + 0x46) & 2) && - read16(DEFAULT_DMIBAR + 0x3e) & 2) + DMIBAR16(DMIVCMRSTS) & VCMNP) ; } MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb; - send_heci_uma_message(info); + send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb); pci_write_config32(HECIDEV, 0x10, 0x0); pci_write_config8(HECIDEV, 0x4, 0x0); - } static int have_match_ranks(struct raminfo *info, int channel, int ranks) @@ -1965,7 +1941,7 @@ static void flush_cache(u32 start, u32 size) end = start + (ALIGN_DOWN(size + 4096, 4096)); for (addr = start; addr < end; addr += 64) - clflush((void *)addr); + clflush((void *)(uintptr_t)addr); } static void clear_errors(void) @@ -1980,7 +1956,7 @@ static void write_testing(struct raminfo *info, int totalrank, int flip) u32 offset; u8 *base; - base = (u8 *)(totalrank << 28); + base = (u8 *)(uintptr_t)(totalrank << 28); for (offset = 0; offset < 9 * 480; offset += 2) { write32(base + offset * 8, get_etalon2(flip, offset)); write32(base + offset * 8 + 4, get_etalon2(flip, offset)); @@ -3628,12 +3604,12 @@ static void restore_274265(struct raminfo *info) static void dmi_setup(void) { - gav(read8(DEFAULT_DMIBAR + 0x254)); - write8(DEFAULT_DMIBAR + 0x254, 0x1); - write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2); + gav(DMIBAR8(0x254)); + DMIBAR8(0x254) = 0x1; + DMIBAR16(0x1b8) = 0x18f2; MCHBAR16_AND_OR(0x48, 0, 0x2); - write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000); + DMIBAR32(0xd68) |= 0x08000000; outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, DEFAULT_GPIOBASE | 0x38); @@ -3667,10 +3643,10 @@ void chipset_init(const int s3resume) ggc = 0xb00 | ((gfxsize + 5) << 4); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); + pci_write_config16(NORTHBRIDGE, GGC, ggc | 2); u16 deven; - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 + deven = pci_read_config16(NORTHBRIDGE, DEVEN); // = 0x3 if (deven & 8) { MCHBAR8(0x2c30) = 0x20; @@ -3678,8 +3654,8 @@ void chipset_init(const int s3resume) MCHBAR16_OR(0x2c30, 0x200); MCHBAR16(0x2c32) = 0x434; MCHBAR32_AND_OR(0x2c44, 0, 0x1053687); - pci_read_config8(GMA, 0x62); // = 0x2 - pci_write_config8(GMA, 0x62, 0x2); + pci_read_config8(GMA, MSAC); // = 0x2 + pci_write_config8(GMA, MSAC, 0x2); read8(DEFAULT_RCBA + 0x2318); write8(DEFAULT_RCBA + 0x2318, 0x47); read8(DEFAULT_RCBA + 0x2320); @@ -3688,7 +3664,7 @@ void chipset_init(const int s3resume) MCHBAR32_AND_OR(0x30, 0, 0x40); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); + pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); write32(DEFAULT_RCBA + 0x3428, 0x1d); } @@ -3706,7 +3682,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); + deven = pci_read_config16(NORTHBRIDGE, DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -3727,7 +3703,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) info.training.reg_178 = 0; info.training.reg_10b = 0; - info.heci_bar = 0; info.memory_reserved_for_heci_mb = 0; /* before SPD */ @@ -3834,7 +3809,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) gav(0x55); - gav(pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4)); + gav(pci_read_config32(NORTHBRIDGE, CAPID0 + 4)); } /* after SPD */ @@ -3880,8 +3855,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR32_OR(0x1890, 0x2000000); MCHBAR32_OR(0x18b4, 0x8000); - gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x50)); // !!!! - pci_write_config8(PCI_DEV(0xff, 2, 1), 0x54, 0x12); + gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!! + pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12); gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; @@ -3891,8 +3866,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) gav(MCHBAR8(0x2ca8)); // !!!! MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); - pci_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0); + pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!! + pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0); gav(MCHBAR32(0x1c04)); // !!!! gav(MCHBAR32(0x1804)); // !!!! @@ -3902,16 +3877,16 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR32(0x18d8) = 0x120000; MCHBAR32(0x18dc) = 0x30a484a; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x0); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x9444a); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); MCHBAR32(0x18d8) = 0x40000; MCHBAR32(0x18dc) = 0xb000000; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x60000); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x0); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x0); MCHBAR32(0x18d8) = 0x180000; MCHBAR32(0x18dc) = 0xc0000142; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xe0, 0x20000); - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xf4, 0x142); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x20000); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x142); MCHBAR32(0x18d8) = 0x1e0000; gav(MCHBAR32(0x18dc)); // !!!! @@ -3923,7 +3898,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) } MCHBAR32(0x188c) = 0x20bc09; - pci_write_config32(PCI_DEV(0xff, 2, 1), 0xd0, 0x40b0c09); + pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; MCHBAR32_OR(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! @@ -3933,8 +3908,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR32(0x18b8) = 0xe00; gav(MCHBAR32(0x182c)); // !!!! MCHBAR32(0x182c) = 0x10202; - gav(pci_read_config32(PCI_DEV(0xff, 2, 1), 0x94)); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 1), 0x94, 0x10202); + gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!! + pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202); MCHBAR32_AND(0x1a1c, 0x8fffffff); MCHBAR32_OR(0x1a70, 0x100000); @@ -3948,13 +3923,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! - pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); + pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! + pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! + pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! + pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!! + pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180); gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!! MCHBAR32(0x1af0) = 0x1f020003; @@ -4223,7 +4198,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! - pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); + pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c00); // !!!! @@ -4625,9 +4600,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap) } u32 reg1c; pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK + reg1c = EPBAR32(EPVC1RCAP); // = 0x8001 // OK pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK - write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK + EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 MCHBAR8_OR(0x1210, 2); diff --git a/src/northbridge/intel/ironlake/registers/host_bridge.h b/src/northbridge/intel/ironlake/registers/host_bridge.h new file mode 100644 index 0000000000..0322a515cc --- /dev/null +++ b/src/northbridge/intel/ironlake/registers/host_bridge.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ +#define __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define GGC 0x52 +#define DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define DMIBAR 0x68 + +#define LAC 0x87 /* Legacy Access Control */ + +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define TOM 0xa0 +#define TOUUD 0xa2 +#define IGD_BASE 0xa4 +#define GTT_BASE 0xa8 +#define TSEG 0xac /* TSEG base */ +#define TOLUD 0xb0 + +#define SKPD 0xdc /* Scratchpad Data */ + +#define CAPID0 0xe0 + +#endif /* __IRONLAKE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/ironlake/smi.c b/src/northbridge/intel/ironlake/smi.c index 9ffcb995a3..0604d13155 100644 --- a/src/northbridge/intel/ironlake/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -11,5 +11,5 @@ void northbridge_write_smram(u8 smram) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_write_config8(QPI_SAD, QPD0F1_SMRAM, smram); } diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 575814c2d5..9d85717d63 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -2,20 +2,19 @@ #include #include +#include #include #include #include unsigned long acpi_fill_mcfg(unsigned long current) { - u32 length = 0; - u32 pciexbar = 0; - int max_buses; + u32 length, pciexbar; - if (!decode_pciebar(&pciexbar, &length)) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - max_buses = length >> 20; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 3579a260b9..9515c317a9 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../iomap.h" +#include "../memmap.h" #include /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e46bd7c7c2..e0ed0f0500 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -234,9 +235,9 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; /* Find base addresses */ - mmio_res = find_resource(dev, 0x10); - gtt_res = find_resource(dev, 0x1c); - pio_res = find_resource(dev, 0x14); + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_3); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_1); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h new file mode 100644 index 0000000000..506efcfbdd --- /dev/null +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __PINEVIEW_HOSTBRIDGE_REGS_H__ +#define __PINEVIEW_HOSTBRIDGE_REGS_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) +#endif /* BOARD_DEVEN */ + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEG 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +#endif /* __PINEVIEW_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index ad89aef04d..bebe3a5b69 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -3,6 +3,7 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include #include @@ -14,15 +15,11 @@ #include #include -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; - const pci_devfn_t dev = HOST_BRIDGE; - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; + const struct { u16 num_buses; u32 addr_mask; @@ -33,7 +30,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) {0, 0}, }; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR); /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) { @@ -41,9 +38,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) return 0; } - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; + const u32 index = (pciexbar_reg >> 1) & 3; + const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask; + const int max_buses = busmask[index].num_buses; if (!pciexbar) { printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); @@ -51,7 +48,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) } *base = pciexbar; - *len = max_buses << 20; + *len = max_buses * MiB; return 1; } @@ -87,11 +84,11 @@ static u32 decode_tseg_size(const u32 esmramc) switch ((esmramc >> 1) & 3) { case 0: - return 1 << 20; + return 1 * MiB; case 1: - return 2 << 20; + return 2 * MiB; case 2: - return 8 << 20; + return 8 * MiB; case 3: default: die("Bad TSEG setting.\n"); @@ -109,7 +106,6 @@ static uintptr_t northbridge_get_tseg_base(void) return pci_read_config32(HOST_BRIDGE, TSEG); } - /* * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/memmap.h similarity index 73% rename from src/northbridge/intel/pineview/iomap.h rename to src/northbridge/intel/pineview/memmap.h index 4560da0eda..50ede0b717 100644 --- a/src/northbridge/intel/pineview/iomap.h +++ b/src/northbridge/intel/pineview/memmap.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef PINEVIEW_IOMAP_H -#define PINEVIEW_IOMAP_H +#ifndef PINEVIEW_MEMMAP_H +#define PINEVIEW_MEMMAP_H #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_PMIOBAR 0x00000400 -#endif /* PINEVIEW_IOMAP_H */ +#endif /* PINEVIEW_MEMMAP_H */ diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 856eab3301..a04b62b5d5 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -18,7 +18,7 @@ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ -static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_base_k = 0xa0000 / KiB; static void add_fixed_resources(struct device *dev, int index) { @@ -33,8 +33,8 @@ static void add_fixed_resources(struct device *dev, int index) | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); } static void mch_domain_read_resources(struct device *dev) @@ -114,7 +114,7 @@ static void mch_domain_read_resources(struct device *dev) (touud - top32memk) >> 10); } - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", pcie_config_base, pcie_config_size); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 7c41b4c24a..cafda8ace6 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -3,71 +3,17 @@ #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H #define NORTHBRIDGE_INTEL_PINEVIEW_H -#include +#include #include #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 #define BOOT_PATH_RESUME 2 -#define SYSINFO_DIMM_NOT_POPULATED 0x00 -#define SYSINFO_DIMM_X16SS 0x01 -#define SYSINFO_DIMM_X16DS 0x02 -#define SYSINFO_DIMM_X8DS 0x05 -#define SYSINFO_DIMM_X8DDS 0x06 - /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78 - -#define GGC 0x52 /* GMCH Graphics Control */ - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D0F0 (1 << 0) -#define DEVEN_D1F0 (1 << 1) -#define DEVEN_D2F0 (1 << 3) -#define DEVEN_D2F1 (1 << 4) - -#ifndef BOARD_DEVEN -#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) -#endif /* BOARD_DEVEN */ - -#define PAM0 0x90 -#define PAM1 0x91 -#define PAM2 0x92 -#define PAM3 0x93 -#define PAM4 0x94 -#define PAM5 0x95 -#define PAM6 0x96 - -#define LAC 0x97 /* Legacy Access Control */ -#define REMAPBASE 0x98 -#define REMAPLIMIT 0x9a -#define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAMC 0x9e /* Extended System Management RAM Control */ - -#define TOM 0xa0 -#define TOUUD 0xa2 -#define GBSM 0xa4 -#define BGSM 0xa8 -#define TSEG 0xac -#define TOLUD 0xb0 /* Top of Low Used Memory */ -#define ERRSTS 0xc8 -#define ERRCMD 0xca -#define SMICMD 0xcc -#define SCICMD 0xce -#define CGDIS 0xd8 -#define SKPAD 0xdc /* Scratchpad Data */ -#define CAPID0 0xe0 -#define DEV0T 0xf0 -#define MSLCK 0xf4 -#define MID0 0xf8 -#define DEBUP0 0xfc +#include "hostbridge_regs.h" /* Device 0:1.0 PCI configuration space (PCI Express) */ @@ -107,133 +53,22 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) /* * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) - -enum fsb_clk { - FSB_CLOCK_667MHz = 0, - FSB_CLOCK_800MHz = 1, -}; - -enum mem_clk { - MEM_CLOCK_667MHz = 0, - MEM_CLOCK_800MHz = 1, -}; - -enum ddr { - DDR2 = 2, - DDR3 = 3, -}; - -enum chip_width { /* as in DDR3 spd */ - CHIP_WIDTH_x4 = 0, - CHIP_WIDTH_x8 = 1, - CHIP_WIDTH_x16 = 2, - CHIP_WIDTH_x32 = 3, -}; - -enum chip_cap { /* as in DDR3 spd */ - CHIP_CAP_256M = 0, - CHIP_CAP_512M = 1, - CHIP_CAP_1G = 2, - CHIP_CAP_2G = 3, - CHIP_CAP_4G = 4, - CHIP_CAP_8G = 5, - CHIP_CAP_16G = 6, -}; - -struct timings { - unsigned int CAS; - enum fsb_clk fsb_clock; - enum mem_clk mem_clock; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tWR; - unsigned int tRFC; - unsigned int tWTR; - unsigned int tRRD; - unsigned int tRTP; -}; - -struct dimminfo { - unsigned int card_type; /* 0x0: unpopulated, - 0xa - 0xf: raw card type A - F */ - u8 type; - enum chip_width width; - enum chip_cap chip_capacity; - unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ - unsigned int sides; - unsigned int banks; - unsigned int ranks; - unsigned int rows; - unsigned int cols; - unsigned int cas_latencies; - unsigned int tAAmin; - unsigned int tCKmin; - unsigned int tWR; - unsigned int tRP; - unsigned int tRCD; - unsigned int tRAS; - unsigned int rank_capacity_mb; /* per rank in Megabytes */ - u8 spd_data[256]; -}; - -struct pllparam { - u8 kcoarse[2][72]; - u8 pi[2][72]; - u8 dben[2][72]; - u8 dbsel[2][72]; - u8 clkdelay[2][72]; -}; - -struct sysinfo { - u8 maxpi; - u8 pioffset; - u8 pi[8]; - u16 coarsectrl; - u16 coarsedelay; - u16 mediumphase; - u16 readptrdelay; - - int txt_enabled; - int cores; - int boot_path; - int max_ddr2_mhz; - int max_ddr3_mt; - int max_fsb_mhz; - int max_render_mhz; - int enable_igd; - int enable_peg; - u16 ggc; - - int dimm_config[2]; - int dimms_per_ch; - int spd_type; - int channel_capacity[2]; - struct timings selected_timings; - struct dimminfo dimms[4]; - u8 spd_map[4]; - - u8 nodll; - u8 async; - u8 dt0mode; - u8 mvco4x; /* 0 (8x) or 1 (4x) */ -}; +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) void pineview_early_init(void); u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); -u8 decode_pciebar(u32 *const base, u32 *const len); +int decode_pcie_bar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ void get_mb_spd_addrmap(u8 *spd_addr_map); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be723..2248d03c89 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -941,7 +941,6 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); } - static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) { u8 rank, dq, reg8, j; diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h index 22e65cd648..4a0547b305 100644 --- a/src/northbridge/intel/pineview/raminit.h +++ b/src/northbridge/intel/pineview/raminit.h @@ -3,6 +3,123 @@ #ifndef PINEVIEW_RAMINIT_H #define PINEVIEW_RAMINIT_H +#define SYSINFO_DIMM_NOT_POPULATED 0x00 +#define SYSINFO_DIMM_X16SS 0x01 +#define SYSINFO_DIMM_X16DS 0x02 +#define SYSINFO_DIMM_X8DS 0x05 +#define SYSINFO_DIMM_X8DDS 0x06 + +enum fsb_clk { + FSB_CLOCK_667MHz = 0, + FSB_CLOCK_800MHz = 1, +}; + +enum mem_clk { + MEM_CLOCK_667MHz = 0, + MEM_CLOCK_800MHz = 1, +}; + +enum ddr { + DDR2 = 2, + DDR3 = 3, +}; + +enum chip_width { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +}; + +enum chip_cap { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +}; + +struct timings { + unsigned int CAS; + enum fsb_clk fsb_clock; + enum mem_clk mem_clock; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tWR; + unsigned int tRFC; + unsigned int tWTR; + unsigned int tRRD; + unsigned int tRTP; +}; + +struct dimminfo { + unsigned int card_type; /* 0x0: unpopulated, + 0xa - 0xf: raw card type A - F */ + u8 type; + enum chip_width width; + enum chip_cap chip_capacity; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + unsigned int sides; + unsigned int banks; + unsigned int ranks; + unsigned int rows; + unsigned int cols; + unsigned int cas_latencies; + unsigned int tAAmin; + unsigned int tCKmin; + unsigned int tWR; + unsigned int tRP; + unsigned int tRCD; + unsigned int tRAS; + unsigned int rank_capacity_mb; /* per rank in Megabytes */ + u8 spd_data[256]; +}; + +struct pllparam { + u8 kcoarse[2][72]; + u8 pi[2][72]; + u8 dben[2][72]; + u8 dbsel[2][72]; + u8 clkdelay[2][72]; +}; + +struct sysinfo { + u8 maxpi; + u8 pioffset; + u8 pi[8]; + u16 coarsectrl; + u16 coarsedelay; + u16 mediumphase; + u16 readptrdelay; + + int txt_enabled; + int cores; + int boot_path; + int max_ddr2_mhz; + int max_ddr3_mt; + int max_fsb_mhz; + int max_render_mhz; + int enable_igd; + int enable_peg; + u16 ggc; + + int dimm_config[2]; + int dimms_per_ch; + int spd_type; + int channel_capacity[2]; + struct timings selected_timings; + struct dimminfo dimms[4]; + u8 spd_map[4]; + + u8 nodll; + u8 async; + u8 dt0mode; + u8 mvco4x; /* 0 (8x) or 1 (4x) */ +}; + void sdram_initialize(int boot_path, const u8 *sdram_addresses); #endif /* PINEVIEW_RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 2cfb9ee8c3..7ff0fae362 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -11,48 +11,19 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; + u32 length, pciexbar; - struct device *const dev = pcidev_on_root(0, 0); - - if (!dev) + if (!decode_pcie_bar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & (0xffffffffULL << 28); - max_buses = 256; - break; - case 1: /* 128M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 27); - max_buses = 128; - break; - case 2: /* 64M */ - pciexbar = pciexbar_reg & (0xffffffffULL << 26); - max_buses = 64; - break; - default: /* RSVD */ - return current; - } - - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, - max_buses - 1); + max_buses - 1); return current; } - static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); @@ -73,37 +44,41 @@ static unsigned long acpi_fill_dmar(unsigned long current) { const struct device *const igfx = pcidev_on_root(2, 0); + /* First, add DRHD entries */ if (igfx && igfx->enabled) { - unsigned long tmp; + const unsigned long tmp = current; - tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); + } + + { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* Then, add RMRR entries after all DRHD entries */ + if (igfx && igfx->enabled) { + const unsigned long tmp = current; - tmp = current; current += acpi_create_igfx_rmrr(current); if (current != tmp) { current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_rmrr_fixup(tmp, current); } } - const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); - - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); - - acpi_dmar_drhd_fixup(tmp, current); - return current; } diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 0f70f8c9d5..977d7a7a8d 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -151,12 +151,12 @@ Device (MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ CTCS = CTCD @@ -187,12 +187,12 @@ Device (MCHC) If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ PL1V = CTDN diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 37ef02531e..dad61f9ee8 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to to true. That way, all + * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 8f388ec188..824af3e11d 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -4,6 +4,8 @@ #define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H #include +#include +#include /* * Digital Port Hotplug Enable: @@ -17,7 +19,13 @@ struct northbridge_intel_sandybridge_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + enum { + PANEL_PORT_LVDS = 0, + PANEL_PORT_DP_A = 1, /* Also known as eDP */ + PANEL_PORT_DP_C = 2, + PANEL_PORT_DP_D = 3, + } gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index b27911d8dc..5cd49cc9a6 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -2,6 +2,7 @@ #include #include +#include #include "sandybridge.h" enum platform_type get_platform_type(void) diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 287c4414d2..bcf3e4ce4d 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -23,7 +23,6 @@ void early_init_dmi(void) DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; } - for (i = 0; i < 2; i++) { DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; } @@ -157,8 +156,8 @@ void early_init_dmi(void) DMIBAR32(0x0914 + (i << 5)) = 0x98200280; } - DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; + DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 + DMIBAR32(DMIL0SLAT) = 0x00c2403c; early_pch_init_native_dmi_pre(); diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 2ee273c1f4..45b5b8f10a 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,10 +52,10 @@ static void sandybridge_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index fee7513492..f75dfda616 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -16,7 +16,6 @@ #include "chip.h" #include "sandybridge.h" -#include "gma.h" struct gt_powermeter { u16 reg; diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h deleted file mode 100644 index c15ad5370f..0000000000 --- a/src/northbridge/intel/sandybridge/gma.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H -#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H - -struct i915_gpu_controller_info; - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, - u8 *mmio, u32 lfb); - -int i915lightup_ivy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, - u8 *mmio, u32 lfb); - -#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 8da4ec9eeb..b0a5149dbf 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -10,6 +10,8 @@ #include #include #include "sandybridge.h" +#include +#include static uintptr_t smm_region_start(void) { diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h new file mode 100644 index 0000000000..98251259e1 --- /dev/null +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#define GFXVT_BASE 0xfed90000ULL +#define VTVC0_BASE 0xfed91000ULL + +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 1d20a4b57a..541bf73bee 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -39,18 +40,16 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base) +int decode_pcie_bar(u32 *const base, u32 *const len) { - struct device *dev; - u32 pciexbar_reg; - *base = 0; + *len = 0; - dev = pcidev_on_root(0, 0); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) @@ -58,14 +57,17 @@ static int get_pcie_bar(u32 *base) switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - *base = pciexbar_reg & (0xffffffffULL << 28); - return 256; + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * MiB; + return 1; case 1: /* 128M */ - *base = pciexbar_reg & (0xffffffffULL << 27); - return 128; + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * MiB; + return 1; case 2: /* 64M */ - *base = pciexbar_reg & (0xffffffffULL << 26); - return 64; + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * MiB; + return 1; } return 0; @@ -129,8 +131,7 @@ static void add_fixed_resources(struct device *dev, int index) static void mc_read_resources(struct device *dev) { - u32 pcie_config_base; - int buses; + u32 pcie_config_base, pcie_config_len; uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; uint16_t ggc; @@ -139,8 +140,8 @@ static void mc_read_resources(struct device *dev) pci_dev_read_resources(dev); - buses = get_pcie_bar(&pcie_config_base); - if (buses) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { + const int buses = pcie_config_len / MiB; struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, pcie_config_base, buses); } @@ -261,8 +262,8 @@ static void northbridge_dmi_init(struct device *dev) u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -272,9 +273,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x250) = reg32; } - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; if (bridge_silicon_revision() >= SNB_STEP_D0) { reg32 = DMIBAR32(0x1f8); @@ -299,9 +300,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0xd04) = reg32; } - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 422067b5d2..319fea3a5d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -54,8 +54,47 @@ static void disable_channel(ramctr_timing *ctrl, int channel) memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } -/* Fill cbmem with information for SMBIOS type 17 */ -static void fill_smbios17(ramctr_timing *ctrl) +static bool nb_supports_ecc(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_ECCDIS); +} + +static uint16_t nb_slots_per_channel(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_DDPCD) + 1; +} + +static uint16_t nb_number_of_channels(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_PDCD) + 1; +} + +static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) +{ + uint32_t ddrsz; + + /* Values from documentation, which assume two DIMMs per channel */ + switch (CAPID_DDRSZ(capid0_a)) { + case 1: + ddrsz = 8192; + break; + case 2: + ddrsz = 2048; + break; + case 3: + ddrsz = 512; + break; + default: + ddrsz = 16384; + break; + } + + /* Account for the maximum number of DIMMs per channel */ + return (ddrsz / 2) * nb_slots_per_channel(capid0_a); +} + +/* Fill cbmem with information for SMBIOS type 16 and type 17 */ +static void setup_sdram_meminfo(ramctr_timing *ctrl) { int channel, slot; const u16 ddr_freq = (1000 << 8) / ctrl->tCK; @@ -66,6 +105,19 @@ static void fill_smbios17(ramctr_timing *ctrl) if (ret != CB_SUCCESS) printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); } + + /* The 'spd_add_smbios17' function allocates this CBMEM area */ + struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); + if (m == NULL) + return; + + const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + + const uint16_t channels = nb_number_of_channels(capid0_a); + + m->ecc_capable = nb_supports_ecc(capid0_a); + m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); + m->number_of_devices = channels * nb_slots_per_channel(capid0_a); } /* Return CRC16 match for all SPDs */ @@ -115,10 +167,8 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); - spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) + if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) ch_dimms++; } @@ -245,7 +295,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; spd_raw_data spds[4]; - struct region_device rdev; + size_t mrc_size; ramctr_timing *ctrl_cached = NULL; MCHBAR32(SAPMCTL) |= 1; @@ -272,10 +322,11 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) early_thermal_init(); /* Try to find timings in MRC cache */ - err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); - - if (!err && !(region_device_sz(&rdev) < sizeof(ctrl))) - ctrl_cached = rdev_mmap_full(&rdev); + ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); + if (mrc_size < sizeof(ctrl)) + ctrl_cached = NULL; /* Before reusing training data, assert that the CPU has not been replaced */ if (ctrl_cached && cpuid != ctrl_cached->cpu) { @@ -364,14 +415,44 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) set_scrambling_seed(&ctrl); + if (!s3resume && ctrl.ecc_enabled) + channel_scrub(&ctrl); + set_normal_operation(&ctrl); final_registers(&ctrl); + /* can't do this earlier because it needs to be done in normal operation */ + if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { + uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); + + printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", + tseg); + + /* + * This test helps to debug the ECC scrubbing. + * It likely tests every channel/rank, as rank interleave and enhanced + * interleave are enabled, but there's no guarantee for it. + */ + + /* Skip first MB to avoid special case for A-seg and test up to TSEG */ + for (i = 1; i < tseg >> 20; i++) { + for (int j = 0; j < 1 * MiB; j += 4096) { + uintptr_t addr = i * MiB + j; + if (read32((u32 *)addr) == 0) + continue; + + printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at" + " addr 0x%lx\n", addr); + break; + } + } + printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); + } + /* Zone config */ dram_zones(&ctrl, 0); - intel_early_me_status(); intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); @@ -386,7 +467,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) } if (!s3resume) - fill_smbios17(&ctrl); + setup_sdram_meminfo(&ctrl); } void perform_raminit(int s3resume) diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index dc0134312f..c5d881a196 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -5,12 +5,9 @@ #include "pei_data.h" -struct sys_info { - u8 boot_path; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 #define BOOT_PATH_RESUME 2 -} __packed; void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 371527e9ef..3527c8e520 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "raminit_native.h" #include "raminit_common.h" @@ -318,8 +319,14 @@ void dram_dimm_mapping(ramctr_timing *ctrl) reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* Rank interleave */ - reg |= 1 << 22; /* Enhanced interleave */ + /* + * Rank interleave: Bit 16 of the physical address space sets + * the rank to use in a dual single rank DIMM configuration. + * That results in every 64KiB being interleaved between two ranks. + */ + reg |= 1 << 21; + /* Enhanced interleave */ + reg |= 1 << 22; if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { ctrl->mad_dimm[channel] = reg; @@ -343,7 +350,8 @@ void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; } - //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ + if (ctrl->ecc_enabled) + udelay(10); } void dram_zones(ramctr_timing *ctrl, int training) @@ -4259,98 +4267,126 @@ int channel_test(ramctr_timing *ctrl) void channel_scrub(ramctr_timing *ctrl) { int channel, slotrank, row, rowsize; + u8 bank; + FOR_ALL_POPULATED_CHANNELS { + wait_for_iosav(channel); + fill_pattern0(ctrl, channel, 0, 0); + MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; + } + + /* + * During runtime the "scrubber" will periodically scan through the memory in the + * physical address space, to identify and fix CRC errors. + * The following loops writes to every DRAM address, setting the ECC bits to the + * correct value. A read from this location will no longer return a CRC error, + * except when a bit has toggled due to external events. + * The same could be accieved by writing to the physical memory map, but it's + * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, + * and firmware running in x86_32. + */ FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; - for (row = 0; row < rowsize; row += 16) { + for (bank = 0; bank < 8; bank++) { + for (row = 0; row < rowsize; row += 16) { - wait_for_iosav(channel); + /* + * DRAM command ACT + * Opens the row for writing. + */ + { + u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = gap, + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = row, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_1 = 1, + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, - ctrl->tRRD), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = row, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_1 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); + /* + * DRAM command WR + * Writes (128 + 1) * 8 (burst length) * 8 (bus width) + * bytes. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 129, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tWTR + + ctrl->CWL + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = row, + .rowbits = 0, + .bank = bank, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 9, + }, + }; + iosav_write_ssq(channel, &ssq); + } + + /* + * DRAM command PRE + * Closes the row. + */ + { + const struct iosav_ssq ssq = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }; + iosav_write_ssq(channel, &ssq); + } + + /* Execute command queue */ + iosav_run_queue(channel, 16, 0); + + wait_for_iosav(channel); } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 129, - .cmd_delay_gap = 4, - .post_ssq_wait = 40, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = row, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 40, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); } } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 3f31950408..32f2b44d4b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -45,8 +45,8 @@ struct iosav_ssq { /* IOSAV_n_SP_CMD_CTRL */ union { struct { - u32 command : 16; - u32 ranksel_ap : 2; + u32 command : 16; /* [15.. 0] */ + u32 ranksel_ap : 2; /* [17..16] */ u32 : 14; }; u32 raw; @@ -55,13 +55,13 @@ struct iosav_ssq { /* IOSAV_n_SUBSEQ_CTRL */ union { struct { - u32 cmd_executions : 9; + u32 cmd_executions : 9; /* [ 8.. 0] */ u32 : 1; - u32 cmd_delay_gap : 5; + u32 cmd_delay_gap : 5; /* [14..10] */ u32 : 1; - u32 post_ssq_wait : 9; + u32 post_ssq_wait : 9; /* [24..16] */ u32 : 1; - u32 data_direction : 2; + u32 data_direction : 2; /* [27..26] */ u32 : 4; }; u32 raw; @@ -70,12 +70,12 @@ struct iosav_ssq { /* IOSAV_n_SP_CMD_ADDR */ union { struct { - u32 address : 16; - u32 rowbits : 3; + u32 address : 16; /* [15.. 0] */ + u32 rowbits : 3; /* [18..16] */ u32 : 1; - u32 bank : 3; + u32 bank : 3; /* [22..20] */ u32 : 1; - u32 rank : 2; + u32 rank : 2; /* [25..24] */ u32 : 6; }; u32 raw; @@ -84,14 +84,14 @@ struct iosav_ssq { /* IOSAV_n_ADDR_UPDATE */ union { struct { - u32 inc_addr_1 : 1; - u32 inc_addr_8 : 1; - u32 inc_bank : 1; - u32 inc_rank : 2; - u32 addr_wrap : 5; - u32 lfsr_upd : 2; - u32 upd_rate : 4; - u32 lfsr_xors : 2; + u32 inc_addr_1 : 1; /* [ 0.. 0] */ + u32 inc_addr_8 : 1; /* [ 1.. 1] */ + u32 inc_bank : 1; /* [ 2.. 2] */ + u32 inc_rank : 2; /* [ 4.. 3] */ + u32 addr_wrap : 5; /* [ 9.. 5] */ + u32 lfsr_upd : 2; /* [11..10] */ + u32 upd_rate : 4; /* [15..12] */ + u32 lfsr_xors : 2; /* [17..16] */ u32 : 14; }; u32 raw; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1ec54b328e..697862f661 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include "raminit.h" #include "pei_data.h" @@ -70,8 +72,8 @@ void save_mrc_data(struct pei_data *pei_data) static void prepare_mrc_cache(struct pei_data *pei_data) { - struct region_device rdev; u16 c1, c2, checksum, seed_checksum; + size_t mrc_size; /* Preset just in case there is an error */ pei_data->mrc_input = NULL; @@ -101,16 +103,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data) return; } - if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) { + pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); + if (pei_data->mrc_input == NULL) { /* Error message printed in find_current_mrc_cache */ return; } - pei_data->mrc_input = rdev_mmap_full(&rdev); - pei_data->mrc_input_len = region_device_sz(&rdev); + pei_data->mrc_input_len = mrc_size; - printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, - pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, + pei_data->mrc_input, mrc_size); } /** @@ -120,7 +124,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data) */ void sdram_initialize(struct pei_data *pei_data) { - struct sys_info sysinfo; int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); /* Wait for ME to be ready */ @@ -129,10 +132,6 @@ void sdram_initialize(struct pei_data *pei_data) printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - memset(&sysinfo, 0, sizeof(sysinfo)); - - sysinfo.boot_path = pei_data->boot_mode; - /* * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. @@ -251,10 +250,10 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data) { const struct device *dev = pcidev_on_root(0x19, 0); - pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; pei_data->wdbbar = 0x04000000; pei_data->wdbsize = 0x1000; - pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->rcba = (uintptr_t)DEFAULT_RCBA; pei_data->pmbase = DEFAULT_PMBASE; pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->gbe_enable = dev && dev->enabled; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e95f154c02..326197b9bd 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -8,6 +8,9 @@ #include #include #include +#include +#include + #include "raminit_native.h" #include "raminit_common.h" #include "raminit_tables.h" @@ -297,7 +300,6 @@ static void find_cas_tck(ramctr_timing *ctrl) ctrl->CAS = val; } - static void dram_timing(ramctr_timing *ctrl) { /* @@ -684,9 +686,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ err = channel_test(ctrl); if (err) return err; - - if (ctrl->ecc_enabled) - channel_scrub(ctrl); } /* Set MAD-DIMM registers */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 1bba1809c6..22aea5b508 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -5,6 +5,8 @@ #include "sandybridge.h" #include +#include +#include /* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */ void read_spd(spd_raw_data *spd, u8 addr, bool id_only); diff --git a/src/northbridge/intel/sandybridge/raminit_tables.c b/src/northbridge/intel/sandybridge/raminit_tables.c index bd0d11778a..c3ba9de863 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.c +++ b/src/northbridge/intel/sandybridge/raminit_tables.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include "raminit_tables.h" const u32 frq_refi_map[2][8] = { diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h index 99077a4528..49101cb5ee 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.h +++ b/src/northbridge/intel/sandybridge/raminit_tables.h @@ -3,7 +3,7 @@ #ifndef RAMINIT_TABLES_H #define RAMINIT_TABLES_H -#include +#include extern const u32 frq_refi_map[2][8]; @@ -23,8 +23,6 @@ extern const u8 frq_aonpd_map[2][8]; extern const u32 frq_comp2_map[2][8]; - - extern const u32 pattern[32][16]; extern const u8 use_base[63][32]; diff --git a/src/northbridge/intel/sandybridge/registers/dmibar.h b/src/northbridge/intel/sandybridge/registers/dmibar.h new file mode 100644 index 0000000000..d47588b192 --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/dmibar.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_DMIBAR_H__ +#define __SANDYBRIDGE_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIRCLDECH 0x040 /* 32bit */ +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ +#define TXTRN (1 << 11) + +#define DMILCTL2 0x098 /* 16bit */ +#define DMILSTS2 0x09a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#define DMIL0SLAT 0x22c /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ + +#endif /* __SANDYBRIDGE_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/registers/epbar.h b/src/northbridge/intel/sandybridge/registers/epbar.h new file mode 100644 index 0000000000..386dbe1262 --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/epbar.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_EPBAR_H__ +#define __SANDYBRIDGE_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#endif /* __SANDYBRIDGE_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h new file mode 100644 index 0000000000..4814b94b6f --- /dev/null +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ +#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 + +#define GGC 0x50 /* GMCH Graphics Control */ +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define PAVPC 0x58 /* Protected Audio Video Path Control */ +#define DPR 0x5c /* DMA Protected Range */ + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 +#define MESEG_MASK 0x78 +#define MELCK (1 << 10) /* ME Range Lock */ +#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ + +#define REMAPBASE 0x90 +#define REMAPLIMIT 0x98 +#define TOM 0xa0 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data of Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEGMB 0xb8 /* TSEG Memory Base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define CAPID0_A 0xe4 /* Capabilities Register A */ +#define CAPID_ECCDIS (1 << 25) +#define CAPID_DDPCD (1 << 14) +#define CAPID_PDCD (1 << 12) +#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) + +#define CAPID0_B 0xe8 /* Capabilities Register B */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#define DIDOR 0xf3 /* Device ID override, for debug and samples only */ + +#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h similarity index 86% rename from src/northbridge/intel/sandybridge/mchbar_regs.h rename to src/northbridge/intel/sandybridge/registers/mchbar.h index 849a8927a6..2fe6b24e76 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ -#define __SANDYBRIDGE_MCHBAR_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ +#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__ /* * ### IOSAV memory controller interface poking state machine notes ### @@ -188,6 +188,85 @@ * [6] Cleared with a new sequence, and set when done and refresh counter is drained. */ +/* + * ### ECC error injection registers ### + * + * ECC_INJECT_COUNT_ch(channel) + * Defines the count of write chunks (64-bit data packets) until the + * next ECC error injection. This only seems to apply if the ECC_inject + * field in the ECC_DFT register is 110 or 111. The count is of chunks + * in order to allow creating ECC errors on different 64-bit chunks. + * + * Note that this register is only 32-bit. + * + * ECC_DFT_ch(channel) + * Control ECC DFT features, such as ECC4ANA, error inject, etc. + * + * Bitfields: + * [7..0] 8-bit fill value for ECC4ANA function. + * [9..8] ECC4ANA trigger: + * 00: ECC4ANA is off, no trigger. + * 10: Trigger on single-bit or uncorrectable error. + * 11: Trigger on uncorrectable error. + * + * [10] ECC4ANA byte select: + * 0: Byte 0 + * 1: Byte 7 + * + * [13..11] ECC_inject: ECC error inject options: + * 000: No ECC error injection. + * 100: Inject non-recoverable ECC error on GODLAT indication. + * 101: Inject non-recoverable ECC error on ECC_INJ_ADDR_COMPARE reg match. + * 110: Reserved. + * 111: Inject non-recoverable ECC error on ECC error insertion counter. + * + * [14] ECC correction disable: when set, the MC reports every error as uncorrectable. + * [15] Mark incoming transactions for ECC4ANA based on ECC_INJ_ADDR_COMPARE reg match. + * + * SCHED_SECOND_CBIT + * More chicken bits! + * + * Bitfields: + * + * [11] Disable ECC4ANA Bug Fix. WARNING: This register is only for Ivy Bridge! + * + * MAD_DIMM_ch(channel) + * Channel characteristics: number of DIMMs, number of ranks, size, + * (enhanced) interleave options and ECC options. + * + * Bitfields: + * [7..0] DIMM A size in 256 MiB units. + * [15..8] DIMM B size in 256 MiB units. + * [16] Select which of the DIMMs is DIMM A, should be the larger DIMM. + * [17] DIMM A number of ranks. (0 => Single Rank, 1 => Dual Rank) + * [18] DIMM B number of ranks. + * [19] DIMM A DDR chip width. (0 => x8, 1 => x16) + * [20] DIMM B DDR chip width. + * [21] Enable Rank Interleave. + * [22] Enable Enhanced Rank Interleave. + * [25..24] ECC control: + * 00: No ECC. + * 01: ECC is active in IO, ECC logic is not active. Used with IOSAV training. + * 10: ECC is disabled in IO, but ECC logic is enabled. Used with ECC4ANA mode. + * 11: ECC active in both IO and ECC logic. + * + * ECC_INJ_ADDR_COMPARE, ECC_INJ_ADDR_MASK + * + * Address compare for ECC error inject. Error injection is issued when + * ECC_INJ_ADDR_COMPARE[31..0] = ADDR[37..6] & ECC_INJ_ADDR_MASK[31..0]. + * + * MC_LOCK + * + * Locking of MC registers. Each bit locks one group of registers. + * + * Bitfields: + * [0] Lock all the address map registers. + * [1] Lock all the MC configuration registers including MCIO. + * [2] Lock all IOSAV and Init registers. + * [3] Lock all power management registers. + * [7] Lock all DFT features. + */ + /* Indexed register helper macros */ #define Gz(r, z) ((r) + ((z) << 8)) #define Ly(r, y) ((r) + ((y) << 2)) @@ -401,6 +480,9 @@ #define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ #define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ +#define ECC_INJ_ADDR_COMPARE 0x5090 /* Address compare for ECC error inject */ +#define ECC_INJ_ADDR_MASK 0x5094 /* Address mask for ECC error inject */ + #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ #define GFXVTBAR 0x5400 /* Base address for IGD */ @@ -451,4 +533,4 @@ #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ #define CRDTLCK 0x77fc -#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1652b095cf..8f9d118288 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -20,23 +20,11 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) - -#define GFXVT_BASE 0xfed90000ULL -#define VTVC0_BASE 0xfed91000ULL +#include "memmap.h" /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include +#include /* Chipset types */ enum platform_type { @@ -44,68 +32,15 @@ enum platform_type { PLATFORM_DESKTOP_SERVER, }; - /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#define EPBAR 0x40 -#define MCHBAR 0x48 - -#define GGC 0x50 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_PEG60 (1 << 13) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_IGD (1 << 4) -#define DEVEN_PEG10 (1 << 3) -#define DEVEN_PEG11 (1 << 2) -#define DEVEN_PEG12 (1 << 1) -#define DEVEN_HOST (1 << 0) - -#define PAVPC 0x58 /* Protected Audio Video Path Control */ -#define DPR 0x5c /* DMA Protected Range */ - -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 - -#define MESEG_BASE 0x70 -#define MESEG_MASK 0x78 -#define MELCK (1 << 10) /* ME Range Lock */ -#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define LAC 0x87 /* Legacy Access Control */ -#define SMRAM 0x88 /* System Management RAM Control */ - -#define REMAPBASE 0x90 -#define REMAPLIMIT 0x98 -#define TOM 0xa0 -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data of Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEGMB 0xb8 /* TSEG Memory Base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ - -#define CAPID0_A 0xe4 /* Capabilities Register A */ -#define CAPID0_B 0xe8 /* Capabilities Register B */ - -#define SKPAD 0xdc /* Scratchpad Data */ - -#define DIDOR 0xf3 /* Device ID override, for debug and samples only */ - +#include "registers/host_bridge.h" /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ #define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ #define MSAC 0x62 /* Multi Size Aperture Control */ @@ -128,7 +63,7 @@ enum platform_type { #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" /* * EPBAR - Egress Port Root Complex Register Block @@ -138,28 +73,7 @@ enum platform_type { #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCAP2 0x008 /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define PORTARB 0x100 /* 256bit */ +#include "registers/epbar.h" /* * DMIBAR @@ -169,46 +83,7 @@ enum platform_type { #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ -#define DMIPVCCAP2 0x008 /* 32bit */ - -#define DMIPVCCCTL 0x00c /* 16bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP 0x2 - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP 0x2 - -#define DMIVCPRCTL 0x02c /* 32bit */ - -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP 0x2 - -#define DMIVCMRCTL 0x0038 /* 32 bit */ -#define DMIVCMRSTS 0x003e /* 16 bit */ -#define VCMNP 0x2 - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ -#define TXTRN (1 << 11) -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ - -#define DMICC 0x208 /* 32bit */ - -#define DMIDRCCFG 0xeb4 /* 32bit */ +#include "registers/dmibar.h" #ifndef __ASSEMBLER__ @@ -227,6 +102,8 @@ void perform_raminit(int s3resume); void report_memory_config(void); enum platform_type get_platform_type(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include struct acpi_rsdp; diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8432..00e9a3ad21 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 57173fd156..4088e75dae 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -9,10 +9,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - u32 pciexbar = 0; - u32 length = 0; + u32 pciexbar, length; - if (!decode_pciebar(&pciexbar, &length)) + if (!decode_pcie_bar(&pciexbar, &length)) return current; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 51deea8f67..5a3c0b6132 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../iomap.h" +#include "../memmap.h" #include /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 5db93824ce..1192fdb1cb 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,17 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include + #include "x4x.h" -#include "iomap.h" void bootblock_early_northbridge_init(void) { - uint32_t reg32; - /* Disable LaGrande Technology (LT) */ - reg32 = TPM32(0); + read32((void *)TPM_BASE_ADDRESS); - reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; + pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index dda41744ae..1535452c1f 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -6,7 +6,6 @@ #include #include #include "x4x.h" -#include "iomap.h" static void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose) @@ -129,7 +128,6 @@ static int decrement_dq_dqs(const struct sysinfo *s, return CB_SUCCESS; } - #define WT_PATTERN_SIZE 80 static const u32 write_training_schedule[WT_PATTERN_SIZE] = { @@ -220,7 +218,7 @@ static int find_dq_limit(const struct sysinfo *s, const u8 channel, expected_result == FAILING ? "failing" : "succeeding", channel); memset(pass_count, 0, sizeof(pass_count)); - while(succes_mask) { + while (succes_mask) { test_result = test_dq_aligned(s, channel); FOR_EACH_BYTELANE(lane) { if (((test_result >> lane) & 1) != expected_result) { @@ -390,7 +388,7 @@ static int rt_find_dqs_limit(struct sysinfo *s, u8 channel, FOR_EACH_BYTELANE(lane) rt_set_dqs(channel, lane, 0, &dqs_setting[lane]); - while(status == CB_SUCCESS) { + while (status == CB_SUCCESS) { test_result = test_dqs_aligned(s, channel); if (test_result == (expected_result == SUCCEEDING ? 0 : 0xff)) return CB_SUCCESS; @@ -498,7 +496,7 @@ int do_read_training(struct sysinfo *s) FOR_EACH_BYTELANE(lane) { saved_dqs_center[channel][lane] /= RT_LOOPS; while (saved_dqs_center[channel][lane]--) { - if(rt_increment_dqs(&s->rt_dqs[channel][lane]) + if (rt_increment_dqs(&s->rt_dqs[channel][lane]) == CB_ERR) /* Should never happen */ printk(BIOS_ERR, diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 87c684ced6..81752cdd9f 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -2,7 +2,6 @@ #include #include -#include "iomap.h" #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include /* DEFAULT_PMBASE */ #else @@ -15,32 +14,30 @@ void x4x_early_init(void) { - const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ - pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); /* Setup EPBAR. */ - pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(d0f0, D0F0_PAM(0), 0x30); - pci_write_config8(d0f0, D0F0_PAM(1), 0x33); - pci_write_config8(d0f0, D0F0_PAM(2), 0x33); - pci_write_config8(d0f0, D0F0_PAM(3), 0x33); - pci_write_config8(d0f0, D0F0_PAM(4), 0x33); - pci_write_config8(d0f0, D0F0_PAM(5), 0x33); - pci_write_config8(d0f0, D0F0_PAM(6), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(0), 0x30); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(1), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(2), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(3), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(4), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(5), 0x33); + pci_write_config8(HOST_BRIDGE, D0F0_PAM(6), 0x33); - if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { + if (!(pci_read_config32(HOST_BRIDGE, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN); /* Set preallocated IGD size from CMOS */ u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */ @@ -51,10 +48,10 @@ void x4x_early_init(void) else if (gfxsize < 1) gfxsize = 1; /* Set GTT size to 2+2M */ - pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); + pci_write_config16(HOST_BRIDGE, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4); } else { /* Does not feature internal graphics */ - pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); - pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); + pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(HOST_BRIDGE, D0F0_GGC, (1 << 1)); } } diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h new file mode 100644 index 0000000000..00b496dca8 --- /dev/null +++ b/src/northbridge/intel/x4x/hostbridge_regs.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_HOSTBRIDGE_REGS_H__ +#define __X4X_HOSTBRIDGE_REGS_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +#endif /* __X4X_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e2be..aa737f391f 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -57,15 +57,11 @@ u32 decode_tseg_size(const u32 esmramc) } } -u8 decode_pciebar(u32 *const base, u32 *const len) +int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; *len = 0; - const pci_devfn_t dev = PCI_DEV(0, 0, 0); - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; + const struct { u16 num_buses; u32 addr_mask; @@ -76,16 +72,16 @@ u8 decode_pciebar(u32 *const base, u32 *const len) {0, 0}, }; - pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO); if (!(pciexbar_reg & 1)) { printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); return 0; } - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; + const u32 index = (pciexbar_reg >> 1) & 3; + const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask; + const int max_buses = busmask[index].num_buses; if (!pciexbar) { printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); @@ -99,16 +95,15 @@ u8 decode_pciebar(u32 *const base, u32 *const len) static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC); return decode_tseg_size(esmramc); } static uintptr_t northbridge_get_tseg_base(void) { - return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); + return pci_read_config32(HOST_BRIDGE, D0F0_TSEG); } - /* Depending of UMA and TSEG configuration, TSEG might start at any * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/memmap.h similarity index 60% rename from src/northbridge/intel/x4x/iomap.h rename to src/northbridge/intel/x4x/memmap.h index d016cf74af..e4aafffbf6 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/memmap.h @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef X4X_IOMAP_H -#define X4X_IOMAP_H +#ifndef X4X_MEMMAP_H +#define X4X_MEMMAP_H #define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_HECIBAR 0xfed10000 -#define TPMBASE 0xfed40000 -#define TPM32(x) (*((volatile u32 *)(TPMBASE + (x)))) +#define TPM_BASE_ADDRESS 0xfed40000 -#endif /* X4X_IOMAP_H */ +#endif /* X4X_MEMMAP_H */ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 9c32dae275..5e46270dc1 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include @@ -111,7 +111,7 @@ static void mch_domain_read_resources(struct device *dev) top32memk - (DEFAULT_HECIBAR >> 10), IORESOURCE_RESERVE); - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, index++, pcie_config_base >> 10, diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 174e8b501e..a1be5aa449 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -14,7 +14,6 @@ #include #include -#include "iomap.h" #include "x4x.h" #define MRC_CACHE_VERSION 0 @@ -99,7 +98,6 @@ static void select_cas_dramfreq_ddr2(struct sysinfo *s, try_cas--; } - if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0)) die("Could not find common memory frequency and CAS\n"); @@ -122,11 +120,11 @@ static void mchinfo_ddr2(struct sysinfo *s) const u32 eax = cpuid_ext(0x04, 0).eax; printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1); - u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), 0xe8); + u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8); if (!(capid & (1<<(79-64)))) printk(BIOS_WARNING, "iTPM enabled\n"); - capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + capid = pci_read_config32(HOST_BRIDGE, 0xe4); if (!(capid & (1<<(57-32)))) printk(BIOS_WARNING, "ME enabled\n"); @@ -246,7 +244,7 @@ static void select_cas_dramfreq_ddr3(struct sysinfo *s, u32 min_tCLK; u8 try_CAS; - u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f; + u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f; switch (s->max_fsb) { default: @@ -344,7 +342,7 @@ static void workaround_stacked_mode(struct sysinfo *s) if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) return; /* IGD0EN gets disabled if not present before this code runs */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN); if (deven & IGD0EN) s->stacked_mode = 1; } @@ -411,7 +409,6 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, return CB_SUCCESS; } - static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings) { @@ -593,9 +590,9 @@ static void checkreset_ddr2(int boot_path) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); /* do magic 0xf0 thing. */ - pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2)); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2)); full_reset(); } @@ -610,20 +607,21 @@ void sdram_initialize(int boot_path, const u8 *spd_map) { struct sysinfo s, *ctrl_cached; u8 reg8; - int fast_boot, cbmem_was_inited, cache_not_found; - struct region_device rdev; + int fast_boot, cbmem_was_inited; + size_t mrc_size; timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); - pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); + pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); memset(&s, 0, sizeof(struct sysinfo)); - cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, - MRC_CACHE_VERSION, &rdev); + ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + MRC_CACHE_VERSION, + &mrc_size); - if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { + if (!ctrl_cached || mrc_size < sizeof(s)) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ system_reset(); @@ -632,9 +630,6 @@ void sdram_initialize(int boot_path, const u8 *spd_map) and therefore requiring valid cached settings */ full_reset(); } - ctrl_cached = NULL; - } else { - ctrl_cached = rdev_mmap_full(&rdev); } /* verify MRC cache for fast boot */ @@ -671,7 +666,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) checkreset_ddr2(s.boot_path); /* Detect dimms per channel */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9); + reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2); @@ -687,7 +682,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1); + pci_or_config8(HOST_BRIDGE, 0xf4, 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 332af327f5..617ce11581 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -13,7 +13,6 @@ #include #endif #include -#include "iomap.h" #include "x4x.h" #define ME_UMA_SIZEMB 0 @@ -33,7 +32,6 @@ u32 ddr_to_mhz(u32 speed) return mhz[speed]; } - static void program_crossclock(struct sysinfo *s) { u8 i, j; @@ -919,9 +917,6 @@ static void program_dll(struct sysinfo *s) break; } - if (async != 1) - reg8 = MCHBAR8(0x188) & 0x1e; - MCHBAR8_AND(0x180, ~0x80); if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) @@ -1270,14 +1265,14 @@ static void pre_jedec_memory_map(void) MCHBAR8(0x110) = (2 << 5) | (3 << 3); MCHBAR16(0x10e) = 0; MCHBAR32(0x108) = 0; - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000); + pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000); /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10); + pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10); /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000); + pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400); + pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000); + pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000); + pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000); } u32 test_address(int channel, int rank) @@ -1286,7 +1281,6 @@ u32 test_address(int channel, int rank) return channel * 512 * MiB + rank * 128 * MiB; } - /* DDR3 Rank1 Address mirror * swap the following pins: * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ @@ -1702,7 +1696,7 @@ static void configure_mmap(struct sysinfo *s) 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; - ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); + ggc = pci_read_config16(HOST_BRIDGE, 0x52); gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, @@ -1733,20 +1727,20 @@ static void configure_mmap(struct sysinfo *s) gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; - pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4); - pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6); + pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); + pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); if (reclaim) { - pci_write_config16(PCI_DEV(0, 0, 0), 0x98, + pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6)); - pci_write_config16(PCI_DEV(0, 0, 0), 0x9a, + pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6)); } - pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); + pci_write_config16(HOST_BRIDGE, 0xa2, touud); + pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); + pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20); /* Enable and set TSEG size to 2M */ - pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); - pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); + pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20); } static void set_enhanced_mode(struct sysinfo *s) @@ -1779,8 +1773,8 @@ static void set_enhanced_mode(struct sysinfo *s) MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; } - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1); + reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz ? 0x20000 : 0)); reg32 = 0x219100c2; @@ -1822,7 +1816,7 @@ static void set_enhanced_mode(struct sysinfo *s) if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) reg32 |= 0x20000; MCHBAR32(0x20) = reg32; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); + pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1); } static void power_settings(struct sysinfo *s) @@ -1943,7 +1937,7 @@ static void power_settings(struct sysinfo *s) MCHBAR32(0x1110) = 0x10810350 & ~0x78; MCHBAR32(0x1114) = 0; x592 = 0xff; - if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3) + if (pci_read_config8(HOST_BRIDGE, 0x8) < 3) x592 = ~0x4; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { @@ -2056,7 +2050,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) MCHBAR8_OR(0x5d8, 0x7); } if (CHANNEL_IS_POPULATED(s->dimms, 1)) { - if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) { + if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); MCHBAR8_OR(0x5d8, 1); } @@ -2166,7 +2160,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) if (!fast_boot) { if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { - if(do_write_training(s)) + if (do_write_training(s)) die("DQ write training failed!"); } if (do_read_training(s)) diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 3cd4879787..e4a80d8441 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -290,7 +290,6 @@ const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */ }, }; - const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ /* 115h[15:0] 117h[23:0] */ { /* 1N mode */ diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 332d89c526..82481abe30 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -3,7 +3,6 @@ #include #include #include -#include "iomap.h" #include "x4x.h" #define MAX_COARSE 15 @@ -19,7 +18,7 @@ struct rec_timing { u8 tap; }; -static inline void barrier(void) +static inline void mfence(void) { asm volatile("mfence":::); } @@ -33,10 +32,10 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel) udelay(2); MCHBAR8(RESET_CNTL(channel)) |= 0x2; udelay(2); - barrier(); + mfence(); /* Read strobe */ read32((u32 *)addr); - barrier(); + mfence(); return (MCHBAR8(sample_offset) >> 6) & 1; } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 5418b4141d..ff157add29 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -4,53 +4,23 @@ #define __NORTHBRIDGE_INTEL_X4X_H__ #include -#include "iomap.h" +#include "memmap.h" /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0EN (1 << 0) -#define D1EN (1 << 1) -#define IGD0EN (1 << 3) -#define IGD1EN (1 << 4) -#define D3F0EN (1 << 6) -#define D3F1EN (1 << 7) -#define D3F2EN (1 << 8) -#define D3F3EN (1 << 9) -#define PEG1EN (1 << 13) -#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_GBSM 0xa4 -#define D0F0_BGSM 0xa8 -#define D0F0_TSEG 0xac -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define HOST_BRIDGE PCI_DEV(0, 0, 0) + +#include "hostbridge_regs.h" /* * D1:F0 PEG */ -#define PEG_CAP 0xa2 -#define SLOTCAP 0xb4 -#define PEGLC 0xec -#define D1F0_VCCAP 0x104 -#define D1F0_VC0RCTL 0x114 +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 /* * Graphics frequencies @@ -70,21 +40,18 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) \ - (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR16_AND_OR(x, and, or) \ - (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR32_AND_OR(x, and, or) \ - (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) #define CHDECMISC 0x111 #define STACKED_MEM (1 << 1) @@ -122,49 +89,49 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 +#define DMIVC0RCTL 0x14 +#define DMIVC1RCTL 0x20 +#define DMIVC1RSTS 0x26 +#define DMIESD 0x44 +#define DMILE1D 0x50 +#define DMILE1A 0x58 +#define DMILE2D 0x60 +#define DMILE2A 0x68 /* * EPBAR */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPESD 0x44 +#define EPLE1D 0x50 +#define EPLE1A 0x58 +#define EPLE2D 0x60 -#define NOP_CMD 0x2 -#define PRECHARGE_CMD 0x4 -#define MRS_CMD 0x6 -#define EMRS_CMD 0x8 -#define EMRS1_CMD (EMRS_CMD | 0x10) -#define EMRS2_CMD (EMRS_CMD | 0x20) -#define EMRS3_CMD (EMRS_CMD | 0x30) -#define ZQCAL_CMD 0xa -#define CBR_CMD 0xc -#define NORMALOP_CMD 0xe +#define NOP_CMD 0x2 +#define PRECHARGE_CMD 0x4 +#define MRS_CMD 0x6 +#define EMRS_CMD 0x8 +#define EMRS1_CMD (EMRS_CMD | 0x10) +#define EMRS2_CMD (EMRS_CMD | 0x20) +#define EMRS3_CMD (EMRS_CMD | 0x30) +#define ZQCAL_CMD 0xa +#define CBR_CMD 0xc +#define NORMALOP_CMD 0xe -#define TOTAL_CHANNELS 2 -#define TOTAL_DIMMS 4 -#define TOTAL_BYTELANES 8 -#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) -#define RAW_CARD_UNPOPULATED 0xff -#define RAW_CARD_POPULATED 0 +#define TOTAL_CHANNELS 2 +#define TOTAL_DIMMS 4 +#define TOTAL_BYTELANES 8 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) +#define RAW_CARD_UNPOPULATED 0xff +#define RAW_CARD_POPULATED 0 #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) @@ -224,9 +191,9 @@ #define DDR3_MAX_CAS 18 enum fsb_clock { - FSB_CLOCK_800MHz = 0, - FSB_CLOCK_1066MHz = 1, - FSB_CLOCK_1333MHz = 2, + FSB_CLOCK_800MHz = 0, + FSB_CLOCK_1066MHz = 1, + FSB_CLOCK_1333MHz = 2, }; enum mem_clock { @@ -234,8 +201,8 @@ enum mem_clock { MEM_CLOCK_533MHz = 1, MEM_CLOCK_667MHz = 2, MEM_CLOCK_800MHz = 3, - MEM_CLOCK_1066MHz = 4, - MEM_CLOCK_1333MHz = 5, + MEM_CLOCK_1066MHz = 4, + MEM_CLOCK_1333MHz = 5, }; enum ddr { @@ -286,7 +253,7 @@ enum n_banks { struct timings { unsigned int CAS; - unsigned int tclk; + unsigned int tclk; enum fsb_clock fsb_clk; enum mem_clock mem_clk; unsigned int tRAS; @@ -300,15 +267,14 @@ struct timings { }; struct dimminfo { - unsigned int card_type; /* 0xff: unpopulated, - 0xa - 0xf: raw card type A - F */ + unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ enum chip_width width; unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ enum n_banks n_banks; unsigned int ranks; unsigned int rows; unsigned int cols; - u16 spd_crc; + u16 spd_crc; u8 mirrored; }; @@ -363,7 +329,7 @@ void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); -u8 decode_pciebar(u32 *const base, u32 *const len); +int decode_pcie_bar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); void rcven(struct sysinfo *s); @@ -372,8 +338,7 @@ u32 ddr_to_mhz(u32 speed); u32 test_address(int channel, int rank); void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); void dqset(u8 ch, u8 lane, const struct dll_setting *setting); -void rt_set_dqs(u8 channel, u8 lane, u8 rank, - struct rt_dqs_setting *dqs_setting); +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); int do_write_training(struct sysinfo *s); int do_read_training(struct sysinfo *s); void search_write_leveling(struct sysinfo *s); diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index f7dd363faa..52863542e5 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -27,20 +27,93 @@ menu "SMI Transfer Monitor (STM)" config MSEG_SIZE hex "mseg size" - default 0x400000 + default 0x100000 help - STM only - 0x100000 - STM/PE - 0x300000+ depending on the amount of memory needed - for the protected execution virtual - machine (VM/PE) + The MSEG_SIZE of 0x100000 assumes that: + IED_REGION_SIZE = 0x400000 + SMM_RESERVED_SIZE = 0x200000 + SMM_TSEG_SIZE = 0x800000 + + To use STM/PE, a larger MSEG_SIZE is necessary. This can be + done by either increasing SMM_TSEG_SIZE or reducing the + IED_REGION_SIZE and/or SMM_RESERVED_SIZE or some combination + of the three. + NOTE: The authors experience is that these configuration + parameters have to be changed at the soc Konfig for them to + be applied. + Minimum sizes: + STM only - 0x100000 - Supports up to 38 processor threads + - 0x200000 - Supports up to 102 processor threads + STM/PE - 0x300000+ depending on the amount of memory needed + for the protected execution virtual + machine (VM/PE) + +config STM_STMPE_ENABLED + bool "STM/PE Enabled" + default n + help + STM/PE provides for additional virtual machines in SMRAM + that provides a protected execution environment for + applications such as introspection, which need to be + protected from malicious code. More information can be + found on the stmpe branch of + https://review.coreboot.org/STM + config BIOS_RESOURCE_LIST_SIZE - hex "bios_resource_list_size" + hex "bios resource list size" default 0x1000 + help + The BIOS resource list defines the resources that the + SMI handler needs. This list is created during the + coreboot bootup. Unless there has been a lot of elements + added to this list, this value should not change. config STM_BINARY_FILE string "STM binary file" - default "3rdparty/blobs/cpu/intel/stm/stm.bin" + default "3rdparty/stm/Stm/build/StmPkg/Core/stm.bin" + help + Location of the STM binary file. The default location is + where the file will be located when coreboot builds + the STM. + +config STM_HEAPSIZE + hex "stm heapsize" + default 0x46000 + help + The STM_HEAPSIZE defines the heap space that is available + to the STM. The default size assumes a MSEG_SIZE of 0x100000. + For STM/PE this size should be a minimum of 0x246000. + +config STM_TTYS0_BASE + hex "stm uart" + default TTYS0_BASE if TTYS0_BASE + default 0x000 + help + Defines the serial port for STM console output. 0x000 indicates + no serial port. + +config STM_CBMEM_CONSOLE + bool "STM cbmem console" + default n + depends on CONSOLE_CBMEM + help + Places the STM console output into the cbmem. + +choice + prompt "Select STM console output" + +config STM_CONSOLE_DEBUG + bool "Debug output" + depends on STM_CBMEM_CONSOLE || STM_TTYS0_BASE + help + "Produces all STM console output" + +config STM_CONSOLE_RELEASE + bool "Deactivate console output" + help + "No console output is produced" +endchoice endmenu #STM diff --git a/src/security/intel/stm/Makefile b/src/security/intel/stm/Makefile new file mode 100644 index 0000000000..1493869e80 --- /dev/null +++ b/src/security/intel/stm/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-2-Clause + +project_name=STM +project_dir=../../../../3rdparty/stm/ +build_dir=$(project_dir)/Stm/build +project_git_branch=$(CONFIG_STM_GIT_BRANCH) + +ifeq ($(CONFIG_STM_CONSOLE_DEBUG),y) +STM_BUILD="debug" +endif + +ifeq ($(CONFIG_STM_CONSOLE_RELEASE),y) +STM_BUILD="release" +endif + + +all: build + +build: + echo "STM - Build" + cd $(project_dir)/Stm; \ + mkdir -p build; \ + cd build; \ + cmake .. -DBIOS=coreboot \ + -DUART=$(CONFIG_STM_TTYS0_BASE) \ + -DHEAPSIZE=$(CONFIG_STM_HEAPSIZE) \ + -DCBMEM_ENABLE=$(CONFIG_STM_CBMEM_CONSOLE) \ + -DSTMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \ + -DBUILD=$(STM_BUILD); \ + $(MAKE); + + +.PHONY: build diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc index 1a23fe97f2..3f5b9ee5c6 100644 --- a/src/security/intel/stm/Makefile.inc +++ b/src/security/intel/stm/Makefile.inc @@ -8,3 +8,13 @@ stm.bin-type := raw ramstage-$(CONFIG_STM) += SmmStm.c ramstage-$(CONFIG_STM) += StmPlatformSmm.c ramstage-$(CONFIG_STM) += StmPlatformResource.c + +3rdparty/stm/Stm/build/StmPkg/Core/stm.bin: $(obj)/config.h + $(MAKE) -C src/security/intel/stm \ + CONFIG_STM_TTYSO_BASE=$(CONFIG_STM_TTYSO_BASE) \ + CONFIG_STM_HEAPSIZE=$(CONFIG_STM_HEAPSIZE) \ + CONFIG_STM_CONSOLE_DEBUG=$(CONFIG_STM_CONSOLE_DEBUG) \ + CONFIG_STM_CONSOLE_RELEASE=$(CONFIG_STM_CONSOLE_RELEASE) \ + CONFIG_STM_GIT_BRANCH=$(CONFIG_STM_GIT_BRANCH) \ + CONFIG_STM_STMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \ + CONFIG_STM_CBMEM_CONSOLE=$(CONFIG_STM_CBMEM_CONSOLE) diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 87873f5a69..e2fab0c063 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define TXT_EVTYPE_BASE 0x400 @@ -476,7 +477,7 @@ int add_pi_resource(STM_RSC *resource_list, uint32_t num_entries) return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08lx\n", resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08zx\n", resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index 0447a9edc2..b395493a06 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -4,6 +4,7 @@ #define _SMM_STM_H_ #include "StmApi.h" +#include /* * Load STM image. diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 1d21bf7af2..eb9a0bb22f 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -72,7 +73,6 @@ struct descriptor { uintptr_t base; } __attribute__((packed)); - static void read_gdtr(struct descriptor *gdtr) { __asm__ __volatile__("sgdt %0" : "=m"(*gdtr)); @@ -117,7 +117,6 @@ void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, psd->smm_other_segment = ROM_DATA_SEG; psd->smm_tr = SMM_TASK_STATE_SEG; - // At this point the coreboot smm_stub is relative to the default // smbase and not the one for the smi handler in tseg. So we have // to adjust the gdtr.base diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 732f3d3c67..3dd912ea6e 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -9,7 +9,7 @@ config INTEL_TXT depends on (TPM1 || TPM2) depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE depends on PLATFORM_HAS_DRAM_CLEAR - depends on SOC_INTEL_COMMON_BLOCK_SA + depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) if INTEL_TXT @@ -19,7 +19,7 @@ config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE help - Intel TXT BIOS ACM file. This file can be obtained by privileged + Intel TXT BIOS ACM file. This file can be obtained through privileged access to Intel resources. Or for some platforms found inside the blob repository. @@ -27,16 +27,34 @@ config INTEL_TXT_SINITACM_FILE string "SINIT ACM file" default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE help - Intel TXT SINIT ACM file. This file can be obtained by privileged + Intel TXT SINIT ACM file. This file can be obtained through privileged access to Intel resources. Or for some platforms found inside the blob repository. +config INTEL_TXT_LOGGING + bool "Enable verbose logging" + help + Print more TXT related debug output. + Use in pre-production environments only! + config INTEL_TXT_BIOSACM_ALIGNMENT hex - default 0x20000 # 128KB + default 0x20000 # 128 KiB help - Exceptions are Ivy- and Sandy Bridge with 64KB and Purely with 256KB - alignment size. Please overwrite it SoC specific. + Exceptions are Ivy and Sandy Bridge with 64 KiB and Purley with 256 KiB + alignment size. If necessary, override from platform-specific Kconfig. + +config INTEL_TXT_CBFS_BIOS_POLICY + string + default "txt_bios_policy.bin" + +config INTEL_TXT_CBFS_BIOS_ACM + string + default "txt_bios_acm.bin" + +config INTEL_TXT_CBFS_SINIT_ACM + string + default "txt_sinit_acm.bin" endmenu # Intel diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 38eb65d69c..39c3ad1dff 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,5 +1,14 @@ ifeq ($(CONFIG_INTEL_TXT),y) +romstage-y += common.c +romstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c + +ramstage-y += common.c +ramstage-y += getsec.c +ramstage-y += getsec_enteraccs.S +ramstage-y += ramstage.c +ramstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c + cbfs-files-y += txt_bios_acm.bin txt_bios_acm.bin-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) txt_bios_acm.bin-type := raw @@ -13,6 +22,8 @@ txt_sinit_acm.bin-align := 0x10 txt_sinit_acm.bin-compression := lzma endif +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) + INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -26,7 +37,9 @@ ibb-files += bootblock INTERMEDIATE+=add_ibb_fit add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) - $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT)) true + $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ + -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT)) true -endif +endif # CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +endif # INTEL_TXT diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c new file mode 100644 index 0000000000..e73defb912 --- /dev/null +++ b/src/security/intel/txt/common.c @@ -0,0 +1,440 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) +#include +#else +#include +#endif + +#include "txt.h" +#include "txt_register.h" +#include "txt_getsec.h" + +/* Usual security practice: if an unexpected error happens, reboot */ +static void __noreturn txt_reset_platform(void) +{ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) + global_reset(); +#else + full_reset(); +#endif +} + +/** + * Dump the ACM error status bits. + * + * @param acm_error The status register to dump + * @return -1 on error (register is not valid) + * 0 on error (Class > 0 and Major > 0) + * 1 on success (Class == 0 and Major == 0 and progress > 0) + */ +int intel_txt_log_acm_error(const uint32_t acm_error) +{ + if (!(acm_error & ACMERROR_TXT_VALID)) + return -1; + + const uint8_t type = (acm_error & ACMERROR_TXT_TYPE_CODE) + >> ACMERROR_TXT_TYPE_SHIFT; + + switch (type) { + case ACMERROR_TXT_AC_MODULE_TYPE_BIOS: + printk(BIOS_ERR, "BIOSACM"); + break; + case ACMERROR_TXT_AC_MODULE_TYPE_SINIT: + printk(BIOS_ERR, "SINIT"); + break; + default: + printk(BIOS_ERR, "ACM"); + break; + } + printk(BIOS_ERR, ": Error code valid\n"); + + if (acm_error & ACMERROR_TXT_EXTERNAL) + printk(BIOS_ERR, " Caused by: External\n"); + else + printk(BIOS_ERR, " Caused by: Processor\n"); + + const uint32_t class = (acm_error & ACMERROR_TXT_CLASS_CODE) + >> ACMERROR_TXT_CLASS_SHIFT; + const uint32_t major = (acm_error & ACMERROR_TXT_MAJOR_CODE) + >> ACMERROR_TXT_MAJOR_SHIFT; + const uint32_t minor = (acm_error & ACMERROR_TXT_MINOR_CODE) + >> ACMERROR_TXT_MINOR_SHIFT; + const uint32_t progress = (acm_error & ACMERROR_TXT_PROGRESS_CODE) + >> ACMERROR_TXT_PROGRESS_SHIFT; + + if (!minor) { + if (class == 0 && major == 0 && progress > 0) { + printk(BIOS_ERR, " Execution successful\n"); + printk(BIOS_ERR, " Progress code 0x%x\n", progress); + } else { + printk(BIOS_ERR, " Error Class: %x\n", class); + printk(BIOS_ERR, " Error: %x.%x\n", major, progress); + } + } else { + printk(BIOS_ERR, " ACM didn't start\n"); + printk(BIOS_ERR, " Error Type: 0x%x\n", acm_error & 0xffffff); + return -1; + } + + return (acm_error & ACMERROR_TXT_EXTERNAL) && class == 0 && major == 0 && progress > 0; +} + +void intel_txt_log_spad(void) +{ + const uint64_t acm_status = read64((void *)TXT_SPAD); + + printk(BIOS_INFO, "TXT-STS: ACM verification "); + + if (acm_status & ACMSTS_VERIFICATION_ERROR) + printk(BIOS_INFO, "error\n"); + else + printk(BIOS_INFO, "successful\n"); + + printk(BIOS_INFO, "TXT-STS: IBB "); + + if (acm_status & ACMSTS_IBB_MEASURED) + printk(BIOS_INFO, "measured\n"); + else + printk(BIOS_INFO, "not measured\n"); + + printk(BIOS_INFO, "TXT-STS: TXT is "); + + if (acm_status & ACMSTS_TXT_DISABLED) + printk(BIOS_INFO, "disabled\n"); + else + printk(BIOS_INFO, "not disabled\n"); + + printk(BIOS_INFO, "TXT-STS: BIOS is "); + + if (acm_status & ACMSTS_BIOS_TRUSTED) + printk(BIOS_INFO, "trusted\n"); + else + printk(BIOS_INFO, "not trusted\n"); +} + +/* Returns true if secrets might be in memory */ +bool intel_txt_memory_has_secrets(void) +{ + bool ret; + if (!CONFIG(INTEL_TXT)) + return false; + + ret = (read8((void *)TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64((void *)TXT_E2STS) & TXT_E2STS_SECRET_STS); + + if (ret) + printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); + return ret; +} + +static struct acm_info_table *find_info_table(const void *ptr) +{ + const struct acm_header_v0 *acm_header = (struct acm_header_v0 *)ptr; + + return (struct acm_info_table *)(ptr + + (acm_header->header_len + acm_header->scratch_size) * sizeof(uint32_t)); +} + +/** + * Validate that the provided ACM is useable on this platform. + */ +static int validate_acm(const void *ptr) +{ + const struct acm_header_v0 *acm_header = (struct acm_header_v0 *)ptr; + uint32_t max_size_acm_area = 0; + + if (acm_header->module_type != CHIPSET_ACM) + return ACM_E_TYPE_NOT_MATCH; + + /* Seems inconsistent across generations. */ + if (acm_header->module_sub_type != 0 && acm_header->module_sub_type != 1) + return ACM_E_MODULE_SUB_TYPE_WRONG; + + if (acm_header->module_vendor != INTEL_ACM_VENDOR) + return ACM_E_MODULE_VENDOR_NOT_INTEL; + + if (acm_header->size == 0) + return ACM_E_SIZE_INCORRECT; + + if (((acm_header->header_len + acm_header->scratch_size) * sizeof(uint32_t) + + sizeof(struct acm_info_table)) > (acm_header->size & 0xffffff) * sizeof(uint32_t)) { + return ACM_E_SIZE_INCORRECT; + } + + if (!getsec_parameter(NULL, NULL, &max_size_acm_area, NULL, NULL, NULL)) + return ACM_E_CANT_CALL_GETSEC; + + /* + * Causes #GP if acm_header->size > processor internal authenticated + * code area capacity. + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + */ + const size_t acm_len = 1UL << log2_ceil((acm_header->size & 0xffffff) << 2); + if (max_size_acm_area < acm_len) { + printk(BIOS_ERR, "TEE-TXT: BIOS ACM doesn't fit into AC execution region\n"); + return ACM_E_NOT_FIT_INTO_CPU_ACM_MEM; + } + + struct acm_info_table *info = find_info_table(ptr); + if (!info) + return ACM_E_NO_INFO_TABLE; + if (info->chipset_acm_type != BIOS) + return ACM_E_NOT_BIOS_ACM; + + static const u8 acm_uuid[] = { + 0xaa, 0x3a, 0xc0, 0x7f, 0xa7, 0x46, 0xdb, 0x18, + 0x2e, 0xac, 0x69, 0x8f, 0x8d, 0x41, 0x7f, 0x5a, + }; + if (memcmp(acm_uuid, info->uuid, sizeof(acm_uuid)) != 0) + return ACM_E_UUID_NOT_MATCH; + + if ((acm_header->flags & ACM_FORMAT_FLAGS_DEBUG) == + (read64((void *)TXT_VER_FSBIF) & TXT_VER_PRODUCTION_FUSED)) + return ACM_E_PLATFORM_IS_NOT_PROD; + + return 0; +} + +/* + * Test all bits for TXT execution. + * + * @return 0 on success + */ +int intel_txt_run_bios_acm(const u8 input_params) +{ + struct cbfsf file; + void *acm_data; + struct region_device acm; + size_t acm_len; + int ret; + + if (cbfs_boot_locate(&file, CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL)) { + printk(BIOS_ERR, "TEE-TXT: Couldn't locate BIOS ACM in CBFS.\n"); + return -1; + } + + cbfs_file_data(&acm, &file); + acm_data = rdev_mmap_full(&acm); + acm_len = region_device_sz(&acm); + if (!acm_data || acm_len == 0) { + printk(BIOS_ERR, "TEE-TXT: Couldn't map BIOS ACM from CBFS.\n"); + return -1; + } + + /* + * CPU enforces only 4KiB alignment. + * Chapter A.1.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + if (!IS_ALIGNED((uintptr_t)acm_data, 4096)) { + printk(BIOS_ERR, "TEE-TXT: BIOS ACM isn't mapped at page boundary.\n"); + rdev_munmap(&acm, acm_data); + return -1; + } + + /* + * Causes #GP if not multiple of 64. + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + */ + if (!IS_ALIGNED(acm_len, 64)) { + printk(BIOS_ERR, "TEE-TXT: BIOS ACM size isn't multiple of 64.\n"); + rdev_munmap(&acm, acm_data); + return -1; + } + + /* + * The ACM should be aligned to it's size, but that's not possible, as + * some ACMs are not power of two. Use the next power of two for verification. + */ + if (!IS_ALIGNED((uintptr_t)acm_data, (1UL << log2_ceil(acm_len)))) { + printk(BIOS_ERR, "TEE-TXT: BIOS ACM isn't aligned to its size.\n"); + rdev_munmap(&acm, acm_data); + return -1; + } + + if (CONFIG(INTEL_TXT_LOGGING)) + txt_dump_acm_info(acm_data); + + ret = validate_acm(acm_data); + if (ret < 0) { + printk(BIOS_ERR, "TEE-TXT: Validation of ACM failed with: %d\n", ret); + rdev_munmap(&acm, acm_data); + return ret; + } + + /* Call into assembly which invokes the referenced ACM */ + getsec_enteraccs(input_params, (uintptr_t)acm_data, acm_len); + + rdev_munmap(&acm, acm_data); + + const uint64_t acm_status = read64((void *)TXT_SPAD); + if (acm_status & ACMERROR_TXT_VALID) { + printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); + /* + * WARNING ! + * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! + */ + intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + return -1; + } + if (intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)) != 1) + return -1; + + return 0; +} + + /* Returns true if cond is not met */ +static bool check_precondition(const int cond) +{ + printk(BIOS_DEBUG, "%s\n", cond ? "true" : "false"); + return !cond; +} + +/* + * Test all bits that are required for Intel TXT. + * Enable SMX if available. + * + * @return 0 on success + */ +bool intel_txt_prepare_txt_env(void) +{ + bool failure = false; + uint32_t txt_feature_flags = 0; + + unsigned int ecx = cpuid_ecx(1); + + printk(BIOS_DEBUG, "TEE-TXT: CPU supports SMX: "); + failure |= check_precondition(ecx & CPUID_SMX); + + printk(BIOS_DEBUG, "TEE-TXT: CPU supports VMX: "); + failure |= check_precondition(ecx & CPUID_VMX); + + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (!(msr.lo & BIT(0))) { + printk(BIOS_ERR, "TEE-TXT: IA32_FEATURE_CONTROL is not locked\n"); + txt_reset_platform(); + } + + printk(BIOS_DEBUG, "TEE-TXT: IA32_FEATURE_CONTROL\n"); + printk(BIOS_DEBUG, " VMXON in SMX enable: "); + failure |= check_precondition(msr.lo & BIT(1)); + + printk(BIOS_DEBUG, " VMXON outside SMX enable: "); + failure |= check_precondition(msr.lo & FEATURE_ENABLE_VMX); + + printk(BIOS_DEBUG, " register is locked: "); + failure |= check_precondition(msr.lo & BIT(0)); + + /* IA32_FEATURE_CONTROL enables getsec instructions */ + printk(BIOS_DEBUG, " GETSEC (all instructions) is enabled: "); + failure |= check_precondition((msr.lo & 0xff00) == 0xff00); + + /* Prevent crash and opt out early */ + if (failure) + return true; + + uint32_t eax = 0; + /* + * GetSec[CAPABILITIES] + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + * Must check BIT0 of TXT chipset has been detected by CPU. + */ + if (!getsec_capabilities(&eax)) + return true; + + printk(BIOS_DEBUG, "TEE-TXT: GETSEC[CAPABILITIES] returned:\n"); + printk(BIOS_DEBUG, " TXT capable chipset: %s\n", (eax & BIT(0)) ? "true" : "false"); + + printk(BIOS_DEBUG, " ENTERACCS available: %s\n", (eax & BIT(2)) ? "true" : "false"); + printk(BIOS_DEBUG, " EXITAC available: %s\n", (eax & BIT(3)) ? "true" : "false"); + printk(BIOS_DEBUG, " SENTER available: %s\n", (eax & BIT(4)) ? "true" : "false"); + printk(BIOS_DEBUG, " SEXIT available: %s\n", (eax & BIT(5)) ? "true" : "false"); + printk(BIOS_DEBUG, " PARAMETERS available: %s\n", (eax & BIT(6)) ? "true" : "false"); + + /* + * Causes #GP if function is not supported by getsec. + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + * Order Number: 325383-060US + */ + if ((eax & 0x7d) != 0x7d) + failure = true; + + const uint64_t status = read64((void *)TXT_SPAD); + + if (status & ACMSTS_TXT_DISABLED) { + printk(BIOS_INFO, "TEE-TXT: TXT disabled by BIOS policy in FIT.\n"); + failure = true; + } + + /* + * Only the BSP must call getsec[ENTERACCS]. + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + * Order Number: 325383-060US + */ + if (!boot_cpu()) { + printk(BIOS_ERR, "TEE-TXT: BSP flag not set in APICBASE_MSR.\n"); + failure = true; + } + + /* + * There must be no MCEs pending. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + * Order Number: 325383-060US + */ + msr = rdmsr(IA32_MCG_STATUS); + if (msr.lo & 0x4) { + printk(BIOS_ERR, "TEE-TXT: IA32_MCG_STATUS.MCIP is set.\n"); + failure = true; + } + + if (!getsec_parameter(NULL, NULL, NULL, NULL, NULL, &txt_feature_flags)) { + return true; + } else { + printk(BIOS_DEBUG, "TEE-TXT: Machine Check Register: "); + if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK) + printk(BIOS_DEBUG, "preserved\n"); + else + printk(BIOS_DEBUG, "must be clear\n"); + } + + if (!(txt_feature_flags & GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK)) { + /* + * Make sure there are no uncorrectable MCE errors. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + */ + msr = rdmsr(IA32_MCG_CAP); + size_t max_mc_msr = msr.lo & MCA_BANKS_MASK; + for (size_t i = 0; i < max_mc_msr; i++) { + msr = rdmsr(IA32_MC0_STATUS + 4 * i); + if (!(msr.hi & MCA_STATUS_HI_UC)) + continue; + + printk(BIOS_ERR, "TEE-TXT: IA32_MC%zd_STATUS.UC is set.\n", i); + failure = true; + break; + } + } + + /* Need to park all APs. */ + if (CONFIG(PARALLEL_MP_AP_WORK)) + mp_park_aps(); + + return failure; +} diff --git a/src/security/intel/txt/getsec.c b/src/security/intel/txt/getsec.c new file mode 100644 index 0000000000..422f10d7c8 --- /dev/null +++ b/src/security/intel/txt/getsec.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "txt_register.h" +#include "txt_getsec.h" + +/** + * Check for SMX support and enable it if possible. + * + * Returns false on error, true on success. + */ +static bool getsec_enabled(void) +{ + unsigned int ecx = cpuid_ecx(1); + /* + * Check if SMX and VMX is supported by CPU. + */ + if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) + return false; + + /* + * Check if SMX, VMX and GetSec instructions haven't been disabled. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if ((msr.lo & 0xff06) != 0xff06) + return false; + + /* + * Enable SMX. Required to execute GetSec instruction. + * Chapter 2.2.4.3 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + write_cr4(read_cr4() | CR4_SMXE); + + return true; +} + +/** + * Get information as returned by getsec[PARAMETER]. + * Arguments can be set to NULL if not needed. + * + * Returns false on error, true on success. + */ +bool getsec_parameter(uint32_t *version_mask, + uint32_t *version_numbers_supported, + uint32_t *max_size_acm_area, + uint32_t *memory_type_mask, + uint32_t *senter_function_disable, + uint32_t *txt_feature_flags) +{ + uint32_t i, eax, ebx, ecx; + + if (!getsec_enabled()) + return false; + + /* + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + */ + for (i = 0; i < 0x1f; i++) { + /* Getsec[PARAMETERS] */ + asm volatile ("getsec\n" + : "=a" (eax), "=b" (ebx), "=c" (ecx) + : "a" (IA32_GETSEC_PARAMETERS), "b" (i) :); + switch (eax & 0x1f) { + case 0: /* NULL - Exit marker */ + return true; + case 1: /* Supported AC module versions */ + if (version_mask) + *version_mask = ebx; + if (version_numbers_supported) + *version_numbers_supported = ecx; + break; + case 2: /* Max size of authenticated code execution area */ + if (max_size_acm_area) + *max_size_acm_area = eax & ~0x1f; + break; + case 3: /* External memory types supported during AC mode */ + if (memory_type_mask) + *memory_type_mask = eax; + break; + case 4: /* Selective SENTER functionality control */ + if (senter_function_disable) + *senter_function_disable = eax & (0x3f00); + break; + case 5: /* TXT extensions support */ + if (txt_feature_flags) + *txt_feature_flags = eax & (0x60); + break; + } + } + + return true; +} + +/** + * Get capabilities as returned by getsec[CAPABILITIES]. + * + * Returns false on error, true on success. + */ + +bool getsec_capabilities(uint32_t *eax) +{ + if (!getsec_enabled()) + return false; + + asm volatile ("getsec\n" + : "=a" (*eax) + : "a" (IA32_GETSEC_CAPABILITIES), "b" (0) :); + + return true; +} diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S new file mode 100644 index 0000000000..3135de79b2 --- /dev/null +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) + +.macro PUSH_MSR x + movl $(\x), %ecx + rdmsr + push %eax + push %edx +.endm + +.macro POP_MSR x + movl $(\x), %ecx + pop %edx + pop %eax + wrmsr +.endm + +.macro CLEAR_MSR x + movl $(\x), %ecx + xorl %edx, %edx + xorl %eax, %eax + wrmsr +.endm + +.align 4 +.text + +/* + * See "SAFER MODE EXTENSIONS REFERENCE." + * Chapter "GETSEC[ENTERACCS] - Execute Authenticated Chipset Code" for reference. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D + * + * void getsec_enteraccs(uint32_t esi, + * uint32_t acm_base, + * uint32_t acm_size); + */ +.global getsec_enteraccs +getsec_enteraccs: + + /* Backup current register state */ + pushl %ebp + movl %esp, %ebp + + pushal + + movl %cr0, %eax + pushl %eax + movl %cr4, %eax + pushl %eax + + /* Pushed 10 32bit registers */ + + /* Reserve space on stack for GDT */ + subl $8, %esp + + PUSH_MSR IA32_MISC_ENABLE + PUSH_MSR MTRR_FIX_64K_00000 + PUSH_MSR MTRR_FIX_16K_80000 + PUSH_MSR MTRR_FIX_16K_A0000 + PUSH_MSR MTRR_FIX_4K_C0000 + PUSH_MSR MTRR_FIX_4K_C8000 + PUSH_MSR MTRR_FIX_4K_D0000 + PUSH_MSR MTRR_FIX_4K_D8000 + PUSH_MSR MTRR_FIX_4K_E0000 + PUSH_MSR MTRR_FIX_4K_F0000 + PUSH_MSR MTRR_FIX_4K_F8000 + + /* Push variable MTRRs in ascending order */ + + xorl %ebx, %ebx + jmp cond_push_var_mtrrs + +body_push_var_mtrrs: + + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx + rdmsr + push %eax + push %edx + incl %ecx /* MTRR_PHYS_MASK */ + rdmsr + push %eax + push %edx + + incl %ebx + +cond_push_var_mtrrs: + + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + cmp %ebx, %eax + jg body_push_var_mtrrs + + /* + * Disable cache. + * Chapter 2.2.4.3 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + movl %cr0, %eax + orl $(CR0_CD | CR0_NW), %eax + movl %eax, %cr0 + + /* Disable fixed MTRRs */ + movl $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* + * Clear fixed MTRRs. + * Chapter 2.2.5.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + CLEAR_MSR MTRR_FIX_64K_00000 + CLEAR_MSR MTRR_FIX_16K_80000 + CLEAR_MSR MTRR_FIX_16K_A0000 + CLEAR_MSR MTRR_FIX_4K_C0000 + CLEAR_MSR MTRR_FIX_4K_C8000 + CLEAR_MSR MTRR_FIX_4K_D0000 + CLEAR_MSR MTRR_FIX_4K_D8000 + CLEAR_MSR MTRR_FIX_4K_E0000 + CLEAR_MSR MTRR_FIX_4K_F0000 + CLEAR_MSR MTRR_FIX_4K_F8000 + + /* + * Clear variable MTRRs + * Chapter 2.2.5.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + movl %eax, %ebx + + xorl %eax, %eax + xorl %edx, %edx + + jmp cond_clear_var_mtrrs + +body_clear_var_mtrrs: + + decl %ebx + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx + wrmsr + incl %ecx /* MTRR_PHYS_MASK */ + wrmsr + +cond_clear_var_mtrrs: + + cmpl $0, %ebx + jnz body_clear_var_mtrrs + + /* + * Setup BIOS ACM as WB + * Chapter A.1.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + movl $(MTRR_PHYS_BASE(0)), %ecx + movl 12(%ebp), %eax /* %eax = acmbase */ + orl $(6), %eax /* MTRR_TYPE_WB */ + movl $0, %edx + wrmsr + + /* Round acmsize to next power of two. Required for MTRR programming. */ + movl $1, %ebx + movl 16(%ebp), %ecx /* %ebx = acmsize */ + dec %ecx + bsr %ecx, %ecx /* find MSB */ + inc %ecx + shl %cl, %ebx + movl $(MTRR_PHYS_MASK(0)), %ecx + xorl %eax, %eax + subl %ebx, %eax /* %eax = 4GIB - log2_ceil(ACM SIZE) */ + orl $((1 << 11)), %eax /* MTRR_PHYS_MASK_VALID */ + movl MTRR_HIGH_MASK, %edx + wrmsr + + /* Enable cache - GPF# if not done */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + /* Enable Numeric error - GPE# if not done */ + movl %cr0, %eax + orl $(CR0_NE), %eax + movl %eax, %cr0 + + /* Enable SMX and FXSTORE - for getsec */ + movl %cr4, %eax + orl $(CR4_SMXE | CR4_OSFXSR), %eax + movl %eax, %cr4 + + /* + * Save GDT + * Chapter A.1.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + sgdt -48(%ebp) + + /* Backup stack pointer */ + movd %esp, %xmm0 + movd %ebp, %xmm1 + + /* + * Get function arguments. + * It's important to pass the exact ACM size as it's used by getsec to verify + * the integrity of ACM. Unlike the size for MTRR programming, which needs to + * be power of two. + * + * The following assembly code is based on tboot's tboot/include/txt/smx.h. + */ + movl 8(%ebp), %esi /* flags */ + movl 12(%ebp), %ebx /* acm_base */ + movl 16(%ebp), %ecx /* acm_size */ + + movl $0, %edx /* reserved, must be zero */ + movl $0, %edi /* must be zero */ + movl $2, %eax /* GetSec[ENTERACCS] */ + + getsec + + /* Restore stack pointer */ + movd %xmm0, %esp + movd %xmm1, %ebp + + /* Reload GDT */ + lgdt -48(%ebp) + + /* Set cs */ + ljmp $0x10, $1f +1: + /* Fix segment registers */ + movl $0x18, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* Disable cache */ + movl %cr0, %eax + orl $(CR0_CD | CR0_NW), %eax + movl %eax, %cr0 + + /* Pop variable MTRRs in descending order */ + + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + movl %eax, %ebx + + jmp cond_pop_var_mtrrs + +body_pop_var_mtrrs: + + decl %ebx + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_MASK(0)), %ecx + pop %edx + pop %eax + wrmsr + decl %ecx /* MTRR_PHYS_BASE */ + pop %edx + pop %eax + wrmsr + +cond_pop_var_mtrrs: + + cmpl $0, %ebx + jne body_pop_var_mtrrs + + POP_MSR MTRR_FIX_4K_F8000 + POP_MSR MTRR_FIX_4K_F0000 + POP_MSR MTRR_FIX_4K_E0000 + POP_MSR MTRR_FIX_4K_D8000 + POP_MSR MTRR_FIX_4K_D0000 + POP_MSR MTRR_FIX_4K_C8000 + POP_MSR MTRR_FIX_4K_C0000 + POP_MSR MTRR_FIX_16K_A0000 + POP_MSR MTRR_FIX_16K_80000 + POP_MSR MTRR_FIX_64K_00000 + POP_MSR IA32_MISC_ENABLE + + /* Enable fixed MTRRs */ + movl $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + orl $(MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* Enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + /* Pop GDT */ + addl $8, %esp + + popl %eax + movl %eax, %cr4 + popl %eax + movl %eax, %cr0 + + popal + + movl %ebp, %esp + popl %ebp + + ret diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c new file mode 100644 index 0000000000..24def330f9 --- /dev/null +++ b/src/security/intel/txt/logging.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "txt.h" +#include "txt_register.h" + +/** + * Logs microcode or SINIT ACM errors. + * Does not log SBIOS ACM errors. + */ +static void log_txt_error(const char *phase) +{ + const uint64_t txt_error = read64((void *)TXT_ERROR); + + if (txt_error & ACMERROR_TXT_VALID) { + printk(BIOS_ERR, "%s: Error occurred\n", phase); + + if (txt_error & ACMERROR_TXT_EXTERNAL) + printk(BIOS_ERR, " Caused by: External\n"); + else + printk(BIOS_ERR, " Caused by: Processor\n"); + + printk(BIOS_ERR, " Type: "); + + switch (txt_error & TXT_ERROR_MASK) { + case 0: + printk(BIOS_ERR, "Legacy Shutdown\n"); + break; + case 5: + printk(BIOS_ERR, "Load memory type error in ACM area\n"); + break; + case 6: + printk(BIOS_ERR, "Unrecognized ACM format\n"); + break; + case 7: + printk(BIOS_ERR, "Failure to authenticate\n"); + break; + case 8: + printk(BIOS_ERR, "Invalid ACM format\n"); + break; + case 9: + printk(BIOS_ERR, "Unexpected Snoop hit\n"); + break; + case 10: + printk(BIOS_ERR, "Invalid event\n"); + break; + case 11: + printk(BIOS_ERR, "Invalid MLE\n"); + break; + case 12: + printk(BIOS_ERR, "Machine check event\n"); + break; + case 13: + printk(BIOS_ERR, "VMXAbort\n"); + break; + case 14: + printk(BIOS_ERR, "AC memory corruption\n"); + break; + case 15: + printk(BIOS_ERR, "Illegal voltage/bus ratio\n"); + break; + default: + printk(BIOS_ERR, "unknown\n"); + break; + } + } +} + +/** + * Dump useful informaation about the BIOS ACM state. + * Should run right after console_init() in romstage. + * Resets the platform if TXT reset is active and MLE cannot be established. + **/ +void intel_txt_log_bios_acm_error(void) +{ + uint32_t bios_acm_error; + uint64_t acm_status; + uint64_t txt_error; + + printk(BIOS_INFO, "TEE-TXT: State of ACM and ucode update:\n"); + + bios_acm_error = read32((void *)TXT_BIOSACM_ERRORCODE); + acm_status = read64((void *)TXT_SPAD); + txt_error = read64((void *)TXT_ERROR); + + /* Errors by BIOS ACM or FIT */ + if ((txt_error & ACMERROR_TXT_VALID) && + (acm_status & ACMERROR_TXT_VALID)) { + intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + log_txt_error("FIT MICROCODE"); + } + /* Errors by SINIT */ + if ((txt_error & ACMERROR_TXT_VALID) && + !(acm_status & ACMERROR_TXT_VALID)) { + intel_txt_log_acm_error(txt_error); + log_txt_error("SINIT"); + } + + /* Check for fatal ACM error and TXT reset */ + uint8_t error = read8((void *)TXT_ESTS); + if (error & TXT_ESTS_TXT_RESET_STS) { + printk(BIOS_CRIT, "TXT-STS: Intel TXT reset detected\n"); + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + } +} + +/** + * Dump information about the provided ACM. + */ +void txt_dump_acm_info(const struct acm_header_v0 *acm_header) +{ + const struct acm_info_table *info = NULL; + if (!acm_header) + return; + + printk(BIOS_INFO, "ACM @ %p\n", acm_header); + + const size_t acm_size = (acm_header->size & 0xffffff) << 2; + const size_t info_off = (acm_header->header_len + acm_header->scratch_size) * 4; + + if (acm_size > (info_off + sizeof(struct acm_info_table))) + info = (const struct acm_info_table *) + ((const unsigned char *)acm_header + info_off); + + printk(BIOS_INFO, " ACM: Binary Info\n"); + if (acm_header->module_type == CHIPSET_ACM) + printk(BIOS_INFO, " Type: Chipset ACM\n"); + + if (acm_header->module_sub_type == 0) + printk(BIOS_INFO, " Subtype: undefined\n"); + else if (acm_header->module_sub_type == 1) + printk(BIOS_INFO, " Subtype: Run at reset\n"); + + printk(BIOS_INFO, " Header: v%u.%u\n", acm_header->header_version[0], + acm_header->header_version[1]); + + printk(BIOS_INFO, " Chipset: %x\n", acm_header->chipset_id); + printk(BIOS_INFO, " Size: %zu\n", acm_size); + + switch (acm_header->flags) { + case ACM_FORMAT_FLAGS_PW: + printk(BIOS_INFO, " Flags: PW signed (Production Worthy)\n"); + break; + case ACM_FORMAT_FLAGS_NPW: + printk(BIOS_INFO, " Flags: NPW signed (Non Production Worthy)\n"); + break; + case ACM_FORMAT_FLAGS_DEBUG: + printk(BIOS_INFO, " Flags: Debug signed\n"); + break; + } + + if (acm_header->module_vendor == INTEL_ACM_VENDOR) + printk(BIOS_INFO, " Vendor: Intel Corporation\n"); + + printk(BIOS_INFO, " Date: %x\n", acm_header->date); + + switch (acm_header->size) { + case ACM_FORMAT_SIZE_64KB: + printk(BIOS_INFO, " Size: 64KB\n"); + printk(BIOS_INFO, " CBnT: no\n"); + break; + case ACM_FORMAT_SIZE_128KB: + printk(BIOS_INFO, " Size: 128KB\n"); + printk(BIOS_INFO, " CBnT: no\n"); + break; + case ACM_FORMAT_SIZE_256KB: + printk(BIOS_INFO, " Size: 256KB\n"); + printk(BIOS_INFO, " CBnT: yes\n"); + break; + default: + printk(BIOS_INFO, " Size: 0x%08x\n", acm_header->size); + + break; + } + + printk(BIOS_INFO, " TXT SVN: %u\n", acm_header->txt_svn); + printk(BIOS_INFO, " SE SVN: %u\n", acm_header->se_svn); + + if (!info) + return; + printk(BIOS_INFO, " Table info:\n"); + printk(BIOS_INFO, " UUID: "); + for (size_t i = 0; i < sizeof(info->uuid); i++) + printk(BIOS_INFO, "%02X ", info->uuid[i]); + printk(BIOS_INFO, "\n"); + printk(BIOS_INFO, " Chipset acm type: 0x%x\n", info->chipset_acm_type); + printk(BIOS_INFO, " Capabilities: 0x%x\n", info->capabilities); +} + +/** + * Dump information about the chipset's TXT capabilities. + */ +void txt_dump_chipset_info(void) +{ + printk(BIOS_INFO, "TEE-TXT: Chipset Key Hash 0x"); + for (int i = 0; i < TXT_ACM_KEY_HASH_LEN; i++) { + printk(BIOS_INFO, "%llx", read64((void *)TXT_ACM_KEY_HASH + + (i * sizeof(uint64_t)))); + } + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); + printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", + (read64((void *)TXT_VER_FSBIF) & TXT_VER_PRODUCTION_FUSED) ? "true" : "false"); +} + +void txt_dump_regions(void) +{ + struct txt_biosdataregion *bdr = NULL; + uintptr_t tseg = 0; + uint64_t reg64; + + reg64 = read64((void *)TXT_HEAP_BASE); + if ((reg64 != 0 && reg64 != ~0UL) && + (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) + bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); + + printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx\n", tseg * MiB); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64((void *)TXT_SINIT_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64((void *)TXT_MSEG_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64((void *)TXT_MSEG_SIZE)); + + if (bdr) { + printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.bios_sinit_size 0x%x\n", + bdr->bios_sinit_size); + printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.lcp_pd_size 0x%llx\n", + bdr->lcp_pd_size); + printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.lcp_pd_base 0x%llx\n", + bdr->lcp_pd_base); + } +} diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c new file mode 100644 index 0000000000..bc30da5c13 --- /dev/null +++ b/src/security/intel/txt/ramstage.c @@ -0,0 +1,371 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "txt.h" +#include "txt_register.h" +#include "txt_getsec.h" + +/* FIXME: Seems to work only on some platforms */ +static void log_ibb_measurements(void) +{ + const uint64_t mseg_size = read64((void *)TXT_MSEG_SIZE); + uint64_t mseg_base = read64((void *)TXT_MSEG_BASE); + + if (!mseg_size || !mseg_base || mseg_size <= mseg_base) + return; + /* + * MSEG SIZE and MSEG BASE might contain random values. + * Assume below 4GiB and 8byte aligned. + */ + if (mseg_base & ~0xfffffff8ULL || mseg_size & ~0xfffffff8ULL) + return; + + printk(BIOS_INFO, "TEE-TXT: IBB Hash 0x"); + for (; mseg_base < mseg_size; mseg_base++) + printk(BIOS_INFO, "%02X", read8((void *)(uintptr_t)mseg_base)); + + printk(BIOS_INFO, "\n"); +} + +void bootmem_platform_add_ranges(void) +{ + uint64_t status = read64((void *)TXT_SPAD); + + if (status & ACMSTS_TXT_DISABLED) + return; + + /* Chapter 5.5.5 Intel TXT reserved memory */ + bootmem_add_range(TXT_RESERVED_SPACE, + TXT_RESERVED_SPACE_SIZE, + BM_MEM_RESERVED); + + /* Intel TPM decode memory */ + bootmem_add_range(TXT_TPM_DECODE_AREA, + TXT_RESERVED_SPACE - TXT_TPM_DECODE_AREA, + BM_MEM_RESERVED); + + /* Intel TXT public space memory */ + bootmem_add_range(TXT_PUBLIC_SPACE, + TXT_TPM_DECODE_AREA - TXT_PUBLIC_SPACE, + BM_MEM_RESERVED); + + /* Intel TXT private space memory */ + bootmem_add_range(TXT_PRIVATE_SPACE, + TXT_PUBLIC_SPACE - TXT_PRIVATE_SPACE, + BM_MEM_RESERVED); + + const union dpr_register dpr = { + .raw = read32((void *)TXT_DPR), + }; + + const uint32_t dpr_base = dpr.top - dpr.size * MiB; + + /* Chapter 5.5.6 Intel TXT Device Memory */ + bootmem_add_range(dpr_base, dpr.size * MiB, BM_MEM_RESERVED); +} + +static bool get_wake_error_status(void) +{ + const uint8_t error = read8((void *)TXT_ESTS); + return !!(error & TXT_ESTS_WAKE_ERROR_STS); +} + +static void check_secrets_txt(void *unused) +{ + uint64_t status = read64((void *)TXT_SPAD); + + if (status & ACMSTS_TXT_DISABLED) + return; + + /* Check for fatal ACM error and TXT reset */ + if (get_wake_error_status()) { + /* + * Check if secrets bit needs to be reset. Only platforms that support + * CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code. + * Assume all memory really was cleared. + * + * TXT will issue a platform reset to come up sober. + */ + if (intel_txt_memory_has_secrets()) { + printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n"); + intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); + + /* Should never reach this point ... */ + intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + die("Waiting for platform reset...\n"); + } + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, check_secrets_txt, NULL); + +/** + * Log TXT startup errors, check all bits for TXT, run BIOSACM using + * GETSEC[ENTERACCS]. + * + * If a "TXT reset" is detected or "memory had secrets" is set, then do nothing as + * 1. Running ACMs will cause a TXT-RESET + * 2. Memory will be scrubbed in BS_DEV_INIT + * 3. TXT-RESET will be issued by code above later + * + */ +static void init_intel_txt(void *unused) +{ + const uint64_t status = read64((void *)TXT_SPAD); + + if (status & ACMSTS_TXT_DISABLED) + return; + + printk(BIOS_INFO, "TEE-TXT: Initializing TEE...\n"); + + intel_txt_log_spad(); + + if (CONFIG(INTEL_TXT_LOGGING)) { + intel_txt_log_bios_acm_error(); + txt_dump_chipset_info(); + } + + printk(BIOS_INFO, "TEE-TXT: Validate TEE...\n"); + + if (intel_txt_prepare_txt_env()) { + printk(BIOS_ERR, "TEE-TXT: Failed to prepare TXT environment\n"); + return; + } + + /* Check for fatal ACM error and TXT reset */ + if (get_wake_error_status()) { + /* Can't run ACMs with TXT_ESTS_WAKE_ERROR_STS set */ + printk(BIOS_ERR, "TEE-TXT: Fatal BIOS ACM error reported\n"); + return; + } + + printk(BIOS_INFO, "TEE-TXT: Testing BIOS ACM calling code...\n"); + + /* + * Test BIOS ACM code. + * ACM should do nothing on reserved functions, and return an error code + * in TXT_BIOSACM_ERRORCODE. Tests showed that this is not true. + * Use special function "NOP" that does 'nothing'. + */ + if (intel_txt_run_bios_acm(ACMINPUT_NOP) < 0) { + printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM with NOP function.\n"); + return; + } + + if (status & (ACMSTS_BIOS_TRUSTED | ACMSTS_IBB_MEASURED)) { + log_ibb_measurements(); + + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); + if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { + printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); + return; + } + } + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, init_intel_txt, NULL); + +static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length) +{ + /* Push size */ + const uint64_t tmp = data_length + 8; + memcpy(*heap_ptr, &tmp, 8); + *heap_ptr += 8; + + if (data_length) { + /* Push data */ + memcpy(*heap_ptr, data, data_length); + *heap_ptr += data_length; + } +} + +/** + * Finalize the TXT device. + * + * - Lock TXT register. + * - Protect TSEG using DMA protected regions. + * - Setup TXT regions. + * - Place SINIT ACM in TXT_SINIT memory segment. + * - Fill TXT BIOSDATA region. + */ +static void lockdown_intel_txt(void *unused) +{ + const uint64_t status = read64((void *)TXT_SPAD); + uintptr_t tseg = 0; + + if (status & ACMSTS_TXT_DISABLED) + return; + + printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); + + /* Lock TXT config, unlocks TXT_HEAP_BASE */ + if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { + printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); + printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); + return; + } + + /* + * Document Number: 558294 + * Chapter 5.5.6.1 DMA Protection Memory Region + */ + + const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + TXT_CAPABILITIES_DPR); + printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); + + if (dpr_capable) { + /* Protect 3 MiB below TSEG and lock register */ + union dpr_register dpr = { + .lock = 1, + .size = 3, + .top = tseg, + }; + write64((void *)TXT_DPR, dpr.raw); + + // DPR TODO: implement SA_ENABLE_DPR in the intelblocks + + printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", + read32((void *)TXT_DPR)); + } + + /* + * Document Number: 558294 + * Chapter 5.5.6.3 Intel TXT Heap Memory Region + */ + write64((void *)TXT_HEAP_SIZE, 0xE0000); + write64((void *)TXT_HEAP_BASE, + ALIGN_DOWN((tseg * MiB) - read64((void *)TXT_HEAP_SIZE), 4096)); + + /* + * Document Number: 558294 + * Chapter 5.5.6.2 SINIT Memory Region + */ + write64((void *)TXT_SINIT_SIZE, 0x20000); + write64((void *)TXT_SINIT_BASE, + ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - + read64((void *)TXT_SINIT_SIZE), 4096)); + + /* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + struct { + struct txt_biosdataregion bdr; + struct txt_heap_acm_element heap_acm; + struct txt_extended_data_element_header end; + } __packed data = {0}; + + /* TPM2.0 requires version 6 of BDT */ + if (CONFIG(TPM2)) + data.bdr.version = 6; + else + data.bdr.version = 5; + + data.bdr.no_logical_procs = dev_count_cpu(); + + void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + data.bdr.bios_sinit_size = cbfs_boot_load_file(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, + sinit_base, + read64((void *)TXT_SINIT_SIZE), + CBFS_TYPE_RAW); + + if (data.bdr.bios_sinit_size) { + printk(BIOS_INFO, "TEE-TXT: Placing SINIT ACM in memory.\n"); + if (CONFIG(INTEL_TXT_LOGGING)) + txt_dump_acm_info(sinit_base); + } else { + printk(BIOS_ERR, "TEE-TXT: Couldn't locate SINIT ACM in CBFS.\n"); + /* Clear memory */ + memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + } + + struct cbfsf file; + /* The following have been removed from BIOS Data Table in version 6 */ + if (!cbfs_boot_locate(&file, CONFIG_INTEL_TXT_CBFS_BIOS_POLICY, NULL)) { + struct region_device policy; + + cbfs_file_data(&policy, &file); + void *policy_data = rdev_mmap_full(&policy); + size_t policy_len = region_device_sz(&policy); + + if (policy_data && policy_len) { + /* Point to FIT Type 9 entry in flash */ + data.bdr.lcp_pd_base = (uintptr_t)policy_data; + data.bdr.lcp_pd_size = (uint64_t)policy_len; + rdev_munmap(&policy, policy_data); + } else { + printk(BIOS_ERR, "TEE-TXT: Couldn't map LCP PD Policy from CBFS.\n"); + } + } else { + printk(BIOS_ERR, "TEE-TXT: Couldn't locate LCP PD Policy in CBFS.\n"); + } + + data.bdr.support_acpi_ppi = 0; + data.bdr.platform_type = 0; + + /* Extended elements - ACM addresses */ + data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; + data.heap_acm.header.size = sizeof(data.heap_acm); + if (data.bdr.bios_sinit_size) { + data.heap_acm.num_acms = 2; + data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; + } else { + data.heap_acm.num_acms = 1; + } + data.heap_acm.acm_addrs[0] = + (uintptr_t)cbfs_boot_map_with_leak(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, + CBFS_TYPE_RAW, + NULL); + /* Extended elements - End marker */ + data.end.type = HEAP_EXTDATA_TYPE_END; + data.end.size = sizeof(data.end); + + /* Fill TXT.HEAP.BASE with 4 subregions */ + u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); + + /* BiosData */ + push_sinit_heap(&heap_struct, &data, sizeof(data)); + + /* OsMLEData */ + /* FIXME: Does firmware need to write this? */ + push_sinit_heap(&heap_struct, NULL, 0); + + /* OsSinitData */ + /* FIXME: Does firmware need to write this? */ + push_sinit_heap(&heap_struct, NULL, 0); + + /* SinitMLEData */ + /* FIXME: Does firmware need to write this? */ + push_sinit_heap(&heap_struct, NULL, 0); + + /* + * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. + */ + + /** + * Chapter 5.10.1 SMM in the Intel TXT for Servers Environment + * Disable MSEG. + */ + write64((void *)TXT_MSEG_SIZE, 0); + write64((void *)TXT_MSEG_BASE, 0); + + if (CONFIG(INTEL_TXT_LOGGING)) + txt_dump_regions(); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, lockdown_intel_txt, NULL); diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h new file mode 100644 index 0000000000..fc5c49e67e --- /dev/null +++ b/src/security/intel/txt/txt.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_INTEL_TXT_H_ +#define SECURITY_INTEL_TXT_H_ + +#include + +/* Error codes */ +#define ACM_E_TYPE_NOT_MATCH 0x01 +#define ACM_E_MODULE_SUB_TYPE_WRONG 0x02 +#define ACM_E_MODULE_VENDOR_NOT_INTEL 0x03 +#define ACM_E_SIZE_INCORRECT 0x04 +#define ACM_E_CANT_CALL_GETSEC 0x05 +#define ACM_E_NOT_FIT_INTO_CPU_ACM_MEM 0x06 +#define ACM_E_NO_INFO_TABLE 0x07 +#define ACM_E_NOT_BIOS_ACM 0x08 +#define ACM_E_UUID_NOT_MATCH 0x09 +#define ACM_E_PLATFORM_IS_NOT_PROD 0x10 + +void intel_txt_log_bios_acm_error(void); +int intel_txt_log_acm_error(const uint32_t acm_error); +void intel_txt_log_spad(void); +bool intel_txt_memory_has_secrets(void); +int intel_txt_run_bios_acm(const u8 input_params); +bool intel_txt_prepare_txt_env(void); + +#endif /* SECURITY_INTEL_TXT_H_ */ diff --git a/src/security/intel/txt/txt_getsec.h b/src/security/intel/txt/txt_getsec.h new file mode 100644 index 0000000000..8e663d51b0 --- /dev/null +++ b/src/security/intel/txt/txt_getsec.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_INTEL_TXT_GETSEC_H_ +#define SECURITY_INTEL_TXT_GETSEC_H_ + +#include + +bool getsec_parameter(uint32_t *version_mask, + uint32_t *version_numbers_supported, + uint32_t *max_size_acm_area, + uint32_t *memory_type_mask, + uint32_t *senter_function_disable, + uint32_t *txt_feature_flags); + +bool getsec_capabilities(uint32_t *eax); + +void getsec_enteraccs(const uint32_t esi, + const uint32_t acm_base, + const uint32_t acm_size); + +#endif /* SECURITY_INTEL_TXT_REGISTER_H_ */ diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h new file mode 100644 index 0000000000..bbf0a7e72d --- /dev/null +++ b/src/security/intel/txt/txt_register.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SECURITY_INTEL_TXT_REGISTER_H_ +#define SECURITY_INTEL_TXT_REGISTER_H_ + +#include + +/* + * Document: 315168-016 + * Intel Trusted Execution Technology (Intel TXT) + * Software Development Guide + * Chapter B + */ +#define TXT_BASE 0xfed30000UL + +#define TXT_STS (TXT_BASE + 0) +#define TXT_ESTS (TXT_BASE + 8) +#define TXT_ESTS_TXT_RESET_STS (1 << 0) +/* + * Chapter 6 + * Intel Trusted Execution Technology Lab Handout + */ +#define TXT_ESTS_WAKE_ERROR_STS (1 << 6) + +#define TXT_ERROR (TXT_BASE + 0x30) +#define ACMERROR_TXT_VALID (1ul << 31) +#define ACMERROR_TXT_EXTERNAL (1ul << 30) + +#define ACMERROR_TXT_PROGRESS_SHIFT 16 +#define ACMERROR_TXT_MINOR_SHIFT 15 +#define ACMERROR_TXT_MAJOR_SHIFT 10 +#define ACMERROR_TXT_CLASS_SHIFT 4 +#define ACMERROR_TXT_TYPE_SHIFT 0 + +#define ACMERROR_TXT_PROGRESS_CODE (0xffull << ACMERROR_TXT_PROGRESS_SHIFT) +#define ACMERROR_TXT_MINOR_CODE (0x01ull << ACMERROR_TXT_MINOR_SHIFT) +#define ACMERROR_TXT_MAJOR_CODE (0x1full << ACMERROR_TXT_MAJOR_SHIFT) +#define ACMERROR_TXT_CLASS_CODE (0x3full << ACMERROR_TXT_CLASS_SHIFT) +#define ACMERROR_TXT_TYPE_CODE (0x0full << ACMERROR_TXT_TYPE_SHIFT) + +#define ACMERROR_TXT_AC_MODULE_TYPE_BIOS 0 +#define ACMERROR_TXT_AC_MODULE_TYPE_SINIT 1 + +#define TXT_ERROR_MASK (0x3ff << 0) + +#define TXT_CMD_RESET (TXT_BASE + 0x38) +#define TXT_CMD_CLOSE_PRIVATE (TXT_BASE + 0x48) + +/* Present in Document Number: 315168-016. */ +#define TXT_SPAD (TXT_BASE + 0xa0) +#define ACMSTS_IBB_MEASURED (1ull << 63) +#define ACMSTS_VERIFICATION_ERROR (1ull << 62) +#define ACMSTS_BG_STARTUP_ERROR (1ull << 61) /* CBnT platforms only */ +#define ACMSTS_TXT_DISABLED (1ull << 60) /* disabled by FIT type 0xA record */ +#define ACMSTS_BIOS_TRUSTED (1ull << 59) +#define ACMSTS_MEM_CLEAR_POWER_DOWN (1ull << 47) +#define ACMSTS_TXT_STARTUP_SUCCESS (1ull << 30) + +#define TXT_VER_FSBIF (TXT_BASE + 0x100) +#define TXT_VER_PRODUCTION_FUSED (1ull << 31) + +#define TXT_DIDVID (TXT_BASE + 0x110) + +/* + * Chapter 6 + * Intel Trusted Execution Technology Lab Handout + */ +#define TXT_CAPABILITIES (TXT_BASE + 0x200) +#define TXT_CAPABILITIES_DPR (1ull << 26) +#define TXT_CAPABILITIES_PMRC (1ull << 19) + +#define TXT_VER_QPIIF (TXT_BASE + 0x200) + +#define TXT_SINIT_BASE (TXT_BASE + 0x270) +#define TXT_SINIT_SIZE (TXT_BASE + 0x278) +#define TXT_MLE_JOIN (TXT_BASE + 0x290) + +#define TXT_HEAP_BASE (TXT_BASE + 0x300) +#define TXT_HEAP_SIZE (TXT_BASE + 0x308) +/* + * Chapter 6 + * Intel Trusted Execution Technology Lab Handout + */ +#define TXT_MSEG_BASE (TXT_BASE + 0x310) +#define TXT_MSEG_SIZE (TXT_BASE + 0x318) + +/* + * Chapter 5.4.2.1 + * Intel Trusted Execution Technology Lab Handout + */ +#define TXT_BIOSACM_ERRORCODE (TXT_BASE + 0x328) + +#define TXT_DPR (TXT_BASE + 0x330) + +#define TXT_ACM_KEY_HASH (TXT_BASE + 0x400) +#define TXT_ACM_KEY_HASH_LEN 0x4 + +#define TXT_E2STS (TXT_BASE + 0x8f0) +#define TXT_E2STS_SECRET_STS (1ull << 1) + +/* + * TXT Memory regions + * Chapter 5.3 + * Intel Trusted Execution Technology Lab Handout + */ +#define TXT_PRIVATE_SPACE 0xfed20000UL +#define TXT_PUBLIC_SPACE 0xfed30000UL +#define TXT_TPM_DECODE_AREA 0xfed40000UL +#define TXT_RESERVED_SPACE 0xfed50000UL + +#define TXT_RESERVED_SPACE_SIZE 0x3ffff + +/* ESI flags for GETSEC[ENTERACCS] see Reference Number: 323372-017 */ +#define ACMINPUT_SCLEAN 0 +#define ACMINPUT_RESET_TPM_AUXILIARY_INDICIES 2 +#define ACMINPUT_NOP 3 +#define ACMINPUT_SCHECK 4 +#define ACMINPUT_CLEAR_SECRETS 5 +#define ACMINPUT_LOCK_CONFIG 6 + +/* + * GetSec EAX value. + * SAFER MODE EXTENSIONS REFERENCE. + * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2 + * Order Number: 325383-060US + */ +#define IA32_GETSEC_CAPABILITIES 0 +#define IA32_GETSEC_ENTERACCS 2 +#define IA32_GETSEC_SENTER 4 +#define IA32_GETSEC_SEXIT 5 +#define IA32_GETSEC_PARAMETERS 6 +#define IA32_GETSEC_SMCTRL 7 +#define IA32_GETSEC_WAKEUP 8 + +#define GETSEC_PARAMS_TXT_EXT (1ul << 5) +#define GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT (1ul << 1) +#define GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK (1ul << 6) + +/* ACM defines */ +#define INTEL_ACM_VENDOR 0x00008086 + +#define ACM_FORMAT_FLAGS_PW 0x00000000 +#define ACM_FORMAT_FLAGS_NPW (1 << 14) +#define ACM_FORMAT_FLAGS_DEBUG (1 << 15) + +/* Old ACMs are power of two aligned, newer ACMs are not */ +#define ACM_FORMAT_SIZE_64KB (64 * KiB / 4) +#define ACM_FORMAT_SIZE_128KB (128 * KiB / 4) +#define ACM_FORMAT_SIZE_256KB (256 * KiB / 4) + +/* MSRs */ +#define IA32_MCG_STATUS 0x17a + +/* DPR register layout, either in PCI config space or TXT MMIO space */ +union dpr_register { + struct { + uint32_t lock : 1; /* [ 0.. 0] */ + uint32_t prs : 1; /* [ 1.. 1] and only present on PCI config */ + uint32_t epm : 1; /* [ 2.. 2] and only present on PCI config */ + uint32_t : 1; + uint32_t size : 8; /* [11.. 4] */ + uint32_t : 8; + uint32_t top : 12; /* [31..20] */ + }; + uint32_t raw; +}; + +typedef enum { + CHIPSET_ACM = 2, +} acm_module_type; + +typedef enum { + BIOS = 0, + SINIT = 1, +} acm_module_sub_type; + +/* + * ACM Header v0.0 without dynamic part + * Chapter A.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ +struct __packed acm_header_v0 { + uint16_t module_type; + uint16_t module_sub_type; + uint32_t header_len; + uint16_t header_version[2]; + uint16_t chipset_id; + uint16_t flags; + uint32_t module_vendor; + uint32_t date; + uint32_t size; + uint16_t txt_svn; + uint16_t se_svn; + uint32_t code_control; + uint32_t error_entry_point; + uint32_t gdt_limit; + uint32_t gdt_ptr; + uint32_t seg_sel; + uint32_t entry_point; + uint8_t reserved2[64]; + uint32_t key_size; + uint32_t scratch_size; + uint8_t rsa2048_pubkey[256]; + uint32_t pub_exp; + uint8_t rsa2048_sig[256]; + uint32_t scratch[143]; + uint8_t user_area[]; +}; + +struct __packed acm_info_table { + uint8_t uuid[16]; + uint8_t chipset_acm_type; + uint8_t version; + uint16_t length; + uint32_t chipset_id_list; + uint32_t os_sinit_data_ver; + uint32_t min_mle_hdr_ver; + uint32_t capabilities; + uint8_t acm_ver; + uint8_t reserved[3]; +}; + +/* + * Extended Data Elements + * Chapter C.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ +struct __packed txt_extended_data_element_header { + uint32_t type; + uint32_t size; + uint8_t data[0]; +}; + +#define HEAP_EXTDATA_TYPE_END 0 +#define HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1 +#define HEAP_EXTDATA_TYPE_ACM 2 +#define HEAP_EXTDATA_TYPE_CUSTOM 4 + +struct __packed txt_bios_spec_ver_element { + struct txt_extended_data_element_header header; + uint16_t ver_major; + uint16_t ver_minor; + uint16_t ver_revision; +}; + +struct __packed txt_heap_acm_element { + struct txt_extended_data_element_header header; + uint32_t num_acms; // must greater 0, smaller than 3 + uint64_t acm_addrs[2]; +}; + +/* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ +struct __packed txt_biosdataregion { + uint32_t version; + uint32_t bios_sinit_size; + uint64_t lcp_pd_base; + uint64_t lcp_pd_size; + uint32_t no_logical_procs; + uint32_t sinit_flags; + union { + uint32_t mle_flags; + struct { + uint32_t support_acpi_ppi : 1; + uint32_t platform_type : 2; + }; + }; + u8 extended_data_elements[0]; +}; + +void txt_dump_regions(void); +void txt_dump_chipset_info(void); +void txt_dump_acm_info(const struct acm_header_v0 *acm_header); + +#endif /* SECURITY_INTEL_TXT_REGISTER_H_ */ diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index 664e7c17a3..ff4cd1581b 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include +#include #include "memory.h" /** @@ -13,6 +14,9 @@ bool security_clear_dram_request(void) if (CONFIG(SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT)) return true; + if (CONFIG(INTEL_TXT) && intel_txt_memory_has_secrets()) + return true; + /* TODO: Add TEE environments here */ return false; diff --git a/src/security/memory/memory.h b/src/security/memory/memory.h index 442ace1189..c6ae4f8468 100644 --- a/src/security/memory/memory.h +++ b/src/security/memory/memory.h @@ -1,4 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - bool security_clear_dram_request(void); diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index a776a4db0a..e040d80611 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -41,7 +41,6 @@ void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, */ void tcpa_log_dump(void *unused); - /** * Ask vboot for a digest and extend a TPM PCR with it. * @param pcr sets the pcr index diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index f5c788c016..d9c62e1e14 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -165,7 +165,6 @@ int tspi_measure_cache_to_pcr(void) hash_alg = VB2_HASH_SHA256; } - printk(BIOS_DEBUG, "TPM: Write digests cached in TCPA log to PCR\n"); for (i = 0; i < tclt->num_entries; i++) { struct tcpa_entry *tce = &tclt->entries[i]; diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 30cd1cc3e9..a3d0235365 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -99,7 +99,6 @@ static uint32_t tlcl_send_receive_no_retry(const uint8_t *request, return result; } - /* Sends a TPM command and gets a response. Returns 0 if success or the TPM * error code if error. Waits for the self test to complete if needed. */ uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response, @@ -246,7 +245,6 @@ uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) return result; } - uint32_t tlcl_assert_physical_presence(void) { VBDEBUG("TPM: Asserting physical presence\n"); diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index 1f49f041f4..c5a5aaa187 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -15,7 +15,6 @@ #define kEncAuthLength 20 #define kPcrDigestLength 20 - /* * Conversion functions. to_tpm_TYPE puts a value of type TYPE into a TPM * command buffer. from_tpm_TYPE gets a value of type TYPE from a TPM command diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f31c7d0178..3efd5add40 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -18,18 +18,18 @@ static uint16_t tpm_tag; /* Depends on the command type. */ #define marshal_TPM_HANDLE(a, b) obuf_write_be32(a, b) #define marshal_TPMI_ALG_HASH(a, b) obuf_write_be16(a, b) -static int marshal_startup(struct obuf *ob, struct tpm2_startup *cmd_body) +static int marshal_startup(struct obuf *ob, const struct tpm2_startup *cmd_body) { return obuf_write_be16(ob, cmd_body->startup_type); } -static int marshal_shutdown(struct obuf *ob, struct tpm2_shutdown *cmd_body) +static int marshal_shutdown(struct obuf *ob, const struct tpm2_shutdown *cmd_body) { return obuf_write_be16(ob, cmd_body->shutdown_type); } static int marshal_get_capability(struct obuf *ob, - struct tpm2_get_capability *cmd_body) + const struct tpm2_get_capability *cmd_body) { int rc = 0; @@ -40,7 +40,7 @@ static int marshal_get_capability(struct obuf *ob, return rc; } -static int marshal_TPM2B(struct obuf *ob, TPM2B *data) +static int marshal_TPM2B(struct obuf *ob, const TPM2B *data) { int rc = 0; @@ -50,7 +50,7 @@ static int marshal_TPM2B(struct obuf *ob, TPM2B *data) return rc; } -static int marshal_TPMA_NV(struct obuf *ob, TPMA_NV *nv) +static int marshal_TPMA_NV(struct obuf *ob, const TPMA_NV *nv) { uint32_t v; @@ -58,7 +58,7 @@ static int marshal_TPMA_NV(struct obuf *ob, TPMA_NV *nv) return obuf_write_be32(ob, v); } -static int marshal_TPMS_NV_PUBLIC(struct obuf *ob, TPMS_NV_PUBLIC *nvpub) +static int marshal_TPMS_NV_PUBLIC(struct obuf *ob, const TPMS_NV_PUBLIC *nvpub) { int rc = 0; @@ -71,7 +71,7 @@ static int marshal_TPMS_NV_PUBLIC(struct obuf *ob, TPMS_NV_PUBLIC *nvpub) return rc; } -static int marshal_TPMT_HA(struct obuf *ob, TPMT_HA *tpmtha) +static int marshal_TPMT_HA(struct obuf *ob, const TPMT_HA *tpmtha) { int rc = 0; @@ -104,7 +104,7 @@ static int marshal_TPMT_HA(struct obuf *ob, TPMT_HA *tpmtha) } static int marshal_TPML_DIGEST_VALUES(struct obuf *ob, - TPML_DIGEST_VALUES *dvalues) + const TPML_DIGEST_VALUES *dvalues) { int i; int rc = 0; @@ -117,7 +117,7 @@ static int marshal_TPML_DIGEST_VALUES(struct obuf *ob, } static int marshal_session_header(struct obuf *ob, - struct tpm2_session_header *session_header) + const struct tpm2_session_header *session_header) { int rc = 0; struct obuf ob_sz; @@ -151,8 +151,8 @@ static int marshal_session_header(struct obuf *ob, * session_header structure. */ static int marshal_common_session_header(struct obuf *ob, - const uint32_t *handles, - size_t handle_count) + const uint32_t *handles, + size_t handle_count) { size_t i; struct tpm2_session_header session_header; @@ -171,7 +171,7 @@ static int marshal_common_session_header(struct obuf *ob, } static int marshal_nv_define_space(struct obuf *ob, - struct tpm2_nv_define_space_cmd *nvd_in) + const struct tpm2_nv_define_space_cmd *nvd_in) { const uint32_t handle[] = { TPM_RH_PLATFORM }; struct obuf ob_sz; @@ -198,10 +198,10 @@ static int marshal_nv_define_space(struct obuf *ob, } static int marshal_nv_write(struct obuf *ob, - struct tpm2_nv_write_cmd *command_body) + const struct tpm2_nv_write_cmd *command_body) { int rc = 0; - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= marshal_TPM2B(ob, &command_body->data.b); @@ -211,18 +211,18 @@ static int marshal_nv_write(struct obuf *ob, } static int marshal_nv_write_lock(struct obuf *ob, - struct tpm2_nv_write_lock_cmd *command_body) + const struct tpm2_nv_write_lock_cmd *command_body) { - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; return marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); } static int marshal_pcr_extend(struct obuf *ob, - struct tpm2_pcr_extend_cmd *command_body) + const struct tpm2_pcr_extend_cmd *command_body) { int rc = 0; - uint32_t handles[] = { command_body->pcrHandle }; + const uint32_t handles[] = { command_body->pcrHandle }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= marshal_TPML_DIGEST_VALUES(ob, &command_body->digests); @@ -231,10 +231,10 @@ static int marshal_pcr_extend(struct obuf *ob, } static int marshal_nv_read(struct obuf *ob, - struct tpm2_nv_read_cmd *command_body) + const struct tpm2_nv_read_cmd *command_body) { int rc = 0; - uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); rc |= obuf_write_be16(ob, command_body->size); @@ -252,13 +252,13 @@ static int marshal_clear(struct obuf *ob) } static int marshal_selftest(struct obuf *ob, - struct tpm2_self_test *command_body) + const struct tpm2_self_test *command_body) { return obuf_write_be8(ob, command_body->yes_no); } static int marshal_hierarchy_control(struct obuf *ob, - struct tpm2_hierarchy_control_cmd *command_body) + const struct tpm2_hierarchy_control_cmd *command_body) { int rc = 0; struct tpm2_session_header session_header; @@ -277,7 +277,7 @@ static int marshal_hierarchy_control(struct obuf *ob, } static int marshal_clear_control(struct obuf *ob, - struct tpm2_clear_control_cmd *command_body) + const struct tpm2_clear_control_cmd *command_body) { int rc = 0; struct tpm2_session_header session_header; @@ -294,10 +294,10 @@ static int marshal_clear_control(struct obuf *ob, return rc; } -static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body) +static int marshal_cr50_vendor_command(struct obuf *ob, const void *command_body) { int rc = 0; - uint16_t *sub_command = command_body; + const uint16_t *sub_command = command_body; switch (*sub_command) { case TPM2_CR50_SUB_CMD_IMMEDIATE_RESET: @@ -343,7 +343,7 @@ static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body) return rc; } -int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) +int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obuf *ob) { struct obuf ob_hdr; const size_t hdr_sz = sizeof(uint16_t) + 2 * sizeof(uint32_t); @@ -432,7 +432,7 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) } static int unmarshal_get_capability(struct ibuf *ib, - struct get_cap_response *gcr) + struct get_cap_response *gcr) { int i; int rc = 0; @@ -491,7 +491,7 @@ static int unmarshal_get_capability(struct ibuf *ib, } static int unmarshal_TPM2B_MAX_NV_BUFFER(struct ibuf *ib, - TPM2B_MAX_NV_BUFFER *nv_buffer) + TPM2B_MAX_NV_BUFFER *nv_buffer) { if (ibuf_read_be16(ib, &nv_buffer->t.size)) return -1; @@ -542,7 +542,7 @@ static int unmarshal_nv_read(struct ibuf *ib, struct nv_read_response *nvr) } static int unmarshal_vendor_command(struct ibuf *ib, - struct vendor_command_response *vcr) + struct vendor_command_response *vcr) { if (ibuf_read_be16(ib, &vcr->vc_subcommand)) return -1; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index 432cf5a382..ae0b7fdca5 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -21,7 +21,7 @@ * Returns 0 on success or -1 on error. * */ -int tpm_marshal_command(TPM_CC command, void *tpm_command_body, +int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obuf *ob); /** diff --git a/src/security/tpm/tss/vendor/cr50/Kconfig b/src/security/tpm/tss/vendor/cr50/Kconfig index f606459d65..52c73859d8 100644 --- a/src/security/tpm/tss/vendor/cr50/Kconfig +++ b/src/security/tpm/tss/vendor/cr50/Kconfig @@ -12,4 +12,11 @@ config POWER_OFF_ON_CR50_UPDATE help Power off machine while waiting for CR50 update to take effect. +config CR50_USE_LONG_INTERRUPT_PULSES + bool + default n + help + Whether to request longer interrupt pulses using Cr50 BOARD_CFG register. + If the Cr50 firmware is too old, it will not be able to honor the request. + endif diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index dadeddfb68..7730eccd29 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -40,7 +40,6 @@ enum cr50_tpm_mode { TPM_MODE_INVALID, }; - /** * CR50 specific tpm command to enable nvmem commits before internal timeout * expires. @@ -96,5 +95,4 @@ uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode); */ uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms); - #endif /* CR50_TSS_STRUCTURES_H_ */ diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 90b275660e..e92396d926 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -171,8 +171,9 @@ endif # All other files will be installed into RO and RW regions # Use $(sort) to cut down on extra spaces that would be translated to commas regions-for-file = $(subst $(spc),$(comma),$(sort \ - $(if $(filter \ - $(if $(filter y,$(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)), \ + $(if $(value regions-for-file-$(1)), \ + $(regions-for-file-$(1)), \ + $(if $(filter $(if $(filter y,$(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)), \ %/romstage,) \ mts \ %/verstage \ @@ -186,15 +187,15 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,\ $(if $(filter \ - $(call strip_quotes,$(CONFIG_RWA_REGION_ONLY)) \ - ,$(1)), FW_MAIN_A, \ + $(call strip_quotes,$(CONFIG_RWA_REGION_ONLY)) \ + ,$(1)), FW_MAIN_A, \ $(if $(filter \ $(call strip_quotes,$(CONFIG_RWB_REGION_ONLY)) \ ,$(1)), FW_MAIN_B, \ $(if $(filter \ $(call strip_quotes,$(CONFIG_RW_REGION_ONLY)) \ ,$(1)), $(RW_PARTITIONS), $(VBOOT_PARTITIONS) ) \ - ))))) + )))))) CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 5bd3922932..4f491db951 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 470102111e..c39af08f1b 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -87,5 +87,4 @@ static inline int vboot_logic_executed(void) } } - #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index ca7cedd168..783392c76d 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 1cddeeb5f3..87f382fb28 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include #include #include #include diff --git a/src/security/vboot/vboot_lib.c b/src/security/vboot/vboot_lib.c index 3ff1523c41..06fd6d7478 100644 --- a/src/security/vboot/vboot_lib.c +++ b/src/security/vboot/vboot_lib.c @@ -6,8 +6,8 @@ /* * vboot callbacks implemented by coreboot -- necessary for making general API - * calls when CONFIG_VBOOT_LIB is enabled. For callbacks specific to verstage - * (CONFIG_VBOOT), please see vboot_logic.c. + * calls when CONFIG(VBOOT_LIB) is enabled. For callbacks specific to verstage + * CONFIG(VBOOT), please see vboot_logic.c. */ void vb2ex_printf(const char *func, const char *fmt, ...) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index e23dcc4ed8..0f18f9a20f 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -208,7 +207,6 @@ static vb2_error_t hash_body(struct vb2_context *ctx, return VB2_SUCCESS; } - static uint32_t extend_pcrs(struct vb2_context *ctx) { return vboot_extend_pcr(ctx, 0, BOOT_MODE_PCR) || diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 2be9b9e25e..4ca6599536 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -25,13 +24,6 @@ void poweroff(void) halt(); } -static uint16_t reset_pm1_status(void) -{ - uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); - acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); - return pm1_sts; -} - static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { @@ -91,33 +83,76 @@ static void log_pm1_status(uint16_t pm1_sts) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); } -static void save_sws(uint16_t pm1_status) +static void log_gpe_events(const struct acpi_pm_gpe_state *state) { - struct soc_power_reg *sws; - uint32_t reg32; - uint16_t reg16; + int i; + uint32_t valid_gpe = state->gpe0_sts & state->gpe0_en; - sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); - if (sws == NULL) - return; - sws->pm1_sts = pm1_status; - sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); - reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); - acpi_write32(MMIO_ACPI_GPE0_STS, reg32); - sws->gpe0_sts = reg32; - sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); - reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); - reg16 &= SLP_TYP; - sws->wake_from = reg16 >> SLP_TYP_SHIFT; + for (i = 0; i <= 31; i++) { + if (valid_gpe & (1U << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); + } } -void acpi_clear_pm1_status(void) +void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state) { - uint16_t pm1_sts = reset_pm1_status(); + state->pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); + state->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); + state->gpe0_sts = acpi_read32(MMIO_ACPI_GPE0_STS); + state->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); + state->previous_sx_state = acpi_get_sleep_type(); + state->aligning_field = 0; +} - save_sws(pm1_sts); - log_pm1_status(pm1_sts); - print_pm1_status(pm1_sts); +void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state) +{ + log_pm1_status(state->pm1_sts); + print_pm1_status(state->pm1_sts); + log_gpe_events(state); +} + +void acpi_clear_pm_gpe_status(void) +{ + acpi_write16(MMIO_ACPI_PM1_STS, acpi_read16(MMIO_ACPI_PM1_STS)); + acpi_write32(MMIO_ACPI_GPE0_STS, acpi_read32(MMIO_ACPI_GPE0_STS)); +} + +static int get_index_bit(uint32_t value, uint16_t limit) +{ + uint16_t i; + uint32_t t; + + if (limit >= TOTAL_BITS(uint32_t)) + return -1; + + /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ + t = (1 << limit) - 1; + if ((value & t) == 0) + return -1; + t = 1; + for (i = 0; i < limit; i++) { + if (value & t) + break; + t <<= 1; + } + return i; +} + +void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state) +{ + int index; + + index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); + if (index < 0) + gnvs->pm1i = ~0ULL; + else + gnvs->pm1i = index; + + index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); + if (index < 0) + gnvs->gpei = ~0ULL; + else + gnvs->gpei = index; } int acpi_get_sleep_type(void) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index b9646b9412..74ea696448 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -3,12 +3,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include static int get_gpio_gevent(uint8_t gpio, const struct soc_amd_event *table, size_t items) @@ -28,7 +30,7 @@ static void program_smi(uint32_t flags, int gevent_num) if (!is_gpio_event_level_triggered(flags)) { printk(BIOS_ERR, "ERROR: %s - Only level trigger allowed for SMI!\n", __func__); - assert(0); + BUG(); return; } @@ -212,10 +214,9 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) soc_gpio_hook(gpio, mux); - /* Clear interrupt and wake status (write 1-to-clear bits) */ - control |= GPIO_INT_STATUS | GPIO_WAKE_STATUS; __gpio_setbits32(gpio, PAD_CFG_MASK, control); - + /* Clear interrupt and wake status (write 1-to-clear bits) */ + __gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); if (control_flags == 0) continue; @@ -298,3 +299,72 @@ void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, program_gpios(c, 1); } } + +static void check_and_add_wake_gpio(int begin, int end, struct gpio_wake_state *state) +{ + int i; + uint32_t reg; + + for (i = begin; i < end; i++) { + reg = gpio_read32(i); + if (!(reg & GPIO_WAKE_STATUS)) + continue; + printk(BIOS_INFO, "GPIO %d woke system.\n", i); + if (state->num_valid_wake_gpios >= ARRAY_SIZE(state->wake_gpios)) + continue; + state->wake_gpios[state->num_valid_wake_gpios++] = i; + } +} + +static void check_gpios(uint32_t wake_stat, int bit_limit, int gpio_base, + struct gpio_wake_state *state) +{ + int i; + int begin; + int end; + + for (i = 0; i < bit_limit; i++) { + if (!(wake_stat & BIT(i))) + continue; + begin = gpio_base + i * 4; + end = begin + 4; + /* There is no gpio 63. */ + if (begin == 60) + end = 63; + check_and_add_wake_gpio(begin, end, state); + } +} + +void gpio_fill_wake_state(struct gpio_wake_state *state) +{ + /* Turn the wake registers into "gpio" index to conform to existing API. */ + const uint8_t stat0 = GPIO_WAKE_STAT_0 / sizeof(uint32_t); + const uint8_t stat1 = GPIO_WAKE_STAT_1 / sizeof(uint32_t); + const uint8_t control_switch = GPIO_MASTER_SWITCH / sizeof(uint32_t); + + /* Register fields and gpio availability need to be confirmed on other chipsets. */ + if (!CONFIG(SOC_AMD_PICASSO)) + dead_code(); + + memset(state, 0, sizeof(*state)); + + state->control_switch = gpio_read32(control_switch); + state->wake_stat[0] = gpio_read32(stat0); + state->wake_stat[1] = gpio_read32(stat1); + + printk(BIOS_INFO, "GPIO Control Switch: 0x%08x, Wake Stat 0: 0x%08x, Wake Stat 1: 0x%08x\n", + state->control_switch, state->wake_stat[0], state->wake_stat[1]); + + check_gpios(state->wake_stat[0], 32, 0, state); + check_gpios(state->wake_stat[1], 14, 128, state); +} + +void gpio_add_events(const struct gpio_wake_state *state) +{ + int i; + int end; + + end = MIN(state->num_valid_wake_gpios, ARRAY_SIZE(state->wake_gpios)); + for (i = 0; i < end; i++) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, state->wake_gpios[i]); +} diff --git a/src/soc/amd/common/block/graphics/Kconfig b/src/soc/amd/common/block/graphics/Kconfig index 8aa2a20a3c..4cda353c5f 100644 --- a/src/soc/amd/common/block/graphics/Kconfig +++ b/src/soc/amd/common/block/graphics/Kconfig @@ -3,3 +3,11 @@ config SOC_AMD_COMMON_BLOCK_GRAPHICS default n help Select this option to use AMD common graphics driver support. + +config SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF + bool + depends on SOC_AMD_COMMON_BLOCK_GRAPHICS + help + Select this option to provide ATIF method with display brightness querying. + Currently, the exported values only open up 0-255 as the brightness range for + the display. diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 466a91c666..24cabfe454 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -1,13 +1,114 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include +#define ATIF_FUNCTION_VERIFY_INTERFACE 0x0 +struct atif_verify_interface_output { + uint16_t size; /* Size of this object, including size field */ + uint16_t version; + uint32_t supported_notifications; + uint32_t supported_functions; /* Bit n set if function n+1 supported. */ +}; + +#define ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS 0x10 +# define ATIF_QBTC_REQUEST_LCD1 0 +/* error codes */ +# define ATIF_QBTC_ERROR_CODE_SUCCESS 0 +# define ATIF_QBTC_ERROR_CODE_FAILURE 1 +# define ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED 2 +struct atif_brightness_input { + uint16_t size; + /* ATIF doc indicates this field is a word, but the kernel drivers uses a byte. */ + uint8_t requested_display; +}; +struct atif_brightness_output { + uint16_t size; /* Size of this object, including size field. */ + uint16_t flags; /* Currently all reserved. */ + uint8_t error_code; + /* default brightness fields currently ignored by Linux driver. */ + uint8_t default_brightness_ac; /* Percentage brightness when connected to AC. */ + uint8_t default_brightness_dc; /* Percentage brightness when connected to DC. */ + /* The following 2 fields are the only ones honored by Linux driver currently. */ + uint8_t min_input_signal_level; /* 0-255 corresponding to 0% */ + uint8_t max_input_signal_level; /* 0-255 corresponding to 100% */ + /* Array of data points consisting of: + * { uint8_t luminance_level; (percent) + * uint8_t input_signal_level; (0-255 in value) } + * Linux ignores these fields so no support currently. */ + uint8_t count_data_points; /* Count of data points. */ +}; + +static void generate_atif(const struct device *dev) +{ + struct atif_verify_interface_output verify_output = { + .size = sizeof(verify_output), + .version = 1, + .supported_functions = + BIT(ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS - 1), + }; + struct atif_brightness_output brightness_error = { + .size = sizeof(brightness_error), + .error_code = ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED, + }; + struct atif_brightness_output brightness_out = { + .size = sizeof(brightness_out), + .error_code = ATIF_QBTC_ERROR_CODE_SUCCESS, + .min_input_signal_level = 0, + .max_input_signal_level = 255, + }; + + /* Scope (\_SB.PCI0.PBRA.IGFX) */ + acpigen_write_scope(acpi_device_path(dev)); + /* Method (ATIF, 2, NotSerialized) */ + acpigen_write_method("ATIF", 2); + /* ToInteger (Arg0, Local0) */ + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + + /* If ((Local0 == Zero)) */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, ATIF_FUNCTION_VERIFY_INTERFACE); + /* Return (Buffer (0x0C) { ... } */ + acpigen_write_return_byte_buffer((uint8_t *)(void *)&verify_output, + sizeof(verify_output)); + acpigen_pop_len(); /* if (LEqual(Local0, 0) */ + + /* ElseIf ((Local0 == 0x10)) */ + acpigen_write_else(); + acpigen_write_if_lequal_op_int(LOCAL0_OP, + ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS); + /* CreateByteField (Arg1, 0x02, DISP) */ + acpigen_write_create_byte_field(ARG1_OP, + offsetof(struct atif_brightness_input, requested_display), "DISP"); + /* ToInteger (DISP, Local1) */ + acpigen_write_to_integer_from_namestring("DISP", LOCAL1_OP); + /* If ((Local1 == Zero)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, ATIF_QBTC_REQUEST_LCD1); + /* Return (Buffer (0x0A) { ... } */ + acpigen_write_return_byte_buffer((uint8_t *)(void *)&brightness_out, + sizeof(brightness_out)); + acpigen_pop_len(); /* if (LEqual(Local2, ATIF_QBTC_REQUEST_LCD1) */ + /* Else */ + acpigen_write_else(); + /* Return (Buffer (0x0A) */ + acpigen_write_return_byte_buffer((uint8_t *)(void *)&brightness_error, + sizeof(brightness_error)); + acpigen_pop_len(); /* else */ + + acpigen_pop_len(); /* if (LEqual(Local0, 0x10) */ + acpigen_pop_len(); /* else */ + + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ +} + static void graphics_fill_ssdt(const struct device *dev) { acpi_device_write_pci_dev(dev); pci_rom_ssdt(dev); + if (CONFIG(SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF)) + generate_atif(dev); } static const char *graphics_acpi_name(const struct device *dev) diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 4d227350fa..b6244cb70d 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -4,6 +4,7 @@ #define __AMDBLOCKS_ACPI_H__ #include +#include /* ACPI MMIO registers 0xfed80800 */ #define MMIO_ACPI_PM1_STS 0x00 @@ -16,7 +17,24 @@ #define MMIO_ACPI_GPE0_STS 0x14 #define MMIO_ACPI_GPE0_EN 0x18 -void acpi_clear_pm1_status(void); +/* Structure to maintain standard ACPI register state for reporting purposes. */ +struct acpi_pm_gpe_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint16_t previous_sx_state; + uint16_t aligning_field; +}; + +/* Fill object with the ACPI PM and GPE state. */ +void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state); +/* Save events to eventlog log and also print information on console. */ +void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state); +/* Clear PM and GPE status registers. */ +void acpi_clear_pm_gpe_status(void); +/* Fill GNVS object from PM GPE object. */ +void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state); /* * If a system reset is about to be requested, modify the PM1 register so it diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 8883893e52..f30fba39b1 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -25,7 +25,6 @@ AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); void *agesawrapper_getlateinitptr(int pick); - void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); void amd_initcpuio(void); const void *agesawrapper_locate_module(const char name[8]); diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 7a9638d935..d5ef5d2bd3 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -3,9 +3,7 @@ #ifndef __AMDBLOCK_GPIO_BANKS_H__ #define __AMDBLOCK_GPIO_BANKS_H__ -#include -#include -#include +#include struct soc_amd_gpio { uint8_t gpio; @@ -22,6 +20,23 @@ struct soc_amd_event { #define GPIO_MASTER_SWITCH 0xFC #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) +#define GPIO_WAKE_EN BIT(31) + +#define GPIO_WAKE_STAT_0 0x2F0 +#define GPIO_WAKE_STAT_1 0x2F4 +struct gpio_wake_state { + uint32_t control_switch; + uint32_t wake_stat[2]; + /* Number of wake_gpio with a valid setting. */ + uint32_t num_valid_wake_gpios; + /* GPIO index number that caused a wake. */ + uint8_t wake_gpios[16]; +}; + +/* Fill gpio_wake_state object for future event reporting. */ +void gpio_fill_wake_state(struct gpio_wake_state *state); +/* Add gpio events to the eventlog. */ +void gpio_add_events(const struct gpio_wake_state *state); #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ @@ -54,7 +69,7 @@ struct soc_amd_event { #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) #define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_STATUS_DELIVERY) + (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) #define GPIO_INT_ENABLE_MASK (3 << 11) #define GPIO_S0I3_WAKE_EN (1 << 13) @@ -121,7 +136,6 @@ enum { #define AMD_GPIO_MUX_MASK 0x03 - /* * Flags used for GPIO configuration. These provide additional information that does not go * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index d226e0c05d..b0080dae8e 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -3,6 +3,8 @@ #ifndef __AMDBLOCKS_SPI_H__ #define __AMDBLOCKS_SPI_H__ +#include + #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) @@ -94,4 +96,16 @@ void fch_spi_early_init(void); */ void fch_spi_config_modes(void); +/* Set the SPI base address variable */ +void spi_set_base(void *base); + +/* Get the SPI base address variable's value */ +uintptr_t spi_get_bar(void); +uint8_t spi_read8(uint8_t reg); +uint16_t spi_read16(uint8_t reg); +uint32_t spi_read32(uint8_t reg); +void spi_write8(uint8_t reg, uint8_t val); +void spi_write16(uint8_t reg, uint16_t val); +void spi_write32(uint8_t reg, uint32_t val); + #endif /* __AMDBLOCKS_SPI_H__ */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 29028a4b72..0878fb7663 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -24,37 +24,37 @@ static uintptr_t espi_get_bar(void) return espi_bar; } -static uint32_t espi_read32(int reg) +static uint32_t espi_read32(unsigned int reg) { return read32((void *)(espi_get_bar() + reg)); } -static void espi_write32(int reg, uint32_t val) +static void espi_write32(unsigned int reg, uint32_t val) { write32((void *)(espi_get_bar() + reg), val); } -static uint16_t espi_read16(int reg) +static uint16_t espi_read16(unsigned int reg) { return read16((void *)(espi_get_bar() + reg)); } -static void espi_write16(int reg, uint16_t val) +static void espi_write16(unsigned int reg, uint16_t val) { write16((void *)(espi_get_bar() + reg), val); } -static uint8_t espi_read8(int reg) +static uint8_t espi_read8(unsigned int reg) { return read8((void *)(espi_get_bar() + reg)); } -static void espi_write8(int reg, uint8_t val) +static void espi_write8(unsigned int reg, uint8_t val) { write8((void *)(espi_get_bar() + reg), val); } -static void espi_enable_decode(int decode_en) +static void espi_enable_decode(uint32_t decode_en) { uint32_t val; @@ -63,7 +63,7 @@ static void espi_enable_decode(int decode_en) espi_write32(ESPI_DECODE, val); } -static bool espi_is_decode_enabled(int decode) +static bool espi_is_decode_enabled(uint32_t decode) { uint32_t val; @@ -104,29 +104,24 @@ static int espi_get_unused_io_window(void) */ static int espi_std_io_decode(uint16_t base, size_t size) { - int ret = -1; + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; if (size != 1) - return ret; + return -1; switch (base) { case 0x80: - ret = ESPI_DECODE_IO_0x80_EN; - break; + return ESPI_DECODE_IO_0x80_EN; case 0x60: case 0x64: - ret = ESPI_DECODE_IO_0X60_0X64_EN; - break; + return ESPI_DECODE_IO_0X60_0X64_EN; case 0x2e: case 0x2f: - ret = ESPI_DECODE_IO_0X2E_0X2F_EN; - break; + return ESPI_DECODE_IO_0X2E_0X2F_EN; default: - ret = -1; - break; + return -1; } - - return ret; } static size_t espi_get_io_window_size(int idx) @@ -188,9 +183,9 @@ int espi_open_io_window(uint16_t base, size_t size) if (std_io != -1) { espi_enable_decode(std_io); return 0; + } else { + return espi_open_generic_io_window(base, size); } - - return espi_open_generic_io_window(base, size); } static int espi_find_mmio_window(uint32_t win_base) @@ -411,7 +406,7 @@ static void espi_clear_status(void) * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a * command. */ -static int espi_check_status(uint32_t *status) +static int espi_poll_status(uint32_t *status) { struct stopwatch sw; @@ -462,8 +457,8 @@ static int espi_send_command(const struct espi_cmd *cmd) return -1; } - if (espi_check_status(&status) == -1) { - espi_show_failure(cmd, "Error: eSPI check status failed", 0); + if (espi_poll_status(&status) == -1) { + espi_show_failure(cmd, "Error: eSPI poll status failed", 0); return -1; } @@ -475,7 +470,8 @@ static int espi_send_command(const struct espi_cmd *cmd) } if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { - espi_show_failure(cmd, "Error: eSPI status register bits set", status); + espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", + status); return -1; } diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index deadfa2a77..107aa4af23 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -166,7 +166,6 @@ static void configure_child_lpc_windows(struct device *dev, struct device *child reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* * Be a bit relaxed, tolerate that LPC region might be bigger than * resource we try to fit, do it like this for all regions < 16 bytes. diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 6f7ad7259d..699bb53431 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index f919668190..92b0cc6de3 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -9,6 +9,8 @@ #include #include #include +#include + #include "psp_def.h" #define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 3752384c84..2094931dca 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -25,14 +25,10 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) size_t size; int i; uint32_t erased = 0xffffffff; - struct region_device rdev; - if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, - &rdev)) - reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - - base = rdev_mmap_full(&rdev); - size = region_device_sz(&rdev); + base = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + DEFAULT_MRC_VERSION, + &size); if (!base || !size) reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 785e6da6b3..c8f6d1ecf9 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -9,3 +9,46 @@ config SOC_AMD_COMMON_BLOCK_SPI config SOC_AMD_COMMON_BLOCK_SPI_DEBUG bool default n + +config EFS_SPI_READ_MODE + int + range 0 7 + default 2 + help + SPI read mode to be programmed by the PSP. + The numbers in the options below indicate how many wires + are utilized for command, address and data. For instance 1-1-2 + means 1 command, 1 address and 2 data wires. + 0: Normal Read (up to 33M) + 1: Reserved + 2: Dual IO (1-1-2) + 3: Quad IO (1-1-4) + 4: Dual IO (1-2-2) + 5: Quad IO (1-4-4) + 6: Normal Read (up to 66M) + 7: Fast Read + +config EFS_SPI_SPEED + int + range 0 5 + default 0 + help + SPI Fast Speed to be programmed by the PSP. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config EFS_SPI_MICRON_FLAG + int + range 0 2 + default 0 + help + For Family 17h Model 00h and later SoC the PSP must be aware if a Micron + part is present in EFS. Automatic detection (option 2) is available + for Family 17h Model 30h-3Fh but is unsupported otherwise. + 0: Board does not use Micron parts + 1: Board always uses Micron parts + 2: Micron parts are optional diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 3d541b7052..c8b733fe04 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -18,4 +18,11 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-y += fch_spi.c endif -endif +bootblock-y += fch_spi_util.c +romstage-y += fch_spi_util.c +postcar-y += fch_spi_util.c +ramstage-y += fch_spi_util.c +verstage-y += fch_spi_util.c +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index bf64c3f260..c39147a8b3 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -8,43 +8,24 @@ #include #include -static uintptr_t fch_spi_base(void) -{ - uintptr_t base; - - base = lpc_get_spibase(); - - if (base) - return base; - - lpc_set_spibase(SPI_BASE_ADDRESS); - lpc_enable_spi_rom(SPI_ROM_ENABLE); - - return SPI_BASE_ADDRESS; -} - static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) { - uintptr_t base = fch_spi_base(); - - write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm)); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100); } static void fch_spi_disable_4dw_burst(void) { - uintptr_t base = fch_spi_base(); - uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + uint16_t val = spi_read16(SPI100_HOST_PREF_CONFIG); - write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); + spi_write16(SPI100_HOST_PREF_CONFIG, val & ~SPI_RD4DW_EN_HOST); } static void fch_spi_set_read_mode(u32 mode) { - uintptr_t base = fch_spi_base(); - uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + uint32_t val = spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK; - write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); + spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode)); } static void fch_spi_config_mb_modes(void) @@ -77,7 +58,6 @@ void fch_spi_config_modes(void) void fch_spi_early_init(void) { - lpc_set_spibase(SPI_BASE_ADDRESS); lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_prefetch(); fch_spi_disable_4dw_burst(); diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 13ad0cd32d..565fdbe149 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -9,6 +8,7 @@ #include #include #include +#include #define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */ #define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) @@ -30,28 +30,6 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static uint32_t spibar; - -static inline uint8_t spi_read8(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline uint32_t spi_read32(uint8_t reg) -{ - return read32((void *)(spibar + reg)); -} - -static inline void spi_write8(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static inline void spi_write32(uint8_t reg, uint32_t val) -{ - write32((void *)(spibar + reg), val); -} - static void dump_state(const char *str, u8 phase) { u8 dump_size; @@ -64,7 +42,7 @@ static void dump_state(const char *str, u8 phase) printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); - addr = spibar + SPI_FIFO; + addr = spi_get_bar() + SPI_FIFO; if (phase == 0) { dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); @@ -111,8 +89,7 @@ static int execute_command(void) void spi_init(void) { - spibar = lpc_get_spibase(); - printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, spibar); + printk(BIOS_DEBUG, "%s: SPI BAR at 0x%08lx\n", __func__, spi_get_bar()); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c new file mode 100644 index 0000000000..5cef565baf --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi_util.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static uintptr_t spi_base; + +void spi_set_base(void *base) +{ + spi_base = (uintptr_t)base; +} + +uintptr_t spi_get_bar(void) +{ + if (ENV_X86 && !spi_base) + spi_set_base((void *)lpc_get_spibase()); + ASSERT(spi_base); + + return spi_base; +} + +uint8_t spi_read8(uint8_t reg) +{ + return read8((void *)(spi_get_bar() + reg)); +} + +uint16_t spi_read16(uint8_t reg) +{ + return read16((void *)(spi_get_bar() + reg)); +} + +uint32_t spi_read32(uint8_t reg) +{ + return read32((void *)(spi_get_bar() + reg)); +} + +void spi_write8(uint8_t reg, uint8_t val) +{ + write8((void *)(spi_get_bar() + reg), val); +} + +void spi_write16(uint8_t reg, uint16_t val) +{ + write16((void *)(spi_get_bar() + reg), val); +} + +void spi_write32(uint8_t reg, uint32_t val) +{ + write32((void *)(spi_get_bar() + reg), val); +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3bdaad22c0..6a5b93244d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER @@ -53,7 +52,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA - select FSP_USES_CB_STACK select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS @@ -244,6 +242,24 @@ config EHCI_BAR hex default 0xfef00000 +config PICASSO_FCH_IOAPIC_ID + hex + default 0x8 + help + The Picasso APU has two IOAPICs, one in the FCH and one in the + northbridge. Set this value for the intended ID to assign to the + FCH IOAPIC. The value should be >= MAX_CPUS and different from + the GNB's IOAPIC_ID. + +config PICASSO_GNB_IOAPIC_ID + hex + default 0x9 + help + The Picasso APU has two IOAPICs, one in the FCH and one in the + northbridge. Set this value for the intended ID to assign to the + GNB IOAPIC. The value should be >= MAX_CPUS and different from + the FCH's IOAPIC_ID. + config SERIRQ_CONTINUOUS_MODE bool default n @@ -271,7 +287,7 @@ config PICASSO_CONSOLE_UART 2: 0xfedc3000 3: 0xfedcf000 -choice PICASSO_UART_CLOCK_SOURCE +choice prompt "UART Frequency" depends on PICASSO_CONSOLE_UART default PICASSO_UART_48MZ @@ -291,12 +307,10 @@ endchoice config PICASSO_UART_LEGACY bool "Decode legacy I/O range" - depends on PICASSO_CONSOLE_UART # TODO: shouldn't depend on this help - Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may - decode legacy addresses and this option enables the one used for the - console. A UART accessed with I/O does not allow all the features - of MMIO. The MMIO decode is still present when this option is used. + Assign I/O 3F8, 2F8, etc. to a Picasso UART. A UART accessed with I/O + does not allow all the features of MMIO. The MMIO decode is still + present when this option is used. config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && PICASSO_CONSOLE_UART @@ -321,7 +335,7 @@ config SMM_MODULE_STACK_SIZE config ACPI_CPU_STRING string - default "\\_PR.C%03d" + default "\\_SB.C%03d" config ACPI_BERT bool "Build ACPI BERT Table" @@ -339,6 +353,14 @@ config ACPI_BERT_SIZE Specify the amount of DRAM reserved for gathering the data used to generate the ACPI table. +config ACPI_SSDT_PSD_INDEPENDENT + bool "Allow core p-state independent transitions" + default y + help + AMD recommends the ACPI _PSD object to be configured to cause + cores to transition between p-states independently. A vendor may + choose to generate _PSD object to allow cores to transition together. + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select ALWAYS_LOAD_OPROM @@ -377,7 +399,6 @@ config MAINBOARD_POWER_RESTORE config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK default 0x40000 help The amount of coreboot-allocated heap and stack usage by the FSP. @@ -429,7 +450,7 @@ config AMD_PUBKEY_FILE string default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" -config USE_PSPSCUREOS +config USE_PSPSECUREOS bool default y help @@ -492,12 +513,25 @@ config PSP_UNLOCK_SECURE_DEBUG help Select this item to enable secure debug options in PSP. -endmenu +config PSP_VERSTAGE_FILE + string "Specify the PSP_verstage file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "$(obj)/psp_verstage.bin" + help + Add psp_verstage file to the build & PSP Directory Table +config PSP_VERSTAGE_SIGNING_TOKEN + string "Specify the PSP_verstage Signature Token file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "" + help + Add psp_verstage signature token to the build & PSP Directory Table + +endmenu config VBOOT select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH if ! VBOOT_STARTS_BEFORE_BOOTBLOCK + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config VBOOT_STARTS_BEFORE_BOOTBLOCK def_bool n @@ -507,6 +541,18 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD. +config CMOS_RECOVERY_BYTE + hex + default 0x51 + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + help + If the workbuf is not passed from the PSP to coreboot, set the + recovery flag and reboot. The PSP will read this byte, mark the + recovery request in VBNV, and reset the system into recovery mode. + + This is the byte before the default first byte used by VBNV + (0x26 + 0x0E - 1) + if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b3af1fd1a8..9757160d19 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -22,6 +22,9 @@ bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c +bootblock-y += pmutil.c +bootblock-y += reset.c +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c @@ -97,6 +100,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) @@ -129,7 +133,7 @@ ifeq ($(CONFIG_PSP_BOOTLOADER_FILE),) $(error CONFIG_PSP_BOOTLOADER_FILE was not defined) endif PSPBTLDR_FILE=$(realpath $(call strip_quotes, $(CONFIG_PSP_BOOTLOADER_FILE))) -$(info Adding PSP $(shell md5sum $(PSPBTLDR_FILE))) +$(info Adding PSP $(shell dd if=$(PSPBTLDR_FILE) | md5sum)) # types = 0x8 and 0x12 PSP_SMUFW1_SUB1_FILE=$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin @@ -147,9 +151,9 @@ PSP_SOFTFUSE_BITS += 0 PSP_TOKEN_UNLOCK="--token-unlock" endif -ifeq ($(CONFIG_USE_PSPSCUREOS),y) +ifeq ($(CONFIG_USE_PSPSECUREOS),y) # types = 0x2 -PSPSCUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPSECUREOS_FILE=$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin endif # type = 0x21 @@ -197,7 +201,7 @@ endif # # type = 0x60 -PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin) +PSP_APCB_FILES=$(APCB_SOURCES) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -212,17 +216,9 @@ PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) # type = 0x63 - construct APOB NV base/size from flash map -# TODO(b/157068645): Add ability to fmaptool to extract offsets and sizes -# This code currently assumes the following FMAP structure. If -# the UNIFIED_MRC_CACHE region is present, it must have a 0 offset. -# FLASH@* { -# BIOS@* { -# RW_MRC_CACHE@* { -_FLASH_BASE=$(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) -_GET_FLASH_BASE=grep "FLASH" | sed 's/.*FLASH@//' | sed 's/ .*//' -_GET_BIOS_REG_BASE=grep "BIOS" | sed 's/.*BIOS@//' | sed 's/ .*//' -_GET_APOBNV_BASE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/ .*//' -_GET_APOBNV_SIZE=grep "RW_MRC_CACHE" | sed 's/.*@//' | sed 's/.* //' +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') +APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') # type2 = 0x64, 0x65 PSP_PMUI_FILE1=$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin @@ -248,15 +244,10 @@ PSP_SHAREDMEM_BASE=$(shell printf "0x%s" $(_PSP_SHAREDMEM_BASE)) endif # type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(obj)/psp_verstage.bin +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK -APOB_NV_SIZE=$(shell printf "0x%x" $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_SIZE))) -APOB_NV_BASE=$(shell printf "0x%x" $(call int-add, \ - $(shell cat $(obj)/fmap.fmd | $(_GET_FLASH_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_BIOS_REG_BASE)) \ - $(shell cat $(obj)/fmap.fmd | $(_GET_APOBNV_BASE)))) - # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 @@ -281,7 +272,7 @@ OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogra OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) OPT_TOKEN_UNLOCK=$(call add_opt_prefix, $(PSP_TOKEN_UNLOCK), "") OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) +OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) @@ -300,6 +291,7 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ @@ -322,10 +314,17 @@ OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +ifeq ($(CONFIG_VBOOT),) +OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) +OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) +endif AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPSECUREOS_FILE) \ $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_SMUFW1_SUB2_FILE) \ $(OPT_SMUFW2_SUB2_FILE) \ @@ -333,8 +332,6 @@ AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ @@ -365,59 +362,19 @@ AMDFW_COMMON_ARGS=$(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSP_S0I3_FILE) \ $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ - $(OPT_VERSTAGE_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) -# Copy prebuild APCBs if they exist -$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin - cp $< $@ - -# APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin - -$(obj)/APCB_empty.bin: $(APCB_MAGIC_BLOB) $(APCB_EDIT_TOOL) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - -$(obj)/APCB_%_x1.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --hex \ - --spd_0_0 $< \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - -$(obj)/APCB_%_x2.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) - $(APCB_EDIT_TOOL) \ - $(APCB_MAGIC_BLOB) \ - $@ \ - --hex \ - --spd_0_0 $< \ - --spd_1_0 $< \ - --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ - --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ - --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ - --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ - $(call strip_quotes, $(PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(PSPSECUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(call strip_quotes, $(PSP_PMUI_FILE1)) \ @@ -449,13 +406,20 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ $(AMDFWTOOL) \ - $(obj)/fmap.fmd + $(obj)/fmap_config.h + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ --output $@ @@ -470,6 +434,8 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ --anywhere \ --output $@ @@ -479,6 +445,8 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ --anywhere \ --output $@ diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 8e6f4cfbbb..9ee29551d4 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -45,7 +45,7 @@ static void init(struct device *dev) /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable); if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) sb_clk_output_48Mhz(); /* Internal connection to I2S */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8062cfa098..17940e9725 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -49,9 +51,11 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ @@ -88,6 +92,8 @@ unsigned long acpi_fill_madt(unsigned long current) */ void acpi_fill_fadt(acpi_fadt_t *fadt) { + const struct soc_amd_picasso_config *cfg = config_of_soc(); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ @@ -112,20 +118,20 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alarm work */ - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0; + fadt->century = 0x32; + fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON; + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ @@ -147,7 +153,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -155,7 +160,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; @@ -164,20 +168,220 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.addrh = 0x0; } +static uint32_t get_pstate_core_freq(msr_t pstate_def) +{ + uint32_t core_freq, core_freq_mul, core_freq_div; + bool valid_freq_divisor; + + /* Core frequency multiplier */ + core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; + + /* Core frequency divisor ID */ + core_freq_div = + (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; + + if (core_freq_div == 0) { + return 0; + } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN) + && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) { + /* Allow 1/8 integer steps for this range */ + valid_freq_divisor = 1; + } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX) + && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { + /* Only allow 1/4 integer steps for this range */ + valid_freq_divisor = 1; + } else { + valid_freq_divisor = 0; + } + + if (valid_freq_divisor) { + /* 25 * core_freq_mul / (core_freq_div / 8) */ + core_freq = + ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); + } else { + printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", + core_freq_div); + core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul); + } + return core_freq; +} + +static uint32_t get_pstate_core_power(msr_t pstate_def) +{ + uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; + + /* Core voltage ID */ + core_vid = + (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; + + /* Current value in amps */ + current_value_amps = + (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; + + /* Current divisor */ + current_divisor = + (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; + + /* Voltage */ + if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { + /* Voltage off for VID codes 0xF8 to 0xFF */ + voltage_in_uvolts = 0; + } else { + voltage_in_uvolts = + SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + } + + /* Power in mW */ + power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps; + + switch (current_divisor) { + case 0: + break; + case 1: + power_in_mw = power_in_mw / 10L; + break; + case 2: + power_in_mw = power_in_mw / 100L; + break; + case 3: + /* current_divisor is set to an undefined value.*/ + printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n"); + power_in_mw = 0; + break; + } + + return power_in_mw; +} + +/* + * Populate structure describing enabled p-states and return count of enabled p-states. + */ +static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) +{ + msr_t pstate_def; + size_t pstate_count, pstate; + uint32_t pstate_enable, max_pstate; + + pstate_count = 0; + max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; + + for (pstate = 0; pstate <= max_pstate; pstate++) { + pstate_def = rdmsr(PSTATE_0_MSR + pstate); + + pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) + >> PSTATE_DEF_HI_ENABLE_SHIFT; + if (!pstate_enable) + continue; + + pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); + pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); + pstate_values[pstate_count].transition_latency = 0; + pstate_values[pstate_count].bus_master_latency = 0; + pstate_values[pstate_count].control_value = pstate; + pstate_values[pstate_count].status_value = pstate; + + pstate_xpss_values[pstate_count].core_freq = + (uint64_t)pstate_values[pstate_count].core_freq; + pstate_xpss_values[pstate_count].power = + (uint64_t)pstate_values[pstate_count].power; + pstate_xpss_values[pstate_count].transition_latency = 0; + pstate_xpss_values[pstate_count].bus_master_latency = 0; + pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; + pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; + pstate_count++; + } + + return pstate_count; +} + void generate_cpu_entries(const struct device *device) { - int cores, cpu; + int logical_cores; + size_t pstate_count, cpu, proc_blk_len; + struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; + struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; + uint32_t threads_per_core, proc_blk_addr; + uint32_t cstate_base_address = + rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK; - cores = get_cpu_count(); - printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); + const acpi_addr_t perf_ctrl = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_CTL_REG, + }; + const acpi_addr_t perf_sts = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_STS_REG, + }; - /* Generate BSP \_SB.P000 */ - acpigen_write_processor(0, ACPI_GPE0_BLK, 6); - acpigen_pop_len(); + acpi_cstate_t cstate_info[] = { + [0] = { + .ctype = 1, + .latency = 1, + .power = 0, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 2, + .bit_offset = 2, + .addrl = 0, + .addrh = 0, + }, + }, + [1] = { + .ctype = 2, + .latency = 400, + .power = 0, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .bit_offset = 0, + .addrl = cstate_base_address + 1, + .addrh = 0, + .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, + }, + }, + }; + + threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) + >> CPUID_EBX_THREADS_SHIFT) + + 1; + pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); + logical_cores = get_cpu_count(); + + for (cpu = 0; cpu < logical_cores; cpu++) { + + if (cpu == 0) { + /* BSP values for \_SB.Pxxx */ + proc_blk_len = 6; + proc_blk_addr = ACPI_GPE0_BLK; + } else { + /* AP values for \_SB.Pxxx */ + proc_blk_addr = 0; + proc_blk_len = 0; + } + + acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len); + + acpigen_write_pct_package(&perf_ctrl, &perf_sts); + + acpigen_write_pss_object(pstate_values, pstate_count); + + acpigen_write_xpss_object(pstate_xpss_values, pstate_count); + + if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) + acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, + HW_ALL); + else + acpigen_write_PSD_package(0, logical_cores, SW_ALL); + + acpigen_write_PPC(0); + + acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); + + acpigen_write_CSD_package(cpu >> 1, threads_per_core, HW_ALL, 0); - /* Generate AP \_SB.Pxxx */ - for (cpu = 1; cpu < cores; cpu++) { - acpigen_write_processor(cpu, 0, 0); acpigen_pop_len(); } } diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 727b9bb444..ffdfcd451c 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -139,6 +139,7 @@ Device (AOAC) { AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 8b61b8f921..eb646dec1e 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -36,14 +36,14 @@ Method (PNOT) * Processor Object */ /* These devices are created at runtime */ -External (\_PR.C000, DeviceObj) -External (\_PR.C001, DeviceObj) -External (\_PR.C002, DeviceObj) -External (\_PR.C003, DeviceObj) -External (\_PR.C004, DeviceObj) -External (\_PR.C005, DeviceObj) -External (\_PR.C006, DeviceObj) -External (\_PR.C007, DeviceObj) +External (\_SB.C000, DeviceObj) +External (\_SB.C001, DeviceObj) +External (\_SB.C002, DeviceObj) +External (\_SB.C003, DeviceObj) +External (\_SB.C004, DeviceObj) +External (\_SB.C005, DeviceObj) +External (\_SB.C006, DeviceObj) +External (\_SB.C007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) @@ -51,33 +51,33 @@ Method (PPKG) If (LGreaterEqual (\PCNT, 8)) { Return (Package () { - \_PR.C000, - \_PR.C001, - \_PR.C002, - \_PR.C003, - \_PR.C004, - \_PR.C005, - \_PR.C006, - \_PR.C007 + \_SB.C000, + \_SB.C001, + \_SB.C002, + \_SB.C003, + \_SB.C004, + \_SB.C005, + \_SB.C006, + \_SB.C007 }) } ElseIf (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.C000, - \_PR.C001, - \_PR.C002, - \_PR.C003 + \_SB.C000, + \_SB.C001, + \_SB.C002, + \_SB.C003 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.C000, - \_PR.C001 + \_SB.C000, + \_SB.C001 }) } Else { Return (Package () { - \_PR.C000 + \_SB.C000 }) } } diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 8147619ab5..6790a5f4a6 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -17,37 +17,14 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Miscellaneous */ Offset (0x00), PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community - TMPS, 8, // 0x2B - Temperature Sensor ID - TLVL, 8, // 0x2C - Throttle Level Limit - FLVL, 8, // 0x2D - Current FAN Level - TCRT, 8, // 0x2E - Critical Threshold - TPSV, 8, // 0x2F - Passive Threshold - TMAX, 8, // 0x30 - CPU Tj_max - Offset (0x34), // 0x34 - AOAC Device Enables - , 7, - IC2E, 1, // I2C2, 7 - IC3E, 1, // I2C3, 8 - IC4E, 1, // I2C4, 9 - , 1, - UT0E, 1, // UART0, 11 - UT1E, 1, // UART1, 12 - , 3, - UT2E, 1, // UART2, 16 - , 9, - UT23, 1, // UART3, 26 - ESPI, 1, // ESPI, 27 + LIDS, 8, // 0x01 - LID State + PWRS, 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 7623d9b03e..6cbfc5f664 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,18 @@ Device (FUR0) Return (Local0) } } + + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { @@ -352,6 +364,14 @@ Device (MISC) Name (_CRS, ResourceTemplate() { Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "is-rv", 1 }, + }, + }) Method (_STA, 0x0, NotSerialized) { Return (0x0F) diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8f4993fa92..9208e136f7 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -49,13 +49,6 @@ Name(CRES, ResourceTemplate() { 0x0000, /* translation */ 0x0cf8 /* length */ ) - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03b0, /* range minimum */ - 0x03df, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ - ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index fb168a1f5a..ec9924bd26 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,11 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include #include +#include +#include +#include +#include +#include struct amd_fsp_acpi_hob_info { uint32_t table_size_in_bytes; @@ -39,15 +45,470 @@ static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t return current; } +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +{ + ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; + memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; + ivhd_ioapic->handle = CONFIG_PICASSO_FCH_IOAPIC_ID; + ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + ivhd_ioapic = (ivrs_ivhd_special_t *)current; + memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->handle = CONFIG_PICASSO_GNB_IOAPIC_ID; + ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_hpet(unsigned long current) +{ + ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; + + ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_hpet->reserved = 0x0000; + ivhd_hpet->dte_setting = 0x00; + ivhd_hpet->handle = 0x00; + ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_f0_device(unsigned long current, + uint16_t dev_id, uint8_t datasetting) +{ + ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *) current; + + ivhd_f0->type = IVHD_DEV_VARIABLE; + ivhd_f0->dev_id = dev_id; + ivhd_f0->dte_setting = datasetting; + ivhd_f0->hardware_id[0] = 'A'; + ivhd_f0->hardware_id[1] = 'M'; + ivhd_f0->hardware_id[2] = 'D'; + ivhd_f0->hardware_id[3] = 'I'; + ivhd_f0->hardware_id[4] = '0'; + ivhd_f0->hardware_id[5] = '0'; + ivhd_f0->hardware_id[6] = '4'; + ivhd_f0->hardware_id[7] = '0'; + + memset(ivhd_f0->compatible_id, 0, sizeof(ivhd_f0->compatible_id)); + + ivhd_f0->uuid_format = 0; + ivhd_f0->uuid_length = 0; + + current += sizeof(ivrs_ivhd_f0_entry_t); + return current; +} + +static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, + uint16_t end_devid, uint8_t setting) +{ + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + current = ALIGN_UP(current, 4); + ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; + + /* Create the start range IVHD entry */ + ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; + ivhd_range->dev_id = start_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + /* Create the end range IVHD entry */ + ivhd_range = (ivrs_ivhd_generic_t *)current; + ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; + ivhd_range->dev_id = end_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + return current; +} + +static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, + unsigned long *current, uint8_t type, uint8_t data) +{ + if (type == IVHD_DEV_4_BYTE_SELECT) { + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + *current = ALIGN_UP(*current, 4); + ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + *current += sizeof(ivrs_ivhd_generic_t); + } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { + ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + ivhd_entry->reserved1 = 0; + ivhd_entry->reserved2 = 0; + ivhd_entry->source_dev_id = parent->path.pci.devfn | + (parent->bus->secondary << 8); + *current += sizeof(ivrs_ivhd_alias_t); + } + + return *current; +} + +static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *ivhd_length) +{ + unsigned int header_type, is_pcie; + unsigned long current_backup; + + header_type = dev->hdr_type & 0x7f; + is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (((header_type == PCI_HEADER_TYPE_NORMAL) || + (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { + /* Device or Bridge is PCIe */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); + *ivhd_length += (*current - current_backup); + } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { + /* Device is legacy PCI or PCI-X */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); + *ivhd_length += (*current - current_backup); + } +} + +static void add_ivhd_device_entries(struct device *parent, struct device *dev, + unsigned int depth, int linknum, int8_t *root_level, + unsigned long *current, uint16_t *ivhd_length) +{ + struct device *sibling; + struct bus *link; + + if (!root_level) + return; + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && + (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if ((*root_level != -1) && (dev->enabled)) { + if (depth != *root_level) + ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = + sibling->sibling) + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, + current, ivhd_length); +} + +static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs) +{ + acpi_ivrs_ivhd40_t *ivhd_40; + unsigned long current_backup; + int8_t root_level; + + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); + + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); + ivhd_40 = (acpi_ivrs_ivhd40_t *)current; + + /* Enable EFR */ + ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; + /* For type 40h bits 6 and 7 are reserved */ + ivhd_40->flags = ivrs->ivhd.flags & 0x3f; + ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); + /* BDF :00.2 */ + ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivhd_40->iommu_base_low = ivrs->ivhd.iommu_base_low; + ivhd_40->iommu_base_high = ivrs->ivhd.iommu_base_high; + ivhd_40->pci_segment_group = 0x0000; + ivhd_40->iommu_info = ivrs->ivhd.iommu_info; + /* For type 40h bits 31:28 and 12:0 are reserved */ + ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000; + + if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { + ivhd_40->efr_reg_image_low = read32((void *)ivhd_40->iommu_base_low + 0x30); + ivhd_40->efr_reg_image_high = read32((void *)ivhd_40->iommu_base_low + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd40_t); + + /* Now repeat all the device entries from type 10h */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivhd_40->length += (current - current_backup); + root_level = -1; + add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, + ¤t, &ivhd_40->length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivhd_40->length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivhd_40->length += (current - current_backup); + + /* Describe EMMC */ + current_backup = current; + current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), + IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); + ivhd_40->length += (current - current_backup); + + return current; +} + +static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs) +{ + acpi_ivrs_ivhd11_t *ivhd_11; + ivhd11_iommu_attr_t *ivhd11_attr_ptr; + unsigned long current_backup; + int8_t root_level; + + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); + + /* + * In order to utilize all features, firmware should expose type 11h + * IVHD which supersedes the type 10h. + */ + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); + ivhd_11 = (acpi_ivrs_ivhd11_t *)current; + + /* Enable EFR */ + ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; + /* For type 11h bits 6 and 7 are reserved */ + ivhd_11->flags = ivrs->ivhd.flags & 0x3f; + ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); + /* BDF :00.2 */ + ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivhd_11->iommu_base_low = ivrs->ivhd.iommu_base_low; + ivhd_11->iommu_base_high = ivrs->ivhd.iommu_base_high; + ivhd_11->pci_segment_group = 0x0000; + ivhd_11->iommu_info = ivrs->ivhd.iommu_info; + ivhd11_attr_ptr = (ivhd11_iommu_attr_t *) &ivrs->ivhd.iommu_feature_info; + ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; + ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks; + ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; + + if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { + ivhd_11->efr_reg_image_low = read32((void *)ivhd_11->iommu_base_low + 0x30); + ivhd_11->efr_reg_image_high = read32((void *)ivhd_11->iommu_base_low + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd11_t); + + /* Now repeat all the device entries from type 10h */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivhd_11->length += (current - current_backup); + root_level = -1; + add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, + ¤t, &ivhd_11->length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivhd_11->length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivhd_11->length += (current - current_backup); + + return acpi_fill_ivrs40(current, ivrs); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) +{ + unsigned long current_backup; + uint64_t mmio_x30_value; + uint64_t mmio_x18_value; + uint64_t mmio_x4000_value; + uint32_t cap_offset_0; + uint32_t cap_offset_10; + int8_t root_level; + + struct device *iommu_dev; + struct device *nb_dev; + + nb_dev = pcidev_on_root(0, 0); + if (!nb_dev) { + printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); + printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); + + return (unsigned long)ivrs; + } + + iommu_dev = pcidev_on_root(0, 2); + if (!iommu_dev) { + printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); + + return (unsigned long)ivrs; + } + + if (ivrs != NULL) { + ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + + /* BDF :00.2 */ + ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivrs->ivhd.capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; + ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); + + cap_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset); + cap_offset_10 = pci_read_config32(iommu_dev, + ivrs->ivhd.capability_offset + 0x10); + mmio_x18_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x18); + mmio_x30_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x30); + mmio_x4000_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x4000); + + ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ? + IVHD_FLAG_PPE_SUP : 0); + ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PRE_F_SUP) ? + IVHD_FLAG_PREF_SUP : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_COHERENT) ? + IVHD_FLAG_COHERENT : 0); + ivrs->ivhd.flags |= ((cap_offset_0 & CAP_OFFSET_0_IOTLB_SP) ? + IVHD_FLAG_IOTLB_SUP : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_ISOC) ? + IVHD_FLAG_ISOC : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_RES_PASS_PW) ? + IVHD_FLAG_RES_PASS_PW : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_PASS_PW) ? + IVHD_FLAG_PASS_PW : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? + IVHD_FLAG_HT_TUN_EN : 0); + + ivrs->ivhd.pci_segment_group = 0x0000; + + ivrs->ivhd.iommu_info = pci_read_config16(iommu_dev, + ivrs->ivhd.capability_offset + 0x10) & 0x1F; + ivrs->ivhd.iommu_info |= (pci_read_config16(iommu_dev, + ivrs->ivhd.capability_offset + 0xC) & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT; + + ivrs->ivhd.iommu_feature_info = 0; + ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_HATS_MASK) + << (IOMMU_FEATURE_HATS_SHIFT - MMIO_EXT_FEATURE_HATS_SHIFT); + + ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_GATS_MASK) + << (IOMMU_FEATURE_GATS_SHIFT - MMIO_EXT_FEATURE_GATS_SHIFT); + + ivrs->ivhd.iommu_feature_info |= (cap_offset_10 & CAP_OFFSET_10_MSI_NUM_PPR) + >> (CAP_OFFSET_10_MSI_NUM_PPR_SHIFT + - IOMMU_FEATURE_MSI_NUM_PPR_SHIFT); + + ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & + MMIO_CNT_CFG_N_COUNTER_BANKS) + << (IOMMU_FEATURE_PN_BANKS_SHIFT - MMIO_CNT_CFG_N_CNT_BANKS_SHIFT); + + ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & MMIO_CNT_CFG_N_COUNTER) + << (IOMMU_FEATURE_PN_COUNTERS_SHIFT - MMIO_CNT_CFG_N_COUNTER_SHIFT); + ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & + MMIO_EXT_FEATURE_PAS_MAX_MASK) + >> (MMIO_EXT_FEATURE_PAS_MAX_SHIFT - IOMMU_FEATURE_PA_SMAX_SHIFT); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_HE_SUP) + ? IOMMU_FEATURE_HE_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GA_SUP) + ? IOMMU_FEATURE_GA_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_IA_SUP) + ? IOMMU_FEATURE_IA_SUP : 0); + ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & + MMIO_EXT_FEATURE_GLX_SUP_MASK) + >> (MMIO_EXT_FEATURE_GLX_SHIFT - IOMMU_FEATURE_GLX_SHIFT); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GT_SUP) + ? IOMMU_FEATURE_GT_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_NX_SUP) + ? IOMMU_FEATURE_NX_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_XT_SUP) + ? IOMMU_FEATURE_XT_SUP : 0); + + /* Enable EFR if supported */ + ivrs->iv_info = pci_read_config32(iommu_dev, + ivrs->ivhd.capability_offset + 0x10) & 0x007fffe0; + if (pci_read_config32(iommu_dev, + ivrs->ivhd.capability_offset) & EFR_FEATURE_SUP) + ivrs->iv_info |= IVINFO_EFR_SUPPORTED; + + } else { + printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); + + return (unsigned long)ivrs; + } + + /* + * Add all possible PCI devices on bus 0 that can generate transactions + * processed by IOMMU. Start with device 00:01.0 + */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivrs->ivhd.length += (current - current_backup); + root_level = -1; + add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, + ¤t, &ivrs->ivhd.length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivrs->ivhd.length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - current_backup); + + /* If EFR is not supported, IVHD type 11h is reserved */ + if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) + return current; + + return acpi_fill_ivrs11(current, ivrs); +} + uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { + acpi_ivrs_t *ivrs; + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); - current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); - current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* IVRS */ + current = ALIGN(current, 8); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); /* Add SRAT, MSCT, SLIT if needed in the future */ diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index f31afbf808..1f7dcb02e4 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -29,7 +29,7 @@ const static int aoac_devs[] = { FCH_AOAC_DEV_ESPI, }; -void power_on_aoac_device(int dev) +void power_on_aoac_device(unsigned int dev) { uint8_t byte; @@ -41,7 +41,7 @@ void power_on_aoac_device(int dev) aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -void power_off_aoac_device(int dev) +void power_off_aoac_device(unsigned int dev) { uint8_t byte; @@ -51,7 +51,7 @@ void power_off_aoac_device(int dev) aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -bool is_aoac_device_enabled(int dev) +bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; @@ -63,7 +63,7 @@ bool is_aoac_device_enabled(int dev) return false; } -void wait_for_aoac_enabled(int dev) +void wait_for_aoac_enabled(unsigned int dev) { while (!is_aoac_device_enabled(dev)) udelay(100); @@ -71,7 +71,7 @@ void wait_for_aoac_enabled(int dev) void enable_aoac_devices(void) { - int i; + unsigned int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) power_on_aoac_device(aoac_devs[i]); diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 556fbad5fc..c715324973 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -9,16 +10,13 @@ #include #include #include +#include +#include #include #include #include #include -#include - -/* vboot includes directory may not be in include path if vboot is not enabled */ -#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) -#include <2struct.h> -#endif +#include asmlinkage void bootblock_resume_entry(void); @@ -129,15 +127,10 @@ void bootblock_soc_init(void) u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); -#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) - if (*(uint32_t *)_vboot2_work != VB2_SHARED_DATA_MAGIC) { - printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); - - printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); - - die("Halting.\n"); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_psp_transfer_buf(); + show_psp_transfer_info(); } -#endif fch_early_init(); } diff --git a/src/soc/amd/picasso/bootblock/vboot_bootblock.c b/src/soc/amd/picasso/bootblock/vboot_bootblock.c new file mode 100644 index 0000000000..3fbc4ef608 --- /dev/null +++ b/src/soc/amd/picasso/bootblock/vboot_bootblock.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include <2struct.h> + +void verify_psp_transfer_buf(void) +{ + if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { + cmos_write(0x00, CMOS_RECOVERY_BYTE); + return; + } + + /* + * If CMOS is valid and the system has already been rebooted once, but + * still returns here, instead of rebooting to verstage again, assume + * that the system is in a reboot loop and halt. + */ + if ((!vbnv_cmos_failed()) && cmos_read(CMOS_RECOVERY_BYTE) == + CMOS_RECOVERY_MAGIC_VAL) + die("Error: Reboot into recovery was unsuccessful. Halting."); + + printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); + printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); + cmos_init(0); + cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); + warm_reset(); +} + +void show_psp_transfer_info(void) +{ + struct transfer_info_struct *info = (struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (info->magic_val == TRANSFER_MAGIC_VAL) { + if ((info->psp_info & PSP_INFO_VALID) == 0) { + printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); + return; + } + + printk(BIOS_INFO, "PSP boot mode: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_MODE ? + "Production" : "Development"); + printk(BIOS_INFO, "Silicon level: %s\n", + info->psp_info & PSP_INFO_PRODUCTION_SILICON ? + "Production" : "Pre-Production"); + } +} diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 1950691c89..3098a817a7 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -16,7 +16,7 @@ /* USB 2.0 PHY Parameters */ -struct usb2_phy_tune { +struct __packed usb2_phy_tune { /* Disconnect Threshold Adjustment. Range 0 - 0x7 */ uint8_t com_pds_tune; /* Squelch Threshold Adjustment. Range 0 - 0x7 */ @@ -37,6 +37,26 @@ struct usb2_phy_tune { uint8_t tx_res_tune; }; +/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */ +union __packed usb3_force_gen1 { + struct { + uint8_t xhci0_port0:1; + uint8_t xhci0_port1:1; + uint8_t xhci0_port2:1; + uint8_t xhci0_port3:1; + } ports; + uint8_t usb3_port_force_gen1_en; +}; + +#define USB_PORT_COUNT 6 + +enum sd_emmc_driver_strength { + SD_EMMC_DRIVE_STRENGTH_B, + SD_EMMC_DRIVE_STRENGTH_A, + SD_EMMC_DRIVE_STRENGTH_C, + SD_EMMC_DRIVE_STRENGTH_D, +}; + struct soc_amd_picasso_config { struct soc_amd_common_config common_config; /* @@ -61,7 +81,7 @@ struct soc_amd_picasso_config { /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ u8 acp_i2s_wake_enable; /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acpi_pme_enable; + u8 acp_pme_enable; /** * IRQ 0 - 15 have a default trigger of edge and default polarity of high. @@ -88,11 +108,28 @@ struct soc_amd_picasso_config { uint32_t stapm_time_constant; uint32_t sustained_power_limit; + /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ + uint8_t dptc_enable; + + /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + uint32_t fast_ppt_limit_tablet_mode; + uint32_t slow_ppt_limit_tablet_mode; + uint32_t sustained_power_limit_tablet_mode; + /* PROCHOT_L de-assertion Ramp Time */ uint32_t prochot_l_deassertion_ramp_time; + enum { + DOWNCORE_AUTO = 0, + DOWNCORE_1 = 1, /* Run with single core */ + DOWNCORE_2 = 3, /* Run with two cores */ + DOWNCORE_3 = 4, /* Run with three cores */ + } downcore_mode; + uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */ + /* Lower die temperature limit */ uint32_t thermctl_limit; + uint32_t thermctl_limit_tablet_mode; /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ uint32_t psi0_current_limit; @@ -116,30 +153,72 @@ struct soc_amd_picasso_config { uint32_t telemetry_vddcr_soc_slope; uint32_t telemetry_vddcr_soc_offset; + struct { + /* + * SDHCI doesn't directly support eMMC. There is an implicit mapping between + * eMMC timing modes and SDHCI UHS-I timing modes defined in the linux + * kernel. + * + * HS -> UHS_SDR12 (0x00) + * DDR52 -> UHS_DDR50 (0x04) + * HS200 -> UHS_SDR104 (0x03) + * HS400 -> NONE (0x05) + * + * The kernel driver uses a heuristic to determine if HS400 is supported. + */ + enum { + SD_EMMC_DISABLE, + SD_EMMC_SD_LOW_SPEED, + SD_EMMC_SD_HIGH_SPEED, + SD_EMMC_SD_UHS_I_SDR_50, + SD_EMMC_SD_UHS_I_DDR_50, + SD_EMMC_SD_UHS_I_SDR_104, + SD_EMMC_EMMC_SDR_26, + SD_EMMC_EMMC_SDR_52, + SD_EMMC_EMMC_DDR_52, + SD_EMMC_EMMC_HS200, + SD_EMMC_EMMC_HS400, + SD_EMMC_EMMC_HS300, + } timing; + + /* + * Sets the driver strength reflected in the SDHCI Preset Value Registers. + * + * According to the SDHCI spec: + * The host should select the weakest drive strength that meets rise / + * fall time requirement at system operating frequency. + */ + enum sd_emmc_driver_strength sdr104_hs400_driver_strength; + enum sd_emmc_driver_strength ddr50_driver_strength; + enum sd_emmc_driver_strength sdr50_driver_strength; + + /* + * Sets the frequency in kHz reflected in the Initialization Preset Value + * Register. + * + * This value is used while in open-drain mode, and has a maximum value of + * 400 kHz. + */ + uint16_t init_khz_preset; + } emmc_config; + + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ + union usb3_force_gen1 usb3_port_force_gen1; + + uint8_t has_usb2_phy_tune_params; + struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; enum { - SD_EMMC_DISABLE, - SD_EMMC_SD_LOW_SPEED, - SD_EMMC_SD_HIGH_SPEED, - SD_EMMC_SD_UHS_I_SDR_50, - SD_EMMC_SD_UHS_I_DDR_50, - SD_EMMC_SD_UHS_I_SDR_104, - SD_EMMC_EMMC_SDR_26, - SD_EMMC_EMMC_SDR_52, - SD_EMMC_EMMC_DDR_52, - SD_EMMC_EMMC_HS200, - SD_EMMC_EMMC_HS400, - SD_EMMC_EMMC_HS300, - } sd_emmc_config; - - uint8_t xhci0_force_gen1; - - struct usb2_phy_tune usb_2_port_0_tune_params; - struct usb2_phy_tune usb_2_port_1_tune_params; - struct usb2_phy_tune usb_2_port_2_tune_params; - struct usb2_phy_tune usb_2_port_3_tune_params; - struct usb2_phy_tune usb_2_port_4_tune_params; - struct usb2_phy_tune usb_2_port_5_tune_params; + USB_OC_PIN_0 = 0x0, + USB_OC_PIN_1 = 0x1, + USB_OC_PIN_2 = 0x2, + USB_OC_PIN_3 = 0x3, + USB_OC_PIN_4 = 0x4, + USB_OC_PIN_5 = 0x5, + USB_OC_NONE = 0xf, + } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* The array index is the general purpose PCIe clock output number. */ + enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index c42f400362..4d6e98d221 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -46,6 +46,15 @@ int get_cpu_count(void) return 1 + (cpuid_ecx(0x80000008) & 0xff); } +static void set_cstate_io_addr(void) +{ + msr_t cst_addr; + + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(MSR_CSTATE_ADDRESS, cst_addr); +} + static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; @@ -109,6 +118,7 @@ static void model_17_init(struct device *dev) { check_mca(); setup_lapic(); + set_cstate_io_addr(); amd_update_microcode_from_cbfs(); } diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 23cb94c837..ac4e23d318 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -10,9 +10,9 @@ #include #include #include -#include +#include -static void disable_mmio_reg(int reg) +static void disable_mmio_reg(unsigned int reg) { pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg), IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); @@ -20,7 +20,7 @@ static void disable_mmio_reg(int reg) pci_write_config32(SOC_DF_F0_DEV, NB_MMIO_LIMIT(reg), 0); } -static bool is_mmio_reg_disabled(int reg) +static bool is_mmio_reg_disabled(unsigned int reg) { uint32_t val = pci_read_config32(SOC_DF_F0_DEV, NB_MMIO_CONTROL(reg)); return !(val & ((MMIO_WE | MMIO_RE))); diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c index 860778d76f..1133670043 100644 --- a/src/soc/amd/picasso/dmi.c +++ b/src/soc/amd/picasso/dmi.c @@ -14,6 +14,7 @@ #include #include #include +#include /** * Populate dimm_info using AGESA TYPE17_DMI_INFO. @@ -27,7 +28,9 @@ static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, dimm->ddr_type = dmi17->MemoryType; - dimm->ddr_frequency = dmi17->Speed; + dimm->configured_speed_mts = ddr4_speed_mhz_to_reported_mts(dmi17->ConfigSpeed); + + dimm->max_speed_mts = ddr4_speed_mhz_to_reported_mts(dmi17->Speed); dimm->rank_per_dimm = dmi17->Attributes; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 80d43fb245..a08a209bc1 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include @@ -11,7 +13,7 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, { int val = SD_DISABLE; - switch (cfg->sd_emmc_config) { + switch (cfg->emmc_config.timing) { case SD_EMMC_DISABLE: val = SD_DISABLE; break; @@ -53,13 +55,21 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, } scfg->emmc0_mode = val; + scfg->emmc0_sdr104_hs400_driver_strength = + cfg->emmc_config.sdr104_hs400_driver_strength; + scfg->emmc0_ddr50_driver_strength = cfg->emmc_config.ddr50_driver_strength; + scfg->emmc0_sdr50_driver_strength = cfg->emmc_config.sdr50_driver_strength; + scfg->emmc0_init_khz_preset = cfg->emmc_config.init_khz_preset; } -static void fill_pcie_descriptors(FSP_S_CONFIG *scfg, - const fsp_pcie_descriptor *descs, size_t num) +static void fill_dxio_descriptors(FSP_S_CONFIG *scfg, + const fsp_dxio_descriptor *descs, size_t num) { size_t i; + ASSERT_MSG(num <= FSPS_UPD_DXIO_DESCRIPTOR_COUNT, + "Too many DXIO descriptors provided."); + for (i = 0; i < num; i++) { memcpy(scfg->dxio_descriptor[i], &descs[i], sizeof(scfg->dxio_descriptor[0])); } @@ -70,36 +80,66 @@ static void fill_ddi_descriptors(FSP_S_CONFIG *scfg, { size_t i; + ASSERT_MSG(num <= FSPS_UPD_DDI_DESCRIPTOR_COUNT, + "Too many DDI descriptors provided."); + for (i = 0; i < num; i++) { memcpy(&scfg->ddi_descriptor[i], &descs[i], sizeof(scfg->ddi_descriptor[0])); } } + static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) { - const fsp_pcie_descriptor *fsp_pcie; + const fsp_dxio_descriptor *fsp_dxio; const fsp_ddi_descriptor *fsp_ddi; - size_t num_pcie; + size_t num_dxio; size_t num_ddi; - mainboard_get_pcie_ddi_descriptors(&fsp_pcie, &num_pcie, + mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); - fill_pcie_descriptors(scfg, fsp_pcie, num_pcie); + fill_dxio_descriptors(scfg, fsp_dxio, num_dxio); fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); } static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) { - size_t num = sizeof(struct usb2_phy_tune); + size_t i; - scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT); + /* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */ + ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); - memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num); - memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num); - memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num); - memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num); - memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num); - memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num); + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en; + + if (cfg->has_usb2_phy_tune_params) { + for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { + memcpy(scfg->fch_usb_2_port_phy_tune[i], + &cfg->usb_2_port_tune_params[i], + sizeof(scfg->fch_usb_2_port_phy_tune[0])); + } + } + + /* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */ + for (i = 0; i < USB_PORT_COUNT; i++) { + scfg->xhci_oc_pin_select &= ~(0xf << (i * 4)); + scfg->xhci_oc_pin_select |= + (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); + } +} + +static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) +{ + _Static_assert(CONFIG_PICASSO_GNB_IOAPIC_ID >= CONFIG_MAX_CPUS, + "PICASSO_GNB_IOAPIC_ID should be >= CONFIG_MAX_CPUS!\n"); + _Static_assert(CONFIG_PICASSO_FCH_IOAPIC_ID >= CONFIG_MAX_CPUS, + "PICASSO_FCH_IOAPIC_ID should be >= CONFIG_MAX_CPUS!\n"); + _Static_assert(CONFIG_PICASSO_GNB_IOAPIC_ID != CONFIG_PICASSO_FCH_IOAPIC_ID, + "PICASSO_GNB_IOAPIC_ID should be != PICASSO_FCH_IOAPIC_ID!\n"); + + scfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + scfg->gnb_ioapic_id = CONFIG_PICASSO_GNB_IOAPIC_ID; + scfg->fch_ioapic_id = CONFIG_PICASSO_FCH_IOAPIC_ID; } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) @@ -110,5 +150,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_assign_ioapic_upds(scfg); fsp_usb_oem_customization(scfg, cfg); } diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 09f60d7280..a21d3477bb 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -4,6 +4,8 @@ #define __SOC_PICASSO_ACPI_H__ #include +#include +#include unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); @@ -13,4 +15,10 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current const char *soc_acpi_name(const struct device *dev); +/* Object to capture state of chipset for logging events. */ +struct chipset_state { + struct acpi_pm_gpe_state gpe_state; + struct gpio_wake_state gpio_state; +}; + #endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 20084f0eba..c1dd6ef6ff 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -3,6 +3,7 @@ #ifndef __PICASSO_I2C_H__ #define __PICASSO_I2C_H__ +#include #include struct soc_amd_i2c_save { diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cb845c44d3..890b1c3647 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -5,6 +5,7 @@ /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 #if CONFIG(HPET_ADDRESS_OVERRIDE) @@ -12,7 +13,12 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 +/* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 +#define AL2AHB_CONTROL_CLK_OFFSET 0x10 +#define AL2AHB_CLK_GATE_EN (1 << 1) +#define AL2AHB_CONTROL_HCLK_OFFSET 0x30 +#define AL2AHB_HCLK_GATE_EN (1 << 1) /* Reserved 0xfecd1000-0xfedc3fff */ @@ -64,7 +70,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x0c) /* 6 bytes */ +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x13) /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h new file mode 100644 index 0000000000..0743ba0c9e --- /dev/null +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file applies to AMD64 products. + * The definitions come from the device's PPR. + */ + +#ifndef SOC_AMD_PICASSO_MSR_H +#define SOC_AMD_PICASSO_MSR_H + +/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ +#define PSTATE_DEF_HI_ENABLE_SHIFT 31 +#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) +#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 +#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) +#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 +#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT) +#define PSTATE_DEF_LO_CORE_VID_SHIFT 14 +#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8 +#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8 +#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A +#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E +#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0 +#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) +#define PSTATE_DEF_LO_CORE_FREQ_BASE 25 + +#endif /* SOC_AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 214ab1d0bc..2abcdd31f7 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -17,27 +17,15 @@ struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ - uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ - uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad relative offset */ - uint8_t tmps; /* 0x2B - Temperature Sensor ID */ - uint8_t tlvl; /* 0x2C - Throttle Level Limit */ - uint8_t flvl; /* 0x2D - Current FAN Level */ - uint8_t tcrt; /* 0x2E - Critical Threshold */ - uint8_t tpsv; /* 0x2F - Passive Threshold */ - uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t pad1[3]; - aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint8_t unused[200]; + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ + uint8_t unused[230]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index c217d75f6c..0ea6f2b338 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -22,9 +22,9 @@ #define EMMC_HS400 10 #define EMMC_HS300 11 -/* Mainboard callback to obtain PCIe and DDI descriptors. */ -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, +/* Mainboard callback to obtain DXI/PCIe and DDI descriptors. */ +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); #endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h new file mode 100644 index 0000000000..afc4d7d1ac --- /dev/null +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PSP_VERSTAGE_PSP_TRANSFER_H +#define PSP_VERSTAGE_PSP_TRANSFER_H + +# if (CONFIG_CMOS_RECOVERY_BYTE != 0) +# define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE +# elif CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +# error "Must set CONFIG_CMOS_RECOVERY_BYTE" +# endif + +#define CMOS_RECOVERY_MAGIC_VAL 0x96 + +#define TRANSFER_INFO_SIZE 64 +#define TIMESTAMP_BUFFER_SIZE 0x200 + +#define TRANSFER_MAGIC_VAL 0x50544953 + +/* Area for things that would cause errors in a linker script */ +#if !defined(__ASSEMBLER__) +#include + +struct transfer_info_struct { + uint32_t magic_val; /* Identifier */ + uint32_t struct_bytes; /* Size of this structure */ + uint32_t buffer_size; /* Size of the transfer buffer area */ + + /* Offsets from start of transfer buffer */ + uint32_t workbuf_offset; + uint32_t console_offset; + uint32_t timestamp_offset; + uint32_t fmap_offset; + + uint32_t unused1[5]; + + /* Fields reserved for the PSP */ + uint64_t timestamp; /* Offset 0x30 */ + uint32_t psp_unused; /* Offset 0x38 */ + uint32_t psp_info; /* Offset 0x3C */ +}; + +_Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE, \ + "TRANSFER_INFO_SIZE is incorrect"); + +/* Make sure the PSP transferred information over to x86 side. */ +void verify_psp_transfer_buf(void); +/* Display the transfer block's PSP_info data */ +void show_psp_transfer_info(void); + +#endif + +#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index e9f7e2e2b2..222858ab51 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -139,30 +139,23 @@ /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -#define GPP_CLK0_REQ_SHL 0 -#define GPP_CLK1_REQ_SHL 2 -#define GFX_CLK0_REQ_SHL 4 -#define GPP_CLK2_REQ_SHL 6 -#define GPP_CLK3_REQ_SHL 8 -#define GFX_CLK1_REQ_SHL 10 -#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL) -#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL) -#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) -#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) -#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL) -#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL) -#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL) -#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL) -#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL) -#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL) -#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) -#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) +#define GPP_CLK0_REQ_SHIFT 0 +#define GPP_CLK1_REQ_SHIFT 2 +#define GPP_CLK4_REQ_SHIFT 4 +#define GPP_CLK2_REQ_SHIFT 6 +#define GPP_CLK3_REQ_SHIFT 8 +#define GPP_CLK5_REQ_SHIFT 10 +#define GPP_CLK6_REQ_SHIFT 12 +#define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) +#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) + #define MISC_CGPLL_CONFIG1 0x08 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ -#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 @@ -228,10 +221,14 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) -#define FCH_UART_LEGACY_DECODE 0xfedc0020 -#define FCH_LEGACY_3F8_SH 3 -#define FCH_LEGACY_2F8_SH 1 -#define FCH_LEGACY_3E8_SH 2 +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ +#define FCH_LEGACY_UART_MAP_SHIFT 8 +#define FCH_LEGACY_UART_MAP_SIZE 2 +#define FCH_LEGACY_UART_MAP_MASK 0x3 +#define FCH_LEGACY_UART_RANGE_2E8 0 +#define FCH_LEGACY_UART_RANGE_2F8 1 +#define FCH_LEGACY_UART_RANGE_3E8 2 +#define FCH_LEGACY_UART_RANGE_3F8 3 #define PM1_LIMIT 16 #define GPE0_LIMIT 28 @@ -252,6 +249,13 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ +/* this is for the devicetree setting and not the values written to the register */ +enum gpp_clk_req_setting { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ +}; + typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ @@ -268,25 +272,18 @@ typedef struct aoac_devs { unsigned int :4; } __packed aoac_devs_t; -struct soc_power_reg { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint16_t wake_from; -}; - void enable_aoac_devices(void); -bool is_aoac_device_enabled(int dev); -void power_on_aoac_device(int dev); -void power_off_aoac_device(int dev); -void wait_for_aoac_enabled(int dev); +bool is_aoac_device_enabled(unsigned int dev); +void power_on_aoac_device(unsigned int dev); +void power_off_aoac_device(unsigned int dev); +void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void fch_pre_init(void); void fch_early_init(void); +void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 3aac936dff..4e5619fa86 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -5,9 +5,9 @@ #include -void set_uart_config(int idx); /* configure hardware of FCH UART selected by idx */ +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -uintptr_t get_uart_base(int idx); /* get MMIO base address of FCH UART */ +uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ #endif /* __PICASSO_UART_H__ */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 69363f5625..e16d0a19e3 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -7,7 +7,6 @@ #include #include #include -#include struct mca_bank { int bank; diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld index 0fed7b0e83..4ad88b1108 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include /* * Start of available space is 0x15000 and this is where the @@ -11,8 +13,6 @@ #define PSP_SRAM_SIZE 160K #define VERSTAGE_START 0x15000 -#define VBOOT_WORK_SIZE 12K -#define FMAP_CACHE_SIZE 2K /* * The temp stack can be made much smaller if needed - even 256 bytes @@ -52,9 +52,15 @@ SECTIONS _everstage = .; ALIGN_COUNTER(64) - REGION(vboot2_work, ., VBOOT_WORK_SIZE, 64) - + _transfer_buffer = .; + REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) + ALIGN_COUNTER(64) + REGION(vboot2_work, ., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE, 64) + ALIGN_COUNTER(64) + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) + TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) FMAP_CACHE(., FMAP_SIZE) + _etransfer_buffer = .; PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE ); diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 6f43ba18af..00cdde6488 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -2,6 +2,7 @@ #include #include +#include #define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr) #define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr) @@ -38,14 +39,16 @@ * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE * | Preram CBMEM console | * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | + * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + * | Transfer Info Structure | * +--------------------------------+ PSP_SHAREDMEM_BASE * | APOB (64KiB) | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS @@ -72,14 +75,18 @@ SECTIONS #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) + _transfer_buffer = .; + REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) - PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., 0x200) + TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) FMAP_CACHE(., FMAP_SIZE) - +#if CONFIG(VBOOT) + _etransfer_buffer = .; + PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) +#endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 73de80365d..96d33f2f1f 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -36,7 +37,7 @@ static const char *pcie_gpp_acpi_name(const struct device *dev) return NULL; } -static struct device_operations pcie_gpp_ops = { +static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -47,14 +48,29 @@ static struct device_operations pcie_gpp_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA, PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB, 0 }; -static const struct pci_driver pcie_gpp_driver __pci_driver = { - .ops = &pcie_gpp_ops, +static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { + .ops = &internal_pcie_gpp_ops, .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; + +static struct device_operations external_pcie_gpp_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const struct pci_driver external_pcie_gpp_driver __pci_driver = { + .ops = &external_pcie_gpp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, +}; diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 320b704716..4f1642bdf7 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -2,6 +2,7 @@ verstage-generic-ccopts += -I$(src)/soc/amd/picasso/psp_verstage/include verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include +verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ verstage-y += delay.c @@ -14,7 +15,6 @@ verstage-y += psp.c verstage-y += reset.c verstage-y += svc.c verstage-y += timer.c -verstage-y += timestamp.c verstage-y += vboot_crypto.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index e01a684a34..89e7014550 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -4,17 +4,16 @@ #include #include +#include #include #include #include #include #include #include -#include #include #include #include -#include static void i2c3_set_bar(void *bar) { @@ -84,6 +83,7 @@ static struct { {"eSPI", {FCH_IO_DEVICE_ESPI}, espi_set_bar}, {"I2C2", {FCH_IO_DEVICE_I2C, 2}, i2c2_set_bar}, {"I2C3", {FCH_IO_DEVICE_I2C, 3}, i2c3_set_bar}, + {"SPI", {FCH_IO_DEVICE_SPI}, spi_set_base}, {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, }; diff --git a/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h index 5245bd1a02..0a3a4d4676 100644 --- a/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h +++ b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h @@ -4,12 +4,10 @@ #define _ARCH_SMP_SPINLOCK_H #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while (0) #define spin_is_locked(lock) 0 #define spin_unlock_wait(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define cpu_relax() do {} while (0) #include #define boot_cpu() 1 diff --git a/src/soc/amd/picasso/psp_verstage/printk.c b/src/soc/amd/picasso/psp_verstage/printk.c index 2f9d30a29e..a99d8bc35d 100644 --- a/src/soc/amd/picasso/psp_verstage/printk.c +++ b/src/soc/amd/picasso/psp_verstage/printk.c @@ -2,12 +2,13 @@ #include #include +#include #include #include void console_hw_init(void) { - // Nothing to init for svc_debug_print + __cbmemc_init(); } int do_printk(int msg_level, const char *fmt, ...) @@ -24,14 +25,16 @@ int do_printk(int msg_level, const char *fmt, ...) int do_vprintk(int msg_level, const char *fmt, va_list args) { - int i, log_this; + int i, cnt, log_this; char buf[256]; log_this = console_log_level(msg_level); if (log_this < CONSOLE_LOG_FAST) return 0; - i = vsnprintf(buf, sizeof(buf), fmt, args); + cnt = vsnprintf(buf, sizeof(buf), fmt, args); + for (i = 0; i < cnt; i++) + __cbmemc_tx_byte(buf[i]); svc_debug_print(buf); return i; } diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index bac05481f6..f367dce6fd 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -4,15 +4,19 @@ #include #include +#include #include +#include +#include +#include +#include #include #include #include #include #include #include - -#define RUN_PSP_SVC_TESTS 0 +#include extern char _bss_start, _bss_end; static struct mem_region_device boot_dev = @@ -26,6 +30,16 @@ static void reboot_into_recovery(struct vb2_context *ctx, uint32_t subcode) subcode += PSP_VBOOT_ERROR_SUBCODE; svc_write_postcode(subcode); + /* + * If there's an error but the PSP_verstage is already booting to RO, + * don't reset the system. It may be that the error is fatal, but if + * the system is stuck, don't intentionally force it into a reboot loop. + */ + if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { + printk(BIOS_ERR, "Already in recovery mode. Staying in RO.\n"); + return; + } + vb2api_fail(ctx, VB2_RECOVERY_RO_UNSPECIFIED, (int)subcode); vboot_save_data(ctx); @@ -33,6 +47,35 @@ static void reboot_into_recovery(struct vb2_context *ctx, uint32_t subcode) vboot_reboot(); } +static uint32_t check_cmos_recovery(void) +{ + /* Only reset if cmos is valid */ + if (vbnv_cmos_failed()) + return 0; + + /* If the byte is set, clear it, then return error to reboot */ + if (cmos_read(CMOS_RECOVERY_BYTE) == CMOS_RECOVERY_MAGIC_VAL) { + cmos_write(0x00, CMOS_RECOVERY_BYTE); + printk(BIOS_DEBUG, "Reboot into recovery requested by coreboot\n"); + return POSTCODE_CMOS_RECOVERY; + } + + return 0; +} + +static uintptr_t locate_amdfw(const char *name, struct region_device *rdev) +{ + struct cbfsf fh; + uint32_t type = CBFS_TYPE_RAW; + + if (cbfs_locate(&fh, rdev, name, &type)) + return 0; + + cbfs_file_data(rdev, &fh); + + return (uintptr_t)rdev_mmap_full(rdev); +} + /* * Tell the PSP where to load the rest of the firmware from */ @@ -41,6 +84,9 @@ static uint32_t update_boot_region(struct vb2_context *ctx) struct psp_ef_table *ef_table; uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; + const char *rname, *fname; + struct region_device rdev; + uintptr_t amdfw_location; /* Continue booting from RO */ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { @@ -49,15 +95,24 @@ static uint32_t update_boot_region(struct vb2_context *ctx) } if (vboot_is_firmware_slot_a(ctx)) { - printk(BIOS_SPEW, "Using FMAP RW_A region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_A_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_A"; + fname = "apu/amdfw_a"; } else { - printk(BIOS_SPEW, "Using FMAP RW_B region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_B_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_B"; + fname = "apu/amdfw_b"; } + if (fmap_locate_area_as_rdev(rname, &rdev)) { + printk(BIOS_ERR, "Error: Could not locate fmap region %s.\n", rname); + return POSTCODE_FMAP_REGION_MISSING; + } + + amdfw_location = locate_amdfw(fname, &rdev); + if (!amdfw_location) { + printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); + return POSTCODE_AMD_FW_MISSING; + } + ef_table = (struct psp_ef_table *)amdfw_location; if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); return POSTCODE_ROMSIG_MISMATCH_ERROR; @@ -94,8 +149,9 @@ static uint32_t update_boot_region(struct vb2_context *ctx) static uint32_t save_buffers(struct vb2_context **ctx) { uint32_t retval; - uint32_t buffer_size = DEFAULT_WORKBUF_TRANSFER_SIZE; + uint32_t buffer_size = MIN_TRANSFER_BUFFER_SIZE; uint32_t max_buffer_size; + struct transfer_info_struct buffer_info = {0}; /* * This should never fail, but if it does, we should still try to @@ -104,28 +160,49 @@ static uint32_t save_buffers(struct vb2_context **ctx) if (svc_get_max_workbuf_size(&max_buffer_size)) { post_code(POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE); printk(BIOS_NOTICE, "Notice: using default transfer buffer size.\n"); - max_buffer_size = DEFAULT_WORKBUF_TRANSFER_SIZE; + max_buffer_size = MIN_TRANSFER_BUFFER_SIZE; } printk(BIOS_DEBUG, "\nMaximum buffer size: %d bytes\n", max_buffer_size); - retval = vb2api_relocate(_vboot2_work, _vboot2_work, buffer_size, ctx); - if (retval != VB2_SUCCESS) { - printk(BIOS_ERR, "Error shrinking workbuf. Error code %#x\n", retval); - buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; - post_code(POSTCODE_WORKBUF_RESIZE_WARNING); + /* Shrink workbuf if MP2 is in use and cannot be used to save buffer */ + if (max_buffer_size < VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) { + retval = vb2api_relocate(_vboot2_work, _vboot2_work, MIN_WORKBUF_TRANSFER_SIZE, + ctx); + if (retval != VB2_SUCCESS) { + printk(BIOS_ERR, "Error shrinking workbuf. Error code %#x\n", retval); + buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; + post_code(POSTCODE_WORKBUF_RESIZE_WARNING); + } + } else { + buffer_size = + (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); + + buffer_info.console_offset = (uint32_t)((uintptr_t)_preram_cbmem_console - + (uintptr_t)_transfer_buffer); + buffer_info.timestamp_offset = (uint32_t)((uintptr_t)_timestamp - + (uintptr_t)_transfer_buffer); + buffer_info.fmap_offset = (uint32_t)((uintptr_t)_fmap_cache - + (uintptr_t)_transfer_buffer); } if (buffer_size > max_buffer_size) { - printk(BIOS_ERR, "Error: Workbuf is larger than max buffer size.\n"); + printk(BIOS_ERR, "Error: Buffer is larger than max buffer size.\n"); post_code(POSTCODE_WORKBUF_BUFFER_SIZE_ERROR); return POSTCODE_WORKBUF_BUFFER_SIZE_ERROR; } - retval = svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, (void *)_vboot2_work, - buffer_size); + buffer_info.magic_val = TRANSFER_MAGIC_VAL; + buffer_info.struct_bytes = sizeof(buffer_info); + buffer_info.buffer_size = buffer_size; + buffer_info.workbuf_offset = (uint32_t)((uintptr_t)_fmap_cache - + (uintptr_t)_vboot2_work); + + memcpy(_transfer_buffer, &buffer_info, sizeof(buffer_info)); + + retval = svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, (void *)_transfer_buffer, + buffer_size); if (retval) { - printk(BIOS_ERR, "Error: Could not save workbuf. Error code 0x%08x\n", - retval); + printk(BIOS_ERR, "Error: Could not save workbuf. Error code 0x%08x\n", retval); return POSTCODE_WORKBUF_SAVE_ERROR; } @@ -141,6 +218,7 @@ void Main(void) * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() */ + timestamp_init(timestamp_get()); svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); @@ -167,15 +245,20 @@ void Main(void) verstage_main(); + ctx = vboot_get_context(); + retval = check_cmos_recovery(); + if (retval) + reboot_into_recovery(ctx, retval); + post_code(POSTCODE_SAVE_BUFFERS); retval = save_buffers(&ctx); if (retval) - goto err; + reboot_into_recovery(ctx, retval); post_code(POSTCODE_UPDATE_BOOT_REGION); retval = update_boot_region(ctx); if (retval) - goto err; + reboot_into_recovery(ctx, retval); post_code(POSTCODE_UNMAP_SPI_ROM); if (boot_dev.base) { @@ -190,9 +273,6 @@ void Main(void) printk(BIOS_DEBUG, "Leaving verstage on PSP\n"); svc_exit(retval); - -err: - reboot_into_recovery(ctx, retval); } const struct region_device *boot_device_ro(void) diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index 6fe5c7a13d..ef5c452500 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -4,6 +4,7 @@ #define PSP_VERSTAGE_H #include +#include #define EMBEDDED_FW_SIGNATURE 0x55aa55aa #define PSP_COOKIE 0x50535024 /* 'PSP$' */ @@ -17,7 +18,7 @@ #define POSTCODE_LATE_INIT 0x03 #define POSTCODE_VERSTAGE_MAIN 0x04 -#define POSTCODE_SAVE_BUFFERS 0x0F +#define POSTCODE_SAVE_BUFFERS 0x0E #define POSTCODE_UPDATE_BOOT_REGION 0x0F #define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 @@ -28,13 +29,17 @@ #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 #define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6 #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xC9 +#define POSTCODE_CMOS_RECOVERY 0xCA #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 #define POSTCODE_LEAVING_VERSTAGE 0xF2 #define SPI_ADDR_MASK 0x00ffffff -#define DEFAULT_WORKBUF_TRANSFER_SIZE (8 * KiB) +#define MIN_TRANSFER_BUFFER_SIZE (8 * KiB) +#define MIN_WORKBUF_TRANSFER_SIZE (MIN_TRANSFER_BUFFER_SIZE - TRANSFER_INFO_SIZE) struct psp_ef_table { uint32_t signature; /* 0x55aa55aa */ diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index 149e3e2b2b..b847276d84 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -150,3 +150,17 @@ uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode) SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval); return retval; } + +uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *rsa_params) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_RSAPKCS_VERIFY, rsa_params, retval); + return retval; +} + +uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); + return retval; +} diff --git a/src/soc/amd/picasso/psp_verstage/timestamp.c b/src/soc/amd/picasso/psp_verstage/timestamp.c deleted file mode 100644 index b3b8f75f7e..0000000000 --- a/src/soc/amd/picasso/psp_verstage/timestamp.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -/* Stubs */ -void timestamp_add_now(enum timestamp_id id) -{ -} - -void timestamp_add(enum timestamp_id id, uint64_t ts) -{ -} - -uint64_t timestamp_get(void) -{ - return 0; -} diff --git a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c index c010eb626b..0bb9066f9c 100644 --- a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c @@ -102,3 +102,49 @@ vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size return VB2_SUCCESS; } + +vb2_error_t vb2ex_hwcrypto_rsa_verify_digest(const struct vb2_public_key *key, + const uint8_t *sig, const uint8_t *digest) +{ + RSAPKCS_VERIFY_PARAMS RSAParams; + uint32_t retval; + uint32_t exp = 65537; + uint32_t sig_size; + size_t digest_size; + + /* PSP only supports 2K and 4K RSA */ + if (key->sig_alg != VB2_SIG_RSA2048 && + key->sig_alg != VB2_SIG_RSA2048_EXP3 && + key->sig_alg != VB2_SIG_RSA4096) { + return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; + } + + /* PSP only supports SHA256, SHA384 and SHA512*/ + if (key->hash_alg != VB2_HASH_SHA256 && + key->hash_alg != VB2_HASH_SHA384 && + key->hash_alg != VB2_HASH_SHA512) { + return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; + } + + if (key->sig_alg == VB2_SIG_RSA2048_EXP3) + exp = 3; + sig_size = vb2_rsa_sig_size(key->sig_alg); + digest_size = vb2_digest_size(key->hash_alg); + + RSAParams.pHash = (char *)digest; + RSAParams.HashLen = digest_size; + RSAParams.pModulus = (char *)key->n; + RSAParams.ModulusSize = sig_size; + RSAParams.pExponent = (char *)&exp; + RSAParams.ExpSize = sizeof(exp); + RSAParams.pSig = (char *)sig; + + retval = svc_rsa_pkcs_verify(&RSAParams); + if (retval) { + printk(BIOS_ERR, "ERROR: HW crypto failed - errorcode: %#x\n", + retval); + return VB2_ERROR_RSA_VERIFY_DIGEST; + } + + return VB2_SUCCESS; +} diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index b6aeb1fb54..902538ff6c 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -49,6 +49,6 @@ void chipset_handle_reset(uint32_t status) { printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", __func__, status); - assert(0); + BUG(); do_cold_reset(); } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 0a337e7720..b96743101c 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -2,20 +2,91 @@ #include #include +#include +#include #include #include #include -#include #include #include +#include #include #include +#include #include #include +#include #include #include "chip.h" #include +static struct chipset_state chipset_state; + +static void fill_chipset_state(void) +{ + acpi_fill_pm_gpe_state(&chipset_state.gpe_state); + gpio_fill_wake_state(&chipset_state.gpio_state); +} + +static void add_chipset_state_cbmem(int unused) +{ + struct chipset_state *state; + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + + if (state) + memcpy(state, &chipset_state, sizeof(*state)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem); + +static const struct device_path hda_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = HD_AUDIO_DEVFN + }, +}; + +static bool devtree_hda_dev_enabled(void) +{ + const struct device *hda_dev; + + hda_dev = find_dev_nested_path(pci_root_bus(), hda_path, ARRAY_SIZE(hda_path)); + + if (!hda_dev) + return false; + + return hda_dev->enabled; +} + + +static const struct device_path sata_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_GPP_B_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = SATA_DEVFN + }, +}; + +static bool devtree_sata_dev_enabled(void) +{ + const struct device *ahci_dev; + + ahci_dev = find_dev_nested_path(pci_root_bus(), sata_path, ARRAY_SIZE(sata_path)); + + if (!ahci_dev) + return false; + + return ahci_dev->enabled; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -44,6 +115,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->stapm_time_constant = config->stapm_time_constant; } + mcfg->ccx_down_core_mode = config->downcore_mode; + mcfg->ccx_disable_smt = config->smt_disable; + mcfg->sustained_power_limit = config->sustained_power_limit; mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time; mcfg->thermctl_limit = config->thermctl_limit; @@ -63,6 +137,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; + mcfg->hd_audio_enable = devtree_hda_dev_enabled(); + mcfg->sata_enable = devtree_sata_dev_enabled(); } asmlinkage void car_stage_entry(void) @@ -79,6 +155,9 @@ asmlinkage void car_stage_entry(void) u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + /* Snapshot chipset state prior to any FSP call. */ + fill_chipset_state(); + post_code(0x43); fsp_memory_init(s3_resume); soc_update_mrc_cache(); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 1c069282af..174cddc487 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -12,7 +12,50 @@ #include #include #include +#include +#include "chip.h" +enum { + ALIB_DPTCI_FUNCTION_ID = 0xc, + THERMAL_CONTROL_LIMIT_ID = 0x3, + SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, + FAST_PPT_LIMIT_PARAM_ID = 0x6, + SLOW_PPT_LIMIT_PARAM_ID = 0x7, + DPTC_TOTAL_UPDATE_PARAMS = 4, +}; + +struct dptc_param { + uint8_t id; + uint32_t value; +} __packed; + +struct dptc_input { + uint16_t size; + struct dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; +} __packed; + +#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = SUSTAINED_POWER_LIMIT_PARAM_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = FAST_PPT_LIMIT_PARAM_ID, \ + .value = _fast, \ + }, \ + { \ + .id = SLOW_PPT_LIMIT_PARAM_ID, \ + .value = _slow, \ + }, \ + }, \ + } /* * * +--------------------------------+ @@ -72,6 +115,7 @@ static void read_resources(struct device *dev) unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; + struct resource *gnb_apic; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -129,6 +173,65 @@ static void read_resources(struct device *dev) printk(BIOS_ERR, "Error: failed to set resources for type %d\n", res->type); } + + /* GNB IOAPIC resource */ + gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic->base = GNB_IO_APIC_ADDR; + gnb_apic->size = 0x00001000; + gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) +{ + /* Name (buf_name, Buffer(size) {...} */ + acpigen_write_name(buf_name); + acpigen_write_byte_buffer(buffer, size); + + /* \_SB.ALIB(0xc, buf_name) */ + acpigen_emit_namestring("\\_SB.ALIB"); + acpigen_write_integer(ALIB_DPTCI_FUNCTION_ID); + acpigen_emit_namestring(buf_name); +} + +static void acipgen_dptci(void) +{ + const config_t *config = config_of_soc(); + + if (!config->dptc_enable) + return; + + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit, + config->sustained_power_limit, + config->fast_ppt_limit, + config->slow_ppt_limit); + struct dptc_input tablet_mode_input = DPTC_INPUTS( + config->thermctl_limit_tablet_mode, + config->sustained_power_limit_tablet_mode, + config->fast_ppt_limit_tablet_mode, + config->slow_ppt_limit_tablet_mode); + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Method(DPTC, 0, Serialized) */ + acpigen_write_method_serialized("DPTC", 0); + + /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); + + dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, + sizeof(tablet_mode_input)); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, sizeof(default_input)); + + acpigen_pop_len(); /* Else */ + + acpigen_pop_len(); /* Method DPTC */ + acpigen_pop_len(); /* Scope \_SB */ } /* Used by \_SB.PCI0._CRS */ @@ -156,6 +259,7 @@ static void root_complex_fill_ssdt(const struct device *device) */ acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); acpigen_pop_len(); + acipgen_dptci(); } static struct device_operations root_complex_operations = { diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index cb22195546..9772e9bc31 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -18,13 +18,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -233,7 +233,6 @@ void sb_enable(struct device *dev) static void sb_init_acpi_ports(void) { u32 reg; - msr_t cst_addr; /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. @@ -244,11 +243,6 @@ static void sb_init_acpi_ports(void) pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_SB.CP00, 6 bytes */ - cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; - wrmsr(MSR_CSTATE_ADDRESS, cst_addr); - if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ pm_write16(PM_ACPI_SMI_CMD, APM_CNT); @@ -279,76 +273,99 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - static void set_nvs_sws(void *unused) { - struct soc_power_reg *sws; + struct chipset_state *state; struct global_nvs *gnvs; - int index; - sws = cbmem_find(CBMEM_ID_POWER_STATE); - if (sws == NULL) + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state == NULL) return; gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; - index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; + acpi_fill_gnvs(gnvs, &state->gpe_state); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); -void southbridge_init(void *chip_info) +/* + * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks + * and unneeded for Raven/Picasso so gate them to save power. + */ +static void al2ahb_clock_gate(void) { - i2c_soc_init(); - sb_init_acpi_ports(); - acpi_clear_pm1_status(); + uint8_t al2ahb_val; + uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; + + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); + al2ahb_val |= AL2AHB_CLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); + al2ahb_val |= AL2AHB_HCLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); } -static void set_sb_final_nvs(void) +/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +static void gpp_clk_setup(void) { - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; + const struct soc_amd_picasso_config *cfg = config_of_soc(); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - gnvs->aoac.ut2e = is_aoac_device_enabled(FCH_AOAC_DEV_UART2); - gnvs->aoac.ut3e = is_aoac_device_enabled(FCH_AOAC_DEV_UART3); - gnvs->aoac.espi = 1; + /* look-up table to be able to iterate over the PCIe clock output settings */ + const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { + GPP_CLK0_REQ_SHIFT, + GPP_CLK1_REQ_SHIFT, + GPP_CLK2_REQ_SHIFT, + GPP_CLK3_REQ_SHIFT, + GPP_CLK4_REQ_SHIFT, + GPP_CLK5_REQ_SHIFT, + GPP_CLK6_REQ_SHIFT, + }; + + uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + + for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { + gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); + /* + * The remapping of values is done so that the default of the enum used for the + * devicetree settings is the clock being enabled, so that a missing devicetree + * configuration for this will result in an always active clock and not an + * inactive PCIe clock output. + */ + switch (cfg->gpp_clk_config[i]) { + case GPP_CLK_REQ: + gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_OFF: + gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_ON: + default: + gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); + } + } + + misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); +} + +void southbridge_init(void *chip_info) +{ + struct chipset_state *state; + + i2c_soc_init(); + sb_init_acpi_ports(); + + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state) { + acpi_pm_gpe_add_events_print_events(&state->gpe_state); + gpio_add_events(&state->gpio_state); + } + acpi_clear_pm_gpe_status(); + + al2ahb_clock_gate(); + + gpp_clk_setup(); } void southbridge_final(void *chip_info) @@ -358,8 +375,6 @@ void southbridge_final(void *chip_info) if (CONFIG(MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); - - set_sb_final_nvs(); } /* diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index a86080cb4c..8a541fc4a2 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -7,6 +7,10 @@ static unsigned long mhz; +/* Use this default TSC frequency when it can not be correctly calculated. + Higher numbers are safer as it will result in longer delays using TSC */ +#define TSC_DEFAULT_FREQ_MHZ 4000 + unsigned long tsc_freq_mhz(void) { msr_t msr; @@ -22,9 +26,19 @@ unsigned long tsc_freq_mhz(void) if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); - cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; + cpufid = (msr.lo & 0xff); + cpudid = (msr.lo & 0x3f00) >> 8; + + /* normally core frequency is calculated as (fid * 25) / (did / 8) */ + if (!cpudid) { + mhz = TSC_DEFAULT_FREQ_MHZ; + printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); + } else if ((cpudid >= 8) && (cpudid < 0x3c)) { + mhz = (200 * cpufid) / cpudid; + } else { + mhz = 25 * cpufid; + printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid); + } - mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); return mhz; } diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d892333ca1..1aa42ef47b 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -9,6 +9,7 @@ #include #include #include +#include static const struct _uart_info { uintptr_t base; @@ -32,25 +33,69 @@ static const struct _uart_info { } }, }; -uintptr_t get_uart_base(int idx) +uintptr_t get_uart_base(unsigned int idx) { - if (idx < 0 || idx >= ARRAY_SIZE(uart_info)) + if (idx >= ARRAY_SIZE(uart_info)) return 0; return uart_info[idx].base; } -void clear_uart_legacy_config(void) +static bool get_uart_idx(uintptr_t base, unsigned int *idx) { - write16((void *)FCH_UART_LEGACY_DECODE, 0); + for (unsigned int i = 0; i < ARRAY_SIZE(uart_info); i++) { + if (base == uart_info[i].base) { + *idx = i; + return true; + } + } + + return false; } -void set_uart_config(int idx) +void clear_uart_legacy_config(void) +{ + write16((void *)FCH_LEGACY_UART_DECODE, 0); +} + +void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx) +{ + uint16_t uart_legacy_decode; + uint8_t uart_map_offset; + + if (uart_idx >= ARRAY_SIZE(uart_info) || range_idx >= ARRAY_SIZE(uart_info)) + return; + + uart_legacy_decode = read16((void *)FCH_LEGACY_UART_DECODE); + /* Map uart_idx to io range_idx */ + uart_map_offset = range_idx * FCH_LEGACY_UART_MAP_SIZE + FCH_LEGACY_UART_MAP_SHIFT; + uart_legacy_decode &= ~(FCH_LEGACY_UART_MAP_MASK << uart_map_offset); + uart_legacy_decode |= uart_idx << uart_map_offset; + /* Enable io range */ + uart_legacy_decode |= 1 << range_idx; + write16((void *)FCH_LEGACY_UART_DECODE, uart_legacy_decode); +} + +static void enable_uart_legacy_decode(uintptr_t base) +{ + unsigned int idx; + const uint8_t range_idx[ARRAY_SIZE(uart_info)] = { + FCH_LEGACY_UART_RANGE_3F8, + FCH_LEGACY_UART_RANGE_2F8, + FCH_LEGACY_UART_RANGE_3E8, + FCH_LEGACY_UART_RANGE_2E8, + }; + + if (get_uart_idx(base, &idx)) { + set_uart_legacy_config(idx, range_idx[idx]); + } +} + +void set_uart_config(unsigned int idx) { uint32_t uart_ctrl; - uint16_t uart_leg; - if (idx < 0 || idx >= ARRAY_SIZE(uart_info)) + if (idx >= ARRAY_SIZE(uart_info)) return; program_gpios(uart_info[idx].mux, 2); @@ -61,20 +106,6 @@ void set_uart_config(int idx) sm_pci_write32(SMB_UART_CONFIG, uart_ctrl); } - if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) { - /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */ - - /* TODO: make clearer once PPR is updated */ - uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14); - if (idx == 0) - uart_leg |= 1 << FCH_LEGACY_3F8_SH; - else if (idx == 1) - uart_leg |= 1 << FCH_LEGACY_2F8_SH; - else if (idx == 2) - uart_leg |= 1 << FCH_LEGACY_3E8_SH; - - write16((void *)FCH_UART_LEGACY_DECODE, uart_leg); - } } static const char *uart_acpi_name(const struct device *dev) @@ -96,7 +127,7 @@ static const char *uart_acpi_name(const struct device *dev) /* Even though this is called enable, it gets called for both enabled and disabled devices. */ static void uart_enable(struct device *dev) { - int dev_id; + unsigned int dev_id; switch (dev->path.mmio.addr) { case APU_UART0_BASE: @@ -119,6 +150,8 @@ static void uart_enable(struct device *dev) if (dev->enabled) { power_on_aoac_device(dev_id); wait_for_aoac_enabled(dev_id); + if (CONFIG(PICASSO_UART_LEGACY)) + enable_uart_legacy_decode(dev->path.mmio.addr); } else { power_off_aoac_device(dev_id); } diff --git a/src/soc/amd/picasso/uart_console.c b/src/soc/amd/picasso/uart_console.c index 3ab2a70920..b5c5159486 100644 --- a/src/soc/amd/picasso/uart_console.c +++ b/src/soc/amd/picasso/uart_console.c @@ -8,7 +8,7 @@ * be provided exactly once and only by the UART that is used for console. */ -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return get_uart_base(idx); } diff --git a/src/soc/amd/picasso/xhci.c b/src/soc/amd/picasso/xhci.c index 171002c0b4..97a012e03f 100644 --- a/src/soc/amd/picasso/xhci.c +++ b/src/soc/amd/picasso/xhci.c @@ -52,5 +52,4 @@ static void configure_xhci_sci(void *unused) gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); } - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd990db..2ef90eb5f4 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -9,10 +9,7 @@ if SOC_AMD_STONEYRIDGE config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC @@ -41,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 0d7b5d1578..16597e1eda 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -148,7 +148,7 @@ PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key ifeq ($(CONFIG_USE_PSPSECUREOS),y) ###2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin +PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin ###12 PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) @@ -184,7 +184,7 @@ OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) ifeq ($(CONFIG_USE_PSPSECUREOS),y) -OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) +OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) endif @@ -204,7 +204,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(PSPSECUREOS_FILE)) \ $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ $(call strip_quotes, $(SMUFWM_FN_FILE)) \ @@ -225,7 +225,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_SMUFWM_FILE) \ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPSECUREOS_FILE) \ $(OPT_PSPNVRAM_FILE) \ $(OPT_PSPSECUREDEBUG_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ @@ -238,7 +238,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_SMUFWM_FN_FILE) \ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPSECUREOS_FILE) \ $(OPT_PSPNVRAM_FILE) \ $(OPT_PSPSECUREDEBUG_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 10e1690852..e62f235952 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -119,7 +119,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -127,7 +126,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 2865352506..0acc408f0f 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -14,25 +14,15 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Miscellaneous */ Offset (0x00), PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community - TMPS, 8, // 0x2B - Temperature Sensor ID - TLVL, 8, // 0x2C - Throttle Level Limit - FLVL, 8, // 0x2D - Current FAN Level - TCRT, 8, // 0x2E - Critical Threshold - TPSV, 8, // 0x2F - Passive Threshold - TMAX, 8, // 0x30 - CPU Tj_max - Offset (0x34), // 0x34 - AOAC Device Enables + LIDS, 8, // 0x01 - LID State + PWRS, 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold + Offset (0x20), // 0x20 - AOAC Device Enables , 5, IC0E, 1, // I2C0, 5 IC1E, 1, // I2C1, 6 @@ -51,11 +41,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve) , 2, ESPI, 1, // ESPI, 27 , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR + FW00, 16, // 0x24 - xHCI FW ROM addr, boot RAM + FW02, 16, // 0x26 - xHCI FW ROM addr, Instruction RAM + FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM + FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x30 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 64e87486cb..1820f7a3bf 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -75,13 +75,6 @@ Name(CRES, ResourceTemplate() { 0x0000, /* translation */ 0x0cf8 /* length */ ) - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03b0, /* range minimum */ - 0x03df, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ - ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, /* address granularity */ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 844ff1bf2d..63db7d4b16 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -3,6 +3,7 @@ #ifndef __STONEYRIDGE_I2C_H__ #define __STONEYRIDGE_I2C_H__ +#include #include struct soc_amd_i2c_save { diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 864cfffa1a..9c479c6e62 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -17,32 +17,22 @@ struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ - uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ - uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad relative offset */ - uint8_t tmps; /* 0x2B - Temperature Sensor ID */ - uint8_t tlvl; /* 0x2C - Throttle Level Limit */ - uint8_t flvl; /* 0x2D - Current FAN Level */ - uint8_t tcrt; /* 0x2E - Critical Threshold */ - uint8_t tpsv; /* 0x2F - Passive Threshold */ - uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t pad1[3]; - aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ + uint8_t pad1[6]; + aoac_devs_t aoac; /* 0x20 - AOAC device enables */ + uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */ + uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x30 - EHCI BAR */ + uint8_t unused[204]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index a58488ba3c..f7cacea37f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -3,7 +3,6 @@ #ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ #define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ - #define SMI_GEVENTS 24 #define SCIMAPS 58 #define SCI_GPES 32 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 80c258f442..85df0b3b3a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -318,14 +318,6 @@ typedef struct aoac_devs { unsigned int :4; } __packed aoac_devs_t; -struct soc_power_reg { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint16_t wake_from; -}; - #define XHCI_FW_SIG_OFFSET 0xc #define XHCI_FW_ADDR_OFFSET 0x6 #define XHCI_FW_SIZE_OFFSET 0x8 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c6fdc60073..63ab6b4e81 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -146,7 +146,6 @@ static void set_resources(struct device *dev) struct bus *bus; struct resource *res; - /* do we need this? */ create_vga_resource(dev); @@ -232,7 +231,6 @@ static void patch_ssdt_processor_scope(acpi_header_t *ssdt) ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } - static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 15219b42a2..267f747b4f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -256,47 +257,34 @@ void sb_clk_output_48Mhz(u32 osc) misc_write32(MISC_CLK_CNTL1, ctrl); } -static uintptr_t sb_init_spi_base(void) +static void sb_init_spi_base(void) { - uintptr_t base; - /* Make sure the base address is predictable */ - base = lpc_get_spibase(); - - if (base) - return base; - - lpc_set_spibase(SPI_BASE_ADDRESS); + if (ENV_X86) + lpc_set_spibase(SPI_BASE_ADDRESS); lpc_enable_spi_rom(SPI_ROM_ENABLE); - - return SPI_BASE_ADDRESS; } void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = sb_init_spi_base(); - write16((void *)(base + SPI100_SPEED_CONFIG), + spi_write16(SPI100_SPEED_CONFIG, (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100); } void sb_disable_4dw_burst(void) { - uintptr_t base = sb_init_spi_base(); - write16((void *)(base + SPI100_HOST_PREF_CONFIG), - read16((void *)(base + SPI100_HOST_PREF_CONFIG)) - & ~SPI_RD4DW_EN_HOST); + spi_write16(SPI100_HOST_PREF_CONFIG, + spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); } void sb_read_mode(u32 mode) { - uintptr_t base = sb_init_spi_base(); - write32((void *)(base + SPI_CNTRL0), - (read32((void *)(base + SPI_CNTRL0)) - & ~SPI_READ_MODE_MASK) | mode); + spi_write32(SPI_CNTRL0, + (spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); } static void setup_spread_spectrum(int *reboot) @@ -513,59 +501,36 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - static void set_nvs_sws(void *unused) { - struct soc_power_reg *sws; + struct acpi_pm_gpe_state *state; struct global_nvs *gnvs; - int index; - sws = cbmem_find(CBMEM_ID_POWER_STATE); - if (sws == NULL) + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state == NULL) return; gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; - index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; + acpi_fill_gnvs(gnvs, state); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); void southbridge_init(void *chip_info) { + struct acpi_pm_gpe_state *state; + sb_init_acpi_ports(); - acpi_clear_pm1_status(); + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + if (state) { + acpi_fill_pm_gpe_state(state); + acpi_pm_gpe_add_events_print_events(state); + } + + acpi_clear_pm_gpe_status(); } static void set_sb_final_nvs(void) diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index ab129c5f05..73346ab658 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -3,7 +3,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) return 0; diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.c index 0a6be32366..e415a854ab 100644 --- a/src/soc/cavium/cn81xx/clock.c +++ b/src/soc/cavium/cn81xx/clock.c @@ -39,7 +39,6 @@ u64 thunderx_get_ref_clock(void) return PLL_REF_CLK; } - /** * Returns the I/O clock speed in Hz */ diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h index 61e00d9cab..5735a80b06 100644 --- a/src/soc/cavium/cn81xx/include/soc/gpio.h +++ b/src/soc/cavium/cn81xx/include/soc/gpio.h @@ -9,8 +9,6 @@ typedef u32 gpio_t; #include /* The following functions must be implemented by SoC/board code. */ - - gpio_t gpio_pin_count(void); void gpio_invert(gpio_t gpio, int value); int gpio_strap_value(gpio_t gpio); diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index 6ac85ef3b1..d9879baec6 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -51,7 +51,6 @@ check_member(cn81xx_timer, ctl_cntacr0, 0x20040); check_member(cn81xx_timer, cwd_wdog[0], 0x40000); check_member(cn81xx_timer, cwd_poke[0], 0x50000); - #define GTI_CC_CNTCR_EN (1 << 0) #define GTI_CC_CNTCR_HDBG (1 << 1) #define GTI_CC_CNTCR_FCREQ (1 << 8) diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c index 03f94d57ac..2f8537cbcd 100644 --- a/src/soc/cavium/cn81xx/uart.c +++ b/src/soc/cavium/cn81xx/uart.c @@ -47,7 +47,6 @@ struct cn81xx_uart { #define UART_FBRD_BAUD_DIVFRAC_SHIFT 0 #define UART_FBRD_BAUD_DIVFRAC_MASK 0x3f - check_member(cn81xx_uart, uctl_ctl, 0x1000); check_member(cn81xx_uart, uctl_spare1, 0x10f8); @@ -94,7 +93,7 @@ unsigned int uart_platform_refclk(void) return uart_hclk(uart); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index 80a41fa375..d9cf2e5a08 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -8,19 +8,15 @@ #include #include -DECLARE_OPTIONAL_REGION(timestamp); - __attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } __attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } - /* C code entry point for the boot block */ void bootblock_main(const uint64_t reg_x0, const uint64_t reg_pc) { - init_timer(); /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 203d804711..172a5edd8c 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -12,5 +12,4 @@ void bootblock_mainboard_init(void); void bootblock_main(const uint64_t reg_x0, const uint64_t reg_pc); - #endif /* SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig new file mode 100644 index 0000000000..3f500f33cf --- /dev/null +++ b/src/soc/intel/alderlake/Kconfig @@ -0,0 +1,216 @@ +config SOC_INTEL_ALDERLAKE + bool + help + Intel Alderlake support + +if SOC_INTEL_ALDERLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_2 + select FSP_PEIM_TO_PEIM_INTERFACE + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_202005_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + +config MAX_CPUS + int + default 24 + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x40400 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + (~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x20000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config IFD_CHIPSET + string + default "adl" + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x10000 + +config MAX_ROOT_PORTS + int + default 12 + +config MAX_PCIE_CLOCKS + int + default 12 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 7 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_UART_DEV_MAX + int + default 7 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# ADL UART source clock: 120MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x25a + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0x7fff + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config CBFS_SIZE + hex + default 0x200000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1400 + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" + +config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT + int "Debug Consent for ADL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual +endif diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc new file mode 100644 index 0000000000..d962b75079 --- /dev/null +++ b/src/soc/intel/alderlake/Makefile.inc @@ -0,0 +1,55 @@ +ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y) +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += gpio.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += gpio.c +romstage-y += meminit.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += lockdown.c +ramstage-y += me.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += soundwire.c +ramstage-y += systemagent.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c + +CPPFLAGS_common += -I$(src)/soc/intel/alderlake +CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include +endif diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c new file mode 100644 index 0000000000..ca5d726874 --- /dev/null +++ b/src/soc/intel/alderlake/acpi.c @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C6_SHORT_LAT, /* 3 */ + C_STATE_C6_LONG_LAT, /* 4 */ + C_STATE_C7_SHORT_LAT, /* 5 */ + C_STATE_C7_LONG_LAT, /* 6 */ + C_STATE_C7S_SHORT_LAT, /* 7 */ + C_STATE_C7S_LONG_LAT, /* 8 */ + C_STATE_C8, /* 9 */ + C_STATE_C9, /* 10 */ + C_STATE_C10, /* 11 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static const acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = {}, + [C_STATE_C1] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C8_LATENCY, + .power = C8_POWER, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C9_LATENCY, + .power = C9_POWER, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C10_LATENCY, + .power = C10_POWER, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_non_s0ix[] = { + C_STATE_C1, + C_STATE_C6_LONG_LAT, + C_STATE_C7S_LONG_LAT +}; + +static int cstate_set_s0ix[] = { + C_STATE_C1, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + int *set; + int i; + + config_t *config = config_of_soc(); + + int is_s0ix_enable = config->s0ix_enable; + + if (is_s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } + + for (i = 0; i < *entries; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + return map; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + config_t *config = config_of_soc(); + + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, cores_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + config_t *config = config_of_soc(); + + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + if (config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +uint32_t soc_read_sci_irq_select(void) +{ + return read32((void *)soc_read_pmc_base() + IRQ_REG); +} + +static unsigned long soc_fill_dmar(unsigned long current) +{ + const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + const uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; + const bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; + + if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 5, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (is_dev_enabled(tbt_dev)) { + const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; + const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; + if (tbtbar && tbten) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + } + + /* Add RMRR entry */ + if (is_dev_enabled(igfx_dev)) { + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + + return current; +} + +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + config_t *config = config_of_soc(); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + if (CONFIG(CONSOLE_CBMEM)) + /* Update the mem console pointer. */ + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, + const struct chipset_power_state *ps) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + return generic_pm1_en; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_HIGH; +} + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} diff --git a/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl b/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl new file mode 100644 index 0000000000..3c65058c64 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x1 +#define B_ICLK_PCR_REQUEST 0x2 + +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + +Scope (\_SB.PCI0) { + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 + /* + * Helper function for Read And Or Write + * Arg0 : Clock source select + * Arg1 : And data + * Arg2 : Or data + */ + Method (RAOW, 3, Serialized) + { + OperationRegion (ICLK, SystemMemory, (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 + } + + /* + * Clock control Method + * Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5) + * Arg1: Frequency select (0: 24MHz, 1: 19.2MHz) + */ + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) + } +} diff --git a/src/soc/intel/alderlake/acpi/dptf.asl b/src/soc/intel/alderlake/acpi/dptf.asl new file mode 100644 index 0000000000..5b30886af8 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/dptf.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below are the unique ACPI Device IDs for thermal/dptf on Alder Lake SoC. */ +/* DPTF ACPI Device ID */ +#define DPTF_DPTF_DEVICE "INTC1041" +/* Generic ACPI Device ID for TSR0/1/2/3 and charger */ +#define DPTF_GEN_DEVICE "INTC1046" +/* Fan ACPI Device ID */ +#define DPTF_FAN_DEVICE "INTC1048" diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl new file mode 100644 index 0000000000..e21f6d5481 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 5*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} + +/* GPIO Power Management bits */ +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0}) + +/* + * Save GPIO Power Management bits + */ +Method (SGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + Local1 = GPID (Local0) + GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG) + } +} + +/* + * Restore GPIO Power Management bits + */ +Method (RGPM, 0, Serialized) +{ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, DerefOf(GPMB[Local0])) + } +} + +/* + * Save current setting of GPIO Power Management bits and + * enable all Power Management bits for all communities + */ +Method (EGPM, 0, Serialized) +{ + /* Save current setting and will restore it when resuming */ + SGPM () + /* Enable PM bits */ + For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) + { + CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG) + } +} diff --git a/src/soc/intel/alderlake/acpi/pch_hda.asl b/src/soc/intel/alderlake/acpi/pch_hda.asl new file mode 100644 index 0000000000..13b4d3ddd0 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/pch_hda.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (Arg0 == ^UUID) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (Arg2 == 0) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (Arg2 == 1) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/alderlake/acpi/pci_irqs.asl b/src/soc/intel/alderlake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..49e452f12b --- /dev/null +++ b/src/soc/intel/alderlake/acpi/pci_irqs.asl @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include + +Name (PICP, Package () { + /* D31: HDA, SMBUS, TRACEHUB */ + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, + Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, + Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, + Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, + Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, + Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, + Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, + Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, + Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, + Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, + Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, + Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, SATA_IRQ }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, + Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, + Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, + Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, + Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ }, + Package(){0x0010FFFF, 6, 0, THC0_IRQ }, + Package(){0x0010FFFF, 7, 0, THC1_IRQ }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, PEG_IRQ }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, IPU_IRQ }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, +}) + +Name (PICN, Package () { + /* D31: HDA, SMBUS, TRACEHUB */ + Package(){0x001FFFFF, 3, 0, 11 }, + Package(){0x001FFFFF, 4, 0, 11 }, + Package(){0x001FFFFF, 7, 0, 11 }, + /* D30: UART0, UART1, SPI0, SPI1 */ + Package(){0x001EFFFF, 0, 0, 11 }, + Package(){0x001EFFFF, 1, 0, 10 }, + Package(){0x001EFFFF, 2, 0, 11 }, + Package(){0x001EFFFF, 3, 0, 11 }, + /* D29: RP9 ~ RP12 */ + Package(){0x001DFFFF, 0, 0, 11 }, + Package(){0x001DFFFF, 1, 0, 10 }, + Package(){0x001DFFFF, 2, 0, 11 }, + Package(){0x001DFFFF, 3, 0, 11 }, + /* D28: RP1 ~ RP8 */ + Package(){0x001CFFFF, 0, 0, 11 }, + Package(){0x001CFFFF, 1, 0, 10 }, + Package(){0x001CFFFF, 2, 0, 11 }, + Package(){0x001CFFFF, 3, 0, 11 }, + Package(){0x001CFFFF, 4, 0, 11 }, + Package(){0x001CFFFF, 5, 0, 10 }, + Package(){0x001CFFFF, 6, 0, 11 }, + Package(){0x001CFFFF, 7, 0, 11 }, + /* D25: I2C4, I2C5, UART2 */ + Package(){0x0019FFFF, 0, 0, 11 }, + Package(){0x0019FFFF, 1, 0, 10 }, + Package(){0x0019FFFF, 2, 0, 11 }, + /* D23: SATA */ + Package(){0x0017FFFF, 0, 0, 11 }, + /* D22: CSME */ + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 4, 0, 11 }, + Package(){0x0016FFFF, 5, 0, 10 }, + /* D21: I2C0 ~ I2C3 */ + Package(){0x0015FFFF, 0, 0, 11 }, + Package(){0x0015FFFF, 1, 0, 10 }, + Package(){0x0015FFFF, 2, 0, 11 }, + Package(){0x0015FFFF, 3, 0, 11 }, + /* D20: xHCI, xDCI, CNVI_WIFI */ + Package(){0x0014FFFF, 0, 0, 11 }, + Package(){0x0014FFFF, 1, 0, 10 }, + Package(){0x0014FFFF, 3, 0, 11 }, + /* D19: SPI3 */ + Package(){0x0013FFFF, 0, 0, 11 }, + /* D18: ISH, SPI2 */ + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 6, 0, 11 }, + /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0010FFFF, 2, 0, 11 }, + Package(){0x0010FFFF, 6, 0, 11 }, + Package(){0x0010FFFF, 7, 0, 11 }, + /* D13: xHCI, xDCI */ + Package(){0x000DFFFF, 0, 0, 11 }, + Package(){0x000DFFFF, 1, 0, 10 }, + /* D8: GNA */ + Package(){0x0008FFFF, 0, 0, 11 }, + /* D7: TBT PCIe */ + Package(){0x0007FFFF, 0, 0, 11 }, + Package(){0x0007FFFF, 1, 0, 10 }, + Package(){0x0007FFFF, 2, 0, 11 }, + Package(){0x0007FFFF, 3, 0, 11 }, + /* D6: PEG60 */ + Package(){0x0006FFFF, 0, 0, 11 }, + /* D5: IPU Device */ + Package(){0x0005FFFF, 0, 0, 11 }, + /* D4: Thermal Device */ + Package(){0x0004FFFF, 0, 0, 11 }, + /* D2: IGFX */ + Package(){0x0002FFFF, 0, 0, 11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl new file mode 100644 index 0000000000..a19feb7168 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/alderlake/acpi/serialio.asl b/src/soc/intel/alderlake/acpi/serialio.asl new file mode 100644 index 0000000000..f7bf452058 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/serialio.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (SPI3) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Serial IO SPI Controller 3") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl new file mode 100644 index 0000000000..42f3b129a9 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include + +/* PCH clock */ +#include "camera_clock_ctl.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* GFX 00:02.0 */ +#include + +/* ESPI 0:1f.0 */ +#include + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include + +/* ISH 0:12.0 */ +#include + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include + +/* PMC Core*/ +#include + +/* GbE 0:1f.6 */ +#include diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl new file mode 100644 index 0000000000..1b13260bc6 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -0,0 +1,964 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +/* + * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI), + * USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers. + * PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1. + */ +#define TCSS_TBT_PCIE0_RP0 0 +#define TCSS_TBT_PCIE0_RP1 1 +#define TCSS_TBT_PCIE0_RP2 2 +#define TCSS_TBT_PCIE0_RP3 3 +#define TCSS_XHCI 4 +#define TCSS_XDCI 5 +#define TCSS_DMA0 6 +#define TCSS_DMA1 7 + +/* + * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + * Command code 0x15 + * Description: Gateway command for handling TCSS DEVEN clear/restore. + * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from + * a pre-defined set of subcommands. + */ +#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015 +#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */ +#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */ +#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100 + +#define MCHBAR_TCSS_DEVEN_OFFSET 0x7090 + +#define REVISION_ID 1 +#define UNRECOGNIZED_UUID 0x4 +#define UNRECOGNIZED_REVISION 0x8 + +#define USB_TUNNELING 0x1 +#define DISPLAY_PORT_TUNNELING 0x2 +#define PCIE_TUNNELING 0x4 +#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8 + +Scope (\_SB) +{ + /* Device base address */ + Method (BASE, 1) + { + Local0 = Arg0 & 0x7 /* Function number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local2 = (Local0 << 12) + (Local1 << 15) + Local3 = \_SB.PCI0.GPCB() + Local2 + Return (Local3) + } + + /* + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be + * found in Device 31, Function 2, Offset 40h. + */ + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) + Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ + , 19, + CPWS, 1, /* CPU WAKE STATUS */ + Offset(0x7C), /* 0x7C, General Purpose Event 0 Enable [127:96] */ + , 19, + CPWE, 1 /* CPU WAKE EN */ + } + + Name (C2PW, 0) /* Set default value to 0. */ + + /* + * C2PM (CPU to PCH Method) + * + * This object is Enable/Disable GPE_CPU_WAKE_EN. + * Arguments: (4) + * Arg0 - An Integer containing the device wake capability + * Arg1 - An Integer containing the target system state + * Arg2 - An Integer containing the target device state + * Arg3 - An Integer containing the request device type + * Return Value: + * return 0 + */ + Method (C2PM, 4, NotSerialized) + { + Local0 = 1 << Arg3 + /* This method is used to enable/disable wake from Tcss Device (WKEN). */ + If (Arg0 && Arg1) + { /* If entering Sx and enabling wake, need to enable WAKE capability. */ + If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */ + If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */ + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { /* If Staying in S0 or Disabling Wake. */ + If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */ + /* If CPU WAKE EN is not set, Set it. */ + If (CPWE == 0) { + /* If CPU WAKE STATUS is set, Clear it. */ + If (CPWS) { + /* Clear CPU WAKE STATUS by writing 1. */ + CPWS = 1 + } + CPWE = 1 /* Set CPU WAKE EN by writing 1. */ + } + If ((C2PW & Local0) == 0) { + /* Set Corresponding Device En BIT in C2PW. */ + C2PW |= Local0 + } + } Else { + /* + * Disable runtime PME, either because staying in D0 or + * disabling wake. + */ + If ((C2PW & Local0) != 0) { + /* + * Clear Corresponding Device En BIT in C2PW. + */ + C2PW &= ~Local0 + } + If ((CPWE != 0) && (C2PW == 0)) { + /* + * If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN + * by writing 0. + */ + CPWE = 0 + } + } + } + Return (0) + } + + Method (_OSC, 4, Serialized) + { + CreateDWordField (Arg3, 0, CDW1) + If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) { + /* Platform-Wide _OSC Capabilities + * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities + * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4 + * support. The OS sets this bit to indicate support for an OSPM-native + * USB4 Connection Manager which handles USB4 connection events and + * link management. + */ + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + } + Return (Arg3) + } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { + /* + * Operating System Capabilities for USB4 + * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. + * Third DWORD: OSPM control field for USB4. + * bit 0: USB tunneling + * bit 1: DisplayPort tunneling + * bit 2: PCIe tunneling + * bit 3: Inter-domain USB4 internet protocol + * bit 31:4: reserved + * Return: The platform acknowledges the capabilities buffer by + * returning a buffer of DWORD of the same length. Masked/Cleared bits + * in the control field indicate that the platform does not permit OSPM + * control of the respectively capabilities or features. + */ + CreateDWordField (Arg3, 8, CDW3) + Local0 = CDW3 + + If (Arg1 != REVISION_ID) { + CDW1 |= UNRECOGNIZED_REVISION + Return (Arg3) + } + Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | + INTER_DOMAIN_USB4_INTERNET_PROTOCOL + CDW3 = Local0 + Return (Arg3) + } Else { + CDW1 |= UNRECOGNIZED_UUID + Return (Arg3) + } + } +} + +Scope (_GPE) +{ + /* PCI Express Hot-Plug wake event */ + Method (_L61, 0, NotSerialized) + { + /* + * Delay for 100ms to meet the timing requirements of the PCI Express Base + * Specification, Revision 1.0A, Section 6.6 ("...software must wait at least + * 100ms from the end of reset of one or more device before it is permitted + * to issue Configuration Requests to those devices"). + */ + Sleep (100) + + If (CondRefOf (\_SB.PCI0.TXHC)) { + /* Invoke PCIe root ports wake event handler */ + \_SB.PCI0.TRP0.HPEV() + \_SB.PCI0.TRP1.HPEV() + \_SB.PCI0.TRP2.HPEV() + \_SB.PCI0.TRP3.HPEV() + } + + /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { + If (\_SB.PCI0.TRP0.PDCX) { + /* Clear all status bits */ + \_SB.PCI0.TRP0.PDCX = 1 + \_SB.PCI0.TRP0.HPSX = 1 + /* + * Intercept Presence Detect Changed interrupt and make sure + * the L0s is disabled on empty slots. + */ + If (!\_SB.PCI0.TRP0.PDSX) { + /* + * The PCIe slot is empty, so disable L0s on hot unplug. + */ + \_SB.PCI0.TRP0.L0SE = 0 + } + /* Performs proper notification to the OS. */ + Notify (\_SB.PCI0.TRP0, 0) + } Else { + /* False event. Clear Hot-Plug status, then exit. */ + \_SB.PCI0.TRP0.HPSX = 1 + } + } + + /* Check Root Port 1 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) { + If (\_SB.PCI0.TRP1.PDCX) { + \_SB.PCI0.TRP1.PDCX = 1 + \_SB.PCI0.TRP1.HPSX = 1 + If (!\_SB.PCI0.TRP1.PDSX) { + \_SB.PCI0.TRP1.L0SE = 0 + } + Notify (\_SB.PCI0.TRP1, 0) + } Else { + \_SB.PCI0.TRP1.HPSX = 1 + } + } + + /* Check Root Port 2 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) { + If (\_SB.PCI0.TRP2.PDCX) { + \_SB.PCI0.TRP2.PDCX = 1 + \_SB.PCI0.TRP2.HPSX = 1 + If (!\_SB.PCI0.TRP2.PDSX) { + \_SB.PCI0.TRP2.L0SE = 0 + } + Notify (\_SB.PCI0.TRP2, 0) + } Else { + \_SB.PCI0.TRP2.HPSX = 1 + } + } + + /* Check Root Port 3 for a Hot Plug Event if the port is enabled */ + If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) { + If (\_SB.PCI0.TRP3.PDCX) { + \_SB.PCI0.TRP3.PDCX = 1 + \_SB.PCI0.TRP3.HPSX = 1 + If (!\_SB.PCI0.TRP3.PDSX) { + \_SB.PCI0.TRP3.L0SE = 0 + } + Notify (\_SB.PCI0.TRP3, 0) + } Else { + \_SB.PCI0.TRP3.HPSX = 1 + } + } + } + + /* PCI Express power management event */ + Method (_L69, 0, Serialized) + { + If (CondRefOf (\_SB.PCI0.TXHC)) { + If (\_SB.PCI0.TRP0.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP0, 0x2) + } + + If (\_SB.PCI0.TRP1.HPME() == 1) { + Notify (\_SB.PCI0.TDM0, 0x2) + Notify (\_SB.PCI0.TRP1, 0x2) + } + + If (\_SB.PCI0.TRP2.HPME() == 1) { + Notify (\_SB.PCI0.TDM1, 0x2) + Notify (\_SB.PCI0.TRP2, 0x2) + } + + If (\_SB.PCI0.TRP3.HPME() == 1) { + Notify (\_SB.PCI0.TDM1, 0x2) + Notify (\_SB.PCI0.TRP3, 0x2) + } + } + + /* Invoke PCIe root ports power management status handler */ + \_SB.PCI0.TRP0.HPME() + \_SB.PCI0.TRP1.HPME() + \_SB.PCI0.TRP2.HPME() + \_SB.PCI0.TRP3.HPME() + } +} + +Scope (\_SB.PCI0) +{ + Device (IOM) + { + Name (_HID, "INTC1072") + Name (_DDN, "Intel(R) Alder Lake Input Output Manager(IOM) driver") + /* IOM preserved MMIO range from 0xFBC10000 to 0xFBC11600. */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) + }) + } + + /* + * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset + * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR. + */ + OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4) + Field (TDEN, ByteAcc, NoLock, Preserve) + { + TRE0, 1, /* PCIE0_EN */ + TRE1, 1, /* PCIE1_EN */ + TRE2, 1, /* PCIE2_EN */ + TRE3, 1, /* PCIE3_EN */ + , 4, + THCE, 1, /* XHCI_EN */ + TDCE, 1, /* XDCI_EN */ + DME0, 1, /* TBT_DMA0_EN */ + DME1, 1, /* TBT_DMA1_EN */ + , 20 + } + + /* + * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset + * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR. + */ + OperationRegion (MBAR, SystemMemory, (GMHB() + 0x7100), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset(0x10), + RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */ + } + Field (MBAR, DWordAcc, NoLock, Preserve) + { + Offset(0x304), /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */ + , 31, + TCD3, 1 /* [31:31] TCSS IN D3 bit */ + } + + /* + * Operation region defined to access the pCode mailbox interface. Get the MCHBAR + * in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR. + */ + OperationRegion (PBAR, SystemMemory, (GMHB() + 0x5DA0), 0x08) + Field (PBAR, DWordAcc, NoLock, Preserve) + { + PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */ + PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */ + PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */ + , 15, /* Reserved */ + PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */ + } + + /* + * Poll pCode MailBox Ready + * + * Return 0xFF - Timeout + * 0x00 - Ready + */ + Method (PMBY, 0) + { + Local0 = 0 + While (PMBR && (Local0 < 1000)) { + Local0++ + Stall (1) + } + If (Local0 == 1000) { + Printf("Timeout occurred.") + Return (0xFF) + } + Return (0) + } + + /* + * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS + * + * Result will be updated in DATA[1:0] + * DATA[0:0] TCSS_DEVEN_CURRENT_STATE: + * 0 - TCSS Deven in normal state. + * 1 - TCSS Deven is cleared by BIOS Mailbox request. + * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS: + * 0 - IDLE. TCSS DEVEN has reached its final requested state. + * 1 - In Progress. TCSS DEVEN is currently in progress of switching state + * according to given request (bit 0 reflects source state). + * + * Return 0x00 - TCSS Deven in normal state + * 0x01 - TCSS Deven is cleared by BIOS Mailbox request + * 0x1x - TCSS Deven is in progress of switching state according to given request + * 0xFE - Command timeout + * 0xFF - Command corrupt + */ + Method (DSGS, 0) + { + If ((PMBY () == 0)) { + PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS + PMBR = 1 + If (PMBY () == 0) { + Local0 = PMBD + Local1 = PMBC + Stall (10) + If ((Local0 != PMBD) || (Local1 != PMBC)) { + Printf("pCode MailBox is corrupt.") + Return (0xFF) + } + Return (Local0) + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } + + /* + * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ + * + * Arg0 : 0 - Restore to previously saved value of TCSS DEVEN + * 1 - Save current TCSS DEVEN value and clear it + * + * Return 0x00 - MAILBOX_BIOS_CMD_CLEAR_TCSS_DEVEN command completed + * 0xFD - Input argument is invalid + * 0xFE - Command timeout + * 0xFF - Command corrupt + */ + Method (DSCR, 1) + { + If (Arg0 > 1) { + Printf("pCode MailBox is corrupt.") + Return (0xFD) + } + If ((PMBY () == 0)) { + PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE + PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ + PMBD = Arg0 + PMBR = 1 + If ((PMBY () == 0)) { + Local0 = PMBD + Local1 = PMBC + Stall (10) + If ((Local0 != PMBD) || (Local1 != PMBC)) { + Printf("pCode MailBox is corrupt.") + Return (0xFF) + } + /* Poll TCSS_DEVEN_REQUEST_STATUS, timeout value is 10ms. */ + Local0 = 0 + While ((DSGS () & 0x10) && (Local0 < 100)) { + Stall (100) + Local0++ + } + If (Local0 == 100) { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } Else { + Return (0x00) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } Else { + Printf("pCode MailBox is not ready.") + Return (0xFE) + } + } + + /* + * IOM REG BAR Base address is in offset 0x7110 in MCHBAR. + */ + Method (IOMA, 0) + { + Return (^RBAR & ~0x1) + } + + /* + * From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where + * 0x40 is the register offset. + */ + OperationRegion (IOMR, SystemMemory, (IOMA() + 0xC10000), 0x100) + Field (IOMR, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 15, + TD3C, 1, /* [15:15] Type C D3 cold bit */ + TACK, 1, /* [16:16] IOM Acknowledge bit */ + DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ + /* display is OFF, clear otherwise */ + Offset(0x70), /* Pyhsical addr is offset 0x70. */ + IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ + IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ + } + + /* + * TBT Group0 ON method + */ + Method (TG0N, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } Else { + If (\_SB.PCI0.TDM0.STAT == 0) { + /* DMA0 is in D3Cold early. */ + \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* RP0 D3 cold exit. */ + \_SB.PCI0.TRP0.D3CX() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* RP1 D3 cold exit. */ + \_SB.PCI0.TRP1.D3CX() + } + } Else { + Printf("Drop TG0N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + } + + /* + * TBT Group0 OFF method + */ + Method (TG0F, 0) + { + If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) { + Printf("TDM0 does not exist.") + } Else { + If (\_SB.PCI0.TDM0.STAT == 1) { + /* DMA0 is not in D3Cold now. */ + \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { + /* Put RP0 to D3 cold. */ + \_SB.PCI0.TRP0.D3CE() + } + If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) { + /* Put RP1 to D3 cold. */ + \_SB.PCI0.TRP1.D3CE() + } + } + } + } + + /* + * TBT Group1 ON method + */ + Method (TG1N, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } Else { + If (\_SB.PCI0.TDM1.STAT == 0) { + /* DMA1 is in D3Cold early. */ + \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */ + + Printf("Bring TBT RPs out of D3Code.") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* RP2 D3 cold exit. */ + \_SB.PCI0.TRP2.D3CX() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* RP3 D3 cold exit. */ + \_SB.PCI0.TRP3.D3CX() + } + } Else { + Printf("Drop TG1N due to it is already exit D3 cold.") + } + + /* TBT RTD3 exit 10ms delay. */ + Sleep (10) + } + } + + /* + * TBT Group1 OFF method + */ + Method (TG1F, 0) + { + If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) { + Printf("TDM1 does not exist.") + } Else { + If (\_SB.PCI0.TDM1.STAT == 1) { + /* DMA1 is not in D3Cold now */ + \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + + Printf("Push TBT RPs to D3Cold together") + If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { + /* Put RP2 to D3 cold. */ + \_SB.PCI0.TRP2.D3CE() + } + If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) { + /* Put RP3 to D3 cold */ + \_SB.PCI0.TRP3.D3CE() + } + } + } + } + + PowerResource (TBT0, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } + } + + PowerResource (TBT1, 5, 1) + { + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } + } + + Method (TCON, 0) + { + /* Reset IOM D3 cold bit if it is in D3 cold now. */ + If (TD3C == 1) /* It was in D3 cold before. */ + { + /* Reset IOM D3 cold bit. */ + TD3C = 0 /* Request IOM for D3 cold exit sequence. */ + Local0 = 0 /* Time check counter variable */ + /* Wait for ack, the maximum wait time for the ack is 100 msec. */ + While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { + /* + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ + Sleep (1) /* Delay of 1ms. */ + Local0++ + } + + If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) { + Printf("Error: Timeout occurred.") + } + Else + { + /* + * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and + * acknowledgement by IOM. + */ + TCD3 = 0 + /* + * If the TCSS Deven is cleared by BIOS Mailbox request, then + * restore to previously saved value of TCSS DEVNE. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { + If (DSGS () == 1) { + DSCR (0) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } + } + } + } + Else { + Printf("Drop TCON due to it is already exit D3 cold.") + } + } + + Method (TCOF, 0) + { + If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) + || (\_SB.PCI0.TDM1.SD3C != 0)) + { + Printf("Skip D3C entry.") + Return + } + + /* + * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and + * clear it. + */ + Local0 = 0 + While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { + If (DSGS () == 0) { + DSCR (1) + } + Local0++ + If (Local0 == 5) { + Printf("pCode mailbox command failed.") + Break + } + } + + /* + * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. + */ + TCD3 = 1 + + /* Request IOM for D3 cold entry sequence. */ + TD3C = 1 + } + + PowerResource (D3C, 5, 0) + { + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } + } + + /* + * TCSS xHCI device + */ + Device (TXHC) + { + Name (_ADR, 0x000D0000) + Name (_DDN, "North XHCI controller") + Name (_STR, Unicode ("North XHCI controller")) + Name (DCPM, TCSS_XHCI) + + Method (_STA, 0x0, NotSerialized) + { + If (THCE == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_xhci.asl" + } + + /* + * TCSS DMA0 device + */ + Device (TDM0) + { + Name (_ADR, 0x000D0002) + Name (_DDN, "TBT DMA0 controller") + Name (_STR, Unicode ("TBT DMA0 controller")) + Name (DUID, 0) /* TBT DMA number */ + Name (DCPM, TCSS_DMA0) + + Method (_STA, 0x0, NotSerialized) + { + If (DME0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_dma.asl" + } + + /* + * TCSS DMA1 device + */ + Device (TDM1) + { + Name (_ADR, 0x000D0003) + Name (_DDN, "TBT DMA1 controller") + Name (_STR, Unicode ("TBT DMA1 controller")) + Name (DUID, 1) /* TBT DMA number */ + Name (DCPM, TCSS_DMA1) + + Method (_STA, 0x0, NotSerialized) + { + If (DME1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + #include "tcss_dma.asl" + } + + /* + * TCSS PCIE Root Port #00 + */ + Device (TRP0) + { + Name (_ADR, 0x00070000) + Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP0) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE0 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #01 + */ + Device (TRP1) + { + Name (_ADR, 0x00070001) + Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP1) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE1 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #02 + */ + Device (TRP2) + { + Name (_ADR, 0x00070002) + Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP2) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE2 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } + + /* + * TCSS PCIE Root Port #03 + */ + Device (TRP3) + { + Name (_ADR, 0x00070003) + Name (TUID, 3) /* TBT PCIE RP Number 3 for RP03 */ + Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ + Name (LMSL, 0) /* PCIE LTR max snoop Latency */ + Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ + Name (DCPM, TCSS_TBT_PCIE0_RP3) + + Method (_STA, 0x0, NotSerialized) + { + If (TRE3 == 1) { + Return (0x0F) + } Else { + Return (0x0) + } + } + + Method (_INI) + { + LTEN = 0 + LMSL = 0x88C8 + LNSL = 0x88C8 + } + #include "tcss_pcierp.asl" + } +} diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl new file mode 100644 index 0000000000..da2e8fe97d --- /dev/null +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) +Field (DPME, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x84), /* 0x84, DMA CFG PM CAP */ + PMST, 2, /* 1:0, PM_STATE */ + , 6, + PMEE, 1, /* 8, PME_EN */ + , 6, + PMES, 1, /* 15, PME_STATUS */ + Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ + , 31, + INFR, 1, /* TBT NVM FW Ready */ + Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ + TB2P, 32, /* TBT to PCIe */ + P2TB, 32, /* PCIe to TBT */ + Offset(0xFC), /* 0xFC, DMA RTD3 Force Power */ + DD3E, 1, /* 0:0 DMA RTD3 Enable */ + DFPE, 1, /* 1:1 DMA Force Power */ + , 22, + DMAD, 8 /* 31:24 DMA Active Delay */ +} + +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +Method (_S0W, 0x0) +{ + Return (0x4) +} + +Method (_PR0) +{ + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +Method (_PR3) +{ + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + DD3E = 0 /* Disable DMA RTD3 */ + STAT = 0x1 +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + DD3E = 1 /* Enable DMA RTD3 */ + STAT = 0 +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_DSW, 3) +{ + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} + +Method (_DSD, 0) +{ + Return( + Package() + { + /* Thunderbolt GUID for IMR_VALID at ../drivers/acpi/property.c */ + ToUUID("C44D002F-69F9-4E7D-A904-A7BAABDF43F7"), + Package () + { + Package (2) { "IMR_VALID", 1 } + }, + + /* Thunderbolt GUID for WAKE_SUPPORTED at ../drivers/acpi/property.c */ + ToUUID("6C501103-C189-4296-BA72-9BF5A26EBE5D"), + Package () + { + Package (2) { "WAKE_SUPPORTED", 1 } + } + } + ) +} + +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0 }) +} diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl new file mode 100644 index 0000000000..abca5d1607 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -0,0 +1,340 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) +Field (PXCS, AnyAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x50), /* LCTL - Link Control Register */ + L0SE, 1, /* 0, L0s Entry Enabled */ + , 3, + LDIS, 1, /* 1, Link Disable */ + , 3, + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */ + ABPX, 1, /* 0, Attention Button Pressed */ + , 2, + PDCX, 1, /* 3, Presence Detect Changed */ + , 2, + PDSX, 1, /* 6, Presence Detect State */ + , 1, + DLSC, 1, /* 8, Data Link Layer State Changed */ + Offset(0x60), /* RSTS - Root Status Register */ + , 16, + PSPX, 1, /* 16, PME Status */ + Offset(0xA4), + D3HT, 2, /* Power State */ + Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */ + , 30, + DPGE, 1, /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */ + /* Power Gating Enable (DLSULPPGE) */ + Offset(0x5BC), /* 0x5BC, PCIE ADVMCTRL */ + , 3, + RPER, 1, /* RTD3PERST[3] */ + RPFE, 1, /* RTD3PFETDIS[4] */ +} + +Field (PXCS, AnyAcc, NoLock, WriteAsZeros) +{ + Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +/* + * _DSM Device Specific Method + * + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ +Method (_DSM, 4, Serialized) +{ + Return (Buffer() { 0x00 }) +} + +Device (PXSX) +{ + Name (_ADR, 0x00000000) + + Method (_PRW, 0) + { + Return (Package() { 0x69, 4 }) + } +} + +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + \_SB.PCI0.TDM0.SD3C = Arg1 + \_SB.PCI0.TDM1.SD3C = Arg1 +} + +Method (_PRW, 0) +{ + Return (Package() { 0x69, 4 }) +} + +/* + * Sub-Method of _L61 Hot-Plug event + * _L61 event handler should invoke this method to support HotPlug wake event from TBT RP. + */ +Method (HPEV, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && HPSX) { + If ((PDCX == 1) && (DLSC == 1)) { + /* Clear all status bits first. */ + PDCX = 1 + HPSX = 1 + + /* Perform proper notification to the OS. */ + Notify (^, 0) + } Else { + /* False event. Clear Hot-Plug Status, then exit. */ + HPSX = 1 + } + } +} + +/* + * Power Management routine for D3 + */ +Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ + +/* + * RTD3 Exit Method to bring TBT controller out of RTD3 mode. + */ +Method (D3CX, 0, Serialized) +{ + If (STAT == 0x1) { + Return + } + + RPFE = 0 /* Set RTD3PFETDIS = 0 */ + RPER = 0 /* Set RTD3PERST = 0 */ + L23R = 1 /* Set L23r2dt = 1 */ + + /* + * Poll for L23r2dt == 0. Wait for transition to Detect. + */ + Local0 = 0 + Local1 = L23R + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23R + } + STAT = 0x1 + + /* Wait for LA = 1 */ + Local0 = 0 + Local1 = LASX + While (Local1 == 0) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = LASX + } +} + +/* + * RTD3 Entry method to enable TBT controller RTD3 mode. + */ +Method (D3CE, 0, Serialized) +{ + If (STAT == 0x0) { + Return + } + + L23E = 1 /* Set L23er = 1 */ + + /* Poll until L23er == 0 */ + Local0 = 0 + Local1 = L23E + While (Local1) { + If (Local0 > 20) { + Break + } + Sleep(5) + Local0++ + Local1 = L23E + } + + STAT = 0 /* D3Cold */ + RPFE = 1 /* Set RTD3PFETDIS = 1 */ + RPER = 1 /* Set RTD3PERST = 1 */ +} + +Method (_PS0, 0, Serialized) +{ + HPEV () /* Check and handle Hot Plug SCI status. */ + If (HPEX == 1) { + HPEX = 0 /* Disable Hot Plug SCI */ + } + HPME () /* Check and handle PME SCI status */ + If (PMEX == 1) { + PMEX = 0 /* Disable Power Management SCI */ + } + + Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ +} + +Method (_PS3, 0, Serialized) +{ + /* Check it is hotplug SCI or not, then clear PDC accordingly */ + If (PDCX == 1) { + If (DLSC == 0) { + /* Clear PDC since it is not a hotplug. */ + PDCX = 1 + } + } + + If (HPEX == 0) { + HPEX = 1 /* Enable Hot Plug SCI. */ + HPEV () /* Check and handle Hot Plug SCI status. */ + } + If (PMEX == 0) { + PMEX = 1 /* Enable Power Management SCI. */ + HPME () /* Check and handle PME SCI status. */ + } +} + +Method (_DSD, 0) { + If ((TUID == 0) || (TUID == 1)) { + Return ( Package() { + /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () + { + Package (2) { "HotPlugSupportInD3", 1 }, + }, + + /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ + ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), + Package () { + Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ + /* + * UID of the TBT RP on platform, range is: 0, 1 ..., + * (NumOfTBTRP - 1). + */ + Package (2) { "UID", TUID }, + }, + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", TUID }, + } + }) + } ElseIf (TUID == 2) { + Return ( Package () { + /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () + { + Package (2) { "HotPlugSupportInD3", 1 }, + }, + + /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ + ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), + Package () { + Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ + /* + * UID of the TBT RP on platform, range is: 0, 1 ..., + * (NumOfTBTRP - 1). + */ + Package (2) { "UID", TUID }, + }, + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 0 }, + } + }) + } Else { /* TUID == 3 */ + Return ( Package () { + /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () + { + Package (2) { "HotPlugSupportInD3", 1 }, + }, + + /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ + ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), + Package () { + Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ + /* + * UID of the TBT RP on platform, range is: 0, 1 ..., + * (NumOfTBTRP - 1). + */ + Package (2) { "UID", TUID }, + }, + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 1 }, + } + }) + } +} + +Method (_S0W, 0x0, NotSerialized) +{ + Return (0x4) +} + +Method (_PR0) +{ + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +Method (_PR3) +{ + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } +} + +/* + * PCI_EXP_STS Handler for PCIE Root Port + */ +Method (HPME, 0, Serialized) +{ + If ((VDID != 0xFFFFFFFF) && (PMSX == 1)) { /* if port exists and PME SCI Status set */ + /* + * Notify child device; this will cause its driver to clear PME_Status from + * device. + */ + Notify (PXSX, 0x2) + PMSX = 1 /* clear rootport's PME SCI status */ + /* + * Consume one pending PME notification to prevent it from blocking the queue. + */ + PSPX = 1 + Return (0x01) + } + Return (0x00) +} diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl new file mode 100644 index 0000000000..acbeb30c13 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100) +Field (XPRT, ByteAcc, NoLock, Preserve) +{ + VDID, 32, + Offset(0x74), /* 0x74, XHCI CFG Power Control And Status */ + D0D3, 2, /* 0x74 BIT[1:0] */ + , 6, + PMEE, 1, /* PME Enable */ + , 6, + PMES, 1, /* PME Status */ +} + +Method (_PS0, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 1) { + /* Clear PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 0 + } +} + +Method (_PS3, 0, Serialized) +{ + If (\_SB.PCI0.TXHC.PMEE == 0) { + /* Set PME_EN of CPU xHCI */ + \_SB.PCI0.TXHC.PMEE = 1 + } +} + +Method (_S0W, 0x0, NotSerialized) +{ + Return (0x4) +} + +/* + * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE + * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. + */ +Name (SD3C, 0) + +Method (_PR0) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +Method (_PR3) +{ + Return (Package () { \_SB.PCI0.D3C }) +} + +/* + * XHCI controller _DSM method + */ +Method (_DSM, 4, serialized) +{ + Return (Buffer() { 0 }) +} + +/* + * _SXD and _SXW methods + */ +Method (_S3D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4D, 0, NotSerialized) +{ + Return (3) +} + +Method (_S3W, 0, NotSerialized) +{ + Return (3) +} + +Method (_S4W, 0, NotSerialized) +{ + Return (3) +} + +/* + * Power resource for wake + */ +Method (_PRW, 0) +{ + Return (Package() { 0x6D, 4 }) +} + +/* + * Device sleep wake + */ +Method (_DSW, 3) +{ + C2PM (Arg0, Arg1, Arg2, DCPM) + /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ + SD3C = Arg1 +} + +/* + * xHCI Root Hub Device + */ +Device (RHUB) +{ + Name (_ADR, Zero) + + /* High Speed Ports */ + Device (HS01) + { + Name (_ADR, 0x01) + } + + /* Super Speed Ports */ + Device (SS01) + { + Name (_ADR, 0x02) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 0 } + } + }) + } + } + + Device (SS02) + { + Name (_ADR, 0x03) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, + Package (2) { "usb4-port-number", 1 } + } + }) + } + } + + Device (SS03) + { + Name (_ADR, 0x04) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 0 } + } + }) + } + } + + Device (SS04) + { + Name (_ADR, 0x05) + Method (_DSD, 0, NotSerialized) + { + Return( Package () + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, + Package (2) { "usb4-port-number", 1 } + } + }) + } + } +} diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl new file mode 100644 index 0000000000..9c70d3ffad --- /dev/null +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Alder Lake-P PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + /* USB3 */ + Device (SS01) { Name (_ADR, 11) } + Device (SS02) { Name (_ADR, 12) } + Device (SS03) { Name (_ADR, 13) } + Device (SS04) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c new file mode 100644 index 0000000000..96e6268f74 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + bootblock_pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/alderlake/bootblock/cpu.c b/src/soc/intel/alderlake/bootblock/cpu.c new file mode 100644 index 0000000000..4225358de5 --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/cpu.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 7 + */ + +#include +#include + +void bootblock_cpu_init(void) +{ + /* + * Alderlake platform doesn't support booting from any other media + * than SPI flash and on IA platform SPI is memory mapped hence + * enabling temporary caching of memory-mapped spi boot media. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c new file mode 100644 index 0000000000..b7d2c15d3c --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2, 3, 4, 27, 28 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void soc_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + const uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c new file mode 100644 index 0000000000..38e909c73d --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Platform Stepping and IDs + * Document number: 619362, 619501 + * Chapter number: 2, 14 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_2, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = !!(cpu_feature_flag & CPUID_AES); + txt = !!(cpu_feature_flag & CPUID_SMX); + vt = !!(cpu_feature_flag & CPUID_VMX); + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + uint16_t mchid = get_dev_id(SA_DEV_ROOT); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, get_dev_revision(SA_DEV_ROOT), mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c new file mode 100644 index 0000000000..794c3bae0f --- /dev/null +++ b/src/soc/intel/alderlake/chip.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_TCSS_XHCI: return "TXHC"; + case SA_DEVFN_TCSS_XDCI: return "TXDC"; + case SA_DEVFN_TCSS_DMA0: return "TDM0"; + case SA_DEVFN_TCSS_DMA1: return "TDM1"; + case SA_DEVFN_TBT0: return "TRP0"; + case SA_DEVFN_TBT1: return "TRP1"; + case SA_DEVFN_TBT2: return "TRP2"; + case SA_DEVFN_TBT3: return "TRP3"; + case SA_DEVFN_IPU: return "IPU0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PMC: return "PMC"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; + } + + return NULL; +} +#endif + +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + +void soc_init_pre_device(void *chip_info) +{ + /* TODO: A bug has been filed, remove this W/A once FSP is updated */ + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* Perform silicon specific init. */ + fsp_silicon_init(romstage_handoff_is_resume()); + + /* Display FIRMWARE_VERSION_INFO_HOB */ + fsp_display_fvi_version_hob(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); + + /* Swap enabled PCI ports in device tree if needed. */ + pcie_rp_update_devicetree(pch_lp_rp_groups); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_cpu_entries, +#endif +}; + +static void soc_enable(struct device *dev) +{ + /* + * Set the operations if it is a special bus type or a hidden PCI + * device. + */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_PMC) + dev->ops = &pmc_ops; +} + +struct chip_operations soc_intel_alderlake_ops = { + CHIP_NAME("Intel Alderlake") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h new file mode 100644 index 0000000000..aaf03f510f --- /dev/null +++ b/src/soc/intel/alderlake/chip.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + +struct soc_intel_alderlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ + uint8_t TcssD3HotDisable; + /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ + uint8_t TcssD3ColdDisable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, + * 4:FixedPoint3, 5:Enabled */ + enum { + SaGv_Disabled, + SaGv_FixedPoint0, + SaGv_FixedPoint1, + SaGv_FixedPoint2, + SaGv_FixedPoint3, + SaGv_Enabled, + } SaGv; + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t RMT; + + /* USB related */ + struct usb2_port_config usb2_ports[16]; + struct usb3_port_config usb3_ports[10]; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + + /* SATA related */ + uint8_t SataEnable; + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[8]; + + /* SataPortsDmVal is the DITO multiplier. Default is 15. */ + uint8_t SataPortsDmVal[8]; + /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ + uint16_t SataPortsDitoVal[8]; + + /* Audio related */ + uint8_t PchHdaDspEnable; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect; + + /* PCIe Root Ports */ + uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe RP L1 substate */ + enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, + } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + + /* Integrated Sensor */ + uint8_t PchIshEnable; + + /* Heci related */ + uint8_t Heci3Enabled; + + /* Gfx related */ + enum { + IGD_SM_0MB = 0x00, + IGD_SM_32MB = 0x01, + IGD_SM_64MB = 0x02, + IGD_SM_96MB = 0x03, + IGD_SM_128MB = 0x04, + IGD_SM_160MB = 0x05, + IGD_SM_4MB = 0xF0, + IGD_SM_8MB = 0xF1, + IGD_SM_12MB = 0xF2, + IGD_SM_16MB = 0xF3, + IGD_SM_20MB = 0xF4, + IGD_SM_24MB = 0xF5, + IGD_SM_28MB = 0xF6, + IGD_SM_36MB = 0xF8, + IGD_SM_40MB = 0xF9, + IGD_SM_44MB = 0xFA, + IGD_SM_48MB = 0xFB, + IGD_SM_52MB = 0xFC, + IGD_SM_56MB = 0xFD, + IGD_SM_60MB = 0xFE, + } IgdDvmt50PreAlloc; + uint8_t InternalGfx; + uint8_t SkipExtGfxScan; + + uint32_t GraphicsConfigPtr; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + /* PL2 Override value in Watts */ + uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ + uint8_t speed_shift_enable; + + /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + uint8_t eist_enable; + + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + /* + * PRMRR size setting with below options + * Disable: 0x0 + * 32MB: 0x2000000 + * 64MB: 0x4000000 + * 128 MB: 0x8000000 + * 256 MB: 0x10000000 + * 512 MB: 0x20000000 + */ + uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + + /* Enable Pch iSCLK */ + uint8_t pch_isclk; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + enum { + FORCE_DISABLE, + FORCE_ENABLE, + } CnviBtAudioOffload; + + /* + * IOM Port Config + * If a port orientation needs to be controlled by the SOC this setting must be + * updated to reflect the correct GPIOs being used for the SOC port flipping. + * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down + * 0,1 are pull up and pull down for port 0 + * 2,3 are pull up and pull down for port 1 + * 4,5 are pull up and pull down for port 2 + * 6,7 are pull up and pull down for port 3 + * values to be programmed correspond to the GPIO family and offsets + */ + uint32_t IomTypeCPortPadCfg[8]; + + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports on ADL. + * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. + * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines + * on the motherboard. + */ + uint16_t TcssAuxOri; + + /* Connect Topology Command timeout value */ + uint16_t ITbtConnectTopologyTimeoutInMs; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t DdiPortAConfig; + uint8_t DdiPortBConfig; + + /* Enable(1)/Disable(0) HPD */ + uint8_t DdiPortAHpd; + uint8_t DdiPortBHpd; + uint8_t DdiPortCHpd; + uint8_t DdiPort1Hpd; + uint8_t DdiPort2Hpd; + uint8_t DdiPort3Hpd; + uint8_t DdiPort4Hpd; + + /* Enable(1)/Disable(0) DDC */ + uint8_t DdiPortADdc; + uint8_t DdiPortBDdc; + uint8_t DdiPortCDdc; + uint8_t DdiPort1Ddc; + uint8_t DdiPort2Ddc; + uint8_t DdiPort3Ddc; + uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * + * Only override CPU flex ratio if don't want to boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + + /* + * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the DMI Power Optimizer. + */ + uint8_t DmiPwrOptimizeDisable; + + /* + * Enable(1)/Disable(0) CPU Replacement check. + * Default 0. Setting this to 1 to check CPU replacement. + */ + uint8_t CpuReplacementCheck; + + /* ISA Serial Base selection. */ + enum { + ISA_SERIAL_BASE_ADDR_3F8, + ISA_SERIAL_BASE_ADDR_2F8, + } IsaSerialUartBase; +}; + +typedef struct soc_intel_alderlake_config config_t; + +#endif diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c new file mode 100644 index 0000000000..ee8051d568 --- /dev/null +++ b/src/soc/intel/alderlake/cpu.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor CPU Datasheet + * Document number: 619501 + * Chapter number: 14 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_fsp_load(void) +{ + fsps_load(romstage_handoff_is_resume()); +} + +static void configure_isst(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + +static void configure_misc(void) +{ + msr_t msr; + + config_t *conf = config_of_soc(); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 23); /* Lock it */ + wrmsr(MSR_POWER_CTL, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERF_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERF_BIAS, msr); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(struct device *cpu) +{ + /* Clear out pending MCEs */ + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); + + /* Enable the local CPU apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Configure Intel Speed Shift */ + configure_isst(); + + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Enable Turbo */ + enable_turbo(); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + global_smi_enable(); +} + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = soc_fsp_load, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); +} diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c new file mode 100644 index 0000000000..84f0a7ed4f --- /dev/null +++ b/src/soc/intel/alderlake/elog.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* CSME-Initiated Host Reset with power down */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD) + elog_add_event(ELOG_TYPE_MI_HRPD); + + /* CSME-Initiated Host Reset with power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC) + elog_add_event(ELOG_TYPE_MI_HRPC); + + /* CSME-Initiated Host Reset without power cycle */ + if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR) + elog_add_event(ELOG_TYPE_MI_HR); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c new file mode 100644 index 0000000000..c909030167 --- /dev/null +++ b/src/soc/intel/alderlake/espi.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve +* certain memory range as reserved range for BIOS usage. +* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" +*/ +static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { + { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return lpc_fixed_mmio_ranges; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + +#if ENV_RAMSTAGE +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); +} +#endif diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c new file mode 100644 index 0000000000..24dbbd6ab7 --- /dev/null +++ b/src/soc/intel/alderlake/finalize.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4, 29 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ +#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ +#define CAM_CLK_EN (1 << 1) +#define MIPI_CLK (1 << 0) +#define HDPLL_CLK (0 << 0) + +static void pch_enable_isclk(void) +{ + pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); + pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); +} + +static void pch_handle_sideband(config_t *config) +{ + if (config->pch_isclk) + pch_enable_isclk(); +} + +static void pch_finalize(void) +{ + config_t *config; + + /* TCO Lock down */ + tco_lockdown(); + + /* TODO: Add Thermal Configuration */ + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + config = config_of_soc(); + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); + + /* Disable XTAL shutdown qualification for low power idle. */ + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); + + pch_handle_sideband(config); + + pmc_clear_pmcon_sts(); +} + +static void tbt_finalize(void) +{ + int i; + const struct device *dev; + + /* Disable Thunderbolt PCIe root ports bus master */ + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (dev) + pci_dev_disable_bus_master(dev); + } +} + +static void soc_finalize(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); + + /* Indicate finalize step with post code */ + post_code(POST_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c new file mode 100644 index 0000000000..a21ca4a1b5 --- /dev/null +++ b/src/soc/intel/alderlake/fsp_params.c @@ -0,0 +1,317 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* THC assignment definition */ +#define THC_NONE 0 +#define THC_0 1 +#define THC_1 2 + +/* SATA DEVSLP idle timeout default values */ +#define DEF_DMVAL 15 +#define DEF_DITOVAL 625 + +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_alderlake_config *config; + config = config_of_soc(); + + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; + params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + } + + for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +} + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_GSPI3, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +__weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + /* Override settings per board. */ +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + + struct device *dev; + struct soc_intel_alderlake_config *config; + config = config_of_soc(); + mainboard_update_soc_chip_config(config); + + /* Parse device tree and enable/disable Serial I/O devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + + /* D3Hot and D3Cold for TCSS */ + params->D3HotEnable = !config->TcssD3HotDisable; + params->D3ColdEnable = !config->TcssD3ColdDisable; + + params->TcssAuxOri = config->TcssAuxOri; + for (i = 0; i < 8; i++) + params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + + /* + * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will + * evaluate this UPD value and skip sending command. There will be no + * delay for command completion. + */ + params->ITbtConnectTopologyTimeoutInMs = 0; + + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = OC_SKIP; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].enable) + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + else + params->Usb3OverCurrentPin[i] = OC_SKIP; + + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* PCH UART selection for FSP Debug */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); + params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; + + /* SATA */ + dev = pcidev_path_on_root(PCH_DEVFN_SATA); + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } + + /* + * Power Optimizer for DMI and SATA. + * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. + * Boards not needing the optimizers explicitly disables them by setting + * these disable variables to 1 in devicetree overrides. + */ + params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); + params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + + /* + * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. + * SataPortsDmVal is the DITO multiplier. Default is 15. + * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. + * The default values can be changed from devicetree. + */ + for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { + if (config->SataPortsEnableDitoConfig[i]) { + params->SataPortsDmVal[i] = config->SataPortsDmVal[i]; + params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; + } + } + + /* Enable TCPU for processor thermal control */ + dev = pcidev_path_on_root(SA_DEVFN_DPTF); + params->Device4Enable = is_dev_enabled(dev); + + /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + + /* LAN */ + dev = pcidev_path_on_root(PCH_DEVFN_GBE); + params->PchLanEnable = is_dev_enabled(dev); + + /* CNVi */ + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); + params->CnviMode = is_dev_enabled(dev); + + /* CNVi BT Core */ + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_BT); + params->CnviBtCore = is_dev_enabled(dev); + + /* CNVi BT Audio Offload */ + params->CnviBtAudioOffload = config->CnviBtAudioOffload; + + /* VMD */ + dev = pcidev_path_on_root(SA_DEVFN_VMD); + params->VmdEnable = is_dev_enabled(dev); + + /* THC */ + dev = pcidev_path_on_root(PCH_DEVFN_THC0); + params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; + + dev = pcidev_path_on_root(PCH_DEVFN_THC1); + params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); + + /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + params->PcieRpAdvancedErrorReporting[i] = + config->PcieRpAdvancedErrorReporting[i]; + params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + } + + /* Enable ClkReqDetect for enabled port */ + memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, + sizeof(config->PcieRpClkReqDetect)); + + params->PmSupport = 1; + params->Hwp = 1; + params->Cx = 1; + params->PsOnEnable = 1; + + mainboard_silicon_init_params(params); +} + +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} + +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + * This platform supports below MultiPhaseSIInit Phase(s): + * Phase | FSP return point | Purpose + * ------- + ------------------------------------------------ + ------------------------------- + * 1 | After TCSS initialization completed | for TCSS specific init + */ +void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: + /* TCSS specific initialization here */ + break; + default: + break; + } +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c new file mode 100644 index 0000000000..f0db5e996b --- /dev/null +++ b/src/soc/intel/alderlake/gpio.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 630094 + * Chapter number: 27 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + */ +static const struct pad_group adl_community0_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64), /* GPP_A */ +}; + +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group adl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group adl_community4_groups[] = { + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ +}; + +static const struct pad_group adl_community5_groups[] = { + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK), /* GPP_SPI0 */ +}; + +static const struct pad_community adl_communities[] = { + [COMM_0] = { /* GPP B, T, A */ + .port = PID_GPIOCOM0, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community0_groups, + .num_groups = ARRAY_SIZE(adl_community0_groups), + }, + [COMM_1] = { /* GPP S, D, H */ + .port = PID_GPIOCOM1, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDH", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community1_groups, + .num_groups = ARRAY_SIZE(adl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPIO_COM2_START, + .last_pad = GPIO_COM2_END, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = adl_community2_groups, + .num_groups = ARRAY_SIZE(adl_community2_groups), + }, + [COMM_4] = { /* GPP F, C, HVMOS, E */ + .port = PID_GPIOCOM4, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community4_groups, + .num_groups = ARRAY_SIZE(adl_community4_groups), + }, + [COMM_5] = { /* GPP R, SPI0 */ + .port = PID_GPIOCOM5, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_RSPI0", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community5_groups, + .num_groups = ARRAY_SIZE(adl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(adl_communities); + return adl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_B, GPP_B }, + { PMC_GPP_T, GPP_T }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPD, GPD }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_HVMOS, GPP_HVMOS }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_SPI0, GPP_SPI0 }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/alderlake/gspi.c b/src/soc/intel/alderlake/gspi.c new file mode 100644 index 0000000000..dd07b07f1a --- /dev/null +++ b/src/soc/intel/alderlake/gspi.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 11 + */ + +#include +#include + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return PCH_DEVFN_GSPI0; + case 1: + return PCH_DEVFN_GSPI1; + case 2: + return PCH_DEVFN_GSPI2; + case 3: + return PCH_DEVFN_GSPI3; + } + return -1; +} diff --git a/src/soc/intel/alderlake/i2c.c b/src/soc/intel/alderlake/i2c.c new file mode 100644 index 0000000000..ef34e2ef1c --- /dev/null +++ b/src/soc/intel/alderlake/i2c.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 13 + */ + +#include +#include +#include + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: + return 0; + case PCH_DEVFN_I2C1: + return 1; + case PCH_DEVFN_I2C2: + return 2; + case PCH_DEVFN_I2C3: + return 3; + case PCH_DEVFN_I2C4: + return 4; + case PCH_DEVFN_I2C5: + return 5; + } + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: + return PCH_DEVFN_I2C0; + case 1: + return PCH_DEVFN_I2C1; + case 2: + return PCH_DEVFN_I2C2; + case 3: + return PCH_DEVFN_I2C3; + case 4: + return PCH_DEVFN_I2C4; + case 5: + return PCH_DEVFN_I2C5; + } + return -1; +} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h new file mode 100644 index 0000000000..087d29f741 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_ +#define _SOC_ALDERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h new file mode 100644 index 0000000000..3c11183831 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_CPU_H_ +#define _SOC_ALDERLAKE_CPU_H_ + +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/espi.h b/src/soc/intel/alderlake/include/soc/espi.h new file mode 100644 index 0000000000..49ccdb4f9d --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/espi.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 2 + */ + +#ifndef _SOC_ALDERLAKE_ESPI_H_ +#define _SOC_ALDERLAKE_ESPI_H_ + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpe.h b/src/soc/intel/alderlake/include/soc/gpe.h new file mode 100644 index 0000000000..34dfcea763 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpe.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h new file mode 100644 index 0000000000..eec698a1e7 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_H_ +#define _SOC_ALDERLAKE_GPIO_H_ + +#include +#include + +#define CROS_GPIO_NAME "INTC1055" +#define CROS_GPIO_DEVICE_NAME "INTC1055:00" + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..68b886acac --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include +#endif +#include + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11_IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group GPD */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..bf95716a5d --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +/* GPIO COMM 0 */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +/* GPIO COMM 1 */ +#define GPP_S 0x3 +#define GPP_H 0x4 +#define GPP_D 0x5 +/* GPIO COMM 2 */ +#define GPD 0x6 +/* GPIO COMM 4 */ +#define GPP_C 0x7 +#define GPP_F 0x8 +#define GPP_HVMOS 0x9 +#define GPP_E 0xA +/* GPIO COMM 5 */ +#define GPP_R 0xB +#define GPP_SPI0 0xC + +#define GPIO_MAX_NUM_PER_GROUP 26 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_ESPI_CLK_LOOPBK 66 + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_ESPI_CLK_LOOPBK +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END GPP_GSPI2_CLK_LOOPBK +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 120 +#define GPD1 121 +#define GPD2 122 +#define GPD3 123 +#define GPD4 124 +#define GPD5 125 +#define GPD6 126 +#define GPD7 127 +#define GPD8 128 +#define GPD9 129 +#define GPD10 130 +#define GPD11 131 +#define GPD_INPUT3VSEL 132 +#define GPD_SLP_LANB 133 +#define GPD_SLP_SUSB 134 +#define GPD_WAKEB 135 +#define GPD_DRAM_RESETB 136 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group C */ +#define GPP_C0 137 +#define GPP_C1 138 +#define GPP_C2 139 +#define GPP_C3 140 +#define GPP_C4 141 +#define GPP_C5 142 +#define GPP_C6 143 +#define GPP_C7 144 +#define GPP_C8 145 +#define GPP_C9 146 +#define GPP_C10 147 +#define GPP_C11 148 +#define GPP_C12 149 +#define GPP_C13 150 +#define GPP_C14 151 +#define GPP_C15 152 +#define GPP_C16 153 +#define GPP_C17 154 +#define GPP_C18 155 +#define GPP_C19 156 +#define GPP_C20 157 +#define GPP_C21 158 +#define GPP_C22 159 +#define GPP_C23 160 + +/* Group F */ +#define GPP_F0 161 +#define GPP_F1 162 +#define GPP_F2 163 +#define GPP_F3 164 +#define GPP_F4 165 +#define GPP_F5 166 +#define GPP_F6 167 +#define GPP_F7 168 +#define GPP_F8 169 +#define GPP_F9 170 +#define GPP_F10 171 +#define GPP_F11 172 +#define GPP_F12 173 +#define GPP_F13 174 +#define GPP_F14 175 +#define GPP_F15 176 +#define GPP_F16 177 +#define GPP_F17 178 +#define GPP_F18 179 +#define GPP_F19 180 +#define GPP_F20 181 +#define GPP_F21 182 +#define GPP_F22 183 +#define GPP_F23 184 +#define GPP_F_CLK_LOOPBK 185 + +/* Group HVMOS */ +#define GPP_L_BKLTEN 186 +#define GPP_L_BKLTCTL 187 +#define GPP_L_VDDEN 188 +#define GPP_SYS_PWROK 189 +#define GPP_SYS_RESETB 190 +#define GPP_MLK_RSTB 191 + +/* Group E */ +#define GPP_E0 192 +#define GPP_E1 193 +#define GPP_E2 194 +#define GPP_E3 195 +#define GPP_E4 196 +#define GPP_E5 197 +#define GPP_E6 198 +#define GPP_E7 199 +#define GPP_E8 200 +#define GPP_E9 201 +#define GPP_E10 202 +#define GPP_E11 203 +#define GPP_E12 204 +#define GPP_E13 205 +#define GPP_E14 206 +#define GPP_E15 207 +#define GPP_E16 208 +#define GPP_E17 209 +#define GPP_E18 210 +#define GPP_E19 211 +#define GPP_E20 212 +#define GPP_E21 213 +#define GPP_E22 214 +#define GPP_E23 215 +#define GPP_E_CLK_LOOPBK 216 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_E_CLK_LOOPBK +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group R */ +#define GPP_R0 217 +#define GPP_R1 218 +#define GPP_R2 219 +#define GPP_R3 220 +#define GPP_R4 221 +#define GPP_R5 222 +#define GPP_R6 223 +#define GPP_R7 224 + +/* Group SPI0 */ +#define GPP_SPI0_IO_2 225 +#define GPP_SPI0_IO_3 226 +#define GPP_SPI0_MOSI_IO_0 227 +#define GPP_SPI0_MOSI_IO_1 228 +#define GPP_SPI0_TPM_CSB 229 +#define GPP_SPI0_FLASH_0_CSB 230 +#define GPP_SPI0_FLASH_1_CSB 231 +#define GPP_SPI0_CLK 232 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_SPI0_CLK +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h new file mode 100644 index 0000000000..88fab6f235 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Firmware Architecture Specification + * Document number: 626540 + * Chapter number: 4 + */ + +#ifndef _SOC_ALDERLAKE_IOMAP_H_ +#define _SOC_ALDERLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define UART_BASE_SIZE 0x1000 + +#define UART_BASE_0_ADDRESS 0xfe03e000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define TBT0_BASE_ADDRESS 0xfed84000 +#define TBT0_BASE_SIZE 0x1000 + +#define TBT1_BASE_ADDRESS 0xfed85000 +#define TBT1_BASE_SIZE 0x1000 + +#define TBT2_BASE_ADDRESS 0xfed86000 +#define TBT2_BASE_SIZE 0x1000 + +#define TBT3_BASE_ADDRESS 0xfed87000 +#define TBT3_BASE_SIZE 0x1000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + +#define REG_BASE_ADDRESS 0xfb000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xfed90000 +#define VTD_BASE_SIZE 0x00004000 + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600 + +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h new file mode 100644 index 0000000000..98e3f42108 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/irq.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 40 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 34 +#define LPSS_SPI3_IRQ 43 + +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 + +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 + +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 + +#define SATA_IRQ 16 + +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 + +#define CNVI_BT_IRQ 18 + +#define THC0_IRQ 23 +#define THC1_IRQ 24 + +#define ISH_IRQ 16 + +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 + +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 + +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 +#endif diff --git a/src/soc/intel/alderlake/include/soc/itss.h b/src/soc/intel/alderlake/include/soc/itss.h new file mode 100644 index 0000000000..ff26c9f97c --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/itss.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_ADL_ITSS_H +#define SOC_INTEL_ADL_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + +#endif /* SOC_INTEL_ADL_ITSS_H */ diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h new file mode 100644 index 0000000000..993a3bc29e --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/me.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ALDERLAKE_ME_H_ +#define _ALDERLAKE_ME_H_ + +#include + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 spi_protection_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 invoke_enhance_dbg_mode: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; +#endif /* _ALDERLAKE_ME_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h new file mode 100644 index 0000000000..76930be0e7 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_MEMINIT_H_ +#define _SOC_ALDERLAKE_MEMINIT_H_ + +#include +#include +#include + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_CH2, + DDR_CH3, + DDR_CH4, + DDR_CH5, + DDR_CH6, + DDR_CH7, + DDR_NUM_CHANNELS +}; +/* Number of memory DIMM slots available on Alderlake board */ +#define NUM_DIMM_SLOT 16 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this slot */ + READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_cfg { + /* DQ mapping */ + uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* Rcomp target values. */ + uint16_t rcomp_targets[5]; + + /* + * Early Command Training Enable/Disable Control + * TRUE = enable, FALSE = disable + */ + bool ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for Alder Lake. + */ + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated); + +#endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/msr.h b/src/soc/intel/alderlake/include/soc/msr.h new file mode 100644 index 0000000000..67e09dcf41 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/msr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/nvs.h b/src/soc/intel/alderlake/include/soc/nvs.h new file mode 100644 index 0000000000..512945898e --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/nvs.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +#endif diff --git a/src/soc/intel/alderlake/include/soc/p2sb.h b/src/soc/intel/alderlake/include/soc/p2sb.h new file mode 100644 index 0000000000..27268511a5 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/p2sb.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 3 + */ + +#ifndef _SOC_ALDERLAKE_P2SB_H_ +#define _SOC_ALDERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pch.h b/src/soc/intel/alderlake/include/soc/pch.h new file mode 100644 index 0000000000..89e8a8a1f7 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pch.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_PCH_H_ +#define _SOC_ALDERLAKE_PCH_H_ + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..d86e81ddc2 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_PCI_DEVS_H_ +#define _SOC_ALDERLAKE_PCI_DEVS_H_ + +#include + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + +#define SA_DEV_SLOT_CPU_PCIE 0x06 +#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) +#define NUM_TBT_FUNCTIONS 4 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) + +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) + +#define SA_DEV_SLOT_VMD 0x0e +#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) +#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 0) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 1) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) + +#define PCH_DEV_SLOT_ISH 0x12 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..baeb7083d7 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 31-35 + */ + +#ifndef SOC_ALDERLAKE_PCR_H +#define SOC_ALDERLAKE_PCR_H + +/* + * Port ids + */ +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM3 0x6b +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_ESPI 0x72 +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h new file mode 100644 index 0000000000..b65b24dc46 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4 + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include +#include +#include +#include +#include + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h new file mode 100644 index 0000000000..8887d9bd1c --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_PMC_H_ +#define _SOC_ALDERLAKE_PMC_H_ +#include + +extern struct device_operations pmc_ops; + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x20 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PMC_EPOC 0x18EC +#define PCH_EPOC_2LM(__epoc) ((__epoc) & 0x1) +/* XTAL frequency in bits 21, 20, 17 */ +#define PCH_EPOC_XTAL_FREQ(__epoc) ((((__epoc) >> 19) & 0x6) | ((__epoc) >> 17 & 0x1)) + +/** + * enum pch_pmc_xtal - External crystal oscillator frequency. + * @XTAL_24_MHZ: 24 MHz external crystal. + * @XTAL_19_2_MHZ: 19.2 MHz external crystal. + * @XTAL_38_4_MHZ: 38.4 MHz external crystal. + */ +enum pch_pmc_xtal { + XTAL_24_MHZ, + XTAL_19_2_MHZ, + XTAL_38_4_MHZ, +}; + +/** + * pmc_get_xtal_freq() - Return frequency of external oscillator. + * + * Return &enum pch_pmc_xtal corredsponding to frequency returned by PMC. + */ +enum pch_pmc_xtal pmc_get_xtal_freq(void); + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#define PMC_GPP_B 0x0 +#define PMC_GPP_T 0x1 +#define PMC_GPP_A 0x2 +#define PMC_GPP_S 0x3 +#define PMC_GPP_H 0x4 +#define PMC_GPP_D 0x5 +#define PMC_GPD 0x6 +#define PMC_GPP_C 0x7 +#define PMC_GPP_F 0x8 +#define PMC_GPP_HVMOS 0x9 +#define PMC_GPP_E 0xA +#define PMC_GPP_R 0xB +#define PMC_GPP_SPI0 0xC + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 +#define HPR_CAUSE0 0x192C +#define HPR_CAUSE0_MI_HRPD (1 << 10) +#define HPR_CAUSE0_MI_HRPC (1 << 9) +#define HPR_CAUSE0_MI_HR (1 << 8) + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif diff --git a/src/soc/intel/alderlake/include/soc/ramstage.h b/src/soc/intel/alderlake/include/soc/ramstage.h new file mode 100644 index 0000000000..e655198316 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/ramstage.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h new file mode 100644 index 0000000000..c72c8aa4f8 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void romstage_pch_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/serialio.h b/src/soc/intel/alderlake/include/soc/serialio.h new file mode 100644 index 0000000000..e42af5f781 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/serialio.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, +}; + +#endif diff --git a/src/soc/intel/alderlake/include/soc/smbus.h b/src/soc/intel/alderlake/include/soc/smbus.h new file mode 100644 index 0000000000..ab4994aa37 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/smbus.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 6 + */ + +#ifndef _SOC_ALDERLAKE_SMBUS_H_ +#define _SOC_ALDERLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/soc_chip.h b/src/soc/intel/alderlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..584eda233f --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_SOC_CHIP_H_ +#define _SOC_ALDERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_ALDERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h new file mode 100644 index 0000000000..ebb3d71392 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/systemagent.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor SA Datasheet + * Document number: 619503 + * Chapter number: 3 + */ + +#ifndef SOC_ALDERLAKE_SYSTEMAGENT_H +#define SOC_ALDERLAKE_SYSTEMAGENT_H + +#include + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +/* MCHBAR offsets */ +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6a40 +#define IMRLIMIT 0x6a48 +#define IPUVTBAR 0x7880 +#define TBTxBAR(x) (0x7888 + (x) * 8) + +#define MAX_TBT_PCIE_PORT 4 + +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBTxBAR(0), TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBTxBAR(1), TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBTxBAR(2), TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBTxBAR(3), TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h new file mode 100644 index 0000000000..846849aa60 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include + +/* Per Port HS Transmitter Emphasis */ +#define USB2_EMP_OFF 0 +#define USB2_DE_EMP_ON 1 +#define USB2_PRE_EMP_ON 2 +#define USB2_DE_EMP_ON_PRE_EMP_ON 3 + +/* Per Port Half Bit Pre-emphasis */ +#define USB2_FULL_BIT_PRE_EMP 0 +#define USB2_HALF_BIT_PRE_EMP 1 + +/* Per Port HS Preemphasis Bias */ +#define USB2_BIAS_0MV 0 +#define USB2_BIAS_11P25MV 1 +#define USB2_BIAS_16P9MV 2 +#define USB2_BIAS_28P15MV 3 +#define USB2_BIAS_39P35MV 5 +#define USB2_BIAS_45MV 6 +#define USB2_BIAS_56P3MV 7 + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +/* USB Overcurrent pins definition */ +enum { + OC0 = 0, + OC1, + OC2, + OC3, + OC4, + OC5, + OC6, + OC7, + OCMAX, + OC_SKIP = 0xff, /* Skip OC programming */ +}; + +/* Standard USB Port based on length: + * - External + * - Back Panel + * - OTG + * - M.2 + * - Internal device down */ + +#define USB2_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_EMP_OFF, \ + .pre_emp_bias = USB2_BIAS_0MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 11.5"-12" */ +#define USB2_PORT_LONG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 6"-11.49" */ +#define USB2_PORT_MID(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_45MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Length = 3"-5.99" */ +#define USB2_PORT_SHORT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_39P35MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Max TX and Pre-emp settings */ +#define USB2_PORT_MAX(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Type-C Port, no BC1.2 charge detect module / MUX + * Length = 3.0" - 9.00" */ +#define USB2_PORT_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#define USB3_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_de_emp = 0x00, \ + .tx_downscale_amp = 0x00, \ +} + +#define USB3_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_de_emp = 0x0, \ + .tx_downscale_amp = 0x00, \ +} + +#endif diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c new file mode 100644 index 0000000000..e9e4b592e8 --- /dev/null +++ b/src/soc/intel/alderlake/lockdown.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include + +static void pmc_lock_pmsync(void) +{ + uint8_t *pmcbase; + uint32_t pmsyncreg; + + pmcbase = pmc_mmio_regs(); + + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); +} + +static void pmc_lock_abase(void) +{ + uint8_t *pmcbase; + uint32_t reg32; + + pmcbase = pmc_mmio_regs(); + + reg32 = read32(pmcbase + GEN_PMCON_B); + reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + write32(pmcbase + GEN_PMCON_B, reg32); +} + +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_B); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_B, reg8); +} + +static void pmc_lockdown_cfg(int chipset_lockdown) +{ + /* PMSYNC */ + pmc_lock_pmsync(); + /* Lock down ABASE and sleep stretching policy */ + pmc_lock_abase(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); +} + +void soc_lockdown_config(int chipset_lockdown) +{ + /* PMC lock down configuration */ + pmc_lockdown_cfg(chipset_lockdown); +} diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c new file mode 100644 index 0000000000..da1a2992e6 --- /dev/null +++ b/src/soc/intel/alderlake/me.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static void dump_me_status(void *unused) +{ + union me_hfsts1 hfsts1; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; + + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + + /* + * Lock Descriptor, and Fuses must be programmed on a + * production system to indicate ME Manufacturing mode is disabled. + */ + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + ((hfsts1.fields.spi_protection_mode == 0) && + (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); + /* + * The SPI Protection Mode bit reflects SPI descriptor + * locked(0) or unlocked(1). + */ + printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", + hfsts1.fields.spi_protection_mode ? "NO" : "YES"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: Enhanced Debug Mode : %s\n", + hfsts1.fields.invoke_enhance_dbg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c new file mode 100644 index 0000000000..e7084a5a16 --- /dev/null +++ b/src/soc/intel/alderlake/meminit.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +static void spd_read_from_cbfs(const struct spd_info *spd_info, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd_info->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd_info, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd_info->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd_info->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); + return; + } +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, + const struct mb_cfg *board_cfg, + bool half_populated) +{ + memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + + memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, + sizeof(mem_cfg->RcompTarget)); + + memcpy(&mem_cfg->DqMapCpu2DramCh0, &board_cfg->dq_map[DDR_CH0], + sizeof(board_cfg->dq_map[DDR_CH0])); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], + sizeof(board_cfg->dqs_map[DDR_CH0])); + + memcpy(&mem_cfg->DqMapCpu2DramCh1, &board_cfg->dq_map[DDR_CH1], + sizeof(board_cfg->dq_map[DDR_CH1])); + memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], + sizeof(board_cfg->dqs_map[DDR_CH1])); + + memcpy(&mem_cfg->DqMapCpu2DramCh2, &board_cfg->dq_map[DDR_CH2], + sizeof(board_cfg->dq_map[DDR_CH2])); + memcpy(&mem_cfg->DqsMapCpu2DramCh2, &board_cfg->dqs_map[DDR_CH2], + sizeof(board_cfg->dqs_map[DDR_CH2])); + + memcpy(&mem_cfg->DqMapCpu2DramCh3, &board_cfg->dq_map[DDR_CH3], + sizeof(board_cfg->dq_map[DDR_CH3])); + memcpy(&mem_cfg->DqsMapCpu2DramCh3, &board_cfg->dqs_map[DDR_CH3], + sizeof(board_cfg->dqs_map[DDR_CH3])); + + if (half_populated) + return; + + memcpy(&mem_cfg->DqMapCpu2DramCh4, &board_cfg->dq_map[DDR_CH4], + sizeof(board_cfg->dq_map[DDR_CH4])); + memcpy(&mem_cfg->DqsMapCpu2DramCh4, &board_cfg->dqs_map[DDR_CH4], + sizeof(board_cfg->dqs_map[DDR_CH4])); + + memcpy(&mem_cfg->DqMapCpu2DramCh5, &board_cfg->dq_map[DDR_CH5], + sizeof(board_cfg->dq_map[DDR_CH5])); + memcpy(&mem_cfg->DqsMapCpu2DramCh5, &board_cfg->dqs_map[DDR_CH5], + sizeof(board_cfg->dqs_map[DDR_CH5])); + + memcpy(&mem_cfg->DqMapCpu2DramCh6, &board_cfg->dq_map[DDR_CH6], + sizeof(board_cfg->dq_map[DDR_CH6])); + memcpy(&mem_cfg->DqsMapCpu2DramCh6, &board_cfg->dqs_map[DDR_CH6], + sizeof(board_cfg->dqs_map[DDR_CH6])); + + memcpy(&mem_cfg->DqMapCpu2DramCh7, &board_cfg->dq_map[DDR_CH7], + sizeof(board_cfg->dq_map[DDR_CH7])); + memcpy(&mem_cfg->DqsMapCpu2DramCh7, &board_cfg->dqs_map[DDR_CH7], + sizeof(board_cfg->dqs_map[DDR_CH7])); +} + +static void meminit_channels(FSP_M_CONFIG *mem_cfg, + const struct mb_cfg *board_cfg, + uintptr_t spd_data_ptr, + bool half_populated) +{ + uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ + + /* Channel 0 */ + mem_cfg->DisableDimmMc0Ch0 = dimm_cfg; + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + /* Channel 1 */ + mem_cfg->DisableDimmMc0Ch1 = dimm_cfg; + mem_cfg->MemorySpdPtr02 = spd_data_ptr; + mem_cfg->MemorySpdPtr03 = 0; + + /* Channel 2 */ + mem_cfg->DisableDimmMc0Ch2 = dimm_cfg; + mem_cfg->MemorySpdPtr04 = spd_data_ptr; + mem_cfg->MemorySpdPtr05 = 0; + + /* Channel 3 */ + mem_cfg->DisableDimmMc0Ch3 = dimm_cfg; + mem_cfg->MemorySpdPtr06 = spd_data_ptr; + mem_cfg->MemorySpdPtr07 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + dimm_cfg = DISABLE_BOTH_DIMMS; + spd_data_ptr = 0; + } + + /* Channel 4 */ + mem_cfg->DisableDimmMc1Ch0 = dimm_cfg; + mem_cfg->MemorySpdPtr08 = spd_data_ptr; + mem_cfg->MemorySpdPtr09 = 0; + + /* Channel 5 */ + mem_cfg->DisableDimmMc1Ch1 = dimm_cfg; + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + /* Channel 6 */ + mem_cfg->DisableDimmMc1Ch2 = dimm_cfg; + mem_cfg->MemorySpdPtr12 = spd_data_ptr; + mem_cfg->MemorySpdPtr13 = 0; + + /* Channel 7 */ + mem_cfg->DisableDimmMc1Ch3 = dimm_cfg; + mem_cfg->MemorySpdPtr14 = spd_data_ptr; + mem_cfg->MemorySpdPtr15 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void memcfg_init(FSP_M_CONFIG *mem_cfg, + const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, + bool half_populated) +{ + if (spd_info->read_type == READ_SMBUS) { + for (int i = 0; i < NUM_DIMM_SLOT; i++) + mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + } else { + size_t spd_data_len = 0; + uintptr_t spd_data_ptr = 0; + + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + } + + mem_cfg->ECT = board_cfg->ect; + mem_cfg->UserBd = board_cfg->UserBd; +} diff --git a/src/soc/intel/alderlake/p2sb.c b/src/soc/intel/alderlake/p2sb.c new file mode 100644 index 0000000000..7eba1144d7 --- /dev/null +++ b/src/soc/intel/alderlake/p2sb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 3 + */ + +#include +#include + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c new file mode 100644 index 0000000000..e4c100933c --- /dev/null +++ b/src/soc/intel/alderlake/pmc.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMC_HID "INTC1026" + +enum pch_pmc_xtal pmc_get_xtal_freq(void) +{ + uint8_t *const pmcbase = pmc_mmio_regs(); + + return PCH_EPOC_XTAL_FREQ(read32(pmcbase + PCH_PMC_EPOC)); +} + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void pmc_init(struct device *dev) +{ + const config_t *config = config_of_soc(); + + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + /* Add the fixed MMIO resource */ + mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + + /* Add the fixed I/O resource */ + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_pmc_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_name_string("_HID", PMC_HID); + acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); + + /* + * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). + * The PMC gets 0xFE000000 - 0xFE00FFFF. + */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* PMC Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static void soc_acpi_mode_init(struct device *dev) +{ + /* + * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order + * to ensure the ordering does not break the assumptions that other + * drivers make about ACPI mode (e.g. Chrome EC). Since it disables + * ACPI mode, other drivers may take different actions based on this + * (e.g. Chrome EC will flush any pending hostevent bits). Because + * TGL has its PMC device available for device_operations, it can be + * done from the "ops->init" callback. + */ + pmc_set_acpi_mode(); +} + +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .init = soc_acpi_mode_init, + .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = soc_pmc_fill_ssdt, +#endif + .scan_bus = scan_static_bus, +}; diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c new file mode 100644 index 0000000000..79088dd781 --- /dev/null +++ b/src/soc/intel/alderlake/pmutil.c @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 4 + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + +/* + * PMC controller gets hidden from PCI bus + * during FSP-Silicon init call. Hence PWRMBASE + * can't be accessible using PCI configuration space + * read/write. + */ +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_alderlake_config *config; + + config = config_of_soc(); + + /* Assign to out variable */ + *dw0 = config->pmc_gpe0_dw0; + *dw1 = config->pmc_gpe0_dw1; + *dw2 = config->pmc_gpe0_dw2; +} + +static int rtc_failed(uint32_t gen_pmcon_b) +{ + return !!(gen_pmcon_b & RTC_BATTERY_DEAD); +} + +int soc_get_rtc_failed(void) +{ + const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (!ps) { + printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + return 1; + } + + return rtc_failed(ps->gen_pmcon_b); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_a & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + ps->hpr_cause0 = read32(pmc + HPR_CAUSE0); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); + + printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); +} diff --git a/src/soc/intel/alderlake/reset.c b/src/soc/intel/alderlake/reset.c new file mode 100644 index 0000000000..1f7ea3c180 --- /dev/null +++ b/src/soc/intel/alderlake/reset.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (cse_request_global_reset()) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + global_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc new file mode 100644 index 0000000000..a1a6c6638d --- /dev/null +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c new file mode 100644 index 0000000000..80420f0948 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + unsigned int i; + uint32_t mask = 0; + const struct device *dev; + + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0; + + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; + + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + m_cfg->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = get_valid_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* DP port config */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAHpd = config->DdiPortAHpd; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; + m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; + m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; + m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; + m_cfg->DdiPortADdc = config->DdiPortADdc; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; + m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; + m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; + m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ + m_cfg->ChHashMask = 0x30CC; + /* Enable SMBus controller */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + m_cfg->SmbusEnable = is_dev_enabled(dev); + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + m_cfg->PchIshEnable = is_dev_enabled(dev); + + /* Tcss USB */ + dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI); + m_cfg->TcssXhciEn = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_XDCI); + m_cfg->TcssXdciEn = is_dev_enabled(dev); + + /* TCSS DMA */ + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + m_cfg->TcssDma0En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); + m_cfg->TcssDma1En = is_dev_enabled(dev); + + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); + + /* Vt-D config */ + /* Disable VT-d support for pre-QS platform */ + m_cfg->VtdDisable = 1; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_alderlake_config *config; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + config = config_of_soc(); + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/alderlake/romstage/pch.c b/src/soc/intel/alderlake/romstage/pch.c new file mode 100644 index 0000000000..bec6150374 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/pch.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void romstage_pch_init(void) +{ + /* Program SMBus base address and enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c new file mode 100644 index 0000000000..6cd22d018a --- /dev/null +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len = 0; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (meminfo_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) + dram_part_num_len = strlen(dram_part_num); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!dram_part_num) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + uint8_t memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Perform PCH init */ + romstage_pch_init(); + /* Initialize HECI interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/alderlake/romstage/systemagent.c b/src/soc/intel/alderlake/romstage/systemagent.c new file mode 100644 index 0000000000..150ffb5dfa --- /dev/null +++ b/src/soc/intel/alderlake/romstage/systemagent.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor SA Datasheet + * Document number: 619503 + * Chapter number: 3 + */ + +#include +#include +#include +#include + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c new file mode 100644 index 0000000000..a072138c96 --- /dev/null +++ b/src/soc/intel/alderlake/smihandler.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from ADP chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + const struct soc_intel_alderlake_config *config; + + config = config_of_soc(); + + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + heci_disable(); +} + +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPE0_STS_BIT] = smihandler_southbridge_gpe0, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, + [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) + [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, + [MONITOR_STS_BIT] = smihandler_southbridge_monitor, +}; diff --git a/src/soc/intel/alderlake/smmrelocate.c b/src/soc/intel/alderlake/smmrelocate.c new file mode 100644 index 0000000000..17b4f2d713 --- /dev/null +++ b/src/soc/intel/alderlake/smmrelocate.c @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + + /* + * All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smbase_msr; + msr_t iedbase_msr; + + smbase_msr.lo = smbase; + smbase_msr.hi = 0; + + /* + * According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. + */ + iedbase_msr.lo = 0; + iedbase_msr.hi = iedbase; + + wrmsr(SMBASE_MSR, smbase_msr); + wrmsr(IEDBASE_MSR, iedbase_msr); + } else { + em64t101_smm_state_save_area_t *save_state; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; + } +} + +/* Returns 1 if SMM MSR save state was set. */ +static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) +{ + msr_t smm_mca_cap; + + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + } + return relo_params->smm_save_state_in_msrs; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); + + /* + * Determine if the processor supports saving state in MSRs. If so, + * enable it before the non-BSPs run so that SMM relocation can occur + * in parallel in the non-BSP CPUs. + */ + if (cpu == 0) { + /* + * If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + } else if (bsp_setup_msr_save_state(relo_params)) + /* + * Just return from relocation handler if MSR save + * state is enabled. In that case the BSP will come + * back into the relocation handler to setup the new + * SMBASE as well disabling SMM save state in MSRs. + */ + return; + } + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~(4 * KiB - 1); + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); +} + +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} diff --git a/src/soc/intel/alderlake/soundwire.c b/src/soc/intel/alderlake/soundwire.c new file mode 100644 index 0000000000..38a2c37758 --- /dev/null +++ b/src/soc/intel/alderlake/soundwire.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct soundwire_link link_xtal_38_4 = { + .clock_stop_mode0_supported = 1, + .clock_stop_mode1_supported = 1, + .clock_frequencies_supported_count = 1, + .clock_frequencies_supported = { 4800 * KHz }, + .default_frame_rate = 48 * KHz, + .default_frame_row_size = 50, + .default_frame_col_size = 4, + .dynamic_frame_shape = 1, + .command_error_threshold = 16, +}; + +static const struct soundwire_link link_xtal_24 = { + .clock_stop_mode0_supported = 1, + .clock_stop_mode1_supported = 1, + .clock_frequencies_supported_count = 1, + .clock_frequencies_supported = { 6 * MHz }, + .default_frame_rate = 48 * KHz, + .default_frame_row_size = 125, + .default_frame_col_size = 2, + .dynamic_frame_shape = 1, + .command_error_threshold = 16, +}; + +static struct intel_soundwire_controller intel_controller = { + .acpi_address = 0x40000000, + .sdw = { + /* TODO: Verified Audio in nocodec mode, add codec support */ + .master_list_count = 0 + } +}; + +int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller) +{ + const struct soundwire_link *link; + enum pch_pmc_xtal xtal = pmc_get_xtal_freq(); + size_t i; + + /* Select link config based on XTAL frequency and set IP clock. */ + switch (xtal) { + case XTAL_24_MHZ: + link = &link_xtal_24; + intel_controller.ip_clock = 24 * MHz; + break; + case XTAL_38_4_MHZ: + link = &link_xtal_38_4; + intel_controller.ip_clock = 38400 * KHz; + break; + case XTAL_19_2_MHZ: + default: + printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal); + return -1; + } + + /* Fill link config in controller map based on selected XTAL. */ + for (i = 0; i < intel_controller.sdw.master_list_count; i++) + memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link)); + + *controller = &intel_controller; + return 0; +} diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c new file mode 100644 index 0000000000..2940de1c12 --- /dev/null +++ b/src/soc/intel/alderlake/spi.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 7 + */ + +#include +#include + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + case PCH_DEVFN_GSPI0: + return 1; + case PCH_DEVFN_GSPI1: + return 2; + case PCH_DEVFN_GSPI2: + return 3; + case PCH_DEVFN_GSPI3: + return 4; + } + return -1; +} diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c new file mode 100644 index 0000000000..3e7a404c45 --- /dev/null +++ b/src/soc/intel/alderlake/systemagent.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor SA Datasheet + * Document number: 619503 + * Chapter number: 3 + */ + +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); + /* TODO: Add set_power_limits() */ +} + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 65536; + } +} diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c new file mode 100644 index 0000000000..cdbf8ec123 --- /dev/null +++ b/src/soc/intel/alderlake/uart.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 621483 + * Chapter number: 9 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct uart_gpio_pad_config uart_gpio_pads[] = { + { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + }, + }, + { + .console_index = 1, + .gpios = { + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ + }, + }, + { + .console_index = 2, + .gpios = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + }, + } +}; + +const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); + +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) +{ + /* + * if index is valid, this function will return corresponding structure + * for uart console else will return NULL. + */ + switch (uart_console) { + case 0: + return pcidev_path_on_root(PCH_DEVFN_UART0); + case 1: + return pcidev_path_on_root(PCH_DEVFN_UART1); + case 2: + return pcidev_path_on_root(PCH_DEVFN_UART2); + default: + printk(BIOS_ERR, "Invalid UART console index\n"); + return NULL; + } +} diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f837a2e686..da57931ad4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -3,7 +3,7 @@ config SOC_INTEL_APOLLOLAKE help Intel Apollolake support -config SOC_INTEL_GLK +config SOC_INTEL_GEMINILAKE bool default n select SOC_INTEL_APOLLOLAKE @@ -21,17 +21,13 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NO_PCAT_8259 - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 - select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Audio options @@ -43,7 +39,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GLK + select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES @@ -92,11 +88,13 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMBUS select UDELAY_TSC select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING if !SOC_INTEL_GLK - select UDK_2017_BINDING if SOC_INTEL_GLK + select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE + select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE select SOC_INTEL_COMMON_RESET select HAVE_CF9_RESET_PREPARE select INTEL_GMA_ADD_VBT if RUN_FSP_GOP @@ -105,6 +103,11 @@ config CPU_SPECIFIC_OPTIONS select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select HAVE_ASAN_IN_ROMSTAGE + +config MAX_CPUS + int + default 4 config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -136,7 +139,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x100000 if SOC_INTEL_GLK + default 0x100000 if SOC_INTEL_GEMINILAKE default 0xc0000 help The size of the cache-as-ram region required during bootblock @@ -181,7 +184,7 @@ config VERSTAGE_ADDR The base address (in CAR) where verstage should be linked config FSP_HEADER_PATH - default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK + default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" config FSP_FD_PATH @@ -291,7 +294,7 @@ config NHLT_RT5682 choice prompt "Cache-as-ram implementation" - default CAR_CQOS if !SOC_INTEL_GLK + default CAR_CQOS if !SOC_INTEL_GEMINILAKE default CAR_NEM help This option allows you to select how cache-as-ram (CAR) is set up. @@ -333,7 +336,7 @@ config CACHE_QOS_SIZE_PER_BIT config L2_CACHE_SIZE hex - default 0x400000 if SOC_INTEL_GLK + default 0x400000 if SOC_INTEL_GEMINILAKE default 0x100000 config SMM_RESERVED_SIZE @@ -342,7 +345,7 @@ config SMM_RESERVED_SIZE config IFD_CHIPSET string - default "glk" if SOC_INTEL_GLK + default "glk" if SOC_INTEL_GEMINILAKE default "aplk" config CPU_BCLK_MHZ diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 517c8ca97d..79fab1a9d1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -30,7 +30,7 @@ romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c romstage-y += meminit.c -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) romstage-y += meminit_util_glk.c else romstage-y += meminit_util_apl.c @@ -54,6 +54,7 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += cse.c ramstage-y += elog.c +ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += heci.c ramstage-y += i2c.c @@ -89,7 +90,7 @@ verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) bootblock-y += gpio_glk.c romstage-y += gpio_glk.c smm-y += gpio_glk.c @@ -148,7 +149,7 @@ files_added:: $(IFWITOOL) endif # DSP firmware settings files. -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs else NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs @@ -184,7 +185,7 @@ cbfs-files-$(CONFIG_NHLT_RT5682) += $(RT5682_RENDER_CAPTURE) $(RT5682_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(RT5682_RENDER_CAPTURE) $(RT5682_RENDER_CAPTURE)-type := raw -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) # Gemini Lake B0 (706a1) only atm. cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) else diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 1c7a04a703..ee1a543728 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -151,7 +152,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -170,19 +171,15 @@ static unsigned long soc_fill_dmar(unsigned long current) unsigned long tmp; /* IGD has to be enabled, GFXVTBAR set and enabled. */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten; + + /* First, add DRHD entries */ + if (emit_igd) { tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } /* DEFVTBAR has to be set and enabled. */ @@ -209,6 +206,15 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index b323000317..7c5b83052b 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include "soc_int.asl" +#include Method(_PRT) { @@ -15,7 +15,7 @@ Method(_PRT) Package(){0x000FFFFF, 0, 0, CSE_INT}, Package(){0x0011FFFF, 0, 0, ISH_INT}, Package(){0x0012FFFF, 0, 0, SATA_INT}, -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) Package(){0x000CFFFF, 0, 0, CNVI_INT}, Package(){0x0013FFFF, 0, 0, PIRQF_INT}, Package(){0x0013FFFF, 1, 0, PIRQF_INT}, @@ -43,10 +43,10 @@ Method(_PRT) Package(){0x0017FFFF, 1, 0, I2C5_INT}, Package(){0x0017FFFF, 2, 0, I2C6_INT}, Package(){0x0017FFFF, 3, 0, I2C7_INT}, - Package(){0x0018FFFF, 0, 0, UART0_INT}, - Package(){0x0018FFFF, 1, 0, UART1_INT}, - Package(){0x0018FFFF, 2, 0, UART2_INT}, - Package(){0x0018FFFF, 3, 0, UART3_INT}, + Package(){0x0018FFFF, 0, 0, LPSS_UART0_IRQ}, + Package(){0x0018FFFF, 1, 0, LPSS_UART1_IRQ}, + Package(){0x0018FFFF, 2, 0, LPSS_UART2_IRQ}, + Package(){0x0018FFFF, 3, 0, LPSS_UART3_IRQ}, Package(){0x0019FFFF, 0, 0, SPI0_INT}, Package(){0x0019FFFF, 1, 0, SPI1_INT}, Package(){0x0019FFFF, 2, 0, SPI2_INT}, diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl deleted file mode 100644 index bdb0471be4..0000000000 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_INT_DEFINE_ASL_ -#define _SOC_INT_DEFINE_ASL_ - -#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ -#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/ -#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/ -#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ -#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ -#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ -#define GPIO_BANK_INT 14 -#define NPK_INT 16 -#define PIRQA_INT 16 -#define PIRQB_INT 17 -#define PIRQC_INT 18 -#define SATA_INT 19 -#define GEN_INT 19 -#define PIRQD_INT 19 -#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ -#define SMBUS_INT 20 /* PIRQE */ -#define CSE_INT 20 /* PIRQE */ -#define IUNIT_INT 21 /* PIRQF */ -#define PIRQF_INT 21 -#define PIRQG_INT 22 -#define PUNIT_INT 24 -#define AUDIO_INT 25 -#define ISH_INT 26 -#define I2C0_INT 27 -#define I2C1_INT 28 -#define I2C2_INT 29 -#define I2C3_INT 30 -#define I2C4_INT 31 -#define I2C5_INT 32 -#define I2C6_INT 33 -#define I2C7_INT 34 -#define SPI0_INT 35 -#define SPI1_INT 36 -#define SPI2_INT 37 -#define UFS_INT 38 -#define EMMC_INT 39 -#define PMC_INT 40 -#define SDIO_INT 42 -#define CNVI_INT 44 - -#endif /* _SOC_INT_DEFINE_ASL_ */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497223..4a8be47c51 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,9 @@ #include "xhci.asl" +/* GFX 00:02.0 */ +#include + /* LPC */ #include diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 1b75cdb7b6..1e506225a5 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -21,7 +21,7 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl" diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e4901e..14e9b11ad2 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,7 +23,7 @@ #include static const struct pad_config tpm_spi_configs[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ #else PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 92edbada79..a4ed8bdcbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -113,7 +113,7 @@ const char *soc_acpi_name(const struct device *dev) case 6: return "HS07"; case 7: return "HS08"; case 8: - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) return "HS09"; } break; @@ -139,9 +139,6 @@ const char *soc_acpi_name(const struct device *dev) /* DSDT: acpi/northbridge.asl */ case SA_DEVFN_ROOT: return "MCHC"; - /* DSDT: acpi/lpc.asl */ - case PCH_DEVFN_LPC: - return "LPCB"; /* DSDT: acpi/xhci.asl */ case PCH_DEVFN_XHCI: return "XHCI"; @@ -445,7 +442,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; -#if !CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GEMINILAKE) case SA_DEVFN_IPU: silconfig->IpuEn = 0; break; @@ -479,7 +476,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ +#if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { @@ -535,7 +532,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config static void glk_fsp_silicon_init_params_cb( struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) uint8_t port; struct device *dev; @@ -554,7 +551,7 @@ static void glk_fsp_silicon_init_params_cb( } dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM); - silconfig->Gmm = dev ? dev->enabled : 0; + silconfig->Gmm = is_dev_enabled(dev); /* On Geminilake, we need to override the default FSP PCIe de-emphasis * settings using the device tree settings. This is because PCIe @@ -665,10 +662,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Disable monitor mwait since it is broken due to a hardware bug * without a fix. Specific to Apollolake. */ - if (!CONFIG(SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GEMINILAKE)) silconfig->MonitorMwaitEnable = 0; - silconfig->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; @@ -681,7 +678,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); @@ -692,14 +689,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; + silconfig->VmxEnable = CONFIG(ENABLE_VMX); + /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - silconfig->PeiGraphicsPeimInit = 1; - else - silconfig->PeiGraphicsPeimInit = 0; + silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); + + silconfig->PavpEnable = CONFIG(PAVP); mainboard_silicon_init_params(silconfig); } @@ -814,7 +812,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) * Override GLK xhci clock gating register(XHCLKGTEN) to * mitigate USB device suspend and resume failure. */ - if (CONFIG(SOC_INTEL_GLK)) { + if (CONFIG(SOC_INTEL_GEMINILAKE)) { uint32_t *cfg; const struct resource *res; uint32_t reg; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ce446a063a..6e4c82d5a4 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -24,6 +24,22 @@ enum pnp_settings { PNP_PERF_POWER, }; +struct soc_intel_apl_pp { + unsigned int up_delay_ms; + unsigned int down_delay_ms; + unsigned int cycle_delay_ms; + unsigned int backlight_on_delay_ms; + unsigned int backlight_off_delay_ms; +}; + +struct soc_intel_apl_blc { + unsigned int pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } polarity; +}; + struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ @@ -32,6 +48,13 @@ struct soc_intel_apollolake_config { /* Common struct containing power limits configuration info */ struct soc_power_limits_config power_limits_config; + /* IGD panel configuration */ + struct soc_intel_apl_pp gpu_pp[2]; + /* Second backlight control shares logic with other pins (aka. display + utility pin). Be sure it's used for PWM before setting any value for + the secondary controls. */ + struct soc_intel_apl_blc gpu_blc[2]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an @@ -101,7 +124,7 @@ struct soc_intel_apollolake_config { int dptf_enable; /* TCC activation offset value in degrees Celsius */ - int tcc_offset; + uint32_t tcc_offset; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index eb07e1e104..72f983f3dd 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -30,7 +30,7 @@ #include static const struct reg_script core_msr_script[] = { -#if !CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GEMINILAKE) /* Enable C-state and IO/MWAIT redirect */ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index fef98e375a..1558d38b00 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -15,7 +15,6 @@ #include #include - #define MKHI_GROUP_ID_MCA 0x0a #define READ_FILE 0x02 #define READ_FILE_FLAG_DEFAULT (1 << 0) diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 408017f940..3e82c32e69 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -18,7 +18,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c index 4a6614f13f..f781c25dee 100644 --- a/src/soc/intel/apollolake/gpio_glk.c +++ b/src/soc/intel/apollolake/gpio_glk.c @@ -5,7 +5,6 @@ #include #include - static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c new file mode 100644 index 0000000000..24d47721ab --- /dev/null +++ b/src/soc/intel/apollolake/graphics.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static void graphics_configure_panelpower( + const struct soc_intel_apl_pp *const pp, + uint8_t *const mmio, const unsigned int panel_idx) +{ + const unsigned int offset = panel_idx * 0x100; + uint32_t reg32; + + reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL + offset, reg32); + + reg32 = pp->up_delay_ms * 10 << 16; + reg32 |= pp->backlight_on_delay_ms * 10; + write32(mmio + PCH_PP_ON_DELAYS + offset, reg32); + + reg32 = pp->down_delay_ms * 10 << 16; + reg32 |= pp->backlight_off_delay_ms * 10; + write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32); +} + +static void graphics_configure_backlight( + const struct soc_intel_apl_blc *const blc, + uint8_t *const mmio, const unsigned int panel_idx) +{ + if (!blc->pwm_hz) + return; + + const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz; + write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period); + write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2); + write32(mmio + BXT_BLC_PWM_CTL(panel_idx), + (blc->polarity ? BXT_BLC_PWM_POLARITY : 0)); + + /* Second backlight control uses display utility pin. */ + if (panel_idx == 1) { + write32(mmio + UTIL_PIN_CTL, 0); /* Make sure it's disabled, don't know + what FSP might have done already. */ + write32(mmio + UTIL_PIN_CTL, UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); + } +} + +void graphics_soc_init(struct device *const dev) +{ + const struct soc_intel_apollolake_config *const conf = dev->chip_info; + const struct resource *mmio_res; + void *mmio; + unsigned int i; + + /* Some hardware configuration first. */ + + if (!conf) + return; + + mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i) + graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i); + + for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i) + graphics_configure_backlight(&conf->gpu_blc[i], mmio, i); +} diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index b672f242bd..9b809c000a 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef _SOC_APL_GPIO_H_ #define _SOC_APL_GPIO_H_ -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include #else #include diff --git a/src/soc/intel/apollolake/include/soc/gpio_apl.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h index b637156ed8..e6e93005da 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_apl.h +++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h @@ -27,7 +27,6 @@ #define GPIO_MAX_NUM_PER_GROUP 32 - /* Host Software Pad Ownership Register. * The pins in the community are divided into 3 groups : * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95 diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h index 156df6f28f..a540a77d0e 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_glk.h +++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h @@ -202,7 +202,6 @@ #define GPIO_175 (AUDIO_OFFSET + 19) #define TOTAL_AUDIO_PADS 20 - /* SCC community pads */ /* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */ #define SCC_OFFSET (AUDIO_OFFSET + 20) @@ -297,11 +296,9 @@ (ALIGN_UP(NUM_SCC_PADS, GPIO_MAX_NUM_PER_GROUP) / \ GPIO_MAX_NUM_PER_GROUP) - #define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \ + NUM_AUDIO_GPI_REGS + NUM_SCC_GPI_REGS) - /* Macros for translating a global pad offset to a local offset */ #define PAD_NW(pad) (pad - NW_OFFSET) #define PAD_N(pad) (pad - N_OFFSET) diff --git a/src/soc/intel/apollolake/include/soc/irq.h b/src/soc/intel/apollolake/include/soc/irq.h new file mode 100644 index 0000000000..8e28ca182b --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/irq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ +#define LPSS_UART0_IRQ 4 /* Need to be shared by PMC and SCC only*/ +#define LPSS_UART1_IRQ 5 /* Need to be shared by PMC and SCC only*/ +#define LPSS_UART2_IRQ 6 /* Need to be shared by PMC and SCC only*/ +#define LPSS_UART3_IRQ 7 /* Need to be shared by PMC and SCC only*/ +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 +#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 14 +#define NPK_INT 16 +#define PIRQA_INT 16 +#define PIRQB_INT 17 +#define PIRQC_INT 18 +#define SATA_INT 19 +#define GEN_INT 19 +#define PIRQD_INT 19 +#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ +#define SMBUS_INT 20 /* PIRQE */ +#define CSE_INT 20 /* PIRQE */ +#define IUNIT_INT 21 /* PIRQF */ +#define PIRQF_INT 21 +#define PIRQG_INT 22 +#define PUNIT_INT 24 +#define AUDIO_INT 25 +#define ISH_INT 26 +#define I2C0_INT 27 +#define I2C1_INT 28 +#define I2C2_INT 29 +#define I2C3_INT 30 +#define I2C4_INT 31 +#define I2C5_INT 32 +#define I2C6_INT 33 +#define I2C7_INT 34 +#define SPI0_INT 35 +#define SPI1_INT 36 +#define SPI2_INT 37 +#define UFS_INT 38 +#define EMMC_INT 39 +#define PMC_INT 40 +#define SDIO_INT 42 +#define CNVI_INT 44 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 96466f0f6d..4e043bbb95 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -6,7 +6,7 @@ /* * Port ids. */ -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define PID_GPIO_AUDIO 0xC9 #define PID_GPIO_SCC 0xC8 #else diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index eb8c077874..aaf62583e6 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -177,7 +177,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 + 4*(x)) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define PMC_GPE_AUDIO_31_0 9 #define PMC_GPE_N_95_64 8 #define PMC_GPE_N_63_32 7 diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index e08c02706b..e11119c485 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -17,4 +17,6 @@ #define TCO_INTRD_SEL_SMI (1 << 2) #define TCO_INTRD_SEL_INT (1 << 1) +#define SMBUS_SLAVE_ADDR 0x24 + #endif diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index be6777ff7f..ad9211b9c2 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -28,7 +28,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) } static const struct pad_config lpc_gpios[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #if !CONFIG(SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index e391a92345..86015715bc 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -152,7 +152,7 @@ static const struct fsp_speed_profiles glk_profile = { static const struct fsp_speed_profiles *get_fsp_profile(void) { - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) return &glk_profile; else return &apl_profile; diff --git a/src/soc/intel/apollolake/report_platform.c b/src/soc/intel/apollolake/report_platform.c index a7b58731dd..e79e28a059 100644 --- a/src/soc/intel/apollolake/report_platform.c +++ b/src/soc/intel/apollolake/report_platform.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -64,18 +65,12 @@ static void report_cpu_info(void) { uint32_t i, cpu_id, cpu_feature_flag; char cpu_name[49]; - msr_t microcode_ver; const char *support = "Supported"; const char *no_support = "Not Supported"; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -86,7 +81,8 @@ static void report_cpu_info(void) } printk(BIOS_INFO, "CPU: %s\n", cpu_name); - printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, microcode_ver.hi); + printk(BIOS_INFO, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, + get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); printk(BIOS_INFO, "CPU: AES %s, TXT %s, VT %s\n", diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d14dd8d3ee..0aa6c397e3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -4,9 +4,9 @@ #include #include #include -#include #include #include +#include #include #include #include @@ -107,7 +107,7 @@ static bool punit_init(void) PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK; - if (!CONFIG(SOC_INTEL_GLK)) { + if (!CONFIG(SOC_INTEL_GEMINILAKE)) { data = MCHBAR32(0x7818); data &= 0xFFFFE01F; data |= 0x20 | 0x200; @@ -231,11 +231,11 @@ static void check_full_retrain(const FSPM_UPD *mupd) static void soc_memory_init_params(FSPM_UPD *mupd) { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); /* * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. @@ -258,22 +258,20 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd) { DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); -#if CONFIG(SOC_INTEL_GLK) - m_upd->FspmConfig.TraceHubEn = dev ? dev->enabled : 0; +#if CONFIG(SOC_INTEL_GEMINILAKE) + m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev); #else - m_upd->FspmConfig.NpkEn = dev ? dev->enabled : 0; + m_upd->FspmConfig.NpkEn = is_dev_enabled(dev); #endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - struct region_device rdev; - check_full_retrain(mupd); fill_console_params(mupd); - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) soc_memory_init_params(mupd); mainboard_memory_init_params(mupd); @@ -310,11 +308,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * wrong/missing key renders DRAM contents useless. */ - if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { - /* Assume leaking is ok. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); - } + mupd->FspmConfig.VariableNvsBufferPtr = + mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version, + NULL); + + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); fsp_version = version; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 038279ec81..4e35ee5a0a 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -13,7 +13,7 @@ /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) { .console_index = 0, .gpios = { diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 4396eaa67d..4584dc7085 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -3,7 +3,7 @@ #include #define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define XHCI_USB3_PORT_STATUS_REG 0x510 #define XHCI_USB2_PORT_NUM 9 #else diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 326dff2467..bd9f78e3ba 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,10 +8,8 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED @@ -25,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select REG_SCRIPT select RTC - select SMP select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER @@ -33,7 +30,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON @@ -134,13 +131,15 @@ config ENABLE_BUILTIN_COM1 config HAVE_REFCODE_BLOB depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." + bool "Use a binary refcode blob instead of native ModPHY init" default n help - The reference code blob will be placed into cbfs. + Use the ChromeBook refcode to intitialize high-speed PHYs instead of + native code. if HAVE_REFCODE_BLOB +# Ask for the blob if the user wants it config REFCODE_BLOB_FILE string "Path and filename to reference code blob." default "refcode.elf" diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 69f21428c8..bfa1846d1a 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -49,7 +49,12 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c + +ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) +ramstage-y += refcode.c +else +ramstage-y += modphy_table.c refcode_native.c +endif smm-y += iosf.c smm-y += pmutil.c @@ -61,7 +66,8 @@ ramstage-y += placeholders.c postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S -cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin +cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \ + 3rdparty/intel-microcode/intel-ucode/06-37-09 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 8870ef537a..1144749ab1 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -125,18 +126,32 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static acpi_tstate_t baytrail_tss_table[] = { +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, }; -static void generate_T_state_entries(int core, int cores_per_package) +static void generate_t_state_entries(int core, int cores_per_package) { /* Indicate SW_ALL coordination for T-states */ acpigen_write_TSD_package(core, cores_per_package, SW_ALL); @@ -148,24 +163,23 @@ static void generate_T_state_entries(int core, int cores_per_package) acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - acpigen_write_TSS_package( - ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); + acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table); } static int calculate_power(int tdp, int p1_ratio, int ratio) { - u32 m; - u32 power; + u32 m, power; /* * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp */ m = (110000 - ((p1_ratio - ratio) * 625)) / 11; m = (m * m) / 1000; + /* + * Power = (ratio / p1_ratio) * m * TDP + */ power = ((ratio * 100000 / p1_ratio) / 100); power *= (m / 100) * (tdp / 1000); power /= 1000; @@ -173,7 +187,7 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static void generate_P_state_entries(int core, int cores_per_package) +static void generate_p_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; @@ -232,12 +246,12 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Add entry for Turbo ratio */ acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + clock_max + 1, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } else { /* _PSS package count without Turbo */ acpigen_write_package(num_entries + 1); @@ -248,12 +262,12 @@ static void generate_P_state_entries(int core, int cores_per_package) /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control */ - control_status); /*status*/ + clock_max, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ /* Set up ratio and vid ranges for VID calculation */ ratio_range_2 = (ratio_turbo - ratio_min) * 2; @@ -264,8 +278,8 @@ static void generate_P_state_entries(int core, int cores_per_package) ratio >= ratio_min; ratio -= ratio_step) { /* Calculate VID for this ratio */ - vid = ((ratio - ratio_min) * vid_range_2) / - ratio_range_2 + vid_min; + vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min; + /* Round up if remainder */ if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) vid++; @@ -276,12 +290,12 @@ static void generate_P_state_entries(int core, int cores_per_package) control_status = (ratio << 8) | (vid & 0xff); acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + clock, /* MHz */ + power, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } /* Fix package length */ @@ -301,20 +315,16 @@ void generate_cpu_entries(const struct device *device) } /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - core, pcontrol_blk, plen); + acpigen_write_processor(core, pcontrol_blk, plen); /* Generate P-state tables */ - generate_P_state_entries( - core, pattrs->num_cpus); + generate_p_state_entries(core, pattrs->num_cpus); /* Generate C-state tables */ - acpigen_write_CST_package( - cstate_map, ARRAY_SIZE(cstate_map)); + acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - generate_T_state_entries( - core, pattrs->num_cpus); + generate_t_state_entries(core, pattrs->num_cpus); acpigen_pop_len(); } @@ -343,8 +353,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) sci_flags |= MP_IRQ_POLARITY_HIGH; irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); return current; } diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 9b07ab815d..c76cf22fb2 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -102,10 +102,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -/* - * Disable as Windows doesn't like it, and systems don't seem to use it. - * IRQNoFlags() { 8 } - */ }) } diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 0f3980cefb..46f12e7646 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -9,25 +9,6 @@ #include #include -static void setup_mmconfig(void) -{ - uint32_t reg; - - /* - * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the - * config access needs to be used initially to properly configure as the IOSF access - * registers live in PCI config space. - */ - reg = 0; - /* Clear the extended register. */ - pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; - pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | - IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; - pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} - static void program_base_addresses(void) { uint32_t reg; @@ -56,10 +37,19 @@ static void program_base_addresses(void) pci_write_config32(lpc_dev, GBASE, reg); } +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + static void spi_init(void) { - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -73,15 +63,6 @@ static void spi_init(void) write32(bcr, reg); } -static void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - static void byt_config_com1_and_enable(void) { uint32_t reg; @@ -95,6 +76,25 @@ static void byt_config_com1_and_enable(void) score_select_func(UART_TXD_PAD, 1); } +static void setup_mmconfig(void) +{ + uint32_t reg; + + /* + * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the + * config access needs to be used initially to properly configure as the IOSF access + * registers live in PCI config space. + */ + reg = 0; + /* Clear the extended register. */ + pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | + IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; + pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} + /* The distinction between nb/sb/cpu is not applicable here so just pick the one that is called first. */ void bootblock_early_northbridge_init(void) diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index b7e3250a84..c7eb149020 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -20,7 +20,6 @@ static struct device_operations cpu_bus_ops = { .init = baytrail_init_cpus, }; - static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index b1cb8d5aef..2029017e1f 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -13,25 +13,24 @@ #include #include #include - #include #include #include #include /* Core level MSRs */ -const struct reg_script core_msr_script[] = { +static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), - REG_MSR_RMW(MSR_POWER_MISC, - ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), REG_SCRIPT_END }; -static void baytrail_core_init(struct device *cpu) +static void soc_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); @@ -54,12 +53,13 @@ static void baytrail_core_init(struct device *cpu) } static struct device_operations cpu_dev_ops = { - .init = baytrail_core_init, + .init = soc_core_init, }; static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x30673 }, { X86_VENDOR_INTEL, 0x30678 }, + { X86_VENDOR_INTEL, 0x30679 }, { 0, 0 }, }; @@ -68,7 +68,6 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -164,8 +163,7 @@ static void per_cpu_smm_trigger(void) intel_microcode_load_unlocked(pattrs->microcode_patch); } -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { struct smm_relocation_params *relo_params = &smm_reloc_params; em64t100_smm_state_save_area_t *smm_state; @@ -184,21 +182,20 @@ static void post_mp_init(void) } static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_southbridge_clear_state, + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = relocation_handler, - .post_mp_init = post_mp_init, + .relocation_handler = relocation_handler, + .post_mp_init = post_mp_init, }; void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) { + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); - } } diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 93a43c5a12..7e92e9037d 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include +#include #include #include #include #include #include +#include static void log_power_and_resets(const struct chipset_power_state *ps) { @@ -17,36 +17,30 @@ static void log_power_and_resets(const struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_PWROK_FAIL); } - if (ps->gen_pmcon1 & SUS_PWR_FLR) { + if (ps->gen_pmcon1 & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - } - if (ps->gen_pmcon1 & RPS) { + if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - } - if (ps->tco_sts & SECOND_TO_STS) { + if (ps->tco_sts & SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); - } - if (ps->pm1_sts & PRBTNOR_STS) { + if (ps->pm1_sts & PRBTNOR_STS) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - } - if (ps->gen_pmcon1 & SRS) { + if (ps->gen_pmcon1 & SRS) elog_add_event(ELOG_TYPE_RESET_BUTTON); - } - if (ps->gen_pmcon1 & GEN_RST_STS) { + if (ps->gen_pmcon1 & GEN_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); - } } static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | - PCIE_WAKE2_STS | PCIE_WAKE1_STS | - PCIE_WAKE0_STS; + const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS | + PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS; + uint32_t gpe0_sts; uint32_t gpio_mask; int i; @@ -54,33 +48,27 @@ static void log_wake_events(const struct chipset_power_state *ps) /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en; - if (ps->pm1_sts & WAK_STS) { + if (ps->pm1_sts & WAK_STS) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - } + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); - if (ps->pm1_sts & PWRBTN_STS) { + if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - } - if (ps->pm1_sts & RTC_STS) { + if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - } - if (gpe0_sts & PME_B0_EN) { + if (gpe0_sts & PME_B0_EN) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - } - if (gpe0_sts & pcie_wake_mask) { + if (gpe0_sts & pcie_wake_mask) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - } gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { - if (gpio_mask & gpe0_sts) { - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } + if (gpio_mask & gpe0_sts) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); gpio_mask <<= 1; i++; } @@ -91,8 +79,8 @@ void southcluster_log_state(void) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) { - printk(BIOS_DEBUG, "Not logging power state information. " - "Power state not found in cbmem.\n"); + printk(BIOS_DEBUG, + "Not logging power state information. Power state not found in cbmem.\n"); return; } diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 92e6e64422..f78188ee28 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -44,28 +44,28 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -78,7 +78,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which * seems to work fine on Linux 5.0 and Windows 10. */ - fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 0da1fe49d3..0ee3cef591 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -205,7 +205,7 @@ static const struct reg_script gfx_init_script[] = { static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY), /* Display */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, diff --git a/src/soc/intel/baytrail/include/soc/gfx.h b/src/soc/intel/baytrail/include/soc/gfx.h index e809631482..ef86dd2299 100644 --- a/src/soc/intel/baytrail/include/soc/gfx.h +++ b/src/soc/intel/baytrail/include/soc/gfx.h @@ -14,10 +14,23 @@ # define GGC_GTT_SIZE_1MB (1 << 8) # define GGC_GTT_SIZE_2MB (2 << 8) # define GGC_GSM_SIZE_MASK (0x1f << 3) -# define GGC_GSM_SIZE_0MB (0 << 3) -# define GGC_GSM_SIZE_32MB (1 << 3) -# define GGC_GSM_SIZE_64MB (2 << 3) -# define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_0MB (0 << 3) +# define GGC_GSM_SIZE_32MB (1 << 3) +# define GGC_GSM_SIZE_64MB (2 << 3) +# define GGC_GSM_SIZE_96MB (3 << 3) +# define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_160MB (5 << 3) +# define GGC_GSM_SIZE_192MB (6 << 3) +# define GGC_GSM_SIZE_224MB (7 << 3) +# define GGC_GSM_SIZE_256MB (8 << 3) +# define GGC_GSM_SIZE_288MB (9 << 3) +# define GGC_GSM_SIZE_320MB (10 << 3) +# define GGC_GSM_SIZE_352MB (11 << 3) +# define GGC_GSM_SIZE_384MB (12 << 3) +# define GGC_GSM_SIZE_416MB (13 << 3) +# define GGC_GSM_SIZE_448MB (14 << 3) +# define GGC_GSM_SIZE_480MB (15 << 3) +# define GGC_GSM_SIZE_512MB (16 << 3) #define GSM_BASE 0x5c #define GTT_BASE 0x70 diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 15d77de03d..d4fcdf3f7b 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -9,34 +9,33 @@ /* * The Bay Trail SoC has a message network called IOSF Sideband. The access * routines are through 3 registers in PCI config space of 00:00.0: - * MCR - control register - * MDR - data register + * MCR - control register + * MDR - data register * MCRX - control register extension * The extension register is only used for addresses that don't fit * into the 8 bit register address. */ -#ifndef PCI_DEV -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) -#endif #define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) -#define MCR_REG 0xd0 -#define IOSF_OPCODE(x) ((x) << 24) -#define IOSF_PORT(x) ((0xff & (x)) << 16) -#define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_REG_UPPER(x) (((~0xff) & (x))) -#define IOSF_BYTE_EN_0 0x10 -#define IOSF_BYTE_EN_1 0x20 -#define IOSF_BYTE_EN_2 0x40 -#define IOSF_BYTE_EN_3 0x80 -#define IOSF_BYTE_EN \ - (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) -#define MDR_REG 0xd4 -#define MCRX_REG 0xd8 +#define IOSF_OPCODE(x) ((x) << 24) +#define IOSF_PORT(x) ((0xff & (x)) << 16) +#define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) ((~0xff) & (x)) + +#define IOSF_BYTE_EN_0 0x10 +#define IOSF_BYTE_EN_1 0x20 +#define IOSF_BYTE_EN_2 0x40 +#define IOSF_BYTE_EN_3 0x80 +#define IOSF_BYTE_EN \ + (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) + +#define MCR_REG 0xd0 +#define MDR_REG 0xd4 +#define MCRX_REG 0xd8 + +uint32_t iosf_read_port(uint32_t cr, int reg); +void iosf_write_port(uint32_t cr, int reg, uint32_t val); uint32_t iosf_aunit_read(int reg); void iosf_aunit_write(int reg, uint32_t val); @@ -49,6 +48,8 @@ void iosf_dunit_write(int reg, uint32_t val); /* Some registers are per channel while the globals live in dunit 0 */ uint32_t iosf_dunit_ch0_read(int reg); uint32_t iosf_dunit_ch1_read(int reg); +uint32_t iosf_cunit_read(int reg); +void iosf_cunit_write(int reg, uint32_t val); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); uint32_t iosf_usbphy_read(int reg); @@ -87,12 +88,13 @@ void iosf_ssus_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ #define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ +#define IOSF_PORT_CUNIT 0x08 #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SEC 0x44 /* SEC */ @@ -109,7 +111,7 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_PCIEPHY 0xa6 /* PCIE PHY */ #define IOSF_PORT_SSUS 0xa8 /* SUS */ #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ @@ -122,6 +124,8 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) #define IOSF_OP_READ_BUNIT 0x10 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) +#define IOSF_OP_READ_CUNIT 0x10 +#define IOSF_OP_WRITE_CUNIT (IOSF_OP_READ_CUNIT | 1) #define IOSF_OP_READ_PMC 0x06 #define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) #define IOSF_OP_READ_GFX 0x00 diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index 967bc35341..3a1d7c79e4 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -140,8 +140,8 @@ extern const struct baytrail_irq_route global_baytrail_irq_route; /* The following macros are used for ACPI by the ASL compiler */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + [dev_] = (((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)) #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index 5ca99e675f..7b3fbf8c90 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -16,7 +16,6 @@ #define UART_CONT 0x80 #define RCBA 0xf0 - #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 #define RID_C_STEPPING_START 0xe diff --git a/src/soc/intel/baytrail/include/soc/modphy_table.h b/src/soc/intel/baytrail/include/soc/modphy_table.h new file mode 100644 index 0000000000..9a483c4a6a --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/modphy_table.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BAYTRAIL_MODPHY_TABLE_H_ +#define _BAYTRAIL_MODPHY_TABLE_H_ + +struct modphy_entry { + u8 port; + u32 reg; + u32 mask; + u32 value; + u8 op_read; + u8 op_write; +}; + +#define MODPHY_ENTRY_END ((struct modphy_entry) { 0, 0, 0, 0, 0, 0 }) + +extern struct modphy_entry reva0_modphy_table[]; /* SOC stepping A0/A1 */ +extern struct modphy_entry revb0_modphy_table[]; /* SOC stepping B0 or later */ + +#endif diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index d485484e0c..cd22e123c9 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -37,13 +37,10 @@ struct pattrs { * This is just to hide the abstraction w/o relying on how the underlying * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - +extern struct pattrs __global_pattrs; static inline const struct pattrs *pattrs_get(void) { - return &PATTRS_GLOB_NAME; + return &__global_pattrs; } #endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 8f303313dc..51189cfd46 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -11,11 +11,9 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); -#if CONFIG(HAVE_REFCODE_BLOB) +/* The baytrail_run_reference_code() function is provided by either + * native refcode or the ChromeBook refcode wrapper */ void baytrail_run_reference_code(void); -#else -static inline void baytrail_run_reference_code(void) {} -#endif void baytrail_init_scc(void); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 57566f85a8..21060eee1a 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -15,7 +15,7 @@ static inline uint32_t read_iosf_reg(int reg) } /* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) +uint32_t iosf_read_port(uint32_t cr, int reg) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); @@ -23,7 +23,7 @@ static uint32_t iosf_read_port(uint32_t cr, int reg) return read_iosf_reg(MDR_REG); } -static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +void iosf_write_port(uint32_t cr, int reg, uint32_t val) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); @@ -32,9 +32,9 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) } #define IOSF_READ(port) \ - IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port)) #define IOSF_WRITE(port) \ - IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port)) uint32_t iosf_bunit_read(int reg) { @@ -68,6 +68,16 @@ void iosf_dunit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); } +uint32_t iosf_cunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(CUNIT), reg); +} + +void iosf_cunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(CUNIT), reg, val); +} + uint32_t iosf_punit_read(int reg) { return iosf_read_port(IOSF_READ(PMC), reg); @@ -85,7 +95,7 @@ uint32_t iosf_usbphy_read(int reg) void iosf_usbphy_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); + iosf_write_port(IOSF_WRITE(USBPHY), reg, val); } uint32_t iosf_ushphy_read(int reg) @@ -95,7 +105,7 @@ uint32_t iosf_ushphy_read(int reg) void iosf_ushphy_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); + iosf_write_port(IOSF_WRITE(USHPHY), reg, val); } uint32_t iosf_lpss_read(int reg) @@ -105,7 +115,7 @@ uint32_t iosf_lpss_read(int reg) void iosf_lpss_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(LPSS), reg, val); + iosf_write_port(IOSF_WRITE(LPSS), reg, val); } uint32_t iosf_ccu_read(int reg) @@ -115,7 +125,7 @@ uint32_t iosf_ccu_read(int reg) void iosf_ccu_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(CCU), reg, val); + iosf_write_port(IOSF_WRITE(CCU), reg, val); } uint32_t iosf_score_read(int reg) @@ -125,7 +135,7 @@ uint32_t iosf_score_read(int reg) void iosf_score_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SCORE), reg, val); + iosf_write_port(IOSF_WRITE(SCORE), reg, val); } uint32_t iosf_scc_read(int reg) @@ -135,7 +145,7 @@ uint32_t iosf_scc_read(int reg) void iosf_scc_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SCC), reg, val); + iosf_write_port(IOSF_WRITE(SCC), reg, val); } uint32_t iosf_aunit_read(int reg) @@ -145,7 +155,7 @@ uint32_t iosf_aunit_read(int reg) void iosf_aunit_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); + iosf_write_port(IOSF_WRITE(AUNIT), reg, val); } uint32_t iosf_cpu_bus_read(int reg) @@ -155,7 +165,7 @@ uint32_t iosf_cpu_bus_read(int reg) void iosf_cpu_bus_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); + iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); } uint32_t iosf_sec_read(int reg) @@ -165,7 +175,7 @@ uint32_t iosf_sec_read(int reg) void iosf_sec_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SEC), reg, val); + iosf_write_port(IOSF_WRITE(SEC), reg, val); } uint32_t iosf_port45_read(int reg) @@ -175,7 +185,7 @@ uint32_t iosf_port45_read(int reg) void iosf_port45_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x45), reg, val); + iosf_write_port(IOSF_WRITE(0x45), reg, val); } uint32_t iosf_port46_read(int reg) @@ -185,7 +195,7 @@ uint32_t iosf_port46_read(int reg) void iosf_port46_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x46), reg, val); + iosf_write_port(IOSF_WRITE(0x46), reg, val); } uint32_t iosf_port47_read(int reg) @@ -195,7 +205,7 @@ uint32_t iosf_port47_read(int reg) void iosf_port47_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x47), reg, val); + iosf_write_port(IOSF_WRITE(0x47), reg, val); } uint32_t iosf_port55_read(int reg) @@ -205,7 +215,7 @@ uint32_t iosf_port55_read(int reg) void iosf_port55_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x55), reg, val); + iosf_write_port(IOSF_WRITE(0x55), reg, val); } uint32_t iosf_port58_read(int reg) @@ -215,7 +225,7 @@ uint32_t iosf_port58_read(int reg) void iosf_port58_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x58), reg, val); + iosf_write_port(IOSF_WRITE(0x58), reg, val); } uint32_t iosf_port59_read(int reg) @@ -225,7 +235,7 @@ uint32_t iosf_port59_read(int reg) void iosf_port59_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x59), reg, val); + iosf_write_port(IOSF_WRITE(0x59), reg, val); } uint32_t iosf_port5a_read(int reg) @@ -235,7 +245,7 @@ uint32_t iosf_port5a_read(int reg) void iosf_port5a_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0x5a), reg, val); + iosf_write_port(IOSF_WRITE(0x5a), reg, val); } uint32_t iosf_porta2_read(int reg) @@ -245,7 +255,7 @@ uint32_t iosf_porta2_read(int reg) void iosf_porta2_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(0xa2), reg, val); + iosf_write_port(IOSF_WRITE(0xa2), reg, val); } uint32_t iosf_ssus_read(int reg) @@ -255,5 +265,5 @@ uint32_t iosf_ssus_read(int reg) void iosf_ssus_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SSUS), reg, val); + iosf_write_port(IOSF_WRITE(SSUS), reg, val); } diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index e31e15e881..29633e57ee 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -44,11 +44,12 @@ static void lpe_enable_acpi_mode(struct device *dev) static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), + /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), + LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END }; struct global_nvs *gnvs; @@ -123,7 +124,7 @@ static void lpe_stash_firmware_info(struct device *dev) } /* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); /* C0 and later steppings use an offset in the MMIO space. */ diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index cdf78b7314..afeb687be8 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -15,16 +15,16 @@ #include "chip.h" -static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, - int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END }; struct resource *bar; @@ -63,14 +63,17 @@ static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + do { \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_; \ + } while (0) + static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; -#define SET_IOSF_REG(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -104,6 +107,8 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } } +#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ @@ -112,9 +117,6 @@ static void i2c_disable_resets(struct device *dev) REG_SCRIPT_END, }; -#define CASE_I2C(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - switch (dev->path.pci.devfn) { CASE_I2C(I2C1): CASE_I2C(I2C2): @@ -141,8 +143,7 @@ static void lpss_init(struct device *dev) if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func); return; } dev_enable_snoop_and_pm(dev, iosf_reg); diff --git a/src/soc/intel/baytrail/modphy_table.c b/src/soc/intel/baytrail/modphy_table.c new file mode 100644 index 0000000000..f028c8f3de --- /dev/null +++ b/src/soc/intel/baytrail/modphy_table.c @@ -0,0 +1,569 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +struct modphy_entry reva0_modphy_table[] = { /* SOC stepping A0/A1 */ + { 0xa6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa3, 0x00002208, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002408, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002238, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x00002438, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x000080a4, 0xffff0000, 0x0000f487, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008100, 0xfffffffc, 0x00000003, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002318, 0x0000ffff, 0x45140000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0x80ffffff, 0x02000000, 0x00, 0x01 }, + { 0xa3, 0x00002304, 0xff80ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + { 0xa3, 0x00002518, 0x0000ffff, 0x47140000, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0x80ffffff, 0x04000000, 0x00, 0x01 }, + { 0xa3, 0x00002504, 0xff80ffff, 0x00040000, 0x00, 0x01 }, + { 0xa3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + /* Workaround for #4376904, #4682850, #4753319 */ + { 0x43, 0x00007f04, 0xffff0000, 0x00004700, 0x06, 0x07 }, + { 0x43, 0x00004100, 0xfff00000, 0x0004fa01, 0x06, 0x07 }, + { 0x43, 0x00004200, 0xfff00000, 0x0004ea01, 0x06, 0x07 }, + { 0x43, 0x00004300, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004400, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004122, 0x00000000, 0x00004011, 0x06, 0x07 }, + { 0x43, 0x00004222, 0x00000000, 0x06004015, 0x06, 0x07 }, + { 0x43, 0x00004500, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004600, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004700, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004800, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + MODPHY_ENTRY_END +}; + +struct modphy_entry revb0_modphy_table[] = { /* SOC stepping B0 or later */ + { 0xa6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00, 0x01 }, + { 0xa3, 0x00002208, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002408, 0xfffffff3, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002238, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x00002438, 0xfffffff8, 0x00000006, 0x00, 0x01 }, + { 0xa3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00, 0x01 }, + { 0xa3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00008000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x00009800, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xff00ffff, 0x00800000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0x00ffffff, 0x55000000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffffff00, 0x00000046, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000294, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000494, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000694, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000894, 0x7fffffff, 0x80000000, 0x00, 0x01 }, + { 0xa6, 0x000080a4, 0xffff0000, 0x0000f487, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008094, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008034, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa3, 0x00008014, 0xf8ffffff, 0x05000000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00, 0x01 }, + { 0xa6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008068, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008048, 0xffffff0f, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00, 0x01 }, + { 0xa6, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008040, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008060, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080e0, 0xefffffff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00008100, 0xfffffffc, 0x00000003, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00, 0x01 }, + { 0xa6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0xfffffff0, 0x00000009, 0x00, 0x01 }, + { 0xa6, 0x00000314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000714, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000914, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002314, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa3, 0x00002514, 0xfffffff8, 0x00000007, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00, 0x01 }, + { 0xa6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002318, 0x0000ffff, 0x45140000, 0x00, 0x01 }, + { 0xa3, 0x00002300, 0x80ffffff, 0x02000000, 0x00, 0x01 }, + { 0xa3, 0x00002304, 0xff80ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + { 0xa3, 0x00002518, 0x0000ffff, 0x47140000, 0x00, 0x01 }, + { 0xa3, 0x00002500, 0x80ffffff, 0x04000000, 0x00, 0x01 }, + { 0xa3, 0x00002504, 0xff80ffff, 0x00040000, 0x00, 0x01 }, + { 0xa3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00, 0x01 }, + /* Workaround for #4376904, #4682850, #4753319 */ + { 0x43, 0x00007f04, 0xffff0000, 0x00004700, 0x06, 0x07 }, + { 0x43, 0x00004100, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004200, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004300, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004400, 0xfff00000, 0x00049209, 0x06, 0x07 }, + { 0x43, 0x00004500, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004600, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004700, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0x43, 0x00004800, 0xffff7fff, 0x00000000, 0x06, 0x07 }, + { 0xa3, 0x00008100, 0xfffffcff, 0x00000300, 0x00, 0x01 }, + { 0xa3, 0x0000804c, 0x0000ffff, 0x85850000, 0x00, 0x01 }, + { 0xa3, 0x00002290, 0x00ffffff, 0x00600000, 0x00, 0x01 }, + { 0xa3, 0x00002490, 0x00ffffff, 0x00600000, 0x00, 0x01 }, + { 0xa3, 0x0000230c, 0xff00ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x0000250c, 0xff00ffff, 0x00020000, 0x00, 0x01 }, + { 0xa3, 0x000080d0, 0xffffff0f, 0x00000050, 0x00, 0x01 }, + { 0xa6, 0x00000288, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000488, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000688, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000888, 0xffff00ff, 0x0000a000, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000290, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000490, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000690, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0xffff00ff, 0x00005500, 0x00, 0x01 }, + { 0xa6, 0x00000890, 0xff00ffff, 0x003b0000, 0x00, 0x01 }, + { 0xa6, 0x0000030c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000030c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000318, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000318, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000050c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000050c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000518, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000518, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000070c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000070c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000718, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000718, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x0000090c, 0xffffff00, 0x0000009c, 0x00, 0x01 }, + { 0xa6, 0x0000090c, 0xffff00ff, 0x00004b00, 0x00, 0x01 }, + { 0xa6, 0x00000918, 0xff00ffff, 0x009c0000, 0x00, 0x01 }, + { 0xa6, 0x00000918, 0x00ffffff, 0x4b000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000254, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000454, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000654, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000644, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa6, 0x00000854, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa6, 0x00000844, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffff7, 0x00000008, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffffb, 0x00000004, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffffd, 0x00000002, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000200, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xffff00ff, 0x00009500, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000400, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0xff00ffff, 0x00950000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa3, 0x00002254, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002244, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffff9ff, 0x00000600, 0x00, 0x01 }, + { 0xa3, 0x00002454, 0x00ffffff, 0x95000000, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000100, 0x00, 0x01 }, + { 0xa3, 0x00002444, 0xfffffeff, 0x00000000, 0x00, 0x01 }, + MODPHY_ENTRY_END +}; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index c5afa426f6..d221009db1 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -64,7 +64,7 @@ uint32_t nc_read_top_of_low_memory(void) static void nc_read_resources(struct device *dev) { unsigned long mmconf; - unsigned long bmbound; + unsigned long bmbound_k; unsigned long bmbound_hi; unsigned long smmrrh; unsigned long smmrrl; @@ -98,25 +98,26 @@ static void nc_read_resources(struct device *dev) reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); - mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, smmrrh, bmbound_k - smmrrh); - /* The BMBOUND_HI register matches register bits of 31:24 with address - * bits of 35:28. Therefore, shift register to align properly. */ + /* + * The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. + */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) - ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); - /* Reserve everything between A segment and 1MB: + /* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 563739277a..8783e1fde9 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -262,7 +262,6 @@ E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_di REG_SCRIPT_END, }; - static void perf_power(void *unused) { printk(BIOS_DEBUG, "Applying perf/power settings.\n"); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 92e58a018b..cc1dd42fc5 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -230,7 +230,6 @@ void disable_all_gpe(void) disable_gpe(~0); } - static uint32_t reset_gpe_status(void) { uint16_t pmbase = get_pmbase(); @@ -338,12 +337,12 @@ void clear_pmc_status(void) uint32_t prsts; uint32_t gen_pmcon1; - prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts); } int rtc_failure(void) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 099eb588d3..b15970e7b3 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -22,11 +22,10 @@ #include #include -/* Global PATTRS */ -DEFINE_PATTRS; - #define SHOW_PATTRS 1 +struct pattrs __global_pattrs; + static void detect_num_cpus(struct pattrs *attrs) { int ecx = 0; diff --git a/src/soc/intel/baytrail/refcode_native.c b/src/soc/intel/baytrail/refcode_native.c new file mode 100644 index 0000000000..a9976fb409 --- /dev/null +++ b/src/soc/intel/baytrail/refcode_native.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOSF_READ(op_read, port) \ + (IOSF_OPCODE(op_read) | IOSF_PORT(port)) +#define IOSF_WRITE(op_write, port) \ + (IOSF_OPCODE(op_write) | IOSF_PORT(port)) + +static void program_modphy_table(struct modphy_entry *table) +{ + u32 tmp; + + for (; table->port; ++table) { + tmp = iosf_read_port(IOSF_READ(table->op_read, table->port), table->reg); + iosf_write_port(IOSF_WRITE(table->op_write, table->port), table->reg, + (tmp & table->mask) | table->value); + } +} + +static void gpio_sc_sdcard_workaround(void) +{ + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *) IO_BASE_ADDRESS + 0x690, (1 << 3)); + udelay(100); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + udelay(100); + write32((char *) IO_BASE_ADDRESS + 0x830, 0x78480); + udelay(40); + write32((char *) IO_BASE_ADDRESS + 0x830, 0x78080); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0)); + udelay(100); + setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1)); + clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2)); + clrsetbits32((char *) IO_BASE_ADDRESS + 0x690, 7, (1 << 0)); +} + +#define BUNIT_BALIMIT0 0x0b +#define AUNIT_AVCCTL 0x21 +#define AUNIT_ACFCACV 0x60 +#define CUNIT_ACCESS_CTRL_VIOL 0x41 +#define CUINT_SSA_REGIONAL_TRUNKGATE_CTL 0x43 +#define TUNIT_CTL 0x03 +#define TUNIT_MISC_CTL 0x04 + +static void ssa_safe_config(void) +{ + u32 tmp; + + tmp = iosf_bunit_read(BUNIT_BALIMIT0); + iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); + + tmp = iosf_aunit_read(AUNIT_AVCCTL); + iosf_aunit_write(AUNIT_AVCCTL, tmp | 0x80000100); + + tmp = iosf_aunit_read(AUNIT_ACFCACV); + iosf_aunit_write(AUNIT_ACFCACV, tmp & 0x7FFFFFFF); + + tmp = iosf_cunit_read(CUNIT_ACCESS_CTRL_VIOL); + iosf_cunit_write(CUNIT_ACCESS_CTRL_VIOL, tmp & 0x7FFFFFFF); + + iosf_cunit_write(CUINT_SSA_REGIONAL_TRUNKGATE_CTL, 0x70008); + + tmp = iosf_cpu_bus_read(TUNIT_CTL); + iosf_cpu_bus_write(TUNIT_CTL, tmp | 0x110430); + + tmp = iosf_cpu_bus_read(TUNIT_MISC_CTL); + iosf_cpu_bus_write(TUNIT_MISC_CTL, tmp | 0x40010); +} + +#define R_PCH_PMC_MTPMC1 0xb0 + +/* + * Replacement for refcode.elf + */ +void baytrail_run_reference_code(void) +{ + u32 tmp; + size_t pollcnt; + + printk(BIOS_DEBUG, "ModPHY init entry\n"); + + if (pci_read_config8(pcidev_on_root(LPC_DEV, LPC_FUNC), REVID) < RID_B_STEPPING_START) { + printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n"); + program_modphy_table(reva0_modphy_table); + } else { + printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n"); + program_modphy_table(revb0_modphy_table); + } + + setbits32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8); + + for (pollcnt = 0; pollcnt < 10; ++pollcnt) { + tmp = read32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1); + printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp); + if (!(tmp & 8)) + break; + } + + gpio_sc_sdcard_workaround(); + ssa_safe_config(); + + printk(BIOS_DEBUG, "ModPHY init done\n"); +} diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 0b7a8c646d..9a67c22e4b 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -36,7 +36,7 @@ int smbus_enable_iobar(uintptr_t base) pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); - reg |= 0x1; + reg |= PCI_COMMAND_IO; pci_write_config16(smbus_dev, PCI_COMMAND, reg); /* Enable Host Controller */ reg = pci_read_config8(smbus_dev, 0x40); @@ -115,11 +115,15 @@ static void print_dram_info(void *dram_data) populate_smbios_tables(dram_data, speed, num_channels); } +#define SPD_SIZE 256 +static u8 spd_buf[NUM_CHANNELS][SPD_SIZE]; + void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; - struct region_device rdev; + size_t i; + size_t mrc_size; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; @@ -131,11 +135,14 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (!mp->io_hole_mb) mp->io_hole_mb = 2048; - if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { - mp->saved_data_size = region_device_sz(&rdev); - mp->saved_data = rdev_mmap_full(&rdev); - /* Assume boot device is memory mapped. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + mp->saved_data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + 0, + &mrc_size); + if (mp->saved_data) { + mp->saved_data_size = mrc_size; } else if (prev_sleep_state == ACPI_S3) { /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -158,8 +165,20 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) */ mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; - if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) + if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) { + /* Workaround for broken SMBus support in the MRC */ enable_smbus(); + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + for (i = 0; i < NUM_CHANNELS; ++i) { + if (mp->mainboard.spd_addrs[i]) { + i2c_eeprom_read(mp->mainboard.spd_addrs[i], + 0, SPD_SIZE, spd_buf[i]); + /* NOTE: MRC looks for Channel 1 SPD at array + index 1 */ + mp->mainboard.dram_data[i] = spd_buf; + } + } + } ret = mrc_entry(mp); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index ddd657a404..76aa711fc8 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea40b1..24c805ac81 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -128,14 +128,12 @@ static void sata_init(struct device *dev) /* Enable clock for ports */ reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; + reg32 &= ~(config->sata_port_map << 24); pci_write_config32(dev, 0x94, reg32); /* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + pci_write_config32(dev, 0x9c, reg32); } static void sata_enable(struct device *dev) diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index f178e83d28..8e3bd48ddd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include @@ -74,7 +73,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 57cd8f4d1e..34a90317ea 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -12,9 +12,9 @@ #include #include "chip.h" -#define CAP_OVERRIDE_LOW 0xa0 -#define CAP_OVERRIDE_HIGH 0xa4 -# define USE_CAP_OVERRIDES (1 << 31) +#define CAP_OVERRIDE_LOW 0xa0 +#define CAP_OVERRIDE_HIGH 0xa4 +#define USE_CAP_OVERRIDES (1 << 31) static void sd_init(struct device *dev) { @@ -22,10 +22,9 @@ static void sd_init(struct device *dev) if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); - pci_write_config32(dev, CAP_OVERRIDE_LOW, - config->sdcard_cap_low); - pci_write_config32(dev, CAP_OVERRIDE_HIGH, - config->sdcard_cap_high | USE_CAP_OVERRIDES); + pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low); + pci_write_config32(dev, CAP_OVERRIDE_HIGH, config->sdcard_cap_high | + USE_CAP_OVERRIDES); } if (config->scc_acpi_mode) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 57e8583675..1810821ec8 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -68,8 +68,7 @@ static void busmaster_disable_on_bus(int bus) /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); @@ -191,18 +190,17 @@ static void southbridge_smi_gsmi(void) { u32 *ret, *param; uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); if (!io_smi) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32 *)&io_smi->rax; sub_command = (uint8_t)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32 *)&io_smi->rbx; /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -265,8 +263,7 @@ static void soc_legacy(void) static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); + em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); uint32_t reg_ebx; if (!io_smi) @@ -317,14 +314,17 @@ static void southbridge_smi_apmc(void) break; case APM_CNT_GNVS_UPDATE: if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (struct global_nvs *)((uint32_t)state->rbx); + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } @@ -447,8 +447,7 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); + "SMI_STS[%d] occurred, but no handler available.\n", i); } } diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index be541da29a..3f3c53fa74 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include #include #include +#include #include #include +#include +#include #include #include #include @@ -47,7 +47,7 @@ void smm_southbridge_clear_state(void) static void smm_southcluster_route_gpios(void) { - u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); + void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; @@ -60,9 +60,9 @@ static void smm_southcluster_route_gpios(void) /* Enable SMIs for the gpios that are set to trigger the SMI. */ for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); - } + route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index a836d41e59..967a710c2a 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -28,9 +28,8 @@ #include "chip.h" #include -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, - unsigned long size) +static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, + unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } @@ -58,8 +57,7 @@ static inline int io_range_in_default(int base, int size) return 0; /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) return 1; /* This will return not in range for partial overlaps */ @@ -70,8 +68,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(struct device *dev, int base, int size, - int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -113,11 +110,6 @@ static void sc_read_resources(struct device *dev) sc_add_io_resources(dev); } -static void sc_rtc_init(void) -{ - cmos_init(rtc_failure()); -} - /* * The UART hardware loses power while in suspend. Because of this the kernel * can hang because it doesn't re-initialize serial ports it is using for @@ -176,15 +168,14 @@ static void sc_init(struct device *dev) /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - sc_rtc_init(); + cmos_init(rtc_failure()); if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); - write32(gen_pmcon1, - read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + } else { - write32(gen_pmcon1, - read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); + write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } if (acpi_is_wakeup_s3()) @@ -198,9 +189,9 @@ static void sc_init(struct device *dev) /* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { - u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); - u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t mask = 0; + void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); + void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); + uint32_t mask = 0; uint32_t mask2 = 0; switch (dev->path.pci.devfn) { @@ -323,7 +314,7 @@ static inline void set_d3hot_bits(struct device *dev, int offset) */ static void hda_work_around(struct device *dev) { - u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); + void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); @@ -475,8 +466,7 @@ void southcluster_enable_dev(struct device *dev) /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config16(dev, PCI_COMMAND, reg16); /* Place device in D3Hot */ @@ -500,7 +490,7 @@ static void southcluster_inject_dsdt(const struct device *device) gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) memset(gnvs, 0, sizeof(*gnvs)); } @@ -517,12 +507,11 @@ static void southcluster_inject_dsdt(const struct device *device) } } - static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .acpi_inject_dsdt = southcluster_inject_dsdt, - .write_acpi_tables = acpi_write_hpet, + .write_acpi_tables = acpi_write_hpet, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, @@ -542,11 +531,11 @@ int __weak mainboard_get_spi_config(struct spi_config *cfg) static void finalize_chipset(void *unused) { - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); - u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); - u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); - u8 *spi = (u8 *)SPI_BASE_ADDRESS; + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); + void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); + void *etr = (void *)(PMC_BASE_ADDRESS + ETR); + uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; /* Set the lock enable on the BIOS control register */ diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 0acfeaa472..edbc6fd579 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -8,10 +8,8 @@ if SOC_INTEL_BRASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS @@ -29,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_RESET - select SMP select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER @@ -37,7 +34,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP select GENERIC_GPIO_LIB select INTEL_GMA_ACPI @@ -96,7 +93,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 8b52bc7c70..0a22162fc2 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -118,10 +118,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -/* - * Disable as Windows doesn't like it, and systems don't seem to use it. - * IRQNoFlags() { 8 } - */ }) } diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 252a82ac1d..c5569a4df1 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -105,7 +105,6 @@ static void setup_mmconfig(void) pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } - void bootblock_soc_early_init(void) { /* Allow memory-mapped PCI config access */ diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index c971cd1586..25965a04a7 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -22,7 +22,6 @@ static struct device_operations cpu_bus_ops = { .init = soc_init_cpus }; - static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index bf2fe224cc..99a1f309ba 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -39,7 +39,6 @@ enum usb_comp_bg_value { USB_COMP_BG_675_MV = 0, }; - struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 9bef5e2164..04bf1082c3 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -71,7 +71,6 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 75c080d5b6..7e92e9037d 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -68,7 +68,7 @@ static void log_wake_events(const struct chipset_power_state *ps) i = 0; while (gpio_mask) { if (gpio_mask & gpe0_sts) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); gpio_mask <<= 1; i++; } diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 92e6e64422..f78188ee28 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -44,28 +44,28 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -78,7 +78,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which * seems to work fine on Linux 5.0 and Windows 10. */ - fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 1bd0033313..7599329b61 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -14,7 +14,7 @@ static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY), REG_SCRIPT_END }; diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 3195e8cdd3..854d4b5ca7 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -8,7 +8,6 @@ #include #include - #define GPIO_DEBUG /* gpio map to pad number LUTs */ @@ -29,7 +28,6 @@ static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = { 66, 67, 68, 69, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85 }; - static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = { 0, 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19, 20, 21, 22, 30, 31, 32, 33, @@ -156,7 +154,6 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } - static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community) { const struct soc_gpio_map *config; @@ -228,7 +225,6 @@ static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); } - void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) { if (config) { diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 085104a6b6..2a01b2d346 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -69,7 +69,6 @@ #define GP_FAMILY_CONF_REG(community, family) \ (COMMUNITY_BASE(community) + 0x1094 + 0x80 * family) - /* Value written into pad control reg 0 */ #define PAD_CONTROL_REG0_TRISTATE (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z) diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index fcb40d52f7..0ea6335b05 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -126,7 +126,6 @@ #define GPIO_S0_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot) #define GPIO_S5_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot) - /* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x80 #define PIRQ_PIC_IRQ3 0x3 diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index a0d4b4fbca..11c44d0387 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -94,7 +94,7 @@ uint32_t iosf_scc_read(int reg) void iosf_scc_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SCC), reg, val); + iosf_write_port(IOSF_WRITE(SCC), reg, val); } uint32_t iosf_usbphy_read(int reg) @@ -104,7 +104,7 @@ uint32_t iosf_usbphy_read(int reg) void iosf_usbphy_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); + iosf_write_port(IOSF_WRITE(USBPHY), reg, val); } #if ENV_RAMSTAGE diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index 456b3d4a49..a69b85d25a 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -21,7 +21,6 @@ #define LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50) #define LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52) - /* Value written into pad control reg 0 in early init */ #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \ | PAD_GPIOFG_HI_Z \ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 4ad91ae470..14be808136 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -102,7 +102,6 @@ static void setup_codec_clock(struct device *dev) /* Default to always running. */ reg |= CLK_CTL_ON; - printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 7ff42c35df..961d405156 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 1f310d490e..0b47e2f0c3 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -51,7 +51,7 @@ * | Cacheable/Usable | * +--------------------------+ 0 */ -#define RES_IN_KIB(r) ((r) >> 10) +#define RES_IN_KiB(r) ((r) >> 10) uint32_t nc_read_top_of_low_memory(void) { @@ -85,14 +85,13 @@ static void nc_read_resources(struct device *dev) /* Determine TSEG data */ smm_region(&smm_base, &smm_size); - tseg_base_k = RES_IN_KIB(smm_base); - tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); + tseg_base_k = RES_IN_KiB(smm_base); + tseg_top_k = tseg_base_k + RES_IN_KiB(smm_size); /* Determine the base of the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); if (fsp_reserved_memory_area) { - fsp_res_base_k = - RES_IN_KIB((unsigned int)fsp_reserved_memory_area); + fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { /* If no FSP reserverd area */ fsp_res_base_k = tseg_base_k; @@ -100,15 +99,15 @@ static void nc_read_resources(struct device *dev) /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ - base_k = RES_IN_KIB(0); - size_k = RES_IN_KIB(0xa0000) - base_k; + base_k = RES_IN_KiB(0); + size_k = RES_IN_KiB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); /* High memory -> fsp_res_base - cacheable and usable */ - base_k = RES_IN_KIB(0x100000); + base_k = RES_IN_KiB(0x100000); size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); @@ -118,7 +117,7 @@ static void nc_read_resources(struct device *dev) reserved_ram_resource(dev, index++, base_k, size_k); /* TSEG TOP -> bmbound is memory backed mmio. */ - bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory()); + bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); /* @@ -126,10 +125,9 @@ static void nc_read_resources(struct device *dev) * bits of 35:28. Therefore, shift register to align properly. */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); - bmbound_hi = RES_IN_KIB(bmbound_hi) << 4; + bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) - ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); /* * Reserve everything between A segment and 1MB: @@ -138,14 +136,13 @@ static void nc_read_resources(struct device *dev) * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); /* * Reserve local APIC */ - base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE); - size_k = RES_IN_KIB(0x00100000); + base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE); + size_k = RES_IN_KiB(0x00100000); mmio_resource(dev, index++, base_k, size_k); if (CONFIG(CHROMEOS)) diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index cd2fc76312..4497166c6b 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -229,7 +229,6 @@ void disable_all_gpe(void) disable_gpe(~0); } - static uint32_t reset_gpe_status(void) { uint16_t pmbase = get_pmbase(); diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index b6b20b9e1b..a82a4abc28 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -11,7 +11,6 @@ #include "../chip.h" - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -83,7 +82,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } - /* SOC initialization after RAM is enabled */ void soc_after_ram_init(struct romstage_params *params) { diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index f56f153ce4..45ce8de982 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a2c26c119f..6e250d81cc 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -100,7 +100,6 @@ static void tristate_gpios(uint32_t val) write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val); } - static void southbridge_smi_sleep(void) { uint32_t reg32; @@ -301,6 +300,10 @@ static void southbridge_smi_apmc(void) if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (struct global_nvs *)((uint32_t)state->rbx); + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index f5e490f82c..0ea5dbd065 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,10 +8,8 @@ if SOC_INTEL_BROADWELL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT @@ -28,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select PARALLEL_MP select RTC - select SMP select SPI_FLASH select SSE2 select TSC_SYNC_MFENCE @@ -40,7 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select INTEL_GMA_ACPI select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index c76c8d22a8..760842b2ab 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -435,22 +435,19 @@ static unsigned long acpi_fill_dmar(unsigned long current) const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfxvtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4); + + /* First, add DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } /* VTVC0BAR has to be set, enabled, and in 32-bit space */ @@ -468,6 +465,16 @@ static unsigned long acpi_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index ef55699df3..5edfaeecaf 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -11,12 +11,12 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45f91d8aef..ae433536cd 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -8,19 +8,6 @@ #include struct soc_intel_broadwell_config { - /* - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - /* GPE configuration */ uint32_t gpe0_en_1; uint32_t gpe0_en_2; @@ -97,7 +84,6 @@ struct soc_intel_broadwell_config { u8 gpu_dp_d_hotplug; /* Panel power sequence timings */ - u8 gpu_panel_port_select; u8 gpu_panel_power_cycle_delay; u16 gpu_panel_power_up_delay; u16 gpu_panel_power_down_delay; @@ -152,7 +138,7 @@ struct soc_intel_broadwell_config { int deep_sx_enable_dc; /* TCC activation offset */ - int tcc_offset; + uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1312525814..8a38137b9d 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -355,7 +355,7 @@ static void set_max_ratio(void) } wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "cpu: frequency set to %d\n", + printk(BIOS_DEBUG, "CPU: frequency set to %d\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } @@ -375,7 +375,7 @@ static void set_energy_perf_bias(u8 policy) msr.lo |= policy & 0xf; wrmsr(IA32_ENERGY_PERF_BIAS, msr); - printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); + printk(BIOS_DEBUG, "CPU: energy policy set to %u\n", policy); } static void configure_mca(void) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index f918958896..9271e27872 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -16,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } @@ -48,7 +48,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* GPIO27 */ if (ps->gpe0_sts[GPE_STD] & GP27_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, 27); /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/fadt.c index 0deeab54bd..f39ad801e0 100644 --- a/src/soc/intel/broadwell/fadt.c +++ b/src/soc/intel/broadwell/fadt.c @@ -43,28 +43,28 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index b85b663cc4..300301bbf9 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -41,7 +41,7 @@ const struct reg_script system_agent_finalize_script[] = { }; const struct reg_script pch_finalize_script[] = { -#if !CONFIG(SPI_CONSOLE) +#if !CONFIG(EM100PRO_SPI_CONSOLE) /* Lock SPIBAR */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN), @@ -65,7 +65,6 @@ const struct reg_script pch_finalize_script[] = { /* PMSYNC */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), - REG_SCRIPT_END }; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1cf9..ba453cdb27 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -298,7 +298,6 @@ static void igd_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PCH_PP_ON_DELAYS, reg32); diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h index 39c48d3f3f..bc9f220af7 100644 --- a/src/soc/intel/broadwell/include/soc/pei_data.h +++ b/src/soc/intel/broadwell/include/soc/pei_data.h @@ -63,7 +63,6 @@ struct usb3_port_setting { #define PEI_DIMM_INFO_PART_NUMBER_SIZE 19 #define PEI_DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */ - /** * This table is filled by the MRC blob and used to populate the mem_info * struct, which is placed in CBMEM and then used to generate SMBIOS type diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c index 76a3e58c3e..deb4156198 100644 --- a/src/soc/intel/broadwell/iobp.c +++ b/src/soc/intel/broadwell/iobp.c @@ -91,8 +91,12 @@ void pch_iobp_write(u32 address, u32 data) /* Check for successful transaction */ status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) + if (status & IOBPS_TX_MASK) { printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); + return; + } + + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); } void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 58cd35d1f6..b3f4fe5b2a 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -90,17 +90,18 @@ static void enable_hpet(struct device *dev) static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - config_t *config = config_of(dev); - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + const uint8_t pirq = 0x80; - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq); + pci_write_config8(dev, PIRQB_ROUT, pirq); + pci_write_config8(dev, PIRQC_ROUT, pirq); + pci_write_config8(dev, PIRQD_ROUT, pirq); + + pci_write_config8(dev, PIRQE_ROUT, pirq); + pci_write_config8(dev, PIRQF_ROUT, pirq); + pci_write_config8(dev, PIRQG_ROUT, pirq); + pci_write_config8(dev, PIRQH_ROUT, pirq); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; @@ -112,16 +113,10 @@ static void pch_pirq_init(struct device *dev) switch (int_pin) { case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; case 4: /* INTD# */ - int_line = config->pirqd_routing; + int_line = pirq; break; } diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 11b21ac959..fa44c7c79d 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -13,7 +13,6 @@ (__array__)[(__index__)] : \ (__default__)) - static inline void me_read_dword_ptr(void *ptr, int offset) { u32 dword = pci_read_config32(PCH_DEV_ME, offset); diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index bada5fd1c1..4673cceca0 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -18,7 +18,7 @@ static uintptr_t dpr_region_start(void) * must be calculated from the size in MiB in bits 11:4. */ uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); - uintptr_t tom = dpr & ~((1 << 20) - 1); + uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB); /* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 14dcd3f556..00a8595eeb 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -587,7 +587,6 @@ static void pch_pcie_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Clear errors in status registers */ diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 502a046474..92cf3637f9 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -52,7 +52,6 @@ static void print_gpio_status(u32 status, int start) } } - /* * PM1_CNT */ @@ -73,7 +72,6 @@ void disable_pm1_control(u32 mask) outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); } - /* * PM1 */ @@ -122,7 +120,6 @@ void enable_pm1(u16 events) outw(events, ACPI_BASE_ADDRESS + PM1_EN); } - /* * SMI */ @@ -193,7 +190,6 @@ void disable_smi(u32 mask) outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } - /* * ALT_GP_SMI */ @@ -244,7 +240,6 @@ void enable_alt_smi(u32 mask) outl(alt_en, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); } - /* * TCO */ @@ -312,7 +307,6 @@ void enable_tco_sci(void) enable_gpe(TCOSCI_EN); } - /* * GPE0 */ diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 4165c678d2..0580ca69b0 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -26,7 +26,7 @@ */ void raminit(struct pei_data *pei_data) { - struct region_device rdev; + size_t mrc_size; struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; @@ -39,19 +39,25 @@ void raminit(struct pei_data *pei_data) vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(MRC_TRAINING_DATA, 0, &rdev)) { - /* MRC cache found */ - pei_data->saved_data_size = region_device_sz(&rdev); - pei_data->saved_data = rdev_mmap_full(&rdev); + } else { /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - } else if (pei_data->boot_mode == ACPI_S3) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - system_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); + + pei_data->saved_data = + mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, + &mrc_size); + if (pei_data->saved_data) { + /* MRC cache found */ + pei_data->saved_data_size = mrc_size; + } else if (pei_data->boot_mode == ACPI_S3) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + system_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + } } /* diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 1029395bf2..938f3ebd37 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -76,7 +77,6 @@ static void report_cpu_info(void) u32 i, index, cpu_id, cpu_feature_flag; char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; const char *mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; @@ -98,11 +98,7 @@ static void report_cpu_info(void) while (cpu_name[0] == ' ') cpu_name++; - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -114,7 +110,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 5ddccc52f0..b1d953ef73 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -36,7 +36,8 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ @@ -199,7 +200,6 @@ static void sata_init(struct device *dev) << SATA_DTLE_EDGE_SHIFT); } - /* * Additional Programming Requirements for Power Optimizer */ diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 86be400e71..1732ef7803 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -100,6 +100,10 @@ static void backlight_off(void) reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0) & ~0xf); + /* Validate pointer before using it */ + if (smm_points_to_smram(reg_base, PCH_PP_OFF_DELAYS + sizeof(uint32_t))) + return; + /* Check if backlight is enabled */ pp_ctrl = read32(reg_base + PCH_PP_CONTROL); if (!(pp_ctrl & EDP_BLC_ENABLE)) @@ -341,6 +345,10 @@ static void southbridge_smi_apmc(void) if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (struct global_nvs *)((u32)state->rbx); + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } @@ -457,7 +465,6 @@ static void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 03ed24494b..3d4162abd0 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -18,7 +18,6 @@ #include #include - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fc7fb460d0..9bd9f43314 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -47,6 +47,22 @@ config SOC_INTEL_COMETLAKE help Intel Cometlake support +config SOC_INTEL_COMETLAKE_1 + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_2 + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_S + bool + select SOC_INTEL_COMETLAKE + +config SOC_INTEL_COMETLAKE_V + bool + select SOC_INTEL_COMETLAKE + config SOC_INTEL_CANNONLAKE_PCH_H bool help @@ -58,11 +74,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON @@ -83,8 +95,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK @@ -295,7 +307,7 @@ choice config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED + select USE_CAR_NEM_ENHANCED_V1 help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified @@ -314,12 +326,18 @@ endchoice config FSP_HEADER_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE - default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2 + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S + default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT int "Debug Consent for CNL" diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index e8f4a1535e..f061c30bf4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -167,7 +167,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 5deb26a043..f1284e1412 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include -#include "gpio_op.asl" Device (GPIO) { @@ -61,7 +61,7 @@ Device (GPIO) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11))) + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) @@ -73,19 +73,19 @@ Method (GADD, 1, NotSerialized) Subtract (Arg0, GPP_D0, Local1) } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) + If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, DRAM_RESET_B))) { - Store (PID_GPIOCOM1, Local0) + Store (PID_GPIOCOM2, Local0) Subtract (Arg0, GPD0, Local1) } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38))) + If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT))) { - Store (PID_GPIOCOM1, Local0) + Store (PID_GPIOCOM3, Local0) Subtract (Arg0, HDA_BCLK, Local1) } - /* GPIO Community 04*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27))) + /* GPIO Community 4*/ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B))) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_C0, Local1) diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index 114b7b7169..5b3123df2c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include -#include "gpio_op.asl" Device (GPIO) { @@ -67,25 +67,25 @@ Device (GPIO) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK))) { Store (PID_GPIOCOM0, Local0) Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7))) + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD))) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_C0, Local1) } /* GPIO Community 3*/ - If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23))) + If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK))) { Store (PID_GPIOCOM3, Local0) Subtract (Arg0, GPP_K0, Local1) } /* GPIO Community 4*/ - If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11))) + If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11))) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_I0, Local1) diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl deleted file mode 100644 index 3c0ed66f58..0000000000 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) - - Return (Local0) -} - -/* - * Get GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (GTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIOTXSTATE_MASK, VAL0, Local0) - - Return (Local0) -} - -/* - * Set GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (STXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) -} - -/* - * Clear GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (CTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) -} - -/* - * Set Pad mode - * Arg0 - GPIO Number - * Arg1 - Pad mode - * 0 = GPIO control pad - * 1 = Native Function 1 - * 2 = Native Function 2 - * 3 = Native Function 3 - */ -Method (GPMO, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Store (VAL0, Local0) - And (Not (GPIOPADMODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) -} - -/* - * Enable/Disable Tx buffer - * Arg0 - GPIO Number - * Arg1 - TxBuffer state - * 0 = Disable Tx Buffer - * 1 = Enable Tx Buffer - */ -Method (GTXE, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - - If (LEqual (Arg1, 1)) { - And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) - } -} - -/* - * Enable/Disable Rx buffer - * Arg0 - GPIO Number - * Arg1 - RxBuffer state - * 0 = Disable Rx Buffer - * 1 = Enable Rx Buffer - */ -Method (GRXE, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - - If (LEqual (Arg1, 1)) { - And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIORXBUFDIS_MASK, VAL0, VAL0) - } -} diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl deleted file mode 100644 index 98ca6781d7..0000000000 --- a/src/soc/intel/cannonlake/acpi/ish.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Integrated Sensor Hub Controller 0:13.0 */ - -Device (ISHB) -{ - Name (_ADR, 0x00130000) - Name (_DDN, "Integrated Sensor Hub Controller") -} diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl deleted file mode 100644 index 0653d3b7c0..0000000000 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -External(\_SB.MS0X, MethodObj) -External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) -External(\_SB.PCI0.EGPM, MethodObj) -External(\_SB.PCI0.RGPM, MethodObj) - -scope(\_SB) -{ - Device(LPID) { - Name(_ADR, 0x00000000) - Name(_CID, EISAID("PNP0D80")) - Name(UUID, - ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) - Method(_DSM, 4) { - If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == Zero) { - Return(Buffer(One) { - 0x60} - ) - } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == 1) { - Return(Package(5) { - 0, Ones, Ones, Ones, Ones} - ) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == 2) { - Return(Buffer(One) { - 0x0} - ) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == 3) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == 4) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == 5) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(1) - } - - /* provide board level s0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(1) - } - - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ - If (CondRefOf (\_SB.PCI0.EGPM)) - { - \_SB.PCI0.EGPM () - } - } - /* - * Function 6 - Low Power S0 Exit Notification - */ - If(Arg2 == 6) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(0) - } - - /* provide board level s0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (\_SB.PCI0.RGPM)) - { - \_SB.PCI0.RGPM () - } - } - } - Return(Buffer(One) {0x00}) - } // Method(_DSM) - } // device (LPID) -} // End Scope(\_SB) diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7ac80..0000000000 --- a/src/soc/intel/cannonlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index 04e974fe11..f292901b05 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -4,7 +4,7 @@ Device (HDAS) { - Name (_ADR, 0x001F0003) + Name (_ADR, 0x001f0003) Name (_DDN, "Audio Controller") Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl index b646b9067e..17e3aa51c6 100644 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl @@ -24,11 +24,13 @@ Name (PICP, Package () { Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* PCI Express Port 17-24 */ - Package(){0x001BFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001BFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001BFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001BFFFF, 3, 0, PCIE_4_IRQ }, + Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, + Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, + Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, + Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, +#endif /* eMMC */ Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, /* SerialIo */ @@ -74,7 +76,7 @@ Name (PICP, Package () { Name (PICN, Package () { /* - * If the setting change in soc_pch_pirq_init(), then + * If the setting change in pch_pirq_init(), then * please make the same static IRQ changes here as well. */ /* D31: cAVS, SMBus, GbE, Nothpeak */ @@ -93,11 +95,13 @@ Name (PICN, Package () { Package () { 0x001CFFFF, 1, 0, 10 }, Package () { 0x001CFFFF, 2, 0, 11 }, Package () { 0x001CFFFF, 3, 0, 11 }, +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* D27: PCI Express Port 17-24 */ Package () { 0x001BFFFF, 0, 0, 11 }, Package () { 0x001BFFFF, 1, 0, 10 }, Package () { 0x001BFFFF, 2, 0, 11 }, Package () { 0x001BFFFF, 3, 0, 11 }, +#endif /* D25: Can't use PIC*/ /* D23 */ Package () { 0x0017FFFF, 0, 0, 11 }, diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 0371f89792..302863baba 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -54,7 +54,11 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13, 17, 21 }) { + Case (Package () { 1, 5, 9, 13 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 17, 21 +#endif + }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +66,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 2, 6, 10, 14, 18, 22 }) { + Case (Package () { 2, 6, 10, 14 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 18, 22 +#endif + }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +78,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 3, 7, 11, 15, 19, 23 }) { + Case (Package () { 3, 7, 11, 15 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 19, 23 +#endif + }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +90,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 4, 8, 12, 16, 20, 24 }) { + Case (Package () { 4, 8, 12, 16 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 20, 24 +#endif + }) { If (PICM) { Return (IQDA) } Else { @@ -368,6 +384,7 @@ Device (RP16) } } +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) Device (RP17) { Name (_ADR, 0x001B0000) @@ -503,3 +520,4 @@ Device (RP24) Return (IRQM (RPPN)) } } +#endif diff --git a/src/soc/intel/cannonlake/acpi/platform.asl b/src/soc/intel/cannonlake/acpi/platform.asl deleted file mode 100644 index 73458641fa..0000000000 --- a/src/soc/intel/cannonlake/acpi/platform.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Enable ACPI _SWS methods */ -#include -/* Generic indicator for sleep state */ -#include - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl deleted file mode 100644 index 7860f606c9..0000000000 --- a/src/soc/intel/cannonlake/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.4 - -Device (SBUS) -{ - Name (_ADR, 0x001f0004) -} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 9cdd3b50ba..0ba85e8e5a 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -//TODO: fix inclusion when using gma ACPI #include "gfx.asl" +//TODO: fix inclusion when using gma ACPI #include /* LPC 0:1f.0 */ #include @@ -32,10 +32,10 @@ #include "serialio.asl" /* SMBus 0:1f.4 */ -#include "smbus.asl" +#include /* ISH 0:13.0 */ -#include "ish.asl" +#include /* USB XHCI 0:14.0 */ #include "xhci.asl" @@ -43,5 +43,8 @@ /* PCI _OSC */ #include -/* GBe 0:1f.6 */ -#include "pch_glan.asl" +/* GbE 0:1f.6 */ +#include + +/* PMC Core */ +#include diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index de32fcda3d..a72b66e75f 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -65,4 +66,7 @@ void bootblock_soc_init(void) gpi_clear_int_cfg(); report_platform_info(); bootblock_pch_init(); + + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index ae52f45454..242aa71141 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -59,26 +59,20 @@ static uint32_t get_pmc_reg_base(void) static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) @@ -95,7 +89,6 @@ void bootblock_pch_early_init(void) soc_config_pwrmbase(); } - static void soc_config_acpibase(void) { uint32_t pmc_reg_value; diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 3ccfcc93d3..6e675f5658 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -12,8 +13,6 @@ #include #include -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -171,17 +170,11 @@ static void report_cpu_info(void) u32 i, cpu_id, cpu_feature_flag; char cpu_name[49]; int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -193,7 +186,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index ef85215623..17698460f7 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -127,7 +127,6 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3457f4d100..2f5c27638f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -115,7 +114,6 @@ struct soc_intel_cannonlake_config { SaGv_Enabled, } SaGv; - /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; @@ -186,6 +184,8 @@ struct soc_intel_cannonlake_config { uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Implemented as slot or built-in? */ + uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; @@ -227,7 +227,6 @@ struct soc_intel_cannonlake_config { uint8_t PchIshEnable; /* Heci related */ - uint8_t Heci3Enabled; uint8_t DisableHeciRetry; /* Gfx related */ diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 36d252e477..0c24535816 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -54,9 +54,10 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_soc(); msr_t msr; + config_t *conf = config_of_soc(); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ @@ -105,6 +106,33 @@ static void configure_dca_cap(void) } } +/* + * The emulated ACPI timer allows replacing of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void enable_pm_timer_emulation(void) +{ + const struct soc_intel_cannonlake_config *config; + msr_t msr; + + config = config_of_soc(); + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -155,33 +183,6 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -/* - * The emulated ACPI timer allows replacing of the ACPI timer - * (PM1_TMR) to have no impart on the system. - */ -static void enable_pm_timer_emulation(void) -{ - const struct soc_intel_cannonlake_config *config; - msr_t msr; - - config = config_of_soc(); - - /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) - return; - /* - * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. - */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index fb254729da..3600d76d95 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -98,7 +97,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a9d3..9eb9cbea8c 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,6 @@ static void pch_finalize(void) uint32_t reg32; uint8_t *pmcbase; config_t *config; - uint8_t reg8; tco_lockdown(); @@ -70,17 +70,12 @@ static void pch_finalize(void) */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); if (config->s0ix_enable) { /* Disable XTAL shutdown qualification for low power idle. */ - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); + pmc_ignore_xtal_shutdown(); if (config->cppmvric2_adsposcdis) { /* Enable Audio DSP OSC qualification for S0ix */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d6e874e51a..613398ba57 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -32,39 +33,6 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; -/* List of Minimum Assertion durations in microseconds */ -enum min_assrt_dur { - MinAssrtDur0s = 0, - MinAssrtDur60us = 60, - MinAssrtDur1ms = 1000, - MinAssrtDur50ms = 50000, - MinAssrtDur98ms = 98000, - MinAssrtDur500ms = 500000, - MinAssrtDur1s = 1000000, - MinAssrtDur2s = 2000000, - MinAssrtDur3s = 3000000, - MinAssrtDur4s = 4000000, -}; - - -/* Signal Assertion duration values */ -struct cfg_assrt_dur { - /* Minimum assertion duration of SLP_A signal */ - enum min_assrt_dur slp_a; - - /* Minimum assertion duration of SLP_4 signal */ - enum min_assrt_dur slp_s4; - - /* Minimum assertion duration of SLP_3 signal */ - enum min_assrt_dur slp_s3; - - /* PCH PM Power Cycle duration */ - enum min_assrt_dur pm_pwr_cyc_dur; -}; - -/* Default value of PchPmPwrCycDur */ -#define PCH_PM_PWR_CYC_DUR 4 - /* * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP * UPD expected value for Serial IO since valid enum index starts from 1. @@ -90,93 +58,6 @@ static uint8_t get_param_value(const config_t *config, uint32_t dev_offset) } #if CONFIG(SOC_INTEL_COMETLAKE) -static enum min_assrt_dur get_high_asst_width(const struct cfg_assrt_dur *cfg_assrt_dur) -{ - enum min_assrt_dur max_assert_dur = cfg_assrt_dur->slp_s4; - - if (max_assert_dur < cfg_assrt_dur->slp_s3) - max_assert_dur = cfg_assrt_dur->slp_s3; - - if (max_assert_dur < cfg_assrt_dur->slp_a) - max_assert_dur = cfg_assrt_dur->slp_a; - - return max_assert_dur; -} - -static void get_min_assrt_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, - uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur, - struct cfg_assrt_dur *cfg_assrt_dur) -{ - /* - * Ensure slp_x_dur_list[] elements are in sync with devicetree config to FSP encoded - * values. - * slp_s4_asst_dur_list : 1s, 1s, 2s, 3s, 4s(Default) - */ - const enum min_assrt_dur slp_s4_asst_dur_list[] = { - MinAssrtDur1s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s - }; - - /* slp_s3_asst_dur_list: 50ms, 60us, 50ms (Default), 2s */ - const enum min_assrt_dur slp_s3_asst_dur_list[] = { - MinAssrtDur50ms, MinAssrtDur60us, MinAssrtDur50ms, MinAssrtDur2s - }; - - /* slp_a_asst_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ - const enum min_assrt_dur slp_a_asst_dur_list[] = { - MinAssrtDur2s, MinAssrtDur0s, MinAssrtDur4s, MinAssrtDur98ms, MinAssrtDur2s - }; - - /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ - const enum min_assrt_dur pm_pwr_cyc_dur_list[] = { - MinAssrtDur4s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s - }; - - /* Get signal assertion width */ - if (slp_s4_min_asst < ARRAY_SIZE(slp_s4_asst_dur_list)) - cfg_assrt_dur->slp_s4 = slp_s4_asst_dur_list[slp_s4_min_asst]; - - if (slp_s3_min_asst < ARRAY_SIZE(slp_s3_asst_dur_list)) - cfg_assrt_dur->slp_s3 = slp_s3_asst_dur_list[slp_s3_min_asst]; - - if (slp_a_min_asst < ARRAY_SIZE(slp_a_asst_dur_list)) - cfg_assrt_dur->slp_a = slp_a_asst_dur_list[slp_a_min_asst]; - - if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) - cfg_assrt_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; -} - - -static uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, - uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur) -{ - /* Sets default minimum asserton duration values */ - struct cfg_assrt_dur cfg_assrt_dur = { - .slp_a = MinAssrtDur2s, - .slp_s4 = MinAssrtDur4s, - .slp_s3 = MinAssrtDur50ms, - .pm_pwr_cyc_dur = MinAssrtDur4s - }; - - enum min_assrt_dur high_asst_width; - - /* Convert assertion durations from register-encoded to microseconds */ - get_min_assrt_dur(slp_s4_min_asst, slp_s3_min_asst, slp_a_min_asst, pm_pwr_cyc_dur, - &cfg_assrt_dur); - - /* Get the higher assertion duration among PCH EDS specified signals for pwr_cyc_dur */ - high_asst_width = get_high_asst_width(&cfg_assrt_dur); - - if (cfg_assrt_dur.pm_pwr_cyc_dur >= high_asst_width) - return pm_pwr_cyc_dur; - - printk(BIOS_DEBUG, - "Set PmPwrCycDur to 4s as configured PmPwrCycDur(%d) violates PCH EDS " - "spec\n", pm_pwr_cyc_dur); - - return PCH_PM_PWR_CYC_DUR; -} - - static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) { uint32_t dev_offset = 0; @@ -262,15 +143,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { - params->Usb2OverCurrentPin[i] = 0; - } - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { - params->Usb3OverCurrentPin[i] = 0; - } - mainboard_silicon_init_params(params); const struct soc_power_limits_config *soc_config; @@ -292,15 +164,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else { params->SataEnable = dev->enabled; params->SataMode = config->SataMode; + params->SataPwrOptEnable = config->satapwroptimize; params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); - memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, sizeof(params->SataPortsHotPlug)); - #if CONFIG(SOC_INTEL_COMETLAKE) memcpy(params->SataPortsDevSlpResetConfig, config->SataPortsDevSlpResetConfig, @@ -374,18 +245,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } if (config->PchUsb2PhySusPgDisable) @@ -393,7 +268,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = @@ -448,7 +327,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; #if !CONFIG(SOC_INTEL_COMETLAKE) - params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE; + params->SerialIoEnableDebugUartAfterPost = CONFIG(INTEL_LPSS_UART_FOR_CONSOLE); #endif /* Enable CNVi Wifi if enabled in device tree */ @@ -482,6 +361,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); + memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented, + sizeof(config->PcieRpSlotImplemented)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); @@ -491,7 +372,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; }; - /* eMMC and SD */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (!dev) @@ -526,9 +406,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->ScsUfsEnabled = dev->enabled; - params->Heci3Enabled = config->Heci3Enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = is_dev_enabled(dev); #if !CONFIG(HECI_DISABLE_USING_SMM) - params->Heci1Disabled = !config->HeciEnabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE); + params->Heci1Disabled = !is_dev_enabled(dev); #endif params->Device4Enable = config->Device4Enable; @@ -552,9 +434,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; - /* Power Optimizer */ - params->SataPwrOptEnable = config->satapwroptimize; - /* Disable PCH ACPI timer */ params->EnableTcoTimer = !config->PmTimerDisabled; @@ -647,6 +526,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PeiGraphicsPeimInit = 0; + params->PavpEnable = CONFIG(PAVP); + /* Disable setting subsystem ID, which causes it to lock */ struct svid_ssid_init_entry { union { diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 91ac47c0b5..3c70ad9a5b 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -32,14 +32,14 @@ static const struct reset_mapping rst_map_com0[] = { * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c */ static const struct pad_group cnl_community0_groups[] = { - INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */ - INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */ + INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */ + INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */ INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64), /* GPP_G */ - INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */ + INTEL_GPP(GPP_A0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */ }; static const struct pad_group cnl_community1_groups[] = { - INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */ + INTEL_GPP_BASE(GPP_D0, GPP_D0, GSPI2_CLK_LOOPBK, 96), /* GPP_D */ INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */ INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */ INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192), /* VGPIO */ @@ -47,20 +47,20 @@ static const struct pad_group cnl_community1_groups[] = { /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; /* This community is not visible to the OS */ static const struct pad_group cnl_community3_groups[] = { - INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ - INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */ + INTEL_GPP(HDA_BCLK, HDA_BCLK, I2S1_TXD), /* AZA */ + INTEL_GPP(HDA_BCLK, HDACPU_SDI, TRIGGER_OUT), /* CPU */ }; static const struct pad_group cnl_community4_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */ - INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ + INTEL_GPP(GPP_C0, PCH_TDO, ITP_PMODE), /* JTAG */ + INTEL_GPP(GPP_C0, EDP_BKLTEN, CL_RST_B), /* HVMOS */ }; static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { @@ -68,7 +68,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, - .last_pad = GPIO_RSVD_11, + .last_pad = SPI0_CLK_LOOPBK, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -108,7 +108,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -128,7 +128,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, - .last_pad = GPIO_RSVD_38, + .last_pad = TRIGGER_OUT, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -148,7 +148,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, - .last_pad = GPIO_RSVD_27, + .last_pad = CL_RST_B, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index eb333fd00a..06e344d16f 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -32,22 +32,22 @@ static const struct reset_mapping rst_map_com0[] = { * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c */ static const struct pad_group cnl_community0_groups[] = { - INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */ - INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */ + INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */ + INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */ }; static const struct pad_group cnl_community1_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */ INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */ - INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10), /* AZA */ + INTEL_GPP(GPP_C0, HDA_BCLK, I2S1_TXD), /* AZA */ INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */ INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD), /* VGPIO_1 */ }; /* This community is not visible to the OS */ static const struct pad_group cnl_community2_groups[] = { - INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ + INTEL_GPP(GPD0, GPD0, DRAM_RESET_B), /* GPD */ }; static const struct pad_group cnl_community3_groups[] = { @@ -55,14 +55,14 @@ static const struct pad_group cnl_community3_groups[] = { INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */ INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */ INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */ - INTEL_GPP(GPP_K0, GPIO_RSVD_11, GPIO_RSVD_19), /* SPI */ + INTEL_GPP(GPP_K0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */ }; static const struct pad_group cnl_community4_groups[] = { - INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_20, GPIO_RSVD_30), /* CPU */ - INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_31, GPIO_RSVD_39), /* JTAG */ - INTEL_GPP_BASE(GPIO_RSVD_20, GPP_I0, GPP_I14, 320), /* GPP_I */ - INTEL_GPP_BASE(GPIO_RSVD_20, GPP_J0, GPP_J11, 352), /* GPP_J */ + INTEL_GPP(HDACPU_SDI, HDACPU_SDI, TRIGGER_OUT), /* CPU */ + INTEL_GPP(HDACPU_SDI, PCH_TDO, ITP_PMODE), /* JTAG */ + INTEL_GPP_BASE(HDACPU_SDI, GPP_I0, GPP_I14, 320), /* GPP_I */ + INTEL_GPP_BASE(HDACPU_SDI, GPP_J0, GPP_J11, 352), /* GPP_J */ }; static const struct pad_community cnl_communities[] = { @@ -70,7 +70,7 @@ static const struct pad_community cnl_communities[] = { [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, - .last_pad = GPIO_RSVD_2, + .last_pad = GSPI1_CLK_LOOPBK, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -110,7 +110,7 @@ static const struct pad_community cnl_communities[] = { [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, - .last_pad = GPD11, + .last_pad = DRAM_RESET_B, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -130,7 +130,7 @@ static const struct pad_community cnl_communities[] = { [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = GPP_K0, - .last_pad = GPIO_RSVD_19, + .last_pad = SPI0_CLK_LOOPBK, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -149,7 +149,7 @@ static const struct pad_community cnl_communities[] = { /* GPP I, J */ [COMM_4] = { .port = PID_GPIOCOM4, - .first_pad = GPIO_RSVD_20, + .first_pad = HDACPU_SDI, .last_pad = GPP_J11, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h deleted file mode 100644 index c11ef50403..0000000000 --- a/src/soc/intel/cannonlake/include/soc/gpio_common.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ -#define _SOC_CANNONLAKE_GPIO_COMMON_H_ - -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIORXBUFDIS_MASK 0x200 - -#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 9b1690ea9d..e7769b5f31 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include #endif -#include #include #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index a1f51d1d97..bd68b04f9b 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include #endif -#include #include #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index f5a926296e..48cbacb8e1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -57,7 +57,7 @@ #define GPP_A21 21 #define GPP_A22 22 #define GPP_A23 23 -#define GPIO_RSVD_0 24 +#define ESPI_CLK_LOOPBK 24 /* Group B */ #define GPP_B0 25 #define GPP_B1 26 @@ -83,8 +83,8 @@ #define GPP_B21 46 #define GPP_B22 47 #define GPP_B23 48 -#define GPIO_RSVD_1 49 -#define GPIO_RSVD_2 50 +#define GSPI0_CLK_LOOPBK 49 +#define GSPI1_CLK_LOOPBK 50 /* Group G */ #define GPP_G0 51 #define GPP_G1 52 @@ -95,17 +95,17 @@ #define GPP_G6 57 #define GPP_G7 58 /* Group SPI */ -#define GPIO_RSVD_3 59 -#define GPIO_RSVD_4 60 -#define GPIO_RSVD_5 61 -#define GPIO_RSVD_6 62 -#define GPIO_RSVD_7 63 -#define GPIO_RSVD_8 64 -#define GPIO_RSVD_9 65 -#define GPIO_RSVD_10 66 -#define GPIO_RSVD_11 67 +#define SPI0_IO_2 59 +#define SPI0_IO_3 60 +#define SPI0_MOSI 61 +#define SPI0_MISO 62 +#define SPI0_CS2_B 63 +#define SPI0_CS0_B 64 +#define SPI0_CS1_B 65 +#define SPI0_CLK 66 +#define SPI0_CLK_LOOPBK 67 -#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1) +#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1) /* Group D */ #define GPP_D0 68 @@ -132,7 +132,7 @@ #define GPP_D21 89 #define GPP_D22 90 #define GPP_D23 91 -#define GPIO_RSVD_12 92 +#define GSPI2_CLK_LOOPBK 92 /* Group F */ #define GPP_F0 93 #define GPP_F1 94 @@ -183,12 +183,12 @@ #define GPP_H21 138 #define GPP_H22 139 #define GPP_H23 140 -/* Group VGPIO */ +/* Group VGPIO 0 */ #define CNV_BTEN 141 #define CNV_GNEN 142 #define CNV_WFEN 143 #define CNV_WCEN 144 -#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_HOST_WAKE_B 145 #define CNV_BT_IF_SELECT 146 #define vCNV_BT_UART_TXD 147 #define vCNV_BT_UART_RXD 148 @@ -216,13 +216,14 @@ #define vISH_UART1_RTS_B 170 #define vCNV_BT_I2S_BCLK 171 #define vCNV_BT_I2S_WS_SYNC 172 +/* Group VGPIO 1 */ #define vCNV_BT_I2S_SDO 173 #define vCNV_BT_I2S_SDI 174 #define vSSP2_SCLK 175 #define vSSP2_SFRM 176 #define vSSP2_TXD 177 #define vSSP2_RXD 178 -#define vCNV_GNSS_HOST_WAKEB 179 +#define vCNV_GNSS_HOST_WAKE_B 179 #define vSD3_CD_B 180 #define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1) @@ -278,26 +279,26 @@ #define GPP_E22 227 #define GPP_E23 228 /* Group Jtag */ -#define GPIO_RSVD_13 229 -#define GPIO_RSVD_14 230 -#define GPIO_RSVD_15 231 -#define GPIO_RSVD_16 232 -#define GPIO_RSVD_17 233 -#define GPIO_RSVD_18 234 -#define GPIO_RSVD_19 235 -#define GPIO_RSVD_20 236 -#define GPIO_RSVD_21 237 +#define PCH_TDO 229 +#define PCH_JTAGX 230 +#define PROC_PRDY_B 231 +#define PROC_PREQ_B 232 +#define CPU_TRST_B 233 +#define PCH_TDI 234 +#define PCH_TMS 235 +#define PCH_TCK 236 +#define ITP_PMODE 237 /* Group HVMOS */ -#define GPIO_RSVD_22 238 -#define GPIO_RSVD_23 239 -#define GPIO_RSVD_24 240 -#define GPIO_RSVD_25 241 -#define GPIO_RSVD_26 242 -#define GPIO_RSVD_27 243 +#define EDP_BKLTEN 238 +#define EDP_BKLTCTL 239 +#define EDP_VDDEN 240 +#define SYS_PWROK 241 +#define SYS_RESET_B 242 +#define CL_RST_B 243 -#define NUM_GPIO_COM4_PADS (GPIO_RSVD_27 - GPP_C0 + 1) +#define NUM_GPIO_COM4_PADS (CL_RST_B - GPP_C0 + 1) -/* Group GPD */ +/* Group GPD */ #define GPD0 244 #define GPD1 245 #define GPD2 246 @@ -310,35 +311,38 @@ #define GPD9 253 #define GPD10 254 #define GPD11 255 +#define SLP_LAN_B 256 +#define SLP_SUS_B 257 +#define WAKE_B 258 +#define DRAM_RESET_B 259 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) /* Group AZA */ -#define HDA_BCLK 256 -#define HDA_RSTB 257 -#define HDA_SYNC 258 -#define HDA_SDO 259 -#define HDA_SDI_0 260 -#define HDA_SDI_1 261 -#define SSP1_SFRM 262 -#define SSP1_TXD 263 +#define HDA_BCLK 260 +#define HDA_RST_B 261 +#define HDA_SYNC 262 +#define HDA_SDO 263 +#define HDA_SDI0 264 +#define HDA_SDI1 265 +#define I2S1_SFRM 266 +#define I2S1_TXD 267 /* Group CPU */ -#define GPIO_RSVD_28 264 -#define GPIO_RSVD_29 265 -#define GPIO_RSVD_30 266 -#define GPIO_RSVD_31 267 -#define GPIO_RSVD_32 268 -#define GPIO_RSVD_33 269 -#define GPIO_RSVD_34 270 -#define GPIO_RSVD_35 271 -#define GPIO_RSVD_36 272 -#define GPIO_RSVD_37 273 -#define GPIO_RSVD_38 274 +#define HDACPU_SDI 268 +#define HDACPU_SDO 269 +#define HDACPU_SCLK 270 +#define PM_SYNC 271 +#define PECI_IO 272 +#define CPUPWRGD 273 +#define THRMTRIP_B 274 +#define PLTRST_CPU_B 275 +#define PM_DOWN 276 +#define TRIGGER_IN 277 +#define TRIGGER_OUT 278 -#define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1) +#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1) -#define TOTAL_PADS 275 +#define TOTAL_PADS 279 #define SD_PWR_EN_PIN GPP_A17 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index dde0a65a2a..9396c0bf2a 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -53,7 +53,7 @@ #define GPP_A21 21 #define GPP_A22 22 #define GPP_A23 23 -#define GPIO_RSVD_0 24 +#define ESPI_CLK_LOOPBK 24 /* Group B */ #define GPP_B0 25 @@ -80,10 +80,10 @@ #define GPP_B21 46 #define GPP_B22 47 #define GPP_B23 48 -#define GPIO_RSVD_1 49 -#define GPIO_RSVD_2 50 +#define GSPI0_CLK_LOOPBK 49 +#define GSPI1_CLK_LOOPBK 50 -#define NUM_GPIO_COM0_PADS (GPIO_RSVD_2 - GPP_A0 + 1) +#define NUM_GPIO_COM0_PADS (GSPI1_CLK_LOOPBK - GPP_A0 + 1) /* Group C */ #define GPP_C0 51 @@ -148,22 +148,22 @@ #define GPP_G7 106 /* AZA */ -#define GPIO_RSVD_3 107 -#define GPIO_RSVD_4 108 -#define GPIO_RSVD_5 109 -#define GPIO_RSVD_6 110 -#define GPIO_RSVD_7 111 -#define GPIO_RSVD_8 112 -#define GPIO_RSVD_9 113 -#define GPIO_RSVD_10 114 +#define HDA_BCLK 107 +#define HDA_RST_B 108 +#define HDA_SYNC 109 +#define HDA_SDO 110 +#define HDA_SDI0 111 +#define HDA_SDI1 112 +#define I2S1_SFRM 113 +#define I2S1_TXD 114 /* VGPIO_0 */ #define CNV_BTEN 115 #define CNV_GNEN 116 #define CNV_WFEN 117 #define CNV_WCEN 118 -#define CNV_BT_HOST_WAKEB 119 -#define vCNV_GNSS_HOST_WAKEB 120 +#define CNV_BT_HOST_WAKE_B 119 +#define vCNV_GNSS_HOST_WAKE_B 120 #define vSD3_CD_B 121 #define CNV_BT_IF_SELECT 122 #define vCNV_BT_UART_TXD 123 @@ -181,11 +181,11 @@ #define vUART0_TXD 135 #define vUART0_RXD 136 #define vUART0_CTS_B 137 -#define vUART0_RTSB 138 +#define vUART0_RTS_B 138 #define vISH_UART0_TXD 139 #define vISH_UART0_RXD 140 #define vISH_UART0_CTS_B 141 -#define vISH_UART0_RTSB 142 +#define vISH_UART0_RTS_B 142 #define vISH_UART1_TXD 143 #define vISH_UART1_RXD 144 #define vISH_UART1_CTS_B 145 @@ -296,41 +296,41 @@ #define GPP_F23 239 /* SPI */ -#define GPIO_RSVD_11 240 -#define GPIO_RSVD_12 241 -#define GPIO_RSVD_13 242 -#define GPIO_RSVD_14 243 -#define GPIO_RSVD_15 244 -#define GPIO_RSVD_16 245 -#define GPIO_RSVD_17 246 -#define GPIO_RSVD_18 247 -#define GPIO_RSVD_19 248 +#define SPI0_IO_2 240 +#define SPI0_IO_3 241 +#define SPI0_MOSI 242 +#define SPI0_MISO 243 +#define SPI0_CS2_B 244 +#define SPI0_CS0_B 245 +#define SPI0_CS1_B 246 +#define SPI0_CLK 247 +#define SPI0_CLK_LOOPBK 248 -#define NUM_GPIO_COM3_PADS (GPIO_RSVD_19 - GPP_K0 + 1) +#define NUM_GPIO_COM3_PADS (SPI0_CLK_LOOPBK - GPP_K0 + 1) /* CPU */ -#define GPIO_RSVD_20 249 -#define GPIO_RSVD_21 250 -#define GPIO_RSVD_22 251 -#define GPIO_RSVD_23 252 -#define GPIO_RSVD_24 253 -#define GPIO_RSVD_25 254 -#define GPIO_RSVD_26 255 -#define GPIO_RSVD_27 256 -#define GPIO_RSVD_28 257 -#define GPIO_RSVD_29 258 -#define GPIO_RSVD_30 259 +#define HDACPU_SDI 249 +#define HDACPU_SDO 250 +#define HDACPU_SCLK 251 +#define PM_SYNC 252 +#define PECI_IO 253 +#define CPUPWRGD 254 +#define THRMTRIP_B 255 +#define PLTRST_CPU_B 256 +#define PM_DOWN 257 +#define TRIGGER_IN 258 +#define TRIGGER_OUT 259 /* JTAG */ -#define GPIO_RSVD_31 260 -#define GPIO_RSVD_32 261 -#define GPIO_RSVD_33 262 -#define GPIO_RSVD_34 263 -#define GPIO_RSVD_35 264 -#define GPIO_RSVD_36 265 -#define GPIO_RSVD_37 266 -#define GPIO_RSVD_38 267 -#define GPIO_RSVD_39 268 +#define PCH_TDO 260 +#define PCH_JTAGX 261 +#define PROC_PRDY_B 262 +#define PROC_PREQ_B 263 +#define CPU_TRST_B 264 +#define PCH_TDI 265 +#define PCH_TMS 266 +#define PCH_TCK 267 +#define ITP_PMODE 268 /* Group I */ #define GPP_I0 269 @@ -348,9 +348,9 @@ #define GPP_I12 281 #define GPP_I13 282 #define GPP_I14 283 -#define GPIO_RSVD_40 284 -#define GPIO_RSVD_41 285 -#define GPIO_RSVD_42 286 +#define SYS_PWROK 284 +#define SYS_RESET_B 285 +#define CL_RST_B 286 /* Group J */ #define GPP_J0 287 @@ -368,7 +368,7 @@ #define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1) -/* Group GPD */ +/* Group GPD */ #define GPD0 299 #define GPD1 300 #define GPD2 301 @@ -381,10 +381,14 @@ #define GPD9 308 #define GPD10 309 #define GPD11 310 +#define SLP_LAN_B 311 +#define SLP_SUS_B 312 +#define WAKE_B 313 +#define DRAM_RESET_B 314 -#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) +#define NUM_GPIO_COM2_PADS (DRAM_RESET_B - GPD0 + 1) -#define TOTAL_PADS (GPD11 + 1) +#define TOTAL_PADS (DRAM_RESET_B + 1) #define COMM_0 0 #define COMM_1 1 diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 05d4025f25..1aa6036bcc 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -62,6 +62,14 @@ #define PCIE_10_IRQ 17 #define PCIE_11_IRQ 18 #define PCIE_12_IRQ 19 +#define PCIE_14_IRQ 16 +#define PCIE_15_IRQ 17 +#define PCIE_16_IRQ 18 +#define PCIE_17_IRQ 19 +#define PCIE_18_IRQ 16 +#define PCIE_19_IRQ 17 +#define PCIE_20_IRQ 18 +#define PCIE_21_IRQ 19 #define SATA_IRQ 16 diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 6eda85755a..e3a07843f4 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -3,7 +3,6 @@ #ifndef _SOC_CANNONLAKE_PCH_H_ #define _SOC_CANNONLAKE_PCH_H_ - #define PCH_H 1 #define PCH_LP 2 #define PCH_UNKNOWN_SERIES 0xFF diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 2c2db0301f..3576d80969 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26) #define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h index 4e513f0f3c..ae9aa6074b 100644 --- a/src/soc/intel/cannonlake/include/soc/romstage.h +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -7,8 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); -/* Provide a callback to allow mainboard to override the DRAM part number. */ -void mainboard_get_dram_part_num(const char **part_num, size_t *len); void systemagent_early_init(void); void romstage_pch_init(void); diff --git a/src/soc/intel/cannonlake/include/soc/sata.h b/src/soc/intel/cannonlake/include/soc/sata.h index 869e44ce23..60366be10e 100644 --- a/src/soc/intel/cannonlake/include/soc/sata.h +++ b/src/soc/intel/cannonlake/include/soc/sata.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_SATA_H_ #define _SOC_SATA_H_ diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index ce87b4ae54..66b3f8b07c 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_USB_H_ #define _SOC_USB_H_ diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 50af9ee360..b21c117df0 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,108 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info; @@ -207,8 +105,8 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index f793c19e5f..96213d110f 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -12,7 +12,7 @@ /* Host Firmware Status Register 2 */ union me_hfsts2 { - uint32_t raw; + uint32_t data; struct { uint32_t nftp_load_failure : 1; uint32_t icc_prog_status : 2; @@ -36,7 +36,7 @@ union me_hfsts2 { /* Host Firmware Status Register 4 */ union me_hfsts4 { - uint32_t raw; + uint32_t data; struct { uint32_t rsvd0 : 9; uint32_t enforcement_flow : 1; @@ -52,7 +52,7 @@ union me_hfsts4 { /* Host Firmware Status Register 5 */ union me_hfsts5 { - uint32_t raw; + uint32_t data; struct { uint32_t acm_active : 1; uint32_t valid : 1; @@ -71,7 +71,7 @@ union me_hfsts5 { /* Host Firmware Status Register 6 */ union me_hfsts6 { - uint32_t raw; + uint32_t data; struct { uint32_t force_boot_guard_acm : 1; uint32_t cpu_debug_disable : 1; @@ -107,24 +107,18 @@ void dump_me_status(void *unused) return; hfsts1.data = me_read_config32(PCI_ME_HFSTS1); - hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); hfsts3.data = me_read_config32(PCI_ME_HFSTS3); - hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); - hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); - hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); - printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", - hfsts1.data); - printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", - hfsts2.raw); - printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", - hfsts3.data); - printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", - hfsts4.raw); - printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", - hfsts5.raw); - printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", - hfsts6.raw); + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", hfsts1.fields.mfg_mode ? "YES" : "NO"); diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index d37ff5407a..1f7ea3c180 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -11,7 +11,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) + if (cse_request_global_reset()) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index cfb07a0497..b082eb60a5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -52,7 +52,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; @@ -74,7 +74,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) m_cfg->VmxEnable = CONFIG(ENABLE_VMX); #if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); #endif if (config->cpu_ratio_override) { @@ -157,6 +157,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Configure VT-d */ tconfig->VtdDisable = 0; + /* Set HECI1 PCI BAR address */ + m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS; + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/romstage/pch.c b/src/soc/intel/cannonlake/romstage/pch.c index c85bdd667f..f94d611abe 100644 --- a/src/soc/intel/cannonlake/romstage/pch.c +++ b/src/soc/intel/cannonlake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void romstage_pch_init(void) { - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index c56add7fb8..0bf0404ab9 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -23,11 +23,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -void __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - /* Default weak implementation, no need to override part number. */ -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -42,7 +37,8 @@ static void save_dimm_info(void) const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; const char *dram_part_num; - size_t dram_part_num_len; + size_t dram_part_num_len = 0; + bool part_num_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ memory_info_hob = fsp_find_extension_hob_by_guid( @@ -64,6 +60,13 @@ static void save_dimm_info(void) } memset(mem_info, 0, sizeof(*mem_info)); + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + part_num_overridden = true; + } + /* Describe the first N DIMMs in the system */ index = 0; dimm_max = ARRAY_SIZE(mem_info->dimm); @@ -79,13 +82,12 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; - dram_part_num_len = sizeof(src_dimm->ModulePartNum); - dram_part_num = (const char *) + if (!part_num_overridden) { + dram_part_num_len = + sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) &src_dimm->ModulePartNum[0]; - - /* Allow mainboard to override DRAM part number. */ - mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + } u8 memProfNum = memory_info_hob->MemoryProfile; diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index 7663b2f1c4..46d385256b 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -3,7 +3,7 @@ #include #include "chip.h" -int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) { config_t *config = config_of(dev); diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3aec51b216..05bd1f7730 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -19,7 +19,6 @@ #include #include "chip.h" - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index c4b4fd5364..330325f272 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -336,7 +336,6 @@ static const struct vr_lookup vr_config_icc[] = { VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2), }; - VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) { { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) }, }; @@ -465,7 +464,6 @@ static const struct vr_lookup vr_config_ll[] = { VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2), }; - VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) { { 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) }, { 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) }, diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 44c2392abc..ba0b2db32f 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -6,13 +6,13 @@ config SOC_INTEL_COMMON if SOC_INTEL_COMMON -comment "Intel SoC Common Code" +comment "Intel SoC Common Code for IP blocks" source "src/soc/intel/common/block/Kconfig" comment "Intel SoC Common PCH Code" source "src/soc/intel/common/pch/Kconfig" -comment "Intel SoC Common coreboot stages" +comment "Intel SoC Common coreboot stages and non-IP blocks" source "src/soc/intel/common/basecode/Kconfig" config SOC_INTEL_COMMON_RESET @@ -30,6 +30,20 @@ config ACPI_CONSOLE help Provide a mechanism for serial console based ACPI debug. +config PAVP + bool "Enable PAVP (Protected Audio-Video Path) support" + default y + help + Protected Audio-Video Path is an Intel technology used to enforce digital + rights protections on multimedia content. Streaming or other media playback + services may require it to be enabled for correct functioning. + + Users might disable PAVP if the concept of digital rights management (DRM) + offends them, or if they have concerns about the security of + the Management Engine, which is where this technology is implemented. + + Set this option to n to disable support. + config MMA bool "Enable MMA (Memory Margin Analysis) support for Intel Core" default n diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 68aea15671..1c93244573 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -1,11 +1,10 @@ config SOC_INTEL_COMMON_BASECODE bool help - Common coreboot stages for Intel platform + Common coreboot stages and non-IP block for Intel platform if SOC_INTEL_COMMON_BASECODE -comment "Intel platform Common coreboot stage files" source "src/soc/intel/common/basecode/*/Kconfig" source "src/soc/intel/common/basecode/*/*/Kconfig" diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 7eb5950e58..5951b30e11 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -122,12 +122,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/common/block/acpi/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/soc/intel/common/block/acpi/acpi/gfx.asl diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl similarity index 87% rename from src/soc/intel/tigerlake/acpi/gpio_op.asl rename to src/soc/intel/common/block/acpi/acpi/gpio_op.asl index f7332aa137..9fa3dc4a86 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_op.asl +++ b/src/soc/intel/common/block/acpi/acpi/gpio_op.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include /* * Get GPIO Value @@ -11,7 +12,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT) + Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT Return (Local0) } @@ -43,7 +44,7 @@ Method (STXS, 1, Serialized) { VAL0, 32 } - VAL0 = PAD_CFG0_TX_STATE | VAL0 + VAL0 |= PAD_CFG0_TX_STATE } /* @@ -57,7 +58,7 @@ Method (CTXS, 1, Serialized) { VAL0, 32 } - VAL0 = ~PAD_CFG0_TX_STATE & VAL0 + VAL0 &= ~PAD_CFG0_TX_STATE } /* @@ -97,9 +98,9 @@ Method (GTXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_TX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_TX_DISABLE | VAL0 + VAL0 |= PAD_CFG0_TX_DISABLE } } @@ -119,8 +120,8 @@ Method (GRXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_RX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_RX_DISABLE | VAL0 + VAL0 |= PAD_CFG0_RX_DISABLE } } diff --git a/src/soc/intel/common/block/acpi/acpi/ipu.asl b/src/soc/intel/common/block/acpi/acpi/ipu.asl index 2380964752..ba1d9af8ab 100644 --- a/src/soc/intel/common/block/acpi/acpi/ipu.asl +++ b/src/soc/intel/common/block/acpi/acpi/ipu.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* IPU3 input system - Device 05, Function 0 */ -Device (IMGU) +/* Imaging Unit - Device 05, Function 0 */ +Device (IPU0) { Name (_ADR, 0x00050000) Name (_DDN, "Imaging Unit") diff --git a/src/soc/intel/common/block/acpi/acpi/ish.asl b/src/soc/intel/common/block/acpi/acpi/ish.asl new file mode 100644 index 0000000000..efdf95e3b3 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/ish.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +/* Calculate _ADR for Intel Integrated Sensor Hub Controller */ +#define ISH_ACPI_DEVICE (PCH_DEV_SLOT_ISH << 16 | 0x0000) + +Device (ISHB) +{ + Name (_ADR, ISH_ACPI_DEVICE) + Name (_DDN, "Integrated Sensor Hub Controller") +} diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/common/block/acpi/acpi/pch_glan.asl similarity index 91% rename from src/soc/intel/tigerlake/acpi/pch_glan.asl rename to src/soc/intel/common/block/acpi/acpi/pch_glan.asl index 97faf7ac80..6bf733d739 100644 --- a/src/soc/intel/tigerlake/acpi/pch_glan.asl +++ b/src/soc/intel/common/block/acpi/acpi/pch_glan.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Intel Gigabit Ethernet Controller 0:1f.6 */ +#include Device (GLAN) { diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/common/block/acpi/acpi/platform.asl similarity index 100% rename from src/soc/intel/jasperlake/acpi/platform.asl rename to src/soc/intel/common/block/acpi/acpi/platform.asl diff --git a/src/soc/intel/jasperlake/acpi/smbus.asl b/src/soc/intel/common/block/acpi/acpi/smbus.asl similarity index 100% rename from src/soc/intel/jasperlake/acpi/smbus.asl rename to src/soc/intel/common/block/acpi/acpi/smbus.asl diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 09f2c47c94..f52d242357 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -1,15 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include const struct soc_intel_common_config *chip_get_common_soc_structure(void) { - const struct soc_intel_common_config *soc_config; - const config_t *config; - - config = config_of_soc(); - soc_config = &config->common_soc_config; - - return soc_config; + return &((config_t *)config_of_soc())->common_soc_config; } diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b2401e..995a95680c 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,6 +51,28 @@ config INTEL_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_CAR_NEM_ENHANCED_V1 + bool + select INTEL_CAR_NEM_ENHANCED + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. + +config USE_CAR_NEM_ENHANCED_V2 + bool + select INTEL_CAR_NEM_ENHANCED + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + TGL platform. + +config COS_MAPPED_TO_MSB + bool + depends on INTEL_CAR_NEM_ENHANCED + help + On TGL and JSL platform the class of service configuration + is mapped to MSB of MSR IA32_PQR_ASSOC. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n @@ -66,3 +88,13 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. + +config INTEL_TME + bool "Total Memory Encryption (TME)/Multi-key TME (MKTME)" + default n + help + Enable Total Memory Encryption (TME)/Multi-key TME (MKTME). The spec is + available at "https://software.intel.com/sites/default/files/managed/a5 + /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, + it would get enabled. If CPU supports MKTME, this same config option + enables MKTME. diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 69ed174968..5af1fc65c1 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -351,54 +351,96 @@ find_llc_subleaf: jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE - * for 4/8/16 way of LLC - */ + * Calculate the total LLC size + * (Line_Size + 1) * (Sets + 1) * (Partitions + 1) * (Ways + 1) + * (EBX[11:0] + 1) * (ECX + 1) * (EBX[21:12] + 1) * EBX[31:22] + 1) + */ + + mov %ebx, %eax + and $0xFFF, %eax + inc %eax + inc %ecx + mul %ecx + mov %eax, %ecx + mov %ebx, %eax + shr $12, %eax + and $0x3FF, %eax + inc %eax + mul %ecx shr $22, %ebx inc %ebx - /* Calculate n-way associativity of LLC */ - mov %bl, %cl + mov %ebx, %edx + mul %ebx /* eax now holds total LLC size */ /* - * Maximizing RO cacheability while locking in the CAR to a - * single way since that particular way won't be victim candidate - * for evictions. - * This has been done after programming LLC_WAY_MASK_1 MSR - * with desired LLC way as mentioned below. - * - * Hence create Code and Data Size as per request - * Code Size (RO) : Up to 16M - * Data Size (RW) : Up to 256K + * The number of the ways that we want to protect from eviction + * can be calculated as RW data stack size / way size where way + * size is Total LLC size / Total number of LLC ways. */ - movl $0x01, %eax + div %ebx /* way size */ + mov %eax, %ecx + /* - * LLC Ways -> LLC_WAY_MASK_1: - * 4: 0x000E - * 8: 0x00FE - * 12: 0x0FFE - * 16: 0xFFFE - * - * These MSRs contain one bit per each way of LLC + * Check if way size if bigger than the cache ram size. + * Then we need to allocate just one way for non-eviction + * of RW data. + */ + movl $0x01, %eax + cmp $CONFIG_DCACHE_RAM_SIZE, %ecx + jnc set_eviction_mask + + /* + * RW data size / way size is equal to number of + * ways to be configured for non-eviction + */ + mov $CONFIG_DCACHE_RAM_SIZE, %eax + div %ecx + mov %eax, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + +set_eviction_mask: + mov %ebx, %ecx /* back up the number of ways */ + mov %eax, %ebx /* back up the non-eviction mask*/ + /* + * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ - shl %cl, %eax - subl $0x02, %eax + mov $0x1, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ecx + mov %ebx, %eax + + xor $~0, %eax /* invert 32 bits */ + and %ecx, %eax +#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx +#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) + movl $IA32_CR_SF_QOS_MASK_1, %ecx +#endif + xorl %edx, %edx + wrmsr + + /* + * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * This MSR contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + mov %ebx, %eax +#if CONFIG(USE_CAR_NEM_ENHANCED_V1) + movl $IA32_L3_MASK_2, %ecx +#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) + movl $IA32_CR_SF_QOS_MASK_2, %ecx +#endif xorl %edx, %edx wrmsr /* - * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 - * - * For SKL SOC, data size remains 256K consistently. - * Hence, creating 1-way associative cache for Data - */ - mov $IA32_L3_MASK_2, %ecx - mov $0x01, %eax - xorl %edx, %edx - wrmsr - /* - * Set IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC * * Possible values: * 0: Default value, no way mask should be applied @@ -407,8 +449,13 @@ find_llc_subleaf: * 3: Shouldn't be use in NEM Mode */ movl $IA32_PQR_ASSOC, %ecx - movl $0x02, %eax + xorl %eax, %eax xorl %edx, %edx +#if CONFIG(COS_MAPPED_TO_MSB) + movl $0x02, %edx +#else + movl $0x02, %eax +#endif wrmsr movl $CONFIG_DCACHE_RAM_BASE, %edi @@ -418,13 +465,17 @@ find_llc_subleaf: cld rep stosl /* - * Set IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC * At this stage we apply LLC_WAY_MASK_1 to the cache. - * i.e. way 0 is protected from eviction. */ movl $IA32_PQR_ASSOC, %ecx - movl $0x01, %eax + xorl %eax, %eax xorl %edx, %edx +#if CONFIG(COS_MAPPED_TO_MSB) + movl $0x01, %edx +#else + movl $0x01, %eax +#endif wrmsr post_code(0x27) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0cebe329c0..cbf9b1b9dd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include /* * Set PERF_CTL MSR (0x199) P_Req with @@ -340,16 +340,14 @@ void cpu_lt_lock_memory(void *unused) msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); } -int get_prmrr_size(void) +int get_valid_prmrr_size(void) { msr_t msr; int i; int valid_size; - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED)) { - printk(BIOS_DEBUG, "PRMRR disabled by config.\n"); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) return 0; - } msr = rdmsr(MSR_PRMRR_VALID_CONFIG); if (!msr.lo) { @@ -369,10 +367,11 @@ int get_prmrr_size(void) valid_size = 0; } - /* die if we could not find a valid size within the limit */ - if (!valid_size) - die("Unsupported PRMRR size limit %i MiB, check your config!\n", + if (!valid_size) { + printk(BIOS_WARNING, "Unsupported PRMRR size of %i MiB, check your config!\n", CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE); + return 0; + } printk(BIOS_DEBUG, "PRMRR size set to %i MiB\n", valid_size); diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 96b9b9fcc8..2e3401d370 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -76,7 +76,10 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0}, + { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, { 0, 0 }, }; @@ -126,19 +129,32 @@ void get_microcode_info(const void **microcode, int *parallel) *parallel = 1; } -static void init_cpus(void *unused) +/* + * Perform BSP and AP initialization + * This function can be called in below cases: + * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude + * this call if user has selected USE_INTEL_FSP_MP_INIT). + * 2. coreboot would like to take APs control back after FSP-S has done with MP + * initialization based on user select USE_INTEL_FSP_MP_INIT. + */ +void init_cpus(void) { struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); + if (dev && dev->link_list) + soc_init_cpus(dev->link_list); +} + +static void coreboot_init_cpus(void *unused) +{ if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); - if (dev && dev->link_list) - soc_init_cpus(dev->link_list); + init_cpus(); } static void wrapper_x86_setup_mtrrs(void *unused) @@ -149,9 +165,6 @@ static void wrapper_x86_setup_mtrrs(void *unused) /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { - if (CONFIG(USE_INTEL_FSP_MP_INIT)) - return; - if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); @@ -159,6 +172,6 @@ static void post_cpus_init(void *unused) } /* Do CPU MP Init before FSP Silicon Init */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, init_cpus, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL); BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 9f09d89656..1cb7d35fb0 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -19,3 +19,21 @@ config SOC_INTEL_CSE_LITE_SKU depends on CHROMEOS help Enables CSE Lite SKU + +config SOC_INTEL_CSE_FMAP_NAME + string "Name of CSE Region in FMAP" + default "SI_ME" + help + Name of CSE region in FMAP + +config SOC_INTEL_CSE_RW_CBFS_NAME + string "CBFS entry name for CSE RW blob" + default "me_rw" + help + CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 30ff66bf6f..11cc3c20d1 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -3,3 +3,12 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c + +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") +CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_ME_RW) +$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) +$(CSE_LITE_ME_RW)-type := raw +endif diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index fecc71ee72..ef6db3da4f 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -616,9 +616,10 @@ static bool cse_is_global_reset_allowed(void) } /* - * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/CSE_RESET_ONLY. + * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. + * Returns 0 on failure and 1 on success. */ -int cse_request_global_reset(enum rst_req_type rst_type) +static int cse_request_reset(enum rst_req_type rst_type) { int status; struct mkhi_hdr reply; @@ -644,7 +645,7 @@ int cse_request_global_reset(enum rst_req_type rst_type) return 0; } - if (!cse_is_global_reset_allowed()) { + if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); return 0; } @@ -663,6 +664,11 @@ int cse_request_global_reset(enum rst_req_type rst_type) return status; } +int cse_request_global_reset(void) +{ + return cse_request_reset(GLOBAL_RESET); +} + static bool cse_is_hmrfpo_enable_allowed(void) { /* @@ -893,6 +899,14 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_CSE1, PCI_DEVICE_ID_INTEL_JSP_CSE2, PCI_DEVICE_ID_INTEL_JSP_CSE3, + PCI_DEVICE_ID_INTEL_ADP_P_CSE0, + PCI_DEVICE_ID_INTEL_ADP_P_CSE1, + PCI_DEVICE_ID_INTEL_ADP_P_CSE2, + PCI_DEVICE_ID_INTEL_ADP_P_CSE3, + PCI_DEVICE_ID_INTEL_ADP_S_CSE0, + PCI_DEVICE_ID_INTEL_ADP_S_CSE1, + PCI_DEVICE_ID_INTEL_ADP_S_CSE2, + PCI_DEVICE_ID_INTEL_ADP_S_CSE3, 0, }; diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 8e43e35c47..c9e4e1f470 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,15 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include #include -#include +#include +#include +#include +#include +#include #include #include #include #include +#include + +/* CSE RW version size reserved in the CSE CBFS RW binary */ +#define CSE_RW_VERSION_SZ 16 /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") +/* CSE RW boot partition signature */ +#define CSE_RW_SIGNATURE 0x000055aa + +/* CSE RW boot partition signature size */ +#define CSE_RW_SIGN_SIZE sizeof(uint32_t) + /* * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. @@ -22,10 +36,10 @@ /* CSE Lite SKU's valid bootable partition identifiers */ enum boot_partition_id { - /* RO(BP1) contains recovery/minimal boot FW */ + /* RO(BP1) contains recovery/minimal boot firmware */ RO = 0, - /* RW(BP2) contains fully functional CSE Firmware */ + /* RW(BP2) contains fully functional CSE firmware */ RW = 1 }; @@ -70,6 +84,11 @@ enum bp_status { /* This value is returned when a partition is not present per initial image layout */ BP_STATUS_PARTITION_NOT_PRESENT = 2, + /* + * This value is returned when unexpected issues are detected in CSE Data area + * and CSE TCB-SVN downgrade scenario. + */ + BP_STATUS_DATA_FAILURE = 3, }; /* @@ -138,16 +157,26 @@ struct get_bp_info_rsp { struct cse_bp_info bp_info; } __packed; +static void cse_log_status_registers(void) +{ + printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " + "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), + me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); +} + static void cse_trigger_recovery(uint8_t rec_sub_code) { + /* Log CSE Firmware Status Registers to help debugging */ + cse_log_status_registers(); if (CONFIG(VBOOT)) { - struct vb2_context *ctx; - ctx = vboot_get_context(); + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + goto failure; vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, rec_sub_code); vboot_save_data(ctx); vboot_reboot(); } - +failure: die("cse_lite: Failed to trigger recovery mode(recovery subcode:%d)\n", rec_sub_code); } @@ -162,6 +191,49 @@ static const struct cse_bp_entry *cse_get_bp_entry(enum boot_partition_id bp, return &cse_bp_info->bp_entries[bp]; } +static void cse_get_bp_entry_range(const struct cse_bp_info *cse_bp_info, + enum boot_partition_id bp, uint32_t *start_offset, uint32_t *end_offset) +{ + const struct cse_bp_entry *cse_bp; + + cse_bp = cse_get_bp_entry(bp, cse_bp_info); + + if (start_offset) + *start_offset = cse_bp->start_offset; + + if (end_offset) + *end_offset = cse_bp->end_offset; + +} + +static const struct fw_version *cse_get_bp_entry_version(enum boot_partition_id bp, + const struct cse_bp_info *bp_info) +{ + const struct cse_bp_entry *cse_bp; + + cse_bp = cse_get_bp_entry(bp, bp_info); + return &cse_bp->fw_ver; +} + +static const struct fw_version *cse_get_rw_version(const struct cse_bp_info *cse_bp_info) +{ + return cse_get_bp_entry_version(RW, cse_bp_info); +} + +static bool cse_is_rw_bp_status_valid(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *rw_bp; + + rw_bp = cse_get_bp_entry(RW, cse_bp_info); + + if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || + rw_bp->status == BP_STATUS_GENERAL_FAILURE) { + printk(BIOS_ERR, "cse_lite: RW BP (status:%u) is not valid\n", rw_bp->status); + return false; + } + return true; +} + static void cse_print_boot_partition_info(const struct cse_bp_info *cse_bp_info) { const struct cse_bp_entry *cse_bp; @@ -196,6 +268,9 @@ static void cse_print_boot_partition_info(const struct cse_bp_info *cse_bp_info) * - When CSE boots from RW partition (COM: Normal and CWS: Normal) * - When CSE boots from RO partition (COM: Soft Temp Disable and CWS: Normal) * - After HMRFPO_ENABLE command is issued to CSE (COM: SECOVER_MEI_MSG and CWS: Normal) + * The prerequisite check should be handled in cse_get_bp_info() and + * cse_set_next_boot_partition() since the CSE's current operation mode is changed between these + * cmd handler calls. */ static bool cse_is_bp_cmd_info_possible(void) { @@ -294,40 +369,348 @@ static bool cse_set_next_boot_partition(enum boot_partition_id bp) return true; } -static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info) +__weak void cse_board_reset(void) { - if (cse_get_current_bp(cse_bp_info) == RW) - return true; + /* Default weak implementation, does nothing. */ +} - if (!cse_set_next_boot_partition(RW)) +/* Set the CSE's next boot partition and issues system reset */ +static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp) +{ + if (!cse_set_next_boot_partition(bp)) return false; + /* Allow the board to perform a reset for CSE RO<->RW jump */ + cse_board_reset(); + + /* If board does not perform the reset, then perform global_reset */ do_global_reset(); - die("cse_lite: Failed to reset system\n"); + die("cse_lite: Failed to reset the system\n"); /* Control never reaches here */ return false; } -static bool cse_is_rw_status_valid(const struct cse_bp_info *cse_bp_info) +static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info) { - const struct cse_bp_entry *rw_bp; + if (cse_get_current_bp(cse_bp_info) == RW) + return true; - /* RW(BP2) alone represents RW partition */ - rw_bp = cse_get_bp_entry(RW, cse_bp_info); + return cse_set_and_boot_from_next_bp(RW); +} - if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || - rw_bp->status == BP_STATUS_GENERAL_FAILURE) { - printk(BIOS_ERR, "cse_lite: RW BP (status:%u) is not valid\n", rw_bp->status); +static bool cse_boot_to_ro(const struct cse_bp_info *cse_bp_info) +{ + if (cse_get_current_bp(cse_bp_info) == RO) + return true; + + return cse_set_and_boot_from_next_bp(RO); +} + +static bool cse_get_rw_rdev(struct region_device *rdev) +{ + if (fmap_locate_area_as_rdev_rw(CONFIG_SOC_INTEL_CSE_FMAP_NAME, rdev) < 0) { + printk(BIOS_ERR, "cse_lite: Failed to locate %s in FMAP\n", + CONFIG_SOC_INTEL_CSE_FMAP_NAME); + return false; + } + + return true; +} + +static bool cse_get_cbfs_rdev(struct region_device *source_rdev) +{ + struct cbfsf file_desc; + + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + return false; + + cbfs_file_data(source_rdev, &file_desc); + return true; +} + +static bool cse_is_rw_bp_sign_valid(const struct region_device *target_rdev) +{ + uint32_t cse_bp_sign; + + if (rdev_readat(target_rdev, &cse_bp_sign, 0, CSE_RW_SIGN_SIZE) != CSE_RW_SIGN_SIZE) { + printk(BIOS_ERR, "cse_lite: Failed to read RW boot partition signature\n"); + return false; + } + + return cse_bp_sign == CSE_RW_SIGNATURE; +} + +static bool cse_get_target_rdev(const struct cse_bp_info *cse_bp_info, + struct region_device *target_rdev) +{ + struct region_device cse_region_rdev; + size_t size; + uint32_t start_offset; + uint32_t end_offset; + + if (!cse_get_rw_rdev(&cse_region_rdev)) + return false; + + cse_get_bp_entry_range(cse_bp_info, RW, &start_offset, &end_offset); + size = end_offset + 1 - start_offset; + + if (rdev_chain(target_rdev, &cse_region_rdev, start_offset, size)) + return false; + + printk(BIOS_DEBUG, "cse_lite: CSE RW partition: offset = 0x%x, size = 0x%x\n", + (uint32_t)start_offset, (uint32_t) size); + + return true; +} + +static bool cse_data_clear_request(const struct cse_bp_info *cse_bp_info) +{ + struct data_clr_request { + struct mkhi_hdr hdr; + uint8_t reserved[4]; + } __packed; + + struct data_clr_request data_clr_rq = { + .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, + .hdr.command = MKHI_BUP_COMMON_DATA_CLEAR, + .reserved = {0}, + }; + + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_soft_temp_disable() || + cse_get_current_bp(cse_bp_info) != RO) { + printk(BIOS_ERR, "cse_lite: CSE doesn't meet DATA CLEAR cmd prerequisites\n"); + return false; + } + + printk(BIOS_DEBUG, "cse_lite: Sending DATA CLEAR HECI command\n"); + + struct mkhi_hdr data_clr_rsp; + size_t data_clr_rsp_sz = sizeof(data_clr_rsp); + + if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, + &data_clr_rsp_sz)) { + return false; + } + + if (data_clr_rsp.result) { + printk(BIOS_ERR, "cse_lite: CSE DATA CLEAR command response failed: %d\n", + data_clr_rsp.result); + return false; + } + + return true; +} + +static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, + void *cse_cbfs_rw_ver) +{ + + if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) + != sizeof(struct fw_version)) { + printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); return false; } return true; } -static bool cse_is_rw_info_valid(struct cse_bp_info *cse_bp_info) +/* + * Compare versions of CSE CBFS RW and CSE RW partition + * If ver_cmp_status = 0, no update is required + * If ver_cmp_status < 0, coreboot downgrades CSE RW region + * If ver_cmp_status > 0, coreboot upgrades CSE RW region + */ +static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev) { - return cse_is_rw_status_valid(cse_bp_info); + struct fw_version cse_cbfs_rw_ver; + const struct fw_version *cse_rw_ver; + + if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) + return false; + + printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + cse_cbfs_rw_ver.major, + cse_cbfs_rw_ver.minor, + cse_cbfs_rw_ver.hotfix, + cse_cbfs_rw_ver.build); + + cse_rw_ver = cse_get_rw_version(cse_bp_info); + + if (cse_cbfs_rw_ver.major != cse_rw_ver->major) + return cse_cbfs_rw_ver.major - cse_rw_ver->major; + else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) + return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; + else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) + return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + else + return cse_cbfs_rw_ver.build - cse_rw_ver->build; +} + +/* Check if CSE RW data partition is valid or not */ +static bool cse_is_rw_dp_valid(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *rw_bp; + + rw_bp = cse_get_bp_entry(RW, cse_bp_info); + return rw_bp->status != BP_STATUS_DATA_FAILURE; +} + +/* + * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE + * otherwise false if any operation fails. + */ +static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info) +{ + /* + * If RW partition status indicates BP_STATUS_DATA_FAILURE, + * - Send DATA CLEAR HECI command to CSE + * - Send SET BOOT PARTITION INFO(RW) command to set CSE's next partition + * - Issue GLOBAL RESET HECI command. + */ + if (cse_is_rw_dp_valid(cse_bp_info)) + return true; + + if (!cse_data_clear_request(cse_bp_info)) + return false; + + return cse_boot_to_rw(cse_bp_info); +} + +static bool cse_erase_rw_region(const struct region_device *target_rdev) +{ + if (rdev_eraseat(target_rdev, 0, region_device_sz(target_rdev)) < 0) { + printk(BIOS_ERR, "cse_lite: CSE RW partition could not be erased\n"); + return false; + } + return true; +} + +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, + size_t size) +{ + if (rdev_writeat(target_rdev, buf, offset, size) < 0) { + printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); + return false; + } + + return true; +} + +static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev) +{ + return !cse_check_version_mismatch(cse_bp_info, source_rdev); +} + +static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev) +{ + return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; +} + +static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev, struct region_device *target_rdev) +{ + return (!cse_is_rw_bp_sign_valid(target_rdev) || + !cse_is_rw_version_latest(cse_bp_info, source_rdev)); +} + +static bool cse_write_rw_region(const struct region_device *target_rdev, + const struct region_device *source_rdev) +{ + void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, + region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); + + /* Points to CSE CBFS RW image after boot partition signature */ + uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; + + /* Size of CSE CBFS RW image without boot partition signature */ + uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - + (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + + /* Update except CSE RW signature */ + if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, + cse_cbfs_rw_wo_sign_sz)) + goto exit_rw_update; + + /* Update CSE RW signature to indicate update is complete */ + if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) + goto exit_rw_update; + + rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); + return true; + +exit_rw_update: + rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); + return false; +} + +static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev, struct region_device *target_rdev) +{ + if (!cse_erase_rw_region(target_rdev)) + return false; + + if (!cse_write_rw_region(target_rdev, source_rdev)) + return false; + + printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); + return true; +} + +static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev) +{ + /* + * To set CSE's operation mode to HMRFPO mode: + * 1. Ensure CSE to boot from RO(BP1) + * 2. Send HMRFPO_ENABLE command to CSE + */ + if (!cse_boot_to_ro(cse_bp_info)) + return false; + + if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + !cse_data_clear_request(cse_bp_info)) { + printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); + return false; + } + + return cse_hmrfpo_enable(); +} + +static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev, struct region_device *target_rdev) +{ + if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) + return CSE_LITE_SKU_COMMUNICATION_ERROR; + + if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) + return CSE_LITE_SKU_FW_UPDATE_ERROR; + + return 0; +} + +static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, + const struct region_device *source_rdev) +{ + struct region_device target_rdev; + + if (!cse_get_target_rdev(cse_bp_info, &target_rdev)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE RW Partition\n"); + return CSE_LITE_SKU_RW_ACCESS_ERROR; + } + + if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); + return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + } + + if (!cse_is_rw_bp_status_valid(cse_bp_info)) + return CSE_LITE_SKU_RW_JUMP_ERROR; + + return 0; } void cse_fw_sync(void *unused) @@ -350,9 +733,16 @@ void cse_fw_sync(void *unused) cse_trigger_recovery(CSE_LITE_SKU_COMMUNICATION_ERROR); } - if (!cse_is_rw_info_valid(&cse_bp_info.bp_info)) { - printk(BIOS_ERR, "cse_lite: CSE RW partition is not valid\n"); - cse_trigger_recovery(CSE_LITE_SKU_RW_JUMP_ERROR); + if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) + cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); + + /* If RW blob is present in CBFS, then trigger CSE firmware update */ + uint8_t rv; + struct region_device source_rdev; + if (cse_get_cbfs_rdev(&source_rdev)) { + rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); + if (rv) + cse_trigger_recovery(rv); } if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { @@ -361,8 +751,12 @@ void cse_fw_sync(void *unused) } } -#if CONFIG(SOC_INTEL_TIGERLAKE) -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL); +#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) +/* + * This needs to happen after the MRC cache write to avoid a 2nd + * memory training sequence. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); #else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); #endif diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 2360d7d07f..776a22b553 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -24,6 +24,15 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, PCI_DEVICE_ID_INTEL_JSP_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_P_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, 0, }; diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index f3969939c9..58afd744f2 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -5,8 +5,11 @@ #include static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CML_DTT, PCI_DEVICE_ID_INTEL_TGL_DTT, PCI_DEVICE_ID_INTEL_JSL_DTT, + PCI_DEVICE_ID_INTEL_ADL_DTT, + 0 }; static struct device_operations dptf_dev_ops = { diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 655d11393a..4190253dd1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -101,7 +101,6 @@ void fast_spi_set_lock_enable(void) { fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE); - fast_spi_read_post_write(SPIBAR_BIOS_CONTROL); } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index a330b55552..da9949088e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -154,7 +154,6 @@ static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr, return xfer_len; } - static int fast_spi_flash_erase(const struct spi_flash *flash, uint32_t offset, size_t len) { diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index bdbc323c12..753d8e0a7e 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -4,42 +4,40 @@ config SOC_INTEL_COMMON_BLOCK_GPIO help Intel Processor common GPIO support +if SOC_INTEL_COMMON_BLOCK_GPIO + # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted # to appear as Active Low to IOAPIC and vice versa config SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure Pad Tolerance as 1.8V or 3.3V config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to configure IOSSTATE and IOSTERM config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Used to provide support for legacy macros config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n # Indicate if SoC supports dual-routing of GPIOs (to different paths like SCI, # NMI, SMI, IOAPIC). This is required to support IRQ and wake on the same pad. config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - depends on SOC_INTEL_COMMON_BLOCK_GPIO bool default n + +endif diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index ee91aa6550..d6958b111f 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -78,7 +78,7 @@ static inline size_t gpio_group_index(const struct pad_community *comm, } printk(BIOS_ERR, "%s: pad %d is not found in community %s!\n", __func__, relative_pad, comm->name); - assert(0); + BUG(); return i; } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 7b01ee63bc..23cf84756d 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -282,6 +282,21 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_EHL_GT2_3, PCI_DEVICE_ID_INTEL_JSL_GT1, PCI_DEVICE_ID_INTEL_JSL_GT2, + PCI_DEVICE_ID_INTEL_JSL_GT3, + PCI_DEVICE_ID_INTEL_JSL_GT4, + PCI_DEVICE_ID_INTEL_ADL_GT0, + PCI_DEVICE_ID_INTEL_ADL_GT1, + PCI_DEVICE_ID_INTEL_ADL_GT1_1, + PCI_DEVICE_ID_INTEL_ADL_GT1_2, + PCI_DEVICE_ID_INTEL_ADL_GT1_3, + PCI_DEVICE_ID_INTEL_ADL_GT1_4, + PCI_DEVICE_ID_INTEL_ADL_GT1_5, + PCI_DEVICE_ID_INTEL_ADL_GT1_6, + PCI_DEVICE_ID_INTEL_ADL_GT1_7, + PCI_DEVICE_ID_INTEL_ADL_GT1_8, + PCI_DEVICE_ID_INTEL_ADL_GT1_9, + PCI_DEVICE_ID_INTEL_ADL_P_GT2, + PCI_DEVICE_ID_INTEL_ADL_S_GT1, 0, }; diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e52c..836371372a 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -257,6 +258,17 @@ static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) return gspi_base[gspi_bus]; } +/* + * PCI resource allocation will likely change the base address of the mapped + * I/O registers. Clearing the cached value after the allocation step will + * cause it to be recomputed by gspi_calc_base_addr() on next access. + */ +static void gspi_clear_cached_base(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL); + /* Parameters for GSPI controller operation. */ struct gspi_ctrlr_params { uintptr_t mmio_base; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index c84415fb60..e4bcf9913d 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -71,6 +71,16 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_BSW_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_P_AUDIO, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, + PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f7c241da78..5aa7729613 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -166,7 +166,7 @@ static struct device_operations i2c_dev_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, + .scan_bus = scan_static_bus, .ops_i2c_bus = &dw_i2c_bus_ops, .ops_pci = &pci_dev_ops_pci, .init = dw_i2c_device_init, @@ -250,6 +250,18 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_I2C3, PCI_DEVICE_ID_INTEL_JSP_I2C4, PCI_DEVICE_ID_INTEL_JSP_I2C5, + PCI_DEVICE_ID_INTEL_ADP_P_I2C0, + PCI_DEVICE_ID_INTEL_ADP_P_I2C1, + PCI_DEVICE_ID_INTEL_ADP_P_I2C2, + PCI_DEVICE_ID_INTEL_ADP_P_I2C3, + PCI_DEVICE_ID_INTEL_ADP_P_I2C4, + PCI_DEVICE_ID_INTEL_ADP_P_I2C5, + PCI_DEVICE_ID_INTEL_ADP_S_I2C0, + PCI_DEVICE_ID_INTEL_ADP_S_I2C1, + PCI_DEVICE_ID_INTEL_ADP_S_I2C2, + PCI_DEVICE_ID_INTEL_ADP_S_I2C3, + PCI_DEVICE_ID_INTEL_ADP_S_I2C4, + PCI_DEVICE_ID_INTEL_ADP_S_I2C5, 0, }; diff --git a/src/soc/intel/common/block/imc/Kconfig b/src/soc/intel/common/block/imc/Kconfig deleted file mode 100644 index 490b80ebeb..0000000000 --- a/src/soc/intel/common/block/imc/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_IMC - bool - depends on MMCONF_SUPPORT - default n - help - Driver for communication with Integrated Memory Controller that is found on - some Xeon server processors. diff --git a/src/soc/intel/common/block/imc/Makefile.inc b/src/soc/intel/common/block/imc/Makefile.inc deleted file mode 100644 index a6bc985eb2..0000000000 --- a/src/soc/intel/common/block/imc/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IMC),y) - -bootblock-y += imc.c -romstage-y += imc.c -verstage-y += imc.c -postcar-y += imc.c -ramstage-y += imc.c - -endif diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c deleted file mode 100644 index 8c49dcda8e..0000000000 --- a/src/soc/intel/common/block/imc/imc.c +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Please note: the driver uses MMIO PCIe register access. IO based access will - * not work. - */ - -#include -#include -#include -#include -#include -#include - -#define IMC_SMBUS_TIMEOUT_MS 100 -#define IMC_SMBCNTL_DTI_TSOD 0x3 -#define IMC_SMBCNTL_DTI_EEPROM 0xa -#define IMC_SMBCNTL_DTI_WP_EEPROM 0x6 - -#define SMBSTAT(i) (0x180 + 0x10 * i) -#define SMBCMD(i) (0x184 + 0x10 * i) -#define SMBCNTL(i) (0x188 + 0x10 * i) - -#define SMBSTAT_RDO (1u << 31) /* Read Data Valid */ -#define SMBSTAT_WOD (1u << 30) /* Write Operation Done */ -#define SMBSTAT_SBE (1u << 29) /* SMBus Error */ -#define SMBSTAT_SMB_BUSY (1u << 28) /* SMBus Busy State */ - -#define SMBCMD_TRIGGER (1u << 31) /* CMD Trigger */ -#define SMBCMD_PNTR_SEL (1u << 30) /* HW polls TSOD with pointer */ -#define SMBCMD_WORD_ACCESS (1u << 29) /* word (vs byte) access */ -#define SMBCMD_TYPE_MASK (3u << 27) /* Mask for access type */ -#define SMBCMD_TYPE_READ (0u << 27) /* Read */ -#define SMBCMD_TYPE_WRITE (1u << 27) /* Write */ -#define SMBCMD_TYPE_PNTR_WRITE (3u << 27) /* Write to pointer */ -#define SMBCMD_SA_MASK (7u << 24) /* Slave Address high bits */ -#define SMBCMD_SA_SHIFT 24 -#define SMBCMD_BA_MASK 0xff0000 /* Bus Txn address */ -#define SMBCMD_BA_SHIFT 16 -#define SMBCMD_WDATA_MASK 0xffff /* data to write */ - -#define SMBCNTL_DTI_MASK 0xf0000000 /* Slave Address low bits */ -#define SMBCNTL_DTI_SHIFT 28 /* Slave Address low bits */ -#define SMBCNTL_CKOVRD (1u << 27) /* # Clock Override */ -#define SMBCNTL_DIS_WRT (1u << 26) /* Disable Write (sadly) */ -#define SMBCNTL_SOFT_RST (1u << 10) /* Soft Reset */ -#define SMBCNTL_TSOD_POLL_EN (1u << 8) /* TSOD Polling Enable */ - -static bool poll_ready(pci_devfn_t dev, enum memory_controller_id mcid, uint32_t *status) -{ - struct stopwatch sw; - - stopwatch_init_msecs_expire(&sw, IMC_SMBUS_TIMEOUT_MS); - - do { - *status = pci_mmio_read_config32(dev, SMBSTAT(mcid)); - if (!(*status & SMBSTAT_SMB_BUSY)) - break; - } while (!stopwatch_expired(&sw)); - - return (!(*status & SMBSTAT_SMB_BUSY)); -} - -static bool claim_controller(pci_devfn_t dev, enum memory_controller_id mcid) -{ - uint32_t cntl, status; - - cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntl &= ~SMBCNTL_TSOD_POLL_EN; - cntl &= ~SMBCNTL_DIS_WRT; - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); - - return poll_ready(dev, mcid, &status); -} - - -static void release_controller(pci_devfn_t dev, enum memory_controller_id mcid) -{ - uint32_t cntl, status; - - cntl = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntl |= SMBCNTL_TSOD_POLL_EN; - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntl); - - poll_ready(dev, mcid, &status); -} - -int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr, - enum device_type_id dti, enum access_width width, - enum memory_controller_id mcid, enum smbus_command cmd, void *data) -{ - int ret = -1; - uint32_t cmdbits = 0, stat = 0, cntlbits = 0, data_mask = 0; - uint16_t wdata = 0, rdata = 0; - - /* slaves addresses are 7 bits length */ - if (slave_addr > (1 << 7) - 1) { - printk(BIOS_ERR, "invalid SMBus address, aborting xfer\n"); - return -1; - } - - if (!claim_controller(dev, mcid)) { - printk(BIOS_ERR, "ayee! couldn't claim controller, giving up xfer\n"); - return -1; - } - - cmdbits = (slave_addr << SMBCMD_SA_SHIFT); - cmdbits |= (bus_addr << SMBCMD_BA_SHIFT); - - if (cmd == IMC_WRITE) { - wdata = (width == IMC_DATA_BYTE ? read8(data) : cpu_to_be16(read16(data))); - cmdbits |= (SMBCMD_TYPE_WRITE | wdata); - } else { - cmdbits |= SMBCMD_TYPE_READ; - } - - if (width == IMC_DATA_WORD) { - cmdbits |= SMBCMD_WORD_ACCESS; - data_mask = 0xffff; - } else { - data_mask = 0xff; - } - - cntlbits = pci_mmio_read_config32(dev, SMBCNTL(mcid)); - cntlbits &= ~SMBCNTL_DTI_MASK; - cntlbits |= (dti << SMBCNTL_DTI_SHIFT); - - pci_mmio_write_config32(dev, SMBCNTL(mcid), cntlbits); - - /* Pull the trigger */ - cmdbits |= SMBCMD_TRIGGER; - pci_mmio_write_config32(dev, SMBCMD(mcid), cmdbits); - - if (!poll_ready(dev, mcid, &stat)) { - printk(BIOS_ERR, "IMC xfer failed for slave %x", slave_addr); - ret = -1; - goto cleanup; - } - - if (stat & SMBSTAT_SBE) { - ret = -1; - goto cleanup; - } - - if (cmd == IMC_READ) { - rdata = stat & data_mask; - if (width == IMC_DATA_WORD) - write16(data, cpu_to_be16(rdata)); - else - write8(data, rdata); - } - - ret = 0; -cleanup: - release_controller(dev, SMBSTAT(mcid)); - - return ret; -} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 09f5e45577..d2b00efb2f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -153,7 +153,7 @@ void mca_configure(void); /* Lock chipset memory registers to protect SMM */ void cpu_lt_lock_memory(void *unused); -/* Get the a supported PRMRR size in bytes with respect users choice */ -int get_prmrr_size(void); +/* Get a supported PRMRR size in bytes with respect to users choice */ +int get_valid_prmrr_size(void); #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index a1dc3d9d56..f554933ef4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -27,6 +27,7 @@ /* Boot partition info and set boot partition info command ids */ #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d +#define MKHI_BUP_COMMON_DATA_CLEAR 0x20 /* ME Current Working States */ #define ME_HFS1_CWS_NORMAL 0x5 @@ -120,12 +121,10 @@ enum rst_req_type { }; /* - * Sends GLOBAL_RESET_REQ cmd to CSE. - * The reset type can be one of the above defined reset type. + * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. * Returns 0 on failure and 1 on success. */ -int cse_request_global_reset(enum rst_req_type rst_type); - +int cse_request_global_reset(void); /* * Sends HMRFPO_ENABLE command. * HMRFPO - Host ME Region Flash Protection Override. @@ -219,4 +218,8 @@ uint8_t cse_wait_com_soft_temp_disable(void); * currently selected partition. */ void cse_fw_sync(void *unused); + +/* Perform a board-specific reset sequence for CSE RO<->RW jump */ +void cse_board_reset(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 2a27ac8baf..6e2bf1c138 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -81,7 +81,6 @@ struct reset_mapping { uint32_t chipset; }; - /* Structure describes the groups within each community */ struct pad_group { int first_pad; /* offset of first pad of the group relative diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index e9abd0018c..31bbde0ce2 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -185,16 +185,6 @@ PAD_RESET(rst) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) -/* - * Set native function with RX Level/Edge configuration and disable - * input/output buffer if necessary - */ -#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(bufdis) | PAD_FUNC(func), \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) - #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS @@ -225,12 +215,6 @@ PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -/* Configure native function, iosstate, iosterm and disable input/output buffer */ -#define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ - PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) - /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ @@ -266,15 +250,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) +#define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | PAD_IOSSTATE(iosstate)) -#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ - PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#define PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* * General purpose input. The following macro sets the @@ -284,7 +269,7 @@ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ - PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1ad05..b04df76844 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -97,8 +97,6 @@ void lpc_disable_clkrun(void); void lpc_io_setup_comm_a_b(void); /* Enable PCH LPC by setting up generic decode range registers. */ void pch_enable_lpc(void); -/* Retrieve and setup SoC specific PCH LPC interrupt routing. */ -void soc_pch_pirq_init(const struct device *dev); /* Get SoC's generic IO decoder range register settings. */ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); @@ -107,5 +105,15 @@ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void); +/* Retrieve and setup PCH LPC interrupt routing. */ +void pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void pch_misc_init(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index d729308d52..1de6b5ec9a 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -44,7 +44,9 @@ #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 #define CPUID_ELKHARTLAKE_A0 0x90660 - +#define CPUID_ELKHARTLAKE_B0 0x90661 +#define CPUID_ALDERLAKE_S_A0 0x90670 +#define CPUID_ALDERLAKE_P_A0 0x906a0 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. @@ -69,6 +71,16 @@ const void *intel_mp_current_microcode(void); */ void get_microcode_info(const void **microcode, int *parallel); +/* + * Perform BSP and AP initialization + * This function can be called in below cases + * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude + * this call if user has selected USE_INTEL_FSP_MP_INIT) + * 2. coreboot would like to take APs control back after FSP-S has done with MP + * initialization based on user select USE_INTEL_FSP_MP_INIT + */ +void init_cpus(void); + /* * SoC Overrides * diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 82874f9224..4aa069e068 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -106,8 +106,9 @@ #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1<<11) +#define PRMRR_SUPPORTED (1<<12) +#define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2) /* Intel SDM: Table 36-6. diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 5f5aab52f4..ca50b13247 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H - /* * The PCIe Root Ports usually come in groups of up to 8 PCI-device * functions. diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index b092618920..dd02f0fe52 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -46,7 +46,6 @@ struct pcr_sbi_msg { uint16_t fid; /* 0x0B - Function ID */ }; - /* * API to perform sideband communication * diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a504d4..fa063f293e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -4,7 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H #include -#include +#include /* Forward declare the power state struct here */ struct chipset_power_state; @@ -220,4 +220,19 @@ void pmc_soc_set_afterg3_en(bool on); */ void pmc_set_power_failure_state(bool target_on); +/* + * This function ensures that the duration programmed in the PchPmPwrCycDur will never be + * smaller than the SLP_Sx assertion widths. + * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the + * default value PCH_PM_PWR_CYC_DUR. + */ +uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur); + +/* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ +void pmc_disable_acpi_timer(void); + +/* Disable XTAL shutdown qualification for low power idle. */ +void pmc_ignore_xtal_shutdown(void); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index f7b01aa067..844d88ec19 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -14,6 +14,8 @@ struct device_operations ipu_pci_ops = { static const uint16_t pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_IPU, PCI_DEVICE_ID_INTEL_JSL_IPU, + PCI_DEVICE_ID_INTEL_ADL_IPU, + 0 }; static const struct pci_driver intel_ipu __pci_driver = { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ea85911732..28c030f032 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -95,6 +95,13 @@ static void pch_lpc_set_resources(struct device *dev) pch_lpc_set_child_resources(dev); } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} +#endif + static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pch_lpc_set_resources, @@ -102,6 +109,7 @@ static struct device_operations device_ops = { #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt = southbridge_inject_dsdt, + .acpi_name = lpc_acpi_name, #endif .init = lpc_soc_init, .scan_bus = scan_static_bus, @@ -233,6 +241,70 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_9, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_10, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_11, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_12, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_13, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_14, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_15, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_16, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_17, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_18, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_19, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_20, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_21, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_22, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_23, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_24, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_25, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_26, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_27, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_28, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, + PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, 0 }; diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 481b3ea52d..67dd661460 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,13 +2,16 @@ #define __SIMPLE_DEVICE__ +#include #include #include #include #include +#include #include #include #include "lpc_def.h" +#include #include uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) @@ -236,7 +239,6 @@ void lpc_set_serirq_mode(enum serirq_mode mode) pci_write_config8(dev, LPC_SERIRQ_CTL, scnt); } - void lpc_io_setup_comm_a_b(void) { /* ComA Range 3F8h-3FFh [2:0] */ @@ -280,7 +282,7 @@ void pch_enable_lpc(void) lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - soc_pch_pirq_init(dev); + pch_pirq_init(); } void lpc_enable_pci_clk_cntl(void) @@ -293,3 +295,112 @@ void lpc_disable_clkrun(void) const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} + +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ +void pch_pirq_init(void) +{ + const struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + uint8_t int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); + } +} + +#define PPI_PORT_B 0x61 +#define SERR_DIS (1 << 2) +#define CMOS_NMI 0x70 +#define NMI_DIS (1 << 7) + +/* LPC MISC programming */ +void pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(PPI_PORT_B)) & 0xf0; + outb((reg8 | SERR_DIS), PPI_PORT_B); + + /* Disable NMI sources */ + outb(NMI_DIS, CMOS_NMI); +} diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 4f4ab43225..d97cd8d2d4 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -143,6 +143,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, PCI_DEVICE_ID_INTEL_JSP_P2SB, + PCI_DEVICE_ID_INTEL_ADP_P_P2SB, + PCI_DEVICE_ID_INTEL_ADP_S_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index f36366a754..e506905283 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -24,9 +24,8 @@ static void pch_pcie_init(struct device *dev) /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); - /* disable parity error response, enable ISA */ - pci_update_config16(dev, PCI_BRIDGE_CONTROL, - ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); + /* disable parity error response */ + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); if (CONFIG(PCIE_DEBUG_INFO)) { printk(BIOS_SPEW, " MBL = 0x%08x\n", @@ -292,6 +291,46 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP13, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP14, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP15, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP16, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP17, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP18, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP19, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP20, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP21, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP22, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP23, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP24, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP25, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27, + PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28, 0 }; diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 3aa0da8b1e..ce41b23620 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -29,3 +29,9 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK and lock register is located under PMC BASE at offset ETR. Note that the reset register is still at 0xCF9 this only controls the enable and lock feature. + +config PMC_LOW_POWER_MODE_PROGRAM + bool + help + Enable this for PMC devices to perform registers programming + to ensure low power in active idle scenario. diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 84e22a2585..24f28e33b7 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -122,6 +122,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, PCI_DEVICE_ID_INTEL_JSP_PMC, + PCI_DEVICE_ID_INTEL_ADP_P_PMC, + PCI_DEVICE_ID_INTEL_ADP_S_PMC, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e33d..8825bbe441 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,6 +18,38 @@ static struct chipset_power_state power_state; +/* List of Minimum Assertion durations in microseconds */ +enum min_assert_dur { + MinAssertDur0s = 0, + MinAssertDur60us = 60, + MinAssertDur1ms = 1000, + MinAssertDur50ms = 50000, + MinAssertDur98ms = 98000, + MinAssertDur500ms = 500000, + MinAssertDur1s = 1000000, + MinAssertDur2s = 2000000, + MinAssertDur3s = 3000000, + MinAssertDur4s = 4000000, +}; + +/* Signal Assertion duration values */ +struct cfg_assert_dur { + /* Minimum assertion duration of SLP_A signal */ + enum min_assert_dur slp_a; + + /* Minimum assertion duration of SLP_4 signal */ + enum min_assert_dur slp_s4; + + /* Minimum assertion duration of SLP_3 signal */ + enum min_assert_dur slp_s3; + + /* PCH PM Power Cycle duration */ + enum min_assert_dur pm_pwr_cyc_dur; +}; + +/* Default value of PchPmPwrCycDur */ +#define PCH_PM_PWR_CYC_DUR 0 + struct chipset_power_state *pmc_get_power_state(void) { struct chipset_power_state *ptr = NULL; @@ -574,3 +605,114 @@ void pmc_set_power_failure_state(const bool target_on) pmc_soc_set_afterg3_en(on); } + +/* This function returns the highest assertion duration of the SLP_Sx assertion widths */ +static enum min_assert_dur get_high_assert_width(const struct cfg_assert_dur *cfg_assert_dur) +{ + enum min_assert_dur max_assert_dur = cfg_assert_dur->slp_s4; + + if (max_assert_dur < cfg_assert_dur->slp_s3) + max_assert_dur = cfg_assert_dur->slp_s3; + + if (max_assert_dur < cfg_assert_dur->slp_a) + max_assert_dur = cfg_assert_dur->slp_a; + + return max_assert_dur; +} + +/* This function converts assertion durations from register-encoded to microseconds */ +static void get_min_assert_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur, + struct cfg_assert_dur *cfg_assert_dur) +{ + /* + * Ensure slp_x_dur_list[] elements in the devicetree config are in sync with + * FSP encoded values. + */ + + /* slp_s4_assert_dur_list : 1s, 1s(default), 2s, 3s, 4s */ + const enum min_assert_dur slp_s4_assert_dur_list[] = { + MinAssertDur1s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s + }; + + /* slp_s3_assert_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ + const enum min_assert_dur slp_s3_assert_dur_list[] = { + MinAssertDur50ms, MinAssertDur60us, MinAssertDur1ms, MinAssertDur50ms, + MinAssertDur2s + }; + + /* slp_a_assert_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ + const enum min_assert_dur slp_a_assert_dur_list[] = { + MinAssertDur2s, MinAssertDur0s, MinAssertDur4s, MinAssertDur98ms, MinAssertDur2s + }; + + /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ + const enum min_assert_dur pm_pwr_cyc_dur_list[] = { + MinAssertDur4s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s + }; + + /* Get signal assertion width */ + if (slp_s4_min_assert < ARRAY_SIZE(slp_s4_assert_dur_list)) + cfg_assert_dur->slp_s4 = slp_s4_assert_dur_list[slp_s4_min_assert]; + + if (slp_s3_min_assert < ARRAY_SIZE(slp_s3_assert_dur_list)) + cfg_assert_dur->slp_s3 = slp_s3_assert_dur_list[slp_s3_min_assert]; + + if (slp_a_min_assert < ARRAY_SIZE(slp_a_assert_dur_list)) + cfg_assert_dur->slp_a = slp_a_assert_dur_list[slp_a_min_assert]; + + if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) + cfg_assert_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; +} + +/* + * This function ensures that the duration programmed in the PchPmPwrCycDur will never be + * smaller than the SLP_Sx assertion widths. + * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the + * default value PCH_PM_PWR_CYC_DUR. + */ +uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, + uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur) +{ + /* Set default values for the minimum assertion duration */ + struct cfg_assert_dur cfg_assert_dur = { + .slp_a = MinAssertDur2s, + .slp_s4 = MinAssertDur1s, + .slp_s3 = MinAssertDur50ms, + .pm_pwr_cyc_dur = MinAssertDur4s + }; + + enum min_assert_dur high_assert_width; + + /* Convert assertion durations from register-encoded to microseconds */ + get_min_assert_dur(slp_s4_min_assert, slp_s3_min_assert, slp_a_min_assert, + pm_pwr_cyc_dur, &cfg_assert_dur); + + /* Get the highest assertion duration among PCH EDS specified signals for pwr_cyc_dur */ + high_assert_width = get_high_assert_width(&cfg_assert_dur); + + if (cfg_assert_dur.pm_pwr_cyc_dur >= high_assert_width) + return pm_pwr_cyc_dur; + + printk(BIOS_DEBUG, + "Set PmPwrCycDur to 4s as configured PmPwrCycDur (%d) violates PCH EDS " + "spec\n", pm_pwr_cyc_dur); + + return PCH_PM_PWR_CYC_DUR; +} + +#if CONFIG(PMC_LOW_POWER_MODE_PROGRAM) +void pmc_disable_acpi_timer(void) +{ + uint8_t *pmcbase = pmc_mmio_regs(); + + setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); +} + +void pmc_ignore_xtal_shutdown(void) +{ + uint8_t *pmcbase = pmc_mmio_regs(); + + setbits8(pmcbase + CPPMVRIC, XTALSDQDIS); +} +#endif /* PMC_LOW_POWER_MODE_PROGRAM */ diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig new file mode 100644 index 0000000000..c7253aebf7 --- /dev/null +++ b/src/soc/intel/common/block/sata/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_SATA + bool + help + Common SATA module for Intel PCH diff --git a/src/soc/intel/common/block/sata/Makefile.inc b/src/soc/intel/common/block/sata/Makefile.inc new file mode 100644 index 0000000000..623d1511e1 --- /dev/null +++ b/src/soc/intel/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c new file mode 100644 index 0000000000..7b234a9500 --- /dev/null +++ b/src/soc/intel/common/block/sata/sata.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = pci_dev_request_bus_master, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_U_SATA, + PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST, + PCI_DEVICE_ID_INTEL_CNL_SATA, + PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_CNP_H_SATA, + PCI_DEVICE_ID_INTEL_CNP_LP_SATA, + PCI_DEVICE_ID_INTEL_ICP_U_SATA, + PCI_DEVICE_ID_INTEL_CMP_SATA, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_SATA, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA_1, + PCI_DEVICE_ID_INTEL_JSP_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_1, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_3, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_4, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_5, + PCI_DEVICE_ID_INTEL_ADP_P_SATA_6, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_1, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_3, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_4, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_5, + PCI_DEVICE_ID_INTEL_ADP_S_SATA_6, + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 6e8323f333..48ba1fc411 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -6,16 +6,16 @@ config SOC_INTEL_COMMON_BLOCK_SGX help Intel Processor common SGX support +if SOC_INTEL_COMMON_BLOCK_SGX + config SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY bool - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Lock memory before SGX activation. This is only needed if MCHECK does not do it. config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE bool "Enable Software Guard Extensions (SGX) if available" - depends on SOC_INTEL_COMMON_BLOCK_SGX default n help Intel Software Guard Extensions (SGX) is a set of new CPU instructions that can be @@ -26,17 +26,16 @@ config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE int + depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX default 256 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_256MB default 128 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_128MB default 64 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB - default 32 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB - default 1 if SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB choice prompt "PRMRR size" + depends on SOC_INTEL_COMMON_BLOCK_SGX_ENABLE default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE - default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE help PRMRR (Protected Memory Range) is the space in RAM that is used to provide a protected memory area (e.g. for the Intel SGX Secure Enclaves). The memory region is accessible @@ -61,12 +60,6 @@ config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB bool "32 MiB" -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_1MB - depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB - bool "1 MiB" - -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_DISABLED - depends on !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE # SGX depends on PRMRR >= 32 MiB - bool "Disabled" - endchoice + +endif diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index aa7ad2f80e..59870fbdc8 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -75,6 +75,7 @@ static struct device_operations smbus_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_SMBUS, PCI_DEVICE_ID_INTEL_CNL_SMBUS, PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, @@ -87,6 +88,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, PCI_DEVICE_ID_INTEL_JSP_SMBUS, + PCI_DEVICE_ID_INTEL_ADP_P_SMBUS, + PCI_DEVICE_ID_INTEL_ADP_S_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 05cecf351b..5b4e6eb126 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H #define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H - /* SMBus IO Base Address */ #define SMBUS_IO_BASE 0xefa0 diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 7bd17c3e78..270b1aa796 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -169,7 +169,6 @@ static void busmaster_disable_on_bus(int bus) } } - void smihandler_southbridge_sleep( const struct smm_save_state_ops *save_state_ops) { @@ -201,8 +200,8 @@ void smihandler_southbridge_sleep( break; case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - gnvs->uior = uart_is_controller_initialized(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) + gnvs->uior = uart_is_controller_initialized(); /* Invalidate the cache before going to S3 */ wbinvd(); @@ -373,6 +372,10 @@ void smihandler_southbridge_apmc( /* EBX in the state save contains the GNVS pointer */ uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index cd5c4d42ae..295df09ed8 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -87,6 +87,22 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_SPI1, PCI_DEVICE_ID_INTEL_JSP_SPI2, PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_P_SPI0, + PCI_DEVICE_ID_INTEL_ADP_P_SPI1, + PCI_DEVICE_ID_INTEL_ADP_P_SPI2, + PCI_DEVICE_ID_INTEL_ADP_P_SPI3, + PCI_DEVICE_ID_INTEL_ADP_P_SPI4, + PCI_DEVICE_ID_INTEL_ADP_P_SPI5, + PCI_DEVICE_ID_INTEL_ADP_P_SPI6, + PCI_DEVICE_ID_INTEL_ADP_S_SPI0, + PCI_DEVICE_ID_INTEL_ADP_S_SPI1, + PCI_DEVICE_ID_INTEL_ADP_S_SPI2, + PCI_DEVICE_ID_INTEL_ADP_S_SPI3, + PCI_DEVICE_ID_INTEL_ADP_S_SPI4, + PCI_DEVICE_ID_INTEL_ADP_S_SPI5, + PCI_DEVICE_ID_INTEL_ADP_S_SPI6, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 67099df5b6..426a5f75ae 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -41,6 +41,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, PCI_DEVICE_ID_INTEL_JSP_SRAM, + PCI_DEVICE_ID_INTEL_ADP_P_SRAM, + PCI_DEVICE_ID_INTEL_ADP_S_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e6bbfc7d63..4c5731f9ca 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "systemagent_def.h" /* SoC override function */ @@ -46,6 +47,38 @@ __weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) return 32768; /* 32 GiB per channel */ } +static bool sa_supports_ecc(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_ECCDIS); +} + +static size_t sa_slots_per_channel(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_DDPCD) + 1; +} + +static size_t sa_number_of_channels(const uint32_t capid0_a) +{ + return !(capid0_a & CAPID_PDCD) + 1; +} + +static void sa_soc_systemagent_init(struct device *dev) +{ + soc_systemagent_init(dev); + + struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO); + if (m == NULL) + return; + + const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A); + + m->ecc_capable = sa_supports_ecc(capid0_a); + m->max_capacity_mib = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capid0_a)) * + sa_number_of_channels(capid0_a); + m->number_of_devices = sa_slots_per_channel(capid0_a) * + sa_number_of_channels(capid0_a); +} + /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. @@ -113,7 +146,6 @@ void sa_fill_gnvs(struct global_nvs *gnvs) gnvs->a4gb, gnvs->a4gs); } - static void sa_get_mem_map(struct device *dev, uint64_t *values) { int i; @@ -125,8 +157,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable - * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - top_of_ram -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * * The default SMRAM space is reserved so that the range doesn't @@ -140,9 +171,10 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * is not omitted the mtrr code will setup the area as cacheable * causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * Don't need to mark the entire top_of_ram till TOLUD range (used + * for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as + * cacheable for OS usage as coreboot already done with mpinit w/ smm + * relocation early. * * It should be noted that cacheable entry types need to be added in * order. The reason is that the current MTRR code assumes this and @@ -173,13 +205,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TOLUD */ base_k = top_of_ram; - size_k = sa_map_values[SA_BGSM_REG] - base_k; - reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); - - /* BGSM -> TOLUD */ - base_k = sa_map_values[SA_BGSM_REG]; size_k = sa_map_values[SA_TOLUD_REG] - base_k; mmio_resource(dev, index++, base_k / KiB, size_k / KiB); @@ -226,7 +253,7 @@ static void imr_resource(struct device *dev, int idx, uint32_t base, /* * Add IMR ranges that hang off the host bridge/memory - * controller device in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * controller device in case CONFIG(SA_ENABLE_IMR) is selected by SoC. */ static void sa_add_imr_resources(struct device *dev, int *resource_cnt) { @@ -262,55 +289,6 @@ static void systemagent_read_resources(struct device *dev) sa_add_imr_resources(dev, &index); } -#if CONFIG(GENERATE_SMBIOS_TABLES) -static bool sa_supports_ecc(const uint32_t capida) -{ - return !(capida & CAPID_ECCDIS); -} - -static size_t sa_slots_per_channel(const uint32_t capida) -{ - return !(capida & CAPID_DDPCD) + 1; -} - -static size_t sa_number_of_channels(const uint32_t capida) -{ - return !(capida & CAPID_PDCD) + 1; -} - -static int sa_smbios_write_type_16(struct device *dev, int *handle, - unsigned long *current) -{ - struct smbios_type16 *t = (struct smbios_type16 *)*current; - int len = sizeof(struct smbios_type16); - const uint32_t capida = pci_read_config32(dev, CAPID0_A); - - struct memory_info *meminfo; - meminfo = cbmem_find(CBMEM_ID_MEMINFO); - if (meminfo == NULL) - return 0; /* can't find mem info in cbmem */ - - memset(t, 0, sizeof(struct smbios_type16)); - t->type = SMBIOS_PHYS_MEMORY_ARRAY; - t->handle = *handle; - t->length = len - 2; - t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; - t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = sa_supports_ecc(capida) ? MEMORY_ARRAY_ECC_SINGLE_BIT : - MEMORY_ARRAY_ECC_NONE; - /* no error information handle available */ - t->memory_error_information_handle = 0xFFFE; - t->maximum_capacity = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capida)) * - sa_number_of_channels(capida) * (MiB / KiB); - t->number_of_memory_devices = sa_slots_per_channel(capida) * - sa_number_of_channels(capida); - - *current += len; - *handle += 1; - return len; -} -#endif - void enable_power_aware_intr(void) { uint8_t pair; @@ -326,14 +304,11 @@ static struct device_operations systemagent_ops = { .read_resources = systemagent_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = soc_systemagent_init, + .init = sa_soc_systemagent_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif -#if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = sa_smbios_write_type_16, -#endif }; static const unsigned short systemagent_ids[] = { @@ -390,16 +365,52 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_4_2, PCI_DEVICE_ID_INTEL_CML_H_8_2, - PCI_DEVICE_ID_INTEL_TGL_ID_U, - PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, - PCI_DEVICE_ID_INTEL_TGL_ID_Y, + PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2, + PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, + PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, + PCI_DEVICE_ID_INTEL_EHL_ID_2, + PCI_DEVICE_ID_INTEL_EHL_ID_3, + PCI_DEVICE_ID_INTEL_EHL_ID_4, + PCI_DEVICE_ID_INTEL_EHL_ID_5, + PCI_DEVICE_ID_INTEL_EHL_ID_6, + PCI_DEVICE_ID_INTEL_EHL_ID_7, + PCI_DEVICE_ID_INTEL_EHL_ID_8, + PCI_DEVICE_ID_INTEL_EHL_ID_9, + PCI_DEVICE_ID_INTEL_EHL_ID_10, + PCI_DEVICE_ID_INTEL_EHL_ID_11, + PCI_DEVICE_ID_INTEL_EHL_ID_12, PCI_DEVICE_ID_INTEL_JSL_ID_1, PCI_DEVICE_ID_INTEL_JSL_ID_2, PCI_DEVICE_ID_INTEL_JSL_ID_3, PCI_DEVICE_ID_INTEL_JSL_ID_4, + PCI_DEVICE_ID_INTEL_JSL_ID_5, + PCI_DEVICE_ID_INTEL_ADL_S_ID_1, + PCI_DEVICE_ID_INTEL_ADL_S_ID_2, + PCI_DEVICE_ID_INTEL_ADL_S_ID_3, + PCI_DEVICE_ID_INTEL_ADL_S_ID_4, + PCI_DEVICE_ID_INTEL_ADL_S_ID_5, + PCI_DEVICE_ID_INTEL_ADL_S_ID_6, + PCI_DEVICE_ID_INTEL_ADL_S_ID_7, + PCI_DEVICE_ID_INTEL_ADL_S_ID_8, + PCI_DEVICE_ID_INTEL_ADL_S_ID_9, + PCI_DEVICE_ID_INTEL_ADL_S_ID_10, + PCI_DEVICE_ID_INTEL_ADL_S_ID_11, + PCI_DEVICE_ID_INTEL_ADL_S_ID_12, + PCI_DEVICE_ID_INTEL_ADL_S_ID_13, + PCI_DEVICE_ID_INTEL_ADL_S_ID_14, + PCI_DEVICE_ID_INTEL_ADL_S_ID_15, + PCI_DEVICE_ID_INTEL_ADL_P_ID_1, + PCI_DEVICE_ID_INTEL_ADL_P_ID_2, + PCI_DEVICE_ID_INTEL_ADL_P_ID_3, + PCI_DEVICE_ID_INTEL_ADL_P_ID_4, + PCI_DEVICE_ID_INTEL_ADL_P_ID_5, + PCI_DEVICE_ID_INTEL_ADL_P_ID_6, + PCI_DEVICE_ID_INTEL_ADL_P_ID_7, + PCI_DEVICE_ID_INTEL_ADL_P_ID_8, + PCI_DEVICE_ID_INTEL_ADL_P_ID_9, 0 }; diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index a7823c347c..7517b140fb 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H - /* Device 0:0.0 PCI configuration space */ /* GMCH Graphics Control Register */ @@ -40,7 +39,7 @@ #define MCH_PAIR 0x5418 /* - * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC. + * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC. * * IMR registers are found under MCHBAR. */ diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index e731465b3b..3437ec7477 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -4,21 +4,10 @@ config SOC_INTEL_COMMON_BLOCK_UART help Intel Processor common UART support -config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART - hex - help - Clock m-divisor value for m/n divider - -config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL - depends on SOC_INTEL_COMMON_BLOCK_UART - hex - help - Clock m-divisor value for m/n divider +if SOC_INTEL_COMMON_BLOCK_UART config INTEL_LPSS_UART_FOR_CONSOLE bool - depends on SOC_INTEL_COMMON_BLOCK_UART select DRIVERS_UART_8250MEM_32 select FIXED_UART_FOR_CONSOLE help @@ -26,3 +15,5 @@ config INTEL_LPSS_UART_FOR_CONSOLE for the coreboot console. WARNING: UART_FOR_CONSOLE has to be set to a correct value, otherwise wrong pad configurations might be selected. + +endif diff --git a/src/soc/intel/common/block/uart/chip.h b/src/soc/intel/common/block/uart/chip.h new file mode 100644 index 0000000000..5981126fa9 --- /dev/null +++ b/src/soc/intel/common/block/uart/chip.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +/* Indirect include for static.c: */ +#include + +#ifndef _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ +#define _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ + +struct soc_intel_common_block_uart_config { + /* The Device ID read from config space at offset[2:4] when not hidden */ + u16 devid; +}; + +#endif /* _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index fac05775fa..142a9365a9 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -12,7 +13,9 @@ #include #include #include +#include #include +#include "chip.h" #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) #define UART_CONSOLE_INVALID_INDEX 0xFF @@ -34,7 +37,7 @@ static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) } #if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) return CONFIG_CONSOLE_UART_BASE_ADDRESS; @@ -225,11 +228,156 @@ static void uart_common_enable_resources(struct device *dev) } } +static void uart_acpi_write_irq(const struct device *dev) +{ + struct acpi_irq irq; + + switch (dev->path.pci.devfn) { + case PCH_DEVFN_UART0: + irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART0_IRQ); + break; + case PCH_DEVFN_UART1: + irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART1_IRQ); + break; + case PCH_DEVFN_UART2: + irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ); + break; + default: + return; + } + + acpi_device_write_interrupt(&irq); +} + +/* + * Generate an ACPI entry if the device is enabled in devicetree for the ACPI + * LPSS driver. In this mode the device and vendor ID reads as 0xffff, but the + * PCI device is still there. + */ +static void uart_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *hid = acpi_device_hid(dev); + struct resource *res; + + /* In ACPI mode the device is "invisible" */ + if (!dev->hidden) + return; + + if (!scope || !hid) + return; + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", hid); + /* + * Advertise compatibility to Sunrise Point, as the Linux kernel doesn't support + * CannonPoint yet... + */ + if (strcmp(hid, "INT34B8") == 0) + acpigen_write_name_string("_CID", "INT3448"); + else if (strcmp(hid, "INT34B9") == 0) + acpigen_write_name_string("_CID", "INT3449"); + else if (strcmp(hid, "INT34BA") == 0) + acpigen_write_name_string("_CID", "INT344A"); + + acpi_device_write_uid(dev); + acpigen_write_name_string("_DDN", "LPSS ACPI UART"); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + uart_acpi_write_irq(dev); + acpigen_write_mem32fixed(1, res->base, res->size); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *uart_acpi_hid(const struct device *dev) +{ + switch (dev->device) { + case PCI_DEVICE_ID_INTEL_APL_UART0: + return "80865abc"; + case PCI_DEVICE_ID_INTEL_APL_UART1: + return "80865abe"; + case PCI_DEVICE_ID_INTEL_APL_UART2: + return "80865ac0"; + case PCI_DEVICE_ID_INTEL_GLK_UART0: + return "808631bc"; + case PCI_DEVICE_ID_INTEL_GLK_UART1: + return "808631be"; + case PCI_DEVICE_ID_INTEL_GLK_UART2: + return "808631c0"; + case PCI_DEVICE_ID_INTEL_GLK_UART3: + return "808631ee"; + case PCI_DEVICE_ID_INTEL_SPT_UART0: + case PCI_DEVICE_ID_INTEL_SPT_H_UART0: + return "INT3448"; + case PCI_DEVICE_ID_INTEL_SPT_UART1: + case PCI_DEVICE_ID_INTEL_SPT_H_UART1: + return "INT3449"; + case PCI_DEVICE_ID_INTEL_SPT_UART2: + case PCI_DEVICE_ID_INTEL_SPT_H_UART2: + return "INT344A"; + case PCI_DEVICE_ID_INTEL_CNP_H_UART0: + return "INT34B8"; + case PCI_DEVICE_ID_INTEL_CNP_H_UART1: + return "INT34B9"; + case PCI_DEVICE_ID_INTEL_CNP_H_UART2: + return "INT34BA"; + default: + return NULL; + } +} + +static const char *uart_acpi_name(const struct device *dev) +{ + switch (dev->device) { + case PCI_DEVICE_ID_INTEL_APL_UART0: + case PCI_DEVICE_ID_INTEL_GLK_UART0: + case PCI_DEVICE_ID_INTEL_SPT_UART0: + case PCI_DEVICE_ID_INTEL_SPT_H_UART0: + case PCI_DEVICE_ID_INTEL_CNP_H_UART0: + return "UAR0"; + case PCI_DEVICE_ID_INTEL_APL_UART1: + case PCI_DEVICE_ID_INTEL_GLK_UART1: + case PCI_DEVICE_ID_INTEL_SPT_UART1: + case PCI_DEVICE_ID_INTEL_SPT_H_UART1: + case PCI_DEVICE_ID_INTEL_CNP_H_UART1: + return "UAR1"; + case PCI_DEVICE_ID_INTEL_APL_UART2: + case PCI_DEVICE_ID_INTEL_GLK_UART2: + case PCI_DEVICE_ID_INTEL_SPT_UART2: + case PCI_DEVICE_ID_INTEL_SPT_H_UART2: + case PCI_DEVICE_ID_INTEL_CNP_H_UART2: + return "UAR2"; + case PCI_DEVICE_ID_INTEL_GLK_UART3: + return "UAR3"; + default: + return NULL; + } +} + static struct device_operations device_ops = { .read_resources = uart_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = uart_common_enable_resources, .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = uart_fill_ssdt, + .acpi_hid = uart_acpi_hid, + .acpi_name = uart_acpi_name, }; static const unsigned short pci_device_ids[] = { @@ -274,6 +422,20 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_UART0, PCI_DEVICE_ID_INTEL_JSP_UART1, PCI_DEVICE_ID_INTEL_JSP_UART2, + PCI_DEVICE_ID_INTEL_ADP_S_UART0, + PCI_DEVICE_ID_INTEL_ADP_S_UART1, + PCI_DEVICE_ID_INTEL_ADP_S_UART2, + PCI_DEVICE_ID_INTEL_ADP_S_UART3, + PCI_DEVICE_ID_INTEL_ADP_S_UART4, + PCI_DEVICE_ID_INTEL_ADP_S_UART5, + PCI_DEVICE_ID_INTEL_ADP_S_UART6, + PCI_DEVICE_ID_INTEL_ADP_P_UART0, + PCI_DEVICE_ID_INTEL_ADP_P_UART1, + PCI_DEVICE_ID_INTEL_ADP_P_UART2, + PCI_DEVICE_ID_INTEL_ADP_P_UART3, + PCI_DEVICE_ID_INTEL_ADP_P_UART4, + PCI_DEVICE_ID_INTEL_ADP_P_UART5, + PCI_DEVICE_ID_INTEL_ADP_P_UART6, 0, }; @@ -282,4 +444,17 @@ static const struct pci_driver pch_uart __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +static void uart_enable(struct device *dev) +{ + struct soc_intel_common_block_uart_config *conf = dev->chip_info; + dev->ops = &device_ops; + dev->device = conf ? conf->devid : 0; +} + +struct chip_operations soc_intel_common_block_uart_ops = { + CHIP_NAME("LPSS UART in ACPI mode") + .enable_dev = uart_enable +}; + #endif /* ENV_RAMSTAGE */ diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index a5cd9ca005..54cb07650e 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -33,6 +33,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, PCI_DEVICE_ID_INTEL_JSP_XDCI, + PCI_DEVICE_ID_INTEL_ADP_P_XDCI, + PCI_DEVICE_ID_INTEL_ADP_S_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9d312d02b2..47f2567d29 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -121,6 +121,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, PCI_DEVICE_ID_INTEL_JSP_XHCI, + PCI_DEVICE_ID_INTEL_ADP_P_XHCI, + PCI_DEVICE_ID_INTEL_ADP_S_XHCI, 0 }; diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index ee94c3e624..83bbb59588 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include + #include "hda_verb.h" -/* - * Set bits in a register and wait for status - */ static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -20,9 +19,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -37,9 +34,6 @@ static int set_bits(void *port, u32 mask, u32 val) return 0; } -/* - * Probe for supported codecs - */ int hda_codec_detect(u8 *base) { u8 reg8; @@ -81,18 +75,16 @@ no_codec: } /* - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -102,27 +94,23 @@ static int hda_wait_for_ready(u8 *base) } /* - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int hda_wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -175,9 +163,6 @@ static u32 hda_find_verb(u32 verb_table_bytes, return 0; } -/* - * Write a supplied verb table - */ int hda_codec_write(u8 *base, u32 size, const u32 *data) { int i; @@ -195,9 +180,6 @@ int hda_codec_write(u8 *base, u32 size, const u32 *data) return 0; } -/* - * Initialize codec, then find the verb table and write it - */ int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) { const u32 *verb; diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h index 9b77ee31bf..ddd57747b7 100644 --- a/src/soc/intel/common/hda_verb.h +++ b/src/soc/intel/common/hda_verb.h @@ -5,16 +5,6 @@ #include -#define HDA_GCAP_REG 0x00 -#define HDA_GCTL_REG 0x08 -#define HDA_GCTL_CRST (1 << 0) -#define HDA_STATESTS_REG 0x0e -#define HDA_IC_REG 0x60 -#define HDA_IR_REG 0x64 -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - int hda_codec_detect(u8 *base); int hda_codec_write(u8 *base, u32 size, const u32 *data); int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data); diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 6e7f2f6c75..cca65d6b2a 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -32,6 +32,7 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index 17b8cbc0e9..22d7147764 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H #define SOC_INTEL_COMMON_PCH_LOCKDOWN_H - /* * This function will get lockdown config specific to soc. * diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index f0916e1faf..798d473cad 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -9,11 +9,7 @@ if SOC_INTEL_DENVERTON_NS config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON @@ -25,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 - select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -121,13 +116,6 @@ config IQAT_ENABLE bool "Enable IQAT" default y -config IQAT_MEMORY_REGION_SIZE - depends on IQAT_ENABLE - hex - default 0x100000 - help - Do not change this value - config HSUART_DEV hex default 0x1a @@ -169,7 +157,7 @@ config DENVERTON_NS_CAR_NEM_ENHANCED depends on !FSP_CAR default y select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED + select USE_CAR_NEM_ENHANCED_V1 help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. diff --git a/src/soc/intel/denverton_ns/acpi/smbus.asl b/src/soc/intel/denverton_ns/acpi/smbus.asl deleted file mode 100644 index 7860f606c9..0000000000 --- a/src/soc/intel/denverton_ns/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.4 - -Device (SBUS) -{ - Name (_ADR, 0x001f0004) -} diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index ad9c088c15..68f55f295b 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -117,7 +117,7 @@ Device (P2SB) #include "pmc.asl" // SMBus 0:1f.4 -#include "smbus.asl" +#include // Northpeak 0:1f.7 #include "npk.asl" diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h index 47660cc3d7..fcf57ff2e4 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -9,7 +9,6 @@ #define GPIO_MAX_NUM_PER_GROUP 32 - #define NUM_NC_GPI_REGS \ (ALIGN_UP(V_PCH_GPIO_NC_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ / GPIO_MAX_NUM_PER_GROUP) @@ -29,7 +28,6 @@ #define NUM_GPI_STATUS_REGS (NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +\ NUM_SC0_GPI_REGS + NUM_SC1_GPI_REGS) - #define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ #include /* intelblocks/gpio.h depends on definitions in diff --git a/src/soc/intel/denverton_ns/include/soc/hob_mem.h b/src/soc/intel/denverton_ns/include/soc/hob_mem.h index 5f377b39e4..e7f0086dc8 100644 --- a/src/soc/intel/denverton_ns/include/soc/hob_mem.h +++ b/src/soc/intel/denverton_ns/include/soc/hob_mem.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _DENVERTON_NS_HOB_MEM_H #define _DENVERTON_NS_HOB_MEM_H diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index a7ec73bd51..ba251a8048 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -5,7 +5,6 @@ /* All these devices live on bus 0 with the associated device and function */ - #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) #if !defined(__SIMPLE_DEVICE__) diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 713fb1e3ac..add558bb98 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index 8ee02cca7f..7f804c7e8e 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include @@ -8,9 +9,7 @@ #define MY_PCI_DEV(SEGBUS, DEV, FN) \ ((((SEGBUS)&0xFFF) << 20) | (((DEV)&0x1F) << 15) | (((FN)&0x07) << 12)) -uintptr_t uart_platform_base(int idx); - -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)pci_io_read_config32( MY_PCI_DEV(0, CONFIG_HSUART_DEV, idx), diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig new file mode 100644 index 0000000000..7e78805648 --- /dev/null +++ b/src/soc/intel/elkhartlake/Kconfig @@ -0,0 +1,210 @@ +config SOC_INTEL_ELKHARTLAKE + bool + help + Intel Elkhartlake support + +if SOC_INTEL_ELKHARTLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_COMPRESS_FSP_S_LZ4 + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_2 + select FSP_PEIM_TO_PEIM_INTERFACE + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM + select CPU_INTEL_COMMON_SMM + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_202005_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x30400 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value + will be sum of FSP-M stack requirement(192 KiB) and CB romstage + stack requirement(~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x20000 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config IFD_CHIPSET + string + default "ehl" + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x8000 + +config MAX_ROOT_PORTS + int + default 8 + +config MAX_PCIE_CLOCKS + int + default 6 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# EHL UART source clock: 100MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config CBFS_SIZE + hex + default 0x200000 + +config FSP_HEADER_PATH + default "src/vendorcode/intel/fsp/fsp2_0/elkhartlake/" + +config FSP_FD_PATH + default "3rdparty/fsp/ElkhartLakeFspBinPkg/Fsp.fd" + +config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT + int "Debug Consent for EHL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1400 +endif diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc new file mode 100644 index 0000000000..5c46f86738 --- /dev/null +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -0,0 +1,60 @@ +ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += gpio.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += gpio.c +romstage-y += meminit.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += systemagent.c +ramstage-y += sd.c +ramstage-y += me.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmc.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c + +verstage-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake +CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include + +endif diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c new file mode 100644 index 0000000000..af837aba5d --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi.c @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * List of supported C-states in this processor. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C6_SHORT_LAT, /* 3 */ + C_STATE_C6_LONG_LAT, /* 4 */ + C_STATE_C7_SHORT_LAT, /* 5 */ + C_STATE_C7_LONG_LAT, /* 6 */ + C_STATE_C7S_SHORT_LAT, /* 7 */ + C_STATE_C7S_LONG_LAT, /* 8 */ + C_STATE_C8, /* 9 */ + C_STATE_C9, /* 10 */ + C_STATE_C10, /* 11 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static const acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = {}, + [C_STATE_C1] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = C1_LATENCY, + .power = C1_POWER, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C6_LATENCY, + .power = C6_POWER, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C7_LATENCY, + .power = C7_POWER, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C8_LATENCY, + .power = C8_POWER, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C9_LATENCY, + .power = C9_POWER, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C10_LATENCY, + .power = C10_POWER, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_non_s0ix[] = { + C_STATE_C1, + C_STATE_C6_LONG_LAT, + C_STATE_C7S_LONG_LAT +}; + +static int cstate_set_s0ix[] = { + C_STATE_C1, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + int *set; + int i; + + config_t *config = config_of_soc(); + + int is_s0ix_enable = config->s0ix_enable; + + if (is_s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } + + for (i = 0; i < *entries; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + return map; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ + config_t *config = config_of_soc(); + + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, cores_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + config_t *config = config_of_soc(); + + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + if (config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +uint32_t soc_read_sci_irq_select(void) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + return read32((void *)pmc_bar + IRQ_REG); +} + +static unsigned long soc_fill_dmar(unsigned long current) +{ + const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; + bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; + + if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { + unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; + bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; + + if (vtvc0bar && vtvc0en) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, + 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + V_P2SB_CFG_IBDF_FUNC); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, + V_P2SB_CFG_HBDF_FUNC); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + + /* + * Create DMAR table only if we have VT-d capability and FSP does not override its + * feature. + */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || + !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + config_t *config = config_of_soc(); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + if (CONFIG(CONSOLE_CBMEM)) + /* Update the mem console pointer. */ + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, + const struct chipset_power_state *ps) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + return generic_pm1_en; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_HIGH; +} + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl new file mode 100644 index 0000000000..ac0d1df5cb --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/elkhartlake/acpi/pch_hda.asl b/src/soc/intel/elkhartlake/acpi/pch_hda.asl new file mode 100644 index 0000000000..340c76528d --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pch_hda.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001f0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (Arg0 == ^UUID) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (Arg2 == Zero) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (Arg2 == One) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..aa494a76f9 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +Name (PICP, Package () { + Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, + Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, + Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, + Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, + + Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, + + Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, + Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, + Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, + + Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, + + Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, + Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, + Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, + Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, + + Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, + Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, + Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, + Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, + + Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + /* SA GNA Device */ + Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IPU Device */ + Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, +}) + +Name (PICN, Package () { + Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, + + Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, + + Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, + + Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + /* SA GNA Device */ + Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, + /* SA IPU Device */ + Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 }, +}) + +Method (_PRT) +{ + If (PICM) { + Return (^PICP) + } Else { + Return (^PICN) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl new file mode 100644 index 0000000000..a19feb7168 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH PCIe support */ + +Method (IRQM, 1, Serialized) { + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 10 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, 0, 10 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 11 }, + Package () { 0x0000ffff, 3, 0, 10 } }) + + /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, 0, 11 }, + Package () { 0x0000ffff, 1, 0, 11 }, + Package () { 0x0000ffff, 2, 0, 10 }, + Package () { 0x0000ffff, 3, 0, 11 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9, 13 }) { + If (PICM) { + Return (IQAA) + } Else { + Return (IQAP) + } + } + + Case (Package () { 2, 6, 10, 14 }) { + If (PICM) { + Return (IQBA) + } Else { + Return (IQBP) + } + } + + Case (Package () { 3, 7, 11, 15 }) { + If (PICM) { + Return (IQCA) + } Else { + Return (IQCP) + } + } + + Case (Package () { 4, 8, 12, 16 }) { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + + Default { + If (PICM) { + Return (IQDA) + } Else { + Return (IQDP) + } + } + } +} + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/pmc.asl b/src/soc/intel/elkhartlake/acpi/pmc.asl new file mode 100644 index 0000000000..ea4134b0fa --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/pmc.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (\_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Elkhart Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/elkhartlake/acpi/scs.asl b/src/soc/intel/elkhartlake/acpi/scs.asl new file mode 100644 index 0000000000..b58608feed --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/scs.asl @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name (TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) // Sleep 50 us + + PGEN = 0 // Disable PG + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + PMCR = PMCR & 0xFFFC + TEMP = PMCR + } + + Method(_PS3, 0, Serialized) { + PGEN = 1 // Enable PG + + /* Set Power State to D3 */ + PMCR = PMCR | 0x0003 + TEMP = PMCR + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } + + /* SD CARD */ + Device (SDXC) + { + Name (_ADR, 0x00140005) + Name (_DDN, "SD Controller") + Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) + + OperationRegion (SDPC, PCI_Config, 0x00, 0x100) + Field (SDPC, WordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + /* + * _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (Arg0 == DSUU) { + /* Check the revision */ + If (Arg1 >= 0) { + /* + * Function Index 0 the return value is a buffer containing + * one bit for each function index, starting with zero. + * Bit 0 - Indicates whether there is support for any + * functions other than function 0. + * Bit 1 - Indicates support to clear power control register + * Bit 2 - Indicates support to set power control register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + /* + * For SD we have to support functions to + * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] + */ + If (Arg2 == 0) { + Return (Buffer () { 0x19 }) + } + /* + * Function Index 3: Set 1.8v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 3) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + /* + * Function Index 4: Set 3.3v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 4) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + } + } + Return(Buffer() { 0x0 }) + } + + Method(_INI) + { + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + } + + Method (_PS0, 0, Serialized) + { + PGEN = 0 /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_SDX) + + /* Set Power State to D0 */ + PMCR = PMCR & 0xFFFC + TEMP = PMCR + + /* Change pad mode to Native */ + GPMO(SD_PWR_EN_PIN, 0x1) + } + + Method (_PS3, 0, Serialized) + { + PGEN = 1 /* Enable PG */ + + /* Set Power State to D3 */ + PMCR = PMCR | 0x0003 + TEMP = PMCR + + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Enable Tx Buffer */ + GTXE(SD_PWR_EN_PIN, 0x1) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDXC) */ +} diff --git a/src/soc/intel/elkhartlake/acpi/serialio.asl b/src/soc/intel/elkhartlake/acpi/serialio.asl new file mode 100644 index 0000000000..f7bf452058 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/serialio.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel Serial IO Devices */ + +Device (I2C0) +{ + Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") +} + +Device (I2C1) +{ + Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") +} + +Device (I2C2) +{ + Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") +} + +Device (I2C3) +{ + Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") +} + +Device (I2C4) +{ + Name (_ADR, 0x00190000) + Name (_DDN, "Serial IO I2C Controller 4") +} + +Device (I2C5) +{ + Name (_ADR, 0x00190001) + Name (_DDN, "Serial IO I2C Controller 5") +} + +Device (SPI0) +{ + Name (_ADR, 0x001e0002) + Name (_DDN, "Serial IO SPI Controller 0") +} + +Device (SPI1) +{ + Name (_ADR, 0x001e0003) + Name (_DDN, "Serial IO SPI Controller 1") +} + +Device (SPI2) +{ + Name (_ADR, 0x00120006) + Name (_DDN, "Serial IO SPI Controller 2") +} + +Device (SPI3) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Serial IO SPI Controller 3") +} + +Device (UAR0) +{ + Name (_ADR, 0x001e0000) + Name (_DDN, "Serial IO UART Controller 0") +} + +Device (UAR1) +{ + Name (_ADR, 0x001e0001) + Name (_DDN, "Serial IO UART Controller 1") +} + +Device (UAR2) +{ + Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO UART Controller 2") +} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl new file mode 100644 index 0000000000..28705b1097 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include + +/* GPIO controller */ +#include "gpio.asl" + +/* GFX 00:02.0 */ +#include + +/* ESPI 0:1f.0 */ +#include + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* pmc 0:1f.2 */ +#include "pmc.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include + +/* PMC Core*/ +#include + +/* EMMC/SD card */ +#include "scs.asl" + +/* GbE 0:1f.6 */ +#include diff --git a/src/soc/intel/elkhartlake/acpi/xhci.asl b/src/soc/intel/elkhartlake/acpi/xhci.asl new file mode 100644 index 0000000000..445c7dbcea --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/xhci.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Elkhartlake PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 9) } + Device (SS02) { Name (_ADR, 10) } + Device (SS03) { Name (_ADR, 11) } + Device (SS04) { Name (_ADR, 12) } + Device (SS05) { Name (_ADR, 13) } + Device (SS06) { Name (_ADR, 14) } + } +} diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c new file mode 100644 index 0000000000..96e6268f74 --- /dev/null +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + bootblock_pch_early_init(); + bootblock_cpu_init(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + bootblock_pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/elkhartlake/bootblock/cpu.c b/src/soc/intel/elkhartlake/bootblock/cpu.c new file mode 100644 index 0000000000..bbce44cd60 --- /dev/null +++ b/src/soc/intel/elkhartlake/bootblock/cpu.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_cpu_init(void) +{ + /* + * Elkhartlake platform doesn't support booting from any other media + * (like eMMC on APL/GLK platform) than only booting from SPI device + * and on IA platform SPI is memory mapped hence enabling temporarily + * caching on memory-mapped spi boot media. + */ + fast_spi_cache_bios_region(); +} diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c new file mode 100644 index 0000000000..9224c486ec --- /dev/null +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0C00 + +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void soc_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +void bootblock_pch_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + p2sb_enable_bar(); + p2sb_configure_hpet(); + + /* + * Enabling PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + const uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable IO Space before changing the address */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF3 PMC space BAR4*/ + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + 0xffffffff, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + /* + * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same + * value programmed in LPC PCI offset 80h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); + } + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); +} diff --git a/src/soc/intel/elkhartlake/bootblock/report_platform.c b/src/soc/intel/elkhartlake/bootblock/report_platform.c new file mode 100644 index 0000000000..b1b7fe8524 --- /dev/null +++ b/src/soc/intel/elkhartlake/bootblock/report_platform.c @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct { + uint32_t cpuid; + const char *name; +} cpu_table[] = { + { CPUID_ELKHARTLAKE_A0, "Elkhartlake A0" }, + { CPUID_ELKHARTLAKE_B0, "Elkhartlake B0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake SKU-0" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_2, "Elkhartlake SKU-1" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_3, "Elkhartlake SKU-2" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_4, "Elkhartlake SKU-3" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_5, "Elkhartlake SKU-4" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_6, "Elkhartlake SKU-5" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_7, "Elkhartlake SKU-6" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_8, "Elkhartlake SKU-7" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_9, "Elkhartlake SKU-8" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_10, "Elkhartlake SKU-9" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_11, "Elkhartlake SKU-10" }, + { PCI_DEVICE_ID_INTEL_JSL_EHL, "Elkhartlake SKU-11" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_12, "Elkhartlake SKU-12" }, + { PCI_DEVICE_ID_INTEL_EHL_ID_13, "Elkhartlake SKU-13" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, + { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, + { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, + { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, + { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1-1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2-1" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1-2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2-2" }, + { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1-3" }, + { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2-3" }, +}; + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cpu_info(void) +{ + uint32_t i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; + txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; + vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + uint8_t mch_revision = get_dev_revision(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = SA_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c new file mode 100644 index 0000000000..cd65260c10 --- /dev/null +++ b/src/soc/intel/elkhartlake/chip.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct pcie_rp_group pch_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { 0 } +}; + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IPU: return "IPU0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_GBE: return "GLAN"; + } + + return NULL; +} +#endif + +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const config_t *config = config_of_soc(); + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + +void soc_init_pre_device(void *chip_info) +{ + /* Snapshot the current GPIO IRQ polarities. FSP is setting a + * default policy that doesn't honor boards' requirements. */ + itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + /* Perform silicon specific init. */ + fsp_silicon_init(romstage_handoff_is_resume()); + + /* Display FIRMWARE_VERSION_INFO_HOB */ + fsp_display_fvi_version_hob(); + + /* Restore GPIO IRQ polarities back to previous settings. */ + itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + pcie_rp_update_devicetree(pch_rp_groups); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_cpu_entries, +#endif +}; + +extern struct device_operations pmc_ops; +static void soc_enable(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI && + dev->path.pci.devfn == PCH_DEVFN_PMC) + dev->ops = &pmc_ops; +} + +struct chip_operations soc_intel_elkhartlake_ops = { + CHIP_NAME("Intel Elkhartlake") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h new file mode 100644 index 0000000000..5037147d74 --- /dev/null +++ b/src/soc/intel/elkhartlake/chip.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + +struct soc_intel_elkhartlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form PMC_GPP_[A:U] or GPD. */ + uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable_ac; + int deep_s3_enable_dc; + int deep_s5_enable_ac; + int deep_s5_enable_dc; + + /* Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, + * 4:FixedPoint3, 5:Enabled */ + enum { + SaGv_Disabled, + SaGv_FixedPoint0, + SaGv_FixedPoint1, + SaGv_FixedPoint2, + SaGv_FixedPoint3, + SaGv_Enabled, + } SaGv; + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t RMT; + + /* USB related */ + struct usb2_port_config usb2_ports[16]; + struct usb3_port_config usb3_ports[10]; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + + /* SATA related */ + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* Audio related */ + uint8_t PchHdaDspEnable; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect; + + /* PCIe Root Ports */ + uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. + * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, + * 0xFF: not used */ + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to + * clksrc. */ + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe RP L1 substate */ + enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, + } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + + /* SMBus */ + uint8_t SmbusEnable; + + /* eMMC and SD */ + uint8_t ScsEmmcHs400Enabled; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; + + /* Integrated Sensor */ + uint8_t PchIshEnable; + + /* Heci related */ + uint8_t Heci3Enabled; + + /* Gfx related */ + uint8_t IgdDvmt50PreAlloc; + uint8_t InternalGfx; + uint8_t SkipExtGfxScan; + + uint32_t GraphicsConfigPtr; + uint8_t Device4Enable; + + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + /* Intel Speed Shift Technology */ + uint8_t speed_shift_enable; + + /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + uint8_t eist_enable; + + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + /* + * PRMRR size setting with below options + * Disable: 0x0 + * 32MB: 0x2000000 + * 64MB: 0x4000000 + * 128 MB: 0x8000000 + * 256 MB: 0x10000000 + * 512 MB: 0x20000000 + */ + uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode + */ + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + + /* Debug interface selection */ + enum { + DEBUG_INTERFACE_RAM = (1 << 0), + DEBUG_INTERFACE_UART_8250IO = (1 << 1), + DEBUG_INTERFACE_USB3 = (1 << 3), + DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), + DEBUG_INTERFACE_TRACEHUB = (1 << 5), + } debug_interface_flag; + + /* GPIO SD card detect pin */ + unsigned int sdcard_cd_gpio; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + enum { + FORCE_DISABLE, + FORCE_ENABLE, + } CnviBtAudioOffload; + + /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t DdiPortAConfig; + uint8_t DdiPortBConfig; + + /* Enable(1)/Disable(0) HPD */ + uint8_t DdiPortAHpd; + uint8_t DdiPortBHpd; + uint8_t DdiPortCHpd; + uint8_t DdiPort1Hpd; + uint8_t DdiPort2Hpd; + uint8_t DdiPort3Hpd; + uint8_t DdiPort4Hpd; + + /* Enable(1)/Disable(0) DDC */ + uint8_t DdiPortADdc; + uint8_t DdiPortBDdc; + uint8_t DdiPortCDdc; + uint8_t DdiPort1Ddc; + uint8_t DdiPort2Ddc; + uint8_t DdiPort3Ddc; + uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * Only override CPU flex ratio to not boot with non-turbo max. + */ + uint8_t cpu_ratio_override; + + /* Skip CPU replacement check + * 0: disable + * 1: enable + * Setting this option to skip CPU replacement check to avoid the forced MRC training + * for the platforms with soldered down SOC. + */ + uint8_t SkipCpuReplacementCheck; + + /* + * SLP_S3 Minimum Assertion Width Policy + * 1 = 60us + * 2 = 1ms + * 3 = 50ms (default) + * 4 = 2s + */ + uint8_t PchPmSlpS3MinAssert; + + /* + * SLP_S4 Minimum Assertion Width Policy + * 1 = 1s (default) + * 2 = 2s + * 3 = 3s + * 4 = 4s + */ + uint8_t PchPmSlpS4MinAssert; + + /* + * SLP_SUS Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 500ms + * 3 = 1s + * 4 = 4s (default) + */ + uint8_t PchPmSlpSusMinAssert; + + /* + * SLP_A Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 4s + * 3 = 98ms + * 4 = 2s (default) + */ + uint8_t PchPmSlpAMinAssert; + + /* + * PCH PM Reset Power Cycle Duration + * 0 = 4s (default) + * 1 = 1s + * 2 = 2s + * 3 = 3s + * 4 = 4s + * + * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the + * stretch duration programmed in the following registers: + * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + * - PM_CFG.SLP_LAN_MIN_ASST_WDTH + */ + uint8_t PchPmPwrCycDur; +}; + +typedef struct soc_intel_elkhartlake_config config_t; + +#endif diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c new file mode 100644 index 0000000000..382bbf7b01 --- /dev/null +++ b/src/soc/intel/elkhartlake/cpu.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_fsp_load(void) +{ + fsps_load(romstage_handoff_is_resume()); +} + +static void configure_isst(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + +static void configure_misc(void) +{ + msr_t msr; + + config_t *conf = config_of_soc(); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 23); /* Lock it */ + wrmsr(MSR_POWER_CTL, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable */ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERF_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERF_BIAS, msr); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(struct device *cpu) +{ + /* Clear out pending MCEs */ + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); + + /* Enable the local CPU apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Configure Intel Speed Shift */ + configure_isst(); + + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Enable Turbo */ + enable_turbo(); +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + global_smi_enable(); +} + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = soc_fsp_load, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); +} diff --git a/src/soc/intel/elkhartlake/elog.c b/src/soc/intel/elkhartlake/elog.c new file mode 100644 index 0000000000..c88efc81bc --- /dev/null +++ b/src/soc/intel/elkhartlake/elog.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + /* SMBUS Wake */ + if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* Thermal Trip */ + if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) + elog_add_event(ELOG_TYPE_THERM_TRIP); + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon_a & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon_a & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco2_sts & TCO_STS_SECOND_TO) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* RTC reset */ + if (ps->gen_pmcon_b & RTC_BATTERY_DEAD) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* Host Reset Status */ + if (ps->gen_pmcon_a & HOST_RST_STS) + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + + if (!ps) { + printk(BIOS_ERR, "chipset_power_state not found!\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > ACPI_S0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL); + +void elog_gsmi_cb_platform_log_wake_source(void) +{ + struct chipset_power_state ps; + pmc_fill_pm_reg_info(&ps); + pch_log_wake_source(&ps); +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c new file mode 100644 index 0000000000..a531fccbb0 --- /dev/null +++ b/src/soc/intel/elkhartlake/espi.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* To reserve certain memory range as reserved range for BIOS usage. +* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" +*/ +static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { + { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return ehl_lpc_fixed_mmio_ranges; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + +#if ENV_RAMSTAGE +static void soc_mirror_dmi_pcr_io_dec(void) +{ + struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); + uint32_t io_dec_arr[] = { + pci_read_config32(dev, ESPI_GEN1_DEC), + pci_read_config32(dev, ESPI_GEN2_DEC), + pci_read_config32(dev, ESPI_GEN3_DEC), + pci_read_config32(dev, ESPI_GEN4_DEC), + }; + /* Mirror these same settings in DMI PCR */ + soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); +} + +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); + soc_mirror_dmi_pcr_io_dec(); +} + +#endif diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c new file mode 100644 index 0000000000..bae8bcf5a8 --- /dev/null +++ b/src/soc/intel/elkhartlake/finalize.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void pch_finalize(void) +{ + config_t *config; + + /* TCO Lock down */ + tco_lockdown(); + + /* TODO: Add Thermal Configuration */ + + /* + * Disable ACPI PM timer based on dt policy + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + * + * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is + * just required to get to chip config. PCH_DEV_PMC is hidden by this + * point and hence removed from the root bus. pcidev_path_on_root thus + * returns NULL for PCH_DEV_PMC device. + */ + config = config_of_soc(); + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); + + /* Disable XTAL shutdown qualification for low power idle. */ + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); + + pmc_clear_pmcon_sts(); +} + +static void soc_finalize(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); + apm_control(APM_CNT_FINALIZE); + + /* Indicate finalize step with post code */ + post_code(POST_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c new file mode 100644 index 0000000000..3d740fb74c --- /dev/null +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * ME End of Post configuration + * 0 - Disable EOP. + * 1 - Send in PEI (Applicable for FSP in API mode) + * 2 - Send in DXE (Not applicable for FSP in API mode) + */ +enum { + EOP_DISABLE, + EOP_PEI, + EOP_DXE, +} EndOfPost; + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_elkhartlake_config *config = config_of_soc(); + /* TODO: Update with UPD override as FSP matures */ +} + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + unsigned int i; + struct device *dev; + FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_elkhartlake_config *config = config_of_soc(); + + /* Parse device tree and fill in FSP UPDs */ + parse_devicetree(params); + + /* TODO: Update with UPD override as FSP matures */ + + /* Override/Fill FSP Silicon Param for mainboard */ + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/elkhartlake/gpio.c b/src/soc/intel/elkhartlake/gpio.c new file mode 100644 index 0000000000..9ba5d8e058 --- /dev/null +++ b/src/soc/intel/elkhartlake/gpio.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; + +static const struct reset_mapping rst_map_com0[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO driver for Elkhartlake on Windows/Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for MCC at: + * linux/drivers/pinctrl/intel/pinctrl-elkhartlake.c + */ +static const struct pad_group ehl_community0_groups[] = { + + INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0), /* GPP_F */ + INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8), + INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ + INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10), + INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ + INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ +}; + +static const struct pad_group ehl_community1_groups[] = { + INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160), /* GPP_H */ + INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192), /* GPP_D */ + INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13), + INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224), /* VGPIO */ + INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256), /* GPP_C */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group ehl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD10), /* GPD */ + INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), +}; + + +static const struct pad_group ehl_community4_groups[] = { + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), + INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ + INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), +}; + + +static const struct pad_group ehl_community5_groups[] = { + INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ +}; + +static const struct pad_community ehl_communities[TOTAL_GPIO_COMM] = { + /* GPP F, B, A, S, R */ + [COMM_0] = { + .port = PID_GPIOCOM0, + .first_pad = GPP_F0, + .last_pad = GPP_R7, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FBASR", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com0, + .num_reset_vals = ARRAY_SIZE(rst_map_com0), + .groups = ehl_community0_groups, + .num_groups = ARRAY_SIZE(ehl_community0_groups), + }, + /* GPP H, D, VGPIO, C */ + [COMM_1] = { + .port = PID_GPIOCOM1, + .first_pad = GPP_H0, + .last_pad = GPP_C23, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_HDC", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ehl_community1_groups, + .num_groups = ARRAY_SIZE(ehl_community1_groups), + }, + /* GPD */ + [COMM_2] = { + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPIO_RSVD_17, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ehl_community2_groups, + .num_groups = ARRAY_SIZE(ehl_community2_groups), + }, + /* GPP E */ + [COMM_4] = { + .port = PID_GPIOCOM4, + .first_pad = GPIO_RSVD_18, + .last_pad = GPIO_RSVD_36, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_E", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ehl_community4_groups, + .num_groups = ARRAY_SIZE(ehl_community4_groups), + }, + /* GPP G */ + [COMM_5] = { + .port = PID_GPIOCOM5, + .first_pad = GPP_G0, + .last_pad = GPP_G7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_G", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = ehl_community5_groups, + .num_groups = ARRAY_SIZE(ehl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(ehl_communities); + return ehl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_A, GPP_A }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_G, GPP_G }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_F, GPP_F }, + { PMC_GPD, GPP_GPD }, + { PMC_GPP_E, GPP_E } + }; + + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/elkhartlake/gspi.c b/src/soc/intel/elkhartlake/gspi.c new file mode 100644 index 0000000000..61ad2608db --- /dev/null +++ b/src/soc/intel/elkhartlake/gspi.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return PCH_DEVFN_GSPI0; + case 1: + return PCH_DEVFN_GSPI1; + case 2: + return PCH_DEVFN_GSPI2; + } + return -1; +} diff --git a/src/soc/intel/elkhartlake/i2c.c b/src/soc/intel/elkhartlake/i2c.c new file mode 100644 index 0000000000..c13a1a6099 --- /dev/null +++ b/src/soc/intel/elkhartlake/i2c.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: + return 0; + case PCH_DEVFN_I2C1: + return 1; + case PCH_DEVFN_I2C2: + return 2; + case PCH_DEVFN_I2C3: + return 3; + case PCH_DEVFN_I2C4: + return 4; + case PCH_DEVFN_I2C5: + return 5; + } + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: + return PCH_DEVFN_I2C0; + case 1: + return PCH_DEVFN_I2C1; + case 2: + return PCH_DEVFN_I2C2; + case 3: + return PCH_DEVFN_I2C3; + case 4: + return PCH_DEVFN_I2C4; + case 5: + return PCH_DEVFN_I2C5; + } + return -1; +} diff --git a/src/soc/intel/elkhartlake/include/soc/bootblock.h b/src/soc/intel/elkhartlake/include/soc/bootblock.h new file mode 100644 index 0000000000..2dc50c1ddc --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/bootblock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_BOOTBLOCK_H_ +#define _SOC_ELKHARTLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h new file mode 100644 index 0000000000..6ee34f234c --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/cpu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_CPU_H_ +#define _SOC_ELKHARTLAKE_CPU_H_ + +#include + +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 + +/* Power in units of mW */ +#define C1_POWER 0x3e8 +#define C6_POWER 0x15e +#define C7_POWER 0xc8 +#define C8_POWER 0xc8 +#define C9_POWER 0xc8 +#define C10_POWER 0xc8 + +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h new file mode 100644 index 0000000000..65ee732e9f --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/espi.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_ESPI_H_ +#define _SOC_ELKHARTLAKE_ESPI_H_ + + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/gpe.h b/src/soc/intel/elkhartlake/include/soc/gpe.h new file mode 100644 index 0000000000..34dfcea763 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/gpe.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h new file mode 100644 index 0000000000..6cca742614 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_GPIO_H_ +#define _SOC_ELKHARTLAKE_GPIO_H_ + +#include +#include + +#define CROS_GPIO_NAME "INT34C8" +#define CROS_GPIO_COMM0_NAME "INT34C8:00" +#define CROS_GPIO_COMM1_NAME "INT34C8:01" +#define CROS_GPIO_COMM4_NAME "INT34C8:02" +#define CROS_GPIO_COMM5_NAME "INT34C8:03" + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..0b8d8a74a9 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_GPIO_DEFS_H_ +#define _SOC_ELKHARTLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include +#endif +#include + + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +/* Group GPD */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group R*/ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000000..278c2c63aa --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_ELKHARTLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ + +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_G 0x2 +#define GPP_C 0x3 +#define GPP_R 0x4 +#define GPP_D 0x5 +#define GPP_S 0x6 +#define GPP_H 0x7 +#define GPP_VGPIO 0x8 +#define GPP_F 0x9 +#define GPP_GPD 0xA +#define GPP_E 0xD + +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 +#define SD_PWR_EN_PIN GPP_H1 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group B */ +#define GPIO_RSVD_0 20 +#define GPIO_RSVD_1 21 +#define GPIO_RSVD_2 22 +#define GPIO_RSVD_3 23 +#define GPIO_RSVD_4 24 +#define GPIO_RSVD_5 25 +#define GPIO_RSVD_6 26 +#define GPIO_RSVD_7 27 +#define GPIO_RSVD_8 28 +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GPIO_RSVD_9 53 +#define GPIO_RSVD_10 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define GPIO_RSVD_11 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define GPIO_COM0_START GPP_F0 +#define GPIO_COM0_END GPP_R7 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GPIO_RSVD_12 140 +#define GPIO_RSVD_13 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define GPIO_COM1_START GPP_H0 +#define GPIO_COM1_END GPP_C23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_RSVD_14 206 +#define GPIO_RSVD_15 207 +#define GPIO_RSVD_16 208 +#define GPIO_RSVD_17 209 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPIO_RSVD_17 +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group E */ +#define GPIO_RSVD_18 210 +#define GPIO_RSVD_19 211 +#define GPIO_RSVD_20 212 +#define GPIO_RSVD_21 213 +#define GPIO_RSVD_22 214 +#define GPIO_RSVD_23 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 +#define GPIO_RSVD_28 244 +#define GPIO_RSVD_29 245 +#define GPIO_RSVD_30 246 +#define GPIO_RSVD_31 247 +#define GPIO_RSVD_32 248 +#define GPIO_RSVD_33 249 +#define GPIO_RSVD_34 250 +#define GPIO_RSVD_35 251 +#define GPIO_RSVD_36 252 + +#define GPIO_COM4_START GPIO_RSVD_18 +#define GPIO_COM4_END GPIO_RSVD_36 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define GPIO_COM5_START GPP_G0 +#define GPIO_COM5_END GPP_G7 +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_PADS 261 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_4 3 +#define COMM_5 4 +#define TOTAL_GPIO_COMM 5 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h new file mode 100644 index 0000000000..0246673b03 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/iomap.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_IOMAP_H_ +#define _SOC_ELKHARTLAKE_IOMAP_H_ + +/* + * Memory-mapped I/O registers. + */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x4000000 + +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 + +#define DMI_BASE_ADDRESS 0xfeda0000 +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xfed80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define GFXVT_BASE_ADDRESS 0xfed90000 +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000 +#define VTVC0_BASE_SIZE 0x1000 + +#define REG_BASE_ADDRESS 0xfb000000 +#define REG_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define SPI_BASE_ADDRESS 0xfe010000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +#define VTD_BASE_ADDRESS 0xfed90000 +#define VTD_BASE_SIZE 0x00004000 + +#define MCH_BASE_ADDRESS 0xfec80000 +#define MCH_BASE_SIZE 0x80000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +/* + * I/O port address space + */ +#define SMBUS_BASE_ADDRESS 0x0efa0 +#define SMBUS_BASE_SIZE 0x20 + +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h new file mode 100644 index 0000000000..ac45424476 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/irq.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_EHL_IRQ_H_ +#define _SOC_EHL_IRQ_H_ + +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +/* LPSS Device IRQs */ +#define LPSS_I2C0_IRQ 16 +#define LPSS_I2C1_IRQ 17 +#define LPSS_I2C2_IRQ 18 +#define LPSS_I2C3_IRQ 19 +#define LPSS_I2C4_IRQ 32 +#define LPSS_I2C5_IRQ 33 +#define LPSS_SPI0_IRQ 22 +#define LPSS_SPI1_IRQ 23 +#define LPSS_SPI2_IRQ 24 +#define LPSS_UART0_IRQ 20 +#define LPSS_UART1_IRQ 21 +#define LPSS_UART2_IRQ 34 + +/* PCI shared IRQs */ +#define PCH_IRQ_16 16 +#define PCH_IRQ_17 17 +#define PCH_IRQ_18 18 +#define PCH_IRQ_19 19 +#define PCH_IRQ_20 20 +#define PCH_IRQ_21 21 +#define PCH_IRQ_22 22 +#define PCH_IRQ_23 23 + +#endif /* _EHL_IRQ_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/itss.h b/src/soc/intel/elkhartlake/include/soc/itss.h new file mode 100644 index 0000000000..a550f4c922 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/itss.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_EHL_ITSS_H +#define SOC_INTEL_EHL_ITSS_H + +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + +#define ITSS_MAX_IRQ 119 +#define IRQS_PER_IPC 32 +#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) + +#endif /* SOC_INTEL_EHL_ITSS_H */ diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h new file mode 100644 index 0000000000..d845629e4a --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/me.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ELKHARTLAKE_ME_H_ +#define _ELKHARTLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + uint32_t data; + struct { + uint32_t working_state: 4; + uint32_t mfg_mode: 1; + uint32_t fpt_bad: 1; + uint32_t operation_state: 3; + uint32_t fw_init_complete: 1; + uint32_t ft_bup_ld_flr: 1; + uint32_t update_in_progress: 1; + uint32_t error_code: 4; + uint32_t operation_mode: 4; + uint32_t reset_count: 4; + uint32_t boot_options_present: 1; + uint32_t reserved1: 1; + uint32_t bist_test_state: 1; + uint32_t bist_reset_request: 1; + uint32_t current_power_source: 2; + uint32_t reserved: 1; + uint32_t d0i3_support_valid: 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + uint32_t data; + struct { + uint32_t reserved_0: 4; + uint32_t fw_sku: 3; + uint32_t reserved: 25; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; +#endif /* _ELKHARTLAKE_ME_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h new file mode 100644 index 0000000000..ea4664a150 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/meminit.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_MEMINIT_H_ +#define _SOC_ELKHARTLAKE_MEMINIT_H_ + +#include +#include + +/* Number of dq bits controlled per dqs */ +#define DQ_BITS_PER_DQS 8 + +/* Number of memory packages, where a "package" represents a 64-bit solution */ +#define DDR_NUM_PACKAGES 2 + +/* Number of DQ byte mappings */ +#define DDR_NUM_BYTE_MAPPINGS 6 + +/* Number of memory DIMM slots available on Elkhart Lake */ +#define NUM_DIMM_SLOT 4 + +/* 64-bit Channel identification */ +enum { + DDR_CH0, + DDR_CH1, + DDR_NUM_CHANNELS +}; + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + READ_SPD_CBFS, /* Find SPD file in CBFS. */ + READ_SMBUS, /* Read on-module SPD by SMBUS. */ + READ_SPD_MEMPTR /* Find SPD data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To read on-module SPD when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address[NUM_DIMM_SLOT]; + + /* To identify SPD file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find SPD data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory dq mapping information */ +struct mb_cfg { + + /* + * For each channel, there are 6 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, even though the last 3 sets + * are not used in EHL. + * We let the meminit_dq_dqs_map routine take care of clearing the + * unused fields for the caller. + * Note that dq_map is only used by LPDDR; it does not need to be + * initialized for designs using DDR4. + */ + uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES]; + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + * dqs_map is only used by LPDDR; same comments apply as for dq_map + * above. + */ + uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + uint16_t rcomp_resistor[3]; + + /* + * Rcomp target values. These will typically be the following + * values for Elkhart Lake : { 80, 40, 40, 40, 30 } + */ + uint16_t rcomp_targets[5]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Board type */ + uint8_t UserBd; +}; + +/* + * Initialize default memory configurations for Elkhart Lake. + */ + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated); + +#endif /* _SOC_ELKHARTLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/msr.h b/src/soc/intel/elkhartlake/include/soc/msr.h new file mode 100644 index 0000000000..67e09dcf41 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/msr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_VR_MISC_CONFIG2 0x636 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/nvs.h b/src/soc/intel/elkhartlake/include/soc/nvs.h new file mode 100644 index 0000000000..512945898e --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/nvs.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/p2sb.h b/src/soc/intel/elkhartlake/include/soc/p2sb.h new file mode 100644 index 0000000000..12ae313e3b --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/p2sb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_P2SB_H_ +#define _SOC_ELKHARTLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/pch.h b/src/soc/intel/elkhartlake/include/soc/pch.h new file mode 100644 index 0000000000..7a2d4adead --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/pch.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_PCH_H_ +#define _SOC_ELKHARTLAKE_PCH_H_ + + +#define PCIE_CLK_NOTUSED 0xFF +#define PCIE_CLK_LAN 0x70 +#define PCIE_CLK_FREE 0x80 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..0ae7db80bf --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_PCI_DEVS_H_ +#define _SOC_ELKHARTLAKE_PCI_DEVS_H_ + +#include + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ + +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif + +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) + +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) + +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + +/* PCH Devices */ +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) + +#define PCH_DEV_SLOT_SIO1 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) + +#define PCH_DEV_SLOT_ISH 0x12 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) + +#define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) +#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) + +#define PCH_DEV_SLOT_SATA 0x17 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0) + +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) + +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) + +#define PCH_DEV_SLOT_PCIE 0x1c +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) + +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..c5c5b31ca2 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_ELKHARTLAKE_PCR_H +#define SOC_ELKHARTLAKE_PCR_H +/* + * Port IDs + */ +#define PID_EMMC 0x51 +#define PID_SDX 0x53 + +#define PID_GPIOCOM0 0x6e +#define PID_GPIOCOM1 0x6d +#define PID_GPIOCOM2 0x6c +#define PID_GPIOCOM4 0x6a +#define PID_GPIOCOM5 0x69 + +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_CSME0 0x90 +#define PID_ISCLK 0xad +#define PID_PSF1 0xba +#define PID_PSF2 0xbb +#define PID_PSF3 0xbc +#define PID_PSF4 0xbd +#define PID_SCS 0xc0 +#define PID_RTC 0xc3 +#define PID_ITSS 0xc4 +#define PID_ESPI 0xc7 +#define PID_SERIALIO 0xcb + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h new file mode 100644 index 0000000000..6ebbbfa170 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x40 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include +#include +#include +#include +#include + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h new file mode 100644 index 0000000000..f331961898 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_PMC_H_ +#define _SOC_ELKHARTLAKE_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PWRMBASE 0x10 +#define ABASE 0x40 + +/* Memory mapped IO registers in PMC */ +#define GEN_PMCON_A 0x1020 +#define DC_PP_DIS (1 << 30) +#define DSX_PP_DIS (1 << 29) +#define AG3_PP_EN (1 << 28) +#define SX_PP_EN (1 << 27) +#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26) +#define GBL_RST_STS (1 << 24) +#define DISB (1 << 23) +#define ALLOW_OPI_PLL_SD_INC0 (1 << 22) +#define MEM_SR (1 << 21) +#define ALLOW_SPXB_CG_INC0 (1 << 20) +#define ALLOW_L1LOW_C0 (1 << 19) +#define MS4V (1 << 18) +#define ALLOW_L1LOW_OPI_ON (1 << 17) +#define SUS_PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define PWR_FLR (1 << 14) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) +#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) +#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) +#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) +#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) +#define HOST_RST_STS (1 << 9) +#define ESPI_SMI_LOCK (1 << 8) +#define S4MAW_MASK (3 << 4) +#define S4MAW_1S (1 << 4) +#define S4MAW_2S (2 << 4) +#define S4MAW_3S (3 << 4) +#define S4MAW_4S (0 << 4) +#define S4ASE (1 << 3) +#define PER_SMI_SEL_MASK (3 << 1) +#define SMI_RATE_64S (0 << 1) +#define SMI_RATE_32S (1 << 1) +#define SMI_RATE_16S (2 << 1) +#define SMI_RATE_8S (3 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define GEN_PMCON_B 0x1024 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) +#define PM_DATA_BAR_DIS (1 << 16) +#define WOL_EN_OVRD (1 << 13) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) +#define RTC_BATTERY_DEAD (1 << 2) + +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define SSML 0x104C +#define SSML_SSL_DS (0 << 0) +#define SSML_SSL_EN (1 << 0) + +#define SSMC 0x1050 +#define SSMC_SSMS (1 << 0) + +#define SSMD 0x1054 +#define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 + +#define S3_PWRGATE_POL 0x1828 +#define S3DC_GATE_SUS (1 << 1) +#define S3AC_GATE_SUS (1 << 0) + +#define S4_PWRGATE_POL 0x182c +#define S4DC_GATE_SUS (1 << 1) +#define S4AC_GATE_SUS (1 << 0) + +#define S5_PWRGATE_POL 0x1830 +#define S5DC_GATE_SUS (1 << 15) +#define S5AC_GATE_SUS (1 << 14) + +#define DSX_CFG 0x1834 +#define REQ_CNV_NOWAKE_DSX (1 << 4) +#define REQ_BATLOW_DSX (1 << 3) +#define DSX_EN_WAKE_PIN (1 << 2) +#define DSX_DIS_AC_PRESENT_PD (1 << 1) +#define DSX_EN_LAN_WAKE_PIN (1 << 0) +#define DSX_CFG_MASK (0x1f << 0) + +#define PMSYNC_TPR_CFG 0x18C4 +#define PCH2CPU_TPR_CFG_LOCK (1 << 31) +#define PCH2CPU_TT_EN (1 << 26) + +#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) + +#define PMC_GPP_B 0x0 +#define PMC_GPP_T 0x1 +#define PMC_GPP_D 0x2 +#define PMC_GPP_A 0x3 +#define PMC_GPP_R 0x4 +#define PMC_GPP_V 0x5 +#define PMC_GPD 0x6 +#define PMC_GPP_H 0x7 +#define PMC_GPP_U 0x8 +#define PMC_VGPIO 0x9 +#define PMC_GPP_F 0xA +#define PMC_GPP_C 0xB +#define PMC_GPP_E 0xC +#define PMC_GPP_G 0xD +#define PMC_GPP_S 0xE + +#define GBLRST_CAUSE0 0x1924 +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) +#define GBLRST_CAUSE1 0x1928 + +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + +#define IRQ_REG ACTL +#define SCI_IRQ_ADJUST 0 +#define ACTL 0x1BD8 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) + +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/ramstage.h b/src/soc/intel/elkhartlake/include/soc/ramstage.h new file mode 100644 index 0000000000..8188fbdb84 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/ramstage.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void soc_init_pre_device(void *chip_info); + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/romstage.h b/src/soc/intel/elkhartlake/include/soc/romstage.h new file mode 100644 index 0000000000..3772db4bc1 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/romstage.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void romstage_pch_init(void); + +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/serialio.h b/src/soc/intel/elkhartlake/include/soc/serialio.h new file mode 100644 index 0000000000..e42af5f781 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/serialio.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; + +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, +}; + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/smbus.h b/src/soc/intel/elkhartlake/include/soc/smbus.h new file mode 100644 index 0000000000..0ea469c8c9 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/smbus.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_SMBUS_H_ +#define _SOC_ELKHARTLAKE_SMBUS_H_ + +/* IO and MMIO registers under primary BAR */ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/soc_chip.h b/src/soc/intel/elkhartlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..6fccc64b53 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_SOC_CHIP_H_ +#define _SOC_ELKHARTLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_ELKHARTLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/systemagent.h b/src/soc/intel/elkhartlake/include/soc/systemagent.h new file mode 100644 index 0000000000..0abfbfcb07 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/systemagent.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_ELKHARTLAKE_SYSTEMAGENT_H +#define SOC_ELKHARTLAKE_SYSTEMAGENT_H + +#include + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 +#define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 +#define REGBAR 0x5420 +#define VTBAR_ENABLED 0x01 +#define VTBAR_MASK 0x7ffffff000ull + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +static const struct sa_mmio_descriptor soc_vtd_resources[] = { + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +}; + +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +#endif diff --git a/src/soc/intel/elkhartlake/include/soc/usb.h b/src/soc/intel/elkhartlake/include/soc/usb.h new file mode 100644 index 0000000000..247b0ba554 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/usb.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include + +/* Per Port HS Transmitter Emphasis */ +#define USB2_EMP_OFF 0 +#define USB2_DE_EMP_ON 1 +#define USB2_PRE_EMP_ON 2 +#define USB2_DE_EMP_ON_PRE_EMP_ON 3 + +/* Per Port Half Bit Pre-emphasis */ +#define USB2_FULL_BIT_PRE_EMP 0 +#define USB2_HALF_BIT_PRE_EMP 1 + +/* Per Port HS Preemphasis Bias */ +#define USB2_BIAS_0MV 0 +#define USB2_BIAS_11P25MV 1 +#define USB2_BIAS_16P9MV 2 +#define USB2_BIAS_28P15MV 3 +#define USB2_BIAS_39P35MV 5 +#define USB2_BIAS_45MV 6 +#define USB2_BIAS_56P3MV 7 + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +/* USB Overcurrent pins definition */ +enum { + OC0 = 0, + OC1, + OC2, + OC3, + OC4, + OC5, + OC6, + OC7, + OCMAX, + OC_SKIP = 0xff, /* Skip OC programming */ +}; + +/* Standard USB Port based on length: + * - External + * - Back Panel + * - OTG + * - M.2 + * - Internal device down */ + +#define USB2_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_EMP_OFF, \ + .pre_emp_bias = USB2_BIAS_0MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 11.5"-12" */ +#define USB2_PORT_LONG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 6"-11.49" */ +#define USB2_PORT_MID(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Length = 3"-5.99" */ +#define USB2_PORT_SHORT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_39P35MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_39P35MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + +/* Max TX and Pre-emp settings */ +#define USB2_PORT_MAX(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_56P3MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +/* Type-C Port, no BC1.2 charge detect module / MUX + * Length = 3.0" - 9.00" */ +#define USB2_PORT_TYPE_C(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_56P3MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ +} + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#define USB3_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ + .tx_de_emp = 0x00, \ + .tx_downscale_amp = 0x00, \ +} + +#define USB3_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_de_emp = 0x0, \ + .tx_downscale_amp = 0x00, \ +} + +#endif diff --git a/src/soc/intel/elkhartlake/lockdown.c b/src/soc/intel/elkhartlake/lockdown.c new file mode 100644 index 0000000000..b2d4210531 --- /dev/null +++ b/src/soc/intel/elkhartlake/lockdown.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void pmc_lock_pmsync(void) +{ + uint8_t *pmcbase; + uint32_t pmsyncreg; + + pmcbase = pmc_mmio_regs(); + + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); +} + +static void pmc_lock_abase(void) +{ + uint8_t *pmcbase; + uint32_t reg32; + + pmcbase = pmc_mmio_regs(); + + reg32 = read32(pmcbase + GEN_PMCON_B); + reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + write32(pmcbase + GEN_PMCON_B, reg32); +} + +static void pmc_lock_smi(void) +{ + uint8_t *pmcbase; + uint8_t reg8; + + pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_B); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_B, reg8); +} + +static void pmc_lockdown_cfg(int chipset_lockdown) +{ + /* PMSYNC */ + pmc_lock_pmsync(); + /* Lock down ABASE and sleep stretching policy */ + pmc_lock_abase(); + + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) + pmc_lock_smi(); +} + +void soc_lockdown_config(int chipset_lockdown) +{ + /* PMC lock down configuration */ + pmc_lockdown_cfg(chipset_lockdown); +} diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c new file mode 100644 index 0000000000..d00702eef5 --- /dev/null +++ b/src/soc/intel/elkhartlake/me.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void dump_me_status(void *unused) +{ + union me_hfsts1 hfsts1; + union me_hfsts2 hfsts2; + union me_hfsts3 hfsts3; + union me_hfsts4 hfsts4; + union me_hfsts5 hfsts5; + union me_hfsts6 hfsts6; + + if (!is_cse_enabled()) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + hfsts2.data = me_read_config32(PCI_ME_HFSTS2); + hfsts3.data = me_read_config32(PCI_ME_HFSTS3); + hfsts4.data = me_read_config32(PCI_ME_HFSTS4); + hfsts5.data = me_read_config32(PCI_ME_HFSTS5); + hfsts6.data = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", hfsts1.data); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", hfsts2.data); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", hfsts3.data); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", hfsts4.data); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c new file mode 100644 index 0000000000..cd777ba3a0 --- /dev/null +++ b/src/soc/intel/elkhartlake/meminit.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd_info->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr, + size_t *spd_data_len) +{ + if (spd_info->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd_info->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + bool half_populated) +{ + memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, + sizeof(mem_cfg->RcompResistor)); + + memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, + sizeof(mem_cfg->RcompTarget)); + + memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], + sizeof(board_cfg->dq_map[DDR_CH0])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], + sizeof(board_cfg->dqs_map[DDR_CH0])); + + if (half_populated) + return; + + memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], + sizeof(board_cfg->dq_map[DDR_CH1])); + + memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], + sizeof(board_cfg->dqs_map[DDR_CH1])); +} + +static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + uintptr_t spd_data_ptr, bool half_populated) +{ + /* Channel 0 */ + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + spd_data_ptr = 0; + } + + /* Channel 1 */ + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, + const struct spd_info *spd_info, bool half_populated) +{ + + if (spd_info->read_type == READ_SMBUS) { + for (int i = 0; i < NUM_DIMM_SLOT; i++) + mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); + } else { + uintptr_t spd_data_ptr = 0; + size_t spd_data_len = 0; + memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); + get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); + } + + /* Early Command Training Enabled */ + mem_cfg->ECT = board_cfg->ect; + + mem_cfg->UserBd = board_cfg->UserBd; +} diff --git a/src/soc/intel/elkhartlake/p2sb.c b/src/soc/intel/elkhartlake/p2sb.c new file mode 100644 index 0000000000..0ddd007920 --- /dev/null +++ b/src/soc/intel/elkhartlake/p2sb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ + uint32_t mask; + + if (count != P2SB_EP_MASK_MAX_REG) { + printk(BIOS_ERR, "Unable to program EPMASK registers\n"); + return; + } + + /* Remove the host accessing right to PSF register range. + * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable sideband + * access for PCI Root Bridge. + */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + + ep_mask[P2SB_EP_MASK_5_REG] = mask; + + /* + * Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband + * access for Broadcast and Multicast. + */ + mask = (1 << 31) | (1 << 30); + + ep_mask[P2SB_EP_MASK_7_REG] = mask; +} diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c new file mode 100644 index 0000000000..57f26d921c --- /dev/null +++ b/src/soc/intel/elkhartlake/pmc.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + GEN_PMCON_A); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); +} + +static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + printk(BIOS_DEBUG, "%sabling Deep S%c\n", + enable ? "En" : "Dis", sx + '0'); + reg = read32(pmcbase + offset); + if (enable) + reg |= mask; + else + reg &= ~mask; + write32(pmcbase + offset, reg); +} + +static void config_deep_s5(int on_ac, int on_dc) +{ + /* Treat S4 the same as S5. */ + config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); + config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); + config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); + config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); +} + +static void config_deep_s3(int on_ac, int on_dc) +{ + config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); + config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); +} + +static void config_deep_sx(uint32_t deepsx_config) +{ + uint32_t reg; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg = read32(pmcbase + DSX_CFG); + reg &= ~DSX_CFG_MASK; + reg |= deepsx_config; + write32(pmcbase + DSX_CFG, reg); +} + +static void pmc_init(struct device *dev) +{ + const config_t *config = config_of_soc(); + + rtc_init(); + + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); + config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); + config_deep_sx(config->deep_sx_config); +} + +static void soc_pmc_read_resources(struct device *dev) +{ + struct resource *res; + + mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + + res = new_resource(dev, 1); + res->base = (resource_t)ACPI_BASE_ADDRESS; + res->size = (resource_t)ACPI_BASE_SIZE; + res->limit = res->base + res->size + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_acpi_mode_init(struct device *dev) +{ + /* + * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order + * to ensure the ordering does not break the assumptions that other + * drivers make about ACPI mode (e.g. Chrome EC). Since it disables + * ACPI mode, other drivers may take different actions based on this + * (e.g. Chrome EC will flush any pending hostevent bits). Because + * EHL has its PMC device available for device_operations, it can be + * done from the "ops->init" callback. + */ + pmc_set_acpi_mode(); +} + +struct device_operations pmc_ops = { + .read_resources = soc_pmc_read_resources, + .set_resources = noop_set_resources, + .init = soc_acpi_mode_init, + .enable = pmc_init, +}; diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c new file mode 100644 index 0000000000..4d5c04d02d --- /dev/null +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + uint8_t disb_val; + /* Only care about bits [23:16] of register GEN_PMCON_A */ + uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); + + disb_val = read8(addr); + disb_val |= (DISB >> 16); + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); + write8(addr, disb_val); +} + +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + +/* + * PMC controller gets hidden from PCI bus + * during FSP-Silicon init call. Hence PWRMBASE + * can't be accessible using PCI configuration space + * read/write. + */ +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_elkhartlake_config *config; + + config = config_of_soc(); + + /* Assign to out variable */ + *dw0 = config->pmc_gpe0_dw0; + *dw1 = config->pmc_gpe0_dw1; + *dw2 = config->pmc_gpe0_dw2; +} + +static int rtc_failed(uint32_t gen_pmcon_b) +{ + return !!(gen_pmcon_b & RTC_BATTERY_DEAD); +} + +int soc_get_rtc_failed(void) +{ + const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (!ps) { + printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + return 1; + } + + return rtc_failed(ps->gen_pmcon_b); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_a & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c new file mode 100644 index 0000000000..fe3d7690b5 --- /dev/null +++ b/src/soc/intel/elkhartlake/reset.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void do_global_reset(void) +{ + /* Ask CSE to do the global reset */ + if (cse_request_global_reset()) + return; + + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + do_full_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + global_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/elkhartlake/romstage/Makefile.inc b/src/soc/intel/elkhartlake/romstage/Makefile.inc new file mode 100644 index 0000000000..a1a6c6638d --- /dev/null +++ b/src/soc/intel/elkhartlake/romstage/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c new file mode 100644 index 0000000000..3961dfc167 --- /dev/null +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_elkhartlake_config *config) +{ + /* TODO: Update with UPD details as FSP matures */ +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const struct soc_intel_elkhartlake_config *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + mainboard_memory_init_params(mupd); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* TODO: Update later together with UPD updates */ +} diff --git a/src/soc/intel/elkhartlake/romstage/pch.c b/src/soc/intel/elkhartlake/romstage/pch.c new file mode 100644 index 0000000000..d3c2554425 --- /dev/null +++ b/src/soc/intel/elkhartlake/romstage/pch.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void romstage_pch_init(void) +{ + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c new file mode 100644 index 0000000000..ae9cc4afe6 --- /dev/null +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len = 0; + bool is_dram_part_overridden = false; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (meminfo_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num = strlen(dram_part_num); + is_dram_part_overridden = true; + } + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; + channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != 2) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; + dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!is_dram_part_overridden) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + u8 memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + romstage_pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/elkhartlake/romstage/systemagent.c b/src/soc/intel/elkhartlake/romstage/systemagent.c new file mode 100644 index 0000000000..6e9b9fa486 --- /dev/null +++ b/src/soc/intel/elkhartlake/romstage/systemagent.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} diff --git a/src/soc/intel/elkhartlake/sd.c b/src/soc/intel/elkhartlake/sd.c new file mode 100644 index 0000000000..a4b89c5803 --- /dev/null +++ b/src/soc/intel/elkhartlake/sd.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev) +{ + config_t *config = config_of(dev); + + if (!config->sdcard_cd_gpio) + return -1; + + gpio->type = ACPI_GPIO_TYPE_INTERRUPT; + gpio->pull = ACPI_GPIO_PULL_NONE; + gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio->irq.shared = ACPI_IRQ_SHARED; + gpio->irq.wake = ACPI_IRQ_WAKE; + gpio->interrupt_debounce_timeout = 10000; /* 100ms */ + gpio->pin_count = 1; + gpio->pins[0] = config->sdcard_cd_gpio; + + return 0; +} diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c new file mode 100644 index 0000000000..7d2a15e737 --- /dev/null +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from MCC chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + const struct soc_intel_elkhartlake_config *config; + + config = config_of_soc(); + + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + heci_disable(); +} + +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPE0_STS_BIT] = smihandler_southbridge_gpe0, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, + [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) + [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, + [MONITOR_STS_BIT] = smihandler_southbridge_monitor, +}; diff --git a/src/soc/intel/elkhartlake/smmrelocate.c b/src/soc/intel/elkhartlake/smmrelocate.c new file mode 100644 index 0000000000..11b631bb86 --- /dev/null +++ b/src/soc/intel/elkhartlake/smmrelocate.c @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", + smbase, iedbase); + + /* + * All threads need to set IEDBASE and SMBASE to the relocated + * handler region. However, the save state location depends on the + * smm_save_state_in_msrs field in the relocation parameters. If + * smm_save_state_in_msrs is non-zero then the CPUs are relocating + * the SMM handler in parallel, and each CPUs save state area is + * located in their respective MSR space. If smm_save_state_in_msrs + * is zero then the SMM relocation is happening serially so the + * save state is at the same default location for all CPUs. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smbase_msr; + msr_t iedbase_msr; + + smbase_msr.lo = smbase; + smbase_msr.hi = 0; + + /* + * According the BWG the IEDBASE MSR is in bits 63:32. It's + * not clear why it differs from the SMBASE MSR. + */ + iedbase_msr.lo = 0; + iedbase_msr.hi = iedbase; + + wrmsr(SMBASE_MSR, smbase_msr); + wrmsr(IEDBASE_MSR, iedbase_msr); + } else { + em64t101_smm_state_save_area_t *save_state; + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - + sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; + } +} + +/* Returns 1 if SMM MSR save state was set. */ +static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) +{ + msr_t smm_mca_cap; + + smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.hi = 0; + smm_feature_control.lo |= SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + relo_params->smm_save_state_in_msrs = 1; + } + return relo_params->smm_save_state_in_msrs; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); + + /* + * Determine if the processor supports saving state in MSRs. If so, + * enable it before the non-BSPs run so that SMM relocation can occur + * in parallel in the non-BSP CPUs. + */ + if (cpu == 0) { + /* + * If smm_save_state_in_msrs is 1 then that means this is the + * 2nd time through the relocation handler for the BSP. + * Parallel SMM handler relocation is taking place. However, + * it is desired to access other CPUs save state in the real + * SMM handler. Therefore, disable the SMM save state in MSRs + * feature. + */ + if (relo_params->smm_save_state_in_msrs) { + msr_t smm_feature_control; + + smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; + wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); + } else if (bsp_setup_msr_save_state(relo_params)) + /* + * Just return from relocation handler if MSR save + * state is enabled. In that case the BSP will come + * back into the relocation handler to setup the new + * SMBASE as well disabling SMM save state in MSRs. + */ + return; + } + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~(4 * KiB - 1); + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + + /* + * Run the relocation handler for on the BSP to check and set up + * parallel SMM relocation. + */ + smm_initiate_relocation(); + + if (smm_reloc_params.smm_save_state_in_msrs) + printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); +} + +void smm_relocate(void) +{ + /* + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation + * shall take place. Run the relocation handler a second time on the + * BSP to do * the final move. For APs, a relocation handler always + * needs to be run. + */ + if (smm_reloc_params.smm_save_state_in_msrs) + smm_initiate_relocation_parallel(); + else if (!boot_cpu()) + smm_initiate_relocation(); +} diff --git a/src/soc/intel/elkhartlake/spi.c b/src/soc/intel/elkhartlake/spi.c new file mode 100644 index 0000000000..8fd3126dee --- /dev/null +++ b/src/soc/intel/elkhartlake/spi.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + case PCH_DEVFN_GSPI0: + return 1; + case PCH_DEVFN_GSPI1: + return 2; + case PCH_DEVFN_GSPI2: + return 3; + } + return -1; +} diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c new file mode 100644 index 0000000000..73f7963b3f --- /dev/null +++ b/src/soc/intel/elkhartlake/systemagent.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Memory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); + + /* Add Vt-d resources if VT-d is enabled */ + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + ARRAY_SIZE(soc_vtd_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + struct soc_power_limits_config *soc_config; + config_t *config; + + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); + + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); +} diff --git a/src/soc/intel/elkhartlake/uart.c b/src/soc/intel/elkhartlake/uart.c new file mode 100644 index 0000000000..cc0e3a848b --- /dev/null +++ b/src/soc/intel/elkhartlake/uart.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct uart_gpio_pad_config uart_gpio_pads[] = { + { + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + }, + }, + { + .console_index = 1, + .gpios = { + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ + }, + }, + { + .console_index = 2, + .gpios = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + }, + } +}; + +const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); + +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) +{ + /* + * if index is valid, this function will return corresponding structure + * for uart console else will return NULL. + */ + switch (uart_console) { + case 0: + return pcidev_path_on_root(PCH_DEVFN_UART0); + case 1: + return pcidev_path_on_root(PCH_DEVFN_UART1); + case 2: + return pcidev_path_on_root(PCH_DEVFN_UART2); + default: + printk(BIOS_ERR, "Invalid UART console index\n"); + return NULL; + } +} diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index f58aa3354e..0343263256 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -8,11 +8,7 @@ if SOC_INTEL_ICELAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE @@ -33,8 +29,8 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE @@ -53,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -62,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select USE_CAR_NEM_ENHANCED_V1 config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ece28ccc35..ff66300da5 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -163,7 +163,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 43aa83c732..6a8f824929 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include - Device (GPIO) { Name (_HID, "INT3455") @@ -26,32 +26,32 @@ Device (GPIO) /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE /* GPIO Community 2 */ CreateDWordField (^RBUF, ^COM2._BAS, BAS2) CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - Store (^^PCRB (PID_GPIOCOM2), BAS2) - Store (GPIO_BASE_SIZE, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - Store (^^PCRB (PID_GPIOCOM4), BAS4) - Store (GPIO_BASE_SIZE, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE /* GPIO Community 5 */ CreateDWordField (^RBUF, ^COM5._BAS, BAS5) CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - Store (^^PCRB (PID_GPIOCOM5), BAS5) - Store (GPIO_BASE_SIZE, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE Return (RBUF) } @@ -69,52 +69,37 @@ Device (GPIO) Method (GADD, 1, NotSerialized) { /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_A23))) + If ((Arg0 >= GPP_G0) && (Arg0 <= GPP_A23)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_G0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_H0), LLessEqual (Arg0, GPP_F19))) + If ((Arg0 >= GPP_H0) && (Arg0 <= GPP_F19)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_D0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_H0 } /* GPIO Community 2 */ - If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11))) + If ((Arg0 >= GPD0) && (Arg0 <= GPD11)) { - Store (PID_GPIOCOM2, Local0) - Subtract (Arg0, GPD0, Local1) + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 } /* GPIO Community 4 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) + If ((Arg0 >= GPP_C0) && (Arg0 <= GPP_E23)) { - Store (PID_GPIOCOM4, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_C0 } - /* GPIO Community 05*/ - If (LAnd (LGreaterEqual (Arg0, GPP_R0), LLessEqual (Arg0, GPP_S7))) + /* GPIO Community 5 */ + If ((Arg0 >= GPP_R0) && (Arg0 <= GPP_S7)) { - Store (PID_GPIOCOM5, Local0) - Subtract (Arg0, GPP_R0, Local1) + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPP_R0 } - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 16))) -} -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) - - Return (Local0) + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 16)) } diff --git a/src/soc/intel/icelake/acpi/pch_glan.asl b/src/soc/intel/icelake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7ac80..0000000000 --- a/src/soc/intel/icelake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/icelake/acpi/platform.asl b/src/soc/intel/icelake/acpi/platform.asl deleted file mode 100644 index 73458641fa..0000000000 --- a/src/soc/intel/icelake/acpi/platform.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Enable ACPI _SWS methods */ -#include -/* Generic indicator for sleep state */ -#include - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} diff --git a/src/soc/intel/icelake/acpi/smbus.asl b/src/soc/intel/icelake/acpi/smbus.asl deleted file mode 100644 index 7860f606c9..0000000000 --- a/src/soc/intel/icelake/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.4 - -Device (SBUS) -{ - Name (_ADR, 0x001f0004) -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 474c6cc922..129a88da8c 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include + /* ESPI 0:1f.0 */ #include @@ -30,7 +33,7 @@ #include "serialio.asl" /* SMBus 0:1f.4 */ -#include "smbus.asl" +#include /* USB XHCI 0:14.0 */ #include "xhci.asl" @@ -38,5 +41,5 @@ /* PCI _OSC */ #include -/* GBe 0:1f.6 */ -#include "pch_glan.asl" +/* GbE 0:1f.6 */ +#include diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 6ebf9101b3..f36bd31e3b 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -40,26 +40,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index f001e3b72c..898b0e3b28 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -12,8 +13,6 @@ #include #include -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -83,7 +82,6 @@ static void report_cpu_info(void) const char cpu_not_found[] = "Platform info not available"; const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13]; @@ -108,11 +106,7 @@ static void report_cpu_info(void) cpu_name++; } - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -124,7 +118,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index a455bfce71..d0ea732df3 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -75,8 +75,6 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 2b190cd5df..386e77520a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -83,7 +82,6 @@ struct soc_intel_icelake_config { SaGv_Enabled, } SaGv; - /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 45c81cade7..2823fd7c4e 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -221,9 +221,6 @@ static void post_mp_init(void) * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 586dbfdd24..235dc6e3cf 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -17,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1497c8d8e4..7f9ff2fee2 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,108 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -201,8 +99,8 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cbafb7..363f579b0f 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -40,10 +41,7 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -69,19 +67,12 @@ static void pch_finalize(void) * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pch_handle_sideband(config); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 458fbae886..184b9d6bf6 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -64,17 +64,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) - params->Usb2OverCurrentPin[i] = 0; - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) - params->Usb3OverCurrentPin[i] = 0; - - /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - /* TODO: Remove me as SkipMpInit is getting deprecated */ - params->SkipMpInit = 0; + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); mainboard_silicon_init_params(params); @@ -84,6 +76,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PeiGraphicsPeimInit = 0; + params->PavpEnable = CONFIG(PAVP); + /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; @@ -126,8 +120,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; @@ -136,8 +130,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = @@ -146,11 +138,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index 404bd0f041..09de609a8a 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -49,14 +49,12 @@ static const struct pad_group icl_community2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */ }; - static const struct pad_group icl_community4_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */ INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8), }; - static const struct pad_group icl_community5_groups[] = { INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */ INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */ diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 31f83d6ad3..577ca5f427 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -8,7 +8,6 @@ #endif #include - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ @@ -258,6 +257,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 #endif diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index 75b0589c5a..62407dff36 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -167,7 +167,6 @@ #define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1) - /* Group GPD */ #define GPD0 123 #define GPD1 124 @@ -184,7 +183,6 @@ #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - /* Group C */ #define GPP_C0 135 #define GPP_C1 136 diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index cbba2b43ef..c4006eff24 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -3,7 +3,6 @@ #ifndef _SOC_ICELAKE_PCH_H_ #define _SOC_ICELAKE_PCH_H_ - #define PCH_H 1 #define PCH_LP 2 #define PCH_UNKNOWN_SERIES 0xFF diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 961207c871..26dae7e58d 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26) #define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 90465a248b..ef648a66b3 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 diff --git a/src/soc/intel/icelake/include/soc/usb.h b/src/soc/intel/icelake/include/soc/usb.h index 247b0ba554..69d2d31a4c 100644 --- a/src/soc/intel/icelake/include/soc/usb.h +++ b/src/soc/intel/icelake/include/soc/usb.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_USB_H_ #define _SOC_USB_H_ diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index d37ff5407a..1f7ea3c180 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -11,7 +11,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) + if (cse_request_global_reset()) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index e944c76985..0801da23bf 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -45,7 +45,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index f1a7033498..bbdcb68b10 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -17,8 +17,6 @@ #include #include #include -#include - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -234,15 +232,3 @@ void smm_relocate(void) else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 89bbdd3614..2da4284ba1 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -8,11 +8,7 @@ if SOC_INTEL_JASPERLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON @@ -32,12 +28,11 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_1 + select PLATFORM_USES_FSP2_2 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON_SMM + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK @@ -60,7 +55,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC - select UDK_2017_BINDING + select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM @@ -210,5 +205,5 @@ config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0xe00 + default 0x1400 endif diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 9d5080b681..8673da17ea 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -164,10 +165,10 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -187,7 +188,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -200,7 +201,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; - if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index f8b180df11..421abc3a21 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include -#include "gpio_op.asl" #include @@ -18,7 +18,6 @@ Device (GPIO) { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM2) Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -39,12 +38,6 @@ Device (GPIO) BAS1 = ^^PCRB (PID_GPIOCOM1) LEN1 = GPIO_BASE_SIZE - /* GPIO Community 2 */ - CreateDWordField (^RBUF, ^COM2._BAS, BAS2) - CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - BAS2 = ^^PCRB (PID_GPIOCOM2) - LEN2 = GPIO_BASE_SIZE - /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl deleted file mode 100644 index 683686f3ca..0000000000 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT) - - Return (Local0) -} - -/* - * Get GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (GTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = PAD_CFG0_TX_STATE & VAL0 - - Return (Local0) -} - -/* - * Set GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (STXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 = PAD_CFG0_TX_STATE | VAL0 -} - -/* - * Clear GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (CTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 = ~PAD_CFG0_TX_STATE & VAL0 -} - -/* - * Set Pad mode - * Arg0 - GPIO Number - * Arg1 - Pad mode - * 0 = GPIO control pad - * 1 = Native Function 1 - * 2 = Native Function 2 - * 3 = Native Function 3 - */ -Method (GPMO, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = VAL0 - Local0 = ~PAD_CFG0_MODE_MASK & Local0 - Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK - VAL0 = Local0 | Arg1 -} - -/* - * Enable/Disable Tx buffer - * Arg0 - GPIO Number - * Arg1 - TxBuffer state - * 0 = Disable Tx Buffer - * 1 = Enable Tx Buffer - */ -Method (GTXE, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - - If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 - } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_TX_DISABLE | VAL0 - } -} - -/* - * Enable/Disable Rx buffer - * Arg0 - GPIO Number - * Arg1 - RxBuffer state - * 0 = Disable Rx Buffer - * 1 = Enable Rx Buffer - */ -Method (GRXE, 2, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - - If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 - } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_RX_DISABLE | VAL0 - } -} diff --git a/src/soc/intel/jasperlake/acpi/ipu.asl b/src/soc/intel/jasperlake/acpi/ipu.asl deleted file mode 100644 index b6d8e8fe01..0000000000 --- a/src/soc/intel/jasperlake/acpi/ipu.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) - Name (_DDN, "Camera and Imaging Subsystem") - } -} diff --git a/src/soc/intel/jasperlake/acpi/ish.asl b/src/soc/intel/jasperlake/acpi/ish.asl deleted file mode 100644 index 5c8b130315..0000000000 --- a/src/soc/intel/jasperlake/acpi/ish.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Integrated Sensor Hub Controller 0:12.0 */ - -Device (ISHB) -{ - Name (_ADR, 0x00120000) - Name (_DDN, "Integrated Sensor Hub Controller") -} diff --git a/src/soc/intel/jasperlake/acpi/pch_glan.asl b/src/soc/intel/jasperlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7ac80..0000000000 --- a/src/soc/intel/jasperlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index 508fb9bd41..b58608feed 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -71,6 +71,7 @@ Scope (\_SB.PCI0) { Name (_ADR, 0x00140005) Name (_DDN, "SD Controller") Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) OperationRegion (SDPC, PCI_Config, 0x00, 0x100) Field (SDPC, WordAcc, NoLock, Preserve) @@ -82,6 +83,65 @@ Scope (\_SB.PCI0) { PGEN, 1, /* PG_ENABLE */ } + /* + * _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (Arg0 == DSUU) { + /* Check the revision */ + If (Arg1 >= 0) { + /* + * Function Index 0 the return value is a buffer containing + * one bit for each function index, starting with zero. + * Bit 0 - Indicates whether there is support for any + * functions other than function 0. + * Bit 1 - Indicates support to clear power control register + * Bit 2 - Indicates support to set power control register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + /* + * For SD we have to support functions to + * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] + */ + If (Arg2 == 0) { + Return (Buffer () { 0x19 }) + } + /* + * Function Index 3: Set 1.8v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 3) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + /* + * Function Index 4: Set 3.3v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + If (Arg2 == 4) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + } + } + Return(Buffer() { 0x0 }) + } + Method(_INI) { /* Clear register 0x1C20/0x4820 */ @@ -98,6 +158,9 @@ Scope (\_SB.PCI0) { /* Set Power State to D0 */ PMCR = PMCR & 0xFFFC TEMP = PMCR + + /* Change pad mode to Native */ + GPMO(SD_PWR_EN_PIN, 0x1) } Method (_PS3, 0, Serialized) @@ -107,6 +170,15 @@ Scope (\_SB.PCI0) { /* Set Power State to D3 */ PMCR = PMCR | 0x0003 TEMP = PMCR + + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Enable Tx Buffer */ + GTXE(SD_PWR_EN_PIN, 0x1) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) } Device (CARD) diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 48411e4407..b82cce50ab 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include + /* ESPI 0:1f.0 */ #include @@ -33,10 +36,10 @@ #include "serialio.asl" /* SMBus 0:1f.4 */ -#include "smbus.asl" +#include /* ISH 0:12.0 */ -#include "ish.asl" +#include /* USB XHCI 0:14.0 */ #include "xhci.asl" @@ -49,3 +52,6 @@ /* EMMC/SD card */ #include "scs.asl" + +/* GbE 0:1f.6 */ +#include diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 54ad85a82e..96e6268f74 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -24,5 +25,8 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index f73c57b65e..f59d9c909f 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -44,26 +44,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) @@ -142,7 +136,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 4f667aa0dc..beab7822c8 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -3,7 +3,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -12,8 +14,6 @@ #include #include -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -29,6 +29,7 @@ static struct { { PCI_DEVICE_ID_INTEL_JSL_ID_2, "Jasperlake SKU4-2" }, { PCI_DEVICE_ID_INTEL_JSL_ID_3, "Jasperlake SKU2-1" }, { PCI_DEVICE_ID_INTEL_JSL_ID_4, "Jasperlake SKU2-2" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_5, "Jasperlake SKU4-3" }, }; static struct { @@ -44,6 +45,8 @@ static struct { } igd_table[] = { { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, + { PCI_DEVICE_ID_INTEL_JSL_GT3, "Jasperlake GT3" }, + { PCI_DEVICE_ID_INTEL_JSL_GT4, "Jasperlake GT4" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) @@ -58,41 +61,14 @@ static inline uint16_t get_dev_id(pci_devfn_t dev) static void report_cpu_info(void) { - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - const char cpu_not_found[] = "Platform info not available"; - const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; - u32 p[13]; - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax >= 0x80000004) { - int j = 0; - - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - p[j++] = cpuidr.eax; - p[j++] = cpuidr.ebx; - p[j++] = cpuidr.ecx; - p[j++] = cpuidr.edx; - } - p[12] = 0; - cpu_name = (char *)p; - - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) - cpu_name++; - } - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); + fill_processor_name(cpu_name); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -104,7 +80,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 044045196b..d34ef557df 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,11 @@ #include #include +static const struct pcie_rp_group pch_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -89,8 +95,6 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI3: return "SPI3"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_GBE: return "GLAN"; @@ -132,6 +136,9 @@ void soc_init_pre_device(void *chip_info) itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); soc_fill_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + pcie_rp_update_devicetree(pch_rp_groups); } static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index d8ea560dfa..4410de9310 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -9,8 +9,6 @@ #include #include #include -#include -#include #include #include #include @@ -62,16 +60,15 @@ struct soc_intel_jasperlake_config { /* TCC activation offset */ uint32_t tcc_offset; - /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. - * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, - * 4:FixedPoint3, 5:Enabled */ + /* System Agent dynamic frequency support. + * When enabled memory will be training at different frequencies. + * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 + * (high), 4:Enabled */ enum { SaGv_Disabled, SaGv_FixedPoint0, SaGv_FixedPoint1, SaGv_FixedPoint2, - SaGv_FixedPoint3, SaGv_Enabled, } SaGv; @@ -138,13 +135,16 @@ struct soc_intel_jasperlake_config { /* Heci related */ uint8_t Heci3Enabled; + /* VR Config Settings for IA Core */ + uint16_t ImonSlope; + uint16_t ImonOffset; + /* Gfx related */ uint8_t IgdDvmt50PreAlloc; uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; - uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ @@ -284,6 +284,66 @@ struct soc_intel_jasperlake_config { */ uint8_t cpu_ratio_override; + /* Skip CPU replacement check + * 0: disable + * 1: enable + * Setting this option to skip CPU replacement check to avoid the forced MRC training + * for the platforms with soldered down SOC. + */ + uint8_t SkipCpuReplacementCheck; + + /* + * SLP_S3 Minimum Assertion Width Policy + * 1 = 60us + * 2 = 1ms + * 3 = 50ms (default) + * 4 = 2s + */ + uint8_t PchPmSlpS3MinAssert; + + /* + * SLP_S4 Minimum Assertion Width Policy + * 1 = 1s (default) + * 2 = 2s + * 3 = 3s + * 4 = 4s + */ + uint8_t PchPmSlpS4MinAssert; + + /* + * SLP_SUS Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 500ms + * 3 = 1s + * 4 = 4s (default) + */ + uint8_t PchPmSlpSusMinAssert; + + /* + * SLP_A Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 4s + * 3 = 98ms + * 4 = 2s (default) + */ + uint8_t PchPmSlpAMinAssert; + + /* + * PCH PM Reset Power Cycle Duration + * 0 = 4s (default) + * 1 = 1s + * 2 = 2s + * 3 = 3s + * 4 = 4s + * + * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the + * stretch duration programmed in the following registers: + * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + * - PM_CFG.SLP_LAN_MIN_ASST_WDTH + */ + uint8_t PchPmPwrCycDur; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 99cbef2e63..3a50929a9b 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -185,9 +185,6 @@ static void post_mp_init(void) * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 586dbfdd24..235dc6e3cf 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -17,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067b8c..0977857684 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,108 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -183,8 +81,8 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6babcfb..1badad3425 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -40,10 +41,7 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -62,19 +60,12 @@ static void pch_finalize(void) * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 6493fd590e..cb0070a879 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -76,6 +78,11 @@ static void parse_devicetree(FSP_S_CONFIG *params) sizeof(config->SerialIoUartMode)); } +__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -84,6 +91,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_jasperlake_config *config = config_of_soc(); + /* Allow mainboard to override any chip config */ + mainboard_update_soc_chip_config(config); + /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); @@ -92,19 +102,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; + params->PavpEnable = CONFIG(PAVP); /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - } /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { @@ -123,7 +127,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->EndOfPostMessage = EOP_PEI; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); params->Enable8254ClockGatingOnS3 = 1; /* disable Legacy PME */ @@ -135,19 +139,25 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* USB configuration */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { - params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; @@ -161,8 +171,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* SATA */ dev = pcidev_path_on_root(PCH_DEVFN_SATA); - if (dev) { - params->SataEnable = dev->enabled; + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; @@ -175,32 +185,30 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) ARRAY_SIZE(config->SataPortsDevSlp), "copy buffer overflow!"); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); - } else { - params->SataEnable = 0; } + /* VR Configuration */ + params->ImonSlope[0] = config->ImonSlope; + params->ImonOffset[0] = config->ImonOffset; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - if (!dev) { - params->ScsSdCardEnabled = 0; - } else { - params->ScsSdCardEnabled = dev->enabled; + params->ScsSdCardEnabled = is_dev_enabled(dev); + if (params->ScsSdCardEnabled) params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; - } - params->Device4Enable = config->Device4Enable; + /* Enable Processor Thermal Control */ + dev = pcidev_path_on_root(SA_DEVFN_DPTF); + params->Device4Enable = is_dev_enabled(dev); /* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset; /* eMMC configuration */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - if (!dev) { - params->ScsEmmcEnabled = 0; - } else { - params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcEnabled = is_dev_enabled(dev); + if (params->ScsEmmcEnabled) params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - } /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -213,16 +221,35 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->XdciEnable = 0; } - /* Disable Pavp */ - params->PavpEnable = 0; - /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Apply minimum assertion width settings if non-zero */ + if (config->PchPmSlpS3MinAssert) + params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; + if (config->PchPmSlpS4MinAssert) + params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; + if (config->PchPmSlpSusMinAssert) + params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; + if (config->PchPmSlpAMinAssert) + params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + + /* Set Power Cycle Duration */ + if (config->PchPmPwrCycDur) + params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, + config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, + config->PchPmPwrCycDur); + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } +/* Disable Multiphase Si init */ +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} + /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 3b3b262996..52c147fb04 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -56,14 +56,12 @@ static const struct pad_group jsl_community2_groups[] = { INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17), }; - static const struct pad_group jsl_community4_groups[] = { INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23), INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288), /* GPP_E */ INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36), }; - static const struct pad_group jsl_community5_groups[] = { INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320), /* GPP_G */ }; @@ -182,14 +180,15 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) static const struct pmc_to_gpio_route routes[] = { { PMC_GPP_A, GPP_A }, { PMC_GPP_B, GPP_B }, + { PMC_GPP_G, GPP_G }, + { PMC_GPP_C, GPP_C }, { PMC_GPP_R, GPP_R }, { PMC_GPP_D, GPP_D }, { PMC_GPP_S, GPP_S }, { PMC_GPP_H, GPP_H }, + { PMC_GPP_F, GPP_F }, { PMC_GPD, GPP_GPD }, - { PMC_GPP_C, GPP_C }, - { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F } + { PMC_GPP_E, GPP_E } }; *num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/jasperlake/include/soc/bootblock.h b/src/soc/intel/jasperlake/include/soc/bootblock.h index c8adc0396e..413ae4f83b 100644 --- a/src/soc/intel/jasperlake/include/soc/bootblock.h +++ b/src/soc/intel/jasperlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/jasperlake/include/soc/espi.h b/src/soc/intel/jasperlake/include/soc/espi.h index 5c99adba38..bc5eeed11a 100644 --- a/src/soc/intel/jasperlake/include/soc/espi.h +++ b/src/soc/intel/jasperlake/include/soc/espi.h @@ -3,7 +3,6 @@ #ifndef _SOC_JASPERLAKE_ESPI_H_ #define _SOC_JASPERLAKE_ESPI_H_ - /* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h index 119fea76b1..384c0672d3 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio.h +++ b/src/soc/intel/jasperlake/include/soc/gpio.h @@ -6,7 +6,6 @@ #include #include - #define CROS_GPIO_NAME "INT34C8" #define CROS_GPIO_COMM0_NAME "INT34C8:00" #define CROS_GPIO_COMM1_NAME "INT34C8:01" diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index 6e822c943b..5b3cc9d781 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -8,7 +8,6 @@ #endif #include - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h index 011b785bef..8d6064c8f7 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h @@ -24,6 +24,7 @@ #define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 +#define SD_PWR_EN_PIN GPP_H1 /* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index c45430a02e..79ffe29f52 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -47,7 +47,7 @@ #define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_SIZE 0x1000 -#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_ADDRESS 0xfed92000 #define IPUVT_BASE_SIZE 0x1000 #define VTVC0_BASE_ADDRESS 0xfed91000 diff --git a/src/soc/intel/jasperlake/include/soc/pch.h b/src/soc/intel/jasperlake/include/soc/pch.h index db62c8649a..cd91a249bd 100644 --- a/src/soc/intel/jasperlake/include/soc/pch.h +++ b/src/soc/intel/jasperlake/include/soc/pch.h @@ -3,7 +3,6 @@ #ifndef _SOC_JASPERLAKE_PCH_H_ #define _SOC_JASPERLAKE_PCH_H_ - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 5954a3115d..34172f8691 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -98,20 +98,22 @@ #define PCH2CPU_TT_EN (1 << 26) #define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_F 0x2 -#define PMC_GPD 0x3 -#define PMC_GPP_R 0x4 -#define PMC_GPP_S 0x6 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 -#define PMC_GPP_C 0x8 -#define PMC_GPP_H 0xA -#define PMC_GPP_E 0xF +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h index 8188fbdb84..1de8e37758 100644 --- a/src/soc/intel/jasperlake/include/soc/ramstage.h +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -9,6 +9,7 @@ #include void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config); void soc_init_pre_device(void *chip_info); #endif diff --git a/src/soc/intel/jasperlake/include/soc/romstage.h b/src/soc/intel/jasperlake/include/soc/romstage.h index bd6096b7a3..3772db4bc1 100644 --- a/src/soc/intel/jasperlake/include/soc/romstage.h +++ b/src/soc/intel/jasperlake/include/soc/romstage.h @@ -5,11 +5,9 @@ #include -/* Provide a callback to allow mainboard to override the DRAM part number. */ -bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 2ad98f7256..6acd7f3e4b 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -9,46 +9,39 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6a40 +#define IMRLIMIT 0x6a48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 -#define TBT3BAR 0x78A0 +#define TBT3BAR 0x78a0 + #define MAX_TBT_PCIE_PORT 4 #define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; #define V_P2SB_CFG_IBDF_BUS 0 diff --git a/src/soc/intel/jasperlake/include/soc/usb.h b/src/soc/intel/jasperlake/include/soc/usb.h index 247b0ba554..69d2d31a4c 100644 --- a/src/soc/intel/jasperlake/include/soc/usb.h +++ b/src/soc/intel/jasperlake/include/soc/usb.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_USB_H_ #define _SOC_USB_H_ diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index 44430556a1..ed6a31dc58 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -78,8 +78,6 @@ static void pmc_init(struct device *dev) pmc_set_power_failure_state(true); pmc_gpe_init(); - pmc_set_acpi_mode(); - config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); @@ -98,8 +96,23 @@ static void soc_pmc_read_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void soc_acpi_mode_init(struct device *dev) +{ + /* + * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order + * to ensure the ordering does not break the assumptions that other + * drivers make about ACPI mode (e.g. Chrome EC). Since it disables + * ACPI mode, other drivers may take different actions based on this + * (e.g. Chrome EC will flush any pending hostevent bits). Because + * JSL has its PMC device available for device_operations, it can be + * done from the "ops->init" callback. + */ + pmc_set_acpi_mode(); +} + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, + .init = soc_acpi_mode_init, .enable = pmc_init, }; diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f92e746ae3..ebe46b1d0e 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -156,7 +156,6 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } - uint32_t *soc_pmc_etr_addr(void) { return (uint32_t *)(soc_read_pmc_base() + ETR); diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index d37ff5407a..1f7ea3c180 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -11,7 +11,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) + if (cse_request_global_reset()) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 6d4055ab51..dccdebf304 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -12,18 +13,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_jasperlake_config *config) { unsigned int i; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *dev; uint32_t mask = 0; - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->SaGv = config->SaGv; @@ -61,16 +60,19 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - if (dev && dev->enabled && config->TraceHubMode) { + if (is_dev_enabled(dev) && config->TraceHubMode) { m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; m_cfg->PchTraceHubMode = config->TraceHubMode; m_cfg->CpuTraceHubMode = config->TraceHubMode; } + /* IPU configuration */ + dev = pcidev_path_on_root(SA_DEVFN_IPU); + m_cfg->SaIpuEnable = is_dev_enabled(dev); + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; @@ -92,10 +94,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Audio */ dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_dev_enabled(dev); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; @@ -114,6 +113,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(config->PchHdaAudioLinkSndwEnable)); + + /* Skip the CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c index e800ce50bd..d3c2554425 100644 --- a/src/soc/intel/jasperlake/romstage/pch.c +++ b/src/soc/intel/jasperlake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include -void pch_init(void) +void romstage_pch_init(void) { - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); } diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 54632383eb..1fa6c2d180 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - /* Default weak implementation, no need to override part number. */ - return false; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -42,7 +36,7 @@ static void save_dimm_info(void) FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; + size_t dram_part_num_len = 0; bool is_dram_part_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ @@ -66,8 +60,11 @@ static void save_dimm_info(void) memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + is_dram_part_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -131,7 +128,7 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 664ea6cfe4..bbdcb68b10 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -17,7 +17,6 @@ #include #include #include -#include static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ void smm_relocate(void) else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-1.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-1.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-1.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-1.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-2.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-2.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-2.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-2.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-3.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-3.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-3.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-3.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-4.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-4.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-4.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-4.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-5.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-5.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-5.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-5.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-6.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-6.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-6.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-6.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd-7.hex b/src/soc/intel/jasperlake/spd/lp4x-spd-7.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x/spd-7.hex rename to src/soc/intel/jasperlake/spd/lp4x-spd-7.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt deleted file mode 100644 index 564322e9e5..0000000000 --- a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt +++ /dev/null @@ -1,13 +0,0 @@ -H9HCNNNBKMMLXR-NEE,spd-1.hex -H9HCNNNFAMMLXR-NEE,spd-2.hex -K4U6E3S4AA-MGCL,spd-1.hex -K4UBE3D4AA-MGCL,spd-3.hex -MT53E1G32D2NP-046 WT:A,spd-4.hex -H9HKNNNCRMBVAR-NEH,spd-5.hex -MT53E1G64D4SQ-046 WT:A,spd-6.hex -MT53E512M32D2NP-046 WT:F,spd-1.hex -NT6AP256T32AV-J2,spd-7.hex -K4U6E3S4AA-MGCR,spd-1.hex -MT53E512M32D2NP-046 WT:E,spd-1.hex -H9HCNNNCPMMLXR-NEE,spd-3.hex -K4UBE3D4AA-MGCR,spd-3.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt new file mode 100644 index 0000000000..a0089f3fc0 --- /dev/null +++ b/src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt @@ -0,0 +1,13 @@ +H9HCNNNBKMMLXR-NEE,lp4x-spd-1.hex +H9HCNNNFAMMLXR-NEE,lp4x-spd-2.hex +K4U6E3S4AA-MGCL,lp4x-spd-1.hex +K4UBE3D4AA-MGCL,lp4x-spd-3.hex +MT53E1G32D2NP-046 WT:A,lp4x-spd-4.hex +H9HKNNNCRMBVAR-NEH,lp4x-spd-5.hex +MT53E1G64D4SQ-046 WT:A,lp4x-spd-6.hex +MT53E512M32D2NP-046 WT:F,lp4x-spd-1.hex +NT6AP256T32AV-J2,lp4x-spd-7.hex +K4U6E3S4AA-MGCR,lp4x-spd-1.hex +MT53E512M32D2NP-046 WT:E,lp4x-spd-1.hex +H9HCNNNCPMMLXR-NEE,lp4x-spd-3.hex +K4UBE3D4AA-MGCR,lp4x-spd-3.hex diff --git a/src/soc/intel/jasperlake/spd/placeholder.spd.hex b/src/soc/intel/jasperlake/spd/placeholder.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/soc/intel/jasperlake/spd/placeholder.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 6571eb24f8..f8e967b32b 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -9,10 +9,7 @@ if SOC_INTEL_QUARK config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 + select ARCH_ALL_STAGES_X86_32 select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 94ae667081..fc96fb6c3b 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -10,7 +10,6 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - unsigned long acpi_fill_mcfg(unsigned long current) { return current; diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index 46e47583be..c7db8d50b9 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -66,7 +66,6 @@ #define QUARK2_MC_DEVICE_ID 0x12C0 #define QNC_MC_REV_ID_A0 0x00 - // // MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5) // [31:24] Message opcode - D0 read; E0 write; @@ -119,7 +118,6 @@ #define QUARK_OPCODE_IO_READ 0x02 // Message bus "IO read" opcode #define QUARK_OPCODE_IO_WRITE 0x03 // Message bus "IO write" opcode - #define QUARK_DRAM_BASE_ADDR_READY 0x78 // Message bus "RMU Main binary // shadow" opcode @@ -501,7 +499,6 @@ #define B_QNC_PM1BLK_PM1S_TO (BIT0) #define N_QNC_PM1BLK_PM1S_RTC 10 - #define R_QNC_PM1BLK_PM1E 0x02 #define S_QNC_PM1BLK_PM1E 2 #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) diff --git a/src/soc/intel/quark/include/soc/acpi.h b/src/soc/intel/quark/include/soc/acpi.h index d40fe81cfa..4a6d5c1eb0 100644 --- a/src/soc/intel/quark/include/soc/acpi.h +++ b/src/soc/intel/quark/include/soc/acpi.h @@ -6,5 +6,4 @@ #include #include - #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h index 84bce7dc51..e4bcab1b93 100644 --- a/src/soc/intel/quark/include/soc/cpu.h +++ b/src/soc/intel/quark/include/soc/cpu.h @@ -6,6 +6,6 @@ #include /* Supported CPUIDs */ -#define CPUID_QUARK_X1000 0X590 +#define CPUID_QUARK_X1000 0x590 #endif /* _QUARK_CPU_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 95e5f28507..2c6a53229b 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -13,7 +13,7 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 -#define LPC_DEVID 0X095E +#define LPC_DEVID 0x095E #define PCIE_PORT0_DEVID 0x11c3 #define PCIE_PORT1_DEVID 0x11c4 diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 8bf066ae16..dd602c2d5c 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -22,7 +22,6 @@ void storage_test_complete(struct device *dev, uint32_t previous_bar, uint16_t previous_command); #endif - /* Logging support */ struct log_entry { struct mono_time time; diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c index 8696277ce1..19ca745ca1 100644 --- a/src/soc/intel/quark/uart_common.c +++ b/src/soc/intel/quark/uart_common.c @@ -8,7 +8,7 @@ unsigned int uart_platform_refclk(void) return 44236800; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return UART_BASE_ADDRESS; } diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a3e8d9f92e..c6e3a229de 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -19,11 +19,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON @@ -35,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -46,8 +41,8 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK @@ -80,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select USE_CAR_NEM_ENHANCED_V1 config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 1beff3d3af..275e77df1a 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -379,7 +379,7 @@ void generate_cpu_entries(const struct device *device) printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config->eist_enable && config->speed_shift_enable) { + if (config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); @@ -403,9 +403,11 @@ void generate_cpu_entries(const struct device *device) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); - if (config->speed_shift_enable) - acpigen_write_CPPC_method(); } + + if (config->speed_shift_enable) + acpigen_write_CPPC_method(); + acpigen_pop_len(); } } @@ -425,22 +427,19 @@ static unsigned long acpi_fill_dmar(unsigned long current) const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ - if (igfx_dev && igfx_dev->enabled && gfxvten && - gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { - unsigned long tmp = current; + const bool emit_igd = + igfx_dev && igfx_dev->enabled && + gfx_vtbar && gfxvten && + !MCHBAR32(GFXVTBAR + 4); + + /* First, add DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; @@ -461,6 +460,16 @@ static unsigned long acpi_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } @@ -625,12 +634,18 @@ const char *soc_acpi_name(const struct device *dev) if (dev->path.type != DEVICE_PATH_PCI) return NULL; - /* Only match devices on the root bus */ - if (dev->bus && dev->bus->secondary > 0) + /* Match functions 0 and 1 for possible GPUs on a secondary bus */ + if (dev->bus && dev->bus->secondary > 0) { + switch (PCI_FUNC(dev->path.pci.devfn)) { + case 0: return "DEV0"; + case 1: return "DEV1"; + } return NULL; + } switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_PEG0: return "PEGP"; case SA_DEVFN_IGD: return "GFX0"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; @@ -673,7 +688,6 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDIO: return "SDIO"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 60e1cf5730..f863fc7021 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#define GPIOTXSTATE_MASK 0x1 -#define GPIORXSTATE_MASK 0x1 - Device (GPIO) { Name (_HID, "INT344B") @@ -24,29 +22,28 @@ Device (GPIO) /* GPIO Community 0 */ CreateDWordField (^RBUF, ^COM0._BAS, BAS0) CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - Store (^^PCRB (PID_GPIOCOM0), BAS0) - Store (GPIO_BASE_SIZE, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE /* GPIO Community 1 */ CreateDWordField (^RBUF, ^COM1._BAS, BAS1) CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - Store (^^PCRB (PID_GPIOCOM1), BAS1) - Store (GPIO_BASE_SIZE, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE /* GPIO Community 3 */ CreateDWordField (^RBUF, ^COM3._BAS, BAS3) CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - Store (^^PCRB (PID_GPIOCOM3), BAS3) - Store (GPIO_BASE_SIZE, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) - And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), - GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) + Local0 = ^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG) & GPIO_DRIVER_IRQ_ROUTE_MASK - If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { - Store (GPIO_IRQ14, IRQN) + If (Local0 == GPIO_DRIVER_IRQ_ROUTE_IRQ14) { + IRQN = GPIO_IRQ14 } Else { - Store (GPIO_IRQ15, IRQN) + IRQN = GPIO_IRQ15 } Return (RBUF) @@ -66,104 +63,45 @@ Method (GADD, 1, NotSerialized) { #if CONFIG(SKYLAKE_SOC_PCH_H) /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + If ((Arg0 >= GPP_A0) && (Arg0 <= GPP_B23)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + If ((Arg0 >= GPP_C0) && (Arg0 <= GPP_H23)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_C0 } - /* GPIO Community 03 */ - If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + /* GPIO Community 3 */ + If ((Arg0 >= GPP_I0) && (Arg0 <= GPP_I10)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, GPP_I0, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPP_I0 } #else /* GPIO Community 0 */ - If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + If ((Arg0 >= GPP_A0) && (Arg0 <= GPP_B23)) { - Store (PID_GPIOCOM0, Local0) - Subtract (Arg0, GPP_A0, Local1) + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_A0 } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) + If ((Arg0 >= GPP_C0) && (Arg0 <= GPP_E23)) { - Store (PID_GPIOCOM1, Local0) - Subtract (Arg0, GPP_C0, Local1) + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_C0 } - /* GPIO Community 03*/ - If (LAnd (LGreaterEqual (Arg0, GPP_F0), LLessEqual (Arg0, GPP_G7))) + /* GPIO Community 3 */ + If ((Arg0 >= GPP_F0) && (Arg0 <= GPP_G7)) { - Store (PID_GPIOCOM3, Local0) - Subtract (Arg0, GPP_F0, Local1) + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPP_F0 } #endif /* CONFIG_SKYLAKE_SOC_PCH_H */ - Store (PCRB (Local0), Local2) - Add (Local2, PAD_CFG_BASE, Local2) - Return (Add (Local2, Multiply (Local1, 8))) -} - -/* - * Get GPIO Rx Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) - - Return (Local0) -} - -/* - * Get GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (GTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) - - Return (Local0) -} - -/* - * Set GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (STXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) -} - -/* - * Clear GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (CTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + + Local2 = PCRB (Local0) + Local2 += PAD_CFG_BASE + Return (Local2 + (Local1 * 8)) } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 9d5f8be19d..6eea5bb53a 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -36,7 +36,7 @@ #include "serialio.asl" /* SMBus 0:1f.3 */ -#include "smbus.asl" +#include /* Storage Controllers */ #include "scs.asl" diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl deleted file mode 100644 index d989fb1bfa..0000000000 --- a/src/soc/intel/skylake/acpi/platform.asl +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Enable ACPI _SWS methods */ -#include - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} - -/* - * The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method (_PTS, 1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method (_WAK, 1) -{ - Return (Package (){ 0, 0 }) -} diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl deleted file mode 100644 index 7860f606c9..0000000000 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.4 - -Device (SBUS) -{ - Name (_ADR, 0x001f0004) -} diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index d306879ae8..957b4c2a5d 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -153,17 +154,11 @@ static void report_cpu_info(void) u32 i, cpu_id, cpu_feature_flag; char cpu_name[49]; int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; fill_processor_name(cpu_name); - - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -175,7 +170,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6ef01d8c0c..dfbdfb812d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -139,8 +139,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = @@ -149,11 +147,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = @@ -166,14 +173,30 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } - memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, - sizeof(params->SataPortsHotPlug)); - memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, - sizeof(params->SataPortsSpinUp)); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); + params->SataEnable = dev && dev->enabled; + if (params->SataEnable) { + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); + + params->SataSalpSupport = config->SataSalpSupport; + params->SataMode = config->SataMode; + params->SataSpeedLimit = config->SataSpeedLimit; + /* + * For unknown reasons FSP skips writing some essential SATA init registers + * (SIR) when SataPwrOptEnable=0. This results in link errors, "unaligned + * write" errors and others. Enabling this option solves these problems. + */ + params->SataPwrOptEnable = 1; + tconfig->SataTestMode = config->SataTestMode; + } + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -208,14 +231,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* Legacy 8254 timer support */ - params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); - params->PchCio2Enable = config->Cio2Enable; - params->SaImguEnable = config->SaImguEnable; - params->Heci3Enabled = config->Heci3Enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CIO); + params->PchCio2Enable = dev && dev->enabled; + + dev = pcidev_path_on_root(SA_DEVFN_IMGU); + params->SaImguEnable = dev && dev->enabled; + + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = dev && dev->enabled; params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; @@ -226,18 +254,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; - params->PchLanEnable = config->EnableLan; - if (config->EnableLan) { + dev = pcidev_path_on_root(PCH_DEVFN_GBE); + params->PchLanEnable = dev && dev->enabled; + if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; params->PchLanClkReqSupported = config->LanClkReqSupported; params->PchLanClkReqNumber = config->LanClkReqNumber; } - params->SataSalpSupport = config->SataSalpSupport; params->SsicPortEnable = config->SsicPortEnable; - params->ScsEmmcEnabled = config->ScsEmmcEnabled; + + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + params->ScsEmmcEnabled = dev && dev->enabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + params->ScsSdCardEnabled = dev && dev->enabled; if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { params->PchScsEmmcHs400DllDataValid = @@ -250,29 +282,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev ? dev->enabled : 0; + params->PchIshEnable = dev && dev->enabled; + + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + params->PchHdaEnable = dev && dev->enabled; - params->PchHdaEnable = config->EnableAzalia; params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; - params->Device4Enable = config->Device4Enable; - params->SataEnable = config->EnableSata; - params->SataMode = config->SataMode; - params->SataSpeedLimit = config->SataSpeedLimit; - params->EnableTcoTimer = !config->PmTimerDisabled; - /* - * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when - * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others. - * Enabling this option solves these problems. - */ - params->SataPwrOptEnable = 1; + dev = pcidev_path_on_root(SA_DEVFN_TS); + params->Device4Enable = dev && dev->enabled; + params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; - tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree @@ -324,7 +349,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; - params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + params->CpuConfig.Bits.SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; @@ -334,7 +359,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev ? dev->enabled : 0; + params->ShowSpiController = dev && dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -348,7 +373,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable or disable Gaussian Mixture Model in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev ? dev->enabled : 0; + params->GmmEnable = dev && dev->enabled; /* * Send VR specific mailbox commands: @@ -403,6 +428,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->PeiGraphicsPeimInit = 0; + params->PavpEnable = CONFIG(PAVP); + soc_irq_settings(params); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 92cd1bad85..fa30c1dfcf 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ @@ -49,19 +48,6 @@ struct soc_intel_skylake_config { GPU_BACKLIGHT_POLARITY_LOW, } gpu_pch_backlight_polarity; - /* - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -99,7 +85,7 @@ struct soc_intel_skylake_config { uint32_t deep_sx_config; /* TCC activation offset */ - int tcc_offset; + uint32_t tcc_offset; /* Package PL4 power limit in Watts */ u32 PowerLimit4; @@ -149,14 +135,12 @@ struct soc_intel_skylake_config { u8 CmdTriStateDis; /* Lan */ - u8 EnableLan; u8 EnableLanLtr; u8 EnableLanK1Off; u8 LanClkReqSupported; u8 LanClkReqNumber; /* SATA related */ - u8 EnableSata; enum { /* Documentation and header files of Skylake FSP disagree on the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses @@ -172,7 +156,6 @@ struct soc_intel_skylake_config { u8 SataSpeedLimit; /* Audio related */ - u8 EnableAzalia; u8 DspEnable; /* HDA Virtual Channel Type Select */ @@ -190,7 +173,6 @@ struct soc_intel_skylake_config { u8 IoBufferOwnership; /* Trace Hub function */ - u8 EnableTraceHub; u32 TraceHubMemReg0Size; u32 TraceHubMemReg1Size; @@ -287,9 +269,6 @@ struct soc_intel_skylake_config { struct usb3_port_config usb3_ports[10]; u8 SsicPortEnable; - /* SMBus */ - u8 SmbusEnable; - /* * SerialIO device mode selection: * @@ -320,14 +299,8 @@ struct soc_intel_skylake_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* Camera */ - u8 Cio2Enable; - u8 SaImguEnable; - /* eMMC and SD */ - u8 ScsEmmcEnabled; u8 ScsEmmcHs400Enabled; - u8 ScsSdCardEnabled; u8 EmmcHs400DllNeed; u8 ScsEmmcHs400RxStrobeDll1; u8 ScsEmmcHs400TxDataDll; @@ -335,7 +308,6 @@ struct soc_intel_skylake_config { u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; - u8 Heci3Enabled; /* Gfx related */ u8 IgdDvmt50PreAlloc; @@ -358,7 +330,6 @@ struct soc_intel_skylake_config { u32 LogoPtr; u32 LogoSize; u32 GraphicsConfigPtr; - u8 Device4Enable; u8 RtcLock; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d941df70b2..79fcda1fa5 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -32,7 +32,6 @@ static void configure_isst(void) config_t *conf = config_of_soc(); msr_t msr; - if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP @@ -58,7 +57,6 @@ static void configure_misc(void) config_t *conf = config_of_soc(); msr_t msr; - msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 550ee41805..dee93d889b 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -22,7 +22,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index c6c2029254..c8e4ec4fb6 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -52,28 +52,28 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 98f12a5b6c..ff3218981a 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -44,17 +45,13 @@ static void pch_disable_heci(void) static void pch_finalize_script(struct device *dev) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - u8 reg8; tco_lockdown(); /* Display me status before we hide it */ intel_me_status(); - pmcbase = pmc_mmio_regs(); config = config_of(dev); /* @@ -73,18 +70,12 @@ static void pch_finalize_script(struct device *dev) * Disabling ACPI PM timer also switches off TCO */ - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CIR31C); - reg32 |= XTALSDQDIS; - write32(pmcbase + CIR31C, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index f106895296..5519762e34 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -5,7 +5,6 @@ #include #include - static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30}, { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30}, diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h index 9e49b8215a..af092050b0 100644 --- a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h @@ -209,5 +209,4 @@ #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) - #endif /* _SOC_GPIO_SOC_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index 940ea13c96..41654e70da 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -11,6 +11,4 @@ #define PCH_P2SB_EPMASK0 0xB0 -#define PCH_PWRM_ACPI_TMR_CTL 0xFC - #endif /* _SOC_P2SB_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 60c5f3a5d2..319a12b53a 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -23,11 +23,25 @@ #endif #define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) +#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0) +#define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1) +#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEV_SLOT_TS 0x04 +#define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) +#define SA_DEV_TS PCI_DEV(0, SA_DEV_SLOT_TS, 0) + +#define SA_DEV_SLOT_IMGU 0x05 +#define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0) +#define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0) + #define SA_DEV_SLOT_GMM 0x08 #define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) #define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index f4995a2e86..350649a211 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -77,11 +77,13 @@ #define DSX_EN_LAN_WAKE_PIN (1 << 0) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 -#define CIR31C 0x31c +#define CPPMVRIC 0x31c #define XTALSDQDIS (1 << 22) #endif diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 4bea447c59..d87c859efa 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_USB_H_ #define _SOC_USB_H_ diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 2a30ae47f1..5207af85c4 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -80,7 +80,6 @@ enum vr_domain { [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ } - void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index dbc172f66c..ad75f027a1 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -215,72 +215,3 @@ void soc_irq_settings(FSP_SIL_UPD *params) /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; } - -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - const config_t *config = config_of(dev); - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - struct device *irq_dev; - - pch_interrupt_routing[0] = config->pirqa_routing; - pch_interrupt_routing[1] = config->pirqb_routing; - pch_interrupt_routing[2] = config->pirqc_routing; - pch_interrupt_routing[3] = config->pirqd_routing; - pch_interrupt_routing[4] = config->pirqe_routing; - pch_interrupt_routing[5] = config->pirqf_routing; - pch_interrupt_routing[6] = config->pirqg_routing; - pch_interrupt_routing[7] = config->pirqh_routing; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; - case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; - case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; - case 4: /* INTD# */ - int_line = config->pirqd_routing; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7dc90f07a1..f9c663980e 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,29 +29,6 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) return skl_lpc_fixed_mmio_ranges; } -static void pch_enable_ioapic(struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} - void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { const config_t *config = config_of(dev); @@ -72,10 +49,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) } static const struct reg_script pch_misc_init_script[] = { - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), - /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), REG_SCRIPT_END @@ -87,6 +60,7 @@ void lpc_soc_init(struct device *dev) /* Legacy initialization */ isa_dma_init(); + pch_misc_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script); /* Enable CLKRUN_EN for power gating LPC */ @@ -96,8 +70,8 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 0d6135fabd..92a7dafbba 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -10,7 +10,6 @@ #include #include - /* HFSTS1[3:0] Current Working State Values */ static const char *const me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -341,7 +340,7 @@ void intel_me_status(void) int send_global_reset(void) { - int status = -1; + int status = 0; union me_hfsts1 hfs1; if (!is_cse_enabled()) @@ -353,7 +352,7 @@ int send_global_reset(void) goto ret; /* ME should be in Normal Mode for this command */ - status = cse_request_global_reset(GLOBAL_RESET); + status = cse_request_global_reset(); ret: return status; } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444ad5e..5e0d6871e2 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -170,11 +170,9 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, * If PEG port is not defined in the device tree, it will be disabled * in FSP */ - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ - if (!dev || !dev->enabled) - m_cfg->Peg0Enable = 0; - else if (dev->enabled) { - m_cfg->Peg0Enable = dev->enabled; + dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ + m_cfg->Peg0Enable = dev && dev->enabled; + if (m_cfg->Peg0Enable) { m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; /* Use maximum possible link speed */ m_cfg->Peg0MaxLinkSpeed = 0; @@ -185,11 +183,9 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg0Gen3EqPh3Method = 0; } - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ - if (!dev || !dev->enabled) - m_cfg->Peg1Enable = 0; - else if (dev->enabled) { - m_cfg->Peg1Enable = dev->enabled; + dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ + m_cfg->Peg1Enable = dev && dev->enabled; + if (m_cfg->Peg1Enable) { m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1PowerDownUnusedLanes = 1; @@ -197,11 +193,9 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg1Gen3EqPh3Method = 0; } - dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ - if (!dev || !dev->enabled) - m_cfg->Peg2Enable = 0; - else if (dev->enabled) { - m_cfg->Peg2Enable = dev->enabled; + dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ + m_cfg->Peg2Enable = dev && dev->enabled; + if (m_cfg->Peg2Enable) { m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2PowerDownUnusedLanes = 1; @@ -226,7 +220,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<enabled) { - /* - * If iGPU is disabled or not defined in the devicetree.cb, - * the FSP does not initialize this device - */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake - * does not have access to the bios_reserved range so it always - * assumes 8MB is used and so the kernel will avoid the last - * 8MB of the stolen window. With the default stolen size of - * 32MB(-8MB) there is not enough space for FBC to work with - * a high resolution panel - */ - m_cfg->IgdDvmt50PreAlloc = 2; - } + m_cfg->InternalGfx = dev && dev->enabled; + + /* + * If iGPU is enabled, set IGD stolen size to 64MB. The FBC + * hardware for skylake does not have access to the bios + * reserved range so it always assumes 8MB is used and so the + * kernel will avoid the last 8MB of the stolen window. With + * the default stolen size of 32MB(-8MB) there is not enough + * space for FBC to work with a high resolution panel. + * + * If disabled, don't reserve memory for it. + */ + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 2 : 0; + m_cfg->PrimaryDisplay = config->PrimaryDisplay; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_skylake_config *config; + const struct device *dev; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; @@ -292,12 +282,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* DCI and TraceHub configs */ m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; + + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + m_cfg->EnableTraceHub = dev && dev->enabled; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + /* Enable SMBus controller */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + m_cfg->SmbusEnable = dev && dev->enabled; /* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 1f40d98255..ba56182af1 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -8,7 +8,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev) config_t *config = config_of(dev); /* Nothing to write if GPIO is not set in devicetree */ - if(!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) + if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) return -1; if (config->sdcard_cd_gpio_default) { diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 3aec51b216..05bd1f7730 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -19,7 +19,6 @@ #include #include "chip.h" - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 091abb927f..4df2e852ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -8,14 +8,11 @@ if SOC_INTEL_TIGERLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP @@ -24,7 +21,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select INTEL_CAR_NEM select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -32,12 +29,11 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_1 + select PLATFORM_USES_FSP2_2 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT - select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON_SMM + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK @@ -90,6 +86,10 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/tigerlake/chipset.cb" + config IFD_CHIPSET string default "tgl" @@ -171,6 +171,11 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC +# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection +# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. +config TPM_CR50 + select CR50_USE_LONG_INTERRUPT_PULSES + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY @@ -210,5 +215,5 @@ config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0xe00 + default 0x2000 endif diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 4b31c6d48a..c7c544615e 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -164,7 +165,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_blk = pmbase + PM1_TMR; fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; @@ -187,7 +188,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -200,7 +201,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; - if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index b17abfe483..5a6e54a4a7 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -2,9 +2,9 @@ #include #include #include +#include #include #include -#include "gpio_op.asl" Device (GPIO) { diff --git a/src/soc/intel/tigerlake/acpi/ipu.asl b/src/soc/intel/tigerlake/acpi/ipu.asl deleted file mode 100644 index b6d8e8fe01..0000000000 --- a/src/soc/intel/tigerlake/acpi/ipu.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0) -{ - Device (IPU0) - { - Name (_ADR, 0x00050000) - Name (_DDN, "Camera and Imaging Subsystem") - } -} diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl deleted file mode 100644 index 5c8b130315..0000000000 --- a/src/soc/intel/tigerlake/acpi/ish.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Integrated Sensor Hub Controller 0:12.0 */ - -Device (ISHB) -{ - Name (_ADR, 0x00120000) - Name (_DDN, "Integrated Sensor Hub Controller") -} diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl index 08fce8c1f1..13b4d3ddd0 100644 --- a/src/soc/intel/tigerlake/acpi/pch_hda.asl +++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl @@ -50,7 +50,7 @@ Device (HDAS) * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl deleted file mode 100644 index 4b01aeb464..0000000000 --- a/src/soc/intel/tigerlake/acpi/platform.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Enable ACPI _SWS methods */ -#include -/* Generic indicator for sleep state */ -#include - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - PICM = Arg0 -} diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl deleted file mode 100644 index 6705f22693..0000000000 --- a/src/soc/intel/tigerlake/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel SMBus Controller 0:1f.4 */ - -Device (SBUS) -{ - Name (_ADR, 0x001f0004) -} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index ff683cf4f6..42f3b129a9 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -17,6 +17,9 @@ /* GPIO controller */ #include "gpio.asl" +/* GFX 00:02.0 */ +#include + /* ESPI 0:1f.0 */ #include @@ -30,10 +33,10 @@ #include "serialio.asl" /* SMBus 0:1f.4 */ -#include "smbus.asl" +#include /* ISH 0:12.0 */ -#include "ish.asl" +#include /* USB XHCI 0:14.0 */ #include "xhci.asl" @@ -43,3 +46,6 @@ /* PMC Core*/ #include + +/* GbE 0:1f.6 */ +#include diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 33c1107a05..98938339bf 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include @@ -382,7 +379,7 @@ Scope (\_SB.PCI0) * Poll pCode MailBox Ready * * Return 0xFF - Timeout - * 0x00 - Ready + * 0x00 - Ready */ Method (PMBY, 0) { @@ -408,13 +405,13 @@ Scope (\_SB.PCI0) * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS: * 0 - IDLE. TCSS DEVEN has reached its final requested state. * 1 - In Progress. TCSS DEVEN is currently in progress of switching state - * according to given request (bit 0 reflects source state). + * according to given request (bit 0 reflects source state). * * Return 0x00 - TCSS Deven in normal state - * 0x01 - TCSS Deven is cleared by BIOS Mailbox request - * 0x1x - TCSS Deven is in progress of switching state according to given request - * 0xFE - Command timeout - * 0xFF - Command corrupt + * 0x01 - TCSS Deven is cleared by BIOS Mailbox request + * 0x1x - TCSS Deven is in progress of switching state according to given request + * 0xFE - Command timeout + * 0xFF - Command corrupt */ Method (DSGS, 0) { diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 3d44d925df..f7c4117dcf 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) Field (DPME, AnyAcc, NoLock, Preserve) @@ -35,20 +32,12 @@ Method (_S0W, 0x0) Method (_PR0) { - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + Return (Package() { \_SB.PCI0.D3C }) } Method (_PR3) { - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + Return (Package() { \_SB.PCI0.D3C }) } /* @@ -75,6 +64,24 @@ Method (D3CE, 0, Serialized) */ Name (SD3C, 0) +Method (_PS0, 0, Serialized) +{ + If (DUID == 0) { + \_SB.PCI0.TBT0._ON() + } Else { + \_SB.PCI0.TBT1._ON() + } +} + +Method (_PS3, 0, Serialized) +{ + If (DUID == 0) { + \_SB.PCI0.TBT0._OFF() + } Else { + \_SB.PCI0.TBT1._OFF() + } +} + Method (_DSW, 3) { /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 096a6735c9..b4c0cefa1e 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) @@ -79,10 +76,14 @@ Device (PXSX) Method (_DSW, 3) { - C2PM (Arg0, Arg1, Arg2, DCPM) /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ - \_SB.PCI0.TDM0.SD3C = Arg1 - \_SB.PCI0.TDM1.SD3C = Arg1 + If ((TUID == 0) || (TUID == 1)) { + \_SB.PCI0.TDM0.SD3C = Arg1 + } Else { + \_SB.PCI0.TDM1.SD3C = Arg1 + } + + C2PM (Arg0, Arg1, Arg2, DCPM) } Method (_PRW, 0) @@ -305,20 +306,12 @@ Method (_S0W, 0x0, NotSerialized) Method (_PR0) { - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + Return (Package() { \_SB.PCI0.D3C }) } Method (_PR3) { - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } + Return (Package() { \_SB.PCI0.D3C }) } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index c32deed8c3..acbeb30c13 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -1,7 +1,4 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100) Field (XPRT, ByteAcc, NoLock, Preserve) diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index e7d97c50bf..96e6268f74 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9fc5ce167b..18ca5e51af 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -49,26 +49,20 @@ static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) @@ -147,7 +141,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 55a9790d65..03d65a4b1c 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,8 +19,6 @@ #include #include -#define BIOS_SIGN_ID 0x8B - static struct { u32 cpuid; const char *name; @@ -32,10 +31,10 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2, "Tigerlake-U-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, "Tigerlake-Y-2-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2, "Tigerlake-Y-4-2" }, }; static struct { @@ -104,7 +103,6 @@ static void report_cpu_info(void) const char cpu_not_found[] = "Platform info not available"; const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ int vt, txt, aes; - msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13]; @@ -129,11 +127,7 @@ static void report_cpu_info(void) cpu_name++; } - microcode_ver.lo = 0; - microcode_ver.hi = 0; - wrmsr(BIOS_SIGN_ID, microcode_ver); cpu_id = cpu_get_cpuid(); - microcode_ver = rdmsr(BIOS_SIGN_ID); /* Look for string to match the name */ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { @@ -145,7 +139,7 @@ static void report_cpu_info(void) printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, microcode_ver.hi); + cpu_id, cpu_type, get_current_microcode_rev()); cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d08355e019..98ed55ca58 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,12 @@ #include #include +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -97,8 +104,6 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_GSPI3: return "SPI3"; - /* Keeping ACPI device name coherent with ec.asl */ - case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_GBE: return "GLAN"; @@ -140,6 +145,9 @@ void soc_init_pre_device(void *chip_info) itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); soc_fill_gpio_pm_configuration(); + + /* Swap enabled PCI ports in device tree if needed. */ + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 59dab58bb8..bcf71b1e62 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -9,23 +9,23 @@ #include #include #include -#include -#include #include #include #include #include #include -#include +#include #define MAX_HD_AUDIO_DMIC_LINKS 2 #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 /* The first two are for TGL-U */ -#define POWER_LIMITS_U_4_CORE 0 -#define POWER_LIMITS_U_2_CORE 1 -#define POWER_LIMITS_MAX 2 +#define POWER_LIMITS_U_2_CORE 0 +#define POWER_LIMITS_U_4_CORE 1 +#define POWER_LIMITS_Y_2_CORE 2 +#define POWER_LIMITS_Y_4_CORE 3 +#define POWER_LIMITS_MAX 4 /* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, @@ -54,6 +54,20 @@ enum fivr_voltage_supported { #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) +/* Bit values for use in LpmStateEnableMask. */ +enum lpm_state_mask { + LPM_S0i2_0 = BIT(0), + LPM_S0i2_1 = BIT(1), + LPM_S0i2_2 = BIT(2), + LPM_S0i3_0 = BIT(3), + LPM_S0i3_1 = BIT(4), + LPM_S0i3_2 = BIT(5), + LPM_S0i3_3 = BIT(6), + LPM_S0i3_4 = BIT(7), + LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 + | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, +}; + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ @@ -76,10 +90,13 @@ struct soc_intel_tigerlake_config { /* Enable S0iX support */ int s0ix_enable; + /* S0iX: Selectively disable individual sub-states, by default all are enabled. */ + enum lpm_state_mask LpmStateDisableMask; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - uint8_t TcssD3HotEnable; + uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdEnable; + uint8_t TcssD3ColdDisable; /* Enable DPTF support */ int dptf_enable; @@ -372,6 +389,59 @@ struct soc_intel_tigerlake_config { * Default 0. Setting this to 1 to check CPU replacement. */ uint8_t CpuReplacementCheck; + + /* + * SLP_S3 Minimum Assertion Width Policy + * 1 = 60us + * 2 = 1ms + * 3 = 50ms (default) + * 4 = 2s + */ + uint8_t PchPmSlpS3MinAssert; + + /* + * SLP_S4 Minimum Assertion Width Policy + * 1 = 1s (default) + * 2 = 2s + * 3 = 3s + * 4 = 4s + */ + uint8_t PchPmSlpS4MinAssert; + + /* + * SLP_SUS Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 500ms + * 3 = 1s + * 4 = 4s (default) + */ + uint8_t PchPmSlpSusMinAssert; + + /* + * SLP_A Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 4s + * 3 = 98ms + * 4 = 2s (default) + */ + uint8_t PchPmSlpAMinAssert; + + /* + * PCH PM Reset Power Cycle Duration + * 0 = 4s (default) + * 1 = 1s + * 2 = 2s + * 3 = 3s + * 4 = 4s + * + * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the + * stretch duration programmed in the following registers: + * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + * - PM_CFG.SLP_LAN_MIN_ASST_WDTH + */ + uint8_t PchPmPwrCycDur; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb new file mode 100644 index 0000000000..0d2b7a231f --- /dev/null +++ b/src/soc/intel/tigerlake/chipset.cb @@ -0,0 +1,71 @@ +chip soc/intel/tigerlake + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 02.0 alias igpu off end + device pci 04.0 alias dptf off end + device pci 05.0 alias ipu off end + device pci 06.0 alias peg off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias npk off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.2 alias cnvi_bt off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_ram off end + chip drivers/intel/wifi + device pci 14.3 alias cnvi_wifi off end + end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.2 alias csme1 off end + device pci 16.3 alias csme2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias thermal off end + end +end diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 9a96f8f7cd..be056fb7a4 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -191,9 +191,6 @@ static void post_mp_init(void) * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index d5b875419a..84f0a7ed4f 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -17,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 513da5a79e..acd3b12244 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,108 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void) soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -189,8 +87,8 @@ void lpc_soc_init(struct device *dev) lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de7f0..2cc9671c30 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -28,10 +29,7 @@ static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -50,19 +48,12 @@ static void pch_finalize(void) * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 798c16a425..38f444bbd5 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -81,15 +83,22 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; +__weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) +{ + /* Override settings per board. */ +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + uint32_t cpu_id; FSP_S_CONFIG *params = &supd->FspsConfig; struct device *dev; struct soc_intel_tigerlake_config *config; config = config_of_soc(); + mainboard_update_soc_chip_config(config); /* Parse device tree and enable/disable Serial I/O devices */ parse_devicetree(params); @@ -99,22 +108,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - } /* D3Hot and D3Cold for TCSS */ - params->D3HotEnable = config->TcssD3HotEnable; - params->D3ColdEnable = config->TcssD3ColdEnable; + params->D3HotEnable = !config->TcssD3HotDisable; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) + params->D3ColdEnable = 0; + else + params->D3ColdEnable = !config->TcssD3ColdDisable; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) @@ -143,16 +149,24 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; @@ -195,10 +209,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* SATA */ dev = pcidev_path_on_root(PCH_DEVFN_SATA); - if (!dev) - params->SataEnable = 0; - else { - params->SataEnable = dev->enabled; + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, @@ -207,6 +219,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* S0iX: Selectively enable individual sub-states, + * by default all are enabled. + * + * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 + */ + params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask; + /* * Power Optimizer for DMI and SATA. * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. @@ -244,41 +264,33 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); - if (!dev) - params->PchLanEnable = 0; - else - params->PchLanEnable = dev->enabled; + params->PchLanEnable = is_dev_enabled(dev); /* CNVi */ dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); - if (dev) - params->CnviMode = dev->enabled; - else - params->CnviMode = 0; + params->CnviMode = is_dev_enabled(dev); + + /* CNVi BT Core */ + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_BT); + params->CnviBtCore = is_dev_enabled(dev); + + /* CNVi BT Audio Offload */ + params->CnviBtAudioOffload = config->CnviBtAudioOffload; /* VMD */ dev = pcidev_path_on_root(SA_DEVFN_VMD); - if (dev) - params->VmdEnable = dev->enabled; - else - params->VmdEnable = 0; + params->VmdEnable = is_dev_enabled(dev); /* THC */ dev = pcidev_path_on_root(PCH_DEVFN_THC0); - if (!dev) - params->ThcPort0Assignment = 0; - else - params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE; + params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; dev = pcidev_path_on_root(PCH_DEVFN_THC1); - if (!dev) - params->ThcPort1Assignment = 0; - else - params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; + params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); /* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() @@ -327,9 +339,45 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } + /* Apply minimum assertion width settings if non-zero */ + if (config->PchPmSlpS3MinAssert) + params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; + if (config->PchPmSlpS4MinAssert) + params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; + if (config->PchPmSlpSusMinAssert) + params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; + if (config->PchPmSlpAMinAssert) + params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + + /* Set Power Cycle Duration */ + if (config->PchPmPwrCycDur) + params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, + config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, + config->PchPmPwrCycDur); + + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ + params->EnableMultiPhaseSiliconInit = 1; mainboard_silicon_init_params(params); } +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + * This platform supports below MultiPhaseSIInit Phase(s): + * Phase | FSP return point | Purpose + * ------- + ------------------------------------------------ + ------------------------------- + * 1 | After TCSS initialization completed | for TCSS specific init + */ +void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: + /* TCSS specific initialization here */ + break; + default: + break; + } +} + /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 783009b693..87be0e0a70 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); /* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void); diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 28dfb386c9..47a41ebc99 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -7,11 +7,11 @@ /* Latency times in us */ #define C1_LATENCY 1 -#define C6_LATENCY 127 -#define C7_LATENCY 253 -#define C8_LATENCY 260 -#define C9_LATENCY 487 -#define C10_LATENCY 1048 +#define C6_LATENCY 121 +#define C7_LATENCY 152 +#define C8_LATENCY 256 +#define C9_LATENCY 340 +#define C10_LATENCY 1034 /* Power in units of mW */ #define C1_POWER 0x3e8 diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h index 6a86147018..f9f8593996 100644 --- a/src/soc/intel/tigerlake/include/soc/espi.h +++ b/src/soc/intel/tigerlake/include/soc/espi.h @@ -9,7 +9,6 @@ #ifndef _SOC_TIGERLAKE_ESPI_H_ #define _SOC_TIGERLAKE_ESPI_H_ - /* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 9b9013f457..b9842b90ef 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -6,7 +6,6 @@ #include #include - #define CROS_GPIO_DEVICE_NAME "INT34C5:00" #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index dc1087c0ea..7f0827d5f6 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -109,7 +109,6 @@ #define GPP_R6_IRQ 0x5E #define GPP_R7_IRQ 0x5F - /* Group D */ #define GPD0_IRQ 0x60 #define GPD1_IRQ 0x61 @@ -182,7 +181,6 @@ #define GPP_D18_IRQ 0x3E #define GPP_D19_IRQ 0x3F - /* Group U */ #define GPP_U0_IRQ 0x40 #define GPP_U1IRQ 0x41 @@ -205,7 +203,6 @@ #define GPP_U18_IRQ 0x52 #define GPP_U19_IRQ 0x53 - #define GPP_VGPIO4_IRQ 0x54 /* Group F */ @@ -260,8 +257,6 @@ #define GPP_C22_IRQ 0x24 #define GPP_C23_IRQ 0x25 - - /* Group E */ #define GPP_E0_IRQ 0x26 #define GPP_E1_IRQ 0x27 diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index d4c7750189..607183aaf9 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -240,7 +240,7 @@ #define GPD11 182 #define GPD_INPUT3VSEL 183 #define GPD_SLP_LANB 184 -#define GPD__SLP_SUSB 185 +#define GPD_SLP_SUSB 185 #define GPD_WAKEB 186 #define GPD_DRAM_RESETB 187 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index cd964f0d76..6fa29d30cc 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -53,7 +53,7 @@ #define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_SIZE 0x1000 -#define IPUVT_BASE_ADDRESS 0xfed92000 +#define IPUVT_BASE_ADDRESS 0xfed92000 #define IPUVT_BASE_SIZE 0x1000 #define VTVC0_BASE_ADDRESS 0xfed91000 diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index ad70290148..f95f9f672c 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -9,4 +9,8 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 + #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 0180f68449..4a52298b7a 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef _SOC_TIGERLAKE_MEMINIT_H_ #define _SOC_TIGERLAKE_MEMINIT_H_ @@ -25,8 +21,13 @@ enum mem_topology { MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ }; +enum ddr_memtype { + MEMTYPE_DDR4, /* Uses DDR4 memory */ + MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +}; + enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ + /* Read SPD from pointer provided to memory location. */ SPD_MEMPTR, /* Read SPD using index into spd.bin in CBFS. */ SPD_CBFS, @@ -131,9 +132,24 @@ struct mb_ddr4_cfg { uint8_t ect; }; +/* DDR Memory Information - Supports DDR4 and LPDDR4x */ +struct ddr_memory_cfg { + enum ddr_memtype mem_type; + union { + const struct mb_ddr4_cfg *ddr4_cfg; + const struct lpddr4x_cfg *lpddr4_cfg; + }; +}; + +/* Initialize LPDDR4x memory configurations */ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); + const struct spd_info *spd, bool half_populated); + /* Initialize DDR4 memory configurations */ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); + const struct spd_info *spd, const bool half_populated); + +/* Determine which DDR memory is used and call appropriate init routine */ +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h index ad0186adc4..1f20018396 100644 --- a/src/soc/intel/tigerlake/include/soc/pch.h +++ b/src/soc/intel/tigerlake/include/soc/pch.h @@ -3,7 +3,6 @@ #ifndef _SOC_TIGERLAKE_PCH_H_ #define _SOC_TIGERLAKE_PCH_H_ - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 82d8360524..cfb70cdb9f 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -34,6 +34,9 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_CPU_PCIE 0x06 +#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) #define NUM_TBT_FUNCTIONS 4 diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index ae70074fc8..7388593484 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -11,8 +11,6 @@ /* * Port ids */ -#define PID_SDX 0x53 - #define PID_GPIOCOM0 0x6e #define PID_GPIOCOM1 0x6d #define PID_GPIOCOM2 0x6c diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index b7a97cc824..f926799c75 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -126,6 +126,7 @@ enum pch_pmc_xtal { enum pch_pmc_xtal pmc_get_xtal_freq(void); #define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h index 8188fbdb84..ec64eec46f 100644 --- a/src/soc/intel/tigerlake/include/soc/ramstage.h +++ b/src/soc/intel/tigerlake/include/soc/ramstage.h @@ -9,6 +9,7 @@ #include void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config); void soc_init_pre_device(void *chip_info); #endif diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index bd6096b7a3..3772db4bc1 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -5,11 +5,9 @@ #include -/* Provide a callback to allow mainboard to override the DRAM part number. */ -bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void); /* Board type */ enum board_type { diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 3e438430da..437356d5e0 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,46 +15,40 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4 -#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; #define V_P2SB_CFG_IBDF_BUS 0 diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 247b0ba554..69b5ca89a7 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _SOC_USB_H_ #define _SOC_USB_H_ @@ -132,7 +131,7 @@ struct usb3_port_config { #define USB3_PORT_DEFAULT(pin) { \ .enable = 1, \ .ocpin = (pin), \ - .tx_de_emp = 0x0, \ + .tx_de_emp = 0x29, \ .tx_downscale_amp = 0x00, \ } diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 5bcd6d8638..0c6f0b0f88 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -1,8 +1,4 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include @@ -439,3 +435,20 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +} diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index befc4fc48b..f2ff483af1 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -11,7 +11,6 @@ * Chapter number: 4 */ - #define __SIMPLE_DEVICE__ #include @@ -163,7 +162,6 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } - uint32_t *soc_pmc_etr_addr(void) { return (uint32_t *)(soc_read_pmc_base() + ETR); diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c index d37ff5407a..1f7ea3c180 100644 --- a/src/soc/intel/tigerlake/reset.c +++ b/src/soc/intel/tigerlake/reset.c @@ -11,7 +11,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset(GLOBAL_RESET)) + if (cse_request_global_reset()) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 662ca06928..dc9caee9fb 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -3,8 +3,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -17,19 +19,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) { unsigned int i; - uint32_t mask = 0; + uint32_t cpu_id, mask = 0; const struct device *dev; + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -64,7 +63,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; @@ -75,7 +74,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - if (dev && dev->enabled && config->TraceHubMode) { + if (is_dev_enabled(dev) && config->TraceHubMode) { m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; m_cfg->PchTraceHubMode = config->TraceHubMode; m_cfg->CpuTraceHubMode = config->TraceHubMode; @@ -86,10 +85,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (!dev || !dev->enabled) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = 1; + m_cfg->PchIshEnable = is_dev_enabled(dev); + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; @@ -118,39 +117,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - if (dev) - m_cfg->TcssDma0En = dev->enabled; - else - m_cfg->TcssDma0En = 0; + m_cfg->TcssDma0En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); - if (dev) - m_cfg->TcssDma1En = dev->enabled; - else - m_cfg->TcssDma1En = 0; + m_cfg->TcssDma1En = is_dev_enabled(dev); /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - if (dev) - m_cfg->TcssItbtPcie0En = dev->enabled; - else - m_cfg->TcssItbtPcie0En = 0; + m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT1); - if (dev) - m_cfg->TcssItbtPcie1En = dev->enabled; - else - m_cfg->TcssItbtPcie1En = 0; + m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TBT2); - if (dev) - m_cfg->TcssItbtPcie2En = dev->enabled; - else - m_cfg->TcssItbtPcie2En = 0; + m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT3); - if (dev) - m_cfg->TcssItbtPcie3En = dev->enabled; - else - m_cfg->TcssItbtPcie3En = 0; + m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); /* Hyper Threading */ m_cfg->HyperThreading = !config->HyperThreadingDisable; @@ -166,10 +149,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_dev_enabled(dev); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; @@ -181,19 +161,43 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + /* IPU configuration */ + dev = pcidev_path_on_root(SA_DEVFN_IPU); + m_cfg->SaIpuEnable = is_dev_enabled(dev); + /* Vt-D config */ - m_cfg->VtdDisable = 0; - m_cfg->VtdIgdEnable = 0x1; - m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; - m_cfg->VtdIpuEnable = 0x1; - m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; - m_cfg->VtdIopEnable = 0x1; - m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; - m_cfg->VtdItbtEnable = 0x1; - m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; - m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; - m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; - m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) { + /* Disable VT-d support for pre-QS platform */ + m_cfg->VtdDisable = 1; + } else { + /* Enable VT-d support for QS platform */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIopEnable = 0x1; + + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + + if (m_cfg->SaIpuEnable) { + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + } + + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + + if (m_cfg->TcssDma0En || m_cfg->TcssDma1En) + m_cfg->VtdItbtEnable = 0x1; + if (m_cfg->TcssItbtPcie0En) + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + if (m_cfg->TcssItbtPcie1En) + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + if (m_cfg->TcssItbtPcie2En) + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + if (m_cfg->TcssItbtPcie3En) + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; + } /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); @@ -203,6 +207,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c index 9fd8a1e43e..d3c2554425 100644 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -3,7 +3,7 @@ #include #include -void pch_init(void) +void romstage_pch_init(void) { /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 54632383eb..1fa6c2d180 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -21,12 +21,6 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } -bool __weak mainboard_get_dram_part_num(const char **part_num, size_t *len) -{ - /* Default weak implementation, no need to override part number. */ - return false; -} - /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -42,7 +36,7 @@ static void save_dimm_info(void) FSP_SMBIOS_MEMORY_INFO_GUID; const uint8_t *serial_num; const char *dram_part_num = NULL; - size_t dram_part_num_len; + size_t dram_part_num_len = 0; bool is_dram_part_overridden = false; /* Locate the memory info HOB, presence validated by raminit */ @@ -66,8 +60,11 @@ static void save_dimm_info(void) memset(mem_info, 0, sizeof(*mem_info)); /* Allow mainboard to override DRAM part number. */ - is_dram_part_overridden = mainboard_get_dram_part_num(&dram_part_num, - &dram_part_num_len); + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) { + dram_part_num_len = strlen(dram_part_num); + is_dram_part_overridden = true; + } /* Save available DIMM information */ index = 0; @@ -131,7 +128,7 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 664ea6cfe4..e75e884464 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -17,7 +18,6 @@ #include #include #include -#include static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -138,8 +138,24 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Make appropriate changes to the save state map. */ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + /* + * The SMRR MSRs are core-level registers, so if two threads that share + * a core try to both set the lock bit (in the same physical register), + * a #GP will be raised on the second write to that register (which is + * exactly what the lock is supposed to do), therefore secondary threads + * should exit here. + */ + if (intel_ht_sibling()) + return; + /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); + + /* Set Lock bit if supported */ + if (mtrr_cap.lo & SMRR_LOCK_SUPPORTED) + relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; + + /* Write SMRRs if supported */ if (mtrr_cap.lo & SMRR_SUPPORTED) write_smrr(relo_params); } @@ -233,15 +249,3 @@ void smm_relocate(void) else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-1.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-1.hex new file mode 100644 index 0000000000..32d141f21f --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-1.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex new file mode 100644 index 0000000000..85b203599b --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-3.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-3.hex new file mode 100644 index 0000000000..d2869eab1b --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-3.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-4.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-4.hex new file mode 100644 index 0000000000..b6769928da --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-4.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 FC 3F 00 00 6D 6D 6D 11 00 6D F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-5.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-5.hex new file mode 100644 index 0000000000..d72bf1ed05 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-5.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 A8 18 2B 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 B5 00 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-6.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-6.hex new file mode 100644 index 0000000000..71cfff96d5 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-6.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-7.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-7.hex new file mode 100644 index 0000000000..7f92cd8529 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-7.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-8.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-8.hex new file mode 100644 index 0000000000..aca688e99d --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-8.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex new file mode 100644 index 0000000000..1ce7c21d4c --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt new file mode 100644 index 0000000000..21565c66b6 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -0,0 +1,16 @@ +H5AN8G6NDJR-XNC,ddr4-spd-1.hex +MT40A512M16TB-062E:J,ddr4-spd-1.hex +H5ANAG6NCMR-XNC,ddr4-spd-2.hex +HMA851S6CJR6N-VK,ddr4-spd-3.hex +K4A8G165WC-BCTD,ddr4-spd-3.hex +H5AN8G6NCJR-VKC,ddr4-spd-3.hex +MT40A1G16KNR-075:E,ddr4-spd-4.hex +K4AAG165WB-MCTD,ddr4-spd-5.hex +H5ANAG6NCMR-VKC,ddr4-spd-6.hex +K4A8G165WC-BCWE,ddr4-spd-1.hex +MT40A1G16KD-062E:E,ddr4-spd-7.hex +K4AAG165WA-BCWE,ddr4-spd-7.hex +H5AN8G6NCJR-XNC,ddr4-spd-1.hex +K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-1.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-1.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x/spd-1.hex rename to src/soc/intel/tigerlake/spd/lp4x-spd-1.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-2.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-2.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x/spd-2.hex rename to src/soc/intel/tigerlake/spd/lp4x-spd-2.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-3.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-3.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x/spd-3.hex rename to src/soc/intel/tigerlake/spd/lp4x-spd-3.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-4.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-4.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x/spd-4.hex rename to src/soc/intel/tigerlake/spd/lp4x-spd-4.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd-5.hex b/src/soc/intel/tigerlake/spd/lp4x-spd-5.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x/spd-5.hex rename to src/soc/intel/tigerlake/spd/lp4x-spd-5.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt deleted file mode 100644 index f57b372bac..0000000000 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ /dev/null @@ -1,15 +0,0 @@ -H9HCNNNBKMMLXR-NEE,spd-1.hex -H9HCNNNFAMMLXR-NEE,spd-2.hex -K4U6E3S4AA-MGCL,spd-1.hex -K4UBE3D4AA-MGCL,spd-3.hex -MT53E1G32D2NP-046 WT:A,spd-4.hex -H9HKNNNCRMBVAR-NEH,spd-1.hex -MT53E1G64D4SQ-046 WT:A,spd-4.hex -MT53E512M32D2NP-046 WT:F,spd-1.hex -NT6AP256T32AV-J2,spd-5.hex -K4U6E3S4AA-MGCR,spd-1.hex -MT53E512M32D2NP-046 WT:E,spd-1.hex -H9HCNNNCPMMLXR-NEE,spd-3.hex -K4UBE3D4AA-MGCR,spd-3.hex -MT53E512M64D4NW-046 WT:E,spd-1.hex -MT53E1G64D8NW-046 WT:E,spd-3.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt new file mode 100644 index 0000000000..70877d2c35 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -0,0 +1,15 @@ +H9HCNNNBKMMLXR-NEE,lp4x-spd-1.hex +H9HCNNNFAMMLXR-NEE,lp4x-spd-2.hex +K4U6E3S4AA-MGCL,lp4x-spd-1.hex +K4UBE3D4AA-MGCL,lp4x-spd-3.hex +MT53E1G32D2NP-046 WT:A,lp4x-spd-4.hex +H9HKNNNCRMBVAR-NEH,lp4x-spd-1.hex +MT53E1G64D4SQ-046 WT:A,lp4x-spd-4.hex +MT53E512M32D2NP-046 WT:F,lp4x-spd-1.hex +NT6AP256T32AV-J2,lp4x-spd-5.hex +K4U6E3S4AA-MGCR,lp4x-spd-1.hex +MT53E512M32D2NP-046 WT:E,lp4x-spd-1.hex +H9HCNNNCPMMLXR-NEE,lp4x-spd-3.hex +K4UBE3D4AA-MGCR,lp4x-spd-3.hex +MT53E512M64D4NW-046 WT:E,lp4x-spd-1.hex +MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex diff --git a/src/soc/intel/tigerlake/spd/placeholder.spd.hex b/src/soc/intel/tigerlake/spd/placeholder.spd.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/src/soc/intel/tigerlake/spd/placeholder.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index e428365c4d..29487a8c81 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -78,13 +78,18 @@ void soc_systemagent_init(struct device *dev) * differentiated here based on SA PCI ID. */ switch (sa_pci_id) { - case PCI_DEVICE_ID_INTEL_TGL_ID_U: - case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: - soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; - break; case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE]; break; + case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2: + soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2: + soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE]; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2: + soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE]; + break; default: printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits " "configuration\n", sa_pci_id); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 8a9bf1e7eb..e449409c4f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -9,12 +9,15 @@ config XEON_SP_COMMON_BASE config SOC_INTEL_SKYLAKE_SP bool select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_0 help Intel Skylake-SP support config SOC_INTEL_COOPERLAKE_SP bool select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_2 + select CACHE_MRC_SETTINGS help Intel Cooperlake-SP support @@ -22,16 +25,11 @@ if XEON_SP_COMMON_BASE config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_RAMSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES - select POSTCAR_CONSOLE + select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET - select PLATFORM_USES_FSP2_0 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP select FSP_M_XIP @@ -39,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select IOAPIC select PARALLEL_MP select ACPI_NO_SMI_GNVS - select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -69,7 +66,6 @@ config USE_FSP2_0_DRIVER depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 select UDK_202005_BINDING - select POSTCAR_CONSOLE select POSTCAR_STAGE config MAX_SOCKET diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 94c1764659..3bbf6b725e 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -8,6 +8,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/pch_irq.asl b/src/soc/intel/xeon_sp/acpi/pch_irq.asl new file mode 100644 index 0000000000..f36968f9cd --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pch_irq.asl @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * PCH devices PCI interrupt routing packages. + * + * Note: The PCH routing PR10-PR68 and AR10-AR68 are defined in uncore_irq.asl + * + * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. + * The mapping fields ae Address, Pin, Source, Source Index. + */ + +// Socket 0, IIOStack 0 device legacy interrupt routing +Name (PR00, Package () +{ + // [DMI0]: Legacy PCI Express Port 0 + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, + // [CB0A]: CBDMA + // [CB0E]: CBDMA + Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, + // [CB0B]: CBDMA + // [CB0F]: CBDMA + Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, + // [CB0C]: CBDMA + // [CB0G]: CBDMA + Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, + // [CB0D]: CBDMA + // [CB0H]: CBDMA + Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, + // Uncore 0 UBOX Device + Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, + // [DISP]: Display Controller + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, + // [IHC2]: HECI #2 + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, + // // [XHCI]: xHCI controller 1 on PCH + Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, + // [TERM]: Thermal Subsystem on PCH + Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, + // [CAMR]: Camera IO Host Controller on PCH + Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, + // [HEC2]: HECI #2 on PCH + Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, + // [IDER]: ME IDE redirect on PCH + Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, + // [MEKT]: MEKT on PCH + Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, + // [SAT1]: SATA controller 1 on PCH + Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, + // [NAN1]: NAND Cycle Router on PCH + Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, + // [RP17]: PCIE PCH Root Port #17 + Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, + // [RP18]: PCIE PCH Root Port #18 + Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, + // [RP19]: PCIE PCH Root Port #19 + Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, + // [RP20]: PCIE PCH Root Port #20 + Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, + // [UAR0]: UART #0 on PCH + Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, + // [UAR1]: UART #1 on PCH + Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, +}) + +// Socket 0, IIOStack 0 device IOAPIC interrupt routing +Name (AR00, Package () +{ + // [DMI0]: Legacy PCI Express Port 0 + Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, + // [CB0A]: CB3DMA + // [CB0E]: CB3DMA + Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, + // [CB0B]: CB3DMA + // [CB0F]: CB3DMA + Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, + // [CB0C]: CB3DMA + // [CB0G]: CB3DMA + Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // [CB0D]: CB3DMA + // [CB0H]: CB3DMA + Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // [UBX0]: Uncore 0 UBOX Device + Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, + // [DISP]: Display Controller + Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, + // [IHC2]: HECI #2 + Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, + // [XHCI]: xHCI controller 1 on PCH + Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, + // [TERM]: Thermal Subsystem on PCH + Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, + // [CAMR]: Camera IO Host Controller on PCH + Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, + // [HEC2]: HECI #2 on PCH + Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, + // [IDER]: ME IDE redirect on PCH + Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, + // [MEKT]: MEKT on PCH + Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, + // [SAT1]: SATA controller 1 on PCH + Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, + // [NAN1]: NAND Cycle Router on PCH + Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, + // [RP17]: PCIE PCH Root Port #17 + Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, + // [RP18]: PCIE PCH Root Port #18 + Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, + // [RP19]: PCIE PCH Root Port #19 + Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, + // [RP20]: PCIE PCH Root Port #20 + Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, + // [UAR0]: UART #0 on PCH + Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, + // [UAR1]: UART #1 on PCH + Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, +}) diff --git a/src/soc/intel/xeon_sp/acpi/pci_irqs.asl b/src/soc/intel/xeon_sp/acpi/pci_irqs.asl new file mode 100644 index 0000000000..eccb46b93d --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pci_irqs.asl @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 + * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 + * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 + * + * PIRQ routing control is in PCR ITSS region. + */ + +OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + +Name (PRSA, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,7,10,11,12,14,15} +}) +Alias (PRSA, PRSB) +Name (PRSC, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,10,11,12,14,15} +}) +Alias (PRSC, PRSD) +Alias (PRSA, PRSE) +Alias (PRSA, PRSF) +Alias (PRSA, PRSG) +Alias (PRSA, PRSH) + +MAKE_LINK_DEV(A,1) +MAKE_LINK_DEV(B,2) +MAKE_LINK_DEV(C,3) +MAKE_LINK_DEV(D,4) +MAKE_LINK_DEV(E,5) +MAKE_LINK_DEV(F,6) +MAKE_LINK_DEV(G,7) +MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl rename to src/soc/intel/xeon_sp/acpi/southcluster.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl similarity index 87% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore.asl rename to src/soc/intel/xeon_sp/acpi/uncore.asl index b1b5f6c624..8d178cbb6b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/acpi/uncore.asl @@ -26,7 +26,8 @@ Scope(\) Scope (\_SB) { - #include "pci_irq.asl" + #include "pci_irqs.asl" + #include "pch_irq.asl" /* TODO: Move to PCH asl. */ #include "uncore_irq.asl" #include "iiostack.asl" } diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl similarity index 51% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/acpi/uncore_irq.asl index 0505152a29..e8d1b14c67 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl @@ -1,235 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + /* * Uncore devices PCI interrupt routing packages. + * + * Note: The PCH routing PR00 and AR00 are defined in pch_irq.asl + * * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. * The mapping fields ae Address, Pin, Source, Source Index. */ -#define GEN_PCIE_LEGACY_IRQ() \ - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ - Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ - Package () { 0x0003FFFF, 0x03, LNKD, 0x00 } - -#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package () { ##dev, 0x00, LNKA, 0x00 }, \ - Package () { ##dev, 0x01, LNKB, 0x00 }, \ - Package () { ##dev, 0x02, LNKC, 0x00 }, \ - Package () { ##dev, 0x03, LNKD, 0x00 } - -#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \ - Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \ - Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \ - Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \ - Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 } - -#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package () { ##dev, 0x00, 0x00, ##irq1 }, \ - Package () { ##dev, 0x01, 0x00, ##irq2 }, \ - Package () { ##dev, 0x02, 0x00, ##irq3 }, \ - Package () { ##dev, 0x03, 0x00, ##irq4 } - -// Socket 0, IIOStack 0 device legacy interrupt routing -Name (PR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - // [CB0A]: CBDMA - // [CB0E]: CBDMA - Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, - // [CB0B]: CBDMA - // [CB0F]: CBDMA - Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, - // [CB0C]: CBDMA - // [CB0G]: CBDMA - Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, - // [CB0D]: CBDMA - // [CB0H]: CBDMA - Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, - // Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - // // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, -}) - -// Socket 0, IIOStack 0 device IOAPIC interrupt routing -Name (AR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, - // [CB0A]: CB3DMA - // [CB0E]: CB3DMA - Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, - // [CB0B]: CB3DMA - // [CB0F]: CB3DMA - Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, - // [CB0C]: CB3DMA - // [CB0G]: CB3DMA - Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, - // [CB0D]: CB3DMA - // [CB0H]: CB3DMA - Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, - // [UBX0]: Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, - // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, -}) - // Socket 0, IIOStack 1 device legacy interrupt routing -Name (PR10, Package (0x40) +Name (PR10, Package () { // PCI Express Port 1A-1D GEN_PCIE_LEGACY_IRQ(), @@ -263,7 +46,7 @@ Name (PR10, Package (0x40) }) // Socket 0, IIOStack 1 device IOAPIC interrupt routing -Name (AR10, Package (0x40) +Name (AR10, Package () { // PCI Express Port A-D GEN_PCIE_IOAPIC_IRQ(0x27,0x21,0x22,0x23), @@ -297,7 +80,7 @@ Name (AR10, Package (0x40) }) // Socket 0, IIOStack 2 device legacy interrupt routing -Name (PR20, Package (0x24) +Name (PR20, Package () { // PCI Express Port A-D on PC02 GEN_PCIE_LEGACY_IRQ(), @@ -326,7 +109,7 @@ Name (PR20, Package (0x24) }) // Socket 0, IIOStack 2 device IOAPIC interrupt routing -Name (AR20, Package (0x24) +Name (AR20, Package () { // PCI Express Port A-D on PC02 GEN_PCIE_IOAPIC_IRQ(0x2F,0x29,0x2A,0x2B), @@ -355,7 +138,7 @@ Name (AR20, Package (0x24) }) // Socket 0, IIOStack 3 device legacy interrupt routing -Name (PR28, Package (0x20) +Name (PR28, Package () { // PCI Express Port 3 on PC03 GEN_PCIE_LEGACY_IRQ(), @@ -379,7 +162,7 @@ Name (PR28, Package (0x20) }) // Socket 0, IIOStack 3 device IOAPIC interrupt routing -Name (AR28, Package (0x20) +Name (AR28, Package () { // PCI Express Port 3 A-D on PC03 GEN_PCIE_IOAPIC_IRQ(0x37,0x31,0x32,0x33), @@ -403,7 +186,7 @@ Name (AR28, Package (0x20) }) // Socket 1, IIOStack 0 device legacy interrupt routing -Name (PR40, Package (0x09) +Name (PR40, Package () { // DMI Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, @@ -416,7 +199,7 @@ Name (PR40, Package (0x09) }) // Socket 1, IIOStack 0 device IOAPIC interrupt routing -Name (AR40, Package (0x09) +Name (AR40, Package () { // DMI Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, @@ -429,7 +212,7 @@ Name (AR40, Package (0x09) }) // Socket 1, IIOStack 1 device legacy interrupt routing -Name (PR50, Package (0x40) +Name (PR50, Package () { // PCI Express Port GEN_PCIE_LEGACY_IRQ(), @@ -455,7 +238,7 @@ Name (PR50, Package (0x40) }) // Socket 1, IIOStack 1 device IOAPIC interrupt routing -Name (AR50, Package (0x40) +Name (AR50, Package () { // PCI Express Port A-D GEN_PCIE_IOAPIC_IRQ(0x57,0x51,0x52,0x53), @@ -481,7 +264,7 @@ Name (AR50, Package (0x40) }) // Socket 1, IIOStack 2 device legacy interrupt routing -Name (PR60, Package (0x24) +Name (PR60, Package () { // PCI Express Port GEN_PCIE_LEGACY_IRQ(), @@ -500,7 +283,7 @@ Name (PR60, Package (0x24) }) // Socket 1, IIOStack 2 device IOAPIC interrupt routing -Name (AR60, Package (0x24) +Name (AR60, Package () { // PCI Express Port A-D GEN_PCIE_IOAPIC_IRQ(0x5F,0x59,0x5A,0x5B), @@ -519,7 +302,7 @@ Name (AR60, Package (0x24) }) // Socket 1, IIOStack 3 device legacy interrupt routing -Name (PR68, Package (0x20) +Name (PR68, Package () { // PCI Express Port GEN_PCIE_LEGACY_IRQ(), @@ -535,7 +318,7 @@ Name (PR68, Package (0x20) }) // Socket 1, IIOStack 3 device legacy interrupt routing -Name (AR68, Package (0x20) +Name (AR68, Package () { // PCI Express Port A-D GEN_PCIE_IOAPIC_IRQ(0x67,0x61,0x62,0x63), diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 9c6450e73c..975afc9e26 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,10 +2,6 @@ if SOC_INTEL_COOPERLAKE_SP -config MAINBOARD_USES_FSP2_0 - bool - default y - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -19,24 +15,34 @@ config MAX_CPUS int default 255 +config CPU_ADDR_BITS + int + default 46 + config PCR_BASE_ADDRESS hex default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. -# currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe9a0000 + default 0xfe8b0000 config DCACHE_RAM_SIZE hex - default 0x60000 + default 0x170000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x10000 + default 0xA0000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. It needs to include FSP-M stack requirement and + CB romstage stack requirement. config CPU_MICROCODE_CBFS_LOC hex @@ -54,10 +60,14 @@ config HEAP_SIZE hex default 0x80000 +config STACK_SIZE + hex + default 0x4000 + config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0x70000 + default 0xA0000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know @@ -66,6 +76,19 @@ config FSP_TEMP_RAM_SIZE config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y -select CACHE_MRC_SETTINGS +config CPU_BCLK_MHZ + int + default 100 + +# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel +# Default value is set to one socket, full config. +config DIMM_MAX + int + default 12 + +# DDR4 +config DIMM_SPD_SIZE + int + default 512 endif diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 969fe252e5..79a83b5416 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,11 +8,11 @@ subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c +romstage-y += romstage.c ddr.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += chip.c acpi.c cpu.c soc_util.c +ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c soc_acpi.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 257494a946..a1ebc4ae92 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -23,127 +25,41 @@ #include "chip.h" -#define SCI_INT_NUM 9 - -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp) +static int acpi_sci_irq(void) { - current = acpi_write_hpet(device, current, rsdp); - current = (ALIGN(current, 16)); - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; -} + int sci_irq = 9; + uint32_t scis; -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); - return current; -} + scis = soc_read_sci_irq_select(); + scis &= SCI_IRQ_SEL; + scis >>= SCI_IRQ_ADJUST; -static void uncore_inject_dsdt(void) -{ - struct iiostack_resource stack_info = {0}; - - get_iiostack_info(&stack_info); - - acpigen_write_scope("\\_SB"); - - for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - char rtname[16]; - - snprintf(rtname, sizeof(rtname), "RT%02x", stack); - - acpigen_write_name(rtname); - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", - rtname, stack); - - acpigen_write_resourcetemplate_header(); - - /* bus resource */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, - 0x0, (ri->BusLimit - ri->BusBase + 1)); - - /* additional io resources on socket 0 bus 0 */ - if (stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); - } - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - /* additional mem32 resources on socket 0 bus 0 */ - if (stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, - (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, - VGA_BASE_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, - ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - - acpigen_write_resourcetemplate_footer(); - } - acpigen_pop_len(); -} - -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; } - if (gnvs) { - acpi_create_gnvs(gnvs); - /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); - acpigen_pop_len(); - } - - /* Add IIOStack ACPI Resource Templates */ - uncore_inject_dsdt(); -} - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; } static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci = SCI_INT_NUM; + int sci = acpi_sci_irq(); uint16_t flags = MP_IRQ_TRIGGER_LEVEL; /* INT_SRC_OVR */ @@ -160,32 +76,13 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -static unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) -{ - struct device *cpu; - uint8_t num_cpus = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - num_cpus, cpu->path.apic.apic_id); - num_cpus++; - } - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { int cur_index; struct iiostack_resource stack_info = {0}; - int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + /* With CPX-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ + int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; /* Local APICs */ @@ -231,6 +128,112 @@ unsigned long acpi_fill_madt(unsigned long current) return acpi_madt_irq_overrides(current); } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->header.revision = get_acpi_table_revision(FADT); + + fadt->sci_int = acpi_sci_irq(); + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; + + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; +} + +unsigned long southbridge_write_acpi_tables(const struct device *device, + unsigned long current, struct acpi_rsdp *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = (ALIGN(current, 16)); + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} + +void southbridge_inject_dsdt(const struct device *device) +{ + struct global_nvs *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ + // apm_control(APM_CNT_GNVS_UPDATE); + + /* Add it to DSDT. */ + printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } + + /* Add IIOStack ACPI Resource Templates */ + uncore_inject_dsdt(); +} + +int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; @@ -255,7 +258,8 @@ void generate_cpu_entries(const struct device *device) /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - /* TODO: Soc specific power states generation */ + /* Generate P-state tables */ + cpx_generate_p_state_entries(core_id, threads_per_package); acpigen_pop_len(); } } @@ -265,211 +269,3 @@ void generate_cpu_entries(const struct device *device) /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(threads_per_package); } - -int soc_madt_sci_irq_polarity(int sci) -{ - if (sci >= 20) - return MP_IRQ_POLARITY_LOW; - else - return MP_IRQ_POLARITY_HIGH; -} - -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = SCI_INT_NUM; - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - - fadt->duty_offset = 1; - fadt->day_alrm = 0xd; - - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; -} - -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - unsigned int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; - - memory_map = get_system_memory_map(); - assert(memory_map != NULL); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - unsigned int nodes = xeon_sp_get_socket_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8 + nodes * nodes; - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - return current; -} diff --git a/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl deleted file mode 100644 index b2a2ebf850..0000000000 --- a/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 - * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 - * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 - * - * PIRQ routing control is in PCR ITSS region. - */ - -OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + - CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) -Field (ITSS, ByteAcc, NoLock, Preserve) -{ - PIRA, 8, /* PIRQA Routing Control */ - PIRB, 8, /* PIRQB Routing Control */ - PIRC, 8, /* PIRQC Routing Control */ - PIRD, 8, /* PIRQD Routing Control */ - PIRE, 8, /* PIRQE Routing Control */ - PIRF, 8, /* PIRQF Routing Control */ - PIRG, 8, /* PIRQG Routing Control */ - PIRH, 8, /* PIRQH Routing Control */ -} - -Name (IREN, 0x80) /* Interrupt Routing Enable */ -Name (IREM, 0x0f) /* Interrupt Routing Mask */ - -Name (PRSA, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} -}) -Alias (PRSA, PRSB) -Name (PRSC, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,10,11,12,14,15} -}) -Alias (PRSC, PRSD) -Alias (PRSA, PRSE) -Alias (PRSA, PRSF) -Alias (PRSA, PRSG) -Alias (PRSA, PRSH) - -#define MAKE_LINK_DEV(id,uid) \ - Device (LNK##id) \ - { \ - Name (_HID, EISAID ("PNP0C0F")) \ - Name (_UID, ##uid) \ - Method (_PRS, 0, NotSerialized) \ - { \ - Return (PRS##id) \ - } \ - Method (_CRS, 0, Serialized) \ - { \ - Name (RTLA, ResourceTemplate () \ - { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ - \ - /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ - Return (RTLA) \ - } \ - Method (_SRS, 1, Serialized) \ - { \ - CreateWordField (Arg0, 1, IRQ0) \ - FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ - } \ - Method (_STA, 0, Serialized) \ - { \ - If (And (^^PIR##id, ^^IREN)) { \ - Return (0x9) \ - } Else { \ - Return (0xb) \ - } \ - } \ - Method (_DIS, 0, Serialized) \ - { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ - } \ - } - -MAKE_LINK_DEV(A,1) -MAKE_LINK_DEV(B,2) -MAKE_LINK_DEV(C,3) -MAKE_LINK_DEV(D,4) -MAKE_LINK_DEV(E,5) -MAKE_LINK_DEV(F,6) -MAKE_LINK_DEV(G,7) -MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index c3159feec3..11fe44b1b2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -450,7 +451,6 @@ static void xeonsp_pci_domain_read_resources(struct device *dev) } } - /* assign resources */ assign_stack_resources(&stack_info, dev, NULL); @@ -493,11 +493,23 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* not implemented yet */ } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PC00"; + return NULL; +} +#endif + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &xeonsp_cpx_pci_domain_set_resources, .scan_bus = &xeonsp_cpx_pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, + .acpi_name = soc_acpi_name +#endif }; static struct device_operations cpu_bus_ops = { @@ -546,27 +558,6 @@ static void attach_iio_stacks(struct device *dev) DEV_FUNC_EXIT(dev); } -static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - - set_ioapic_id((void *)IO_APIC_ADDR, 2); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); - - reg32 &= ~0x00ff0000; - reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 1, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 3, 1); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -593,7 +584,7 @@ static void chip_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); - pch_enable_ioapic(NULL); + pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); } diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e46f34f653..e7c146c291 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -84,8 +84,8 @@ struct soc_intel_xeon_sp_cpx_config { uint32_t pstate_req_ratio; - uint32_t coherency_support; - uint32_t ats_support; + uint8_t vtd_support; + uint8_t x2apic; /* Generic IO decode ranges */ uint32_t gen1_dec; @@ -99,4 +99,10 @@ struct soc_intel_xeon_sp_cpx_config { typedef struct soc_intel_xeon_sp_cpx_config config_t; +/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ +void cpx_generate_p_state_entries(int core, int cores_per_package); +int calculate_power(int tdp, int p1_ratio, int ratio); +void uncore_inject_dsdt(void); +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); + #endif diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 1df5c1350c..0999f6d721 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -16,6 +16,7 @@ #include #include #include "chip.h" +#include static const void *microcode_patch; @@ -44,7 +45,6 @@ static void xeon_configure_mca(void) mca_configure(); } - void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_mp_current_microcode(); @@ -64,6 +64,18 @@ static void each_cpu_init(struct device *cpu) __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); setup_lapic(); + /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; @@ -80,6 +92,9 @@ static void each_cpu_init(struct device *cpu) /* Clear out pending MCEs */ xeon_configure_mca(); + + /* Enable Vmx */ + set_vmx_and_lock(); } static struct device_operations cpu_dev_ops = { @@ -88,6 +103,7 @@ static struct device_operations cpu_dev_ops = { static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A1}, {0, 0}, }; @@ -119,7 +135,7 @@ static void set_max_turbo_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); FUNC_EXIT(); } diff --git a/src/soc/intel/xeon_sp/cpx/ddr.c b/src/soc/intel/xeon_sp/cpx/ddr.c new file mode 100644 index 0000000000..0fa36ab6c9 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ddr.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +uint32_t get_ddr_voltage(uint8_t DdrVoltage) +{ + /* SPD Byte 11: Module Nominal Voltage, currently DDR4 only supports 1.2V. + Either Bit 0 or Bit 1 is set, return 1.2V */ + if (DdrVoltage & 0x3) + return 1200; + return 0; +} + +uint16_t get_max_memory_speed(uint32_t commonTck) +{ + if (commonTck <= DDR_8400_TCK_MIN) + return 8400; + else if (commonTck <= DDR_6400_TCK_MIN) + return 6400; + else if (commonTck <= DDR_6000_TCK_MIN) + return 6000; + else if (commonTck <= DDR_5600_TCK_MIN) + return 5600; + else if (commonTck <= DDR_5200_TCK_MIN) + return 5200; + else if (commonTck <= DDR_4800_TCK_MIN) + return 4800; + else if (commonTck <= DDR_4400_TCK_MIN) + return 4400; + else if (commonTck <= DDR_4266_TCK_MIN) + return 4266; + else if (commonTck <= DDR_4200_TCK_MIN) + return 4200; + else if (commonTck <= DDR_4000_TCK_MIN) + return 4000; + else if (commonTck <= DDR_3800_TCK_MIN) + return 3800; + else if (commonTck <= DDR_3733_TCK_MIN) + return 3733; + else if (commonTck <= DDR_3600_TCK_MIN) + return 3600; + else if (commonTck <= DDR_3466_TCK_MIN) + return 3466; + else if (commonTck <= DDR_3400_TCK_MIN) + return 3400; + else if (commonTck <= DDR_3200_TCK_MIN) + return 3200; + else if (commonTck <= DDR_3000_TCK_MIN) + return 3000; + else if (commonTck <= DDR_2933_TCK_MIN) + return 2933; + else if (commonTck <= DDR_2800_TCK_MIN) + return 2800; + else if (commonTck <= DDR_2666_TCK_MIN) + return 2666; + else if (commonTck <= DDR_2600_TCK_MIN) + return 2600; + else if (commonTck <= DDR_2400_TCK_MIN) + return 2400; + else if (commonTck <= DDR_2200_TCK_MIN) + return 2200; + else if (commonTck <= DDR_2133_TCK_MIN) + return 2133; + else if (commonTck <= DDR_2000_TCK_MIN) + return 2000; + else if (commonTck <= DDR_1866_TCK_MIN) + return 1866; + else if (commonTck <= DDR_1800_TCK_MIN) + return 1800; + else if (commonTck <= DDR_1600_TCK_MIN) + return 1600; + else if (commonTck <= DDR_1400_TCK_MIN) + return 1400; + else if (commonTck <= DDR_1333_TCK_MIN) + return 1333; + else if (commonTck <= DDR_1200_TCK_MIN) + return 1200; + else if (commonTck <= DDR_1066_TCK_MIN) + return 1066; + else if (commonTck <= DDR_1000_TCK_MIN) + return 1000; + else + return 800; +} diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index 0263472fc0..b3ad455d67 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -5,11 +5,13 @@ #include #include #include +#include #include #include static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; +static const uint8_t fsp_hob_prevbooterr_guid[16] = FSP_PREV_BOOT_ERR_SRC_HOB_GUID; struct guid_name_map { const void *guid; @@ -19,6 +21,7 @@ struct guid_name_map { static const struct guid_name_map guid_names[] = { { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, + { fsp_hob_prevbooterr_guid, "FSP_PREV_BOOT_ERR_SRC_HOB_GUID" }, }; const char *soc_get_guid_name(const uint8_t *guid) @@ -33,9 +36,9 @@ const char *soc_get_guid_name(const uint8_t *guid) return NULL; } -static void soc_display_memmap_hob(const struct SystemMemoryMapHob *hob_addr) +static void soc_display_memmap_hob(const struct SystemMemoryMapHob **hob_addr) { - struct SystemMemoryMapHob *hob = (struct SystemMemoryMapHob *)hob_addr; + struct SystemMemoryMapHob *hob = (struct SystemMemoryMapHob *)*hob_addr; printk(BIOS_DEBUG, "================== MEMORY MAP HOB DATA ==================\n"); printk(BIOS_DEBUG, "hob: %p, structure size: 0x%lx\n", @@ -47,6 +50,7 @@ static void soc_display_memmap_hob(const struct SystemMemoryMapHob *hob_addr) printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n", hob->memSize, hob->memFreq); + printk(BIOS_DEBUG, "\tNumChPerMC: %d\n", hob->NumChPerMC); printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d, entry size: %ld\n", hob->numberEntries, sizeof(SYSTEM_MEMORY_MAP_ELEMENT)); for (int e = 0; e < hob->numberEntries; ++e) { @@ -56,6 +60,9 @@ static void soc_display_memmap_hob(const struct SystemMemoryMapHob *hob_addr) mem_element->ElementSize, mem_element->Type); } + printk(BIOS_DEBUG, "\tBiosFisVersion: 0x%x\n", hob->BiosFisVersion); + printk(BIOS_DEBUG, "\tMmiohBase: 0x%x\n", hob->MmiohBase); + hexdump(hob, sizeof(*hob)); } @@ -129,22 +136,16 @@ static void soc_display_iio_universal_data_hob(const IIO_UDS *hob) printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality); printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); - printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase); - printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base); printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit); printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base); printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit); - printk(BIOS_DEBUG, "\t\tPciResourceBusBase: 0x%x\n", - ri->PciResourceBusBase); - printk(BIOS_DEBUG, "\t\tPciResourceBusLimit: 0x%x\n", - ri->PciResourceBusLimit); - printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", - ri->PciResourceIoBase); - printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", - ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", ri->PciResourceMem32Base); printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", @@ -169,6 +170,55 @@ static void soc_display_iio_universal_data_hob(const IIO_UDS *hob) hexdump(hob, sizeof(*hob)); } +/* + * Display PREV_BOOT_ERR_SRC_HOB. Check various issues: + * a. Length field of the HOB needs to be more than 2. + * b. CPX-SP FSP only implements MC_BANK_INFO type. + * c. Type field (first field of each record) needs to be of enum ERROR_ACCESS_TYPE. + */ +static void soc_display_prevbooterr_hob(const PREV_BOOT_ERR_SRC_HOB *hob) +{ + printk(BIOS_DEBUG, "================ PREV_BOOT_ERR_SRC HOB DATA ================\n"); + printk(BIOS_DEBUG, "hob: %p, Length: 0x%x\n", hob, hob->Length); + + if (hob->Length <= 2) { + printk(BIOS_INFO, "PREV_BOOT_ERR_SRC_HOB does not have valid error record.\n"); + return; + } + + MCBANK_ERR_INFO *mcbinfo; + for (uint16_t len = 2; len < hob->Length; ) { + const uint8_t type = *(uint8_t *)((void *)hob + len); + switch (type) { + case McBankType: + printk(BIOS_DEBUG, "\t MCBANK ERR INFO:\n"); + mcbinfo = (MCBANK_ERR_INFO *)((void *)hob + len); + printk(BIOS_DEBUG, "\t\t Segment: %d, Socket: %d, ApicId: 0x%x\n", + mcbinfo->Segment, mcbinfo->Socket, mcbinfo->ApicId); + printk(BIOS_DEBUG, "\t\t McBankNum: 0x%x\n", mcbinfo->McBankNum); + printk(BIOS_DEBUG, "\t\t McBankStatus: 0x%llx\n", + mcbinfo->McBankStatus); + printk(BIOS_DEBUG, "\t\t McBankAddr: 0x%llx\n", mcbinfo->McbankAddr); + printk(BIOS_DEBUG, "\t\t McBankMisc: 0x%llx\n", mcbinfo->McBankMisc); + len += sizeof(MCBANK_ERR_INFO); + break; + case PciExType: + printk(BIOS_ERR, "\t PCI EX ERR INFO:\n"); + len += sizeof(PCI_EX_ERR_INFO); + break; + case CsrOtherType: + printk(BIOS_ERR, "\t CSR ERR INFO:\n"); + len += sizeof(CSR_ERR_INFO); + break; + default: + printk(BIOS_ERR, "\t illegal ERROR_ACCESS_TYPE:%d\n", type); + break; + } + } + + hexdump(hob, hob->Length); +} + void soc_display_hob(const struct hob_header *hob) { uint8_t *guid; @@ -181,5 +231,7 @@ void soc_display_hob(const struct hob_header *hob) if (fsp_guid_compare(guid, fsp_hob_iio_uds_guid)) soc_display_iio_universal_data_hob((const IIO_UDS *)(guid + 16)); else if (fsp_guid_compare(guid, fsp_hob_memmap_guid)) - soc_display_memmap_hob((const struct SystemMemoryMapHob *)(guid + 16)); + soc_display_memmap_hob((const struct SystemMemoryMapHob **)(guid + 16)); + else if (fsp_guid_compare(guid, fsp_hob_prevbooterr_guid)) + soc_display_prevbooterr_hob((const PREV_BOOT_ERR_SRC_HOB *)(guid + 16)); } diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 14580004d0..19f6e4c5d5 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,9 +7,7 @@ #include #define CPUID_COOPERLAKE_SP_A0 0x05065a - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 +#define CPUID_COOPERLAKE_SP_A1 0x05065b void cpx_init_cpus(struct device *dev); msr_t read_msr_ppin(void); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h new file mode 100644 index 0000000000..61a5ebe338 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/ddr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _CPX_DDR_H_ +#define _CPX_DDR_H_ + +#include + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +uint16_t get_max_memory_speed(uint32_t commonTck); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +#endif /* _CPX_DDR_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h b/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h deleted file mode 100644 index b66856174b..0000000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* not implemented, adding defaults just to make common code happy */ - -#ifndef _SOC_GPIO_H_ -#define _SOC_GPIO_H - -#define GPIO_NUM_PAD_CFG_REGS 0 -#define NUM_GPI_STATUS_REGS 0 - -#endif diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h deleted file mode 100644 index efd50577b6..0000000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h b/src/soc/intel/xeon_sp/cpx/include/soc/msr.h deleted file mode 100644 index 922bce94b6..0000000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_MSR_H_ -#define _SOC_MSR_H_ - -#include - -#define IA32_MCG_CAP 0x179 -#define IA32_MCG_CAP_COUNT_MASK 0xff -#define IA32_MCG_CAP_CTL_P_BIT 8 -#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) - -#define IA32_MCG_CTL 0x17b - -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) -#define MONIOR_ENABLE_BIT (1 << 18) - -#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 - -/* MSR_PKG_CST_CONFIG_CONTROL bits */ -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */ -/* No package C-state limit. All C-States supported by the processor are available. */ -#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) -#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) -#define IO_MWAIT_REDIRECTION_SHIFT 10 -#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) -#define CFG_LOCK_SHIFT 15 -#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) - -/* MSR_PMG_IO_CAPTURE_BASE bits */ -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ -#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) -#define CST_RANGE_SHIFT 16 /* 18:16 bits */ -#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) - -/* MSR_POWER_CTL bits */ -#define MSR_POWER_CTL 0x1fc -#define BIDIR_PROCHOT_ENABLE_SHIFT 0 -#define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) -#define FAST_BRK_SNP_ENABLE_SHIFT 3 -#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) -#define FAST_BRK_INT_ENABLE_SHIFT 4 -#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) -#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 -#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) -#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 -#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) -#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 -#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) -#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 -#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) -#define PROCHOT_LOCK_SHIFT 27 -#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) -#define LTR_IIO_DISABLE_SHIFT 29 -#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) - -/* MSR_IA32_PERF_CTRL (0x199) bits */ -#define MSR_IA32_PERF_CTRL 0x199 -#define PSTATE_REQ_SHIFT 8 /* 8:14 bits */ -#define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT) -#define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT) - -/* MSR_MISC_PWR_MGMT bits */ -#define MSR_MISC_PWR_MGMT 0x1aa -#define HWP_ENUM_SHIFT 6 -#define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT) -#define HWP_EPP_SHIFT 12 -#define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT) -#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13 -#define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT) -#define LOCK_THERM_INT_SHIFT 22 -#define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT) - -/* MSR_TURBO_RATIO_LIMIT bits */ -#define MSR_TURBO_RATIO_LIMIT 0x1ad - -/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */ -#define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae - -/* MSR_VR_CURRENT_CONFIG bits */ -#define MSR_VR_CURRENT_CONFIG 0x601 -#define CURRENT_LIMIT_LOCK_SHIFT 31 -#define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT) - -/* MSR_TURBO_ACTIVATION_RATIO bits */ -#define MSR_TURBO_ACTIVATION_RATIO 0x64c -#define MAX_NON_TURBO_RATIO_SHIFT 0 -#define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) - -/* MSR_ENERGY_PERF_BIAS_CONFIG bits */ -#define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01 -#define EPB_ENERGY_POLICY_SHIFT 3 -#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) - -/* MSR Protected Processor Inventory Number */ -#define MSR_PPIN_CTL 0x04e -#define MSR_PPIN_CTL_LOCK 0x1 -#define MSR_PPIN_CTL_ENABLE_SHIFT 1 -#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) -#define MSR_PPIN 0x04f -#define MSR_PPIN_CAP_SHIFT 23 -#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) - -#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 71c68cf885..965bb66088 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -71,36 +71,26 @@ #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 +/* CPU Devices */ +#define CBDMA_DEV_NUM 0x04 #define VMD_DEV_NUM 0x05 #define VMD_FUNC_NUM 0x05 +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 0x5 +#define VTD_FUNC 0x0 + #define APIC_DEV_NUM 0x05 #define APIC_FUNC_NUM 0x04 -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function - -#define PCH_IOAPIC_BUS_NUMBER 0x00 -#define PCH_IOAPIC_DEV_NUM 0x1F -#define PCH_IOAPIC_FUNC_NUM 0x00 /* PCH Device info */ #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 #define XHCI_FUNC_NUM 0x0 - -#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 - -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) @@ -112,15 +102,9 @@ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) - -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function - -#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 - -#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x04 +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 #define PCH_IOAPIC_BUS_NUMBER 0x00 #define PCH_IOAPIC_DEV_NUM 0x1F diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c new file mode 100644 index 0000000000..deb9030c20 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 9952d62d1c..6f47a30234 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -1,8 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include #include +#include +#include +#include +#include #include +#include +#include +#include + #include "chip.h" void __weak mainboard_memory_init_params(FSPM_UPD *mupd) @@ -10,19 +21,91 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) /* Default weak implementation */ } +static const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; + + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ + assert(memmap_addr != NULL && hob_size != 0); + /* assert the pointer to the hob is not NULL */ + assert(*memmap_addr != NULL); + + return *memmap_addr; +} + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const struct SystemMemoryMapHob *hob; + MEMMAP_DIMM_DEVICE_INFO_STRUCT src_dimm; + int dimm_max, index = 0; + uint32_t vdd_voltage; + + hob = get_system_memory_map(); + assert(hob != NULL); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + dimm_max = ARRAY_SIZE(mem_info->dimm); + vdd_voltage = get_ddr_voltage(hob->DdrVoltage); + /* For now only implement for one socket and hard-coded for DDR4 */ + for (int ch = 0; ch < MAX_CH; ch++) { + for (int dimm = 0; dimm < MAX_IMC; dimm++) { + src_dimm = hob->Socket[0].ChannelInfo[ch].DimmInfo[dimm]; + if (src_dimm.Present) { + if (index >= dimm_max) { + printk(BIOS_WARNING, "Too many DIMMs info for %s.\n", + __func__); + return; + } + dest_dimm = &mem_info->dimm[index]; + dest_dimm->max_speed_mts = + get_max_memory_speed(src_dimm.commonTck); + dest_dimm->configured_speed_mts = hob->memFreq; + dimm_info_fill(dest_dimm, + src_dimm.DimmSize << 6, + 0x1a, /* hard-coded memory device type as DDR4 */ + hob->memFreq, /* replaced by configured_speed_mts */ + src_dimm.NumRanks, + ch, /* for mainboard locator string override */ + dimm, /* for mainboard locator string override */ + (const char *)&src_dimm.PartNumber[0], + sizeof(src_dimm.PartNumber), + (const uint8_t *)&src_dimm.serialNumber[0], + 64, /* hard-coded for DDR4 data width */ + vdd_voltage, + true, /* hard-coded as ECC supported */ + src_dimm.VendorID, + src_dimm.actKeyByte2); + index++; + } + } + } + + /* Save available DIMM information */ + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; - FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; - - /* - * Currently FSP for CPX does not implement user-provided StackBase/Size - * properly. When KTI link needs to be trained, inter-socket communication - * library needs quite a bit of memory for its heap usage. However, location - * is hardcoded so this workaround is needed. - */ - arch_upd->StackBase = (void *) 0xfe930000; - arch_upd->StackSize = 0x70000; + const struct device *dev; + const config_t *config = config_of_soc(); /* ErrorLevel - 0 (disable) to 8 (verbose) */ m_cfg->DebugPrintLevel = 8; @@ -67,5 +150,18 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ m_cfg->PchAdrEn = 0x02; + /* Make all IIO PCIe ports and port menus visible */ + m_cfg->PEXPHIDE = 0x0; + m_cfg->HidePEXPMenu = 0x0; + + /* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is + 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */ + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + m_cfg->ThermalDeviceEnable = dev && dev->enabled; + + /* Enable VT-d according to DTB */ + m_cfg->VtdSupport = config->vtd_support; + m_cfg->X2apic = config->x2apic; + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c new file mode 100644 index 0000000000..db1d3d2bd2 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -0,0 +1,715 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* TODO: Check if the common/acpi weak function can be used */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); +} + +int soc_madt_sci_irq_polarity(int sci) +{ + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +uint32_t soc_read_sci_irq_select(void) +{ + struct device *dev = PCH_DEV_PMC; + + if (!dev) + return 0; + + return pci_read_config32(dev, PMC_ACPI_CNT); +} + +/* + * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() + * with a call from the common/function or find another way to call this at the correct place + */ +void uncore_inject_dsdt(void) +{ + struct iiostack_resource stack_info = {0}; + + get_iiostack_info(&stack_info); + + acpigen_write_scope("\\_SB"); + + for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { + const STACK_RES *ri = &stack_info.res[stack]; + char rtname[16]; + + snprintf(rtname, sizeof(rtname), "RT%02x", stack); + + acpigen_write_name(rtname); + printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", + rtname, stack); + + acpigen_write_resourcetemplate_header(); + + /* bus resource */ + acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, + 0x0, (ri->BusLimit - ri->BusBase + 1)); + + /* additional io resources on socket 0 bus 0 */ + if (stack == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); + + /* IO decode CF8-CFF */ + acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); + } + + /* IO resource */ + acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, + ri->PciResourceIoLimit, 0x0, + (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); + + /* additional mem32 resources on socket 0 bus 0 */ + if (stack == 0) { + acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, + (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, + VGA_BASE_SIZE); + acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, + (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, + SPI_BASE_SIZE); + } + + /* Mem32 resource */ + acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, + ri->PciResourceMem32Limit, 0x0, + (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); + + /* Mem64 resource */ + acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, + ri->PciResourceMem64Limit, 0x0, + (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); + + acpigen_write_resourcetemplate_footer(); + } + acpigen_pop_len(); +} + +/* To be renamed soc_power_states_generation() */ +void cpx_generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CONFIG_CPU_BCLK_MHZ; + //clock = 1; + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) +{ + struct device *cpu; + uint8_t num_cpus = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, + num_cpus, cpu->path.apic.apic_id); + num_cpus++; + } + + return current; +} + +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + unsigned int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + unsigned int mmap_index; + + memory_map = get_system_memory_map(); + assert(memory_map != NULL); + printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ + unsigned int nodes = xeon_sp_get_socket_count(); + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8 + nodes * nodes; + return current; +} + +/* + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +static int get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +} + +/* + * This function adds PCIe bridge device entry in DMAR table. If it is called + * in the context of ATSR subtable, it adds ATSR subtable when it is first called. + */ +static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, + int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + bool is_atsr, bool *first) +{ + + if (get_stack_for_port(port) != stack) + return 0; + + const uint32_t bus = iio_resource.StackRes[stack].BusBase; + const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + + const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + return 0; + + unsigned long atsr_size = 0; + unsigned long pci_br_size = 0; + if (is_atsr == true && first && *first == true) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", 0, pcie_seg); + atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); + *first = false; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); + + return (atsr_size + pci_br_size); +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, + int stack, const IIO_UDS *hob) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + /* Do not generate DRHD for non-PCIe stack */ + if (!reg_base) + return current; + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = PORT_0; p < MAX_PORTS; ++p) + current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, + iio_resource, pcie_seg, false, NULL); + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) +{ + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = PORT_0; p < MAX_PORTS; ++p) { + if (socket == 0 && p == PORT_0) + continue; + current += acpi_create_dmar_ds_pci_br_for_port(current, p, + stack, iio_resource, pcie_seg, true, &first); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack, hob); + current = acpi_create_drhd(current, socket, CSTACK, hob); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack, hob); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // Root Port ATS Capability + current = acpi_create_atsr(current, hob); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const config_t *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index fb78910a19..8debc6a236 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -29,12 +29,16 @@ const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; - const void *memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ assert(memmap_addr != NULL && hob_size != 0); - printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + /* assert the pointer to the hob is not NULL */ + assert(*memmap_addr != NULL); - return (const struct SystemMemoryMapHob *) memmap_addr; + return *memmap_addr; } void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, @@ -130,7 +134,6 @@ void xeonsp_init_cpu_config(void) } } - /* update apic_id, node_id in sorted order */ num_apics = 0; get_core_thread_bits(&core_bits, &thread_bits); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h similarity index 72% rename from src/soc/intel/xeon_sp/cpx/include/soc/acpi.h rename to src/soc/intel/xeon_sp/include/soc/acpi.h index 2f923d47a1..6a76ef222b 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -11,6 +11,12 @@ typedef struct { uint8_t buf[32]; } MEM_BLK; +/* P-state configuration */ +#define PSS_MAX_ENTRIES 16 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/xeon_sp/include/soc/acpi_asl.h b/src/soc/intel/xeon_sp/include/soc/acpi_asl.h new file mode 100644 index 0000000000..e08e02be35 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/acpi_asl.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_ACPI_ASL_H_ +#define _SOC_ACPI_ASL_H_ + +#define GEN_PCIE_LEGACY_IRQ() \ + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ + Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ + Package () { 0x0003FFFF, 0x03, LNKD, 0x00 } + +#define GEN_UNCORE_LEGACY_IRQ(dev) \ + Package () { ##dev, 0x00, LNKA, 0x00 }, \ + Package () { ##dev, 0x01, LNKB, 0x00 }, \ + Package () { ##dev, 0x02, LNKC, 0x00 }, \ + Package () { ##dev, 0x03, LNKD, 0x00 } + +#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \ + Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \ + Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \ + Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \ + Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 } + +#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ + Package () { ##dev, 0x00, 0x00, ##irq1 }, \ + Package () { ##dev, 0x01, 0x00, ##irq2 }, \ + Package () { ##dev, 0x02, 0x00, ##irq3 }, \ + Package () { ##dev, 0x03, 0x00, ##irq4 } + + +#define MAKE_LINK_DEV(id,uid) \ + Device (LNK##id) \ + { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, ##uid) \ + Method (_PRS, 0, NotSerialized) \ + { \ + Return (PRS##id) \ + } \ + Method (_CRS, 0, Serialized) \ + { \ + Name (RTLA, ResourceTemplate () \ + { \ + IRQ (Level, ActiveLow, Shared) {} \ + }) \ + CreateWordField (RTLA, 1, IRQ0) \ + Store (Zero, IRQ0) \ + \ + /* Set the bit from PIRQ Routing Register */ \ + ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ + Return (RTLA) \ + } \ + Method (_SRS, 1, Serialized) \ + { \ + CreateWordField (Arg0, 1, IRQ0) \ + FindSetRightBit (IRQ0, Local0) \ + Decrement (Local0) \ + Store (Local0, ^^PIR##id) \ + } \ + Method (_STA, 0, Serialized) \ + { \ + If (And (^^PIR##id, ^^IREN)) { \ + Return (0x9) \ + } Else { \ + Return (0xb) \ + } \ + } \ + Method (_DIS, 0, Serialized) \ + { \ + Or (^^PIR##id, ^^IREN, ^^PIR##id) \ + } \ + } + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/gpe.h b/src/soc/intel/xeon_sp/include/soc/gpe.h new file mode 100644 index 0000000000..c4acf1c1f3 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/gpe.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE_MAX GPE0_DW0_02 +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 68f6f558ae..f9c364454f 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #ifndef _SOC_IOMAP_H_ #define _SOC_IOMAP_H_ @@ -19,7 +18,9 @@ #define SPI_BASE_ADDRESS 0xfe010000 #define SPI_BASE_SIZE 0x1000 +#define TCO_BASE_ADDRESS 0x400 #define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_SIZE 0x100 /* Video RAM */ #define VGA_BASE_ADDRESS 0xa0000 @@ -28,6 +29,9 @@ /* High Performance Event Timer */ #define HPET_BASE_ADDRESS 0xfed00000 +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h similarity index 100% rename from src/soc/intel/xeon_sp/skx/include/soc/irq.h rename to src/soc/intel/xeon_sp/include/soc/irq.h diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h similarity index 100% rename from src/soc/intel/xeon_sp/skx/include/soc/msr.h rename to src/soc/intel/xeon_sp/include/soc/msr.h diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/include/soc/nvs.h rename to src/soc/intel/xeon_sp/include/soc/nvs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index c4c1a885bc..f5a45c6106 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -3,15 +3,103 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include +#include #include #include -#define PM1_CNT 0x04 -#define PM1_STS 0x00 -#define PM1_TMR 0x08 -#define PM2_CNT 0x50 +/* ACPI_BASE_ADDRESS / PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define PM1_EN 0x02 +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define ESPI_SMI_EN (1 << 28) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define PM1_STS_BIT 8 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x80 + (x * 4)) +#define GPE0_EN(x) (0x90 + (x * 4)) +#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define GPIO_T2_STS (1 << 15) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define GPE0_EN(x) (0x90 + (x * 4)) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) -#define GPE0_REG_MAX 4 -#define GPE0_STS(x) (0x80 + (x * 4)) +#define ENABLE_SMI_PARAMS \ + (APMC_EN | GBL_SMI_EN | EOS) + +/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ +#define ETR 0xac +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) + +#define PRSTS 0x10 + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + +uint16_t get_pmbase(void); #endif diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 49e58d366a..40b41c7d59 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -21,10 +21,22 @@ #define SCIS_IRQ23 7 #define PWRMBASE 0x48 #define GEN_PMCON_A 0xa0 +#define DISB (1 << 23) +#define GBL_RST_STS (1 << 16) #define SMI_LOCK (1 << 4) #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) #define RTC_BATTERY_DEAD (1 << 2) +#define SUS_PWR_FLR (1 << 14) +#define HOST_RST_STS (1 << 9) +#define PWR_FLR (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) +/* Memory mapped IO registers in PMC */ +#define GPIO_GPE_CFG 0x120 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4 * (x)) +#define GBLRST_CAUSE0 0x124 +#define GBLRST_CAUSE1 0x128 #endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 8bd5709fe0..90689afc7f 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ @@ -9,5 +8,5 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); - +void save_dimm_info(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c new file mode 100644 index 0000000000..a418ae5bab --- /dev/null +++ b/src/soc/intel/xeon_sp/pmc.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "chip.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); +} + +#if ENV_RAMSTAGE +/* Fill up PMC resource structure */ +int pmc_soc_get_resources(struct pmc_resource_config *cfg) +{ + cfg->pwrmbase_offset = PWRMBASE; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; + cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; + cfg->abase_offset = ABASE; + cfg->abase_addr = ACPI_BASE_ADDRESS; + cfg->abase_size = ACPI_BASE_SIZE; + + return 0; +} + +static const struct reg_script pch_pmc_misc_init_script[] = { + /* Enable SCI and clear SLP requests. */ + REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), + REG_SCRIPT_END +}; + +static const struct reg_script pmc_write1_to_clear_script[] = { + REG_PCI_OR32(GEN_PMCON_A, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_PCI_OR32(GEN_PMCON_B, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), + REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), + REG_SCRIPT_END +}; + +void pmc_soc_init(struct device *dev) +{ + pmc_set_power_failure_state(true); + pmc_gpe_init(); + + /* Note that certain bits may be cleared from running script as + * certain bit fields are write 1 to clear. */ + reg_script_run_on_dev(dev, pch_pmc_misc_init_script); + pmc_set_acpi_mode(); + + /* Clear registers that contain write-1-to-clear bits. */ + reg_script_run_on_dev(dev, pmc_write1_to_clear_script); +} +#endif + +/* + * GPE0 + */ + +const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) +{ + static const char *const gpe_sts_bits[] = { + }; + + *gpe_arr = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE); +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t) (pmc_mmio_regs()); +} + +uint32_t *soc_pmc_etr_addr(void) +{ + /* + * The pointer returned must not be cached, because the address depends on the + * MMCONF base address and the assigned PCI bus number, which both may change + * during the boot process! + */ + return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + /* No functionality for this yet */ +} + +int rtc_failure(void) +{ + u8 reg8; + int rtc_failed; + /* PMC Controller Device 0x1F, Func 02 */ + reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + } + + return !!rtc_failed; +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) +{ + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (!(ps->pm1_sts & WAK_STS) && + (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); + ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); + + pmc = pmc_mmio_regs(); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} + +const char *const *soc_smi_sts_array(size_t *smi_arr) +{ + static const char *const smi_sts_bits[] = { + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [7] = "BIOS_RLS", + [8] = "PM1", + [9] = "GPE0", + [10] = "GPI", + [11] = "MCSMI", + [12] = "DEVMON", + [13] = "TCO", + [14] = "PERIODIC", + [20] = "PCI_EXP_SMI", + [23] = "IE_SMI", + [25] = "SCC_SMI", + [26] = "SPI", + [27] = "GPIO_UNLOCK", + [28] = "ESPI_SMI", + [29] = "SERIAL_I/O", + [30] = "ME_SMI", + [31] = "XHCI", + }; + + *smi_arr = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index a4853c064e..f3e32fd9ca 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -41,7 +41,7 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - + save_dimm_info(); run_postcar_phase(&pcf); } @@ -54,3 +54,4 @@ __weak void mainboard_rtc_failed(void) { } +__weak void save_dimm_info(void) { } diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 0e3e699de6..2e0778ee12 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -15,6 +15,10 @@ config MAX_SOCKET int default 2 +config CPU_ADDR_BITS + int + default 46 + # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 773ced0fec..1a7e3dd564 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -19,7 +19,7 @@ romstage-y += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += soc_util.c +ramstage-y += soc_acpi.c ramstage-y += chip.c ramstage-y += soc_util.c ramstage-y += cpu.c diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f5e8..cbafbdb07b 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -14,8 +14,15 @@ #include #include #include + #include "chip.h" +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = 0; + return NULL; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -48,41 +55,7 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); - - /* Update the mem console pointer. */ - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); -} - -uint32_t soc_read_sci_irq_select(void) -{ - struct device *dev = PCH_DEV_PMC; - - if (!dev) - return 0; - - return pci_read_config32(dev, PMC_ACPI_CNT); -} - -acpi_cstate_t *soc_get_cstate_map(size_t *entries) -{ - *entries = 0; - return NULL; -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); - return current; -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); uint16_t flags = MP_IRQ_TRIGGER_LEVEL; @@ -101,25 +74,6 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -static unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) -{ - struct device *cpu; - int num_cpus = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - num_cpus, cpu->path.apic.apic_id); - } - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { size_t hob_size = 0; @@ -177,50 +131,6 @@ unsigned long acpi_fill_madt(unsigned long current) return acpi_madt_irq_overrides(current); } -void generate_t_state_entries(int core, int cores_per_package) -{ -} - -void generate_p_state_entries(int core, int cores_per_package) -{ -} - -void generate_cpu_entries(const struct device *device) -{ - int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; - int plen = 6; - int total_threads = dev_count_cpu(); - int threads_per_package = get_threads_per_package(); - int numcpus = total_threads / threads_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", - numcpus, threads_per_package, total_threads); - - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { - for (core_id = 0; core_id < threads_per_package; core_id++) { - if (core_id > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor((cpu_id) * threads_per_package + - core_id, pcontrol_blk, plen); - - /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - - /* TODO: Soc specific power states generation */ - acpigen_pop_len(); - } - } - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, threads_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(threads_per_package); -} - void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; @@ -307,31 +217,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.addrh = 0x00; } -static acpi_tstate_t xeon_sp_tss_table[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, -}; - -acpi_tstate_t *soc_get_tss_table(int *entries) -{ - *entries = ARRAY_SIZE(xeon_sp_tss_table); - return xeon_sp_tss_table; -} - -int soc_madt_sci_irq_polarity(int sci) -{ - if (sci >= 20) - return MP_IRQ_POLARITY_LOW; - else - return MP_IRQ_POLARITY_HIGH; -} - unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) @@ -342,485 +227,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return current; } -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - int nodes = get_cpu_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8+nodes*nodes; - return current; -} - -static int get_stack_for_port(int p) -{ - if (p == 0) - return CSTACK; - else if (p >= PORT_1A && p <= PORT_1D) - return PSTACK0; - else if (p >= PORT_2A && p <= PORT_2D) - return PSTACK1; - else if (p >= PORT_3A && p <= PORT_3D) - return PSTACK2; - else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK3; // MCP0 - else - return PSTACK4; // MCP1 -} - -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) -{ - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - - uint32_t enum_id; - unsigned long tmp = current; - - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - uint32_t reg_base = - hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); - - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - - // Add PCH IOAPIC - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - } - - // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); - - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } - - // Add PCIe Ports - if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, - bus, dev, func); - } - - // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } - } - - // Add HPET - if (socket == 0 && stack == CSTACK) { - uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count - printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", - __func__, hpet_capid, num_hpets); - //BIT 15 - if (num_hpets && (num_hpets != 0x1f) && - (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { - printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); - } - } - - acpi_dmar_drhd_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_atsr(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - unsigned long tmp = current; - bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " - "vtd_mmio_cap: 0x%llx\n", - __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); - - // ATSR is applicable only for platform supporting device IOTLBs - // through the VT-d extended capability register - assert(vtd_mmio_cap != 0xffffffffffffffff); - if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 - continue; - - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (socket == 0 && p == 0) - continue; - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - if (first) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", - 0, pcie_seg); - current += acpi_create_dmar_atsr(current, 0, pcie_seg); - first = 0; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); - } - } - if (tmp != current) - acpi_dmar_atsr_fixup(tmp, current); - } - - return current; -} - -static unsigned long acpi_create_rmrr(unsigned long current) -{ - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_rhsa(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " - "Proximity Domain: 0x%x\n", vtd_base, socket); - current += acpi_create_dmar_rhsa(current, vtd_base, socket); - } - } - - return current; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - // DRHD - for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { - int socket = iio; - if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry - socket = 0; - - if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); - } else { - for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - } - } - - // RMRR - current = acpi_create_rmrr(current); - - // ATSR - causes hang - current = acpi_create_atsr(current); - - // RHSA - current = acpi_create_rhsa(current); - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_dmar_t *dmar; - - const struct soc_intel_xeon_sp_skx_config *const config = config_of(device); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* DMAR */ - if (config->vtd_support) { - current = ALIGN(current, 8); - dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", - (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); - acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - } - - return current; -} - -void uncore_inject_dsdt(void) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - acpigen_write_scope("\\_SB"); - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - const STACK_RES *ri = &iio_resource.StackRes[stack]; - char rtname[16]; - snprintf(rtname, sizeof(rtname), "RT%02x", - (socket*MAX_IIO_STACK)+stack); - - acpigen_write_name(rtname); - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", - rtname, socket, stack); - - acpigen_write_resourcetemplate_header(); - - /* bus resource */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, - 0x0, (ri->BusLimit - ri->BusBase + 1)); - - // additional io resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, - 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, - 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, - 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, - 0, 0x0020); - } - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - // additional mem32 resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, - (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, - VGA_BASE_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, - ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - - acpigen_write_resourcetemplate_footer(); - } - } - acpigen_pop_len(); -} - void southbridge_inject_dsdt(const struct device *device) { struct global_nvs *gnvs; @@ -847,3 +253,62 @@ void southbridge_inject_dsdt(const struct device *device) // Add IIOStack ACPI Resource Templates uncore_inject_dsdt(); } + + + +static acpi_tstate_t xeon_sp_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = ARRAY_SIZE(xeon_sp_tss_table); + return xeon_sp_tss_table; +} + +void generate_t_state_entries(int core, int cores_per_package) +{ +} + +void generate_cpu_entries(const struct device *device) +{ + int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; + int plen = 6; + int total_threads = dev_count_cpu(); + int threads_per_package = get_threads_per_package(); + int numcpus = total_threads / threads_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", + numcpus, threads_per_package, total_threads); + + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { + for (core_id = 0; core_id < threads_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor((cpu_id) * threads_per_package + + core_id, pcontrol_blk, plen); + + /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ + + /* TODO: Soc specific power states generation */ + acpigen_pop_len(); + } + } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, threads_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(threads_per_package); +} diff --git a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl deleted file mode 100644 index 8e4456f29d..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 64, // 0x15 - PM1 wake status bit - GPEI, 64, // 0x1D - GPE wake status bit - U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap - U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap - - - /* Device Config */ - Offset (0x30), - S5U0, 8, // 0x30 - Enable USB0 in S5 - S5U1, 8, // 0x31 - Enable USB1 in S5 - S3U0, 8, // 0x32 - Enable USB0 in S3 - S3U1, 8, // 0x33 - Enable USB1 in S3 - TACT, 8, // 0x34 - Thermal Active trip point - TPSV, 8, // 0x35 - Thermal Passive trip point - TCRT, 8, // 0x36 - Thermal Critical trip point - DPTE, 8, // 0x37 - Enable DPTF - - /* Base addresses */ - Offset (0x50), - CMEM, 32, // 0x50 - CBMEM TOC - TOLM, 32, // 0x54 - Top of Low Memory - CBMC, 32, // 0x58 - coreboot mem console pointer - MMOB, 32, // 0x5C - MMIO Base Low Base - MMOL, 32, // 0x60 - MMIO Base Low Limit - MMHB, 64, // 0x64 - MMIO Base High Base - MMHL, 64, // 0x6C - MMIO Base High Limit - TSGB, 32, // 0x74 - TSEG Base - TSSZ, 32, // 0x78 - TSEG Size -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl deleted file mode 100644 index 964be3c785..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#define MAKE_IIO_DEV(id,rt) \ - Device (PC##id) \ - { \ - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ - Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ - Name (_UID, 0x##id) \ - Method (_PRT, 0, NotSerialized) \ - { \ - If (PICM) \ - { \ - Return (\_SB_.AR##rt) \ - } \ - Return (\_SB_.PR##rt) \ - } \ - External(\_SB.RT##id) \ - Method (_CRS, 0, NotSerialized) \ - { \ - Return (\_SB.RT##id) \ - } \ - Name (SUPP, 0x00) \ - Name (CTRL, 0x00) \ - Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ - Method (_OSC, 4, NotSerialized) \ - { \ - CreateDWordField (Arg3, 0x00, CDW1) \ - If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ - { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ - { \ - CreateDWordField (Arg3, 0x08, CDW3) \ - } \ - SUPP = CDW2 \ - CTRL = CDW3 \ - If ((AHPE || ((SUPP & 0x16) != 0x16))) \ - { \ - CTRL &= 0x1E \ - Sleep (0x03E8) \ - } \ - /* Never allow SHPC (no SHPC controller in system) */ \ - CTRL &= 0x1D \ - /* Disable Native PCIe AER handling from OS */ \ - CTRL &= 0x17 \ - If ((Arg1 != One)) /* unknown revision */ \ - { \ - CDW1 |= 0x08 \ - } \ - If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ - { \ - CDW1 |= 0x10 \ - } \ - CDW3 = CTRL \ - Return (Arg3) \ - } \ - Else \ - { \ - /* indicate unrecognized UUID */ \ - CDW1 |= 0x04 \ - IO80 = 0xEE \ - Return (Arg3) \ - } \ - } \ - } - -MAKE_IIO_DEV(00, 00) -MAKE_IIO_DEV(01, 10) -MAKE_IIO_DEV(02, 20) -MAKE_IIO_DEV(03, 28) - -#if MAX_SOCKET > 1 -MAKE_IIO_DEV(06, 40) -MAKE_IIO_DEV(07, 50) -MAKE_IIO_DEV(08, 60) -MAKE_IIO_DEV(09, 68) -#endif diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl deleted file mode 100644 index dcb6fe2af3..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 - * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 - * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 - * - * PIRQ routing control is in PCR ITSS region. - */ - -OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) -Field (ITSS, ByteAcc, NoLock, Preserve) -{ - PIRA, 8, /* PIRQA Routing Control */ - PIRB, 8, /* PIRQB Routing Control */ - PIRC, 8, /* PIRQC Routing Control */ - PIRD, 8, /* PIRQD Routing Control */ - PIRE, 8, /* PIRQE Routing Control */ - PIRF, 8, /* PIRQF Routing Control */ - PIRG, 8, /* PIRQG Routing Control */ - PIRH, 8, /* PIRQH Routing Control */ -} - -Name (IREN, 0x80) /* Interrupt Routing Enable */ -Name (IREM, 0x0f) /* Interrupt Routing Mask */ - -Name (PRSA, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} -}) -Alias (PRSA, PRSB) -Name (PRSC, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,10,11,12,14,15} -}) -Alias (PRSC, PRSD) -Alias (PRSA, PRSE) -Alias (PRSA, PRSF) -Alias (PRSA, PRSG) -Alias (PRSA, PRSH) - -#define MAKE_LINK_DEV(id,uid) \ - Device (LNK##id) \ - { \ - Name (_HID, EISAID ("PNP0C0F")) \ - Name (_UID, ##uid) \ - Method (_PRS, 0, NotSerialized) \ - { \ - Return (PRS##id) \ - } \ - Method (_CRS, 0, Serialized) \ - { \ - Name (RTLA, ResourceTemplate () \ - { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ - \ - /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ - Return (RTLA) \ - } \ - Method (_SRS, 1, Serialized) \ - { \ - CreateWordField (Arg0, 1, IRQ0) \ - FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ - } \ - Method (_STA, 0, Serialized) \ - { \ - If (And (^^PIR##id, ^^IREN)) { \ - Return (0x9) \ - } Else { \ - Return (0xb) \ - } \ - } \ - Method (_DIS, 0, Serialized) \ - { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ - } \ - } - -MAKE_LINK_DEV(A,1) -MAKE_LINK_DEV(B,2) -MAKE_LINK_DEV(C,3) -MAKE_LINK_DEV(D,4) -MAKE_LINK_DEV(E,5) -MAKE_LINK_DEV(F,6) -MAKE_LINK_DEV(G,7) -MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl deleted file mode 100644 index 498a997926..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#include -#include -#include -#include -#include - -Scope(\) -{ - // Private Chipset Register(PCR). Memory Mapped through ILB - OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) - Field(PCRR, DWordAcc, Lock, Preserve) - { - Offset (0xD03100), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - } -} - -Scope (_SB) -{ - #include "pci_irq.asl" - #include "uncore_irq.asl" - #include "iiostack.asl" -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl deleted file mode 100644 index 9926367536..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ /dev/null @@ -1,551 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Uncore devices PCI interrupt routing packages. - * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. - * The mapping fields ae Address, Pin, Source, Source Index. - */ - -#define GEN_PCIE_LEGACY_IRQ() \ - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0003FFFF, 0x00, LNKA, 0x00 } - -#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package () { ##dev, 0x00, LNKA, 0x00 }, \ - Package () { ##dev, 0x01, LNKB, 0x00 }, \ - Package () { ##dev, 0x02, LNKC, 0x00 }, \ - Package () { ##dev, 0x03, LNKD, 0x00 } - -#define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0003FFFF, 0x00, 0x00, ##irq } - -#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package () { ##dev, 0x00, 0x00, ##irq1 }, \ - Package () { ##dev, 0x01, 0x00, ##irq2 }, \ - Package () { ##dev, 0x02, 0x00, ##irq3 }, \ - Package () { ##dev, 0x03, 0x00, ##irq4 } - -// Socket 0, IIOStack 0 device legacy interrupt routing -Name (PR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - // [CB0A]: CBDMA - // [CB0E]: CBDMA - Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, - // [CB0B]: CBDMA - // [CB0F]: CBDMA - Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, - // [CB0C]: CBDMA - // [CB0G]: CBDMA - Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, - // [CB0D]: CBDMA - // [CB0H]: CBDMA - Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, - // Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - // // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, -}) - -// Socket 0, IIOStack 0 device IOAPIC interrupt routing -Name (AR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, - // [CB0A]: CB3DMA - // [CB0E]: CB3DMA - Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, - // [CB0B]: CB3DMA - // [CB0F]: CB3DMA - Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, - // [CB0C]: CB3DMA - // [CB0G]: CB3DMA - Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, - // [CB0D]: CB3DMA - // [CB0H]: CB3DMA - Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, - // [UBX0]: Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, - // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, -}) - -// Socket 0, IIOStack 1 device legacy interrupt routing -Name (PR10, Package (0x40) -{ - // PCI Express Port 1A-1D - GEN_PCIE_LEGACY_IRQ(), - - // Uncore CHAUTIL Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore CHASAD Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - - // Uncore CMSCHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - - // Uncore CHASADALL Device - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // Uncore PCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - - // Uncore VCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 0, IIOStack 1 device IOAPIC interrupt routing -Name (AR10, Package (0x40) -{ - // PCI Express Port 1A-1D - GEN_PCIE_IOAPIC_IRQ(0x27), - - // Uncore CHAUTIL Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASAD Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CMSCHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASADALL Device - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore PCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore VCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) -}) - -// Socket 0, IIOStack 2 device legacy interrupt routing -Name (PR20, Package (0x24) -{ - // PCI Express Port 2 on PC02 - GEN_PCIE_LEGACY_IRQ(), - - // Uncore M2MEM Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - - // Uncore MCDECS2 Device - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - - // Uncore MCDECS Device - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 2 device IOAPIC interrupt routing -Name (AR20, Package (0x24) -{ - // PCI Express Port 2 on PC02 - GEN_PCIE_IOAPIC_IRQ(0x2F), - - // Uncore M2MEM Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS2 Device - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS Device - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) -}) - -// Socket 0, IIOStack 3 device legacy interrupt routing -Name (PR28, Package (0x20) -{ - // PCI Express Port 3 on PC03 - GEN_PCIE_LEGACY_IRQ(), - - // KTI Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - - // M3K Device - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - - // M2U Device - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - - // M2D Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // M20 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 3 device IOAPIC interrupt routing -Name (AR28, Package (0x20) -{ - // PCI Express Port 3 on PC03 - GEN_PCIE_IOAPIC_IRQ(0x37), - - // KTI Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), - - // M3K Device - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2U Device - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2D Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), - - // M20 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) -}) - -// Socket 1, IIOStack 0 device legacy interrupt routing -Name (PR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - - // CBDMA - GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), - - // Ubox - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) -}) - -// Socket 1, IIOStack 0 device IOAPIC interrupt routing -Name (AR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, - - // CBDMA - GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), - - // Ubox - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), -}) - -// Socket 1, IIOStack 1 device legacy interrupt routing -Name (PR50, Package (0x40) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // CHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // PCU Devices - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 1, IIOStack 1 device IOAPIC interrupt routing -Name (AR50, Package (0x40) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x57), - - // CHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), - - // PCU Devices - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) -}) - -// Socket 1, IIOStack 2 device legacy interrupt routing -Name (PR60, Package (0x24) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Integrated Memory Controller - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 2 device IOAPIC interrupt routing -Name (AR60, Package (0x24) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x5F), - - // Integrated Memory Controller - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (PR68, Package (0x20) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (AR68, Package (0x20) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x67), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) -}) diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 440fb40f3d..adb70e58d0 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ @@ -37,6 +36,7 @@ struct soc_intel_xeon_sp_skx_config { * 6h = PIRQG# * 7h = PIRQH# */ + uint16_t ir00_routing; uint16_t ir01_routing; uint16_t ir02_routing; @@ -76,4 +76,8 @@ struct soc_intel_xeon_sp_skx_config { typedef struct soc_intel_xeon_sp_skx_config config_t; +/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ +void uncore_inject_dsdt(void); +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); + #endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index c59edab0bb..ea9f531886 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -221,7 +221,6 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; - void xeon_sp_init_cpus(struct device *dev) { FUNC_ENTER(); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h deleted file mode 100644 index 0e00c2b4b6..0000000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include -#include - -#define MEM_BLK_COUNT 0x140 -typedef struct { - uint8_t buf[32]; -} MEM_BLK; - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); -void uncore_inject_dsdt(void); - -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h deleted file mode 100644 index becdd76570..0000000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_NVS_H_ -#define _SOC_NVS_H_ - -#include - -/* TODO - this requires xeon sp, server board support */ -/* NOTE: We do not use intelblocks/nvs.h since it includes - mostly client specific attributes */ -struct __packed global_nvs { - uint8_t pcnt; /* 0x00 - Processor Count */ - uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t rsvd3[251]; -}; - -#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index bce7738460..ab8537881b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -31,30 +31,10 @@ #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 - -#define VTD_TOLM_CSR 0xd0 -#define VTD_TSEG_BASE_CSR 0xa8 -#define VTD_TSEG_LIMIT_CSR 0xac -#define VTD_EXT_CAP_LOW 0x10 -#define VTD_MMCFG_BASE_CSR 0x90 -#define VTD_MMCFG_LIMIT_CSR 0x98 -#define VTD_TOHM_CSR 0xd4 -#define VTD_MMIOL_CSR 0xdc -#define VTD_ME_BASE_CSR 0xf0 -#define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C -#define VTD_EXT_CAP_HIGH 0x14 - -#define SAD_ALL_DEV 29 -#define SAD_ALL_FUNC 0 -#define SAD_ALL_PAM0123_CSR 0x40 -#define SAD_ALL_PAM456_CSR 0x44 +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44 #define PCU_IIO_STACK 1 #define PCU_DEV 30 @@ -71,27 +51,48 @@ #define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ #define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK ((uint32_t)1 << 1) -#define RST_CPL2_MASK ((uint32_t)1 << 2) -#define RST_CPL3_MASK ((uint32_t)1 << 3) -#define RST_CPL4_MASK ((uint32_t)1 << 4) -#define PCODE_INIT_DONE1_MASK ((uint32_t)1 << 9) -#define PCODE_INIT_DONE2_MASK ((uint32_t)1 << 10) -#define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) -#define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) - #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) -#define BIOS_MB_CMD_MASK ((uint32_t)0xff) +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff #define BIOS_CMD_READ_PCU_MISC_CFG 0x5 #define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 #define BIOS_ERR_INVALID_CMD 0x01 +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12) + #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) + +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc + +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 #define PCU_CR1_C2C3TT_REG 0xdc #define PCU_CR1_PCIE_ILTR_OVRD 0xfc @@ -111,30 +112,49 @@ #define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 #define PROCHOT_RATIO 0xa /* bits 0:7 */ -#define UBOX_DECS_BUS 0 -#define UBOX_DECS_DEV 8 -#define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc - #define CHA_UTIL_ALL_DEV 29 #define CHA_UTIL_ALL_FUNC 1 #define CHA_UTIL_ALL_MMCFG_CSR 0xc0 -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function -#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB +/* PCH Device info */ -#define VMD_DEV_NUM 5 -#define VMD_FUNC_NUM 5 +#define XHCI_BUS_NUMBER 0x0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0x0 -#define APIC_DEV_NUM 5 -#define APIC_FUNC_NUM 0 +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 + +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) + +#define CBDMA_DEV_NUM 0x04 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function +#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB + +#define VMD_DEV_NUM 0x05 +#define VMD_FUNC_NUM 0x05 + +#define APIC_DEV_NUM 0x05 +#define APIC_FUNC_NUM 0x00 #define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00 -// ================================== IOAPIC Definitions for DMAR/ACPI ==================== +// ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 #define PC00_IOAPIC_ID 0x09 #define PC01_IOAPIC_ID 0x0A @@ -149,24 +169,4 @@ #define PC10_IOAPIC_ID 0x13 #define PC11_IOAPIC_ID 0x14 -/* PCH Device info */ - -#define XHCI_BUS_NUMBER 0x0 -#define PCH_DEV_SLOT_XHCI 0x14 -#define XHCI_FUNC_NUM 0x0 - -#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 - -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) - #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index b56f298325..c7f7383731 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -27,7 +27,6 @@ int get_threads_per_package(void); int get_platform_thread_count(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index c4c473b4e6..a1c370d070 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c new file mode 100644 index 0000000000..c986214b3c --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* TODO: Check if the common/acpi weak function can be used */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void acpi_init_gnvs(struct global_nvs *gnvs) +{ + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); + + /* Update the mem console pointer. */ + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); +} + +int soc_madt_sci_irq_polarity(int sci) +{ + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +uint32_t soc_read_sci_irq_select(void) +{ + struct device *dev = PCH_DEV_PMC; + + if (!dev) + return 0; + + return pci_read_config32(dev, PMC_ACPI_CNT); +} + +/* + * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() + * with a call from the common/function or find another way to call this at the correct place + */ +void uncore_inject_dsdt(void) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + acpigen_write_scope("\\_SB"); + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + const STACK_RES *ri = &iio_resource.StackRes[stack]; + char rtname[16]; + snprintf(rtname, sizeof(rtname), "RT%02x", + (socket*MAX_IIO_STACK)+stack); + + acpigen_write_name(rtname); + printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", + rtname, socket, stack); + + acpigen_write_resourcetemplate_header(); + + /* bus resource */ + acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, + 0x0, (ri->BusLimit - ri->BusBase + 1)); + + // additional io resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); + + /* IO decode CF8-CFF */ + acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, + 0, 0x03B0); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, + 0, 0x0918); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, + 0, 0x000C); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, + 0, 0x0020); + } + + /* IO resource */ + acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, + ri->PciResourceIoLimit, 0x0, + (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); + + // additional mem32 resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, + (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, + VGA_BASE_SIZE); + acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, + (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, + SPI_BASE_SIZE); + } + + /* Mem32 resource */ + acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, + ri->PciResourceMem32Limit, 0x0, + (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); + + /* Mem64 resource */ + acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, + ri->PciResourceMem64Limit, 0x0, + (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); + + acpigen_write_resourcetemplate_footer(); + } + } + acpigen_pop_len(); +} + +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) +{ + struct device *cpu; + int num_cpus = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, + num_cpus, cpu->path.apic.apic_id); + } + + return current; +} + +/* Northbridge SRAT,SLIT, etc. Make a common entry point and use. */ +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + unsigned int mmap_index; + + memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memory_map != NULL && hob_size != 0); + printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ + int nodes = get_cpu_count(); + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8+nodes*nodes; + return current; +} + + +static int get_stack_for_port(int p) +{ + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; + else if (p >= PORT_4A && p <= PORT_4D) + return PSTACK3; // MCP0 + else + return PSTACK4; // MCP1 +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, + bus, dev, func); + } + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (socket == 0 && p == 0) + continue; + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + if (first) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", + 0, pcie_seg); + current += acpi_create_dmar_atsr(current, 0, pcie_seg); + first = 0; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, CSTACK); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // ATSR - causes hang + current = acpi_create_atsr(current); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const config_t *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", + (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); + acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index f69f0b98d4..e21edbc8f7 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -415,7 +415,6 @@ void xeonsp_init_cpu_config(void) } } - /* update apic_id, node_id in sorted order */ num_apics = 0; get_core_thread_bits(&core_bits, &thread_bits); @@ -442,65 +441,4 @@ void xeonsp_init_cpu_config(void) } } -unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; - unsigned int mmap_index; - - memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memory_map != NULL && hob_size != 0); - printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - #endif diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index 3d03c3fc3f..84105dd6a4 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ - #include #include #include diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 17a28494f7..67e2fbf725 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -4,6 +4,7 @@ #include #include #include +#include #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h index e86675baa7..43893f7f88 100644 --- a/src/soc/mediatek/common/include/soc/ddp_common.h +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -6,7 +6,6 @@ #include #include - struct disp_ovl_regs { u32 sta; u32 inten; @@ -113,7 +112,6 @@ check_member(disp_color_regs, width, 0xC50); check_member(disp_color_regs, height, 0xC54); static struct disp_color_regs *const disp_color0 = (void *)DISP_COLOR0_BASE; - enum { COLOR_BYPASS_ALL = BIT(7), COLOR_SEQ_SEL = BIT(13), diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 5348e0575c..283cf94561 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -3,6 +3,7 @@ #ifndef SOC_MEDIATEK_COMMON_GPIO_H #define SOC_MEDIATEK_COMMON_GPIO_H +#include #include #include #include diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index 6477906138..d8cb9f5153 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -6,6 +6,7 @@ void mtcmos_audio_power_on(void); void mtcmos_display_power_on(void); +void mtcmos_protect_audio_bus(void); void mtcmos_protect_display_bus(void); #endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */ diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 681b97c5e3..d9ba2308e9 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -20,6 +20,8 @@ struct mux { void *reg; + void *set_reg; + void *clr_reg; void *upd_reg; u8 mux_shift; u8 mux_width; @@ -56,6 +58,12 @@ void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); -void mt_pll_raise_ca53_freq(u32 freq); +void mt_pll_raise_little_cpu_freq(u32 freq); + +enum fmeter_type { + FMETER_ABIST = 0, + FMETER_CKGEN, +}; +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id); #endif diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index cb86db3665..918f3d2717 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -5,6 +5,7 @@ #include #include +#include enum { SPI_CFG1_CS_IDLE_SHIFT = 0, diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 9550ba83fa..960d742d63 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -12,11 +12,11 @@ void mtk_mmu_init(void) mmu_init(); /* - * Set 0x0 to 4GB address as device memory. We want to config IO_PHYS + * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS * address to DEV_MEM, and map a proper range of dram for the memory * test during calibration. */ - mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 71deb71c77..cfd148c7fa 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include @@ -22,11 +21,6 @@ enum { PWR_RST_B = 1U << 0 }; -enum { - DISP_PWR_STA_MASK = 0x1 << 3, - AUDIO_PWR_STA_MASK = 0x1 << 24, -}; - static void mtcmos_power_on(const struct power_domain_data *pd) { write32(&mtk_spm->poweron_config_set, diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 35b03d845e..539d82cafe 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel) u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); + if (mux->set_reg && mux->clr_reg) { + write32(mux->clr_reg, mask << mux->mux_shift); + write32(mux->set_reg, sel << mux->mux_shift); + } else { + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + } + if (mux->upd_reg) write32(mux->upd_reg, 1 << mux->upd_shift); } diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 99cba13b24..ba3c71a8c6 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -139,22 +139,22 @@ static int mtk_uart_tst_byte(void) return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -void uart_init(int idx) +void uart_init(unsigned int idx) { mtk_uart_init(); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return mtk_uart_rx_byte(); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { mtk_uart_tx_byte(data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { mtk_uart_tx_flush(); } diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index 8c98b35f7f..e44a76f592 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -56,7 +56,6 @@ void da9212_probe(uint8_t i2c_num) unsigned char device_id = 0; unsigned char variant_id = 0; - /* select to page 4, clear REVERT at first time */ ret |= i2c_write_field(i2c_num, DA9212_SLAVE_ADDR, DA9212_REG_PAGE_CON, DA9212_REG_PAGE4, diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index f80fb97121..ff803c3d3b 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 6becfce6c6..6f9b301e73 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -4,6 +4,7 @@ #define _DSI_REG_H_ #include +#include /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 102 diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h index 0d8e0d381a..efc04d1ddc 100644 --- a/src/soc/mediatek/mt8173/include/soc/spm.h +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -11,8 +11,10 @@ enum { }; enum { + DISP_PWR_STA_MASK = 0x1 << 3, DISP_SRAM_PDN_MASK = 0xf << 8, DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 24, AUDIO_SRAM_PDN_MASK = 0xf << 8, AUDIO_SRAM_ACK_MASK = 0xf << 12, }; diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index e8fe6dc6d3..3e61f8c399 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -25,7 +25,6 @@ static void mt6311_hw_init(uint8_t i2c_num) int ret = 0; unsigned char var[3] = {0}; - /* * Phase Shedding Trim Software Setting * The phase 2 of MT6311 will enter PWM mode if the threshold is diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 8a86f0b3ae..7133fde400 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -373,7 +373,6 @@ void mt_pll_enable_ssusb_clk(void) setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } - /* after pmic_init */ void mt_pll_post_init(void) { @@ -418,7 +417,7 @@ void mt_pll_set_aud_div(u32 rate) } } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index ef57fa6204..d08de45325 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -9,7 +9,6 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) - /* initialize rtc related gpio */ static int rtc_gpio_init(void) { diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 13918a07f4..eba3f5e348 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -4,6 +4,7 @@ #include #include #include +#include static void disp_config_main_path_connection(void) { diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 6f7ae37743..8a5d319b29 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -5,29 +5,25 @@ #include #include #include +#include #include #include #include #include -enum { - CKE_FIXOFF = 0, - CKE_FIXON, - CKE_DYNAMIC -}; - -static void cke_fix_onoff(int option, u8 chn) +void dramc_cke_fix_onoff(enum cke_type option, u8 chn) { u8 on = 0, off = 0; /* if CKE is dynamic, set both CKE fix On and Off as 0 */ if (option != CKE_DYNAMIC) { on = option; - off = (1 - option); + off = 1 - option; } - clrsetbits32(&ch[chn].ao.ckectrl, - (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXON, on, + CKECTRL_CKEFIXOFF, off); } static void dvfs_settings(u8 freq_group) @@ -56,9 +52,9 @@ static void dvfs_settings(u8 freq_group) for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle); - setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } @@ -295,8 +291,8 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); - cke_fix_onoff(CKE_DYNAMIC, CHANNEL_A); - cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B); + dramc_cke_fix_onoff(CKE_DYNAMIC, CHANNEL_A); + dramc_cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) { setbits32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); @@ -521,6 +517,19 @@ static void update_initial_settings(u8 freq_group) (0x1 << 31) | (0xa << 21) | (0xa << 26)); setbits32(&ch[0].ao.ckectrl, 0x1 << 23); clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); + + /* CA prebit shift and delay */ + SET32_BITFIELDS(&ch[0].ao.shu[0].selph_ca7, + SHU_SELPH_CA7_DLY_RA0, 0x0, + SHU_SELPH_CA7_DLY_RA1, 0x0, + SHU_SELPH_CA7_DLY_RA2, 0x0, + SHU_SELPH_CA7_DLY_RA3, 0x0, + SHU_SELPH_CA7_DLY_RA4, 0x0, + SHU_SELPH_CA7_DLY_RA5, 0x0); + SET32_BITFIELDS(&ch[0].phy.shu[0].rk[0].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 0x20); + SET32_BITFIELDS(&ch[0].phy.shu[0].rk[1].ca_cmd[9], + SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 0x20); } static void dramc_power_on_sequence(void) @@ -528,8 +537,8 @@ static void dramc_power_on_sequence(void) for (size_t chn = 0; chn < CHANNEL_MAX; chn++) clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); - dramc_cke_fix_onoff(CHANNEL_A, false, true); - dramc_cke_fix_onoff(CHANNEL_B, false, true); + dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); + dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_B); udelay(200); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) @@ -539,8 +548,8 @@ static void dramc_power_on_sequence(void) setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); udelay(2000); - dramc_cke_fix_onoff(CHANNEL_A, true, false); - dramc_cke_fix_onoff(CHANNEL_B, true, false); + dramc_cke_fix_onoff(CKE_FIXON, CHANNEL_A); + dramc_cke_fix_onoff(CKE_FIXON, CHANNEL_B); udelay(2); } @@ -697,7 +706,7 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) regs_bak[i].value = read32(regs_bak[i].addr); setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); - dramc_cke_fix_onoff(chn, true, false); + dramc_cke_fix_onoff(CKE_FIXON, chn); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); @@ -841,8 +850,8 @@ static void auto_refresh_cke_off(void) setbits32(&ch[chn].ao.refctrl0, 0x1 << 29); udelay(3); - cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); - cke_fix_onoff(CKE_FIXOFF, CHANNEL_B); + dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); + dramc_cke_fix_onoff(CKE_FIXOFF, CHANNEL_B); dramc_set_broadcast(broadcast_bak); } @@ -889,12 +898,12 @@ static void dramc_setting_DDR1600(void) clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), - (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -948,11 +957,12 @@ static void dramc_setting_DDR2400(void) clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { @@ -1056,7 +1066,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); - clrbits32(&ch[0].phy.pll3, 0x1 < 0); + clrbits32(&ch[0].phy.pll3, 0x1 << 0); setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3); @@ -1087,7 +1097,11 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, for (size_t b = 0; b < 2; b++) setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index aa156f74f6..4a884b1976 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -47,10 +47,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + } impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -91,7 +93,7 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -150,9 +152,6 @@ void dramc_sw_impedance_save_reg(u8 freq_group, sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -202,7 +201,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group, SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); } static void transfer_pll_to_spm_control(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index aac6d17ed6..17fa2306e3 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include #include enum { @@ -71,6 +73,11 @@ struct per_byte_dly { u16 final_dly; }; +static const u8 lp4_ca_mapping_pop[CHANNEL_MAX][CA_NUM_LP4] = { + [CHANNEL_A] = {1, 4, 3, 2, 0, 5}, + [CHANNEL_B] = {0, 3, 2, 4, 1, 5}, +}; + static void dramc_auto_refresh_switch(u8 chn, bool option) { SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1); @@ -85,13 +92,6 @@ static void dramc_auto_refresh_switch(u8 chn, bool option) } } -void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) -{ - SET32_BITFIELDS(&ch[chn].ao.ckectrl, - CKECTRL_CKEFIXON, cke_on, - CKECTRL_CKEFIXOFF, cke_off); -} - static u16 dramc_mode_reg_read(u8 chn, u8 mr_idx) { u16 value; @@ -115,7 +115,7 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) { u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); - dramc_cke_fix_onoff(chn, true, false); + dramc_cke_fix_onoff(CKE_FIXON, chn); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSOP, value); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 1); @@ -130,6 +130,19 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -241,33 +254,320 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, } } -static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, - const struct sdram_params *params, const bool fast_calib) +static void cbt_set_perbit_delay_cell(u8 chn, u8 rank) { - u32 final_vref, clk_dly, cmd_dly, cs_dly; + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0], + SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, 0, + SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, 0, + SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, 0, + SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, 0, + SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, 0, + SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, 0); +} - clk_dly = params->cbt_clk_dly[chn][rank]; - cmd_dly = params->cbt_cmd_dly[chn][rank]; - cs_dly = params->cbt_cs_dly[chn][rank]; - final_vref = params->cbt_final_vref[chn][rank]; +static void set_dram_mr_cbt_on_off(u8 chn, u8 rank, u8 fsp, + u8 cbt_on, struct mr_value *mr) +{ + u8 MR13Value = mr->MR13Value; - if (fast_calib) { + if (cbt_on) { + MR13Value |= 0x1; + if (fsp == FSP_1) + MR13Value &= 0x7f; + else + MR13Value |= 0x80; + } else { + MR13Value &= 0xfe; + if (fsp == FSP_1) + MR13Value |= 0x80; + else + MR13Value &= 0x7f; + } + + dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value); + mr->MR13Value = MR13Value; +} + +static void cbt_set_fsp(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) +{ + u8 MR13Value = mr->MR13Value; + + if (fsp == FSP_0) { + MR13Value &= ~(BIT(6)); + MR13Value &= 0x7f; + } else { + MR13Value |= BIT(6); + MR13Value |= 0x80; + } + + dramc_mode_reg_write_by_rank(chn, rank, 13, MR13Value); + mr->MR13Value = MR13Value; +} + +static void o1_path_on_off(u8 cbt_on) +{ + u8 fix_dqien = (cbt_on == 1) ? 3 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.padctrl, PADCTRL_FIXDQIEN, fix_dqien); + SET32_BITFIELDS(&ch[chn].phy.b[0].dq[5], + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, cbt_on); + SET32_BITFIELDS(&ch[chn].phy.b[1].dq[5], + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, cbt_on); + SET32_BITFIELDS(&ch[chn].phy.b[0].dq[3], + B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, cbt_on); + SET32_BITFIELDS(&ch[chn].phy.b[1].dq[3], + B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, cbt_on); + } + udelay(1); +} + +static void cbt_entry(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) +{ + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0, + DRAMC_PD_CTRL_DCMEN, 0); + SET32_BITFIELDS(&ch[chn].ao.stbcal, STBCAL_DQSIENCG_NORMAL_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_MIOCKCTRLOFF, 1); + + dramc_cke_fix_onoff(CKE_FIXON, chn); + set_dram_mr_cbt_on_off(chn, rank, fsp, 1, mr); + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_WRITE_LEVEL_EN, 1); + + udelay(1); + dramc_cke_fix_onoff(CKE_FIXOFF, chn); + o1_path_on_off(1); +} + +static void cbt_exit(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) +{ + dramc_cke_fix_onoff(CKE_FIXON, chn); + + udelay(1); + set_dram_mr_cbt_on_off(chn, rank, fsp, 0, mr); + o1_path_on_off(0); +} + +static void cbt_set_vref(u8 chn, u8 rank, u8 vref, bool is_final) +{ + if (!is_final) { + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DMVREFCA, vref); + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQS_SEL, 1); + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQSBX_G, 0xa); + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQS_WLEV, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQS_WLEV, 0); + } else { + vref |= BIT(6); + dramc_dbg("final_vref: %#x\n", vref); + + /* CBT set vref */ + dramc_mode_reg_write_by_rank(chn, rank, 12, vref); + } +} + +static void cbt_set_ca_clk_result(u8 chn, u8 rank, + const struct sdram_params *params) +{ + const u8 *perbit_dly; + u8 clk_dly = params->cbt_clk_dly[chn][rank]; + u8 cmd_dly = params->cbt_cmd_dly[chn][rank]; + const u8 *ca_mapping = lp4_ca_mapping_pop[chn]; + + for (u8 rk = 0; rk < rank + 1; rk++) { /* Set CLK and CA delay */ - SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].ca_cmd[9], SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, cmd_dly, SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, clk_dly); udelay(1); + + perbit_dly = params->cbt_ca_perbit_delay[chn][rk]; + + /* Set CA perbit delay line calibration results */ + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].ca_cmd[0], + SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, perbit_dly[ca_mapping[0]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, perbit_dly[ca_mapping[1]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, perbit_dly[ca_mapping[2]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, perbit_dly[ca_mapping[3]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, perbit_dly[ca_mapping[4]], + SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, perbit_dly[ca_mapping[5]]); + } +} + +static u8 get_cbt_vref_pinmux_value(u8 chn, u8 vref_level) +{ + u8 vref_bit, vref_new, vref_org; + + vref_new = 0; + vref_org = BIT(6) | (vref_level & 0x3f); + for (vref_bit = 0; vref_bit < 8; vref_bit++) { + if (vref_org & (1 << vref_bit)) + vref_new |= (1 << phy_mapping[chn][vref_bit]); } - /* Set CLK and CS delay */ - SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly); + dramc_dbg("vref_new: %#x --> %#x\n", vref_org, vref_new); - final_vref |= (1 << 6); + return vref_new; +} - /* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); - dramc_dbg("final_vref: %#x\n", final_vref); +static void cbt_dramc_dfs_direct_jump(u8 shu_level) +{ + u8 shu_ack = 0; + static bool phy_pll_en = true; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + shu_ack |= (0x1 << chn); + + if (phy_pll_en) { + dramc_dbg("Disable CLRPLL\n"); + SET32_BITFIELDS(&ch[0].phy.pll2, PLL2_RG_RCLRPLL_EN, 0); + dramc_dbg("DFS jump to CLRPLL, shu lev=%d, ACK=%x\n", + shu_level, shu_ack); + } else { + dramc_dbg("Disable PHYPLL\n"); + SET32_BITFIELDS(&ch[0].phy.pll1, PLL1_RG_RPHYPLL_EN, 0); + dramc_dbg("DFS jump to PHYPLL, shu lev=%d, ACK=%x\n", + shu_level, shu_ack); + } + + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 0); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 0); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL_PCM, 0); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL_PCM, shu_level); + + if (phy_pll_en) { + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy.pll2, PLL2_RG_RCLRPLL_EN, 1); + dramc_dbg("Enable CLRPLL\n"); + } else { + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy.pll1, PLL1_RG_RPHYPLL_EN, 1); + dramc_dbg("Enable PHYPLL\n"); + } + + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 3); + + udelay(20); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 1); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 0); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 1); + + while ((READ32_BITFIELD(&mtk_spm->dramc_dpy_clk_sw_con, + DRAMC_DPY_CLK_SW_CON_SC_DMDRAMCSHU_ACK) & shu_ack) + != shu_ack) { + dramc_dbg("wait shu_en ack.\n"); + } + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 0); + + if (shu_level == 0) + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 3); + + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 0); + SET32_BITFIELDS(&mtk_spm->spm_power_on_val0, + SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 0); + + if (phy_pll_en) + SET32_BITFIELDS(&ch[0].phy.pll1, PLL1_RG_RPHYPLL_EN, 0); + else + SET32_BITFIELDS(&ch[0].phy.pll2, PLL2_RG_RCLRPLL_EN, 0); + dramc_dbg("Shuffle flow complete\n"); + + phy_pll_en = !phy_pll_en; +} + +static void cbt_switch_freq(cbt_freq freq) +{ + if (freq == CBT_LOW_FREQ) + cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_MAX - 1); + else + cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_1); +} + +static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, + const struct sdram_params *params, const bool fast_calib, + struct mr_value *mr) +{ + u8 final_vref, cs_dly; + u8 fsp = get_freq_fsq(freq_group); + + cs_dly = params->cbt_cs_dly[chn][rank]; + final_vref = params->cbt_final_vref[chn][rank]; + + struct reg_value regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.stbcal}, + {&ch[chn].ao.ckectrl}, + {&ch[chn].ao.write_lev}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].ao.spcmdctrl}, + }; + + for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + dramc_auto_refresh_switch(chn, false); + if (rank == RANK_1) { + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_TXRANK, rank); + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_TXRANKFIX, 1); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 0); + } + + cbt_set_perbit_delay_cell(chn, rank); + + if (fsp == FSP_1) + cbt_switch_freq(CBT_LOW_FREQ); + cbt_entry(chn, rank, fsp, mr); + if (fsp == FSP_1) + cbt_switch_freq(CBT_HIGH_FREQ); + + u8 new_vref = get_cbt_vref_pinmux_value(chn, final_vref); + cbt_set_vref(chn, rank, new_vref, 0); + + cbt_set_ca_clk_result(chn, rank, params); + + for (u8 rk = 0; rk < rank + 1; rk++) { + /* Set CLK and CS delay */ + SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].ca_cmd[9], + SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly); + } + + if (fsp == FSP_1) + cbt_switch_freq(CBT_LOW_FREQ); + cbt_exit(chn, rank, fsp, mr); + + cbt_set_fsp(chn, rank, fsp, mr); + cbt_set_vref(chn, rank, final_vref, 1); + + if (fsp == FSP_1) + cbt_switch_freq(CBT_HIGH_FREQ); + + /* restore MRR pinmux */ + set_mrr_pinmux_mapping(); + if (rank == RANK_1) { + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, 0); + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_TXRANK, 0); + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_TXRANKFIX, 0); + SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 0x1); + } + + for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); } static void dramc_read_dbi_onoff(size_t chn, bool on) @@ -365,12 +665,30 @@ void dramc_hw_gating_onoff(u8 chn, bool on) clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); } -static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) { + u8 dvs_delay; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0]; - clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + switch (freq_group) { + case LP4X_DDR1600: + dvs_delay = 5; + break; + case LP4X_DDR2400: + dvs_delay = 4; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + dvs_delay = 3; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20); clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } @@ -408,7 +726,13 @@ void dramc_apply_config_before_calibration(u8 freq_group) dramc_hw_gating_onoff(chn, false); clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30); + } + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits32(&ch[chn].ao.mrs, 0x3 << 24); setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -416,21 +740,14 @@ void dramc_apply_config_before_calibration(u8 freq_group) clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); - dramc_rx_input_delay_tracking_init_by_freq(chn); + dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group); setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); else - setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - } - - for (size_t r = 0; r < 2; r++) { - for (size_t b = 0; b < 2; b++) - clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], - (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); } } @@ -474,7 +791,7 @@ void dramc_apply_config_after_calibration(const struct mr_value *mr) clrbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); clrbits32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7)); - dramc_cke_fix_onoff(chn, false, false); + dramc_cke_fix_onoff(CKE_DYNAMIC, chn); clrbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); clrbits32(&ch[chn].ao.eyescan, 0x7 << 8); @@ -2158,7 +2475,7 @@ static void dqsosc_auto(u8 chn, u8 rank, u8 freq_group, SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_MIOCKCTRLOFF, 1); - dramc_cke_fix_onoff(chn, true, false); + dramc_cke_fix_onoff(CKE_FIXON, chn); start_dqsosc(chn); udelay(1); @@ -2677,8 +2994,57 @@ void dramc_dqs_precalculation_preset(void) } } -int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, - const struct mr_value *mr) +void get_dram_info_after_cal(u8 *density_result) +{ + u8 vendor_id, density, max_density = 0; + u32 ddr_size, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5); + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8); + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + ddr_size = 4; + break; + case 0x1: + ddr_size = 6; + break; + case 0x2: + ddr_size = 8; + break; + case 0x3: + ddr_size = 12; + break; + case 0x4: + ddr_size = 16; + break; + case 0x5: + ddr_size = 24; + break; + case 0x6: + ddr_size = 32; + break; + default: + ddr_size = 0; + break; + } + if (ddr_size > max_size) { + max_size = ddr_size; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, ddr_size, max_density); + } + + *density_result = max_density; +} + +int dramc_calibrate_all_channels(const struct sdram_params *pams, + u8 freq_group, struct mr_value *mr) { bool fast_calib; switch (pams->source) { @@ -2702,7 +3068,7 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams, - fast_calib); + fast_calib, mr); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 9f54f498e1..fa73ddb4e6 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -5,6 +5,7 @@ #include #include #include +#include void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index fd09ef1b77..8afbef00d8 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -49,10 +49,10 @@ const u8 phy_mapping[CHANNEL_MAX][16] = { }; struct optimize_ac_time { - u8 rfc; - u8 rfc_05t; - u8 rfc_pb; - u8 rfrc_pb05t; + u8 trfc; + u8 trfrc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; u16 tx_ref_cnt; }; @@ -157,7 +157,7 @@ static void set_rank_info_to_conf(const struct sdram_params *params) (is_dual_rank ? 0 : 1) << 12); } -static void set_MRR_pinmux_mapping(void) +void set_mrr_pinmux_mapping(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { const u8 *map = phy_mapping[chn]; @@ -182,7 +182,7 @@ static void set_MRR_pinmux_mapping(void) static void global_option_init(const struct sdram_params *params) { set_rank_info_to_conf(params); - set_MRR_pinmux_mapping(); + set_mrr_pinmux_mapping(); } static void set_vcore_voltage(u8 freq_group) @@ -319,30 +319,102 @@ static void dramc_init_pre_settings(void) setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(u8 freq_group) +static void dramc_ac_timing_optimize(u8 freq_group, u8 density) { - struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, - .rfrc_pb05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, - .rfrc_pb05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, - .rfrc_pb05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, - .rfrc_pb05t = 1, .tx_ref_cnt = 138}, + u8 rfcab_grp = 0; + u8 trfc, trfrc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + enum tRFCAB { + tRFCAB_130 = 0, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM }; + const struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = { + [LP4X_DDR1600] = { + [tRFCAB_130] = {.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 32}, + [tRFCAB_180] = {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 42}, + [tRFCAB_280] = {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 62}, + [tRFCAB_380] = {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 82} + }, + [LP4X_DDR2400] = { + [tRFCAB_130] = {.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 46}, + [tRFCAB_180] = {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15, + .trfrc_pb05t = 0, .tx_ref_cnt = 61}, + [tRFCAB_280] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 91}, + [tRFCAB_380] = {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45, + .trfrc_pb05t = 0, .tx_ref_cnt = 121} + }, + [LP4X_DDR3200] = { + [tRFCAB_130] = {.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12, + .trfrc_pb05t = 0, .tx_ref_cnt = 59}, + [tRFCAB_180] = {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24, + .trfrc_pb05t = 0, .tx_ref_cnt = 79}, + [tRFCAB_280] = {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44, + .trfrc_pb05t = 0, .tx_ref_cnt = 119}, + [tRFCAB_380] = {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64, + .trfrc_pb05t = 0, .tx_ref_cnt = 159} + }, + [LP4X_DDR3600] = { + [tRFCAB_130] = {.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + [tRFCAB_180] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 92}, + [tRFCAB_280] = {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53, + .trfrc_pb05t = 1, .tx_ref_cnt = 138}, + [tRFCAB_380] = {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76, + .trfrc_pb05t = 1, .tx_ref_cnt = 185} + }, + }; + + switch (density) { + case 0x0: + rfcab_grp = tRFCAB_130; + break; + case 0x1: + case 0x2: + rfcab_grp = tRFCAB_180; + break; + case 0x3: + case 0x4: + rfcab_grp = tRFCAB_280; + break; + case 0x5: + case 0x6: + rfcab_grp = tRFCAB_380; + break; + default: + dramc_err("density err!\n"); + break; + } + + const struct optimize_ac_time *ac_tim = &rf_cab_opt[freq_group][rfcab_grp]; + trfc = ac_tim->trfc; + trfrc_05t = ac_tim->trfrc_05t; + trfc_pb = ac_tim->trfc_pb; + trfrc_pb05t = ac_tim->trfrc_pb05t; + tx_ref_cnt = ac_tim->tx_ref_cnt; + dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb05t %d\n", + density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + 0xff << 16, trfc << 16); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + 0x1 << 2, trfrc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + 0x3ff << 0, tx_ref_cnt << 0); clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + 0xff << 0, trfc_pb << 0); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); + 0x1 << 1, trfrc_pb05t << 1); } } @@ -494,6 +566,7 @@ static int run_calib(const struct dramc_param *dparam, struct dram_shared_data *shared, const int shuffle, bool *first_run) { + u8 density; const u8 *freq_tbl; if (CONFIG(MT8183_DRAM_EMCP)) @@ -518,7 +591,8 @@ static int run_calib(const struct dramc_param *dparam, dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; - dramc_ac_timing_optimize(freq_group); + get_dram_info_after_cal(&density); + dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 6565ec5bd8..0c0b54d73a 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -10,7 +10,7 @@ enum { SEL_OFFSET = 0x80, EH_RSEL_OFFSET = 0xF0, GPIO_DRV0_OFFSET = 0xA0, - GPIO_DRV1_OFFSET = 0XB0, + GPIO_DRV1_OFFSET = 0xB0, }; static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h index bc4e6ab501..a059abf566 100644 --- a/src/soc/mediatek/mt8183/include/soc/ddp.h +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -42,7 +42,6 @@ check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; - /* DISP_REG_CONFIG_MMSYS_CG_CON0 Configures free-run clock gating 0 0: Enable clock diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index b5ae253cdf..c630b5aa90 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -29,6 +29,7 @@ enum dram_odt_type { }; enum { + CA_NUM_LP4 = 6, DQ_DATA_WIDTH = 16, DQS_BIT_NUMBER = 8, DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index a883fe7dce..f925162e4a 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -3,14 +3,14 @@ #ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H #define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H +#include +#include #include #include -#include "emi.h" - enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 2, + DRAMC_PARAM_HEADER_VERSION = 4, }; enum DRAMC_PARAM_STATUS_CODES { @@ -37,10 +37,16 @@ enum DRAMC_PARAM_FLAGS { DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, }; +enum DRAMC_PARAM_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + struct dramc_param_header { u32 status; /* DRAMC_PARAM_STATUS_CODES */ u32 magic; - u32 version; + u32 version; /* DRAMC_PARAM_HEADER_VERSION */ u32 size; /* size of whole dramc_param */ u16 config; /* DRAMC_PARAM_CONFIG */ u16 flags; /* DRAMC_PARAM_FLAGS */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 66433602c5..a0937d01c6 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -27,6 +27,7 @@ #define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 #define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a #define MR23_DEFAULT_VALUE 0x3f +#define CA_TRAINING_NUM 10 enum dram_te_op { TE_OP_WRITE_READ_CHECK = 0, @@ -42,6 +43,17 @@ enum { GATING_GOLDEND_DQSCNT = 0x4646 }; +enum cke_type { + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC +}; + +typedef enum { + CBT_LOW_FREQ = 0, + CBT_HIGH_FREQ, +} cbt_freq; + enum { IMPCAL_STAGE_DRVP = 0x1, IMPCAL_STAGE_DRVN, @@ -98,13 +110,15 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(const struct mr_value *mr); int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group, const struct mr_value *mr); + u8 freq_group, struct mr_value *mr); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); -void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); u32 get_shu_freq(u8 shu); void dramc_hw_dqsosc(u8 chn); void dramc_dqs_precalculation_preset(void); +void get_dram_info_after_cal(u8 *density); +void set_mrr_pinmux_mapping(void); +void dramc_cke_fix_onoff(enum cke_type option, u8 chn); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 1e1448b923..99005a19a6 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -623,8 +623,9 @@ DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) DEFINE_BIT(DDRCONF0_RDATRST, 0) DEFINE_BIT(PERFCTL0_RWOFOEN, 4) +DEFINE_BITFIELD(RKCFG_TXRANK, 1, 0) +DEFINE_BIT(RKCFG_TXRANKFIX, 3) DEFINE_BIT(RKCFG_DQSOSC2RK, 11) -DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26) DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) @@ -797,6 +798,7 @@ DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) +DEFINE_BITFIELD(SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD, 13, 8) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) /* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */ @@ -908,6 +910,90 @@ DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0) DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6) DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0) +/* DRAMC_REG_MRR_BIT_MUX1 */ +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0) + +/* DRAMC_REG_SHU_SELPH_CA7 */ +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0) + +/* DRAMC_REG_MRR_BIT_MUX2 */ +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0) + +/* DDRPHY_SHU1_R0_CA_CMD0 */ +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY, 23, 20) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY, 19, 16) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY, 15, 12) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY, 11, 8) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY, 7, 4) +DEFINE_BITFIELD(SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY, 3, 0) + +/* DDRPHY_PLL2 */ +DEFINE_BIT(PLL2_RG_RCLRPLL_EN, 31) + +/* DDRPHY_PLL1 */ +DEFINE_BIT(PLL1_RG_RPHYPLL_EN, 31) + +/* DRAMC_REG_PADCTRL */ +DEFINE_BITFIELD(PADCTRL_FIXDQIEN, 19, 16) + +/* SPM_POWER_ON_VAL0 */ +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DR_SHU_EN_PCM, 22) +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DPHY_RXDLY_TRACK_EN, 25) +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_DDRPHY_FB_CK_EN_PCM, 16) +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_TX_TRACKING_DIS, 11) +DEFINE_BITFIELD(SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL_PCM, 31, 30) +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL2_SHU_EN_PCM, 27) +DEFINE_BIT(SPM_POWER_ON_VAL0_SC_PHYPLL1_SHU_EN_PCM, 26) + +/* SPM_POWER_ON_VAL1 */ +DEFINE_BIT(SPM_POWER_ON_VAL1_SC_DR_SHORT_QUEUE_PCM, 31) + +/* SPM_DRAMC_DPY_CLK_SW_CON */ +DEFINE_BITFIELD(DRAMC_DPY_CLK_SW_CON_SC_DMDRAMCSHU_ACK, 25, 24) + +/* DRAMC_REG_DRAMC_PD_CTRL */ +DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0) +DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30) +DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26) + +/* DRAMC_REG_WRITE_LEV */ +DEFINE_BIT(WRITE_LEV_DQS_WLEV, 7) +DEFINE_BITFIELD(WRITE_LEV_DQSBX_G, 11, 8) +DEFINE_BITFIELD(WRITE_LEV_DQS_SEL, 19, 16) +DEFINE_BITFIELD(WRITE_LEV_DMVREFCA, 27, 20) +DEFINE_BIT(WRITE_LEV_WRITE_LEVEL_EN, 0) +DEFINE_BIT(WRITE_LEV_BYTEMODECBTEN, 3) + +/* DRAMC_REG_STBCAL */ +DEFINE_BIT(STBCAL_DQSIENCG_NORMAL_EN, 29) + +/* DDRPHY_B0_DQ5 */ +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17) + +/* DDRPHY_B1_DQ5 */ +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17) + +/* DDRPHY_B0_DQ3 */ +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1) + +/* DDRPHY_B1_DQ3 */ +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1) + +/* DDRPHY_CA_CMD5 */ +DEFINE_BIT(CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN, 17) + +/* DDRPHY_CA_CMD3 */ +DEFINE_BIT(CA_CMD3_RG_RX_ARCMD_SMT_EN, 1) + struct dramc_channel_regs { union { struct dramc_ddrphy_ao_regs phy; diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 4535d905cf..9da79e648c 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_DSI_H #include +#include /* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index b2d78b965f..6931d5bb81 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -13,8 +13,9 @@ enum DRAMC_PARAM_SOURCE { }; struct sdram_params { - u16 source; /* DRAMC_PARAM_SOURCE */ + u16 source; /* DRAMC_PARAM_SOURCE */ u16 frequency; + u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; /* DUTY */ @@ -26,6 +27,7 @@ struct sdram_params { u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; /* Gating */ u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h index 2c1fa9b948..8cfe8b0aa3 100644 --- a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -351,22 +351,22 @@ enum { }; enum { - STA_PD_98_5_US = 0X5, + STA_PD_98_5_US = 0x5, }; enum { - WATCHDOG_TIMER_7_5_MS = 0XF, + WATCHDOG_TIMER_7_5_MS = 0xF, }; enum { - WDT_MONITOR_ALL = 0XFFFF, + WDT_MONITOR_ALL = 0xFFFF, }; enum { MONITOR_LATCH_MATCHED_TRANS = 0x1 << 28, STARV_15 = 0x1 << 24, DCXO = 0x1 << 19, - MONITOR_ALL_INT = 0XFFFFFFFF, + MONITOR_ALL_INT = 0xFFFFFFFF, INT0_MONITOR = MONITOR_ALL_INT, INT1_MONITOR = MONITOR_ALL_INT & ~MONITOR_LATCH_MATCHED_TRANS & ~STARV_15 & ~DCXO, @@ -396,6 +396,6 @@ enum { }; enum { - DUMMY_READ_CYCLES = 0X8, + DUMMY_READ_CYCLES = 0x8, }; #endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index fa6d6d00ce..327355ae05 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -117,8 +117,10 @@ #define PCM_SW_INT_ALL (0x3FF) enum { + DISP_PWR_STA_MASK = 0x1 << 3, DISP_SRAM_PDN_MASK = 0x1 << 8, DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 24, AUDIO_SRAM_PDN_MASK = 0xf << 8, AUDIO_SRAM_ACK_MASK = 0xf << 12, }; diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index ff30f67538..6b80a43a8c 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -97,7 +97,8 @@ static int dram_run_fast_calibration(const struct dramc_param *dparam, return 0; } -static int dram_run_full_calibration(struct dramc_param *dparam, u16 config) +static int dram_run_full_calibration(struct dramc_param *dparam, + u32 ddr_geometry, u16 config) { initialize_dramc_param(dparam, config); @@ -111,6 +112,8 @@ static int dram_run_full_calibration(struct dramc_param *dparam, u16 config) return -2; dparam->do_putc = do_putchar; + dparam->freq_params[0].ddr_geometry = ddr_geometry; + printk(BIOS_INFO, "ddr_geometry: %d, config: %#x\n", ddr_geometry, config); prog_set_entry(&dram, prog_entry(&dram), dparam); prog_run(&dram); @@ -184,9 +187,11 @@ static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) "Failed to read calibration data from flash\n"); } + const struct sdram_params *sdram_cfg = get_sdram_config(); + /* Run full calibration */ printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); - int err = dram_run_full_calibration(dparam, config); + int err = dram_run_full_calibration(dparam, sdram_cfg->ddr_geometry, config); if (err == 0) { printk(BIOS_INFO, "Successfully loaded DRAM blobs and " "ran DRAM calibration\n"); @@ -211,7 +216,7 @@ static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) /* Init params from sdram configs and run partial calibration */ printk(BIOS_INFO, "DRAM-K: Partial Calibration\n"); - init_sdram_params(dparam->freq_params, get_sdram_config()); + init_sdram_params(dparam->freq_params, sdram_cfg); if (mt_set_emi(dparam) != 0) die("Set emi failed with params from sdram config\n"); if (mt_mem_test() != 0) diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7b4febc56d..6e6e43a6c4 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -831,7 +831,7 @@ void pmic_set_vsim2_cali(unsigned int vsim2_mv) break; default: - assert(0); + BUG(); return; }; diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 4570269421..0e96f4cc68 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -362,7 +362,7 @@ void mt_pll_init(void) setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -void mt_pll_raise_ca53_freq(u32 freq) +void mt_pll_raise_little_cpu_freq(u32 freq) { /* enable [4] intermediate clock armpll_divider_pll1_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c index bae3fce5bf..4d195b79f0 100644 --- a/src/soc/mediatek/mt8183/pmic_wrap.c +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -47,7 +47,6 @@ enum { COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), }; - static void pwrap_soft_reset(void) { write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1); diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 2aa10b4746..01c6a2fbfa 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig new file mode 100644 index 0000000000..24122048b6 --- /dev/null +++ b/src/soc/mediatek/mt8192/Kconfig @@ -0,0 +1,18 @@ +config SOC_MEDIATEK_MT8192 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select HAVE_UART_SPECIAL + +if SOC_MEDIATEK_MT8192 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc new file mode 100644 index 0000000000..533eae294d --- /dev/null +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -0,0 +1,43 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) + +bootblock-y += bootblock.c +bootblock-y += flash_controller.c +bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +bootblock-y += ../common/timer.c +bootblock-y += ../common/uart.c +bootblock-y += ../common/wdt.c + +verstage-y += flash_controller.c +verstage-y += ../common/gpio.c gpio.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +verstage-y += ../common/timer.c +verstage-y += ../common/uart.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c +romstage-y += flash_controller.c +romstage-y += ../common/gpio.c gpio.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/timer.c +romstage-y += ../common/uart.c + +ramstage-y += flash_controller.c +ramstage-y += ../common/gpio.c gpio.c +ramstage-y += emi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += soc.c +ramstage-y += ../common/timer.c +ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c new file mode 100644 index 0000000000..8dffe5671b --- /dev/null +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); + mtk_wdt_init(); + mt_pll_init(); +} diff --git a/src/soc/mediatek/mt8192/dramc_param.c b/src/soc/mediatek/mt8192/dramc_param.c new file mode 100644 index 0000000000..f8f6c7dd14 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_param.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define print(_x_...) printk(BIOS_INFO, _x_) + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +void dump_param_header(const void *blob) +{ + const struct dramc_param *dparam = blob; + const struct dramc_param_header *header = &dparam->header; + + print("header.status = %#x\n", header->status); + print("header.version = %#x (expected: %#x)\n", + header->version, DRAMC_PARAM_HEADER_VERSION); + print("header.size = %#x (expected: %#lx)\n", + header->size, sizeof(*dparam)); + print("header.flags = %#x\n", header->flags); + print("header.checksum = %#x\n", header->checksum); +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = ¶m->header; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = ¶m->header; + + memset(hdr, 0, sizeof(*hdr)); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->size = sizeof(*param); + return 0; +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c new file mode 100644 index 0000000000..7b1d3c2113 --- /dev/null +++ b/src/soc/mediatek/mt8192/emi.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +size_t sdram_size(void) +{ + size_t dram_size = 0x100000000; + + return dram_size; +} diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/mt8192/flash_controller.c new file mode 100644 index 0000000000..aa43af6e0d --- /dev/null +++ b/src/soc/mediatek/mt8192/flash_controller.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GET_NTH_BYTE(d, n) ((d >> (8 * n)) & 0xff) + +static int polling_cmd(u32 val) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while ((read32(&mt8192_nor->cmd) & val) != 0) { + if (stopwatch_expired(&sw)) + return -1; + } + + return 0; +} + +static int mt8192_nor_execute_cmd(u8 cmdval) +{ + u8 val = cmdval & ~SFLASH_AUTOINC; + + write8(&mt8192_nor->cmd, cmdval); + return polling_cmd(val); +} + +static int sflashhw_read_flash_status(u8 *value) +{ + if (mt8192_nor_execute_cmd(SFLASH_READSTATUS)) + return -1; + + *value = read8(&mt8192_nor->rdsr); + return 0; +} + +static int wait_for_write_done(void) +{ + struct stopwatch sw; + u8 reg; + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + + while (sflashhw_read_flash_status(®) == 0) { + if (!(reg & SFLASH_WRITE_IN_PROGRESS)) + return 0; + if (stopwatch_expired(&sw)) + return -1; + } + + return -1; +} + +/* set serial flash program address */ +static void set_sfpaddr(u32 addr) +{ + write8(&mt8192_nor->radr[2], GET_NTH_BYTE(addr, 2)); + write8(&mt8192_nor->radr[1], GET_NTH_BYTE(addr, 1)); + write8(&mt8192_nor->radr[0], GET_NTH_BYTE(addr, 0)); +} + +static int sector_erase(int offset) +{ + if (wait_for_write_done()) + return -1; + + write8(&mt8192_nor->prgdata[5], SFLASH_OP_WREN); + write8(&mt8192_nor->cnt, 8); + mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + + write8(&mt8192_nor->prgdata[5], SECTOR_ERASE_CMD); + write8(&mt8192_nor->prgdata[4], GET_NTH_BYTE(offset, 2)); + write8(&mt8192_nor->prgdata[3], GET_NTH_BYTE(offset, 1)); + write8(&mt8192_nor->prgdata[2], GET_NTH_BYTE(offset, 0)); + write8(&mt8192_nor->cnt, 32); + mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + + if (wait_for_write_done()) + return -1; + + return 0; +} + +static int dma_read(u32 addr, uintptr_t dma_buf, u32 len) +{ + struct stopwatch sw; + + assert(IS_ALIGNED((uintptr_t)addr, SFLASH_DMA_ALIGN) && + IS_ALIGNED(len, SFLASH_DMA_ALIGN)); + + /* do dma reset */ + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_SW_RESET); + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); + /* flash source address and dram dest address */ + write32(&mt8192_nor->fdma_fadr, addr); + write32(&mt8192_nor->fdma_dadr, dma_buf); + write32(&mt8192_nor->fdma_end_dadr, (dma_buf + len)); + /* start dma */ + write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); + + stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); + while ((read32(&mt8192_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "dma read timeout!\n"); + return -1; + } + } + + return 0; +} + +static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, + void *buf) +{ + uintptr_t dma_buf = (uintptr_t)_dma_coherent; + size_t dma_buf_len = REGION_SIZE(dma_coherent); + u32 start = ALIGN_DOWN(addr, SFLASH_DMA_ALIGN); + u32 skip = addr - start; + u32 total = ALIGN_UP(skip + len, SFLASH_DMA_ALIGN); + u32 drop = total - skip - len; + u32 done, read_len, copy_len; + uint8_t *dest = (uint8_t *)buf; + + setbits8(&mt8192_nor->read_dual, SFLASH_READ_DUAL_EN); + write8(&mt8192_nor->prgdata[3], SFLASH_1_1_2_READ); + + /* DMA: start [ skip | len | drop ] = total end */ + for (done = 0; done < total; dest += copy_len) { + read_len = MIN(dma_buf_len, total - done); + if (dma_read(start + done, dma_buf, read_len)) + return -1; + + done += read_len; + /* decide the range to copy into buffer */ + if (done == total) + read_len -= drop; /* Only drop in last iteration */ + + copy_len = read_len - skip; + memcpy(dest, (uint8_t *)dma_buf + skip, copy_len); + if (skip) + skip = 0; /* Only apply skip in first iteration. */ + } + return 0; +} + +static int nor_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) +{ + const u8 *buffer = (const u8 *)buf; + + set_sfpaddr(addr); + while (len) { + write8(&mt8192_nor->wdata, *buffer); + if (mt8192_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) + return -1; + + if (wait_for_write_done()) + return -1; + buffer++; + len--; + } + return 0; +} + +static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) +{ + int sector_start = offset; + int sector_num = (u32)len / flash->sector_size; + + while (sector_num) { + if (!sector_erase(sector_start)) { + sector_start += flash->sector_size; + sector_num--; + } else { + printk(BIOS_WARNING, "Erase failed at %#x!\n", + sector_start); + return -1; + } + } + return 0; +} + +const struct spi_flash_ops spi_flash_ops = { + .read = nor_read, + .write = nor_write, + .erase = nor_erase, +}; + +int mtk_spi_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash) +{ + write32(&mt8192_nor->wrprot, SFLASH_COMMAND_ENABLE); + memcpy(&flash->spi, spi, sizeof(*spi)); + + flash->sector_size = 0x1000; + flash->erase_cmd = SECTOR_ERASE_CMD; + flash->size = CONFIG_ROM_SIZE; + + flash->ops = &spi_flash_ops; + + return 0; +} diff --git a/src/soc/mediatek/mt8192/gpio.c b/src/soc/mediatek/mt8192/gpio.c new file mode 100644 index 0000000000..dcc133299c --- /dev/null +++ b/src/soc/mediatek/mt8192/gpio.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void *gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + switch (gpio.base & 0x0f) { + case 0: + reg_addr = (void *)IOCFG_RM_BASE; + break; + case 1: + reg_addr = (void *)IOCFG_BM_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_BL_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_BR_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_LB_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_RT_BASE; + break; + case 7: + reg_addr = (void *)IOCFG_LT_BASE; + break; + case 8: + reg_addr = (void *)IOCFG_TL_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, 1 << bit); + else + clrbits32(reg1, 1 << bit); + } + + if (enable == GPIO_PULL_ENABLE) + setbits32(reg2, 1 << bit); + else { + clrbits32(reg2, 1 << bit); + clrbits32(reg2 + 0x010, 1 << bit); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, 1 << bit); + setbits32(reg2, 1 << bit); + } else { + clrbits32(reg2, 1 << bit); + setbits32(reg1, 1 << bit); + } + } else { + clrbits32(reg1, 1 << bit); + clrbits32(reg2, 1 << bit); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h new file mode 100644 index 0000000000..e0cd5364a3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, + UART0_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01018000, + SPI5_BASE = IO_PHYS + 0x01019000, + SPI6_BASE = IO_PHYS + 0x0101D000, + SPI7_BASE = IO_PHYS + 0x0101E000, + SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, + SFLASH_REG_BASE = IO_PHYS + 0x01234000, + IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + IOCFG_BM_BASE = IO_PHYS + 0x01D10000, + IOCFG_BL_BASE = IO_PHYS + 0x01D30000, + IOCFG_BR_BASE = IO_PHYS + 0x01D40000, + IOCFG_LM_BASE = IO_PHYS + 0x01E20000, + SSUSB_SIF_BASE = IO_PHYS + 0x01E40300, + IOCFG_LB_BASE = IO_PHYS + 0x01E70000, + IOCFG_RT_BASE = IO_PHYS + 0x01EA0000, + IOCFG_LT_BASE = IO_PHYS + 0x01F20000, + IOCFG_TL_BASE = IO_PHYS + 0x01F30000, + MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + MSDC0_BASE = IO_PHYS + 0x01F60000, +}; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h b/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h new file mode 100644 index 0000000000..185ba8d6bd --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__ + +enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX +}; + +enum { + RANK_0 = 0, + RANK_1, + RANK_MAX +}; + +enum { + FSP_0 = 0, + FSP_1, + FSP_MAX, +}; + +typedef enum { + DRAM_DFS_SHU0 = 0, + DRAM_DFS_SHU1, + DRAM_DFS_SHU2, + DRAM_DFS_SHU3, + DRAM_DFS_SHU4, + DRAM_DFS_SHU5, + DRAM_DFS_SHU6, + DRAM_DFS_SHU_MAX +} dram_dfs_shu; + +typedef enum { + ODT_OFF = 0, + ODT_ON, + ODT_MAX +} dram_odt_state; + +typedef enum { + DBI_OFF = 0, + DBI_ON +} dbi_mode; + +enum { + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC +}; + +enum { + CA_NUM_LP4 = 6, + DQ_DATA_WIDTH = 16, + DQS_BIT_NUMBER = 8, + DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER), +}; +#define BYTE_NUM DQS_NUMBER +#define DQS_NUMBER_LP4 DQS_NUMBER +#define DQ_DATA_WIDTH_LP4 DQ_DATA_WIDTH + +typedef enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1 +} dram_cbt_mode; + +/* DONOT change the sequence of pinmux */ +typedef enum { + PINMUX_DSC = 0, + PINMUX_LPBK, + PINMUX_EMCP, + PINMUX_MAX +} dram_pinmux_type; + +enum { + CBT_R0_R1_NORMAL = 0, + CBT_R0_R1_BYTE, + CBT_R0_NORMAL_R1_BYTE, + CBT_R0_BYTE_R1_NORMAL +}; + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h new file mode 100644 index 0000000000..89ff628bde --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ + +#include +#include +#include + +enum { + DRAMC_PARAM_HEADER_VERSION = 2, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_FAST_CALIBRATION, +}; + +enum DRAMC_PARAM_DVFS_FLAG { + DRAMC_DISABLE_DVFS, + DRAMC_ENABLE_DVFS, +}; + +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +enum DRAMC_PARAM_DDR_TYPE { + DDR_TYPE_DISCRETE, + DDR_TYPE_EMCP, +}; + +enum DRAMC_PARAM_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4, + DDR_TYPE_2CH_1RK_4GB_4_0, + DDR_TYPE_2CH_2RK_6GB_2_4, +}; + +enum DRAM_PARAM_VOLTAGE_TYPE { + DRAM_VOLTAGE_NVCORE_NVDRAM, + DRAM_VOLTAGE_HVCORE_HVDRAM, + DRAM_VOLTAGE_LVCORE_LVDRAM, +}; + +struct dramc_param_header { + u32 checksum; /* checksum of dramc_datas, update in the coreboot */ + u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ + u16 size; /* size of whole dramc_param, update in the coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ + u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ +}; + +struct sdram_params { + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* Gating */ + u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* TX perbit */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* TX OE */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_base_info { + u16 config_dvfs; /* DRAMC_PARAM_DVFS_FLAG */ + u16 ddr_type; /* DRAMC_PARAM_DDR_TYPE */ + u16 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ + u16 voltage_type; /* DRAM_PARAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + dram_cbt_mode cbt_mode[RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +struct dramc_param_ops { + struct dramc_param *param; + bool (*read_from_flash)(struct dramc_param *dparam); + bool (*write_to_flash)(const struct dramc_param *dparam); +}; + +struct sdram_info { + u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ +}; + +const struct sdram_info *get_sdram_config(void); +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob); +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h new file mode 100644 index 0000000000..0348573bd0 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_EMI_H +#define SOC_MEDIATEK_MT8192_EMI_H + +#include + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/mt8192/include/soc/flash_controller.h new file mode 100644 index 0000000000..5373a87ef3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/flash_controller.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ +#define __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ + +#include +#include +#include + +enum { + SFLASH_POLLINGREG_US = 500000, + SFLASH_WRBUF_SIZE = 128, + SFLASHNAME_LENGTH = 16, + SFLASH_WRITE_IN_PROGRESS = 1, + SFLASH_COMMAND_ENABLE = 0x30, + SFLASH_DMA_ALIGN = 0x10, + + /* NOR flash controller commands */ + SFLASH_RD_TRIGGER = 1 << 0, + SFLASH_READSTATUS = 1 << 1, + SFLASH_PRG_CMD = 1 << 2, + SFLASH_WR_TRIGGER = 1 << 4, + SFLASH_WRITESTATUS = 1 << 5, + SFLASH_AUTOINC = 1 << 7, + /* NOR flash commands */ + SFLASH_OP_WREN = 0x6, + SECTOR_ERASE_CMD = 0x20, + SFLASH_UNPROTECTED = 0x0, + /* DMA commands */ + SFLASH_DMA_TRIGGER = 1 << 0, + SFLASH_DMA_SW_RESET = 1 << 1, + SFLASH_DMA_WDLE_EN = 1 << 2, + /* Dual mode */ + SFLASH_READ_DUAL_EN = 0x1, + SFLASH_1_1_2_READ = 0x3b +}; + +/* register Offset */ +struct mt8192_nor_regs { + u32 cmd; + u32 cnt; + u32 rdsr; + u32 rdata; + u32 radr[3]; + u32 wdata; + u32 prgdata[6]; + u32 shreg[10]; + u32 cfg[2]; + u32 shreg10; + u32 status[5]; + u32 timing; + u32 flash_cfg; + u32 reserved2[3]; + u32 sf_time; + u32 reserved3; + u32 diff_addr; + u32 del_sel[2]; + u32 intrstus; + u32 intren; + u32 pp_ctl; + u32 cfg3; + u32 chksum_ctl; + u32 chksum; + u32 aaicmd; + u32 wrprot; + u32 radr3; + u32 read_dual; + u32 delsel[3]; + u32 reserved[397]; + u32 cfg1_bri[2]; + u32 fdma_ctl; + u32 fdma_fadr; + u32 fdma_dadr; + u32 fdma_end_dadr; +}; +check_member(mt8192_nor_regs, fdma_end_dadr, 0x724); +static struct mt8192_nor_regs *const mt8192_nor = (void *)SFLASH_REG_BASE; + +int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); + +#endif /* __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h new file mode 100644 index 0000000000..716a63d08e --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/gpio.h @@ -0,0 +1,726 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_GPIO_H +#define SOC_MEDIATEK_MT8192_GPIO_H + +#include +#include +#include + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +enum { + PIN(0, EINT0, 0, 9, 0x23, 0xb0, + SPI6_CLK, I2S5_MCK, PWM_0, TDM_LRCK, + TP_GPIO0_AO, MD_INT0, RES7), + PIN(1, EINT1, 0, 10, 0x23, 0xb0, + SPI6_CSB, I2S5_BCK, PWM_1, TDM_BCK, + TP_GPIO1_AO, MD_INT1_C2K_UIM0_HOT_PLUG, DBG_MON_A9), + PIN(2, EINT2, 0, 11, 0x23, 0xb0, + SPI6_MI, I2S5_LRCK, PWM_2, TDM_MCK, + TP_GPIO2_AO, MD_INT2_C2K_UIM1_HOT_PLUG, DBG_MON_A10), + PIN(3, EINT3, 0, 12, 0x23, 0xb0, + SPI6_MO, I2S5_DO, PWM_3, TDM_DATA0, + TP_GPIO3_AO, CLKM0, DBG_MON_A11), + PIN(4, EINT4, 0, 13, 0x23, 0xb0, + SPI4_A_CLK, I2S2_MCK, DMIC1_CLK, TDM_DATA1, + TP_GPIO4_AO, PCM1_DI, IDDIG), + PIN(5, EINT5, 0, 14, 0x23, 0xb0, + SPI4_A_CSB, I2S2_BCK, DMIC1_DAT, + TDM_DATA2, TP_GPIO5_AO, PCM1_CLK, USB_DRVVBUS), + PIN(6, EINT6, 0, 15, 0x23, 0xb0, + SPI4_A_MI, I2S2_LRCK, DMIC_CLK, TDM_DATA3, + TP_GPIO6_AO, PCM1_SYNC, RES7), + PIN(7, EINT7, 0, 16, 0x23, 0xb0, + SPI4_A_MO, I2S2_DI, DMIC_DAT, WIFI_TXD, + TP_GPIO7_AO, PCM1_DO0, RES7), + PIN(8, EINT8, 0, 17, 0x23, 0xb0, + SRCLKENAI1, I2S2_DI2, KPCOL2, + CONN_TCXOENA_REQ, CLKM1, PCM1_DO1, DBG_MON_A12), + PIN(9, EINT9, 0, 18, 0x23, 0xb0, + SRCLKENAI0, DVFSRC_EXT_REQ, KPROW2, + CMMCLK4, CLKM3, PCM1_DO2, DBG_MON_A13), + PIN(10, EINT10, 1, 0, 0x15, 0x20, + MSDC2_CLK, SPI4_B_CLK, I2S8_MCK, + RES4, MD_INT0, TP_GPIO8_AO, RES7), + PIN(11, EINT11, 1, 1, 0x15, 0x20, + MSDC2_CMD, SPI4_B_CSB, I2S8_BCK, PCIE_CLKREQ_N, + MD_INT1_C2K_UIM0_HOT_PLUG, TP_GPIO9_AO, RES7), + PIN(12, EINT12, 1, 2, 0x15, 0x20, + MSDC2_DAT3, SPI4_B_MI, I2S8_LRCK, DMIC1_CLK, + MD_INT2_C2K_UIM1_HOT_PLUG, TP_GPIO10_AO, RES7), + PIN(13, EINT13, 1, 3, 0x15, 0x20, + DMSDC2_DAT0, SPI4_B_MO, I2S8_DI, DMIC1_DAT, + ANT_SEL10, TP_GPIO11_AO, RES7), + PIN(14, EINT14, 1, 4, 0x15, 0x20, + MSDC2_DAT2, IDDIG, SCL_6306, PCIE_PERESET_N, + ANT_SEL11, TP_GPIO12_AO, RES7), + PIN(15, EINT15, 1, 5, 0x15, 0x20, + MSDC2_DAT1, USB_DRVVBUS, SDA_6306, + PCIE_WAKE_N, ANT_SEL12, TP_GPIO13_AO, RES7), + PIN(16, EINT16, 0, 2, 0x17, 0x50, + SRCLKENAI1, IDDIG, TP_GPIO14_AO, KPCOL2, + GPS_L1_ELNA_EN, SPI7_A_MI, DBG_MON_A0), + PIN(17, EINT17, 0, 3, 0x17, 0x50, + SRCLKENAI0, USB_DRVVBUS, TP_GPIO15_AO, + KPROW2, RES5, SPI7_A_MO, DBG_MON_A1), + PIN(18, EINT18, 0, 21, 0x36, 0xa0, + SRCLKENAI0, SPI4_C_MI, SPI1_B_MI, + GPS_L1_ELNA_EN, ANT_SEL10, MD_INT0, DBG_MON_B2), + PIN(19, EINT19, 0, 22, 0x36, 0xa0, + SRCLKENAI1, SPI4_C_MO, SPI1_B_MO, RES4, + ANT_SEL11, MD_INT1_C2K_UIM0_HOT_PLUG, DBG_MON_B3), + PIN(20, EINT20, 0, 23, 0x36, 0xa0, + SRCLKENAI0, SPI4_C_CLK, SPI1_B_CLK, PWM_3, + ANT_SEL12, MD_INT2_C2K_UIM1_HOT_PLUG, DBG_MON_B4), + PIN(21, EINT21, 0, 24, 0x36, 0xa0, + RES1, SPI4_C_CSB, SPI1_B_CSB, RES4, + RES5, IDDIG, DBG_MON_B5), + PIN(22, EINT22, 0, 3, 0x21, 0x90, + RES1, SPI0_C_CLK, SPI7_B_CLK, I2S7_BCK, + I2S9_BCK, SCL_6306, RES7), + PIN(23, EINT23, 0, 4, 0x21, 0x90, + RES1, SPI0_C_CSB, SPI7_B_CSB, I2S7_LRCK, + I2S9_LRCK, SDA_6306, RES7), + PIN(24, EINT24, 0, 5, 0x21, 0x90, + SRCLKENAI1, SPI0_C_MI, SPI7_B_MI, I2S6_DI, + I2S8_DI, SPINOR_CS, RES7), + PIN(25, EINT25, 0, 6, 0x21, 0x90, + SRCLKENAI0, SPI0_C_MO, SPI7_B_MO, + I2S7_DO, I2S9_DO, SPINOR_CK, RES7), + PIN(26, PERIPHERAL_EN4, 0, 5, 0x22, 0x80, + PWM_2, CLKM0, USB_DRVVBUS, SPI5_C_MI, + I2S9_BCK, RES6, RES7), + PIN(27, PERIPHERAL_EN5, 0, 6, 0x22, 0x80, + PWM_3, CLKM1, RES3, SPI5_C_MO, + I2S9_LRCK, SPINOR_IO0, RES7), + PIN(28, PERIPHERAL_EN6, 0, 7, 0x22, 0x80, + PWM_0, CLKM2, RES3, SPI5_C_CSB, + I2S9_MCK, SPINOR_IO1, RES7), + PIN(29, PERIPHERAL_EN7, 0, 8, 0x22, 0x80, + PWM_1, CLKM3, RES3, SPI5_C_CLK, + I2S9_DO, SPINOR_IO2, RES7), + PIN(30, PERIPHERAL_EN8, 0, 9, 0x22, 0x80, + PWM_2, CLKM0, GPS_L1_ELNA_EN, I2S7_MCK, + I2S9_MCK, SPINOR_IO3, RES7), + PIN(31, I2S3_MCK, 0, 27, 0x22, 0x70, + I2S3_MCK, I2S1_MCK, I2S5_MCK, + SRCLKENAI0, I2S0_MCK, RES6, RES7), + PIN(32, I2S3_BCK, 0, 24, 0x22, 0x70, + I2S3_BCK, I2S1_BCK, I2S5_BCK, + PCM0_CLK, I2S0_BCK, RES6, RES7), + PIN(33, I2S3_LRCK, 0, 26, 0x22, 0x70, + I2S3_LRCK, I2S1_LRCK, I2S5_LRCK, + PCM0_SYNC, I2S0_LRCK, RES6, RES7), + PIN(34, I2S0_DI, 0, 23, 0x22, 0x70, + I2S3_DO, I2S1_DO, I2S5_DO, PCM0_DO, + RES5, RES6, RES7), + PIN(35, I2S3_DO, 0, 25, 0x22, 0x70, + I2S3_DO, I2S1_DO, I2S5_DO, + PCM0_DO, RES5, RES6, RES7), + PIN(36, SPI5_CLK, 0, 20, 0x21, 0x90, + SPI5_A_CLK, DMIC1_CLK, RES3, + MD_URXD0, UCTS0, URXD1, RES7), + PIN(37, SPI5_CSB, 0, 21, 0x21, 0x90, + SPI5_A_CSB, DMIC1_DAT, RES3, + MD_UTXD0, URTS0, UTXD1, RES7), + PIN(38, SPI5_MI, 0, 22, 0x21, 0x90, + SPI5_A_MI, DMIC_CLK, RES3, + MD_URXD1, URXD0, UCTS1, RES7), + PIN(39, SPI5_MO, 0, 23, 0x21, 0x90, + SPI5_A_MO, DMIC_DAT, RES3, + MD_UTXD1, UTXD0, URTS1, RES7), + PIN(40, DISP_PWM, 0, 0, 0x17, 0x50, + DISP_PWM, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A6), + PIN(41, DSI_TE, 0, 1, 0x17, 0x50, + DSI_TE, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A7), + PIN(42, LCM_RST, 0, 4, 0x17, 0x50, + LCM_RST, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A8), + PIN(43, INT_SIM1, 0, 25, 0x36, 0xa0, + MD_INT1_C2K_UIM0_HOT_PLUG, MD_INT2_C2K_UIM1_HOT_PLUG, + SCL_6306, ADSP_URXD0, PTA_RXD, SSPM_URXD_AO, DBG_MON_B0), + PIN(44, INT_SIM2, 0, 26, 0x36, 0xa0, + MD_INT2_C2K_UIM1_HOT_PLUG, MD_INT1_C2K_UIM0_HOT_PLUG, + SDA_6306, ADSP_UTXD0, PTA_TXD, SSPM_UTXD_AO, DBG_MON_B1), + PIN(45, SIM2_SCLK, 1, 9, 0x20, 0x60, + MD1_SIM2_SCLK, MD1_SIM1_SCLK, MCUPM_JTAG_TDI, + APU_JTAG_TDI, CCU_JTAG_TDI, LVTS_SCK, CONN_DSP_JDI), + PIN(46, SIM2_SRST, 1, 11, 0x20, 0x60, + MD1_SIM2_SRST, MD1_SIM1_SRST, MCUPM_JTAG_TMS, + APU_JTAG_TMS, CCU_JTAG_TMS, LVTS_SDI, CONN_DSP_JMS), + PIN(47, SIM2_SIO, 1, 10, 0x20, 0x60, + MD1_SIM2_SIO, MD1_SIM1_SIO, MCUPM_JTAG_TDO, + APU_JTAG_TDO, CCU_JTAG_TDO, LVTS_SCF, CONN_DSP_JDO), + PIN(48, SIM1_SIO, 1, 7, 0x20, 0x60, + MD1_SIM1_SIO, MD1_SIM2_SIO, MCUPM_JTAG_TRSTN, + APU_JTAG_TRST, CCU_JTAG_TRST, LVTS_FOUT, CONN_DSP_JINTP), + PIN(49, SIM1_SRST, 1, 8, 0x20, 0x60, + MD1_SIM1_SRST, MD1_SIM2_SRST, MCUPM_JTAG_TCK, + APU_JTAG_TCK, CCU_JTAG_TCK, LVTS_SDO, CONN_DSP_JCK), + PIN(50, SIM1_SCLK, 1, 6, 0x20, 0x60, + MD1_SIM1_SCLK, MD1_SIM2_SCLK, RES3, + RES4, RES5, LVTS_26M, RES7), + PIN(51, MSDC1_CLK, 1, 0, 0x20, 0x60, + MSDC1_CLK, PCM1_CLK, CONN_DSP_JCK, UDI_TCK, + IPU_JTAG_TCK, SSPM_JTAG_TCK, JTCK_SEL3), + PIN(52, MSDC1_CMD, 1, 1, 0x20, 0x60, + MSDC1_CMD, PCM1_SYNC, CONN_DSP_JMS, UDI_TMS, + IPU_JTAG_TMS, SSPM_JTAG_TMS, JTMS_SEL3), + PIN(53, MSDC1_DAT3, 1, 5, 0x20, 0x60, + MSDC1_DAT3, PCM1_DI, CONN_DSP_JINTP, + CONN_MCU_AICE_TMSC, RES5, RES6, RES7), + PIN(54, MSDC1_DAT0, 1, 2, 0x20, 0x60, + MSDC1_DAT0, PCM1_DO0, CONN_DSP_JDI, + UDI_TDI, IPU_JTAG_TDI, SSPM_JTAG_TDI, JTDI_SEL3), + PIN(55, MSDC1_DAT2, 1, 4, 0x20, 0x60, + MSDC1_DAT2, PCM1_DO2, CONN_MCU_AICE_TCKC, + UDI_NTRST, IPU_JTAG_TRST, SSPM_JTAG_TRSTN, JTRSTN_SEL3), + PIN(56, MSDC1_DAT1, 1, 3, 0x20, 0x60, + MSDC1_DAT1, PCM1_DO1, CONN_DSP_JDO, UDI_TDO, + IPU_JTAG_TDO, SSPM_JTAG_TDO, JTDO_SEL3), + PIN(57, MIPI2_D_SCLK, 0, 1, 0x22, 0x80, + MIPI2_D_SCLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(58, MIPI2_D_SDATA, 0, 2, 0x22, 0x80, + MIPI2_D_SDATA, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(59, MIPI_M_SCLK, 0, 3, 0x22, 0x80, + MIPI_M_SCLK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(60, MIPI_M_SDATA, 0, 4, 0x22, 0x80, + MIPI_M_SDATA, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(61, MD_UCNT, 0, 28, 0x22, 0x70, + MD_UCNT_A_TGL, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(62, DIGRF_IRQ, 0, 22, 0x22, 0x70, + DIGRF_IRQ, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(63, BPI_D_BUS0, 0, 0, 0x22, 0x70, + BPI_BUS0, RES2, PCIE_WAKE_N, + RES4, RES5, RES6, RES7), + PIN(64, BPI_D_BUS1, 0, 1, 0x22, 0x70, + BPI_BUS1, RES2, PCIE_PERESET_N, + RES4, RES5, RES6, RES7), + PIN(65, BPI_D_BUS2, 0, 12, 0x22, 0x70, + BPI_BUS2, RES2, PCIE_CLKREQ_N, + RES4, RES5, RES6, RES7), + PIN(66, BPI_D_BUS3, 0, 15, 0x22, 0x70, + BPI_BUS3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(67, BPI_D_BUS4, 0, 16, 0x22, 0x70, + BPI_BUS4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(68, BPI_D_BUS5, 0, 17, 0x22, 0x70, + BPI_BUS5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(69, BPI_D_BUS6, 0, 18, 0x22, 0x70, + BPI_BUS6, CONN_BPI_BUS6, + RES3, RES4, RES5, RES6, RES7), + PIN(70, BPI_D_BUS7, 0, 19, 0x22, 0x70, + BPI_BUS7, CONN_BPI_BUS7, RES3, + RES4, RES5, RES6, RES7), + PIN(71, BPI_D_BUS8, 0, 20, 0x22, 0x70, + BPI_BUS8, CONN_BPI_BUS8, + RES3, RES4, RES5, RES6, RES7), + PIN(72, BPI_D_BUS9, 0, 21, 0x22, 0x70, + BPI_BUS9, CONN_BPI_BUS9, + RES3, RES4, RES5, RES6, RES7), + PIN(73, BPI_D_BUS10, 0, 2, 0x22, 0x70, + BPI_BUS10, CONN_BPI_BUS10, + RES3, RES4, RES5, RES6, RES7), + PIN(74, BPI_D_BUS11_OLAT0, 0, 3, 0x22, 0x70, + BPI_BUS11_OLAT0, CONN_BPI_BUS11_OLAT0, + RES3, RES4, RES5, RES6, RES7), + PIN(75, BPI_D_BUS12_OLAT1, 0, 4, 0x22, 0x70, + BPI_BUS12_OLAT1, CONN_BPI_BUS12_OLAT1, + RES3, RES4, RES5, RES6, RES7), + PIN(76, BPI_D_BUS13_OLAT2, 0, 5, 0x22, 0x70, + BPI_BUS13_OLAT2, CONN_BPI_BUS13_OLAT2, + RES3, RES4, RES5, RES6, RES7), + PIN(77, BPI_D_BUS14_OLAT3, 0, 6, 0x22, 0x70, + BPI_BUS14_OLAT3, CONN_BPI_BUS14_OLAT3, + RES3, RES4, RES5, RES6, RES7), + PIN(78, BPI_D_BUS15_OLAT4, 0, 7, 0x22, 0x70, + BPI_BUS15_OLAT4, CONN_BPI_BUS15_OLAT4, + RES3, RES4, RES5, RES6, RES7), + PIN(79, BPI_D_BUS16_OLAT5, 0, 8, 0x22, 0x70, + BPI_BUS16_OLAT5, CONN_BPI_BUS16_OLAT5, + RES3, RES4, RES5, RES6, RES7), + PIN(80, BPI_D_BUS17_ANT0, 0, 9, 0x22, 0x70, + BPI_BUS17_ANT0, CONN_BPI_BUS17_ANT0, + PCIE_WAKE_N, RES4, RES5, RES6, RES7), + PIN(81, BPI_D_BUS18_ANT1, 0, 10, 0x22, 0x70, + BPI_BUS18_ANT1, CONN_BPI_BUS18_ANT1, + PCIE_PERESET_N, RES4, RES5, RES6, RES7), + PIN(82, BPI_D_BUS19_ANT2, 0, 11, 0x22, 0x70, + BPI_BUS19_ANT2, CONN_BPI_BUS19_ANT2, + PCIE_CLKREQ_N, RES4, RES5, RES6, RES7), + PIN(83, BPI_D_BUS20_ANT3, 0, 13, 0x22, 0x70, + BPI_BUS20_ANT3, CONN_BPI_BUS20_ANT3, + RES3, RES4, RES5, RES6, RES7), + PIN(84, BPI_D_BUS21_ANT4, 0, 14, 0x22, 0x70, + BPI_BUS21_ANT4, CONN_BPI_BUS21_ANT4, + RES3, RES4, RES5, RES6, RES7), + PIN(85, MIPI1_D_SCLK, 0, 31, 0x22, 0x70, + MIPI1_D_SCLK, CONN_MIPI1_SCLK, + RES3, RES4, RES5, RES6, RES7), + PIN(86, MIPI1_D_SDATA, 0, 0, 0x22, 0x80, + MIPI1_D_SDATA, CONN_MIPI1_SDATA, + RES3, RES4, RES5, RES6, RES7), + PIN(87, MIPI0_D_SCLK, 0, 29, 0x22, 0x70, + MIPI0_D_SCLK, CONN_MIPI0_SCLK, + RES3, RES4, RES5, RES6, RES7), + PIN(88, MIPI0_D_SDATA, 0, 30, 0x22, 0x70, + SMIPI0_D_SDATA, CONN_MIPI0_SDATA, + RES3, RES4, RES5, RES6, RES7), + PIN(89, SPMI_SCL, 0, 24, 0x21, 0x90, + SPMI_SCL, SCL10, RES3, + RES4, RES5, RES6, RES7), + PIN(90, SPMI_SDA, 0, 25, 0x21, 0x90, + SPMI_SDA, SDA10, RES3, + RES4, RES5, RES6, RES7), + PIN(91, AP_GOOD, 0, 0, 0x21, 0x90, + AP_GOOD, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(92, URXD0, 0, 2, 0x21, 0xa0, + URXD0, MD_URXD0, MD_URXD1, + SSPM_URXD_AO, CONN_UART0_RXD, RES6, RES7), + PIN(93, UTXD0, 0, 4, 0x21, 0xa0, + UTXD0, MD_UTXD0, MD_UTXD1, SSPM_UTXD_AO, + CONN_UART0_TXD, WIFI_TXD, RES7), + PIN(94, URXD1, 0, 3, 0x21, 0xa0, + URXD1, ADSP_URXD0, MD32_0_RXD, + SSPM_URXD_AO, TP_URXD1_AO, TP_URXD2_AO, MBISTREADEN_TRIGGER), + PIN(95, UTXD1, 0, 5, 0x21, 0xa0, + UTXD1, ADSP_UTXD0, MD32_0_TXD, SSPM_UTXD_AO, + TP_UTXD1_AO, TP_UTXD2_AO, MBISTWRITEEN_TRIGGER), + PIN(96, TDM_LRCK, 0, 31, 0x21, 0x90, + TDM_LRCK, I2S7_LRCK, I2S9_LRCK, + DPI_D0, ADSP_JTAG0_TDI, RES6, IO_JTAG_TDI), + PIN(97, TDM_BCK, 0, 26, 0x21, 0x90, + TDM_BCK, I2S7_BCK, I2S9_BCK, DPI_D1, + ADSP_JTAG0_TRSTN, RES6, IO_JTAG_TRSTN), + PIN(98, TDM_MCLK, 0, 0, 0x21, 0xa0, + TDM_MCK, I2S7_MCK, I2S9_MCK, DPI_D2, + ADSP_JTAG0_TCK, RES6, IO_JTAG_TCK), + PIN(99, TDM_DATA0, 0, 27, 0x21, 0x90, + TDM_DATA0, I2S6_DI, I2S8_DI, DPI_D3, + ADSP_JTAG0_TDO, RES6, IO_JTAG_TDO), + PIN(100, TDM_DATA1, 0, 28, 0x21, 0x90, + TDM_DATA1, I2S7_DO, I2S9_DO, DPI_D4, + ADSP_JTAG0_TMS, RES6, IO_JTAG_TMS), + PIN(101, TDM_DATA2, 0, 29, 0x21, 0x90, + TDM_DATA2, DMIC1_CLK, SRCLKENAI0, DPI_D5, + CLKM0, RES6, DAP_MD32_SWD), + PIN(102, TDM_DATA3, 0, 30, 0x21, 0x90, + TDM_DATA3, DMIC1_DAT, SRCLKENAI1, + DPI_D6, RES5, DVFSRC_EXT_REQ, DAP_MD32_SWCK), + PIN(103, SPI0_MI, 0, 18, 0x21, 0x90, + SPI0_A_MI, SCP_SPI0_MI, RES3, DPI_D7, + DFD_TDO, SPM_JTAG_TDO, JTDO_SEL1), + PIN(104, SPI0_CSB, 0, 17, 0x21, 0x90, + SPI0_A_CSB, SCP_SPI0_CS, RES3, DPI_D8, DFD_TMS, + SPM_JTAG_TMS, JTMS_SEL1), + PIN(105, SPI0_MO, 0, 19, 0x21, 0x90, + SPI0_A_MO, SCP_SPI0_MO, SCP_SDA0, DPI_D9, + DFD_TDI, SPM_JTAG_TDI, JTDI_SEL1), + PIN(106, SPI0_CLK, 0, 16, 0x21, 0x90, + SPI0_A_CLK, SCP_SPI0_CK, SCP_SCL0, + DPI_D10, DFD_TCK_XI, SPM_JTAG_TCK, JTCK_SEL1), + PIN(107, DMIC_CLK, 0, 1, 0x21, 0x90, + DMIC_CLK, PWM_0, CLKM2, RES4, RES5, + SPM_JTAG_TRSTN, JTRSTN_SEL1), + PIN(108, DMIC_DAT, 0, 2, 0x21, 0x90, + DMIC_DAT, PWM_1, CLKM3, RES4, + RES5, RES6, DAP_SONIC_SWD), + PIN(109, I2S1_MCK, 0, 10, 0x21, 0x90, + I2S1_MCK, I2S3_MCK, I2S2_MCK, DPI_DE, + I2S2_MCK_1, SRCLKENAI0, DAP_SONIC_SWCK), + PIN(110, I2S1_BCK, 0, 7, 0x21, 0x90, + I2S1_BCK, I2S3_BCK, I2S2_BCK, DPI_D11, + I2S2_BCK_1, CONN_MCU_TDO, RES7), + PIN(111, I2S1_LRCK, 0, 9, 0x21, 0x90, + I2S1_LRCK, I2S3_LRCK, I2S2_LRCK, + DPI_VSYNC, I2S2_LRCK_1, CONN_MCU_TDI, RES7), + PIN(112, I2S2_DI, 0, 11, 0x21, 0x90, + I2S2_DI, I2S0_DI, I2S2_DI2, DPI_CK, + I2S2_DI_1, CONN_MCU_TMS, RES7), + PIN(113, I2S1_DO, 0, 8, 0x21, 0x90, + I2S1_DO, I2S3_DO, I2S5_DO, DPI_HSYNC, + I2S2_DI2, CONN_MCU_TCK, RES7), + PIN(114, SCP_SPI2_MI, 0, 14, 0x21, 0x90, + SPI2_MI, SCP_SPI2_MI, RES3, + PCM0_DI, RES5, CONN_MCU_TRST_B, RES7), + PIN(115, SCP_SPI2_CSB, 0, 13, 0x21, 0x90, + SPI2_CSB, SCP_SPI2_CS, RES3, PCM0_SYNC, + RES5, CONN_MCU_DBGI_N, RES7), + PIN(116, SCP_SPI2_MO, 0, 15, 0x21, 0x90, + SPI2_MO, SCP_SPI2_MO, SCP_SDA1, + PCM0_DO, RES5, CONN_MCU_DBGACK_N, RES7), + PIN(117, SCP_SPI2_CK, 0, 12, 0x21, 0x90, + SPI2_CLK, SCP_SPI2_CK, SCP_SCL1, + PCM0_CLK, RES5, RES6, RES7), + PIN(118, SCL1, 0, 23, 0x23, 0xb0, + SCL1, SCP_SCL0, SCP_SCL1, + RES4, RES5, RES6, RES7), + PIN(119, SDA1, 0, 29, 0x23, 0xb0, + SDA1, SCP_SDA0, SCP_SDA1, + RES4, RES5, RES6, RES7), + PIN(120, SCL9, 0, 28, 0x23, 0xb0, + SCL9, SCP_SCL0, RES3, + RES4, RES5, RES6, RES7), + PIN(121, SDA9, 0, 2, 0x23, 0xc0, + SDA9, SCP_SDA0, RES3, + RES4, RES5, RES6, RES7), + PIN(122, SCL8, 0, 27, 0x23, 0xb0, + SCL8, SCP_SDA0, RES3, + RES4, RES5, RES6, RES7), + PIN(123, SDA8, 0, 1, 0x23, 0xc0, + SDA8, SCP_SCL0, RES3, + RES4, RES5, RES6, RES7), + PIN(124, SCL7, 0, 26, 0x23, 0xb0, + SCL7, DMIC1_CLK, RES3, + RES4, RES5, RES6, RES7), + PIN(125, SDA7, 0, 0, 0x23, 0xc0, + SDA7, DMIC1_DAT, RES3, + RES4, RES5, RES6, RES7), + PIN(126, PERIPHERAL_EN0, 0, 19, 0x23, 0xb0, + CMFLASH0, PWM_2, TP_UCTS1_AO, + UCTS0, SCL11, GPS_L1_ELNA_EN, DBG_MON_A14), + PIN(127, PERIPHERAL_EN1, 0, 20, 0x23, 0xb0, + CMFLASH1, PWM_3, TP_URTS1_AO, URTS0, + SDA11, RES6, DBG_MON_A15), + PIN(128, PERIPHERAL_EN2, 0, 21, 0x23, 0xb0, + CMFLASH2, PWM_0, TP_UCTS2_AO, + UCTS1, SCL_6306, RES6, DBG_MON_A16), + PIN(129, PERIPHERAL_EN3, 0, 22, 0x23, 0xb0, + CMFLASH3, PWM_1, TP_URTS2_AO, URTS1, + SDA_6306, RES6, DBG_MON_A17), + PIN(130, CAM_RST3, 0, 6, 0x23, 0xb0, + CMVREF0, ANT_SEL10, SCP_JTAG0_TDO, + MD32_0_JTAG_TDO, SCL11, SPI5_B_CLK, DBG_MON_A22), + PIN(131, CAM_RST4, 0, 7, 0x23, 0xb0, + CMVREF1, ANT_SEL11, SCP_JTAG0_TDI, + MD32_0_JTAG_TDI, SDA11, SPI5_B_MO, DBG_MON_A25), + PIN(132, CAM_RST5, 0, 8, 0x23, 0xb0, + CMVREF2, ANT_SEL12, SCP_JTAG0_TMS, + MD32_0_JTAG_TMS, RES5, RES6, DBG_MON_A28), + PIN(133, CAM_PDN3, 0, 3, 0x23, 0xb0, + CMVREF3, GPS_L1_ELNA_EN, SCP_JTAG0_TCK, + MD32_0_JTAG_TCK, CMMCLK5, SPI5_B_CSB, DBG_MON_A23), + PIN(134, CAM_PDN4, 0, 4, 0x23, 0xb0, + CMVREF4, RES2, SCP_JTAG0_TRSTN, + MD32_0_JTAG_TRST, RES5, RES6, DBG_MON_A26), + PIN(135, CAM_PDN5, 0, 5, 0x23, 0xb0, + PWM_0, SRCLKENAI1, MD_URXD0, + MD32_0_RXD, CONN_TCXOENA_REQ, RES6, DBG_MON_A29), + PIN(136, CAM_CLK3, 0, 0, 0x23, 0xb0, + CMMCLK3, CLKM1, MD_UTXD0, MD32_0_TXD, + RES5, SPI5_B_MI, DBG_MON_A24), + PIN(137, CAM_CLK4, 0, 1, 0x23, 0xb0, + CMMCLK4, CLKM2, MD_URXD1, RES4, + RES5, CONN_UART0_RXD, DBG_MON_A27), + PIN(138, CAM_CLK5, 0, 2, 0x23, 0xb0, + CMMCLK5, CLKM3, MD_UTXD1, + RES4, RES5, CONN_UART0_TXD, DBG_MON_A30), + PIN(139, SCL4, 0, 25, 0x23, 0xb0, + SCL4, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A21), + PIN(140, SDA4, 0, 31, 0x23, 0xb0, + SDA4, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A20), + PIN(141, SCL2, 0, 24, 0x23, 0xb0, + SCL2, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A18), + PIN(142, SDA2, 0, 30, 0x23, 0xb0, + SDA2, RES2, RES3, RES4, + RES5, RES6, DBG_MON_A19), + PIN(143, CAM_RST0, 0, 6, 0x20, 0x70, + CMVREF0, SPI3_CLK, ADSP_JTAG1_TDO, + SCP_JTAG1_TDO, RES5, RES6, DBG_MON_A31), + PIN(144, CAM_RST1, 0, 7, 0x20, 0x70, + CMVREF1, SPI3_CSB, ADSP_JTAG1_TDI, + SCP_JTAG1_TDI, RES5, RES6, RES7), + PIN(145, CAM_RST2, 0, 8, 0x20, 0x70, + CMVREF2, SPI3_MI, ADSP_JTAG1_TMS, + SCP_JTAG1_TMS, RES5, RES6, RES7), + PIN(146, CAM_PDN0, 0, 3, 0x20, 0x70, + CMVREF3, SPI3_MO, ADSP_JTAG1_TCK, + SCP_JTAG1_TCK, RES5, RES6, DBG_MON_A32), + PIN(147, CAM_PDN1, 0, 4, 0x20, 0x70, + CMVREF4, EXT_FRAME_SYNC, ADSP_JTAG1_TRSTN, + SCP_JTAG1_TRSTN, RES5, RES6, RES7), + PIN(148, CAM_PDN2, 0, 5, 0x20, 0x70, + PWM_1, AGPS_SYNC, RES3, RES4, + RES5, RES6, RES7), + PIN(149, CAM_CLK0, 0, 0, 0x20, 0x70, + CMMCLK0, CLKM0, MD32_0_GPIO0, + RES4, RES5, RES6, RES7), + PIN(150, CAM_CLK1, 0, 1, 0x20, 0x70, + CMMCLK1, CLKM1, MD32_0_GPIO1, + RES4, RES5, RES6, CONN_MCU_AICE_TMSC), + PIN(151, CAM_CLK2, 0, 2, 0x20, 0x70, + CMMCLK2, CLKM2, MD32_0_GPIO2, + RES4, RES5, RES6, CONN_MCU_AICE_TCKC), + PIN(152, KPROW1, 1, 3, 0x36, 0x90, + KPROW1, PWM_2, IDDIG, RES4, RES5, + MBISTREADEN_TRIGGER, DBG_MON_B9), + PIN(153, KPROW0, 1, 2, 0x36, 0x90, + KPROW0, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B8), + PIN(154, KPCOL0, 1, 0, 0x36, 0x90, + KPCOL0, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B6), + PIN(155, KPCOL1, 1, 1, 0x36, 0x90, + KPCOL1, PWM_3, USB_DRVVBUS, CONN_TCXOENA_REQ, + RES5, MBISTWRITEEN_TRIGGER, DBG_MON_B7), + PIN(156, SPI1_CLK, 0, 29, 0x36, 0xa0, + SPI1_A_CLK, SCP_SPI1_A_CK, MRG_CLK, + AGPS_SYNC, MD_URXD0, UDI_TMS, DBG_MON_B10), + PIN(157, SPI1_CSB, 0, 30, 0x36, 0xa0, + SPI1_A_CSB, SCP_SPI1_A_CS, MRG_SYNC, + EXT_FRAME_SYNC, MD_UTXD0, UDI_TCK, DBG_MON_B11), + PIN(158, SPI1_MI, 0, 31, 0x36, 0xa0, + SPI1_A_MI, SCP_SPI1_A_MI, MRG_DI, + PTA_RXD, MD_URXD1, UDI_TDO, DBG_MON_B12), + PIN(159, SPI1_MO, 0, 0, 0x36, 0xb0, + SPI1_A_MO, SCP_SPI1_A_MO, MRG_DO, PTA_TXD, + MD_UTXD1, UDI_NTRST, DBG_MON_B13), + PIN(160, SCL3, 0, 27, 0x36, 0xa0, + SCL3, RES2, SCP_SCL1, RES4, + RES5, RES6, DBG_MON_B14), + PIN(161, SDA3, 0, 28, 0x36, 0xa0, + SDA3, RES2, SCP_SDA1, RES4, + RES5, RES6, DBG_MON_B15), + PIN(162, ANT_SEL0, 0, 0, 0x36, 0xa0, + ANT_SEL0, GPS_L1_ELNA_EN, RES3, + RES4, RES5, UDI_TDI, DBG_MON_B16), + PIN(163, ANT_SEL1, 0, 1, 0x36, 0xa0, + ANT_SEL1, CONN_TCXOENA_REQ, RES3, + RES4, RES5, RES6, DBG_MON_B17), + PIN(164, ANT_SEL2, 0, 2, 0x36, 0xa0, + ANT_SEL2, SCP_SPI1_B_CK, TP_URXD1_AO, + RES4, UCTS0, RES6, DBG_MON_B18), + PIN(165, ANT_SEL3, 0, 3, 0x36, 0xa0, + ANT_SEL3, SCP_SPI1_B_CS, TP_UTXD1_AO, + CONN_TCXOENA_REQ, URTS0, RES6, DBG_MON_B19), + PIN(166, ANT_SEL4, 0, 4, 0x36, 0xa0, + ANT_SEL4, SCP_SPI1_B_MI, TP_URXD2_AO, + SRCLKENAI1, UCTS1, RES6, DBG_MON_B207), + PIN(167, ANT_SEL5, 0, 5, 0x36, 0xa0, + ANT_SEL5, SCP_SPI1_B_MO, TP_UTXD2_AO, + SRCLKENAI0, URTS1, RES6, DBG_MON_B21), + PIN(168, ANT_SEL6, 0, 6, 0x36, 0xa0, + ANT_SEL6, SPI0_B_CLK, TP_UCTS1_AO, + KPCOL2, MD_UCTS0, SCL11, DBG_MON_B22), + PIN(169, ANT_SEL7, 0, 7, 0x36, 0xa0, + ANT_SEL7, SPI0_B_CSB, TP_URTS1_AO, KPROW2, + MD_URTS0, SDA11, DBG_MON_B23), + PIN(170, ANT_SEL8, 0, 8, 0x36, 0xa0, + ANT_SEL8, SPI0_B_MI, TP_UCTS2_AO, + SRCLKENAI1, MD_UCTS1, RES6, DBG_MON_B24), + PIN(171, ANT_SEL9, 0, 9, 0x36, 0xa0, + ANT_SEL9, SPI0_B_MO, TP_URTS2_AO, + SRCLKENAI0, MD_URTS1, RES6, DBG_MON_B25), + PIN(172, CONN_TOP_CLK, 0, 13, 0x36, 0xa0, + CONN_TOP_CLK, AUXIF_CLK0, RES3, + RES4, RES5, RES6, DBG_MON_B29), + PIN(173, CONN_TOP_DATA, 0, 14, 0x36, 0xa0, + CONN_TOP_DATA, AUXIF_ST0, RES3, + RES4, RES5, RES6, DBG_MON_B30), + PIN(174, CONN_HRST_B, 0, 12, 0x36, 0xa0, + CONN_HRST_B, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B28), + PIN(175, CONN_WB_PTA, 0, 15, 0x36, 0xa0, + CONN_WB_PTA, RES2, RES3, RES4, + RES5, RES6, DBG_MON_B31), + PIN(176, CONN_BT_CLK, 0, 10, 0x36, 0xa0, + CONN_BT_CLK, AUXIF_CLK1, RES3, RES4, + RES5, RES6, DBG_MON_B26), + PIN(177, CONN_BT_DATA, 0, 11, 0x36, 0xa0, + CONN_BT_DATA, AUXIF_ST1, RES3, + RES4, RES5, RES6, DBG_MON_B27), + PIN(178, CONN_WF_CTRL0, 0, 16, 0x36, 0xa0, + CONN_WF_CTRL0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(179, CONN_WF_CTRL1, 0, 17, 0x36, 0xa0, + CONN_WF_CTRL1, UFS_MPHY_SCL, + RES3, RES4, RES5, RES6, RES7), + PIN(180, CONN_WF_CTRL2, 0, 18, 0x36, 0xa0, + CONN_WF_CTRL2, UFS_MPHY_SDA, + RES3, RES4, RES5, RES6, RES7), + PIN(181, CONN_WF_CTRL3, 0, 19, 0x36, 0xa0, + CONN_WF_CTRL3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(182, CONN_WF_CTRL4, 0, 20, 0x36, 0xa0, + CONN_WF_CTRL4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(183, MSDC0_CMD, 1, 1, 0x18, 0x30, + MSDC0_CMD, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(184, MSDC0_DAT0, 1, 2, 0x18, 0x30, + MSDC0_DAT0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(185, MSDC0_DAT2, 1, 4, 0x18, 0x30, + MSDC0_DAT2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(186, MSDC0_DAT4, 1, 6, 0x18, 0x30, + MSDC0_DAT4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(187, MSDC0_DAT6, 1, 8, 0x18, 0x30, + MSDC0_DAT6, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(188, MSDC0_DAT1, 1, 3, 0x18, 0x30, + MSDC0_DAT1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(189, MSDC0_DAT5, 1, 7, 0x18, 0x30, + MSDC0_DAT5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(190, MSDC0_DAT7, 1, 9, 0x18, 0x30, + MSDC0_DAT7, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(191, MSDC0_DSL, 1, 10, 0x18, 0x30, + MSDC0_DSL, GPS_L1_ELNA_EN, + IDDIG, DMIC_CLK, RES5, RES6, RES7), + PIN(192, MSDC0_CLK, 1, 0, 0x18, 0x30, + MSDC0_CLK, RES2, USB_DRVVBUS, + DMIC_DAT, RES5, RES6, RES7), + PIN(193, MSDC0_DAT3, 1, 5, 0x18, 0x30, + MSDC0_DAT3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(194, MSDC0_RSTB, 1, 11, 0x18, 0x30, + MSDC0_RSTB, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(195, SCP_VREQ_VAO, 0, 16, 0x14, 0x50, + SCP_VREQ_VAO, DVFSRC_EXT_REQ, + RES3, RES4, RES5, RES6, RES7), + PIN(196, AUD_DAT_MOSI2, 0, 6, 0x14, 0x50, + AUD_DAT_MOSI2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(197, AUD_NLE_MOSI1, 0, 8, 0x14, 0x50, + AUD_NLE_MOSI1, AUD_CLK_MISO, + I2S2_MCK, I2S6_MCK, I2S8_MCK, RES6, RES7), + PIN(198, AUD_NLE_MOSI0, 0, 7, 0x14, 0x50, + AUD_NLE_MOSI0, AUD_SYNC_MISO, + I2S2_BCK, I2S6_BCK, I2S8_BCK, RES6, RES7), + PIN(199, AUD_DAT_MISO2, 0, 3, 0x14, 0x50, + AUD_DAT_MISO2, RES2, I2S2_DI2, + RES4, RES5, RES6, RES7), + PIN(200, SCL6, 0, 6, 0x17, 0x50, + SCL6, RES2, SCP_SCL1, SCL_6306, + RES5, RES6, DBG_MON_A4), + PIN(201, SDA6, 0, 8, 0x17, 0x50, + SDA6, RES2, SCP_SDA1, SDA_6306, + RES5, RES6, DBG_MON_A5), + PIN(202, SCL5, 0, 15, 0x14, 0x50, + SCL5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(203, SDA5, 0, 17, 0x14, 0x50, + SDA5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(204, SCL0, 0, 5, 0x17, 0x50, + SCL0, RES2, RES3, RES4, + RES5, SPI7_A_CLK, DBG_MON_A2), + PIN(205, SDA0, 0, 7, 0x17, 0x50, + SDA0, RES2, RES3, RES4, + RES5, SPI7_A_CSB, DBG_MON_A3), + PIN(206, SRCLKENA0, 0, 18, 0x14, 0x50, + SRCLKENA0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(207, SRCLKENA1, 0, 19, 0x14, 0x50, + SRCLKENA1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(208, WATCHDOG, 0, 20, 0x14, 0x50, + WATCHDOG, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(209, PWRAP_SPI0_MI, 0, 12, 0x14, 0x50, + PWRAP_SPI0_MI, PWRAP_SPI0_MO, + RES3, RES4, RES5, RES6, RES7), + PIN(210, PWRAP_SPI0_CSN, 0, 11, 0x14, 0x50, + PWRAP_SPI0_CSN, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(211, PWRAP_SPI0_MO, 0, 13, 0x14, 0x50, + PWRAP_SPI0_MO, PWRAP_SPI0_MI, + RES3, RES4, RES5, RES6, RES7), + PIN(212, PWRAP_SPI0_CK, 0, 10, 0x14, 0x50, + PWRAP_SPI0_CK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(213, RTC32K_CK, 0, 14, 0x14, 0x50, + RTC32K_CK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(214, AUD_CLK_MOSI, 0, 0, 0x14, 0x50, + AUD_CLK_MOSI, RES2, I2S1_MCK, + I2S7_MCK, I2S9_MCK, RES6, RES7), + PIN(215, AUD_SYNC_MOSI, 0, 9, 0x14, 0x50, + AUD_SYNC_MOSI, RES2, I2S1_BCK, + I2S7_BCK, I2S9_BCK, RES6, RES7), + PIN(216, AUD_DAT_MOSI0, 0, 4, 0x14, 0x50, + AUD_DAT_MOSI0, RES2, I2S1_LRCK, + I2S7_LRCK, I2S9_LRCK, RES6, RES7), + PIN(217, AUD_DAT_MOSI1, 0, 5, 0x14, 0x50, + AUD_DAT_MOSI1, RES2, I2S1_DO, + I2S7_DO, I2S9_DO, RES6, RES7), + PIN(218, AUD_DAT_MISO0, 0, 1, 0x14, 0x50, + AUD_DAT_MISO0, VOW_DAT_MISO, I2S2_LRCK, + I2S6_LRCK, I2S8_LRCK, RES6, RES7), + PIN(219, AUD_DAT_MISO1, 0, 2, 0x14, 0x50, + AUD_DAT_MISO1, VOW_CLK_MISO, I2S2_DI, + I2S6_DI, I2S8_DI, RES6, RES7), +}; + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +struct gpio_regs { + struct val_regs dir[7]; + uint8_t rsv00[144]; + struct val_regs dout[7]; + uint8_t rsv01[144]; + struct val_regs din[7]; + uint8_t rsv02[144]; + struct val_regs mode[28]; + uint8_t rsv03[560]; + uint32_t dram_pinmux_trapping; +}; + +check_member(gpio_regs, mode[27].val, 0x4b0); +check_member(gpio_regs, dram_pinmux_trapping, 0x6f0); + +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/gpio_base.h b/src/soc/mediatek/mt8192/include/soc/gpio_base.h new file mode 100644 index 0000000000..61e1318824 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/gpio_base.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_GPIO_BASE_H +#define SOC_MEDIATEK_MT8192_GPIO_BASE_H + +#include + +typedef union { + u32 raw; + struct { + u32 id : 8; + u32 flag : 3; + u32 bit : 5; + u32 base : 8; + u32 offset : 8; + }; +} gpio_t; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/infracfg.h b/src/soc/mediatek/mt8192/include/soc/infracfg.h new file mode 100644 index 0000000000..032e6cdd93 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/infracfg.h @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_INFRACFG_H +#define SOC_MEDIATEK_MT8192_INFRACFG_H + +#include +#include + +struct mt8192_infracfg_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; /* 0x0050 */ + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; /* 0x0070 */ + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; /* 0x00b4 */ + u32 reserved4[2]; + u32 module_sw_cg_3_set; /* 0x00c0 */ + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[5]; + u32 module_sw_cg_4_set; /* 0x00e0 */ + u32 module_sw_cg_4_clr; + u32 module_sw_cg_4_sta; + u32 reserved6[5]; + u32 i2c_dbtool_misc; /* 0x0100 */ + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved7[5]; + u32 infra_globalcon_rst0_set; /* 0x0120 */ + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst1_set; /* 0x0130 */ + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst2_set; /* 0x0140 */ + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved10[1]; + u32 infra_globalcon_rst3_set; /* 0x0150 */ + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved11[41]; + u32 infra_topaxi_si0_ctl; /* 0x0200 */ + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 reserved12[1]; + u32 infra_apb_async_sta; /* 0x0230 */ + u32 infra_topaxi_si2_ctl; + u32 infra_topaxi_fmem_mdhw_ctrl; + u32 infra_conn_gals_ctl; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved13[1]; + u32 infra_topaxi_aslice_ctrl; /* 0x0260 */ + u32 infra_topaxi_aslice_ctrl_1; + u32 infra_topaxi_aslice_ctrl_2; + u32 infra_topaxi_aslice_ctrl_3; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 infra_ssusb_dev; + u32 reserved14[1]; + u32 infra_topaxi_emi_gmc_l2c_ctrl; /* 0x0288 */ + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_cbip_slice_ctrl_2; + u32 reserved15[1]; + u32 infra_topaxi_aslice_ctrl_4; /* 0x02b8 */ + u32 reserved16[1]; + u32 infra_topaxi_protecten_mcu; /* 0x02c0 */ + u32 infra_topaxi_protecten_mcu_set; + u32 infra_topaxi_protecten_mcu_clr; + u32 reserved17[1]; + u32 infra_topaxi_protecten_mm; /* 0x02d0 */ + u32 infra_topaxi_protecten_mm_set; + u32 infra_topaxi_protecten_mm_clr; + u32 reserved18[1]; + u32 infra_topaxi_protecten_mcu_sta0; /* 0x02e0 */ + u32 infra_topaxi_protecten_mcu_sta1; + u32 infra_topaxi_protecten_mm_sta0; + u32 infra_topaxi_protecten_mm_sta1; + u32 reserved19[1]; + u32 infra_apu_master_m0_gals_ctl; /* 0x02f4 */ + u32 infra_apu_master_m1_gals_ctl; + u32 infra_topaxi_bus_dbg_con_ao; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved20[4]; + u32 md2_bank4_map0; /* 0x0350 */ + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved21[1]; + u32 ap2md_dummy; /* 0x0370 */ + u32 reserved22[3]; + u32 conn_map0; /* 0x0380 */ + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 conn_map2; + u32 conn_map3; + u32 conn_map4; + u32 module_clk_sel_set; + u32 module_clk_sel_clr; + u32 pmicw_clock_ctrl_set; + u32 pmicw_clock_ctrl_clr; + u32 dramc_wbr_set; + u32 dramc_wbr_clr; + u32 topaxi_si0_ctl_set; + u32 topaxi_si0_ctl_clr; + u32 topaxi_si1_ctl_set; + u32 topaxi_si1_ctl_clr; + u32 reserved23[14]; + u32 peri_cci_sideband_con; /* 0x0400 */ + u32 mfg_cci_sideband_con; + u32 reserved24[2]; + u32 infra_pwm_cksw_ctrl; /* 0x0410 */ + u32 reserved25[59]; + u32 infra_ao_dbg_con0; /* 0x0500 */ + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 infra_ao_dbg_sta; + u32 reserved26[58]; + u32 mfg_misc_con; /* 0x0600 */ + u32 reserved27[63]; + u32 infra_rsvd0; /* 0x0700 */ + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_set_2; + u32 infra_topaxi_protecten_clr_2; + u32 reserved28[1]; + u32 infra_topaxi_protecten_sta0_2; /* 0x0720 */ + u32 infra_topaxi_protecten_sta1_2; + u32 reserved29[2]; + u32 infra_globalcon_rst4_set; /* 0x0730 */ + u32 infra_globalcon_rst4_clr; + u32 infra_globalcon_rst4_sta; + u32 infra_ao_sec_rst_con4; + u32 reserved30[16]; + u32 mcu2emi_m0_parity; /* 0x0780 */ + u32 mcu2emi_m0_parity_dbg_aw_1; + u32 mcu2emi_m0_parity_dbg_aw_2; + u32 mcu2emi_m0_parity_dbg_ar_1; + u32 mcu2emi_m0_parity_dbg_ar_2; + u32 mcu2emi_m1_parity; + u32 mcu2emi_m1_parity_dbg_aw_1; + u32 mcu2emi_m1_parity_dbg_aw_2; + u32 mcu2emi_m1_parity_dbg_ar_1; + u32 mcu2emi_m1_parity_dbg_ar_2; + u32 mcu2ifr_reg_parity; + u32 mcu2ifr_reg_parity_dbg_aw_1; + u32 mcu2ifr_reg_parity_dbg_aw_2; + u32 mcu2ifr_reg_parity_dbg_ar_1; + u32 mcu2ifr_reg_parity_dbg_ar_2; + u32 ifr_l3c2mcu_parity; + u32 ifr_l3c2mcu_parity_dbg_r_1; + u32 reserved31[47]; + u32 md1_sbc_key0; /* 0x0880 */ + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved32[1]; + u32 md1_misc_lock; /* 0x08a8 */ + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved33[11]; + u32 infra_bonding; /* 0x0900 */ + u32 reserved34[63]; + u32 infra_ao_scpsys_apb_async_sta; /* 0x0a00 */ + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_mcu2apu_asl0_ctl; + u32 infra_mcu2reg_asl0_ctl; + u32 infra_mcu_decoder_infra_ctl; + u32 infra_mcu_decoder_sta0; + u32 infra_mcu_decoder_sta1; + u32 infra_idle_async_bit_en_0; + u32 infra_apu_slave_gals_ctrl; + u32 infra_aximem_idle_bit_en_0; + u32 infra_mcu_path_sync_ctl; + u32 infra_conn2ap_int_mask; + u32 infra_mcu_pwr_ctl_mask; + u32 infra_md_rsv; + u32 reserved35[7]; + u32 infra_mem_26m_cksel; /* 0x0a60 */ + u32 reserved36[39]; + u32 pll_ulposc_con0; /* 0x0b00 */ + u32 pll_ulposc_con1; + u32 reserved37[2]; + u32 pll_auxadc_con0; /* 0x0b10 */ + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 reserved38[24]; + u32 infra_topaxi_protecten_vdnr; /* 0x0b80 */ + u32 infra_topaxi_protecten_vdnr_set; + u32 infra_topaxi_protecten_vdnr_clr; + u32 infra_topaxi_protecten_vdnr_sta0; + u32 infra_topaxi_protecten_vdnr_sta1; + u32 reserved39[3]; + u32 infra_topaxi_protecten_vdnr_1; /* 0x0ba0 */ + u32 infra_topaxi_protecten_vdnr_set_1; + u32 infra_topaxi_protecten_vdnr_clr_1; + u32 infra_topaxi_protecten_vdnr_sta0_1; + u32 infra_topaxi_protecten_vdnr_sta1_1; + u32 reserved40[19]; + u32 cldma_ctrl; /* 0x0c00 */ + u32 reserved41[63]; + u32 infrabus_dbg0; /* 0x0d00 */ + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 infrabus_dbg17; + u32 infrabus_dbg18; + u32 infrabus_dbg19; + u32 infrabus_dbg20; + u32 infrabus_dbg21; + u32 infrabus_dbg22; + u32 infrabus_dbg23; + u32 infrabus_dbg24; + u32 infrabus_dbg25; + u32 infrabus_dbg26; + u32 infrabus_dbg27; + u32 infrabus_dbg28; + u32 infrabus_dbg29; + u32 infrabus_dbg30; + u32 infrabus_dbg31; + u32 infrabus_dbg32; + u32 infrabus_dbg33; + u32 infrabus_dbg34; + u32 infrabus_dbg35; + u32 infrabus_dbg36; + u32 infrabus_dbg37; + u32 infrabus_dbg38; + u32 infrabus_dbg39; + u32 infrabus_dbg40; + u32 infrabus_dbg41; + u32 infrabus_dbg42; + u32 infrabus_dbg43; + u32 infrabus_dbg44; + u32 infrabus_dbg45; + u32 reserved42[4]; + u32 infra_topaxi_protecten_mm_2; /* 0x0dc8 */ + u32 infra_topaxi_protecten_mm_set_2; + u32 infra_topaxi_protecten_mm_clr_2; + u32 infra_topaxi_protecten_mm_sta0_2; + u32 infra_topaxi_protecten_mm_sta1_2; + u32 reserved43[5]; + u32 infrabus_dbg_mask2; /* 0x0df0 */ + u32 reserved44[19]; + u32 infra_ao_sec_mm0; /* 0x0e40 */ + u32 infra_ao_sec_mm1; + u32 infra_ao_sec_mm2; + u32 infra_ao_sec_mm3; + u32 infra_ao_sec_mm4; + u32 infra_ao_sec_mm5; + u32 infra_ao_sec_mm6; + u32 infra_ao_sec_mm7; + u32 infra_ao_sec_mm8; + u32 infra_ao_sec_mm9; + u32 infra_ao_sec_mm10; + u32 infra_ao_sec_mm11; + u32 infra_ao_sec_mm12; + u32 infra_ao_sec_mm13; + u32 infra_ao_sec_mm14; + u32 infra_ao_sec_mm15; + u32 infra_ao_sec_mm16; + u32 reserved45[5]; + u32 infra_ao_mm_hang_free; /* 0x0e98 */ + u32 infra_ao_module_hang_free; + u32 reserved46[24]; + u32 infra_misc; /* 0x0f00 */ + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved47[27]; + u32 infra_ao_sec_con; /* 0x0f80 */ + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 reserved48[1]; + u32 infra_ao_sec_cg_con2; /* 0x0f9c */ + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved49[2]; + u32 infra_ao_sec_hyp; /* 0x0fb0 */ + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8192_infracfg_regs, infra_globalcon_dcmctl, 0x0050); +check_member(mt8192_infracfg_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mt8192_infracfg_regs, module_sw_cg_3_set, 0x00c0); +check_member(mt8192_infracfg_regs, module_sw_cg_4_set, 0x00e0); +check_member(mt8192_infracfg_regs, i2c_dbtool_misc, 0x0100); +check_member(mt8192_infracfg_regs, infra_globalcon_rst0_set, 0x0120); +check_member(mt8192_infracfg_regs, infra_topaxi_si0_ctl, 0x0200); +check_member(mt8192_infracfg_regs, md2_bank4_map0, 0x0350); +check_member(mt8192_infracfg_regs, conn_map0, 0x0380); +check_member(mt8192_infracfg_regs, peri_cci_sideband_con, 0x0400); +check_member(mt8192_infracfg_regs, infra_pwm_cksw_ctrl, 0x0410); +check_member(mt8192_infracfg_regs, infra_ao_dbg_con0, 0x0500); +check_member(mt8192_infracfg_regs, mfg_misc_con, 0x0600); +check_member(mt8192_infracfg_regs, infra_rsvd0, 0x0700); +check_member(mt8192_infracfg_regs, infra_globalcon_rst4_set, 0x0730); +check_member(mt8192_infracfg_regs, mcu2emi_m0_parity, 0x0780); +check_member(mt8192_infracfg_regs, md1_sbc_key0, 0x0880); +check_member(mt8192_infracfg_regs, infra_bonding, 0x0900); +check_member(mt8192_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00); +check_member(mt8192_infracfg_regs, infra_mem_26m_cksel, 0x0a60); +check_member(mt8192_infracfg_regs, pll_ulposc_con0, 0x0b00); +check_member(mt8192_infracfg_regs, pll_auxadc_con0, 0x0b10); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr, 0x0b80); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0); +check_member(mt8192_infracfg_regs, cldma_ctrl, 0x0c00); +check_member(mt8192_infracfg_regs, infrabus_dbg0, 0x0d00); +check_member(mt8192_infracfg_regs, infra_topaxi_protecten_mm_2, 0x0dc8); +check_member(mt8192_infracfg_regs, infrabus_dbg_mask2, 0x0df0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mm0, 0x0e40); +check_member(mt8192_infracfg_regs, infra_ao_mm_hang_free, 0x0e98); +check_member(mt8192_infracfg_regs, infra_misc, 0x0f00); +check_member(mt8192_infracfg_regs, infra_ao_sec_con, 0x0f80); +check_member(mt8192_infracfg_regs, infra_ao_sec_hyp, 0x0fb0); +check_member(mt8192_infracfg_regs, infra_ao_sec_mfg_hyp, 0x0fb4); + +static struct mt8192_infracfg_regs *const mt8192_infracfg = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8192_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h new file mode 100644 index 0000000000..1d270ecd41 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h @@ -0,0 +1,1038 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUCFG_H +#define SOC_MEDIATEK_MT8192_MCUCFG_H + +#include +#include + +struct mt8192_mcucfg_regs { + u32 reserved1[2]; + u32 mbista_mcsi_sf1_con; /* 0x0008 */ + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved2[2]; + u32 mbist_trigger_mux_ctl; /* 0x0030 */ + u32 reserved3[3]; + u32 dfd_ctrl; /* 0x0040 */ + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 reserved4[5]; + u32 mp_top_dbg_mon_sel; /* 0x0060 */ + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u32 reserved5[28]; + u32 mp0_ptp_sensor_sel; /* 0x00e0 */ + u32 reserved6[5]; + u32 armpll_jit_clk_out_sel; /* 0x00f8 */ + u32 reserved7[1]; + u32 cci_tra_cfg0; /* 0x0100 */ + u32 reserved8[4]; + u32 cci_tra_cfg5; /* 0x0114 */ + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u32 reserved9[51]; + u32 cci_m0_tra; /* 0x0200 */ + u32 cci_m1_tra; + u32 cci_m2_tra; + u32 reserved10[5]; + u32 cci_s1_tra; /* 0x0220 */ + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u32 reserved11[4]; + u32 cci_m0_tra_latch; /* 0x0240 */ + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u32 reserved12[5]; + u32 cci_s1_tra_latch; /* 0x0260 */ + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u32 reserved13[20]; + u32 cci_m0_if; /* 0x02c0 */ + u32 cci_m1_if; + u32 cci_m2_if; + u32 reserved14[5]; + u32 cci_s1_if; /* 0x02e0 */ + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u32 reserved15[12]; + u32 cci_m0_if_latch; /* 0x0320 */ + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u32 reserved16[5]; + u32 cci_s1_if_latch; /* 0x0340 */ + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u32 reserved17[44]; + u32 l3c_share_status0; /* 0x0400 */ + u32 l3c_share_status1; + u32 l3c_share_status2; + u32 reserved18[1]; + u32 mp0_cpu0_dc_age; /* 0x0410 */ + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u32 reserved19[52]; + u32 mp0_cpu0_nonwfx_ctrl; /* 0x0500 */ + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u32 reserved20[48]; + u32 mp0_ses_apb_trig; /* 0x0600 */ + u32 mp0_ses_clk_en; + u32 reserved21[2]; + u32 wfx_ret_met_dbc_sel; /* 0x0610 */ + u32 reserved22[3]; + u32 adb_bist_cfg1; /* 0x0620 */ + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 adb_bist_done1; + u32 reserved23[1]; + u32 adb_bist_pass1; /* 0x063c */ + u32 reserved24[48]; + u32 axi2acp_cfg_ctrl; /* 0x0700 */ + u32 axi2acp_cfg_mask_id; + u32 reserved25[2]; + u32 axi2acp_ar_def_set; /* 0x0710 */ + u32 reserved26[1]; + u32 axi2acp_aw_def_set; /* 0x0718 */ + u32 reserved27[1]; + u32 axi2acp_err_addr0; /* 0x0720 */ + u32 axi2acp_err_addr1; + u32 axi2acp_err_st; + u32 axi2acp_err_id; + u32 axi2acp_err_irq; + u32 axi2acp_err_dbgout; + u32 reserved28[50]; + u32 mst_ccim0_inject_fault; /* 0x0800 */ + u32 mst_ccim0_rec_par; + u32 mst_ccim0_log_rid; + u32 reserved29[1]; + u32 mst_ccim0_log_rd0; /* 0x0810 */ + u32 mst_ccim0_log_rd1; + u32 mst_ccim0_log_rd2; + u32 mst_ccim0_log_rd3; + u32 mst_ccim1_inject_fault; + u32 mst_ccim1_rec_par; + u32 mst_ccim1_log_rid; + u32 reserved30[1]; + u32 mst_ccim1_log_rd0; /* 0x0830 */ + u32 mst_ccim1_log_rd1; + u32 mst_ccim1_log_rd2; + u32 mst_ccim1_log_rd3; + u32 mst_intaxi_inject_fault; + u32 mst_intaxi_rec_par; + u32 mst_intaxi_log_rid; + u32 reserved31[1]; + u32 mst_intaxi_log_rd0; /* 0x0850 */ + u32 mst_intaxi_log_rd1; + u32 reserved32[2]; + u32 slv_1to2_inject_fault; /* 0x0860 */ + u32 slv_1to2_rec_par; + u32 slv_1to2_log_awid; + u32 slv_1to2_log_arid; + u32 slv_1to2_log_awa0; + u32 slv_1to2_log_awa1; + u32 slv_1to2_log_ara0; + u32 slv_1to2_log_ara1; + u32 slv_1to2_log_wid; + u32 reserved33[3]; + u32 slv_1to2_log_wd0; /* 0x0890 */ + u32 slv_1to2_log_wd1; + u32 slv_1to2_log_wd2; + u32 slv_1to2_log_wd3; + u32 slv_l3c_inject_fault; + u32 slv_l3c_rec_par; + u32 slv_l3c_log_awid; + u32 slv_l3c_log_arid; + u32 slv_l3c_log_awa0; + u32 slv_l3c_log_awa1; + u32 slv_l3c_log_ara0; + u32 slv_l3c_log_ara1; + u32 slv_l3c_log_wid; + u32 reserved34[1]; + u32 slv_l3c_log_wd0; /* 0x08c8 */ + u32 slv_l3c_log_wd1; + u32 slv_gic_inject_fault; + u32 slv_gic_rec_par; + u32 slv_gic_log_awid; + u32 slv_gic_log_arid; + u32 slv_gic_log_awa0; + u32 slv_gic_log_awa1; + u32 slv_gic_log_ara0; + u32 slv_gic_log_ara1; + u32 slv_gic_log_wid; + u32 reserved35[1]; + u32 slv_gic_log_wd0; /* 0x08f8 */ + u32 slv_gic_log_wd1; + u32 reserved36[64]; + u32 ildo_vin_big0; /* 0x0a00 */ + u32 ildo_out_big0; + u32 ildo_ovstck_big0; + u32 ildo_vo2hck_big0; + u32 ildo_mhstck_big0; + u32 ildo_mlstck_big0; + u32 ilod_uvwin_big0; + u32 ilod_ovwin_big0; + u32 ildo_pd_cfg_big0; + u32 reserved37[3]; + u32 ildo_vin_big1; /* 0x0a30 */ + u32 ildo_out_big1; + u32 ildo_ovstck_big1; + u32 ildo_vo2hck_big1; + u32 ildo_mhstck_big1; + u32 ildo_mlstck_big1; + u32 ilod_uvwin_big1; + u32 ilod_ovwin_big1; + u32 ildo_pd_cfg_big1; + u32 reserved38[3]; + u32 ildo_vin_big2; /* 0x0a60 */ + u32 ildo_out_big2; + u32 ildo_ovstck_big2; + u32 ildo_vo2hck_big2; + u32 ildo_mhstck_big2; + u32 ildo_mlstck_big2; + u32 ilod_uvwin_big2; + u32 ilod_ovwin_big2; + u32 ildo_pd_cfg_big2; + u32 reserved39[3]; + u32 ildo_vin_big3; /* 0x0a90 */ + u32 ildo_out_big3; + u32 ildo_ovstck_big3; + u32 ildo_vo2hck_big3; + u32 ildo_mhstck_big3; + u32 ildo_mlstck_big3; + u32 ilod_uvwin_big3; + u32 ilod_ovwin_big3; + u32 ildo_pd_cfg_big3; + u32 reserved40[1495]; + u32 l3c_share_cfg0; /* 0x2210 */ + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u32 reserved41[1]; + u32 udi_cfg0; /* 0x2220 */ + u32 udi_cfg1; + u32 reserved42[2]; + u32 mcusys_core_status; /* 0x2230 */ + u32 reserved43[1]; + u32 cfg_sys_valid; /* 0x2238 */ + u32 cfg_sysbase_addr_0; + u32 cfg_sysbase_addr_1; + u32 cfg_sysbase_addr_2; + u32 cfg_sysbase_addr_3; + u32 cfg_sysbase_addr_4; + u32 reserved44[4]; + u32 mcusys_base; /* 0x2260 */ + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 ext_l3c_sram_base; + u32 ext_gic_periph_base; + u32 mcusys_qos_shaper_degree; + u32 mcusys_qos_shaper_others; + u32 mcusys_qos_age_set_enable; + u32 sspm_cpueb_turbo_pll_ctl; + u32 cpu_eb_apb_base; + u32 cpu_eb_tcm_btb_delsel; + u32 cpu_eb_mem_misc; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u32 cpu_plldiv_cfg2; + u32 cpu_plldiv_cfg3; + u32 cpu_plldiv_cfg4; + u32 reserved45[11]; + u32 bus_plldiv_cfg; /* 0x22e0 */ + u32 reserved46[3]; + u32 plldiv_ctl0; /* 0x22f0 */ + u32 reserved47[3]; + u32 mcsi_ram_delsel0; /* 0x2300 */ + u32 mcsi_ram_delsel1; + u32 reserved48[30]; + u32 etb_cfg0; /* 0x2380 */ + u32 reserved49[3]; + u32 bus_parity_gen_en; /* 0x2390 */ + u32 bus_parity_clr; + u32 bus_parity_chk_en; + u32 bus_parity_fail; + u32 dsu2biu_addr_remap_cfg; + u32 dsu2biu_addr_remap_sta; + u32 reserved50[2]; + u32 dsu2biu_addr_remap_0_cfg0; /* 0x23b0 */ + u32 dsu2biu_addr_remap_0_cfg1; + u32 dsu2biu_addr_remap_0_cfg2; + u32 reserved51[1]; + u32 dsu2biu_addr_remap_1_cfg0; /* 0x23c0 */ + u32 dsu2biu_addr_remap_1_cfg1; + u32 dsu2biu_addr_remap_1_cfg2; + u32 reserved52[1]; + u32 dsu2biu_addr_remap_magic; /* 0x23d0 */ + u32 reserved53[11]; + u32 cci_rgu; /* 0x2400 */ + u32 reserved54[3]; + u32 mcsi_cfg0; /* 0x2410 */ + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u32 reserved55[7]; + u32 mcsic_dcm0; /* 0x2440 */ + u32 mcsic_dcm1; + u32 reserved56[18]; + u32 apmcu2emi_early_cke_ctl01; /* 0x2490 */ + u32 reserved57[1]; + u32 apmcu2emi_early_ebg_ctl0; /* 0x2498 */ + u32 apmcu2emi_early_ebg_ctl1; + u32 apmcu2emi_early_ebg_ctl2; + u32 apmcu2emi_early_ebg_ctl3; + u32 apmcu2emi_early_ebg_ctl4; + u32 apmcu2emi_early_ebg_ctl5; + u32 reserved58[20]; + u32 mp_adb_dcm_cfg0; /* 0x2500 */ + u32 reserved59[1]; + u32 mp_adb_dcm_cfg2; /* 0x2508 */ + u32 reserved60[1]; + u32 mp_adb_dcm_cfg4; /* 0x2510 */ + u32 reserved61[1]; + u32 mp_misc_dcm_cfg0; /* 0x2518 */ + u32 reserved62[9]; + u32 etb_ck_ctl; /* 0x2540 */ + u32 reserved63[15]; + u32 dcc_cpu_con0; /* 0x2580 */ + u32 dcc_cpu_con1; + u32 reserved64[6]; + u32 dcc_bus_con0; /* 0x25a0 */ + u32 reserved65[7]; + u32 mcusys_dcm_cfg0; /* 0x25c0 */ + u32 reserved66[79]; + u32 fcm_spmc_sw_cfg1; /* 0x2700 */ + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u32 reserved67[9]; + u32 mcusys_spmc_sw_cfg; /* 0x2740 */ + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u32 reserved68[45]; + u32 cpc_pllbuck_req_ctrl; /* 0x2800 */ + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u32 reserved69[1]; + u32 cpc_mcusys_last_core_resp; /* 0x2824 */ + u32 cpc_pwr_on_mask; + u32 reserved70[5]; + u32 cpc_spmc_pwr_status; /* 0x2840 */ + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u32 reserved71[1]; + u32 cpc_gp0_gp1_status; /* 0x2854 */ + u32 reserved72[1]; + u32 cpc_turbo_ctrl; /* 0x285c */ + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u32 reserved73[1]; + u32 cpc_turbo_gp0_resp; /* 0x2880 */ + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u32 reserved74[20]; + u32 emi_wfifo; /* 0x2900 */ + u32 axi1to4_cfg; + u32 apb_cfg; + u32 emi_adb_edge_sel; + u32 reserved75[4]; + u32 sclk_cfg_slow_down_ck; /* 0x2920 */ + u32 reserved76[3]; + u32 acpwakeup; /* 0x2930 */ + u32 reserved77[1]; + u32 l3gic_idle_bypass; /* 0x2938 */ + u32 reserved78[21]; + u32 mcusys_dbg_mon_sel; /* 0x2990 */ + u32 mcusys_dbg_mon; + u32 reserved79[58]; + u32 gic_acao_ctl0; /* 0x2a80 */ + u32 reserved80[1]; + u32 gic_acao_ctl2; /* 0x2a88 */ + u32 reserved81[29]; + u32 spmc_dbg_setting; /* 0x2b00 */ + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u32 reserved82[2]; + u32 trace_data_entry0_l; /* 0x2b20 */ + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u32 reserved83[1]; + u32 cluster_off_dormant_counter; /* 0x2b70 */ + u32 cluster_off_dormant_counter_clear; + u32 turbo_gp0_gp1_latency; + u32 turbo_gp2_latency; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u32 reserved84[4]; + u32 cpc_wdt_latch_info6; /* 0x2bb0 */ + u32 cpc_wdt_latch_info7; + u32 cpc_ptm_event_en_ctrl; + u32 cpc_ptm_event_en_ctrl1; + u32 cpc_ptm_trace_sel; + u32 cpc_ptm_trace_status_l; + u32 cpc_ptm_trace_status_h; + u32 reserved85[29]; + u32 sesv6_bg_ctrl; /* 0x2c40 */ + u32 reserved86[3]; + u32 dsu_sesv6_ao_reg0; /* 0x2c50 */ + u32 dsu_sesv6_ao_reg1; + u32 dsu_sesv6_ao_reg2; + u32 dsu_sesv6_ao_reg3; + u32 dsu_sesv6_ao_reg4; + u32 reserved87[39]; + u32 ildo_dout_sel; /* 0x2d00 */ + u32 reserved88[31]; + u32 dreq20_little_en; /* 0x2d80 */ + u32 reserved89[2]; + u32 dreq20_big_vproc_iso; /* 0x2d8c */ + u32 reserved90[28]; + u32 pikachu_event; /* 0x2e00 */ + u32 pikachu_status; + u32 reserved91[126]; + u32 cpu0_drcc_ao_config; /* 0x3000 */ + u32 reserved92[3]; + u32 cpu0_sesv6_ao_reg0; /* 0x3010 */ + u32 cpu0_sesv6_ao_reg1; + u32 cpu0_sesv6_ao_reg2; + u32 cpu0_sesv6_ao_reg3; + u32 cpu0_sesv6_ao_reg4; + u32 reserved93[7]; + u32 cpu0_dfs_cfg; /* 0x3040 */ + u32 reserved94[3]; + u32 cpu0_turbo_cfg; /* 0x3050 */ + u32 reserved95[105]; + u32 cpu0_resereved_reg; /* 0x31f8 */ + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u32 reserved96[3]; + u32 cpu1_sesv6_ao_reg0; /* 0x3210 */ + u32 cpu1_sesv6_ao_reg1; + u32 cpu1_sesv6_ao_reg2; + u32 cpu1_sesv6_ao_reg3; + u32 cpu1_sesv6_ao_reg4; + u32 reserved97[7]; + u32 cpu1_dfs_cfg; /* 0x3240 */ + u32 reserved98[3]; + u32 cpu1_turbo_cfg; /* 0x3250 */ + u32 reserved99[105]; + u32 cpu1_resereved_reg; /* 0x33f8 */ + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u32 reserved100[3]; + u32 cpu2_sesv6_ao_reg0; /* 0x3410 */ + u32 cpu2_sesv6_ao_reg1; + u32 cpu2_sesv6_ao_reg2; + u32 cpu2_sesv6_ao_reg3; + u32 cpu2_sesv6_ao_reg4; + u32 reserved101[7]; + u32 cpu2_dfs_cfg; /* 0x3440 */ + u32 reserved102[3]; + u32 cpu2_turbo_cfg; /* 0x3450 */ + u32 reserved103[105]; + u32 cpu2_resereved_reg; /* 0x35f8 */ + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u32 reserved104[3]; + u32 cpu3_sesv6_ao_reg0; /* 0x3610 */ + u32 cpu3_sesv6_ao_reg1; + u32 cpu3_sesv6_ao_reg2; + u32 cpu3_sesv6_ao_reg3; + u32 cpu3_sesv6_ao_reg4; + u32 reserved105[7]; + u32 cpu3_dfs_cfg; /* 0x3640 */ + u32 reserved106[3]; + u32 cpu3_turbo_cfg; /* 0x3650 */ + u32 reserved107[105]; + u32 cpu3_resereved_reg; /* 0x37f8 */ + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u32 reserved108[3]; + u32 cpu4_sesv6_ao_reg0; /* 0x3810 */ + u32 cpu4_sesv6_ao_reg1; + u32 cpu4_sesv6_ao_reg2; + u32 cpu4_sesv6_ao_reg3; + u32 cpu4_sesv6_ao_reg4; + u32 reserved109[3]; + u32 cpu4_didt_reg; /* 0x3830 */ + u32 cpu4_mem_lre_reg; + u32 reserved110[2]; + u32 cpu4_dfs_cfg; /* 0x3840 */ + u32 reserved111[3]; + u32 cpu4_turbo_cfg; /* 0x3850 */ + u32 reserved112[105]; + u32 cpu4_resereved_reg; /* 0x39f8 */ + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u32 reserved113[3]; + u32 cpu5_sesv6_ao_reg0; /* 0x3a10 */ + u32 cpu5_sesv6_ao_reg1; + u32 cpu5_sesv6_ao_reg2; + u32 cpu5_sesv6_ao_reg3; + u32 cpu5_sesv6_ao_reg4; + u32 reserved114[3]; + u32 cpu5_didt_reg; /* 0x3a30 */ + u32 cpu5_mem_lre_reg; + u32 reserved115[2]; + u32 cpu5_dfs_cfg; /* 0x3a40 */ + u32 reserved116[3]; + u32 cpu5_turbo_cfg; /* 0x3a50 */ + u32 reserved117[105]; + u32 cpu5_resereved_reg; /* 0x3bf8 */ + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u32 reserved118[3]; + u32 cpu6_sesv6_ao_reg0; /* 0x3c10 */ + u32 cpu6_sesv6_ao_reg1; + u32 cpu6_sesv6_ao_reg2; + u32 cpu6_sesv6_ao_reg3; + u32 cpu6_sesv6_ao_reg4; + u32 reserved119[3]; + u32 cpu6_didt_reg; /* 0x3c30 */ + u32 cpu6_mem_lre_reg; + u32 reserved120[2]; + u32 cpu6_dfs_cfg; /* 0x3c40 */ + u32 reserved121[3]; + u32 cpu6_turbo_cfg; /* 0x3c50 */ + u32 reserved122[105]; + u32 cpu6_resereved_reg; /* 0x3df8 */ + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u32 reserved123[3]; + u32 cpu7_sesv6_ao_reg0; /* 0x3e10 */ + u32 cpu7_sesv6_ao_reg1; + u32 cpu7_sesv6_ao_reg2; + u32 cpu7_sesv6_ao_reg3; + u32 cpu7_sesv6_ao_reg4; + u32 reserved124[3]; + u32 cpu7_didt_reg; /* 0x3e30 */ + u32 cpu7_mem_lre_reg; + u32 reserved125[2]; + u32 cpu7_dfs_cfg; /* 0x3e40 */ + u32 reserved126[3]; + u32 cpu7_turbo_cfg; /* 0x3e50 */ + u32 reserved127[105]; + u32 cpu7_resereved_reg; /* 0x3ff8 */ + u32 cpu7_resereved_reg_rd; + u32 reserved128[512]; + u32 mp0_mbist_cfg; /* 0x4800 */ + u32 reserved129[15]; + u32 mp0_l3_data_ram_delsel; /* 0x4840 */ + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u32 reserved130[12]; + u32 mp0_dcm_cfg0; /* 0x4880 */ + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u32 reserved131[7]; + u32 mp0_l3_cache_parity1; /* 0x48c0 */ + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u32 reserved132[1]; + u32 mp0_cluster_cfg0; /* 0x48d0 */ + u32 reserved133[3]; + u32 mp0_cluster_cfg4; /* 0x48e0 */ + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u32 reserved134[4]; + u32 mp0_cluster_cfg8; /* 0x4900 */ + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 mp0_mem_dreq_cfg; + u32 mp0_victim_rd_mask; + u32 reserved135[174]; + u32 cpu_type0_spmc0_cfg; /* 0x4c00 */ + u32 reserved136[7]; + u32 cpu_type0_ram_delsel0_cfg; /* 0x4c20 */ + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 reserved137[53]; + u32 cpu_type1_spmc0_cfg; /* 0x4d00 */ + u32 reserved138[3]; + u32 cpu_type1_mpmmen; /* 0x4d10 */ + u32 reserved139[3]; + u32 cpu_type1_ram_delsel0_cfg; /* 0x4d20 */ + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 reserved140[5]; + u32 cpu_type1_drss_cfg0; /* 0x4d40 */ + u32 cpu_type1_drss_cfg1; + u32 reserved141[302]; + u32 mcusys_pwr_con; /* 0x5200 */ + u32 mp0_cputop_pwr_con; + u32 mp0_cpu0_pwr_con; + u32 mp0_cpu1_pwr_con; + u32 mp0_cpu2_pwr_con; + u32 mp0_cpu3_pwr_con; + u32 mp0_cpu4_pwr_con; + u32 mp0_cpu5_pwr_con; + u32 mp0_cpu6_pwr_con; + u32 mp0_cpu7_pwr_con; + u32 reserved142[246]; + u32 sec_pol_ctl_en0; /* 0x5600 */ + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 reserved143[7]; + u32 int_pol_ctl0; /* 0x5668 */ + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 reserved144[7]; + u32 int_msk_ctl0; /* 0x56d0 */ + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 reserved145[10]; + u32 int_msk_ctl_all; /* 0x5744 */ + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u32 reserved146[572]; + u32 dfd_internal_ctl; /* 0x6040 */ + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_finish_wait_time; + u32 dfd_internal_chain_group; + u32 dfd_internal_chain_inv_info_ll; + u32 dfd_internal_chain_inv_info_lh; + u32 dfd_internal_chain_inv_info_hl; + u32 dfd_internal_chain_inv_info_hh; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 dfd_v35_enable; + u32 dfd_v35_tap_number; + u32 dfd_v35_tap_en; + u32 dfd_v35_ctl; + u32 dfd_v35_tap_seq0; + u32 dfd_v35_tap_seq1; + u32 dfd_v35_seq0_0; + u32 dfd_v35_seq0_1; + u32 dfd_v35_seq1_0; + u32 dfd_v35_seq1_1; + u32 dfd_v35_seq2_0; + u32 dfd_v35_seq2_1; + u32 reserved147[6]; + u32 dfd_soc_clock_stop_mask; /* 0x60f0 */ + u32 reserved148[2]; + u32 dfd_hw_trigger_mask; /* 0x60fc */ + u32 dfd_v50_enable; + u32 dfd_v50_self_trigger_iteration; + u32 dfd_v50_start_trigger; + u32 dfd_v50_cpuck_halt; + u32 dfd_v50_26m_resume; + u32 dfd_v50_26m_halt_release; + u32 dfd_v50_system_halt_time; + u32 dfd_v50_group_0_1_diff; + u32 dfd_v50_group_0_2_diff; + u32 dfd_v50_group_0_3_diff; + u32 dfd_v50_group_0_4_diff; + u32 dfd_v50_group_0_5_diff; + u32 dfd_v50_group_0_6_diff; + u32 dfd_v50_group_0_7_diff; + u32 dfd_v50_group_0_8_diff; + u32 dfd_v50_group_0_9_diff; + u32 dfd_v50_group_0_10_diff; + u32 dfd_v50_group_0_11_diff; + u32 dfd_v50_group_0_12_diff; + u32 dfd_v50_group_0_13_diff; + u32 dfd_v50_group_0_14_diff; + u32 dfd_v50_group_0_15_diff; + u32 dfd_v50_group_0_16_diff; + u32 dfd_v50_group_0_17_diff; + u32 dfd_v50_group_0_18_diff; + u32 dfd_v50_group_0_19_diff; + u32 dfd_v50_group_0_20_diff; + u32 dfd_v50_group_0_21_diff; + u32 dfd_v50_group_0_22_diff; + u32 dfd_v50_group_0_23_diff; + u32 dfd_v50_group_0_24_diff; + u32 dfd_v50_group_0_25_diff; + u32 dfd_v50_group_0_26_diff; + u32 dfd_v50_group_0_27_diff; + u32 dfd_v50_group_0_28_diff; + u32 dfd_v50_group_0_29_diff; + u32 dfd_v50_group_0_30_diff; + u32 dfd_v50_group_0_31_diff; + u32 dfd_v50_chain_group_3_0_info; + u32 dfd_v50_chain_group_7_4_info; + u32 dfd_v50_chain_group_11_8_info; + u32 dfd_v50_chain_group_15_12_info; + u32 dfd_v50_chain_group_19_16_info; + u32 dfd_v50_chain_group_23_20_info; + u32 dfd_v50_chain_group_27_24_info; + u32 dfd_v50_chain_group_31_28_info; + u32 dfd_v50_chain_group_35_32_info; + u32 dfd_v50_chain_group_39_36_info; + u32 dfd_v50_chain_group_43_40_info; + u32 dfd_v50_chain_group_47_44_info; + u32 dfd_v50_chain_group_51_48_info; + u32 dfd_v50_chain_group_55_52_info; + u32 dfd_v50_chain_group_59_56_info; + u32 dfd_v50_chain_group_63_60_info; + u32 dfd_v50_chain_group_67_64_info; + u32 dfd_v50_chain_group_71_68_info; + u32 dfd_v50_chain_group_75_72_info; + u32 dfd_v50_chain_group_79_76_info; + u32 dfd_v50_chain_group_83_80_info; + u32 dfd_v50_chain_group_87_84_info; + u32 dfd_v50_chain_group_91_88_info; + u32 dfd_v50_chain_group_95_92_info; + u32 dfd_v50_chain_group_99_96_info; + u32 dfd_v50_chain_group_103_100_info; + u32 dfd_v50_chain_group_107_104_info; + u32 dfd_v50_chain_group_111_108_info; + u32 dfd_v50_chain_group_115_112_info; + u32 dfd_v50_chain_group_119_116_info; + u32 dfd_v50_chain_group_123_120_info; + u32 dfd_v50_chain_group_127_124_info; + u32 dfd_test_si_2; + u32 dfd_test_si_3; + u32 dfd_test_so; + u32 dfd_bus_halt_time; + u32 dfd_read_addr; + u32 dfd_v50_clk_stop_time; + u32 dfd_v50_group_0_32_diff; + u32 dfd_v50_group_0_33_diff; + u32 dfd_v50_group_0_34_diff; + u32 dfd_v50_group_0_35_diff; + u32 dfd_v50_group_0_36_diff; + u32 dfd_v50_group_0_37_diff; + u32 dfd_v50_group_0_38_diff; + u32 dfd_v50_group_0_39_diff; + u32 dfd_v50_group_0_40_diff; + u32 dfd_v50_group_0_41_diff; + u32 dfd_v50_group_0_42_diff; + u32 dfd_v50_group_0_43_diff; + u32 dfd_v50_group_0_44_diff; + u32 dfd_v50_group_0_45_diff; + u32 dfd_v50_group_0_46_diff; + u32 dfd_v50_group_0_47_diff; + u32 dfd_v50_group_0_48_diff; + u32 dfd_v50_group_0_49_diff; + u32 dfd_v50_group_0_50_diff; + u32 dfd_v50_group_0_51_diff; + u32 dfd_v50_group_0_52_diff; + u32 dfd_v50_group_0_53_diff; + u32 dfd_v50_group_0_54_diff; + u32 dfd_v50_group_0_55_diff; + u32 dfd_v50_group_0_56_diff; + u32 dfd_v50_group_0_57_diff; + u32 dfd_v50_group_0_58_diff; + u32 dfd_v50_group_0_59_diff; + u32 dfd_v50_group_0_60_diff; + u32 dfd_v50_group_0_61_diff; + u32 dfd_v50_group_0_62_diff; + u32 dfd_v50_group_0_63_diff; + u32 reserved149[20]; + u32 dfd_v50_spare; /* 0x6300 */ + u32 reserved150[1843]; + u32 mcusys_reserved_reg4; /* 0x7fd0 */ + u32 mcusys_reserved_reg4_rd; + u32 reserved151[2]; + u32 mcusys_reserved_reg0; /* 0x7fe0 */ + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8192_mcucfg_regs, mbista_mcsi_sf1_con, 0x0008); +check_member(mt8192_mcucfg_regs, mbist_trigger_mux_ctl, 0x0030); +check_member(mt8192_mcucfg_regs, dfd_ctrl, 0x0040); +check_member(mt8192_mcucfg_regs, mp_top_dbg_mon_sel, 0x0060); +check_member(mt8192_mcucfg_regs, mp0_ptp_sensor_sel, 0x00e0); +check_member(mt8192_mcucfg_regs, armpll_jit_clk_out_sel, 0x00f8); +check_member(mt8192_mcucfg_regs, cci_tra_cfg5, 0x0114); +check_member(mt8192_mcucfg_regs, cci_m0_tra, 0x0200); +check_member(mt8192_mcucfg_regs, cci_s1_tra, 0x0220); +check_member(mt8192_mcucfg_regs, cci_m0_tra_latch, 0x0240); +check_member(mt8192_mcucfg_regs, cci_s1_tra_latch, 0x0260); +check_member(mt8192_mcucfg_regs, cci_m0_if, 0x02c0); +check_member(mt8192_mcucfg_regs, cci_s1_if, 0x02e0); +check_member(mt8192_mcucfg_regs, cci_m0_if_latch, 0x0320); +check_member(mt8192_mcucfg_regs, cci_s1_if_latch, 0x0340); +check_member(mt8192_mcucfg_regs, l3c_share_status0, 0x0400); +check_member(mt8192_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x0500); +check_member(mt8192_mcucfg_regs, mp0_ses_apb_trig, 0x0600); +check_member(mt8192_mcucfg_regs, wfx_ret_met_dbc_sel, 0x0610); +check_member(mt8192_mcucfg_regs, adb_bist_cfg1, 0x0620); +check_member(mt8192_mcucfg_regs, axi2acp_cfg_ctrl, 0x0700); +check_member(mt8192_mcucfg_regs, axi2acp_ar_def_set, 0x0710); +check_member(mt8192_mcucfg_regs, mst_ccim0_inject_fault, 0x0800); +check_member(mt8192_mcucfg_regs, slv_1to2_inject_fault, 0x0860); +check_member(mt8192_mcucfg_regs, slv_1to2_log_wd0, 0x0890); +check_member(mt8192_mcucfg_regs, ildo_vin_big0, 0x0a00); +check_member(mt8192_mcucfg_regs, ildo_vin_big1, 0x0a30); +check_member(mt8192_mcucfg_regs, ildo_vin_big2, 0x0a60); +check_member(mt8192_mcucfg_regs, ildo_vin_big3, 0x0a90); +check_member(mt8192_mcucfg_regs, l3c_share_cfg0, 0x2210); +check_member(mt8192_mcucfg_regs, mcusys_core_status, 0x2230); +check_member(mt8192_mcucfg_regs, mcusys_base, 0x2260); +check_member(mt8192_mcucfg_regs, bus_plldiv_cfg, 0x22e0); +check_member(mt8192_mcucfg_regs, plldiv_ctl0, 0x22f0); +check_member(mt8192_mcucfg_regs, mcsi_ram_delsel0, 0x2300); +check_member(mt8192_mcucfg_regs, etb_cfg0, 0x2380); +check_member(mt8192_mcucfg_regs, bus_parity_gen_en, 0x2390); +check_member(mt8192_mcucfg_regs, dsu2biu_addr_remap_0_cfg0, 0x23b0); +check_member(mt8192_mcucfg_regs, cci_rgu, 0x2400); +check_member(mt8192_mcucfg_regs, mcsi_cfg0, 0x2410); +check_member(mt8192_mcucfg_regs, mcsic_dcm0, 0x2440); +check_member(mt8192_mcucfg_regs, apmcu2emi_early_cke_ctl01, 0x2490); +check_member(mt8192_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500); +check_member(mt8192_mcucfg_regs, etb_ck_ctl, 0x2540); +check_member(mt8192_mcucfg_regs, dcc_cpu_con0, 0x2580); +check_member(mt8192_mcucfg_regs, dcc_bus_con0, 0x25a0); +check_member(mt8192_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0); +check_member(mt8192_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700); +check_member(mt8192_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740); +check_member(mt8192_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800); +check_member(mt8192_mcucfg_regs, cpc_spmc_pwr_status, 0x2840); +check_member(mt8192_mcucfg_regs, emi_wfifo, 0x2900); +check_member(mt8192_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920); +check_member(mt8192_mcucfg_regs, acpwakeup, 0x2930); +check_member(mt8192_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990); +check_member(mt8192_mcucfg_regs, gic_acao_ctl0, 0x2a80); +check_member(mt8192_mcucfg_regs, spmc_dbg_setting, 0x2b00); +check_member(mt8192_mcucfg_regs, trace_data_entry0_l, 0x2b20); +check_member(mt8192_mcucfg_regs, cpc_wdt_latch_info6, 0x2bb0); +check_member(mt8192_mcucfg_regs, sesv6_bg_ctrl, 0x2c40); +check_member(mt8192_mcucfg_regs, dsu_sesv6_ao_reg0, 0x2c50); +check_member(mt8192_mcucfg_regs, ildo_dout_sel, 0x2d00); +check_member(mt8192_mcucfg_regs, dreq20_little_en, 0x2d80); +check_member(mt8192_mcucfg_regs, dreq20_big_vproc_iso, 0x2d8c); +check_member(mt8192_mcucfg_regs, pikachu_event, 0x2e00); +check_member(mt8192_mcucfg_regs, cpu0_drcc_ao_config, 0x3000); +check_member(mt8192_mcucfg_regs, cpu0_sesv6_ao_reg0, 0x3010); +check_member(mt8192_mcucfg_regs, cpu0_dfs_cfg, 0x3040); +check_member(mt8192_mcucfg_regs, cpu0_turbo_cfg, 0x3050); +check_member(mt8192_mcucfg_regs, cpu0_resereved_reg, 0x31f8); +check_member(mt8192_mcucfg_regs, cpu1_sesv6_ao_reg0, 0x3210); +check_member(mt8192_mcucfg_regs, cpu1_dfs_cfg, 0x3240); +check_member(mt8192_mcucfg_regs, cpu1_turbo_cfg, 0x3250); +check_member(mt8192_mcucfg_regs, cpu1_resereved_reg, 0x33f8); +check_member(mt8192_mcucfg_regs, cpu2_sesv6_ao_reg0, 0x3410); +check_member(mt8192_mcucfg_regs, cpu2_dfs_cfg, 0x3440); +check_member(mt8192_mcucfg_regs, cpu2_turbo_cfg, 0x3450); +check_member(mt8192_mcucfg_regs, cpu2_resereved_reg, 0x35f8); +check_member(mt8192_mcucfg_regs, cpu3_sesv6_ao_reg0, 0x3610); +check_member(mt8192_mcucfg_regs, cpu3_dfs_cfg, 0x3640); +check_member(mt8192_mcucfg_regs, cpu3_turbo_cfg, 0x3650); +check_member(mt8192_mcucfg_regs, cpu3_resereved_reg, 0x37f8); +check_member(mt8192_mcucfg_regs, cpu4_sesv6_ao_reg0, 0x3810); +check_member(mt8192_mcucfg_regs, cpu4_didt_reg, 0x3830); +check_member(mt8192_mcucfg_regs, cpu4_dfs_cfg, 0x3840); +check_member(mt8192_mcucfg_regs, cpu4_turbo_cfg, 0x3850); +check_member(mt8192_mcucfg_regs, cpu4_resereved_reg, 0x39f8); +check_member(mt8192_mcucfg_regs, cpu5_sesv6_ao_reg0, 0x3a10); +check_member(mt8192_mcucfg_regs, cpu5_didt_reg, 0x3a30); +check_member(mt8192_mcucfg_regs, cpu5_dfs_cfg, 0x3a40); +check_member(mt8192_mcucfg_regs, cpu5_turbo_cfg, 0x3a50); +check_member(mt8192_mcucfg_regs, cpu5_resereved_reg, 0x3bf8); +check_member(mt8192_mcucfg_regs, cpu6_sesv6_ao_reg0, 0x3c10); +check_member(mt8192_mcucfg_regs, cpu6_didt_reg, 0x3c30); +check_member(mt8192_mcucfg_regs, cpu6_dfs_cfg, 0x3c40); +check_member(mt8192_mcucfg_regs, cpu6_turbo_cfg, 0x3c50); +check_member(mt8192_mcucfg_regs, cpu6_resereved_reg, 0x3df8); +check_member(mt8192_mcucfg_regs, cpu7_sesv6_ao_reg0, 0x3e10); +check_member(mt8192_mcucfg_regs, cpu7_didt_reg, 0x3e30); +check_member(mt8192_mcucfg_regs, cpu7_dfs_cfg, 0x3e40); +check_member(mt8192_mcucfg_regs, cpu7_turbo_cfg, 0x3e50); +check_member(mt8192_mcucfg_regs, cpu7_resereved_reg, 0x3ff8); +check_member(mt8192_mcucfg_regs, mp0_mbist_cfg, 0x4800); +check_member(mt8192_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840); +check_member(mt8192_mcucfg_regs, mp0_dcm_cfg0, 0x4880); +check_member(mt8192_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg4, 0x48e0); +check_member(mt8192_mcucfg_regs, mp0_cluster_cfg8, 0x4900); +check_member(mt8192_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00); +check_member(mt8192_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20); +check_member(mt8192_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00); +check_member(mt8192_mcucfg_regs, cpu_type1_mpmmen, 0x4d10); +check_member(mt8192_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20); +check_member(mt8192_mcucfg_regs, cpu_type1_drss_cfg0, 0x4d40); +check_member(mt8192_mcucfg_regs, mcusys_pwr_con, 0x5200); +check_member(mt8192_mcucfg_regs, sec_pol_ctl_en0, 0x5600); +check_member(mt8192_mcucfg_regs, int_pol_ctl0, 0x5668); +check_member(mt8192_mcucfg_regs, int_msk_ctl0, 0x56d0); +check_member(mt8192_mcucfg_regs, int_msk_ctl_all, 0x5744); +check_member(mt8192_mcucfg_regs, dfd_internal_ctl, 0x6040); +check_member(mt8192_mcucfg_regs, dfd_soc_clock_stop_mask, 0x60f0); +check_member(mt8192_mcucfg_regs, dfd_hw_trigger_mask, 0x60fc); +check_member(mt8192_mcucfg_regs, dfd_v50_spare, 0x6300); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg4, 0x7fd0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); +check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); + +static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld new file mode 100644 index 0000000000..df9d376f27 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 4) + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TPM_TCPA_LOG(0x00103000, 2K) + FMAP_CACHE(0x00103800, 2K) + WATCHDOG_TOMBSTONE(0x00104000, 4) + PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) + TIMESTAMP(0x00113c00, 1K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) + SRAM_END(0x00120000) + + SRAM_L2C_START(0x00200000) + BOOTBLOCK(0x00201000, 64K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 188K) + DRAM_INIT_CODE(0x00240000, 208K) + PRERAM_CBFS_CACHE(0x00274000, 48K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40000000, 2M) + RAMSTAGE(0x40200000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h new file mode 100644 index 0000000000..d5a9cf9a3e --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_PLL_H +#define SOC_MEDIATEK_MT8192_PLL_H + +#include +#include +#include + +struct mtk_topckgen_regs { + u32 clk_mode; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 clk_cfg_update2; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved1[1]; + u32 clk_cfg_1; /* 0x0020 */ + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved2[1]; + u32 clk_cfg_2; /* 0x0030 */ + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved3[1]; + u32 clk_cfg_3; /* 0x0040 */ + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved4[1]; + u32 clk_cfg_4; /* 0x0050 */ + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved5[1]; + u32 clk_cfg_5; /* 0x0060 */ + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved6[1]; + u32 clk_cfg_6; /* 0x0070 */ + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved7[1]; + u32 clk_cfg_7; /* 0x0080 */ + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved8[1]; + u32 clk_cfg_8; /* 0x0090 */ + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 reserved9[1]; + u32 clk_cfg_9; /* 0x00a0 */ + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 reserved10[1]; + u32 clk_cfg_10; /* 0x00b0 */ + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 reserved11[1]; + u32 clk_cfg_11; /* 0x00c0 */ + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 reserved12[1]; + u32 clk_cfg_12; /* 0x00d0 */ + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved13[1]; + u32 clk_cfg_13; /* 0x00e0 */ + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved14[1]; + u32 clk_cfg_14; /* 0x00f0 */ + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 reserved15[1]; + u32 clk_cfg_15; /* 0x0100 */ + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 reserved16[1]; + u32 clk_cfg_16; /* 0x0110 */ + u32 clk_cfg_16_set; + u32 clk_cfg_16_clr; + u32 reserved17[9]; + u32 clk_misc_cfg_0; /* 0x0140 */ + u32 reserved18[3]; + u32 clk_misc_cfg_1; /* 0x0150 */ + u32 reserved19[10]; + u32 clk_dbg_cfg; /* 0x017c */ + u32 reserved20[32]; + u32 clk_scp_cfg_0; /* 0x0200 */ + u32 reserved21[3]; + u32 clk_scp_cfg_1; /* 0x0210 */ + u32 reserved22[3]; + u32 clk26cali_0; /* 0x0220 */ + u32 clk26cali_1; + u32 reserved23[2]; + u32 cksta_reg; /* 0x0230 */ + u32 cksta_reg1; + u32 cksta_reg2; + u32 reserved24[49]; + u32 clkmon_clk_sel_reg; /* 0x0300 */ + u32 clkmon_k1_reg; + u32 reserved25[6]; + u32 clk_auddiv_0; /* 0x0320 */ + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 aud_top_cfg; + u32 aud_top_mon; + u32 clk_auddiv_3; + u32 clk_auddiv_4; + u32 reserved26[113]; + u32 clk_extck_reg; /* 0x0500 */ +}; + +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0150); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017c); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200); +check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x0210); +check_member(mtk_topckgen_regs, clk26cali_0, 0x0220); +check_member(mtk_topckgen_regs, cksta_reg, 0x0230); +check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x0300); +check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x0500); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 reserved0[2]; + u32 pllon_con0; + u32 pllon_con1; + u32 pllon_con2; + u32 pllon_con3; + u32 reserved1[104]; + u32 ap_pllgp1_con0; /* 0x0200 */ + u32 ap_pllgp1_con1; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl0_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 armpll_bl1_con0; + u32 armpll_bl1_con1; + u32 armpll_bl1_con2; + u32 armpll_bl1_con3; + u32 armpll_bl2_con0; + u32 armpll_bl2_con1; + u32 armpll_bl2_con2; + u32 armpll_bl2_con3; + u32 armpll_bl3_con0; + u32 armpll_bl3_con1; + u32 armpll_bl3_con2; + u32 armpll_bl3_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 ap_pllgp1_con2; + u32 reserved2[33]; + u32 ap_pllgp2_con0; /* 0x0300 */ + u32 ap_pllgp2_con1; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 apupll_con0; + u32 apupll_con1; + u32 apupll_con2; + u32 apupll_con3; + u32 ap_pllgp3_con0; + u32 npupll_con0; + u32 npupll_con1; + u32 npupll_con2; + u32 npupll_con3; + u32 usbpll_con0; + u32 usbpll_con1; + u32 usbpll_con2; +}; + +check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); +check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); +check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); + +enum { + USBPLL_EN = 0x1 << 2, + + PLL_DIV_EN = 0xff << 24, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9, +}; + +enum { + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 1075 * MHz, + ARMPLL_BL_HZ = 774 * MHz, + CCIPLL_HZ = 730 * MHz, + MAINPLL_HZ = 2184UL * MHz, + UNIVPLL_HZ = 2496UL * MHz, + USBPLL_HZ = 192UL * 13 * MHz, + MSDCPLL_HZ = 384 * MHz, + MMPLL_HZ = 2750UL * MHz, + ADSPPLL_HZ = 750 * MHz, + MFGPLL_HZ = 358 * MHz, + TVDPLL_HZ = 594 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, +}; + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, + MAINPLL_D5_D4_HZ = MAINPLL_D5_HZ / 4, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_D4_HZ, + UART_HZ = CLK26M_HZ, +}; + +DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) +DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) + +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + +#endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h new file mode 100644 index 0000000000..034fa3570a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MTK_MT8192_SPI_H +#define MTK_MT8192_SPI_H + +#include + +#define SPI_BUS_NUMBER 8 + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +enum { + SPI_CFG0_CS_HOLD_SHIFT = 0, + SPI_CFG0_CS_SETUP_SHIFT = 16, +}; + +enum { + SPI_CFG2_SCK_LOW_SHIFT = 0, + SPI_CFG2_SCK_HIGH_SHIFT = 16, +}; + +enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, +}; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h new file mode 100644 index 0000000000..73ef798679 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SPM_H +#define SOC_MEDIATEK_MT8192_SPM_H + +#include +#include + +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 + +enum { + DISP_PWR_STA_MASK = 0x1 << 20, + DISP_SRAM_PDN_MASK = 0x1 << 8, + DISP_SRAM_ACK_MASK = 0x1 << 12, + AUDIO_PWR_STA_MASK = 0x1 << 21, + AUDIO_SRAM_PDN_MASK = 0x1 << 8, + AUDIO_SRAM_ACK_MASK = 0x1 << 12, +}; + +struct mtk_spm_regs { + u32 poweron_config_set; + u32 spm_power_on_val0; + u32 spm_power_on_val1; + u32 spm_clk_con; + u32 spm_clk_settle; + u32 spm_ap_standby_con; + u32 pcm_con0; + u32 pcm_con1; + u32 spm_power_on_val2; + u32 spm_power_on_val3; + u32 pcm_reg_data_ini; + u32 pcm_pwr_io_en; + u32 pcm_timer_val; + u32 pcm_wdt_val; + u32 spm_src6_mask; + u32 reserved1[1]; + u32 spm_sw_rst_con; /* 0x0040 */ + u32 spm_sw_rst_con_set; + u32 spm_sw_rst_con_clr; + u32 vs1_psr_mask_b; + u32 vs2_psr_mask_b; + u32 reserved2[12]; + u32 md32_clk_con; /* 0x0084 */ + u32 spm_sram_rsv_con; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u32 spm_scp_mailbox; + u32 scp_spm_mailbox; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_scp_irq; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u32 spm_src_req; + u32 spm_src_mask; + u32 spm_src2_mask; + u32 spm_src3_mask; + u32 spm_src4_mask; + u32 spm_src5_mask; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_ext_mask; + u32 spm_twam_event_clear; + u32 scp_clk_con; + u32 pcm_debug_con; + u32 ahb_bus_con; + u32 ddr_en_dbc_con0; + u32 ddr_en_dbc_con1; + u32 spm_resource_ack_con0; + u32 spm_resource_ack_con1; + u32 spm_resource_ack_con2; + u32 spm_resource_ack_con3; + u32 pcm_reg0_data; + u32 pcm_reg2_data; + u32 pcm_reg6_data; + u32 pcm_reg7_data; + u32 pcm_reg13_data; + u32 src_req_sta_0; + u32 src_req_sta_1; + u32 src_req_sta_2; + u32 pcm_timer_out; + u32 pcm_wdt_out; + u32 spm_irq_sta; + u32 src_req_sta_4; + u32 md32pcm_wakeup_sta; + u32 md32pcm_event_sta; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_misc; + u32 mm_dvfs_halt; + u32 reserved3[2]; + u32 bus_protect_rdy; /* 0x0150 */ + u32 bus_protect1_rdy; + u32 bus_protect2_rdy; + u32 bus_protect3_rdy; + u32 subsys_idle_sta; + u32 pcm_sta; + u32 src_req_sta_3; + u32 pwr_status; + u32 pwr_status_2nd; + u32 cpu_pwr_status; + u32 other_pwr_status; + u32 spm_vtcxo_event_count_sta; + u32 spm_infra_event_count_sta; + u32 spm_vrf18_event_count_sta; + u32 spm_apsrc_event_count_sta; + u32 spm_ddren_event_count_sta; + u32 md32pcm_sta; + u32 md32pcm_pc; + u32 reserved4[3]; + u32 dvfsrc_event_sta; /* 0x01a4 */ + u32 bus_protect4_rdy; + u32 bus_protect5_rdy; + u32 bus_protect6_rdy; + u32 bus_protect7_rdy; + u32 bus_protect8_rdy; + u32 reserved5[5]; + u32 spm_twam_last_sta0; /* 0x01d0 */ + u32 spm_twam_last_sta1; + u32 spm_twam_last_sta2; + u32 spm_twam_last_sta3; + u32 spm_twam_curr_sta0; + u32 spm_twam_curr_sta1; + u32 spm_twam_curr_sta2; + u32 spm_twam_curr_sta3; + u32 spm_twam_timer_out; + u32 spm_cg_check_sta; + u32 spm_dvfs_sta; + u32 spm_dvfs_opp_sta; + u32 spm_mcusys_pwr_con; + u32 spm_cputop_pwr_con; + u32 spm_cpu0_pwr_con; + u32 spm_cpu1_pwr_con; + u32 spm_cpu2_pwr_con; + u32 spm_cpu3_pwr_con; + u32 spm_cpu4_pwr_con; + u32 spm_cpu5_pwr_con; + u32 spm_cpu6_pwr_con; + u32 spm_cpu7_pwr_con; + u32 reserved6[1]; + u32 armpll_clk_con; /* 0x022c */ + u32 mcusys_idle_sta; + u32 gic_wakeup_sta; + u32 cpu_spare_con; + u32 cpu_spare_con_set; + u32 cpu_spare_con_clr; + u32 armpll_clk_sel; + u32 ext_int_wakeup_req; + u32 ext_int_wakeup_req_set; + u32 ext_int_wakeup_req_clr; + u32 reserved7[3]; + u32 mp0_cpu0_irq_mask; /* 0x0260 */ + u32 mp0_cpu1_irq_mask; + u32 mp0_cpu2_irq_mask; + u32 mp0_cpu3_irq_mask; + u32 mp1_cpu0_irq_mask; + u32 mp1_cpu1_irq_mask; + u32 mp1_cpu2_irq_mask; + u32 mp1_cpu3_irq_mask; + u32 mp0_cpu0_wfi_en; + u32 mp0_cpu1_wfi_en; + u32 mp0_cpu2_wfi_en; + u32 mp0_cpu3_wfi_en; + u32 mp0_cpu4_wfi_en; + u32 mp0_cpu5_wfi_en; + u32 mp0_cpu6_wfi_en; + u32 mp0_cpu7_wfi_en; + u32 root_cputop_addr; + u32 root_core_addr; + u32 reserved8[10]; + u32 spm2sw_mailbox_0; /* 0x02d0 */ + u32 spm2sw_mailbox_1; + u32 spm2sw_mailbox_2; + u32 spm2sw_mailbox_3; + u32 sw2spm_int; + u32 sw2spm_int_set; + u32 sw2spm_int_clr; + u32 sw2spm_mailbox_0; + u32 sw2spm_mailbox_1; + u32 sw2spm_mailbox_2; + u32 sw2spm_mailbox_3; + u32 sw2spm_cfg; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 mfg0_pwr_con; + u32 mfg1_pwr_con; + u32 mfg2_pwr_con; + u32 mfg3_pwr_con; + u32 mfg4_pwr_con; + u32 mfg5_pwr_con; + u32 mfg6_pwr_con; + u32 ifr_pwr_con; + u32 ifr_sub_pwr_con; + u32 dpy_pwr_con; + u32 isp_pwr_con; + u32 isp2_pwr_con; + u32 ipe_pwr_con; + u32 vde_pwr_con; + u32 vde2_pwr_con; + u32 ven_pwr_con; + u32 ven_core1_pwr_con; + u32 mdp_pwr_con; + u32 dis_pwr_con; + u32 audio_pwr_con; + u32 adsp_pwr_con; + u32 cam_pwr_con; + u32 cam_rawa_pwr_con; + u32 cam_rawb_pwr_con; + u32 cam_rawc_pwr_con; + u32 sysram_con; + u32 sysrom_con; + u32 sspm_sram_con; + u32 scp_sram_con; + u32 dpy_shu_sram_con; + u32 ufs_sram_con; + u32 devapc_ifr_sram_con; + u32 devapc_subifr_sram_con; + u32 devapc_acp_sram_con; + u32 usb_sram_con; + u32 dummy_sram_con; + u32 md_ext_buck_iso_con; + u32 ext_buck_iso; + u32 dxcc_sram_con; + u32 msdc_pwr_con; + u32 debugtop_sram_con; + u32 dp_tx_pwr_con; + u32 dpmaif_sram_con; + u32 dpy_shu2_sram_con; + u32 dramc_mcu2_sram_con; + u32 dramc_mcu_sram_con; + u32 mcupm_pwr_con; + u32 dpy2_pwr_con; + u32 peri_pwr_con; +}; + +check_member(mtk_spm_regs, md32_clk_con, 0x0084); +check_member(mtk_spm_regs, bus_protect_rdy, 0x0150); +check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4); +check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0); +check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260); +check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0); +check_member(mtk_spm_regs, peri_pwr_con, 0x03c8); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +#endif /* SOC_MEDIATEK_MT8192_SPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h new file mode 100644 index 0000000000..c988270e4b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/usb.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_USB_H +#define SOC_MEDIATEK_MT8192_USB_H + +#include + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 2 + +#endif diff --git a/src/soc/mediatek/mt8192/mtcmos.c b/src/soc/mediatek/mt8192/mtcmos.c new file mode 100644 index 0000000000..5a3b1fb189 --- /dev/null +++ b/src/soc/mediatek/mt8192/mtcmos.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +enum { + DISP_PROT_STEP1_0_MASK = 0x05015405, + DISP_PROT_STEP1_1_MASK = 0x00001100, + DISP_PROT_STEP2_0_MASK = 0x00800040, + DISP_PROT_STEP2_1_MASK = 0x0a02800a, + DISP_PROT_STEP2_2_MASK = 0x00002200, + + AUDIO_PROT_STEP1_0_MASK = 0x00000010, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8192_infracfg->infra_topaxi_protecten_clr, + DISP_PROT_STEP2_0_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr, + DISP_PROT_STEP2_1_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr_2, + DISP_PROT_STEP2_2_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr, + DISP_PROT_STEP1_0_MASK); + write32(&mt8192_infracfg->infra_topaxi_protecten_mm_clr_2, + DISP_PROT_STEP1_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8192_infracfg->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP1_0_MASK); +} diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c new file mode 100644 index 0000000000..11750d20a3 --- /dev/null +++ b/src/soc/mediatek/mt8192/pll.c @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +enum mux_id { + TOP_AXI_SEL, + TOP_SPM_SEL, + TOP_SCP_SEL, + TOP_BUS_AXIMEM_SEL, + TOP_DISP_SEL, + TOP_MDP_SEL, + TOP_IMG1_SEL, + TOP_IMG2_SEL, + TOP_IPE_SEL, + TOP_DPE_SEL, + TOP_CAM_SEL, + TOP_CCU_SEL, + TOP_DSP_SEL, + TOP_DSP7_SEL, + TOP_MFG_REF_SEL, + TOP_MFG_PLL_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_CAMTG4_SEL, + TOP_CAMTG5_SEL, + TOP_CAMTG6_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HCLK_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_MSDC30_2_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_ATB_SEL, + TOP_PWRMCU_SEL, + TOP_DPI_SEL, + TOP_SCAM_SEL, + TOP_DISP_PWM_SEL, + TOP_USB_TOP_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_I2C_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_SENINF2_SEL, + TOP_SENINF3_SEL, + TOP_TL_SEL, + TOP_DXCC_SEL, + TOP_AUD_ENGEN1_SEL, + TOP_AUD_ENGEN2_SEL, + TOP_AES_UFSFDE_SEL, + TOP_UFS_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_ADSP_SEL, + TOP_DPMAIF_MAIN_SEL, + TOP_VENC_SEL, + TOP_VDEC_SEL, + TOP_CAMTM_SEL, + TOP_PWM_SEL, + TOP_AUDIO_H_SEL, + TOP_SPMI_MST_SEL, + TOP_DVFSRC_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_MCUPM_SEL, + TOP_SFLASH_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = NULL, \ + .upd_shift = 0, \ + } + +#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0), + MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2), + MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_DISP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), + MUX_UPD(TOP_MDP_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), + MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), + MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_IPE_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8), + MUX_UPD(TOP_DPE_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9), + MUX_UPD(TOP_CAM_SEL, clk_cfg_2, 16, 4, clk_cfg_update, 10), + MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 24, 4, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12), + /* CLK_CFG_4 */ + MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16), + MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, 16, 2, clk_cfg_update, 18), + MUX(TOP_MFG_PLL_SEL, clk_cfg_4, 18, 1), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 0, 3, clk_cfg_update, 20), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24), + MUX_UPD(TOP_UART_SEL, clk_cfg_6, 8, 1, clk_cfg_update, 25), + MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26), + MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28), + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 8, 3, clk_cfg_update, 29), + MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30), + MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0), + /* CLK_CFG_8 */ + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), + MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3), + MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, 24, 3, clk_cfg_update1, 4), + /* CLK_CFG_9 */ + MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5), + MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, 8, 1, clk_cfg_update1, 6), + MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7), + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8), + /* CLK_CFG_10 */ + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 0, 2, clk_cfg_update1, 9), + MUX_UPD(TOP_I2C_SEL, clk_cfg_10, 8, 2, clk_cfg_update1, 10), + MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 11), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 12), + /* CLK_CFG_11 */ + MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, 0, 3, clk_cfg_update1, 13), + MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, 8, 3, clk_cfg_update1, 14), + MUX_UPD(TOP_TL_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15), + MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 16), + /* CLK_CFG_12 */ + MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 17), + MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19), + MUX_UPD(TOP_UFS_SEL, clk_cfg_12, 24, 3, clk_cfg_update1, 20), + /* CLK_CFG_13 */ + MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, 0, 1, clk_cfg_update1, 21), + MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, 8, 1, clk_cfg_update1, 22), + MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 23), + MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 24), + /* CLK_CFG_14 */ + MUX_UPD(TOP_VENC_SEL, clk_cfg_14, 0, 4, clk_cfg_update1, 25), + MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, 8, 4, clk_cfg_update1, 26), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 27), + MUX_UPD(TOP_PWM_SEL, clk_cfg_14, 24, 1, clk_cfg_update1, 28), + /* CLK_CFG_15 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, 0, 2, clk_cfg_update1, 29), + MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 30), + MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, 16, 1, clk_cfg_update2, 0), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, 24, 3, clk_cfg_update2, 1), + /* CLK_CFG_16 */ + MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 0, 2, clk_cfg_update2, 2), + MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, 8, 2, clk_cfg_update2, 3), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ + { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ + { .id = TOP_SCP_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + /* CLK_CFG_1 */ + { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mainpll_d4 */ + { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: tvdpll_ck */ + { .id = TOP_IMG1_SEL, .sel = 1 }, /* 1: univpll_d4 */ + { .id = TOP_IMG2_SEL, .sel = 1 }, /* 1: univpll_d4 */ + /* CLK_CFG_2 */ + { .id = TOP_IPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_DPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ + { .id = TOP_CAM_SEL, .sel = 3 }, /* 3: univpll_d4 */ + { .id = TOP_CCU_SEL, .sel = 8 }, /* 8: univpll_d5 */ + /* CLK_CFG_3 */ + { .id = TOP_DSP_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + /* CLK_CFG_4 */ + { .id = TOP_DSP7_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_MFG_REF_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + { .id = TOP_MFG_PLL_SEL, .sel = 1 }, /* 1: mfgpll */ + { .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_5 */ + { .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_CAMTG5_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + /* CLK_CFG_6 */ + { .id = TOP_CAMTG6_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_7 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + { .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_MSDC30_2_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ + { .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_8 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: osc_d10 */ + { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_d2 */ + { .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + { .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + /* CLK_CFG_10 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ + { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */ + /* CLK_CFG_11 */ + { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */ + { .id = TOP_TL_SEL, .sel = 1 }, /* 1: univpll_192m_d2 */ + { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + /* CLK_CFG_12 */ + { .id = TOP_AUD_ENGEN1_SEL, .sel = 2 }, /* 2: apll1_d4 */ + { .id = TOP_AUD_ENGEN2_SEL, .sel = 2 }, /* 2: apll2_d4 */ + { .id = TOP_AES_UFSFDE_SEL, .sel = 6 }, /* 6: univpll_d6 */ + { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */ + /* CLK_CFG_13 */ + { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ + { .id = TOP_ADSP_SEL, .sel = 7 }, /* 7: adsppll_ck */ + { .id = TOP_DPMAIF_MAIN_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + /* CLK_CFG_14 */ + { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ + { .id = TOP_VDEC_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ + { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ + { .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_15 */ + { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ + { .id = TOP_SPMI_MST_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ + /* CLK_CFG_16 */ + { .id = TOP_MCUPM_SEL, .sel = 2 }, /* 2: mainpll_d6_d2 */ + { .id = TOP_SFLASH_SEL, .sel = 1 }, /* 1: mainpll_d7_d8 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_MAINPLL, + APMIXED_UNIVPLL, + APMIXED_USBPLL, + APMIXED_MSDCPLL, + APMIXED_MMPLL, + APMIXED_ADSPPLL, + APMIXED_MFGPLL, + APMIXED_TVDPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_PLL_MAX +}; + +const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl0_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, + 23, 22, univpll_con1, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_USBPLL, usbpll_con0, usbpll_con2, + NO_RSTB_SHIFT, 22, usbpll_con0, 24, usbpll_con0, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + 23, 22, mmpll_con1, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, + NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, + { .id = APMIXED_USBPLL, .rate = USBPLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, + { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, 0x2); + + /* reduce PLL current */ + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp1_con1, PLLGP1_LVRREF, 1); + SET32_BITFIELDS(&mtk_apmixed->ap_pllgp2_con1, PLLGP2_LVRREF, 1); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (i == APMIXED_USBPLL) + setbits32(plls[APMIXED_USBPLL].pwr_reg, USBPLL_EN); + else + setbits32(plls[i].reg, PLL_EN); + } + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* enable infrasys DCM */ + setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + + /* initialize SPM request */ + setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); + clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); + + /* + * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING CONSTANTS! + */ + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* enable [14] dramc_pll104m_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca55 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca55 clock source back to armpll_ll */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} + +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) +{ + u32 output, count, clk_dbg_cfg, clk_misc_cfg_0; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else { + die("unsupport fmeter type\n"); + } + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x1000); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); + + /* wait frequency meter until finished */ + if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + output = (count * 26000) / 1024; /* KHz */ + } else { + printk(BIOS_WARNING, "fmeter timeout\n"); + output = 0; + } + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + if (type == FMETER_ABIST) + return output * 2; + else if (type == FMETER_CKGEN) + return output; + + return 0; +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c new file mode 100644 index 0000000000..9850fa6fbe --- /dev/null +++ b/src/soc/mediatek/mt8192/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8192_ops = { + CHIP_NAME("SOC Mediatek MT8192") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c new file mode 100644 index 0000000000..d35e5ad3ca --- /dev/null +++ b/src/soc/mediatek/mt8192/spi.c @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SCP_SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(CAM_RST1), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT5), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + }, + { + .regs = (void *)SPI6_BASE, + .cs_gpio = GPIO(EINT1), + }, + { + .regs = (void *)SPI7_BASE, + .cs_gpio = GPIO(SDA0), + } +}; + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_A_MI), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_A_MO), + PAD_FUNC(SPI0_CLK, SPI0_A_CLK), + }, + { + PAD_FUNC(SPI1_MI, SPI1_A_MI), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_A_MO), + PAD_FUNC(SPI1_CLK, SPI1_A_CLK), + }, + { + PAD_FUNC(SCP_SPI2_MI, SPI2_MI), + PAD_FUNC_GPIO(SCP_SPI2_CSB), + PAD_FUNC(SCP_SPI2_MO, SPI2_MO), + PAD_FUNC(SCP_SPI2_CK, SPI2_CLK), + }, + { + PAD_FUNC(CAM_RST2, SPI3_MI), + PAD_FUNC_GPIO(CAM_RST1), + PAD_FUNC(CAM_PDN0, SPI3_MO), + PAD_FUNC(CAM_RST0, SPI3_CLK), + }, + { + PAD_FUNC(EINT6, SPI4_A_MI), + PAD_FUNC_GPIO(EINT5), + PAD_FUNC(EINT7, SPI4_A_MO), + PAD_FUNC(EINT4, SPI4_A_CLK), + }, + { + PAD_FUNC(SPI5_MI, SPI5_A_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_A_MO), + PAD_FUNC(SPI5_CLK, SPI5_A_CLK), + }, + { + PAD_FUNC(EINT2, SPI6_MI), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT3, SPI6_MO), + PAD_FUNC(EINT0, SPI6_CLK), + }, + { + PAD_FUNC(EINT16, SPI7_A_MI), + PAD_FUNC_GPIO(SDA0), + PAD_FUNC(EINT17, SPI7_A_MO), + PAD_FUNC(SCL0, SPI7_A_CLK), + } +}; + +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + assert(pad_select == SPI_PAD0_MASK); + const struct pad_func *ptr = NULL; + + ptr = pad0_funcs[bus]; + for (int i = 0; i < 4; i++) + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); +} + +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) +{ + write32(®s->spi_cfg0_reg, + ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | + ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); + + write32(®s->spi_cfg2_reg, + ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | + ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); + + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); +} + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { + .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c new file mode 100644 index 0000000000..44f2f150ed --- /dev/null +++ b/src/soc/mediatek/mt8192/usb.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define REG_SPM_POWERON_CONFIG_EN (void *)(SPM_BASE + 0x000) +#define REG_SPM_SSPM_PWR_CON (void *)(SPM_BASE + 0x390) + +void mtk_usb_prepare(void) +{ + /* power on SSUSB SRAM FIFO */ + setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); + clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); +} diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 27bbee80e6..6743a105c4 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -348,7 +348,6 @@ struct display_controller { }; check_member(display_controller, winbuf, 0x800 * 4); - /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define DISP_COMMAND_RAISE (1 << 0) #define DISP_CTRL_MODE_STOP (0 << 5) diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h index 09ef4aaba7..0e3e2fe4f0 100644 --- a/src/soc/nvidia/tegra/displayport.h +++ b/src/soc/nvidia/tegra/displayport.h @@ -326,11 +326,9 @@ struct tegra_dc_dp_data { int enabled; }; - /* DPCD definitions */ /* you know, all the vendors pick their own set of defines. * All of them. - * FIXME so we can use the ones in include/device/drm_dp_helper.h */ #define NV_DPCD_REV (0x00000000) #define NV_DPCD_REV_MAJOR_SHIFT (4) diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h index 387fb676ea..c6336e54e2 100644 --- a/src/soc/nvidia/tegra/usb.h +++ b/src/soc/nvidia/tegra/usb.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA_USB_H__ #define __SOC_NVIDIA_TEGRA_USB_H__ - enum usb_phy_type { /* For use in lpm_ctrl[31:29] */ USB_PHY_UTMIP = 0, USB_PHY_ULPI = 2, diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index a6fa93b32e..167f4a1229 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -5,7 +5,6 @@ #include #include #include -#include struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index e3885bf834..4155c34b21 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -616,7 +616,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, if (link_cfg->hblank_sym < 0) link_cfg->hblank_sym = 0; - /* Refer to dev_disp.ref for more information. */ /* # symbols/vblank = ((SetRasterBlankStart.X - */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */ diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h index 45cd9143c7..b19ae5fa7f 100644 --- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h @@ -35,7 +35,7 @@ enum { NvBootMemoryType_Num, /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, + NvBootMemoryType_Unused = 0x7FFFFFF, }; enum { diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 85d331b5ce..38a385cd29 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -2,31 +2,25 @@ /* Function unit addresses. */ enum { - UP_TAG_BASE = 0X60000000, - TIMER_BASE = 0X60005000, - CLK_RST_BASE = 0X60006000, - FLOW_CTLR_BASE = 0X60007000, + UP_TAG_BASE = 0x60000000, + TIMER_BASE = 0x60005000, + CLK_RST_BASE = 0x60006000, + FLOW_CTLR_BASE = 0x60007000, TEGRA_EVP_BASE = 0x6000f000, - PMC_CTLR_BASE = 0X7000e400, - MC_CTLR_BASE = 0X70019000, - SYSCTR_CTLR_BASE = 0X700f0000 + PMC_CTLR_BASE = 0x7000e400, + MC_CTLR_BASE = 0x70019000, + SYSCTR_CTLR_BASE = 0x700f0000 }; - - /* UP tag registers. */ static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); enum { UP_TAG_AVP = 0xaaaaaaaa }; - - /* Timer registers. */ static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); - - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -152,14 +146,9 @@ enum { CLR_NONCPURESET = 0x1 << 29 }; - - /* Reset vector. */ - static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); - - /* Flow controller registers. */ static uint32_t *flow_ctlr_halt_cop_events_ptr = (void *)(FLOW_CTLR_BASE + 0x4); @@ -185,7 +174,6 @@ enum { RAM_REPAIR_STS = 0x1 << 1, }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -220,8 +208,6 @@ enum { PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT }; - - /* Memory controller registers. */ static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); @@ -232,8 +218,6 @@ enum { VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 }; - - /* System counter registers. */ static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); enum { @@ -243,10 +227,7 @@ enum { static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); - - /* Utility functions. */ - static __always_inline void __noreturn halt(void) { for (;;); @@ -285,10 +266,7 @@ static void udelay(unsigned int usecs) ; } - - /* Accessors. */ - static int wakeup_on_lp(void) { return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); @@ -304,10 +282,7 @@ static unsigned int get_osc_freq(void) return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } - - /* Clock configuration. */ - static void config_oscillator(void) { // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy @@ -416,10 +391,7 @@ static void enable_cpu_clocks(void) write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } - - /* Function unit configuration. */ - static void config_core_sight(void) { // Enable the CoreSight clock. @@ -449,10 +421,7 @@ static void config_mselect(void) write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } - - /* Resets. */ - static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. @@ -471,10 +440,7 @@ static void clear_cpu_resets(void) CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } - - /* RAM repair */ - void ram_repair(void) { // Request Cluster0 RAM repair. @@ -490,9 +456,7 @@ void ram_repair(void) ; } - /* Power. */ - static void power_on_partition(unsigned int id) { uint32_t bit = 0x1 << id; @@ -544,10 +508,7 @@ static void power_on_main_cpu(void) write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } - - /* Entry point. */ - void lp0_resume(void) { // If not on the AVP, reset. @@ -608,10 +569,7 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - - /* Header. */ - extern uint8_t blob_data; extern uint8_t blob_data_size; extern uint8_t blob_total_size; diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 30ceee6006..01444a1d02 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -11,7 +11,6 @@ #include #include - static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index adf0248849..3a078f8573 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -336,7 +335,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi) spi_delay(spi, dma_blk - count); } - static int fifo_error(struct tegra_spi_channel *spi) { return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; @@ -524,8 +522,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); - - } static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index d016cc2618..aba8dd954d 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -5,7 +5,6 @@ #include #include - struct tegra124_uart { union { uint32_t thr; // Transmit holding register. @@ -76,12 +75,12 @@ static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr) return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { //Default to UART A unsigned int base = 0x70006000; //UARTs A - E are mapped as index 0 - 4 - if ((idx < 5) && (idx >= 0)) { + if ((idx < 5)) { if (idx != 1) { //not UART B base += idx * 0x100; } else { @@ -91,25 +90,25 @@ uintptr_t uart_platform_base(int idx) return base; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_init(uart_ptr); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); return tegra124_uart_rx_byte(uart_ptr); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_tx_byte(uart_ptr, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct tegra124_uart *uart_ptr = uart_platform_baseptr(idx); tegra124_uart_tx_flush(uart_ptr); diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index ce5eaf20ca..1657d7ce44 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -179,7 +179,6 @@ void tegra210_main(void) pmc_print_rst_status(); - bootblock_mainboard_init(); printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n"); diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 7da5d2117d..8625f76a8c 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -91,7 +91,6 @@ int update_display_mode(struct display_controller *disp_ctrl, WRITEL(config->vsync_width << 16 | config->hsync_width, &disp_ctrl->disp.sync_width); - WRITEL((config->vback_porch << 16) | config->hback_porch, &disp_ctrl->disp.back_porch); diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index db57191e6d..26b64c8b34 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -5,7 +5,6 @@ #include #include #include -#include struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 82923c3cfe..9c55242765 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -631,7 +631,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, if (link_cfg->hblank_sym < 0) link_cfg->hblank_sym = 0; - /* Refer to dev_disp.ref for more information. */ /* # symbols/vblank = ((SetRasterBlankStart.X - */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */ @@ -1189,7 +1188,6 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp, int j; u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); - printk(BIOS_INFO, "dp: %s\n", __func__); tegra_dc_sor_set_lane_parm(sor, link_cfg); diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 3ee114e177..5026ef4b58 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -434,7 +434,6 @@ static int tegra_output_dsi_enable(struct tegra_dsi *dsi, return 0; } - static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, unsigned int vrefresh) { @@ -520,8 +519,6 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, return plld/1000000; } - - static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { unsigned long value; diff --git a/src/soc/nvidia/tegra210/include/soc/ccplex.h b/src/soc/nvidia/tegra210/include/soc/ccplex.h index 3975f44445..b27d5abc16 100644 --- a/src/soc/nvidia/tegra210/include/soc/ccplex.h +++ b/src/soc/nvidia/tegra210/include/soc/ccplex.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__ #define __SOC_NVIDIA_TEGRA210_CCPLEX_H__ - #define MTS_LOAD_ADDRESS 0x82000000 /* Prepare the clocks and rails to start the cpu. */ diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h index 5c5097ab66..56c3355fe6 100644 --- a/src/soc/nvidia/tegra210/include/soc/id.h +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -3,7 +3,6 @@ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ - #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index 4a53a07853..ec5c54ea3b 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -2,7 +2,6 @@ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H - /* * Macros for calculating the phy timings */ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h index 7513302d05..f9d7c6b592 100644 --- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -38,7 +38,7 @@ enum { NvBootMemoryType_Num, /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, + NvBootMemoryType_Unused = 0x7FFFFFF, }; enum { diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 0740d36807..9e2754d05f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -26,7 +26,6 @@ enum { UP_TAG_AVP = 0xaaaaaaaa }; - /* APB Misc JTAG Configuration Register */ static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24); enum { @@ -40,7 +39,6 @@ enum { CFG2TMC_RAM_SVOP_PDP_VAL_2 = 0x2 << 24, }; - /* PINMUX registers. */ static uint32_t *pinmux_pwr_i2c_scl_ptr = (void *)(PINMUX_BASE + 0xdc); static uint32_t *pinmux_pwr_i2c_sda_ptr = (void *)(PINMUX_BASE + 0xe0); @@ -57,7 +55,6 @@ enum { static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); static uint32_t *timer_us_cfg_ptr = (void *)(TIMER_BASE + 0x14); - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -264,7 +261,6 @@ enum { ACTIVE_SLOW = 0x1 << 0 }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -346,7 +342,6 @@ enum { static uint32_t *sb_aa64_reset_low = (void *)(SECURE_BOOT_BASE + 0x30); static uint32_t *sb_aa64_reset_high = (void *)(SECURE_BOOT_BASE + 0x34); - /* EMC registers */ static uint32_t *pmacro_cfg_pm_global = (void *)(EMC_BASE + 0xc30); enum { @@ -408,7 +403,6 @@ enum { #define MAX77621_VOUT_VAL (0x80 | 0x27) #define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8)) - /* Utility functions. */ static __always_inline void __noreturn halt(void) @@ -592,7 +586,6 @@ static void enable_select_cpu_clocks(void) udelay(10); } - /* Function unit configuration. */ static void config_core_sight(void) @@ -609,7 +602,6 @@ static void config_core_sight(void) write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } - /* RAM repair */ void ram_repair(void) @@ -621,7 +613,6 @@ void ram_repair(void) ; } - /* Power. */ static void power_on_partition(unsigned int id) @@ -764,7 +755,6 @@ static void mbist_workaround(void) write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); - clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0; write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared); @@ -1085,7 +1075,6 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - /* Header. */ extern uint8_t blob_data; diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 8fde9c2ea7..66f9fd8c93 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -320,7 +319,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi) ASSERT(spi_byte_count(spi) == dma_blk_count); } - static int fifo_error(struct tegra_spi_channel *spi) { return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; @@ -551,8 +549,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); - - } static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 865e1fafe1..98c3d4ca9c 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -26,7 +26,6 @@ struct tegra210_uart { uint32_t msr; // Modem status register. } __packed; - static struct tegra210_uart * const uart_ptr = (void *)CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; @@ -82,22 +81,22 @@ static int tegra210_uart_tst_byte(void) return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; } -void uart_init(int idx) +void uart_init(unsigned int idx) { tegra210_uart_init(); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { tegra210_uart_tx_byte(data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { tegra210_uart_tx_flush(); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return tegra210_uart_rx_byte(); } diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index e8dc499fb6..c906ef2f73 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -11,7 +11,6 @@ #define QCLIB_TE_NAME_LENGTH 24 /* FMAP_REGION names */ -#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" #define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG" /* TE_NAME (table entry name) */ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d06cb429eb..d4796a2e7c 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -3,12 +3,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -16,6 +18,8 @@ #include #include +#define QCLIB_VERSION 0 + struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, .version = QCLIB_INTERFACE_VERSION, @@ -70,9 +74,16 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te) } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { - - assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, - (const void *)te->blob_address, te->size)); + /* + * Don't store training data if we're in recovery mode + * because we always want to retrain due to + * possibility of RW training data possibly being + * updated to a different format. + */ + if (vboot_recovery_mode_enabled()) + return; + assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION, + (const void *)te->blob_address, te->size)); } else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, sizeof(te->name))) { @@ -112,7 +123,7 @@ __weak int qclib_soc_blob_load(void) { return 0; } void qclib_load_and_run(void) { int i; - ssize_t ssize; + ssize_t data_size; struct mmu_context pre_qclib_mmu_context; /* zero ddr_information SRAM region, needs new data each boot */ @@ -127,13 +138,23 @@ void qclib_load_and_run(void) /* output area, QCLib fills in DDR details */ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); - /* Attempt to load DDR Training Blob */ - ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, - REGION_SIZE(ddr_training)); - if (ssize < 0) - goto fail; + /* + * We never want to use training data when booting into + * recovery mode. + */ + if (vboot_recovery_mode_enabled()) { + memset(_ddr_training, 0, REGION_SIZE(ddr_training)); + } else { + /* Attempt to load DDR Training Blob */ + data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, + _ddr_training, REGION_SIZE(ddr_training)); + if (data_size < 0) { + printk(BIOS_ERR, "Unable to load previous training data.\n"); + memset(_ddr_training, 0, REGION_SIZE(ddr_training)); + } + } qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, - _ddr_training, ssize, 0); + _ddr_training, REGION_SIZE(ddr_training), 0); /* hook for SoC specific binary blob loads */ if (qclib_soc_blob_load()) { diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index 2e2a8af8d8..e7874a786a 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -17,7 +17,6 @@ static inline int gpio_not_valid(gpio_t gpio) return (gpio > GPIO_MAX_NUM); } - /******************************************************* Function description: configure GPIO functinality Arguments : @@ -30,7 +29,6 @@ unsigned enable - 0 Disable, 1 - Enable. Return : None *******************************************************/ - void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, unsigned int pull, unsigned int drvstr, unsigned int enable) @@ -60,7 +58,6 @@ unsigned *enable - 0 - Disable, 1- Enable. Return : None *******************************************************/ - void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, unsigned int *pull, unsigned int *drvstr, unsigned int *enable) @@ -93,7 +90,6 @@ int gpio_get(gpio_t gpio) if (gpio_not_valid(gpio)) return -1; - return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) & GPIO_IO_IN_MASK; } diff --git a/src/soc/qualcomm/ipq40xx/include/soc/blsp.h b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h index 7671539c1a..cbef2084a9 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/blsp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/blsp.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ - #ifndef __BLSP_H_ #define __BLSP_H_ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h index 5c13581026..f3241fb5b9 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _IPQ40XX_CDP_H_ #define _IPQ40XX_CDP_H_ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h index 2b48a2c484..1c4c32977d 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h @@ -5,6 +5,7 @@ #define __IPQ40XX_CLOCK_H_ #include +#include /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xFF @@ -174,7 +175,6 @@ #define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) #define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) - /* Uart specific clock settings */ void uart_pll_vote_clk_enable(unsigned int); @@ -185,5 +185,4 @@ void usb_clock_config(void); int audio_clock_config(unsigned int frequency); int blsp_i2c_clock_config(blsp_qup_id_t id); - #endif /* __PLATFORM_IPQ40XX_CLOCK_H_ */ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h index c730d2c190..feac71c7b9 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/ipq_uart.h @@ -10,7 +10,6 @@ extern void __udelay(unsigned long usec); - enum MSM_BOOT_UART_DM_PARITY_MODE { MSM_BOOT_UART_DM_NO_PARITY, MSM_BOOT_UART_DM_ODD_PARITY, diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h index 9fcc15fae2..0ccc5caabb 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/spi.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h @@ -134,7 +134,6 @@ struct blsp_spi { void *qup_deassert_wait; }; - #define SUCCESS 0 #define DUMMY_DATA_VAL 0 @@ -148,7 +147,6 @@ struct blsp_spi { * (count function disabled) and does not hold significance in the count. */ #define MAX_PACKET_COUNT ((64 * KiB) - 1) - struct ipq_spi_slave { struct spi_slave slave; const struct blsp_spi *regs; diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 265c25e28b..9c506111fa 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -87,7 +87,7 @@ static int valid_data = 0; /* Received data */ static unsigned int word = 0; -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; void *base = uart_board_param.uart_dm_base; @@ -195,7 +195,7 @@ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -230,7 +230,7 @@ void ipq40xx_uart_init(void) * @brief uart_tx_flush - transmits a string of data * @param idx: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -244,7 +244,7 @@ void uart_tx_flush(int idx) * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/ipq40xx/usb.c b/src/soc/qualcomm/ipq40xx/usb.c index 7707c50fba..b3c0813fbb 100644 --- a/src/soc/qualcomm/ipq40xx/usb.c +++ b/src/soc/qualcomm/ipq40xx/usb.c @@ -44,14 +44,12 @@ #define DWC3_GSNPSID 0xc120 #define DWC3_DCTL 0xc704 - /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GSNPSID_MASK 0xffff0000 #define DWC3_GEVTEN 0xc114 - #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) #define DWC3_GCTL_DISSCRAMBLE (1 << 3) diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index 2e2a8af8d8..e7874a786a 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -17,7 +17,6 @@ static inline int gpio_not_valid(gpio_t gpio) return (gpio > GPIO_MAX_NUM); } - /******************************************************* Function description: configure GPIO functinality Arguments : @@ -30,7 +29,6 @@ unsigned enable - 0 Disable, 1 - Enable. Return : None *******************************************************/ - void gpio_tlmm_config_set(gpio_t gpio, unsigned int func, unsigned int pull, unsigned int drvstr, unsigned int enable) @@ -60,7 +58,6 @@ unsigned *enable - 0 - Disable, 1- Enable. Return : None *******************************************************/ - void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, unsigned int *pull, unsigned int *drvstr, unsigned int *enable) @@ -93,7 +90,6 @@ int gpio_get(gpio_t gpio) if (gpio_not_valid(gpio)) return -1; - return (read32(GPIO_IN_OUT_ADDR(gpio)) >> GPIO_IO_IN_SHIFT) & GPIO_IO_IN_MASK; } diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index d7cb3c484d..79a5a2dd89 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -156,7 +156,6 @@ #define GMAC_COREn_CLCK_INV_DISABLE (0 << 5) #define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4) - /* Uart specific clock settings */ void uart_pll_vote_clk_enable(unsigned int); diff --git a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h index 29a56e73ca..323b47d449 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/gsbi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/gsbi.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: ISC */ - #ifndef __GSBI_H_ #define __GSBI_H_ diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index e9e3e04995..98a891141c 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -122,7 +122,6 @@ #define GSBI_QUP_APPS_PRE_DIV_SFT 3 #define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 - #define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \ (32*(gsbi_n-1))) #define GSBI_QUP_APSS_NS_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29cc) + \ diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h index ef499197b7..5903652d25 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h @@ -11,7 +11,6 @@ extern void __udelay(unsigned long usec); - enum MSM_BOOT_UART_DM_PARITY_MODE { MSM_BOOT_UART_DM_NO_PARITY, MSM_BOOT_UART_DM_ODD_PARITY, diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index d65f0fd381..2b18bda608 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -32,7 +32,6 @@ #define GSBI_IDX_TO_GSBI(idx) (idx + 5) - /* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning * (count function disabled) and does not hold significance in the count. */ #define MAX_PACKET_COUNT ((64 * KiB) - 1) @@ -141,7 +140,6 @@ static unsigned int qup_apps_clk_state[NUM_PORTS] = { GSBI7_QUP_APPS_CLK }; - static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay) { unsigned int count = TIMEOUT_CNT; diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index ea564b3527..3a3a8bf27b 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -160,7 +160,7 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) } #endif -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; unsigned int tx_data = 0; @@ -269,7 +269,7 @@ static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -316,7 +316,7 @@ uint32_t uartmem_getbaseaddr(void) * uart_tx_flush - transmits a string of data * @s: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -351,7 +351,7 @@ int uart_can_rx_byte(void) * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 0dc96ba06a..bad62b236b 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -6,7 +6,6 @@ config SOC_QUALCOMM_QCS405 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select ARM64_USE_ARCH_TIMER select HAVE_UART_SPECIAL diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index 1d46071b21..b21ae26b71 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -3,7 +3,6 @@ #ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ - #define QSPI_BASE 0x88DF000 #define TLMM_EAST_TILE_BASE 0x7B00000 #define TLMM_NORTH_TILE_BASE 0x1300000 diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h index 7671539c1a..cbef2084a9 100644 --- a/src/soc/qualcomm/qcs405/include/soc/blsp.h +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ - #ifndef __BLSP_H_ #define __BLSP_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h index 8c25631dbd..7c4286049e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/cdp.h +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _QCS405_CDP_H_ #define _QCS405_CDP_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index 86be1b0cc1..18f77816de 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -17,7 +17,6 @@ typedef struct { #define TLMM_GPIO_IN_OUT_OFF 0x4 #define TLMM_GPIO_ID_STATUS_OFF 0x10 - /* GPIO INTR CFG MASK */ #define GPIO_INTR_DECT_CTL_MASK 0x3 #define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index f758a22d05..d0959c6fac 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -3,7 +3,6 @@ #ifndef __QUP_H__ #define __QUP_H__ - /* QUP block registers */ #define QUP_CONFIG 0x000 #define QUP_STATE 0x004 diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h index cfd98ad969..4fe647453a 100644 --- a/src/soc/qualcomm/qcs405/include/soc/spi.h +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -155,7 +155,6 @@ struct blsp_spi { void *qup_deassert_wait; }; - #define SUCCESS 0 #define DUMMY_DATA_VAL 0 @@ -169,7 +168,6 @@ struct blsp_spi { * (count function disabled) and does not hold significance in the count. */ #define MAX_PACKET_COUNT ((64 * KiB) - 1) - struct qcs_spi_slave { struct spi_slave slave; const struct blsp_spi *regs; diff --git a/src/soc/qualcomm/qcs405/include/soc/uart.h b/src/soc/qualcomm/qcs405/include/soc/uart.h index e3f0cfd5ee..c222add717 100644 --- a/src/soc/qualcomm/qcs405/include/soc/uart.h +++ b/src/soc/qualcomm/qcs405/include/soc/uart.h @@ -10,7 +10,6 @@ extern void __udelay(unsigned long usec); - enum MSM_BOOT_UART_DM_PARITY_MODE { MSM_BOOT_UART_DM_NO_PARITY, MSM_BOOT_UART_DM_ODD_PARITY, diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c index 3ba4ba6874..316cd9fed0 100644 --- a/src/soc/qualcomm/qcs405/qup.c +++ b/src/soc/qualcomm/qcs405/qup.c @@ -60,7 +60,6 @@ static void i2c_set_mstr_clk_ctl(unsigned int id, unsigned int hz) qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl); } - static qup_return_t qup_i2c_master_status(blsp_qup_id_t id) { uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS)); diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 1229053783..97f9e76520 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -89,8 +89,7 @@ static int valid_data = 0; /* Received data */ static unsigned int word = 0; - -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { int num_of_chars = 1; void *base = uart_board_param.uart_dm_base; @@ -199,7 +198,7 @@ unsigned int msm_boot_uart_dm_init(void *uart_dm_base) * * Initializes clocks, GPIO and UART controller. */ -void uart_init(int idx) +void uart_init(unsigned int idx) { /* Note int idx isn't used in this driver. */ void *dm_base; @@ -231,7 +230,7 @@ void qcs405_uart_init(void) * @brief uart_tx_flush - transmits a string of data * @param idx: string to transmit */ -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { void *base = uart_board_param.uart_dm_base; @@ -246,7 +245,7 @@ void uart_tx_flush(int idx) * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +uint8_t uart_rx_byte(unsigned int idx) { uint8_t byte; diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index 3820e1371e..19d1e0e3e7 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -5,6 +5,7 @@ #include #include #include +#include /* USB BASE ADDRESS */ #define USB_HOST0_DWC3_BASE 0x758C100 @@ -196,7 +197,6 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) /* Clear core reset. */ clock_reset_bcr(dwc3->usb3_bcr, 0); - if (port == HSUSB_SS_PORT_0) { /* Set PHY reset. */ setbits32(&dwc3->usb2_phy_bcr, BIT(1)); diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d3dab7acd9..570b68a119 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -6,6 +6,7 @@ config SOC_QUALCOMM_SC7180 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER @@ -13,6 +14,10 @@ config SOC_QUALCOMM_SC7180 select SOC_QUALCOMM_COMMON select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select CACHE_MRC_SETTINGS if SOC_QUALCOMM_SC7180 @@ -25,6 +30,7 @@ config VBOOT select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config SC7180_QSPI bool diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 4961d244d0..a0d3bc6cda 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -29,6 +29,7 @@ verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ romstage-y += cbmem.c +romstage-y += watchdog.c romstage-y += timer.c romstage-y += ../common/qclib.c romstage-y += qclib.c @@ -59,12 +60,101 @@ ramstage-y += usb.c ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include +BL31_MAKEARGS += PLAT=sc7180 + +SC7180_BLOB := $(top)/3rdparty/qc_blobs/sc7180 + +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +BL31_MAKEARGS += QTI_SDI_BUILD=1 +BL31_MAKEARGS += QTISECLIB_PATH=$(SC7180_BLOB)/qtiseclib/libqtisec_dbg.a +else +BL31_MAKEARGS += QTISECLIB_PATH=$(SC7180_BLOB)/qtiseclib/libqtisec.a +endif # CONFIG_QC_SDI_ENABLE + ################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SC7180_BLOB)/boot/QcSdi.elf +QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi +$(QCSDI_CBFS)-file := $(QCSDI_FILE) +$(QCSDI_CBFS)-type := stage +$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(QCSDI_CBFS) +endif + +################################################################################ +QCLIB_FILE := $(SC7180_BLOB)/boot/QcLib.elf +QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib +$(QCLIB_CBFS)-file := $(QCLIB_FILE) +$(QCLIB_CBFS)-type := stage +$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +cbfs-files-y += $(QCLIB_CBFS) + +################################################################################ +PMIC_FILE := $(SC7180_BLOB)/boot/Pmic.bin +PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg +$(PMIC_CBFS)-file := $(PMIC_FILE) +$(PMIC_CBFS)-type := raw +$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(PMIC_CBFS) + +################################################################################ +DCB_FILE := $(SC7180_BLOB)/boot/dcb.bin +DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb +$(DCB_CBFS)-file := $(DCB_FILE) +$(DCB_CBFS)-type := raw +$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(DCB_CBFS) + +################################################################################ +AOP_FILE := $(SC7180_BLOB)/aop/aop.mbn +AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop +$(AOP_CBFS)-file := $(AOP_FILE) +$(AOP_CBFS)-type := payload +$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CBFS) + +################################################################################ +UART_FW_FILE := $(SC7180_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := none +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(SC7180_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := none +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(SC7180_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := none +cbfs-files-y += $(I2C_FW_CBFS) + +################################################################################ +QC_SEC_FILE := $(SC7180_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin endif diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 85ea67e69d..eb90f86383 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 1683d70cbe..919735d7d6 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -11,14 +11,6 @@ #define DIV(div) (2 * div - 1) struct clock_config qup_cfg[] = { - { - .hz = QUPV3_UART_SRC_HZ, - .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), - .m = 384, - .n = 15625, - .d_2 = 15625, - }, { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, @@ -104,6 +96,20 @@ struct clock_config qup_wrap_cfg[] = { }, }; +static struct sc7180_mnd_clock *mdss_clock[MDSS_CLK_COUNT] = { + [MDSS_CLK_ESC0] = &mdss->esc0, + [MDSS_CLK_PCLK0] = &mdss->pclk0, + [MDSS_CLK_BYTE0] = &mdss->byte0, + [MDSS_CLK_BYTE0_INTF] = &mdss->byte0, +}; + +static u32 *mdss_cbcr[MDSS_CLK_COUNT] = { + [MDSS_CLK_ESC0] = &mdss->esc0_cbcr, + [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr, + [MDSS_CLK_BYTE0] = &mdss->byte0_cbcr, + [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr, +}; + static int clock_configure_gpll0(void) { setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT); @@ -202,7 +208,7 @@ void clock_configure_qspi(uint32_t hz) qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg)); clock_enable(&gcc->qspi_cnoc_ahb_cbcr); - clock_enable(&gcc->qspi_core.cbcr); + clock_enable(&gcc->qspi_core_cbcr); } int clock_reset_bcr(void *bcr_addr, bool reset) @@ -323,11 +329,63 @@ static void speed_up_boot_cpu(void) printk(BIOS_DEBUG, "L3 Frequency bumped to 1.2096(GHz)\n"); } +int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, + uint32_t half_divider, uint32_t m, + uint32_t n, uint32_t d_2) +{ + struct clock_config mdss_clk_cfg; + uint32_t reg_val; + + if (clk_type >= MDSS_CLK_COUNT) + return -1; + + /* Initialize it with received arguments */ + mdss_clk_cfg.hz = 0; + mdss_clk_cfg.src = source; + + /* + * client is expected to provide 2n divider value, + * as the divider value in register is in form "2n-1" + */ + mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0; + mdss_clk_cfg.m = m; + mdss_clk_cfg.n = n; + mdss_clk_cfg.d_2 = d_2; + + /* configure and set the clock */ + reg_val = (mdss_clk_cfg.src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (mdss_clk_cfg.div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&mdss_clock[clk_type]->clock.rcg_cfg, reg_val); + + /* Set m/n/d values for a specific clock */ + if (mdss_clk_cfg.m != 0) + clock_configure_mnd((struct sc7180_clock *)mdss_clock[clk_type], + mdss_clk_cfg.m, mdss_clk_cfg.n, mdss_clk_cfg.d_2); + + /* Commit config to RCG */ + setbits32(&mdss_clock[clk_type]->clock.rcg_cmd, + BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +int mdss_clock_enable(enum mdss_clock clk_type) +{ + if (clk_type >= MDSS_CLK_COUNT) + return -1; + + /* Enable clock*/ + clock_enable(mdss_cbcr[clk_type]); + + return 0; +} + void clock_init(void) { clock_configure_gpll0(); - clock_enable_vote(&gcc->qup_wrap0_core_2x.cbcr, + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, &gcc->apcs_clk_br_en1, QUPV3_WRAP0_CORE_2X_CLK_ENA); clock_enable_vote(&gcc->qup_wrap0_core_cbcr, diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c new file mode 100644 index 0000000000..016531bda3 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#define DSI_DMA_STREAM1 0x0 +#define DSI_EMBED_MODE1 0x1 +#define DSI_POWER_MODE2 0x1 +#define DSI_PACK_TYPE1 0x0 +#define DSI_VC1 0x0 +#define DSI_DT1 0x0 +#define DSI_WC1 0x0 +#define DSI_EOF_BLLP_PWR 0x9 +#define DSI_DMA_TRIGGER_SEL 0x4 + +#define DSI_EN 0x1 +#define DSI_CLKLN_EN 0x1 +#define DSI_VIDEO_EN 0x1 + +#define HS_TX_TO 0xEA60 +#define TIMER_RESOLUTION 0x4 + +static void mdss_dsi_host_init(int num_of_lanes) +{ + uint8_t dlnx_en; + uint32_t ctrl_mode = BIT(8) | BIT(0); /* Enable DSI and CLKlane. */ + + switch (num_of_lanes) { + default: + case 1: + dlnx_en = 1; + break; + + case 2: + dlnx_en = 3; + break; + + case 3: + dlnx_en = 7; + break; + + case 4: + dlnx_en = 0x0F; + break; + } + + /* + * Need to send pixel data before sending the ON commands + * so need to configure controller to VIDEO MODE. + */ + ctrl_mode |= BIT(1); + + write32(&dsi0->trig_ctrl, DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL); + write32(&dsi0->ctrl, dlnx_en << 4 | ctrl_mode); + write32(&dsi0->cmd_mode_dma_ctrl, + DSI_EMBED_MODE1 << 28 | DSI_POWER_MODE2 << 26 | + DSI_PACK_TYPE1 << 24 | DSI_VC1 << 22 | DSI_DT1 << 16 | DSI_WC1); +} + +static void mdss_dsi_reset(void) +{ + /* + * Disable DSI Controller, DSI lane states, + * DSI command-mode and DSI video-mode engines + */ + write32(&dsi0->ctrl, 0x0); + + /* DSI soft reset */ + write32(&dsi0->soft_reset, 0x1); + write32(&dsi0->soft_reset, 0x0); + + /* set hs timer count speed */ + write32(&dsi0->hs_timer_ctrl, HS_TX_TO | TIMER_RESOLUTION << 16); + + /* dma fifo reset */ + write32(&dsi0->tpg_dma_fifo_reset, 0x1); + write32(&dsi0->tpg_dma_fifo_reset, 0x0); +} + +void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) +{ + uint16_t dst_format; + uint8_t lane_en = 15; /* Enable 4 lanes by default */ + uint16_t hfp, hbp, vfp, vbp; + + switch (bpp) { + case 16: + dst_format = DSI_VIDEO_DST_FORMAT_RGB565; + break; + case 18: + dst_format = DSI_VIDEO_DST_FORMAT_RGB666; + break; + case 24: + default: + dst_format = DSI_VIDEO_DST_FORMAT_RGB888; + break; + } + + hfp = edid->mode.hso; + hbp = edid->mode.hbl - edid->mode.hso; + vfp = edid->mode.vso; + vbp = edid->mode.vbl - edid->mode.vso; + + mdss_dsi_clock_config(); + + write32(&dsi0->video_mode_active_h, + ((edid->mode.ha + hbp) << 16) | + hbp); + + write32(&dsi0->video_mode_active_v, + ((edid->mode.va + vbp) << 16) | (vbp)); + + write32(&dsi0->video_mode_active_total, + ((edid->mode.va + vfp + + vbp - 1) << 16) | + (edid->mode.ha + hfp + + hbp - 1)); + + write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16) | 0); + write32(&dsi0->video_mode_active_vsync, 0x0); + write32(&dsi0->video_mode_active_vsync_vpos, edid->mode.vspw << 16 | 0); + + write32(&dsi0->video_mode_ctrl, + DSI_EOF_BLLP_PWR << 12 | dst_format << 4); + + write32(&dsi0->hs_timer_ctrl, HS_TX_TO | TIMER_RESOLUTION << 16); + + write32(&dsi0->ctrl, lane_en << 4 | DSI_VIDEO_EN << 1 | DSI_EN | DSI_CLKLN_EN << 8); +} + +enum cb_err mdss_dsi_config(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp) +{ + mdss_dsi_reset(); + if ((mdss_dsi_phy_10nm_init(edid, num_of_lanes, bpp)) != 0) { + printk(BIOS_ERR, "dsi phy setup returned error\n"); + return CB_ERR; + } + + mdss_dsi_host_init(num_of_lanes); + + return CB_SUCCESS; +} + +void mdss_dsi_clock_config(void) +{ + /* Clock for AHI Bus Master, for DMA out from memory */ + write32(&dsi0->clk_ctrl, 0); + setbits32(&dsi0->clk_ctrl, DSI_AHBM_SCLK_ON | DSI_FORCE_ON_DYN_AHBM_HCLK); + + /* Clock for MDP/DSI, for DMA out from MDP */ + setbits32(&dsi0->clk_ctrl, DSI_FORCE_ON_DYN_AHBM_HCLK); + + /* Clock for rest of DSI */ + setbits32(&dsi0->clk_ctrl, DSI_AHBS_HCLK_ON | DSI_DSICLK_ON | + DSI_BYTECLK_ON | DSI_ESCCLK_ON); +} diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c new file mode 100644 index 0000000000..050a5d88f1 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -0,0 +1,765 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HAL_DSI_PHY_PLL_READY_TIMEOUT_MS 150 /* ~15 ms */ +#define HAL_DSI_PHY_REFGEN_TIMEOUT_MS 150 /* ~15 ms */ + +#define DSI_MAX_REFRESH_RATE 95 +#define DSI_MIN_REFRESH_RATE 15 + +#define HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 1000 + +#define S_DIV_ROUND_UP(n, d) \ + (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d))) + +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + +struct dsi_phy_divider_lut_entry_type { + uint16_t pll_post_div; + uint16_t phy_post_div; +}; + +/* PLL divider LUTs */ +static struct dsi_phy_divider_lut_entry_type pll_dividerlut_dphy[] = { +/* pll post div will always be power of 2 */ + { 2, 11 }, + { 4, 5 }, + { 2, 9 }, + { 8, 2 }, + { 1, 15 }, + { 2, 7 }, + { 1, 13 }, + { 4, 3 }, + { 1, 11 }, + { 2, 5 }, + { 1, 9 }, + { 8, 1 }, + { 1, 7 }, + { 2, 3 }, + { 1, 5 }, + { 4, 1 }, + { 1, 3 }, + { 2, 1 }, + { 1, 1 } +}; + +enum dsi_laneid_type { + DSI_LANEID_0 = 0, + DSI_LANEID_1, + DSI_LANEID_2, + DSI_LANEID_3, + DSI_LANEID_CLK, + DSI_LANEID_MAX, + DSI_LANEID_FORCE_32BIT = 0x7FFFFFFF +}; + +struct dsi_phy_configtype { + uint32_t desired_bitclk_freq; + uint32_t bits_per_pixel; + uint32_t num_data_lanes; + uint32_t pclk_divnumerator; + uint32_t pclk_divdenominator; + + /* pixel clk source select */ + uint32_t phy_post_div; + uint32_t pll_post_div; +}; + +static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent, + s32 min_result, bool even) +{ + s32 v; + + v = (tmax - tmin) * percent; + v = S_DIV_ROUND_UP(v, 100) + tmin; + if (even && (v & 0x1)) + return MAX(min_result, v - 1); + + return MAX(min_result, v); +} + +static void mdss_dsi_phy_reset(void) +{ + write32(&dsi0_phy->phy_cmn_ctrl1, 0x40); + udelay(100); + write32(&dsi0_phy->phy_cmn_ctrl1, 0x0); +} + +static void mdss_dsi_power_down(void) +{ + /* power up DIGTOP & PLL */ + write32(&dsi0_phy->phy_cmn_ctrl0, 0x60); + + /* Disable PLL */ + write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x0); + + /* Resync re-time FIFO OFF*/ + write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x0); +} + +static void mdss_dsi_phy_setup_lanephy(enum dsi_laneid_type lane) +{ + uint32_t reg_val = 0; + uint32_t lprx_ctrl = 0; + uint32_t hstx_strength = 0x88; + uint32_t data_strength_lp_n = 0x5; + uint32_t data_strength_lp_p = 0x5; + uint32_t pemph_bottom = 0; + uint32_t pemph_top = 0; + uint32_t strength_override = 0; + uint32_t clk_lane = 0; + + if (lane == DSI_LANEID_CLK) + clk_lane = 1; + else + clk_lane = 0; + + if (lane == DSI_LANEID_0) + lprx_ctrl = 3; + + /* + * DSIPHY_STR_LP_N + * DSIPHY_STR_LP_P + */ + reg_val = ((data_strength_lp_n << 0x4) & 0xf0) | + (data_strength_lp_p & 0x0f); + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lptx_str_ctrl, reg_val); + + /* + * DSIPHY_LPRX_EN + * DSIPHY_CDRX_EN + * Transition from 0 to 1 for DLN0-3 CLKLN stays 0 + */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, 0x0); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, lprx_ctrl); + + /* Pin Swap */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_pin_swap, 0x0); + + /* + * DSIPHY_HSTX_STR_HSTOP + * DSIPHY_HSTX_STR_HSBOT + */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_hstx_str_ctrl, hstx_strength); + + /* PGM Delay */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[0], 0x0); + + /* DLN0_CFG1 */ + reg_val = (strength_override << 0x5) & 0x20; + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[1], reg_val); + + /* DLN0_CFG2 */ + reg_val = ((pemph_bottom << 0x04) & 0xf0) | + (pemph_top & 0x0f); + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[2], reg_val); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_top_ctrl, 0x0); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_bot_ctrl, 0x0); + + /* + * DSIPHY_LPRX_DLY + * IS_CKLANE + */ + reg_val = (clk_lane << 0x07) & 0x80; + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[3], reg_val); + + reg_val = 0; + if (lane == DSI_LANEID_CLK) + reg_val = 1; + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_tx_dctrl, reg_val); +} + +static void mdss_dsi_calculate_phy_timings(struct msm_dsi_phy_ctrl *timing, + struct dsi_phy_configtype *phy_cfg) +{ + const unsigned long bit_rate = phy_cfg->desired_bitclk_freq; + s32 ui, ui_x8; + s32 tmax, tmin; + s32 pcnt0 = 50; + s32 pcnt1 = 50; + s32 pcnt2 = 10; + s32 pcnt3 = 30; + s32 pcnt4 = 10; + s32 pcnt5 = 2; + s32 coeff = 1000; /* Precision, should avoid overflow */ + s32 hb_en, hb_en_ckln; + s32 temp; + + if (!bit_rate) + return; + + hb_en = 0; + timing->half_byte_clk_en = 0; + hb_en_ckln = 0; + + ui = mult_frac(1000000, coeff, bit_rate / 1000); + ui_x8 = ui << 3; + + temp = S_DIV_ROUND_UP(38 * coeff, ui_x8); + tmin = MAX(temp, 0); + temp = (95 * coeff) / ui_x8; + tmax = MAX(temp, 0); + timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); + + temp = 300 * coeff - (timing->clk_prepare << 3) * ui; + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = (tmin > 255) ? 511 : 255; + timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); + + tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8); + temp = 105 * coeff + 12 * ui - 20 * coeff; + tmax = (temp + 3 * ui) / ui_x8; + timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); + + temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8); + tmin = MAX(temp, 0); + temp = (85 * coeff + 6 * ui) / ui_x8; + tmax = MAX(temp, 0); + timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); + + temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 255; + timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); + + tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; + temp = 105 * coeff + 12 * ui - 20 * coeff; + tmax = (temp / ui_x8) - 1; + timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); + + temp = 50 * coeff + ((hb_en << 2) - 8) * ui; + timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); + + tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; + tmax = 255; + timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); + + temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; + timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); + + temp = 60 * coeff + 52 * ui - 43 * ui; + tmin = DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 63; + timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false); + + temp = 8 * ui + (timing->clk_prepare << 3) * ui; + temp += (((timing->clk_zero + 3) << 3) + 11) * ui; + temp += hb_en_ckln ? (((timing->hs_rqst << 3) + 4) * ui) : + (((timing->hs_rqst << 3) + 8) * ui); + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 63; + if (tmin > tmax) { + temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false); + timing->clk_pre = temp >> 1; + timing->clk_pre_inc_by_2 = 1; + } else { + timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false); + timing->clk_pre_inc_by_2 = 0; + } + + timing->ta_go = 3; + timing->ta_sure = 0; + timing->ta_get = 4; + + printk(BIOS_INFO, "PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", + timing->clk_pre, timing->clk_post, + timing->clk_pre_inc_by_2, timing->clk_zero, + timing->clk_trail, timing->clk_prepare, timing->hs_exit, + timing->hs_zero, timing->hs_prepare, timing->hs_trail, + timing->hs_rqst); +} + +static enum cb_err mdss_dsi_phy_timings(struct msm_dsi_phy_ctrl *phy_timings) +{ + uint32_t reg_val = 0; + + /* + * Step 4 Common block including GlobalTiming Parameters + * BYTECLK_SEL + */ + reg_val = (0x02 << 3) & 0x18; + write32(&dsi0_phy->phy_cmn_glbl_ctrl, reg_val); + + /* VREG_CTRL */ + write32(&dsi0_phy->phy_cmn_vreg_ctrl, 0x59); + + /*HALFBYTECLK_EN*/ + write32(&dsi0_phy->phy_cmn_timing_ctrl[0], phy_timings->half_byte_clk_en); + + /* T_CLK_ZERO */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[1], phy_timings->clk_zero); + + /* T_CLK_PREPARE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[2], phy_timings->clk_prepare); + + /* T_CLK_TRAIL */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[3], phy_timings->clk_trail); + + /* T_HS_EXIT */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[4], phy_timings->hs_exit); + + /* T_HS_ZERO */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[5], phy_timings->hs_zero); + + /* T_HS_PREPARE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[6], phy_timings->hs_prepare); + + /* T_HS_TRAIL */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[7], phy_timings->hs_trail); + + /* T_HS_RQST */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[8], phy_timings->hs_rqst); + + /* T_TA_GO & T_TA_SURE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[9], + phy_timings->ta_sure << 3 | phy_timings->ta_go); + + /* T_TA_GET */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[10], phy_timings->ta_get); + + /*DSIPHY_TRIG3_CMD*/ + write32(&dsi0_phy->phy_cmn_timing_ctrl[11], 0x0); + + /* DSI clock out timing ctrl T_CLK_PRE & T_CLK_POST*/ + reg_val = ((phy_timings->clk_post << 8) | phy_timings->clk_pre); + write32(&dsi0->clkout_timing_ctrl, reg_val); + + /* DCTRL */ + write32(&dsi0_phy->phy_cmn_ctrl2, 0x40); + + return CB_SUCCESS; +} + +static enum cb_err dsi_phy_waitforrefgen(void) +{ + uint32_t timeout = HAL_DSI_PHY_REFGEN_TIMEOUT_MS; + uint32_t refgen = 0; + enum cb_err ret = CB_SUCCESS; + + while (!refgen) { + refgen = (read32(&dsi0_phy->phy_cmn_phy_status) & 0x1); + if (!refgen) { + udelay(100); + timeout--; + if (!timeout) { + /* timeout while polling the lock status */ + ret = CB_ERR; + break; + } + } + } + + return ret; +} + +static enum cb_err mdss_dsi_phy_commit(void) +{ + enum cb_err ret = CB_SUCCESS; + + ret = dsi_phy_waitforrefgen(); + if (ret) { + printk(BIOS_ERR, "%s: waitforrefgen error\n", __func__); + return ret; + } + + mdss_dsi_power_down(); + + /* Remove PLL, DIG and all lanes from pwrdn */ + write32(&dsi0_phy->phy_cmn_ctrl0, 0x7F); + + /* Lane enable */ + write32(&dsi0_phy->phy_cmn_dsi_lane_ctrl0, 0x1F); + + mdss_dsi_phy_setup_lanephy(DSI_LANEID_0); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_1); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_2); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_3); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_CLK); + + return ret; +} + +static void mdss_dsi_phy_setup(void) +{ + /* First reset phy */ + mdss_dsi_phy_reset(); + + /* commit phy settings */ + mdss_dsi_phy_commit(); +} + +static void dsi_phy_resync_fifo(void) +{ + /* Resync FIFO*/ + write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x1); +} + +static void dsi_phy_pll_global_clk_enable(bool enable) +{ + uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1); + uint32_t clk_enable = 0; + + /* Set CLK_EN */ + if (enable) + clk_enable = 1; + + clk_cfg &= ~0x20; + clk_cfg |= ((clk_enable << 0x5) & 0x20); + + /* clk cfg1 */ + write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg); +} + +static enum cb_err dsi_phy_pll_lock_detect(void) +{ + enum cb_err ret = CB_SUCCESS; + + /* Enable PLL */ + write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x1); + + /* Wait for Lock */ + if (!wait_us(15000, read32(&phy_pll_qlink->pll_common_status_one) & 0x1)) { + /* timeout while polling the lock status */ + ret = CB_ERR; + printk(BIOS_ERR, "dsi pll lock detect timedout, error.\n"); + } + + return ret; +} + +static void dsi_phy_toggle_dln3_tx_dctrl(void) +{ + uint32_t reg_val = 0; + + reg_val = read32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl); + + /* clear bit 0 and keep all other bits including bit 2 */ + reg_val &= ~0x01; + + /* toggle bit 0 */ + write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, (0x01 | reg_val)); + write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, 0x4); +} + +static void dsi_phy_pll_set_source(void) +{ + uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1); + uint32_t dsi_clksel = 1; + + clk_cfg &= ~0x03; + clk_cfg |= ((dsi_clksel) & 0x3); + + /* clk cfg1 */ + write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg); +} + +static void dsi_phy_pll_bias_enable(bool enable) +{ + uint32_t reg_val = 0; + + /* Set BIAS_EN_MUX, BIAS_EN */ + if (enable) + reg_val = (0x01 << 6) | (0x01 << 7); + + /* pll system muxes */ + write32(&phy_pll_qlink->pll_system_muxes, reg_val); + +} + +static void dsi_phy_mnd_divider(struct dsi_phy_configtype *phy_cfg) +{ + uint32_t m_val = 1; + uint32_t n_val = 1; + + if (phy_cfg->bits_per_pixel == 18) { + switch (phy_cfg->num_data_lanes) { + case 1: + case 2: + m_val = 2; + n_val = 3; + break; + case 4: + m_val = 4; + n_val = 9; + break; + default: + break; + } + } else if ((phy_cfg->bits_per_pixel == 16) && + (phy_cfg->num_data_lanes == 3)) { + m_val = 3; + n_val = 8; + } else if ((phy_cfg->bits_per_pixel == 30) && + (phy_cfg->num_data_lanes == 4)) { + m_val = 2; + n_val = 3; + } + + /*Save M/N info */ + phy_cfg->pclk_divnumerator = m_val; + phy_cfg->pclk_divdenominator = n_val; +} + +static uint32_t dsi_phy_dsiclk_divider(struct dsi_phy_configtype *phy_cfg) +{ + uint32_t m_val = phy_cfg->pclk_divnumerator; + uint32_t n_val = phy_cfg->pclk_divdenominator; + uint32_t div_ctrl = 0; + + div_ctrl = (m_val * phy_cfg->bits_per_pixel) / + (n_val * phy_cfg->num_data_lanes * 2); + + return div_ctrl; +} + + +static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg) +{ + bool div_found = false; + uint32_t m_val = 1; + uint32_t n_val = 1; + uint32_t div_ctrl = 0; + uint32_t reg_val = 0; + uint32_t pll_post_div = 0; + uint32_t phy_post_div = 0; + uint64_t vco_freq_hz = 0; + uint64_t fval = 0; + uint64_t pll_output_freq_hz; + uint64_t desired_bitclk_hz; + uint64_t min_vco_freq_hz = 0; + uint32_t lut_max; + int i; + struct dsi_phy_divider_lut_entry_type *lut; + + /* use 1000Mhz */ + min_vco_freq_hz = (HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 * 1000000); + + dsi_phy_mnd_divider(phy_cfg); + + m_val = phy_cfg->pclk_divnumerator; + n_val = phy_cfg->pclk_divdenominator; + + /* Desired clock in MHz */ + desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq; + + /* D Phy */ + lut = pll_dividerlut_dphy; + lut_max = sizeof(pll_dividerlut_dphy) / sizeof(*lut); + lut += (lut_max - 1); + + /* PLL Post Div - from LUT + * Check the LUT in reverse order + */ + for (i = lut_max - 1; i >= 0; i--, lut--) { + fval = (uint64_t)lut->phy_post_div * + (uint64_t)lut->pll_post_div; + if (fval) { + if ((desired_bitclk_hz * fval) > min_vco_freq_hz) { + /* Range found */ + pll_post_div = lut->pll_post_div; + phy_post_div = lut->phy_post_div; + div_found = true; + break; + } + } + } + + if (div_found) { + phy_cfg->pll_post_div = pll_post_div; + phy_cfg->phy_post_div = phy_post_div; + + /*div_ctrl_7_4 */ + div_ctrl = dsi_phy_dsiclk_divider(phy_cfg); + + /* DIV_CTRL_7_4 DIV_CTRL_3_0 + * (DIV_CTRL_3_0 = PHY post divider ratio) + */ + reg_val = (div_ctrl << 0x04) & 0xf0; + reg_val |= (phy_post_div & 0x0f); + write32(&dsi0_phy->phy_cmn_clk_cfg0, reg_val); + + /* PLL output frequency = desired_bitclk_hz * phy_post_div */ + pll_output_freq_hz = desired_bitclk_hz * phy_post_div; + + /* VCO output freq*/ + vco_freq_hz = pll_output_freq_hz * pll_post_div; + + } + + return (unsigned long)vco_freq_hz; +} + +static void dsi_phy_pll_outputdiv_rate(struct dsi_phy_configtype *pll_cfg) +{ + /* Output divider */ + uint32_t pll_post_div = 0; + uint32_t reg_val = 0; + + pll_post_div = log2(pll_cfg->pll_post_div); + reg_val = pll_post_div & 0x3; + write32(&phy_pll_qlink->pll_outdiv_rate, reg_val); +} + +static enum cb_err dsi_phy_pll_calcandcommit(struct dsi_phy_configtype *phy_cfg) +{ + unsigned long vco_freq_hz; + enum cb_err ret = CB_SUCCESS; + + /* validate input parameters */ + if (!phy_cfg) { + return CB_ERR; + } else if ((phy_cfg->bits_per_pixel != 16) && + (phy_cfg->bits_per_pixel != 18) && + (phy_cfg->bits_per_pixel != 24)) { + /* Unsupported pixel bit depth */ + return CB_ERR; + } else if ((phy_cfg->num_data_lanes == 0) || + (phy_cfg->num_data_lanes > 4)) { + /* Illegal number of DSI data lanes */ + return CB_ERR; + } + + vco_freq_hz = dsi_phy_calc_clk_divider(phy_cfg); + if (!vco_freq_hz) { + /* bitclock too low - unsupported */ + printk(BIOS_ERR, "vco_freq_hz is 0, unsupported\n"); + return CB_ERR; + } + + /* Enable PLL bias */ + dsi_phy_pll_bias_enable(true); + + /* Set byte clk source */ + dsi_phy_pll_set_source(); + + dsi_phy_pll_outputdiv_rate(phy_cfg); + dsi_phy_pll_vco_10nm_set_rate(vco_freq_hz); + dsi_phy_toggle_dln3_tx_dctrl(); + + /* Steps 6,7 Start PLL & Lock */ + if (ret == CB_SUCCESS) + ret = dsi_phy_pll_lock_detect(); + + /* Step 8 - Resync Data Paths */ + if (ret == CB_SUCCESS) { + /* Global clock enable */ + dsi_phy_pll_global_clk_enable(true); + + /* Resync FIFOs */ + dsi_phy_resync_fifo(); + } + + return ret; +} + +static uint32_t dsi_calc_desired_bitclk(struct edid *edid, uint32_t num_lines, uint32_t bpp) +{ + uint64_t desired_bclk = 0; + uint32_t pixel_clock_in_hz; + + pixel_clock_in_hz = edid->mode.pixel_clock * KHz; + if (num_lines) { + desired_bclk = pixel_clock_in_hz * (uint64_t)bpp; + desired_bclk = desired_bclk/(uint64_t)(num_lines); + } + + printk(BIOS_INFO, "Desired bitclock: %uHz\n", (uint32_t)desired_bclk); + return (uint32_t)desired_bclk; +} + +static enum cb_err mdss_dsi_phy_pll_setup(struct edid *edid, + uint32_t num_of_lanes, uint32_t bpp) +{ + struct dsi_phy_configtype phy_cfg; + struct msm_dsi_phy_ctrl phy_timings; + enum cb_err ret; + + /* Setup the PhyStructure */ + memset(&phy_cfg, 0, sizeof(struct dsi_phy_configtype)); + memset(&phy_timings, 0, sizeof(struct msm_dsi_phy_ctrl)); + + phy_cfg.bits_per_pixel = bpp; + phy_cfg.num_data_lanes = num_of_lanes; + + /* desired DSI PLL bit clk freq in Hz */ + phy_cfg.desired_bitclk_freq = dsi_calc_desired_bitclk(edid, num_of_lanes, bpp); + + ret = dsi_phy_pll_calcandcommit(&phy_cfg); + if (ret) + return ret; + mdss_dsi_calculate_phy_timings(&phy_timings, &phy_cfg); + ret = mdss_dsi_phy_timings(&phy_timings); + + return ret; +} + +static enum cb_err enable_dsi_clk(void) +{ + enum cb_err ret; + uint32_t i = 0; + struct mdp_external_clock_entry clks[] = { + {.clk_type = MDSS_CLK_ESC0, .clk_secondary_source = 1}, + {.clk_type = MDSS_CLK_PCLK0, .clk_source = 1}, + {.clk_type = MDSS_CLK_BYTE0, .clk_source = 1}, + {.clk_type = MDSS_CLK_BYTE0_INTF, .clk_source = 1, + .clk_div = 2, .source_div = 2}, + }; + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + /* Set Ext Source */ + ret = mdss_clock_configure(clks[i].clk_type, + clks[i].clk_source, + clks[i].clk_div, + clks[i].clk_pll_m, + clks[i].clk_pll_n, + clks[i].clk_pll_2d); + if (ret) { + printk(BIOS_ERR, + "mdss_clock_configure failed for %u\n", + clks[i].clk_type); + return CB_ERR; + } + + ret = mdss_clock_enable(clks[i].clk_type); + if (ret) { + printk(BIOS_ERR, + "mdss_clock_enable failed for %u\n", + clks[i].clk_type); + return CB_ERR; + } + } + + return ret; +} + +enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp) +{ + enum cb_err ret; + + /* Phy set up */ + mdss_dsi_phy_setup(); + ret = mdss_dsi_phy_pll_setup(edid, num_of_lanes, bpp); + enable_dsi_clk(); + + return ret; +} diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c new file mode 100644 index 0000000000..b01fc2e436 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VCO_DELAY_USEC 1 + +/* Bit definition of SSC control registers */ +#define SSC_CENTER BIT(0) +#define SSC_EN BIT(1) + +struct dsi_pll_regs { + u32 pll_prop_gain_rate; + u32 decimal_div_start; + u32 frac_div_start_low; + u32 frac_div_start_mid; + u32 frac_div_start_high; + u32 pll_clock_inverters; +}; + +static void dsi_pll_init_val(void) +{ + write32(&phy_pll_qlink->pll_core_input_override, 0x10); + write32(&phy_pll_qlink->pll_int_loop_settings, 0x3f); + write32(&phy_pll_qlink->pll_int_loop_settings_two, 0x0); + write32(&phy_pll_qlink->pll_analog_ctrls_four, 0x0); + write32(&phy_pll_qlink->pll_int_loop_ctrls, 0x80); + write32(&phy_pll_qlink->pll_freq_update_ctrl_overrides, 0x0); + write32(&phy_pll_qlink->pll_band_sel_cal_timer_low, 0x0); + write32(&phy_pll_qlink->pll_band_sel_cal_timer_high, 0x02); + write32(&phy_pll_qlink->pll_band_sel_cal_settings, 0x82); + write32(&phy_pll_qlink->pll_band_sel_min, 0x00); + write32(&phy_pll_qlink->pll_band_sel_max, 0xff); + write32(&phy_pll_qlink->pll_band_sel_pfilt, 0x00); + write32(&phy_pll_qlink->pll_band_sel_ifilt, 0x00); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_two, 0x25); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_four, 0x4f); + write32(&phy_pll_qlink->pll_band_sel_icode_high, 0x0a); + write32(&phy_pll_qlink->pll_band_sel_icode_low, 0x0); + write32(&phy_pll_qlink->pll_pll_gain, 0x42); + write32(&phy_pll_qlink->pll_icode_low, 0x00); + write32(&phy_pll_qlink->pll_icode_high, 0x00); + write32(&phy_pll_qlink->pll_lockdet, 0x30); + write32(&phy_pll_qlink->pll_fastlock_ctrl, 0x04); + write32(&phy_pll_qlink->pll_pass_out_override_one, 0x00); + write32(&phy_pll_qlink->pll_pass_out_override_two, 0x00); + write32(&phy_pll_qlink->pll_rate_change, 0x01); + write32(&phy_pll_qlink->pll_digital_timers, 0x08); + write32(&phy_pll_qlink->pll_dec_frac_muxes, 0x00); + write32(&phy_pll_qlink->pll_mash_ctrl, 0x03); + write32(&phy_pll_qlink->pll_ssc_mux_ctrl, 0x0); + write32(&phy_pll_qlink->pll_ssc_ctrl, 0x0); + write32(&phy_pll_qlink->pll_pll_fastlock_en_band, 0x03); + write32(&phy_pll_qlink->pll_freq_tune_accum_init_mux, 0x0); + write32(&phy_pll_qlink->pll_lock_min_delay, 0x19); + write32(&phy_pll_qlink->pll_spare_and_jpc_overrides, 0x0); + write32(&phy_pll_qlink->pll_bias_ctrl_1, 0x40); + write32(&phy_pll_qlink->pll_bias_ctrl_2, 0x20); + write32(&phy_pll_qlink->pll_alog_obsv_bus_ctrl_1, 0x0); +} + +static void dsi_pll_calc_dec_frac(struct dsi_pll_regs *regs, + unsigned long rate) +{ + u32 frac_bits = 18; + u64 pll_freq; + u64 divider; + u64 dec, dec_multiple; + u32 frac; + u64 multiplier; + + pll_freq = rate; + divider = SRC_XO_HZ * 2; + + multiplier = 1 << frac_bits; + dec_multiple = (pll_freq * multiplier) / divider; + frac = dec_multiple % multiplier; + + dec = dec_multiple / multiplier; + if (pll_freq <= 1900UL * MHz) + regs->pll_prop_gain_rate = 8; + else if (pll_freq <= 3000UL * MHz) + regs->pll_prop_gain_rate = 10; + else + regs->pll_prop_gain_rate = 12; + + if (pll_freq < 1100UL * MHz) + regs->pll_clock_inverters = 8; + else + regs->pll_clock_inverters = 0; + + regs->decimal_div_start = dec; + regs->frac_div_start_low = (frac & 0xff); + regs->frac_div_start_mid = (frac & 0xff00) >> 8; + regs->frac_div_start_high = (frac & 0x30000) >> 16; +} + +static void dsi_pll_commit(struct dsi_pll_regs *reg) +{ + write32(&phy_pll_qlink->pll_core_input_override, 0x12); + write32(&phy_pll_qlink->pll_decimal_div_start_1, reg->decimal_div_start); + write32(&phy_pll_qlink->pll_frac_div_start_low1, reg->frac_div_start_low); + write32(&phy_pll_qlink->pll_frac_div_start_mid1, reg->frac_div_start_mid); + write32(&phy_pll_qlink->pll_frac_div_start_high1, reg->frac_div_start_high); + write32(&phy_pll_qlink->pll_lockdet_rate[0], 0x40); + write32(&phy_pll_qlink->pll_lock_delay, 0x06); + write32(&phy_pll_qlink->pll_cmode, 0x10); + write32(&phy_pll_qlink->pll_clock_inverters, reg->pll_clock_inverters); +} + +static void dsi_pll_config_hzindep_reg(struct dsi_pll_regs *reg) +{ + write32(&phy_pll_qlink->pll_analog_ctrls_one, 0x80); + write32(&phy_pll_qlink->pll_analog_ctrls_two, 0x03); + write32(&phy_pll_qlink->pll_analog_ctrls_three, 0x00); + write32(&phy_pll_qlink->pll_dsm_divider, 0x00); + write32(&phy_pll_qlink->pll_feedback_divider, 0x4e); + write32(&phy_pll_qlink->pll_cal_settings, 0x40); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_three, 0xba); + write32(&phy_pll_qlink->pll_freq_detect_settings_one, 0x0c); + write32(&phy_pll_qlink->pll_outdiv, 0x00); + write32(&phy_pll_qlink->pll_core_override, 0x00); + write32(&phy_pll_qlink->pll_digital_timers_two, 0x08); + write32(&phy_pll_qlink->pll_prop_gain_rate[0], reg->pll_prop_gain_rate); + write32(&phy_pll_qlink->pll_band_set_rate[0], 0xc0); + write32(&phy_pll_qlink->pll_gain_ifilt_band[0], 0xfa); + write32(&phy_pll_qlink->pll_fl_int_gain_pfilt_band[0], 0x4c); + write32(&phy_pll_qlink->pll_lock_override, 0x80); + write32(&phy_pll_qlink->pll_pfilt, 0x29); + write32(&phy_pll_qlink->pll_ifilt, 0x3f); +} + +void dsi_phy_pll_vco_10nm_set_rate(unsigned long rate) +{ + struct dsi_pll_regs regs; + + dsi_pll_init_val(); + dsi_pll_calc_dec_frac(®s, rate); + dsi_pll_commit(®s); + dsi_pll_config_hzindep_reg(®s); +} diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c new file mode 100644 index 0000000000..2d6bf6fcd3 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define MDSS_MDP_MAX_PREFILL_FETCH 25 + +static void mdss_source_pipe_config(struct edid *edid) +{ + uint32_t img_size, out_size, stride; + uint32_t fb_off = 0; + uint32_t flip_bits = 0; + uint32_t src_xy = 0; + uint32_t dst_xy = 0; + + /* write active region size*/ + img_size = (edid->mode.va << 16) | edid->mode.ha; + out_size = img_size; + stride = (edid->mode.ha * edid->framebuffer_bits_per_pixel/8); + + if (!fb_off) { /* left */ + dst_xy = (edid->mode.vborder << 16) | edid->mode.hborder; + src_xy = dst_xy; + } else { /* right */ + dst_xy = (edid->mode.vborder << 16); + src_xy = (edid->mode.vborder << 16) | fb_off; + } + + printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", + __func__, out_size, fb_off, src_xy, dst_xy); + + write32(&mdp_sspp->sspp_src_ystride0, stride); + write32(&mdp_sspp->sspp_src_size, out_size); + write32(&mdp_sspp->sspp_out_size, out_size); + write32(&mdp_sspp->sspp_src_xy, src_xy); + write32(&mdp_sspp->sspp_out_xy, dst_xy); + + /* Tight Packing 4bpp Alpha 8-bit A R B G */ + write32(&mdp_sspp->sspp_src_format, 0x000236ff); + write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001); + + flip_bits |= BIT(31); + write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size); + write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size); + write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size); + write32(&mdp_sspp->sspp_src_op_mode, flip_bits); +} + +static void mdss_vbif_setup(void) +{ + write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333); + write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333); +} + +static void mdss_intf_tg_setup(struct edid *edid) +{ + uint32_t hsync_period, vsync_period; + uint32_t hsync_start_x, hsync_end_x; + uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; + + hsync_period = edid->mode.ha + edid->mode.hbl; + vsync_period = edid->mode.va + edid->mode.vbl; + hsync_start_x = edid->mode.hbl - edid->mode.hso; + hsync_end_x = hsync_period - edid->mode.hso - 1; + display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; + display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; + hsync_ctl = (hsync_period << 16) | edid->mode.hspw; + display_hctl = (hsync_end_x << 16) | hsync_start_x; + + write32(&mdp_intf->intf_hsync_ctl, hsync_ctl); + write32(&mdp_intf->intf_vysnc_period_f0, + vsync_period * hsync_period); + write32(&mdp_intf->intf_vysnc_pulse_width_f0, + edid->mode.vspw * hsync_period); + write32(&mdp_intf->intf_disp_hctl, display_hctl); + write32(&mdp_intf->intf_disp_v_start_f0, display_vstart); + write32(&mdp_intf->intf_disp_v_end_f0, display_vend); + write32(&mdp_intf->intf_underflow_color, 0x00); + write32(&mdp_intf->intf_panel_format, 0x2100); +} + +static void mdss_intf_fetch_start_config(struct edid *edid) +{ + uint32_t v_total, h_total, fetch_start, vfp_start; + uint32_t prefetch_avail, prefetch_needed; + uint32_t fetch_enable = BIT(31); + + /* + * MDP programmable fetch is for MDP with rev >= 1.05. + * Programmable fetch is not needed if vertical back porch + * plus vertical puls width is >= 25. + */ + if ((edid->mode.vbl - edid->mode.vso) >= MDSS_MDP_MAX_PREFILL_FETCH) + return; + + /* + * Fetch should always be outside the active lines. If the fetching + * is programmed within active region, hardware behavior is unknown. + */ + v_total = edid->mode.va + edid->mode.vbl; + h_total = edid->mode.ha + edid->mode.hbl; + vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso; + prefetch_avail = v_total - vfp_start; + prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - edid->mode.vbl + edid->mode.vso; + + /* + * In some cases, vertical front porch is too high. In such cases limit + * the mdp fetch lines as the last (25 - vbp - vpw) lines of + * vertical front porch. + */ + if (prefetch_avail > prefetch_needed) + prefetch_avail = prefetch_needed; + + fetch_start = (v_total - prefetch_avail) * h_total + h_total + 1; + write32(&mdp_intf->intf_prof_fetch_start, fetch_start); + write32(&mdp_intf->intf_config, fetch_enable); +} + +static void mdss_layer_mixer_setup(struct edid *edid) +{ + uint32_t mdp_rgb_size; + uint32_t left_staging_level; + + /* write active region size*/ + mdp_rgb_size = (edid->mode.va << 16) | edid->mode.ha; + + write32(&mdp_layer_mixer->layer_out_size, mdp_rgb_size); + write32(&mdp_layer_mixer->layer_op_mode, 0x0); + for (int i = 0; i < 6; i++) { + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100); + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000); + } + + /* Enable border fill */ + left_staging_level = BIT(24); + left_staging_level |= BIT(1); + + /* Base layer for layer mixer 0 */ + write32(&mdp_ctl->ctl_layer0, left_staging_level); +} + +static void mdss_vbif_qos_remapper_setup(void) +{ + /* + * VBIF remapper registers are used for translating internal display hardware + * priority level (from 0 to 7) into system fabric priority level. + * These remapper settings are defined for all the clients which corresponds + * to the xin clients connected to SSPP on VBIF. + */ + write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003); + write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113); + write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224); + write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334); + write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445); + write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776); + write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003); + write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113); + write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224); + write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334); + write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445); + write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776); +} + +void mdp_dsi_video_config(struct edid *edid) +{ + mdss_intf_tg_setup(edid); + mdss_intf_fetch_start_config(edid); + mdss_vbif_setup(); + mdss_vbif_qos_remapper_setup(); + mdss_source_pipe_config(edid); + mdss_layer_mixer_setup(edid); + + /* Select Video Mode Interface */ + write32(&mdp_ctl->ctl_top, 0x0); + + /* PPB0 to INTF1 */ + write32(&mdp_ctl->ctl_intf_active, BIT(1)); + write32(&mdp_intf->intf_mux, 0x0F0000); +} + +void mdp_dsi_video_on(void) +{ + uint32_t ctl0_reg_val; + + ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF; + write32(&mdp_ctl->ctl_intf_flush, 0x2); + write32(&mdp_ctl->ctl_flush, ctl0_reg_val); +} diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index 51d9135ffd..67204e87e7 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include -#include #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 2b65e99396..832ef42968 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -3,7 +3,6 @@ #ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ #define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ - #define AOSS_CC_BASE 0x0C2A0000 #define GCC_BASE 0x00100000 #define QSPI_BASE 0x088DC000 @@ -12,6 +11,7 @@ #define TLMM_WEST_TILE_BASE 0x03500000 #define SILVER_PLL_BASE 0x18280000 #define L3_PLL_BASE 0x18284000 +#define DISP_CC_BASE 0x0AF00000 /* * QUP SERIAL ENGINE BASE ADDRESSES diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index d202605327..b303efefc1 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -20,7 +20,6 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) -#define QUPV3_UART_SRC_HZ 7372800 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 @@ -29,10 +28,11 @@ #define AOP_RESET_SHFT 0 #define RCG_MODE_DUAL_EDGE 2 +#define WDOG_RESET_BIT_MASK 1 + #define SCALE_FREQ_SHFT 11 struct sc7180_clock { - u32 cbcr; u32 rcg_cmd; u32 rcg_cfg; }; @@ -58,6 +58,7 @@ struct sc7180_dfsr_clock { }; struct sc7180_qupv3_clock { + u32 cbcr; struct sc7180_mnd_clock mnd_clk; struct sc7180_dfsr_clock dfsr_clk; }; @@ -85,6 +86,7 @@ struct sc7180_gcc { u32 qup_wrap0_s_ahb_cbcr; u32 qup_wrap0_core_cbcr; u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; struct sc7180_clock qup_wrap0_core_2x; u8 _res2[0x17030 - 0x17020]; struct sc7180_qupv3_clock qup_wrap0_s[6]; @@ -102,6 +104,7 @@ struct sc7180_gcc { u8 _res6[0x4b000 - 0x26004]; u32 qspi_bcr; u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; struct sc7180_clock qspi_core; u8 _res7[0x50000 - 0x4b014]; u32 usb3_phy_prim_bcr; @@ -124,9 +127,40 @@ check_member(sc7180_gcc, usb3_phy_prim_bcr, 0x50000); check_member(sc7180_gcc, apcs_clk_br_en1, 0x52008); struct sc7180_aoss { - u8 _res[0x5002c]; + u8 _res0[0x50020]; + u32 aoss_cc_reset_status; + u8 _res1[0x5002C - 0x50024]; u32 aoss_cc_apcs_misc; }; +check_member(sc7180_aoss, aoss_cc_reset_status, 0x50020); +check_member(sc7180_aoss, aoss_cc_apcs_misc, 0x5002C); + +struct sc7180_disp_cc { + u8 _res0[0x2004]; + u32 pclk0_cbcr; + u8 _res1[0x2028 - 0x2008]; + u32 byte0_cbcr; + u32 byte0_intf_cbcr; + u8 _res2[0x2038 - 0x2030]; + u32 esc0_cbcr; + u8 _res3[0x2098 - 0x203C]; + struct sc7180_mnd_clock pclk0; + u8 _res4[0x2110 - 0x20AC]; + struct sc7180_mnd_clock byte0; + u8 _res5[0x2148 - 0x2124]; + struct sc7180_mnd_clock esc0; + u8 _res6[0x10000 - 0x215C]; +}; +check_member(sc7180_disp_cc, byte0_cbcr, 0x2028); +check_member(sc7180_disp_cc, esc0_cbcr, 0x2038); + +enum mdss_clock { + MDSS_CLK_ESC0 = 0, + MDSS_CLK_PCLK0, + MDSS_CLK_BYTE0, + MDSS_CLK_BYTE0_INTF, + MDSS_CLK_COUNT +}; enum clk_ctl_gpll_user_ctl { CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, @@ -202,12 +236,6 @@ struct clock_config { uint16_t d_2; }; -struct mdss_clock_config { - const char *clk_name; - uintptr_t rcgr; - uintptr_t cbcr; -}; - /* CPU PLL */ #define L_VAL_1516P8MHz 0x4F #define L_VAL_1209P6MHz 0x3F @@ -265,6 +293,7 @@ static struct sc7180_gcc *const gcc = (void *)GCC_BASE; static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; static struct sc7180_apss_clock *const apss_silver = (void *)SILVER_PLL_BASE; static struct sc7180_apss_clock *const apss_l3 = (void *)L3_PLL_BASE; +static struct sc7180_disp_cc *const mdss = (void *)DISP_CC_BASE; void clock_init(void); void clock_reset_aop(void); @@ -273,5 +302,8 @@ int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); +int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, + uint32_t half_divider, uint32_t m, uint32_t n, uint32_t d); +int mdss_clock_enable(enum mdss_clock clk_type); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h b/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h new file mode 100644 index 0000000000..a81c66cbfe --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_RESOURCES_H_ +#define _SOC_DISPLAY_RESOURCES_H_ + +#include + +#define MDP_MAX_CLOCK_NAME 30 + +/* MDP External Clocks Entry */ +struct mdp_external_clock_entry { + enum mdss_clock clk_type; + + /* Primary Clock Source */ + uint32_t clk_source; + + /* Secondary Clock source */ + uint32_t clk_secondary_source; + + /* Clock pre-divider */ + uint32_t clk_div; + + /* Clock M value */ + uint32_t clk_pll_m; + + /* Clock N value */ + uint32_t clk_pll_n; + + /* Clock 2D value */ + uint32_t clk_pll_2d; + + /* Clock may need source divider */ + uint32_t source_div; +}; + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h new file mode 100644 index 0000000000..91d7adee64 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_DSI_PHY_H +#define _SOC_DISPLAY_DSI_PHY_H + +#include +#include + +#define MAX_REGULATOR_CONFIG 7 +#define MAX_BIST_CONFIG 6 +#define MAX_TIMING_CONFIG 40 +#define MAX_LANE_CONFIG 45 +#define MAX_STRENGTH_CONFIG 10 +#define MAX_CTRL_CONFIG 4 +#define DMA_TPG_FIFO_LEN 64 + +struct msm_panel_info; +struct mipi_dsi_phy_ctrl { + uint32_t regulator[5]; + uint32_t timing[12]; + uint32_t ctrl[4]; + uint32_t strength[4]; + uint32_t pll[21]; +}; + +enum dsi_reg_mode { + DSI_PHY_REGULATOR_DCDC_MODE, + DSI_PHY_REGULATOR_LDO_MODE, +}; + +enum { + DSI_PLL_TYPE_10NM, + DSI_PLL_TYPE_MAX, +}; + +struct msm_dsi_phy_ctrl { + uint32_t clk_pre; + uint32_t clk_post; + uint32_t clk_zero; + uint32_t clk_trail; + uint32_t clk_prepare; + uint32_t hs_exit; + uint32_t hs_zero; + uint32_t hs_prepare; + uint32_t hs_trail; + uint32_t hs_rqst; + uint32_t ta_go; + uint32_t ta_sure; + uint32_t ta_get; + uint32_t half_byte_clk_en; + bool clk_pre_inc_by_2; +}; + +struct mdss_dsi_phy_ctrl { + uint32_t regulator[MAX_REGULATOR_CONFIG]; + uint32_t timing[MAX_TIMING_CONFIG]; + uint32_t ctrl[MAX_CTRL_CONFIG]; + uint32_t strength[MAX_STRENGTH_CONFIG]; + char bistCtrl[MAX_BIST_CONFIG]; + char laneCfg[MAX_LANE_CONFIG]; + enum dsi_reg_mode regulator_mode; + int pll_type; +}; + +enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h new file mode 100644 index 0000000000..7dcca988b4 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_DSI_PHY_PLL_H +#define _SOC_DISPLAY_DSI_PHY_PLL_H + +#include + +enum { + MDSS_DSI_PLL_10NM, + MDSS_UNKNOWN_PLL, +}; + +struct mdss_pll_vco_calc { + s32 div_frac_start1; + s32 div_frac_start2; + s32 div_frac_start3; + s64 dec_start1; + s64 dec_start2; + s64 pll_plllock_cmp1; + s64 pll_plllock_cmp2; + s64 pll_plllock_cmp3; +}; + +void dsi_phy_pll_vco_10nm_set_rate(unsigned long rate); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h new file mode 100644 index 0000000000..57a30220bf --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_MDSS_REG_H_ +#define _SOC_DISPLAY_MDSS_REG_H_ + +#include +#include + +struct dsi_regs { + uint32_t hw_version; + uint32_t ctrl; + uint32_t reserved0[2]; + uint32_t video_mode_ctrl; + uint32_t reserved1[4]; + uint32_t video_mode_active_h; + uint32_t video_mode_active_v; + uint32_t video_mode_active_total; + uint32_t video_mode_active_hsync; + uint32_t video_mode_active_vsync; + uint32_t video_mode_active_vsync_vpos; + uint32_t cmd_mode_dma_ctrl; + uint32_t cmd_mode_mdp_ctrl; + uint32_t cmd_mode_mdp_dcs_cmd_ctrl; + uint32_t dma_cmd_offset; + uint32_t dma_cmd_length; + uint32_t reserved2[2]; + uint32_t cmd_mode_mdp_stream0_ctrl; + uint32_t cmd_mode_mdp_stream0_total; + uint32_t cmd_mode_mdp_stream1_ctrl; + uint32_t cmd_mode_mdp_stream1_total; + uint32_t reserved4[7]; + uint32_t trig_ctrl; + uint32_t reserved5[2]; + uint32_t cmd_mode_dma_sw_trigger; + uint32_t reserved6[3]; + uint32_t misr_cmd_ctrl; + uint32_t misr_video_ctrl; + uint32_t lane_status; + uint32_t lane_ctrl; + uint32_t reserved7[3]; + uint32_t hs_timer_ctrl; + uint32_t timeout_status; + uint32_t clkout_timing_ctrl; + uint32_t eot_packet; + uint32_t eot_packet_ctrl; + uint32_t reserved8[15]; + uint32_t err_int_mask0; + uint32_t int_ctrl; + uint32_t iobist_ctrl; + uint32_t soft_reset; + uint32_t clk_ctrl; + uint32_t reserved9[15]; + uint32_t test_pattern_gen_ctrl; + uint32_t reserved10[7]; + uint32_t test_pattern_gen_cmd_dma_init_val; + uint32_t reserved11[14]; + uint32_t cmd_mode_mdp_ctrl2; + uint32_t reserved12[12]; + uint32_t tpg_dma_fifo_reset; + uint32_t reserved13[44]; + uint32_t video_compression_mode_ctrl; + uint32_t video_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl; + uint32_t cmd_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl3; +}; + +check_member(dsi_regs, video_mode_active_h, 0x24); +check_member(dsi_regs, cmd_mode_mdp_stream0_ctrl, 0x58); +check_member(dsi_regs, trig_ctrl, 0x84); +check_member(dsi_regs, cmd_mode_dma_sw_trigger, 0x90); +check_member(dsi_regs, misr_cmd_ctrl, 0xA0); +check_member(dsi_regs, hs_timer_ctrl, 0xBC); +check_member(dsi_regs, err_int_mask0, 0x10C); +check_member(dsi_regs, test_pattern_gen_ctrl, 0x15c); +check_member(dsi_regs, test_pattern_gen_cmd_dma_init_val, 0x17c); +check_member(dsi_regs, cmd_mode_mdp_ctrl2, 0x1B8); +check_member(dsi_regs, tpg_dma_fifo_reset, 0x1EC); +check_member(dsi_regs, video_compression_mode_ctrl, 0x2A0); + +struct dsi_phy_regs { + uint32_t phy_cmn_revision_id0; + uint32_t reserved0[3]; + uint32_t phy_cmn_clk_cfg0; + uint32_t phy_cmn_clk_cfg1; + uint32_t phy_cmn_glbl_ctrl; + uint32_t phy_cmn_rbuf_ctrl; + uint32_t phy_cmn_vreg_ctrl; + uint32_t phy_cmn_ctrl0; + uint32_t phy_cmn_ctrl1; + uint32_t phy_cmn_ctrl2; + uint32_t phy_cmn_lane_cfg0; + uint32_t phy_cmn_lane_cfg1; + uint32_t phy_cmn_pll_ctrl; + uint32_t reserved1[23]; + uint32_t phy_cmn_dsi_lane_ctrl0; + uint32_t reserved2[4]; + uint32_t phy_cmn_timing_ctrl[12]; + uint32_t reserved3[4]; + uint32_t phy_cmn_phy_status; + uint32_t reserved4[68]; + struct { + uint32_t dln0_cfg[4]; + uint32_t dln0_test_datapath; + uint32_t dln0_pin_swap; + uint32_t dln0_hstx_str_ctrl; + uint32_t dln0_offset_top_ctrl; + uint32_t dln0_offset_bot_ctrl; + uint32_t dln0_lptx_str_ctrl; + uint32_t dln0_lprx_ctrl; + uint32_t dln0_tx_dctrl; + uint32_t reserved5[20]; + } phy_ln_regs[5]; +}; + +check_member(dsi_phy_regs, phy_cmn_clk_cfg0, 0x10); +check_member(dsi_phy_regs, phy_cmn_dsi_lane_ctrl0, 0x98); +check_member(dsi_phy_regs, phy_cmn_timing_ctrl[0], 0xAC); +check_member(dsi_phy_regs, phy_cmn_phy_status, 0xEC); +check_member(dsi_phy_regs, phy_ln_regs[0], 0x200); +check_member(dsi_phy_regs, phy_ln_regs[1], 0x280); +check_member(dsi_phy_regs, phy_ln_regs[2], 0x300); +check_member(dsi_phy_regs, phy_ln_regs[3], 0x380); +check_member(dsi_phy_regs, phy_ln_regs[4], 0x400); + +struct dsi_phy_pll_qlink_regs { + uint32_t pll_analog_ctrls_one; + uint32_t pll_analog_ctrls_two; + uint32_t pll_int_loop_settings; + uint32_t pll_int_loop_settings_two; + uint32_t pll_analog_ctrls_three; + uint32_t pll_analog_ctrls_four; + uint32_t pll_int_loop_ctrls; + uint32_t pll_dsm_divider; + uint32_t pll_feedback_divider; + uint32_t pll_system_muxes; + uint32_t pll_freq_update_ctrl_overrides; + uint32_t pll_cmode; + uint32_t pll_cal_settings; + uint32_t pll_band_sel_cal_timer_low; + uint32_t pll_band_sel_cal_timer_high; + uint32_t pll_band_sel_cal_settings; + uint32_t pll_band_sel_min; + uint32_t pll_band_sel_max; + uint32_t pll_band_sel_pfilt; + uint32_t pll_band_sel_ifilt; + uint32_t pll_band_sel_cal_settings_two; + uint32_t pll_band_sel_cal_settings_three; + uint32_t pll_band_sel_cal_settings_four; + uint32_t pll_band_sel_icode_high; + uint32_t pll_band_sel_icode_low; + uint32_t pll_freq_detect_settings_one; + uint32_t pll_freq_detect_thresh; + uint32_t pll_freq_det_refclk_high; + uint32_t pll_freq_det_refclk_low; + uint32_t pll_freq_det_pllclk_high; + uint32_t pll_freq_det_pllclk_low; + uint32_t pll_pfilt; + uint32_t pll_ifilt; + uint32_t pll_pll_gain; + uint32_t pll_icode_low; + uint32_t pll_icode_high; + uint32_t pll_lockdet; + uint32_t pll_outdiv; + uint32_t pll_fastlock_ctrl; + uint32_t pll_pass_out_override_one; + uint32_t pll_pass_out_override_two; + uint32_t pll_core_override; + uint32_t pll_core_input_override; + uint32_t pll_rate_change; + uint32_t pll_digital_timers; + uint32_t pll_digital_timers_two; + uint32_t pll_decimal_div_start; + uint32_t pll_frac_div_start_low; + uint32_t pll_frac_div_start_mid; + uint32_t pll_frac_div_start_high; + uint32_t pll_dec_frac_muxes; + uint32_t pll_decimal_div_start_1; + uint32_t pll_frac_div_start_low1; + uint32_t pll_frac_div_start_mid1; + uint32_t pll_frac_div_start_high1; + uint32_t reserve0[4]; + uint32_t pll_mash_ctrl; + uint32_t reserved1[6]; + uint32_t pll_ssc_mux_ctrl; + uint32_t pll_ssc_stepsize_low1; + uint32_t pll_ssc_stepsize_high1; + uint32_t pll_ssc_div_per_low_1; + uint32_t pll_ssc_div_per_high_1; + uint32_t pll_ssc_adjper_low_1; + uint32_t pll_ssc_adjper_high_1; + uint32_t reserved2[6]; + uint32_t pll_ssc_ctrl; + uint32_t pll_outdiv_rate; + uint32_t pll_lockdet_rate[2]; + uint32_t pll_prop_gain_rate[2]; + uint32_t pll_band_set_rate[2]; + uint32_t pll_gain_ifilt_band[2]; + uint32_t pll_fl_int_gain_pfilt_band[2]; + uint32_t pll_pll_fastlock_en_band; + uint32_t reserved9[3]; + uint32_t pll_freq_tune_accum_init_mux; + uint32_t pll_lock_override; + uint32_t pll_lock_delay; + uint32_t pll_lock_min_delay; + uint32_t pll_clock_inverters; + uint32_t pll_spare_and_jpc_overrides; + uint32_t pll_bias_ctrl_1; + uint32_t pll_bias_ctrl_2; + uint32_t pll_alog_obsv_bus_ctrl_1; + uint32_t pll_common_status_one; +}; + +check_member(dsi_phy_pll_qlink_regs, pll_mash_ctrl, 0xEC); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_mux_ctrl, 0x108); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_ctrl, 0x13C); +check_member(dsi_phy_pll_qlink_regs, pll_freq_tune_accum_init_mux, 0x17C); + +struct mdp_intf_regs { + uint32_t timing_eng_enable; + uint32_t intf_config; + uint32_t intf_hsync_ctl; + uint32_t intf_vysnc_period_f0; + uint32_t intf_vysnc_period_f1; + uint32_t intf_vysnc_pulse_width_f0; + uint32_t intf_vysnc_pulse_width_f1; + uint32_t intf_disp_v_start_f0; + uint32_t intf_disp_v_start_f1; + uint32_t intf_disp_v_end_f0; + uint32_t intf_disp_v_end_f1; + uint32_t intf_active_v_start_f0; + uint32_t intf_active_v_start_f1; + uint32_t intf_active_v_end_f0; + uint32_t intf_active_v_end_f1; + uint32_t intf_disp_hctl; + uint32_t intf_active_hctl; + uint32_t intf_border_color; + uint32_t intf_underflow_color; + uint32_t reserved0[17]; + uint32_t intf_panel_format; + uint32_t reserved1[55]; + uint32_t intf_prof_fetch_start; + uint32_t reserved2[58]; + uint32_t intf_mux; +}; + +check_member(mdp_intf_regs, intf_panel_format, 0x90); +check_member(mdp_intf_regs, intf_prof_fetch_start, 0x170); +check_member(mdp_intf_regs, intf_mux, 0x25C); + +struct mdp_ctl_regs { + uint32_t ctl_layer0; + uint32_t ctl_layer1; + uint32_t reserved0[3]; + uint32_t ctl_top; + uint32_t ctl_flush; + uint32_t ctl_start; + uint32_t reserved1[53]; + uint32_t ctl_intf_active; + uint32_t reserved2[6]; + uint32_t ctl_intf_flush; +}; + +check_member(mdp_ctl_regs, ctl_top, 0x14); +check_member(mdp_ctl_regs, ctl_intf_active, 0xF4); +check_member(mdp_ctl_regs, ctl_intf_flush, 0x110); + +struct mdp_layer_mixer_regs { + uint32_t layer_op_mode; + uint32_t layer_out_size; + uint32_t layer_border_color_0; + uint32_t layer_border_color_1; + uint32_t reserved0[4]; + struct { + uint32_t layer_blend_op; + uint32_t layer_blend_const_alpha; + uint32_t layer_blend_fg_color_fill_color0; + uint32_t layer_blend_fg_color_fill_color1; + uint32_t layer_blend_fg_fill_size; + uint32_t layer_blend_fg_fill_xy; + } layer_blend[6]; +}; + +struct mdp_sspp_regs { + uint32_t sspp_src_size; + uint32_t sspp_src_img_size; + uint32_t sspp_src_xy; + uint32_t sspp_out_size; + uint32_t sspp_out_xy; + uint32_t sspp_src0; + uint32_t sspp_src1; + uint32_t sspp_src2; + uint32_t sspp_src3; + uint32_t sspp_src_ystride0; + uint32_t sspp_src_ystride1; + uint32_t sspp_tile_frame_size; + uint32_t sspp_src_format; + uint32_t sspp_src_unpack_pattern; + uint32_t sspp_src_op_mode; + uint32_t reserved0[51]; + uint32_t sspp_sw_pic_ext_c0_req_pixels; + uint32_t reserved1[3]; + uint32_t sspp_sw_pic_ext_c1c2_req_pixels; + uint32_t reserved2[3]; + uint32_t sspp_sw_pic_ext_c3_req_pixels; +}; + +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128); + +struct vbif_rt_regs { + uint32_t reserved0[88]; + uint32_t vbif_out_axi_amemtype_conf0; + uint32_t vbif_out_axi_amemtype_conf1; + uint32_t reserved1[250]; + struct { + uint32_t vbif_xinl_qos_rp_remap; + uint32_t vbif_xinh_qos_rp_remap; + } qos_rp_remap[8]; + struct { + uint32_t vbif_xinl_qos_lvl_remap; + uint32_t vbif_xinh_qos_lvl_remap; + } qos_lvl_remap[8]; +}; + +check_member(vbif_rt_regs, vbif_out_axi_amemtype_conf0, 0x160); +check_member(vbif_rt_regs, qos_rp_remap[0], 0x550); + +enum { + MDSS_BASE = 0xAE00000, +}; + +enum { + MDP_0_CTL_BASE = MDSS_BASE + 0x2000, + MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000, + MDP_VP_0_LAYER_MIXER_BASE = MDSS_BASE + 0x45000, + MDP_1_INTF_BASE = MDSS_BASE + 0x6b800, + MDP_VBIF_RT_BASE = MDSS_BASE + 0xB0000, + DSI0_CTL_BASE = MDSS_BASE + 0x94000, + DSI0_PHY_BASE = MDSS_BASE + 0x94400, + DSI0_PHY_DLN0_BASE = MDSS_BASE + 0x94600, + DSI0_PHY_DLN1_BASE = MDSS_BASE + 0x94680, + DSI0_PHY_DLN2_BASE = MDSS_BASE + 0x94700, + DSI0_PHY_DLN3_BASE = MDSS_BASE + 0x94780, + DSI0_PHY_CLKLN_BASE = MDSS_BASE + 0x94800, + DSI0_PHY_PLL_QLINK_COM = MDSS_BASE + 0x94a00, +}; + +/* DSI_0_CLK_CTRL */ +enum { + INTF = BIT(31), + PERIPH = BIT(30), + CWB = BIT(28), + ROT = BIT(27), + CDM_0 = BIT(26), + DMA_3 = BIT(25), + DMA_2 = BIT(24), + MERGE_3D = BIT(23), + DSC = BIT(22), + DSPP_3 = BIT(21), + LAYER_MIXER_5 = BIT(20), + DSPP_PA_LUTV_3 = BIT(19), + VIG_3 = BIT(18), + CTL = BIT(17), + WB = BIT(16), + DSPP_2 = BIT(15), + DSPP_1 = BIT(14), + DSPP_0 = BIT(13), + DMA_1 = BIT(12), + DMA_0 = BIT(11), + LAYER_MIXER_4 = BIT(10), + LAYER_MIXER_3 = BIT(9), + LAYER_MIXER_2 = BIT(8), + LAYER_MIXER_1 = BIT(7), + LAYER_MIXER_0 = BIT(6), + DSPP_PA_LUTV_2 = BIT(5), + DSPP_PA_LUTV_1 = BIT(4), + DSPP_PA_LUTV_0 = BIT(3), + VIG_2 = BIT(2), + VIG_1 = BIT(1), + VIG_0 = BIT(0), +}; + +enum { + DSI_AHBS_HCLK_ON = BIT(0), + DSI_AHBM_SCLK_ON = BIT(1), + DSI_PCLK_ON = BIT(2), + DSI_DSICLK_ON = BIT(3), + DSI_BYTECLK_ON = BIT(4), + DSI_ESCCLK_ON = BIT(5), + DSI_FORCE_ON_DYN_AHBS_HCLK = BIT(8), + DSI_FORCE_ON_DYN_AHBM_HCLK = BIT(9), + DSI_FORCE_ON_DYN_DSICLK = BIT(10), + DSI_FORCE_ON_DYN_BYTECLK = BIT(11), + DSI_AHBS_HCLK_HYSTERISIS1_CTRL = (3 << 11), + DSI_AHBM_HCLK_HYSTERISIS1_CTRL = (3 << 13), + DSI_DSICLK_HYSTERISIS1_CTRL = (3 << 15), + DSI_FORCE_ON_DYN_PCLK = BIT(20), + DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK = BIT(21), + DSI_DMA_CLK_STOP = BIT(22), +}; + +/* DSI_0_INT_CTRL */ +enum { + DSI_CMD_MODE_DMA_DONE_AK = BIT(0), + DSI_CMD_MODE_DMA_DONE_STAT = BIT(0), + DSI_CMD_MODE_DMA_DONE_MASK = BIT(1), + DSI_CMD_MODE_MDP_DONE_AK = BIT(8), + DSI_CMD_MODE_MDP_DONE_STAT = BIT(8), + DSI_CMD_MODE_MDP_DONE_MASK = BIT(9), + DSI_CMD_MDP_STREAM0_DONE_AK = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_STAT = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_MASK = BIT(11), + DSI_VIDEO_MODE_DONE_AK = BIT(16), + DSI_VIDEO_MODE_DONE_STAT = BIT(16), + DSI_VIDEO_MODE_DONE_MASK = BIT(17), + DSI_BTA_DONE_AK = BIT(20), + DSI_BTA_DONE_STAT = BIT(20), + DSI_BTA_DONE_MASK = BIT(21), + DSI_ERROR_AK = BIT(24), + DSI_ERROR_STAT = BIT(24), + DSI_ERROR_MASK = BIT(25), + DSI_DYNAMIC_BLANKING_DMA_DONE_AK = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_STAT = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_MASK = BIT(27), + DSI_DYNAMIC_REFRESH_DONE_AK = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_STAT = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_MASK = BIT(29), + DSI_DESKEW_DONE_AK = BIT(30), + DSI_DESKEW_DONE_STAT = BIT(30), + DSI_DESKEW_DONE_MASK = BIT(31), +}; + +/* DSI_0_COMMAND_MODE_MDP_DCS_CMD_CTRL */ +enum { + WR_MEM_START = 255, + WR_MEM_CONTINUE = 255 << 8, + INSERT_DCS_COMMAND = BIT(16), +}; + +/* DSI_0_COMMAND_MODE_DMA_CTRL */ +enum { + PACKET_TYPE = BIT(24), + POWER_MODE = BIT(26), + EMBEDDED_MODE = BIT(28), + WC_SEL = BIT(29), + BROADCAST_MASTER = BIT(30), + BROADCAST_EN = BIT(31), +}; + +static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE; +static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE; +static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM; +static struct mdp_intf_regs *const mdp_intf = (void *)MDP_1_INTF_BASE; +static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE; +static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE; +static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE; +static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE; + +void mdp_dsi_video_config(struct edid *edid); +void mdp_dsi_video_on(void); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h new file mode 100644 index 0000000000..47fd3084c6 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_MIPI_DSI_H_ +#define _SOC_DISPLAY_MIPI_DSI_H_ + +/********************************************************** + DSI register configuration options + **********************************************************/ +#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ +#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ + +#define DSI_VIDEO_DST_FORMAT_RGB565 0 +#define DSI_VIDEO_DST_FORMAT_RGB666 1 +#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 +#define DSI_VIDEO_DST_FORMAT_RGB888 3 + +enum { + DSI_VIDEO_MODE, + DSI_CMD_MODE, +}; + +enum cb_err mdss_dsi_config(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp); +void mdss_dsi_clock_config(void); +void mdss_dsi_video_mode_config(struct edid *edid, + uint32_t bpp); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index e28d808893..8bfa36e9a0 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -159,10 +159,10 @@ enum { RES_7), PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index 9f5806f4b9..9df5102114 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -7,8 +7,8 @@ #include #include #include -#include #include +#include #define GENMASK(h, l) (BIT(h + 1) - BIT(l)) diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h index 6f7c16843c..f3bc89ad9b 100644 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -79,5 +79,4 @@ void setup_usb_host0(struct usb_board_data *data); /* Call reset_ before setup_ */ void reset_usb0(void); - #endif /* _SC7180_USB_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/watchdog.h b/src/soc/qualcomm/sc7180/include/soc/watchdog.h new file mode 100644 index 0000000000..c5ddb55bba --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/watchdog.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7180_WDOG_H__ +#define _SOC_QUALCOMM_SC7180_WDOG_H__ + +void check_wdog(void); + +#endif /* _SOC_QUALCOMM_SC7180_WDOG_H__ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 2a0cd8a417..9b0adc4d5d 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -27,7 +27,8 @@ SECTIONS SSRAM_END(0x146AE000) BSRAM_START(0x14800000) - REGION(pbl_timestamps, 0x14800000, 84K, 4K) + REGION(pbl_timestamps, 0x14800000, 83K, 4K) + WATCHDOG_TOMBSTONE(0x14814FFC, 4) BOOTBLOCK(0x14815000, 40K) PRERAM_CBFS_CACHE(0x1481F000, 70K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) @@ -40,10 +41,9 @@ SECTIONS REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) - REGION(dcb, 0x14870000, 16K, 4K) - REGION(pmic, 0x14874000, 44K, 4K) - REGION(limits_cfg, 0x1487F000, 4K, 4K) - REGION(qclib, 0x14880000, 512K, 4K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 48K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) BSRAM_END(0x14900000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 6affc635f2..274d906240 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -9,7 +9,6 @@ int qclib_soc_blob_load(void) { size_t size; - ssize_t ssize; /* Attempt to load PMICCFG Blob */ size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", @@ -25,13 +24,5 @@ int qclib_soc_blob_load(void) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); - /* Attempt to load Limits Config Blob */ - ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, - REGION_SIZE(limits_cfg)); - if (ssize < 0) - return -1; - qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, - _limits_cfg, ssize, 0); - return 0; } diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index b5adee2b7c..342ee1f7fa 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -52,12 +52,8 @@ void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, clrbits_le32(®s->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); - /* HPG section 3.1.7.1 */ - if (protocol == SE_PROTOCOL_UART) { - /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */ - clock_configure_qup(bus, QUPV3_UART_SRC_HZ); - } else { + if (protocol != SE_PROTOCOL_UART) { setbits_le32(®s->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); /* configure clock dfsr */ diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index c3827ef325..d086a277c4 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include #include #include #include +#include /* SE_SPI_LOOPBACK register fields */ #define LOOPBACK_ENABLE 0x1 diff --git a/src/soc/qualcomm/sc7180/qupv3_uart.c b/src/soc/qualcomm/sc7180/qupv3_uart.c index f9d99bb71e..45d3d02d58 100644 --- a/src/soc/qualcomm/sc7180/qupv3_uart.c +++ b/src/soc/qualcomm/sc7180/qupv3_uart.c @@ -34,7 +34,7 @@ #define UART_RX_PACK_VECTOR0 0xF #define UART_RX_PACK_VECTOR2 0x00 -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; @@ -43,7 +43,7 @@ void uart_tx_flush(int idx) ; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; unsigned int reg_value; @@ -71,7 +71,7 @@ void uart_init(int idx) /* sc7180 requires 16 clock pulses to sample 1 bit of data */ uart_freq = baud_rate * 16; - div = DIV_ROUND_CLOSEST(QUPV3_UART_SRC_HZ, uart_freq); + div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); write32(®s->geni_ser_m_clk_cfg, (div << 4) | 1); write32(®s->geni_ser_s_clk_cfg, (div << 4) | 1); @@ -113,7 +113,7 @@ void uart_init(int idx) write32(®s->geni_s_cmd0, START_UART_RX); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct qup_regs *regs = qup[idx].regs; @@ -122,7 +122,7 @@ unsigned char uart_rx_byte(int idx) return 0; } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct qup_regs *regs = qup[idx].regs; @@ -134,7 +134,7 @@ void uart_tx_byte(int idx, unsigned char data) write32(®s->geni_tx_fifon, data); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)qup[idx].regs; } @@ -147,7 +147,7 @@ void uart_fill_lb(void *data) serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - serial.input_hertz = QUPV3_UART_SRC_HZ; + serial.input_hertz = SRC_XO_HZ; lb_add_serial(&serial, data); } diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index b3a6cd5870..7d88a20986 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -16,22 +16,22 @@ static void set_tx(int line_state) gpio_set(UART_TX_PIN, line_state); } -void uart_init(int idx) +void uart_init(unsigned int idx) { gpio_output(UART_TX_PIN, 1); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart_bitbang_tx_byte(data, set_tx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; /* not implemented */ } diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index c4b65d6e4e..370fa66911 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -291,8 +290,6 @@ static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = (void *)QMP_PHY_PCS_REG_BASE; - - struct usb_dwc3 { u32 sbuscfg0; u32 sbuscfg1; @@ -437,8 +434,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, }; - - struct usb_dwc3_cfg { struct usb_dwc3 *usb_host_dwc3; struct usb_qusb_phy_pll *qusb_phy_pll; @@ -482,7 +477,6 @@ static struct usb_dwc3_cfg usb_port0 = { .efuse_offset = 25, }; - static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; static void reset_usb(struct usb_dwc3_cfg *dwc3) @@ -506,7 +500,6 @@ void reset_usb0(void) reset_usb(&usb_port0); } - /* * Update board specific PHY tuning override values that specified from * board file. diff --git a/src/soc/qualcomm/sc7180/watchdog.c b/src/soc/qualcomm/sc7180/watchdog.c new file mode 100644 index 0000000000..954f68aa3d --- /dev/null +++ b/src/soc/qualcomm/sc7180/watchdog.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void check_wdog(void) +{ + uint32_t wdog_sta = read32(&aoss->aoss_cc_reset_status); + + if (wdog_sta & WDOG_RESET_BIT_MASK) + mark_watchdog_tombstone(); +} diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index c93ec6c1bb..2b9bef3bd5 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -9,6 +9,7 @@ config SOC_QUALCOMM_SDM845 select GENERIC_GPIO_LIB select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON + select CACHE_MRC_SETTINGS if SOC_QUALCOMM_SDM845 @@ -21,6 +22,7 @@ config VBOOT select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config SDM845_QSPI bool diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index ba6bc8cd29..aa80a1439e 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -3,7 +3,6 @@ #ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ #define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ - #define QSPI_BASE 0x88DF000 #define TLMM_EAST_TILE_BASE 0x03500000 #define TLMM_NORTH_TILE_BASE 0x03900000 diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index b78db833a4..8d7138e5d1 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -10,22 +10,22 @@ static void set_tx(int line_state) gpio_set(UART_TX_PIN, line_state); } -void uart_init(int idx) +void uart_init(unsigned int idx) { gpio_output(UART_TX_PIN, 1); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { uart_bitbang_tx_byte(data, set_tx); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { return 0; /* not implemented */ } diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 627603fae5..422b306a14 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -280,7 +280,6 @@ static int rk_edp_dpcd_write(struct rk_edp *edp, u32 addr, return rk_edp_dpcd_transfer(edp, addr, values, size, DPCD_WRITE); } - static int rk_edp_link_power_up(struct rk_edp *edp) { u8 value; diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index 393b45753d..dbbfd3e041 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index cd5c543381..702d99f843 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -523,7 +523,6 @@ check_member(rk_edp_regs, pll_reg_5, 0xa00); #define EDID_HEADER 0x00 #define EDID_EXTENSION_FLAG 0x7e - enum dpcd_request { DPCD_READ, DPCD_WRITE, diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 0184fefa6d..dfaf42629f 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -32,7 +32,6 @@ struct rockchip_spi { }; check_member(rockchip_spi, rxdr, 0x800); - #define SF_READ_DATA_CMD 0x3 /* --------Bit fields in CTRLR0--------begin */ diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index d1e980addf..bb09700b36 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -25,7 +25,6 @@ check_member(rk_pwm_regs, int_en, 0x44); #define RK_PWM_DISABLE (0 << 0) #define RK_PWM_ENABLE (1 << 0) - #define PWM_ONE_SHOT (0 << 1) #define PWM_CONTINUOUS (1 << 1) #define RK_PWM_CAPTURE (1 << 2) diff --git a/src/soc/rockchip/common/uart.c b/src/soc/rockchip/common/uart.c index 2c6d6cec68..b98f182d7c 100644 --- a/src/soc/rockchip/common/uart.c +++ b/src/soc/rockchip/common/uart.c @@ -9,7 +9,7 @@ unsigned int uart_platform_refclk(void) return OSC_HZ; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index 93ef9cb2ed..0f49722df9 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -263,7 +263,6 @@ enum { HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - /* fc_aviconf0-fc_aviconf3 field values */ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ea1d7ff531..0ba07d6137 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -81,7 +81,7 @@ enum { PLL_SSMOD_RESET_SHIFT = 2, PLL_SSMOD_DOWNSPEAD_MASK = 1, PLL_SSMOD_DOWNSPEAD_SHIFT = 3, - PLL_SSMOD_DIVVAL_MASK = 0Xf, + PLL_SSMOD_DIVVAL_MASK = 0xf, PLL_SSMOD_DIVVAL_SHIFT = 4, PLL_SSMOD_SPREADAMP_MASK = 0x1f, PLL_SSMOD_SPREADAMP_SHIFT = 8, diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index 06fd781d8e..bf69aecd56 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -52,7 +52,6 @@ #define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */ #define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */ - #define DDRC0_BASE_ADDR 0xffa80000 #define SERVER_MSCH0_BASE_ADDR 0xffa84000 #define DDRC1_BASE_ADDR 0xffa88000 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index bc89c37af3..fc7499f2d8 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -434,7 +434,6 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); - /* speed setting */ if (sdram_params->ddr_freq < 400 * MHz) speed = 0x0; diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c index 6bb854d2f4..27b23f1ea3 100644 --- a/src/soc/rockchip/rk3399/spi_bitbang.c +++ b/src/soc/rockchip/rk3399/spi_bitbang.c @@ -8,6 +8,7 @@ #include #include #include +#include struct rockchip_bitbang_slave { struct spi_bitbang_ops ops; diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 98a4c663ec..9166b02cad 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -508,7 +508,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device) return ret; } - base = dp->base; /* Enable enhanced mode */ setbits32(&base->sys_ctl_4, ENHANCED); diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index 5a6226df95..bc5570daad 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -94,9 +94,6 @@ static struct s3c24x0_i2c_bus i2c_busses[] = { }, }; - - - static int i2c_int_pending(struct i2c_regs *regs) { return read8(®s->con) & I2cConIntPending; @@ -146,9 +143,6 @@ static int i2c_wait_for_int(struct i2c_regs *regs) return 1; } - - - static int i2c_send_stop(struct i2c_regs *regs) { uint8_t mode = read8(®s->stat) & (I2cStatModeMask); diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/exynos5250/include/soc/dsim.h index 8aba3f5ac5..d85180252b 100644 --- a/src/soc/samsung/exynos5250/include/soc/dsim.h +++ b/src/soc/samsung/exynos5250/include/soc/dsim.h @@ -52,7 +52,6 @@ check_member(exynos5_dsim, phyacchr1, 0x54); #define VIDEO_MODE (1 << 25) #define BURST_MODE (1 << 26) - #define DSIM_PHYACCHR_AFC_EN (1 << 14) #define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 diff --git a/src/soc/samsung/exynos5250/include/soc/setup.h b/src/soc/samsung/exynos5250/include/soc/setup.h index eb23eeff12..4b468cb4fa 100644 --- a/src/soc/samsung/exynos5250/include/soc/setup.h +++ b/src/soc/samsung/exynos5250/include/soc/setup.h @@ -141,7 +141,6 @@ struct exynos5_phy_control; | (CPUD_RATIO << 4) \ | (ARM_RATIO)) - /* CLK_FSYS */ #define CLK_SRC_FSYS0_VAL 0x66666 #define CLK_DIV_FSYS0_VAL 0x0BB00000 diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 0451902df1..879d04a598 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 326312576b..ef03c04f23 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -100,7 +100,7 @@ static void exynos5_uart_tx_flush(struct s5p_uart *uart) while (read32(&uart->ufstat) & 0x1ff0000); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 4) return 0x12c00000 + idx * 0x10000; @@ -108,25 +108,25 @@ uintptr_t uart_platform_base(int idx) return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 7c2fd9f035..758e09b05d 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -31,7 +31,6 @@ * 11. Source sends video data. */ - static int exynos_dp_init_dp(void) { int ret; @@ -843,7 +842,6 @@ int exynos_init_dp(struct edp_device_info *edp_info) { unsigned int ret; - dp_phy_control(1); ret = exynos_dp_init_dp(); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index e53adbb8c8..b6d9e0b37f 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -75,7 +75,6 @@ void exynos_dp_enable_video_mute(unsigned int enable) return; } - static void exynos_dp_init_analog_param(void) { u32 reg; @@ -999,7 +998,6 @@ int exynos_dp_init_video(void) return 0; } - void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) { u32 reg; diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 45657f13cf..ab17d52c44 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -71,7 +71,6 @@ struct i2c_bus unsigned int clk_div; }; - static struct i2c_bus i2c_busses[] = { { .bus_num = 0, @@ -236,9 +235,6 @@ enum { I2cStatMasterXmit = 0x3 << 6 }; - - - static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, unsigned int op_clk) { @@ -487,9 +483,6 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_msg *segments, return 0; } - - - static int i2c_int_pending(struct i2c_regs *regs) { return read8(®s->con) & I2cConIntPending; @@ -539,9 +532,6 @@ static int i2c_wait_for_int(struct i2c_regs *regs) return 1; } - - - static int i2c_send_stop(struct i2c_regs *regs) { uint8_t mode = read8(®s->stat) & (I2cStatModeMask); diff --git a/src/soc/samsung/exynos5420/include/soc/dmc.h b/src/soc/samsung/exynos5420/include/soc/dmc.h index 7dd09f9e83..a17f1fecba 100644 --- a/src/soc/samsung/exynos5420/include/soc/dmc.h +++ b/src/soc/samsung/exynos5420/include/soc/dmc.h @@ -300,7 +300,6 @@ enum { MEM_TIMINGS_MSR_COUNT = 5, }; - /* These are the memory timings for a particular memory type and speed */ struct mem_timings { enum mem_manuf mem_manuf; /* Memory manufacturer */ diff --git a/src/soc/samsung/exynos5420/include/soc/dp.h b/src/soc/samsung/exynos5420/include/soc/dp.h index 6d4b2d7ac1..50a6cbf5ee 100644 --- a/src/soc/samsung/exynos5420/include/soc/dp.h +++ b/src/soc/samsung/exynos5420/include/soc/dp.h @@ -1338,12 +1338,10 @@ enum { VIDEO_TIMING_FROM_REGISTER }; - struct exynos_dp_platform_data { struct edp_device_info *edp_dev_info; }; - int exynos_init_dp(struct edp_device_info *edp_info); void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd); diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/exynos5420/include/soc/dsim.h index 82067fa226..b6b7ee9a12 100644 --- a/src/soc/samsung/exynos5420/include/soc/dsim.h +++ b/src/soc/samsung/exynos5420/include/soc/dsim.h @@ -52,7 +52,6 @@ check_member(exynos5_dsim, phyacchr1, 0x54); #define VIDEO_MODE (1 << 25) #define BURST_MODE (1 << 26) - #define DSIM_PHYACCHR_AFC_EN (1 << 14) #define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h index 8454537249..4867c56eed 100644 --- a/src/soc/samsung/exynos5420/include/soc/setup.h +++ b/src/soc/samsung/exynos5420/include/soc/setup.h @@ -642,7 +642,6 @@ struct exynos5_phy_control; #define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_LOCK_COARSE_MASK (0x7F << 10) - #define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_VAL 0x7F @@ -711,7 +710,6 @@ struct exynos5_phy_control; #define PHY_CON39_VAL_34_OHM 0x0DB60DB6 #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF - #define CTRL_BSTLEN_OFFSET 8 #define CTRL_RDLAT_OFFSET 0 diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 42ca5fcf9e..0a2f0275ac 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index c7a0649f5d..16a4b11da3 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -92,7 +92,7 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) write8(&uart->utxh, data); } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 4) return 0x12c00000 + idx * 0x10000; @@ -100,25 +100,25 @@ uintptr_t uart_platform_base(int idx) return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { /* Exynos5250 implements this too. */ } diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 9b21532bba..977f938eb4 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -177,7 +177,6 @@ static void init_gemgxlclk(void) write32(&prci->gemgxlpllcfg1, cfg1); } - #define FU540_UART_DEVICES 2 #define FU540_UART_REG_DIV 0x18 #define FU540_UART_DIV_VAL 4 @@ -185,7 +184,6 @@ static void init_gemgxlclk(void) #define FU540_SPI_DIV 0x00 #define FU540_SPI_DIV_VAL 4 - static void update_peripheral_clock_dividers(void) { write32((uint32_t *)(FU540_QSPI0 + FU540_SPI_DIV), FU540_SPI_DIV_VAL); diff --git a/src/soc/sifive/fu540/ddrregs.h b/src/soc/sifive/fu540/ddrregs.h index 78b6dce801..8786f689f5 100644 --- a/src/soc/sifive/fu540/ddrregs.h +++ b/src/soc/sifive/fu540/ddrregs.h @@ -140,7 +140,6 @@ DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA, DENALI_PHY_119 DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA, DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA, DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA, DENALI_PHY_1209_DATA, DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA, DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA}; - uint32_t DENALI_CTL_DATA[265] = { DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA, DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA, DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA, DENALI_CTL_09_DATA, DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA, DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA, DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA, DENALI_CTL_19_DATA, diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index d877452318..87c59a4716 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -13,7 +13,6 @@ static struct spi_ctrl *spictrls[] = { (struct spi_ctrl *)FU540_QSPI2 }; - /** * Wait until SPI is ready for transmission and transmit byte. */ @@ -35,7 +34,6 @@ static void spi_tx(volatile struct spi_ctrl *spictrl, uint8_t in) #endif } - /** * Wait until SPI receive queue has data and read byte. */ diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h index bdddf4f69e..96124c1fdf 100644 --- a/src/soc/sifive/fu540/spi_internal.h +++ b/src/soc/sifive/fu540/spi_internal.h @@ -22,7 +22,6 @@ typedef union { } spi_reg_sckmode; _ASSERT_SIZEOF(spi_reg_sckmode, 4); - typedef union { struct { uint32_t mode : 2; @@ -32,7 +31,6 @@ typedef union { } spi_reg_csmode; _ASSERT_SIZEOF(spi_reg_csmode, 4); - typedef union { struct { uint32_t cssck : 8; @@ -44,7 +42,6 @@ typedef union { } spi_reg_delay0; _ASSERT_SIZEOF(spi_reg_delay0, 4); - typedef union { struct { uint32_t intercs : 8; @@ -56,7 +53,6 @@ typedef union { } spi_reg_delay1; _ASSERT_SIZEOF(spi_reg_delay1, 4); - typedef union { struct { uint32_t proto : 2; @@ -70,7 +66,6 @@ typedef union { } spi_reg_fmt; _ASSERT_SIZEOF(spi_reg_fmt, 4); - typedef union { struct { uint32_t data : 8; @@ -81,7 +76,6 @@ typedef union { } spi_reg_txdata; _ASSERT_SIZEOF(spi_reg_txdata, 4); - typedef union { struct { uint32_t data : 8; @@ -92,7 +86,6 @@ typedef union { } spi_reg_rxdata; _ASSERT_SIZEOF(spi_reg_rxdata, 4); - typedef union { struct { uint32_t txmark : 3; @@ -102,7 +95,6 @@ typedef union { } spi_reg_txmark; _ASSERT_SIZEOF(spi_reg_txmark, 4); - typedef union { struct { uint32_t rxmark : 3; @@ -112,7 +104,6 @@ typedef union { } spi_reg_rxmark; _ASSERT_SIZEOF(spi_reg_rxmark, 4); - typedef union { struct { uint32_t en : 1; @@ -122,7 +113,6 @@ typedef union { } spi_reg_fctrl; _ASSERT_SIZEOF(spi_reg_fctrl, 4); - typedef union { struct { uint32_t cmd_en : 1; @@ -139,7 +129,6 @@ typedef union { } spi_reg_ffmt; _ASSERT_SIZEOF(spi_reg_ffmt, 4); - typedef union { struct { uint32_t txwm : 1; @@ -154,7 +143,6 @@ _ASSERT_SIZEOF(spi_reg_ip, 4); #undef _ASSERT_SIZEOF - /** * SPI control register memory map. * diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index c35e0f6166..353f6cd624 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -6,7 +6,7 @@ #include #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { if (idx < 2) return FU540_UART(idx); diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index 565103bb9e..14a628d441 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -47,7 +47,6 @@ static inline void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physe } } - static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) { volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr; volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t)); diff --git a/src/soc/ti/Kconfig b/src/soc/ti/Kconfig new file mode 100644 index 0000000000..eb66519f2e --- /dev/null +++ b/src/soc/ti/Kconfig @@ -0,0 +1 @@ +source "src/soc/ti/am335x/Kconfig" diff --git a/src/soc/ti/Makefile.inc b/src/soc/ti/Makefile.inc new file mode 100644 index 0000000000..357cc82e18 --- /dev/null +++ b/src/soc/ti/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_TI_AM335X) += am335x diff --git a/src/cpu/ti/am335x/Kconfig b/src/soc/ti/am335x/Kconfig similarity index 76% rename from src/cpu/ti/am335x/Kconfig rename to src/soc/ti/am335x/Kconfig index 3684480929..533a0de628 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/soc/ti/am335x/Kconfig @@ -1,4 +1,4 @@ -config CPU_TI_AM335X +config SOC_TI_AM335X select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 @@ -9,10 +9,10 @@ config CPU_TI_AM335X bool default n -if CPU_TI_AM335X +if SOC_TI_AM335X config MEMLAYOUT_LD_FILE string - default "src/cpu/ti/am335x/memlayout.ld" + default "src/soc/ti/am335x/memlayout.ld" endif diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc similarity index 79% rename from src/cpu/ti/am335x/Makefile.inc rename to src/soc/ti/am335x/Makefile.inc index 6f414bcf79..e744c72526 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -1,3 +1,4 @@ +ifeq ($(CONFIG_SOC_TI_AM335X),y) bootblock-y += bootblock.c bootblock-y += bootblock_media.c bootblock-y += dmtimer.c @@ -13,6 +14,7 @@ romstage-y += monotonic_timer.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c +ramstage-y += soc.c bootblock-y += uart.c romstage-y += uart.c @@ -28,17 +30,13 @@ real-target: $(obj)/MLO header_ld := $(call src-to-obj,omap-header,$(dir)/header.ld) get_header_size= \ - $(eval omap_header_info=$(shell $(CBFSTOOL) $(1) print | grep $(2))) \ - $(shell echo $$(($(word 2,$(omap_header_info)) + \ - $(word 4,$(omap_header_info))))) + $(shell echo $$(wc -c < $(objcbfs)/bootblock.bin)) -$(obj)/omap-header.bin: $$(omap-header-objs) $(obj)/coreboot.rom +$(obj)/omap-header.bin: $$(omap-header-objs) $(objcbfs)/bootblock.bin @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ - $(call get_header_size,$(obj)/coreboot.rom, \ - $(CONFIG_CBFS_PREFIX)/romstage \ - ) \ + $(call get_header_size,$(obj)/coreboot.rom) \ ) \ -o $@.tmp $< -T $(header_ld) $(OBJCOPY_omap-header) --only-section=".header" -O binary $@.tmp $@ @@ -51,3 +49,4 @@ omap-header-y += header.c omap-header-srcs += $(CONFIG_MEMLAYOUT_LD_FILE) omap-header-y += header.ld +endif diff --git a/src/cpu/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c similarity index 100% rename from src/cpu/ti/am335x/bootblock.c rename to src/soc/ti/am335x/bootblock.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c similarity index 85% rename from src/cpu/ti/am335x/bootblock_media.c rename to src/soc/ti/am335x/bootblock_media.c index 050e0b77da..1c65c38684 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/soc/ti/am335x/bootblock_media.c @@ -5,7 +5,7 @@ /* FIXME: No idea how big the internal SRAM actually is. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/cpu/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c similarity index 100% rename from src/cpu/ti/am335x/cbmem.c rename to src/soc/ti/am335x/cbmem.c diff --git a/src/cpu/ti/am335x/clock.h b/src/soc/ti/am335x/clock.h similarity index 98% rename from src/cpu/ti/am335x/clock.h rename to src/soc/ti/am335x/clock.h index aadd3f6e93..38b4ece249 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/soc/ti/am335x/clock.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_CLOCK_H__ -#define __CPU_TI_AM335X_CLOCK_H__ +#ifndef __SOC_TI_AM335X_CLOCK_H__ +#define __SOC_TI_AM335X_CLOCK_H__ #include @@ -219,4 +219,4 @@ struct am335x_cm_cefuse_regs { static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = (void *)0x44e00a00; -#endif /* __CPU_TI_AM335X_CLOCK_H__ */ +#endif /* __SOC_TI_AM335X_CLOCK_H__ */ diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/soc/ti/am335x/dmtimer.c similarity index 100% rename from src/cpu/ti/am335x/dmtimer.c rename to src/soc/ti/am335x/dmtimer.c diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/soc/ti/am335x/dmtimer.h similarity index 69% rename from src/cpu/ti/am335x/dmtimer.h rename to src/soc/ti/am335x/dmtimer.h index 7e93a0c8f6..ad8515fbba 100644 --- a/src/cpu/ti/am335x/dmtimer.h +++ b/src/soc/ti/am335x/dmtimer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __CPU_TI_AM335X_DMTIMER_H__ -#define __CPU_TI_AM335X_DMTIMER_H__ +#ifndef __SOC_TI_AM335X_DMTIMER_H__ +#define __SOC_TI_AM335X_DMTIMER_H__ #include diff --git a/src/cpu/ti/am335x/gpio.c b/src/soc/ti/am335x/gpio.c similarity index 97% rename from src/cpu/ti/am335x/gpio.c rename to src/soc/ti/am335x/gpio.c index de7f7404f7..d3d3581f86 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/soc/ti/am335x/gpio.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio, diff --git a/src/cpu/ti/am335x/gpio.h b/src/soc/ti/am335x/gpio.h similarity index 93% rename from src/cpu/ti/am335x/gpio.h rename to src/soc/ti/am335x/gpio.h index 62ad77ab16..0877a6258c 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/soc/ti/am335x/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_GPIO_H__ -#define __CPU_TI_AM335X_GPIO_H__ +#ifndef __SOC_TI_AM335X_GPIO_H__ +#define __SOC_TI_AM335X_GPIO_H__ #include @@ -55,4 +55,4 @@ int gpio_direction_output(unsigned int gpio, int value); int gpio_get_value(unsigned int gpio); int gpio_set_value(unsigned int gpio, int value); -#endif /* __CPU_TI_AM335X_CLOCK_H__ */ +#endif /* __SOC_TI_AM335X_CLOCK_H__ */ diff --git a/src/cpu/ti/am335x/header.c b/src/soc/ti/am335x/header.c similarity index 97% rename from src/cpu/ti/am335x/header.c rename to src/soc/ti/am335x/header.c index 9edfdd062b..c0a7589abd 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -52,6 +52,6 @@ struct omap_image_headers headers __attribute__((section(".header"))) = { }, .image_header = { .size = (uintptr_t)&header_load_size, - .destination = (uintptr_t)_dram + .destination = (uintptr_t)_sram } }; diff --git a/src/cpu/ti/am335x/header.h b/src/soc/ti/am335x/header.h similarity index 93% rename from src/cpu/ti/am335x/header.h rename to src/soc/ti/am335x/header.h index 578d2136f2..a0a54ad0f3 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/soc/ti/am335x/header.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_HEADER_H -#define __CPU_TI_AM335X_HEADER_H +#ifndef __SOC_TI_AM335X_HEADER_H +#define __SOC_TI_AM335X_HEADER_H #include diff --git a/src/cpu/ti/am335x/header.ld b/src/soc/ti/am335x/header.ld similarity index 100% rename from src/cpu/ti/am335x/header.ld rename to src/soc/ti/am335x/header.ld diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld similarity index 85% rename from src/cpu/ti/am335x/memlayout.ld rename to src/soc/ti/am335x/memlayout.ld index 78528e63b7..991e4012a4 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -6,11 +6,14 @@ SECTIONS { - DRAM_START(0x40000000) + SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) ROMSTAGE(0x402f5400, 88K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) + SRAM_END(0x40310000) + DRAM_START(0x80000000) + RAMSTAGE(0x80200000, 192K) /* TODO: Implement MMU support and move TTB to a better location. */ diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/soc/ti/am335x/monotonic_timer.c similarity index 100% rename from src/cpu/ti/am335x/monotonic_timer.c rename to src/soc/ti/am335x/monotonic_timer.c diff --git a/src/cpu/ti/am335x/nand.c b/src/soc/ti/am335x/nand.c similarity index 100% rename from src/cpu/ti/am335x/nand.c rename to src/soc/ti/am335x/nand.c diff --git a/src/cpu/ti/am335x/pinmux.c b/src/soc/ti/am335x/pinmux.c similarity index 100% rename from src/cpu/ti/am335x/pinmux.c rename to src/soc/ti/am335x/pinmux.c diff --git a/src/cpu/ti/am335x/pinmux.h b/src/soc/ti/am335x/pinmux.h similarity index 98% rename from src/cpu/ti/am335x/pinmux.h rename to src/soc/ti/am335x/pinmux.h index 0cb56a6199..c46d03dbc9 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/soc/ti/am335x/pinmux.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_PINMUX_H -#define __CPU_TI_AM335X_PINMUX_H +#ifndef __SOC_TI_AM335X_PINMUX_H +#define __SOC_TI_AM335X_PINMUX_H #include diff --git a/src/soc/ti/am335x/soc.c b/src/soc/ti/am335x/soc.c new file mode 100644 index 0000000000..0362ed9c0c --- /dev/null +++ b/src/soc/ti/am335x/soc.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct chip_operations soc_ti_am335x_ops = { + CHIP_NAME("TI AM335X") +}; diff --git a/src/cpu/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c similarity index 94% rename from src/cpu/ti/am335x/uart.c rename to src/soc/ti/am335x/uart.c index a8823400ad..e3648a93a6 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #define EFR_ENHANCED_EN (1 << 4) #define FCR_FIFO_EN (1 << 0) @@ -135,7 +135,7 @@ unsigned int uart_platform_refclk(void) return 48000000; } -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { const unsigned int bases[] = { 0x44e09000, 0x48022000, 0x48024000, @@ -146,7 +146,7 @@ uintptr_t uart_platform_base(int idx) return 0; } -void uart_init(int idx) +void uart_init(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( @@ -154,19 +154,19 @@ void uart_init(int idx) am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(int idx) +unsigned char uart_rx_byte(unsigned int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(int idx, unsigned char data) +void uart_tx_byte(unsigned int idx, unsigned char data) { struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(int idx) +void uart_tx_flush(unsigned int idx) { } diff --git a/src/cpu/ti/am335x/uart.h b/src/soc/ti/am335x/uart.h similarity index 100% rename from src/cpu/ti/am335x/uart.h rename to src/soc/ti/am335x/uart.h diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 220b327de0..ee696edb02 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -77,11 +77,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -89,7 +88,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3609314f4e..f1506bc44f 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -13,7 +13,6 @@ #include "smbus.h" #include "smi.h" - #define PM_REG_USB_ENABLE 0xef enum usb_enable { @@ -106,7 +105,6 @@ void hudson_enable(struct device *dev) } } - static void hudson_init_acpi_ports(void) { /* We use some of these ports in SMM regardless of whether or not diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 9b6663a3d8..eeb60ca35a 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -4,6 +4,7 @@ #define HUDSON_H #include +#include /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index c9330df52c..5e828f7059 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -7,7 +7,6 @@ #include #include - /* * Update the PCI devices with a valid IRQ number * that is set in the mainboard PCI_IRQ structures. diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 5850f2ba66..6381d97e9a 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); - #endif diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index e0f36cabcc..7dcbbf9a50 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -4,6 +4,7 @@ #include #include #include +#include /* warning: Porting.h includes an open #pragma pack(1) */ #include #include diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index cce11dc566..b2f9ff2f72 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include #include #include @@ -7,6 +8,7 @@ #include #include #include +#include #include diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index b931cf05ab..c5ca8b40d9 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -83,7 +83,6 @@ typedef struct _AMD_CONFIG_PARAMS { IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. } AMD_CONFIG_PARAMS; - /// AGESA Binary module header structure typedef struct _AMD_IMAGE_HEADER { IN unsigned int Signature; ///< Binary Signature diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 1bcfd6647d..99c7323033 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -48,7 +48,6 @@ typedef union _PCI_ADDR { #include /* platform default configuration */ #include - //------------------------------------------------------------------------------------------------------------------------// /** * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 3868d2461c..9272194442 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - /* * ACPI - create the Fixed ACPI Description Tables (FADT) */ @@ -101,7 +100,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; @@ -112,7 +111,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -120,7 +118,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 34c32f53a7..bbba3fa083 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -39,12 +39,10 @@ void init_sb800_MANUAL_fans(struct device *dev) if (sb_chip->fan4_enabled) for (i = 0; i < FAN_REGISTER_COUNT; i++) pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); - } void init_sb800_IMC_fans(struct device *dev) { - AMDSBCFG sb_config; unsigned char *message_ptr; int i; @@ -63,7 +61,6 @@ void init_sb800_IMC_fans(struct device *dev) pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); - /* * Do an initial manual setup of the fans for things like polarity * and frequency. @@ -107,7 +104,6 @@ if (sb_chip->imc_fan_zone0_enabled) { message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; - } /* @@ -138,10 +134,8 @@ if (sb_chip->imc_fan_zone1_enabled) { message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; - } - /* ********** Zone 2 ********** */ @@ -170,7 +164,6 @@ if (sb_chip->imc_fan_zone2_enabled) { message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; - } /* @@ -202,7 +195,6 @@ if (sb_chip->imc_fan_zone3_enabled) { message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; - } /* diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index 5a02543260..d11fbcfc66 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -70,7 +70,6 @@ void init_sb800_MANUAL_fans(struct device *dev); #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF - /* IMC Fan Control Definitions */ #define IMC_MODE1_FAN_ENABLED ( 1 << 0 ) #define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 ) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 43a88b7cd0..15e6d67c0c 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -213,7 +213,6 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ }; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -227,7 +226,6 @@ static const struct pci_driver azalia_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_HDA, }; - static struct device_operations gec_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -358,7 +356,6 @@ static void sb800_enable(struct device *dev) } break; - case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */ /* Initialize the fans */ #if CONFIG(SB800_IMC_FAN_CONTROL) diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index 5dac9ae61f..483716c202 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "SBPLATFORM.h" int acpi_get_sleep_type(void) diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 11b24afdd9..5e5ca5d5f5 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _CIMX_H_ #define _CIMX_H_ diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 86bde267ff..7d1ffb981e 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include "smbus.h" #include /* printk */ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 4a66a4b043..468ae23393 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -105,7 +105,6 @@ static void ImcSleep(void) WaitForEcLDN9MailboxCmdAck(); } - static void ImcWakeup(void) { u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h index 3238c929c5..ca6b3ca191 100644 --- a/src/southbridge/amd/common/amd_defs.h +++ b/src/southbridge/amd/common/amd_defs.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #ifndef _AMD_SB_DEFS_H_ #define _AMD_SB_DEFS_H_ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index da861ee2e1..09bf1d6682 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -83,7 +83,7 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin #PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin #PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin #TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif @@ -94,7 +94,7 @@ FIRMWARE_TYPE=CZ PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin +PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin @@ -120,7 +120,7 @@ OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) +OPT_PSPSECUREOS_FILE=$(call add_opt_prefix, $(PSPSECUREOS_FILE), --secureos) OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) @@ -135,7 +135,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ - $(call strip_quotes, $(PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(PSPSECUREOS_FILE)) \ $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ @@ -149,7 +149,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(SMUFWM2_FILE)) \ $(call strip_quotes, $(SMUFWM2_FN_FILE)) \ $(call strip_quotes, $(PSPRCVR2_FILE)) \ - $(call strip_quotes, $(PSPSCUREOS2_FILE)) \ + $(call strip_quotes, $(PSPSECUREOS2_FILE)) \ $(call strip_quotes, $(PSPNVRAM2_FILE)) \ $(call strip_quotes, $(SMUSCS2_FILE)) \ $(call strip_quotes, $(PSPSECUREDEBUG2_FILE)) \ @@ -169,7 +169,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_SMUFWM_FILE) \ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPSECUREOS_FILE) \ $(OPT_PSPNVRAM_FILE) \ $(OPT_PSPSECUREDEBUG_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ @@ -182,7 +182,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_2SMUFWM_FN_FILE) \ $(OPT_2PSPRCVR_FILE) \ $(OPT_2PUBSIGNEDKEY_FILE) \ - $(OPT_2PSPSCUREOS_FILE) \ + $(OPT_2PSPSECUREOS_FILE) \ $(OPT_2PSPNVRAM_FILE) \ $(OPT_2PSPSECUREDEBUG_FILE) \ $(OPT_2PSPTRUSTLETS_FILE) \ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 14bb5e29c3..f43dbb93f7 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -187,7 +187,7 @@ static void lpc_wideio_window(uint16_t base, uint16_t size) pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); enable_wideio(2, size); } else { /* All WIDEIO locations used*/ - assert(0); + BUG(); } } } diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 0b73921e7b..0bb9a97f40 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -79,11 +79,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; @@ -91,7 +90,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index a367caa910..239891065d 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -55,5 +55,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); - #endif diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c index 2d28210569..996215de34 100644 --- a/src/southbridge/amd/pi/hudson/uart.c +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -2,7 +2,7 @@ #include -uintptr_t uart_platform_base(int idx) +uintptr_t uart_platform_base(unsigned int idx) { return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9de3bf8c94..7852ace972 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -14,6 +14,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 1e80cf9938..3b10201930 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -27,7 +27,7 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-y += smihandler.c me.c me_8.x.c pch.c -romstage-y += early_smbus.c me_status.c +romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl deleted file mode 100644 index 3f3386d908..0000000000 --- a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl +++ /dev/null @@ -1,473 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 4b101d2190..85e8d24490 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -50,7 +50,7 @@ Device (LPCB) RCBA, 18, } - #include "irqlinks.asl" + #include #include "acpi/ec.asl" @@ -184,8 +184,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 4f5d8caa72..15be4abaef 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -12,10 +12,6 @@ #include "chip.h" #include "pch.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - typedef struct southbridge_intel_bd82x6x_config config_t; static int set_bits(void *port, u32 mask, u32 val) @@ -30,9 +26,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -52,15 +46,14 @@ static int codec_detect(u8 *base) u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) goto no_codec; @@ -70,22 +63,22 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -93,15 +86,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ - int timeout = 1000; while (timeout--) { @@ -114,28 +106,25 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 1msec timeout */ + int timeout = 1000; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 1msec timeout */ - - int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -159,16 +148,15 @@ static void codec_init(struct device *dev, u8 *base, int addr) } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) == -1) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } - reg32 = read32(base + 0x64); - /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -183,7 +171,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -203,7 +191,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; @@ -217,13 +205,12 @@ static void azalia_init(struct device *dev) u32 codec_mask; u32 reg32; - /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); @@ -268,9 +255,9 @@ static void azalia_init(struct device *dev) /* Codec Initialization Programming Sequence */ /* Take controller out of reset */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); + reg32 = read32(base + HDA_GCTL_REG); + reg32 |= HDA_GCTL_CRST; + write32(base + HDA_GCTL_REG, reg32); /* Wait 1ms */ udelay(1000); diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 1d132ee7ea..6320d2ea9f 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -202,7 +202,6 @@ int intel_early_me_init_done(u8 status) timestamp_add_now(TS_ME_INFORM_DRAM_DONE); } - me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); @@ -220,7 +219,6 @@ int intel_early_me_init_done(u8 status) printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - /* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", me_ack_values[(hfs & 0xe) >> 1]); diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index c130958191..684f830a9b 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -87,7 +87,7 @@ void pch_log_state(void) /* GPIO 0-15 */ for (i = 0; i < 16; i++) { if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } /* SMBUS Wake */ diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index ffd7db3f03..b0f4777d03 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2efddd89a1..df5625afa5 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -520,7 +520,9 @@ static void lpc_init(struct device *dev) report_pch_info(dev); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ pch_enable_ioapic(dev); @@ -732,7 +734,6 @@ static struct device_operations device_ops = { .ops_pci = &pci_dev_ops_pci, }; - /* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and * Intel C200 Series Chipset */ diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 03b954f9fa..3a1ba55cec 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "me.h" #include "pch.h" @@ -28,304 +27,8 @@ #include #endif -/* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] __unused = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; - -/* MMIO base address for MEI interface */ -static u32 *mei_base_address; - -static void mei_dump(void *ptr, int dword, int offset, const char *type) -{ - struct mei_csr *csr; - - if (!CONFIG(DEBUG_INTEL_ME)) - return; - - printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); - - switch (offset) { - case MEI_H_CSR: - case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } - printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); - break; - case MEI_ME_CB_RW: - case MEI_H_CB_WW: - printk(BIOS_SPEW, "CB: 0x%08x\n", dword); - break; - default: - printk(BIOS_SPEW, "0x%08x\n", offset); - break; - } -} - -/* - * ME/MEI access helpers using memcpy to avoid aliasing. - */ - -static inline void mei_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = read32(mei_base_address + (offset/sizeof(u32))); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); -} - -static inline void mei_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + (offset/sizeof(u32)), dword); - mei_dump(ptr, dword, offset, "WRITE"); -} - -#ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} -#endif - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); -} - -static inline void write_cb(u32 dword) -{ - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); -} - -static inline u32 read_cb(void) -{ - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); - return dword; -} - -/* Wait for ME ready bit to be asserted */ -static int mei_wait_for_me_ready(void) -{ - struct mei_csr me; - unsigned int try = ME_RETRY; - - while (try--) { - read_me_csr(&me); - if (me.ready) - return 0; - udelay(ME_DELAY); - } - - printk(BIOS_ERR, "ME: failed to become ready\n"); - return -1; -} - -static void mei_reset(void) -{ - struct mei_csr host; - - if (mei_wait_for_me_ready() < 0) - return; - - /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); - host.reset = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - if (mei_wait_for_me_ready() < 0) - return; - - /* Re-init and indicate host is ready */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); -} - -static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) -{ - struct mei_csr host; - unsigned int ndata, n; - u32 *data; - - /* Number of dwords to write, ignoring MKHI */ - ndata = mei->length >> 2; - - /* Pad non-dword aligned request message length */ - if (mei->length & 3) - ndata++; - if (!ndata) { - printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); - return -1; - } - ndata++; /* Add MEI header */ - - /* - * Make sure there is still room left in the circular buffer. - * Reset the buffer pointers if the requested message will not fit. - */ - read_host_csr(&host); - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); - mei_reset(); - read_host_csr(&host); - } - - /* - * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length - * will fit in the available circular buffer depth. - */ - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); - return -1; - } - - /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); - ndata--; - - /* Write MKHI header */ - mei_write_dword_ptr(mkhi, MEI_H_CB_WW); - ndata--; - - /* Write message data */ - data = req_data; - for (n = 0; n < ndata; ++n) - write_cb(*data++); - - /* Generate interrupt to the ME */ - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); -} - -static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) -{ - struct mei_header mei_rsp; - struct mkhi_header mkhi_rsp; - struct mei_csr me, host; - unsigned int ndata, n; - unsigned int expected; - u32 *data; - - /* Total number of dwords to read from circular buffer */ - expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; - if (rsp_bytes & 3) - expected++; - - /* - * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the - * expected number of dwords are present in the circular buffer. - */ - for (n = ME_RETRY; n; --n) { - read_me_csr(&me); - if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) - break; - udelay(ME_DELAY); - } - if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); - return -1; - } - - /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); - if (!mei_rsp.is_complete) { - printk(BIOS_ERR, "ME: response is not complete\n"); - return -1; - } - - /* Handle non-dword responses and expect at least MKHI header */ - ndata = mei_rsp.length >> 2; - if (mei_rsp.length & 3) - ndata++; - if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); - return -1; - } - - /* Read and verify MKHI response header from the ME */ - mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || - mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); - return -1; - } - ndata--; /* MKHI header has been read */ - - /* Make sure caller passed a buffer with enough space */ - if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); - return -1; - } - - /* Read response data from the circular buffer */ - data = rsp_data; - for (n = 0; n < ndata; ++n) - *data++ = read_cb(); - - /* Tell the ME that we have consumed the response */ - read_host_csr(&host); - host.interrupt_status = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - return mei_wait_for_me_ready(); -} - -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) -{ - if (mei_send_msg(mei, mkhi, req_data) < 0) - return -1; - if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) - return -1; - return 0; -} +/* FIXME: For verification purposes only */ +#include "me_common.c" /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) @@ -439,11 +142,10 @@ static void intel_me7_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + update_mei_base_address(); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) + if (!is_mei_base_address_valid()) return; /* Make sure ME is in a mode that expects EOP */ @@ -549,94 +251,13 @@ static me_bios_path intel_me_path(struct device *dev) return path; } -/* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) -{ - struct resource *res; - struct mei_csr host; - - /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res || res->base == 0 || res->size == 0) { - printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); - return -1; - } - mei_base_address = (u32 *)(uintptr_t)res->base; - - /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - /* Clean up status for next message */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); - - return 0; -} - -/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) -{ - struct me_heres status; - u32 extend[8] = {0}; - int i, count = 0; - - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); - if (!status.extend_feature_present) { - printk(BIOS_ERR, "ME: Extend Feature not present\n"); - return -1; - } - - if (!status.extend_reg_valid) { - printk(BIOS_ERR, "ME: Extend Register not valid\n"); - return -1; - } - - switch (status.extend_reg_algorithm) { - case PCI_ME_EXT_SHA1: - count = 5; - printk(BIOS_DEBUG, "ME: Extend SHA-1: "); - break; - case PCI_ME_EXT_SHA256: - count = 8; - printk(BIOS_DEBUG, "ME: Extend SHA-256: "); - break; - default: - printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); - return -1; - } - - for (i = 0; i < count; ++i) { - extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend[i]); - } - printk(BIOS_DEBUG, "\n"); - -#if CONFIG(CHROMEOS) - /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif - - return 0; -} - -/* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) -{ - dev->enabled = 0; - pch_enable(dev); -} - /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); switch (path) { case ME_S3WAKE_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661041..c26078ff6c 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -197,7 +197,6 @@ struct me_fw_version { u16 recovery_hot_fix; } __packed; - #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index ff94a88e78..4d232ede9c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "me.h" #include "pch.h" @@ -28,302 +27,33 @@ #include #endif -/* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] __unused = { - [ME_NORMAL_BIOS_PATH] = "Normal", - [ME_S3WAKE_BIOS_PATH] = "S3 Wake", - [ME_ERROR_BIOS_PATH] = "Error", - [ME_RECOVERY_BIOS_PATH] = "Recovery", - [ME_DISABLE_BIOS_PATH] = "Disable", - [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", -}; +/* FIXME: For verification purposes only */ +#include "me_common.c" -/* MMIO base address for MEI interface */ -static u32 *mei_base_address; - -static void mei_dump(void *ptr, int dword, int offset, const char *type) +/* Send END OF POST message to the ME */ +static int __unused mkhi_end_of_post(void) { - struct mei_csr *csr; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; - if (!CONFIG(DEBUG_INTEL_ME)) - return; + u32 eop_ack; - printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); - - switch (offset) { - case MEI_H_CSR: - case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } - printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); - break; - case MEI_ME_CB_RW: - case MEI_H_CB_WW: - printk(BIOS_SPEW, "CB: 0x%08x\n", dword); - break; - default: - printk(BIOS_SPEW, "0x%08x\n", offset); - break; - } -} - -/* - * ME/MEI access helpers using memcpy to avoid aliasing. - */ - -static inline void mei_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = read32(mei_base_address + (offset/sizeof(u32))); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); -} - -static inline void mei_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + (offset/sizeof(u32)), dword); - mei_dump(ptr, dword, offset, "WRITE"); -} - -#ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} -#endif - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); -} - -static inline void write_cb(u32 dword) -{ - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); -} - -static inline u32 read_cb(void) -{ - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); - return dword; -} - -/* Wait for ME ready bit to be asserted */ -static int mei_wait_for_me_ready(void) -{ - struct mei_csr me; - unsigned int try = ME_RETRY; - - while (try--) { - read_me_csr(&me); - if (me.ready) - return 0; - udelay(ME_DELAY); - } - - printk(BIOS_ERR, "ME: failed to become ready\n"); - return -1; -} - -static void mei_reset(void) -{ - struct mei_csr host; - - if (mei_wait_for_me_ready() < 0) - return; - - /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); - host.reset = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - if (mei_wait_for_me_ready() < 0) - return; - - /* Re-init and indicate host is ready */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); -} - -static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data) -{ - struct mei_csr host; - unsigned int ndata, n; - u32 *data; - - /* Number of dwords to write, ignoring MKHI */ - ndata = mei->length >> 2; - - /* Pad non-dword aligned request message length */ - if (mei->length & 3) - ndata++; - if (!ndata) { - printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); - return -1; - } - ndata++; /* Add MEI header */ - - /* - * Make sure there is still room left in the circular buffer. - * Reset the buffer pointers if the requested message will not fit. - */ - read_host_csr(&host); - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); - mei_reset(); - read_host_csr(&host); - } - - /* - * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length - * will fit in the available circular buffer depth. - */ - if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { - printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __func__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; } - /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); - ndata--; - - /* Write MKHI header */ - mei_write_dword_ptr(mkhi, MEI_H_CB_WW); - ndata--; - - /* Write message data */ - data = req_data; - for (n = 0; n < ndata; ++n) - write_cb(*data++); - - /* Generate interrupt to the ME */ - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - /* Make sure ME is ready after sending request data */ - return mei_wait_for_me_ready(); -} - -static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) -{ - struct mei_header mei_rsp; - struct mkhi_header mkhi_rsp; - struct mei_csr me, host; - unsigned int ndata, n; - unsigned int expected; - u32 *data; - - /* Total number of dwords to read from circular buffer */ - expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; - if (rsp_bytes & 3) - expected++; - - /* - * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the - * expected number of dwords are present in the circular buffer. - */ - for (n = ME_RETRY; n; --n) { - read_me_csr(&me); - if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) - break; - udelay(ME_DELAY); - } - if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); - return -1; - } - - /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); - if (!mei_rsp.is_complete) { - printk(BIOS_ERR, "ME: response is not complete\n"); - return -1; - } - - /* Handle non-dword responses and expect at least MKHI header */ - ndata = mei_rsp.length >> 2; - if (mei_rsp.length & 3) - ndata++; - if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); - return -1; - } - - /* Read and verify MKHI response header from the ME */ - mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || - mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); - return -1; - } - ndata--; /* MKHI header has been read */ - - /* Make sure caller passed a buffer with enough space */ - if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); - return -1; - } - - /* Read response data from the circular buffer */ - data = rsp_data; - for (n = 0; n < ndata; ++n) - *data++ = read_cb(); - - /* Tell the ME that we have consumed the response */ - read_host_csr(&host); - host.interrupt_status = 1; - host.interrupt_generate = 1; - write_host_csr(&host); - - return mei_wait_for_me_ready(); -} - -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) -{ - if (mei_send_msg(mei, mkhi, req_data) < 0) - return -1; - if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) - return -1; + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); return 0; } @@ -398,33 +128,6 @@ static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("Wireless LAN (WLAN)", cap->wlan); } -/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - #ifdef __SIMPLE_DEVICE__ void intel_me8_finalize_smm(void) @@ -432,11 +135,10 @@ void intel_me8_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = (void *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + update_mei_base_address(); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) + if (!is_mei_base_address_valid()) return; /* Make sure ME is in a mode that expects EOP */ @@ -534,91 +236,6 @@ static me_bios_path intel_me_path(struct device *dev) return path; } -/* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) -{ - struct resource *res; - struct mei_csr host; - - /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res || res->base == 0 || res->size == 0) { - printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); - return -1; - } - mei_base_address = (u32 *)(uintptr_t)res->base; - - /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - /* Clean up status for next message */ - read_host_csr(&host); - host.interrupt_generate = 1; - host.ready = 1; - host.reset = 0; - write_host_csr(&host); - - return 0; -} - -#if CONFIG(CHROMEOS) -#include -#endif - -/* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) -{ - struct me_heres status; - u32 extend[8] = {0}; - int i, count = 0; - - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); - if (!status.extend_feature_present) { - printk(BIOS_ERR, "ME: Extend Feature not present\n"); - return -1; - } - - if (!status.extend_reg_valid) { - printk(BIOS_ERR, "ME: Extend Register not valid\n"); - return -1; - } - - switch (status.extend_reg_algorithm) { - case PCI_ME_EXT_SHA1: - count = 5; - printk(BIOS_DEBUG, "ME: Extend SHA-1: "); - break; - case PCI_ME_EXT_SHA256: - count = 8; - printk(BIOS_DEBUG, "ME: Extend SHA-256: "); - break; - default: - printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); - return -1; - } - - for (i = 0; i < count; ++i) { - extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend[i]); - } - printk(BIOS_DEBUG, "\n"); - -#if CONFIG(CHROMEOS) - /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif - - return 0; -} - -/* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) -{ - dev->enabled = 0; - pch_enable(dev); -} - static int intel_me_read_mbp(me_bios_payload *mbp_data); /* Check whether ME is present and do basic init */ @@ -628,7 +245,7 @@ static void intel_me_init(struct device *dev) me_bios_payload mbp_data; /* Do initial setup and determine the BIOS path */ - printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); switch (path) { case ME_S3WAKE_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c new file mode 100644 index 0000000000..cdfd83224c --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -0,0 +1,420 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "me.h" +#include "pch.h" + +/* Path that the BIOS should take based on ME state */ +static const char *me_bios_path_values[] __unused = { + [ME_NORMAL_BIOS_PATH] = "Normal", + [ME_S3WAKE_BIOS_PATH] = "S3 Wake", + [ME_ERROR_BIOS_PATH] = "Error", + [ME_RECOVERY_BIOS_PATH] = "Recovery", + [ME_DISABLE_BIOS_PATH] = "Disable", + [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", +}; + +static inline const char *const me_get_bios_path_string(int path) +{ + return me_bios_path_values[path]; +} + +/* MMIO base address for MEI interface */ +static u32 *mei_base_address; + +static void mei_dump(void *ptr, int dword, int offset, const char *type) +{ + struct mei_csr *csr; + + if (!CONFIG(DEBUG_INTEL_ME)) + return; + + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); + + switch (offset) { + case MEI_H_CSR: + case MEI_ME_CSR_HA: + csr = ptr; + if (!csr) { + printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); + break; + } + printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); + break; + case MEI_ME_CB_RW: + case MEI_H_CB_WW: + printk(BIOS_SPEW, "CB: 0x%08x\n", dword); + break; + default: + printk(BIOS_SPEW, "0x%08x\n", offset); + break; + } +} + +/* + * ME/MEI access helpers using memcpy to avoid aliasing. + */ + +static inline void mei_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = read32(mei_base_address + (offset / sizeof(u32))); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "READ"); +} + +static inline void mei_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + write32(mei_base_address + (offset / sizeof(u32)), dword); + mei_dump(ptr, dword, offset, "WRITE"); +} + +#ifndef __SIMPLE_DEVICE__ +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +{ + u32 dword = pci_read_config32(dev, offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "PCI READ"); +} +#endif + +static inline void read_host_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_H_CSR); +} + +static inline void write_host_csr(struct mei_csr *csr) +{ + mei_write_dword_ptr(csr, MEI_H_CSR); +} + +static inline void read_me_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_ME_CSR_HA); +} + +static inline void write_cb(u32 dword) +{ + write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); + mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); +} + +static inline u32 read_cb(void) +{ + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); + mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + return dword; +} + +/* Wait for ME ready bit to be asserted */ +static int mei_wait_for_me_ready(void) +{ + struct mei_csr me; + unsigned int try = ME_RETRY; + + while (try--) { + read_me_csr(&me); + if (me.ready) + return 0; + udelay(ME_DELAY); + } + + printk(BIOS_ERR, "ME: failed to become ready\n"); + return -1; +} + +static void mei_reset(void) +{ + struct mei_csr host; + + if (mei_wait_for_me_ready() < 0) + return; + + /* Reset host and ME circular buffers for next message */ + read_host_csr(&host); + host.reset = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + if (mei_wait_for_me_ready() < 0) + return; + + /* Re-init and indicate host is ready */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); +} + +static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data) +{ + struct mei_csr host; + unsigned int ndata, n; + u32 *data; + + /* Number of dwords to write, ignoring MKHI */ + ndata = mei->length >> 2; + + /* Pad non-dword aligned request message length */ + if (mei->length & 3) + ndata++; + if (!ndata) { + printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); + return -1; + } + ndata++; /* Add MEI header */ + + /* + * Make sure there is still room left in the circular buffer. + * Reset the buffer pointers if the requested message will not fit. + */ + read_host_csr(&host); + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); + mei_reset(); + read_host_csr(&host); + } + + /* + * This implementation does not handle splitting large messages + * across multiple transactions. Ensure the requested length + * will fit in the available circular buffer depth. + */ + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", + ndata + 2, host.buffer_depth); + return -1; + } + + /* Write MEI header */ + mei_write_dword_ptr(mei, MEI_H_CB_WW); + ndata--; + + /* Write MKHI header */ + mei_write_dword_ptr(mkhi, MEI_H_CB_WW); + ndata--; + + /* Write message data */ + data = req_data; + for (n = 0; n < ndata; ++n) + write_cb(*data++); + + /* Generate interrupt to the ME */ + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); + + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); +} + +static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) +{ + struct mei_header mei_rsp; + struct mkhi_header mkhi_rsp; + struct mei_csr me, host; + unsigned int ndata, n; + unsigned int expected; + u32 *data; + + /* Total number of dwords to read from circular buffer */ + expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; + if (rsp_bytes & 3) + expected++; + + /* + * The interrupt status bit does not appear to indicate that the + * message has actually been received. Instead we wait until the + * expected number of dwords are present in the circular buffer. + */ + for (n = ME_RETRY; n; --n) { + read_me_csr(&me); + if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) + break; + udelay(ME_DELAY); + } + if (!n) { + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); + return -1; + } + + /* Read and verify MEI response header from the ME */ + mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + if (!mei_rsp.is_complete) { + printk(BIOS_ERR, "ME: response is not complete\n"); + return -1; + } + + /* Handle non-dword responses and expect at least MKHI header */ + ndata = mei_rsp.length >> 2; + if (mei_rsp.length & 3) + ndata++; + if (ndata != (expected - 1)) { + printk(BIOS_ERR, "ME: response is missing data %d != %d\n", + ndata, (expected - 1)); + return -1; + } + + /* Read and verify MKHI response header from the ME */ + mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); + if (!mkhi_rsp.is_response || + mkhi->group_id != mkhi_rsp.group_id || + mkhi->command != mkhi_rsp.command) { + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); + return -1; + } + ndata--; /* MKHI header has been read */ + + /* Make sure caller passed a buffer with enough space */ + if (ndata != (rsp_bytes >> 2)) { + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); + return -1; + } + + /* Read response data from the circular buffer */ + data = rsp_data; + for (n = 0; n < ndata; ++n) + *data++ = read_cb(); + + /* Tell the ME that we have consumed the response */ + read_host_csr(&host); + host.interrupt_status = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + return mei_wait_for_me_ready(); +} + +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) +{ + if (mei_send_msg(mei, mkhi, req_data) < 0) + return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) + return -1; + return 0; +} + +#ifdef __SIMPLE_DEVICE__ + +static inline void update_mei_base_address(void) +{ + uint32_t reg32 = pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *)(uintptr_t)reg32; +} + +static inline bool is_mei_base_address_valid(void) +{ + return mei_base_address && mei_base_address != (u32 *)0xfffffff0; +} + +#else + +/* Prepare ME for MEI messages */ +static int intel_mei_setup(struct device *dev) +{ + struct resource *res; + struct mei_csr host; + + /* Find the MMIO base for the ME interface */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res || res->base == 0 || res->size == 0) { + printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); + return -1; + } + mei_base_address = (u32 *)(uintptr_t)res->base; + + /* Ensure Memory and Bus Master bits are set */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Clean up status for next message */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); + + return 0; +} + +#if CONFIG(CHROMEOS) +#include +#endif + +/* Read the Extend register hash of ME firmware */ +static int intel_me_extend_valid(struct device *dev) +{ + struct me_heres status; + u32 extend[8] = {0}; + int i, count = 0; + + pci_read_dword_ptr(dev, &status, PCI_ME_HERES); + if (!status.extend_feature_present) { + printk(BIOS_ERR, "ME: Extend Feature not present\n"); + return -1; + } + + if (!status.extend_reg_valid) { + printk(BIOS_ERR, "ME: Extend Register not valid\n"); + return -1; + } + + switch (status.extend_reg_algorithm) { + case PCI_ME_EXT_SHA1: + count = 5; + printk(BIOS_DEBUG, "ME: Extend SHA-1: "); + break; + case PCI_ME_EXT_SHA256: + count = 8; + printk(BIOS_DEBUG, "ME: Extend SHA-256: "); + break; + default: + printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", + status.extend_reg_algorithm); + return -1; + } + + for (i = 0; i < count; ++i) { + extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); + printk(BIOS_DEBUG, "%08x", extend[i]); + } + printk(BIOS_DEBUG, "\n"); + +#if CONFIG(CHROMEOS) + /* Save hash in NVS for the OS to verify */ + chromeos_set_me_hash(extend, count); +#endif + + return 0; +} + +/* Hide the ME virtual PCI devices */ +static void intel_me_hide(struct device *dev) +{ + dev->enabled = 0; + pch_enable(dev); +} + +#endif diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 7b0662b4fe..82b95f69e4 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -41,7 +41,7 @@ int pch_silicon_type(void) return pch_type; } -int pch_silicon_supported(int type, int rev) +static int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); int cur_rev = pch_silicon_revision(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ed75505f65..eff08581a0 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -21,11 +21,10 @@ * It does not matter where we put the SMBus I/O base, as long as we * keep it consistent and don't interfere with other devices. Stage2 * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE * again. But handling static BARs is a generic problem that should be * solved in the device allocator. */ -#define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 @@ -43,7 +42,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); @@ -156,8 +154,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ @@ -231,26 +228,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define CIR0 0x0050 /* 32bit */ #define TCLOCKDN (1u << 31) -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 2eff162bd5..f6bffbb3b9 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -216,8 +216,7 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - pci_update_config16(dev, PCI_BRIDGE_CONTROL, - ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 63801a213e..484f0f11a2 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -108,7 +108,8 @@ static void sata_init(struct device *dev) /* SATA configuration */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* AHCI */ if (sata_mode == 0) { diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index dcd2724632..b251596667 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_read_byte(res->base, device, address); } @@ -47,7 +48,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_write_byte(res->base, device, address, val); } @@ -60,7 +61,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 8af14283c3..40672f87cd 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -103,6 +104,7 @@ static void xhci_sleep(u8 slp_typ) xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; + /* FIXME: This looks broken (conditions are always false) */ if ((xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); if ((xhci_bar + 0x4D0) & 1) @@ -140,7 +142,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) @@ -191,6 +192,11 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (struct global_nvs *)((u32)state->rbx); + struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; + if (smm_region_overlaps_handler(&r)) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 9356a2be16..3030d25757 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_SMBUS def_bool n select HAVE_DEBUG_SMBUS @@ -97,3 +100,8 @@ config INTEL_CHIPSET_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE + +config FIXED_SMBUS_IO_BASE + hex + depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS + default 0x400 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa99c..1ededd23ec 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -5,6 +5,8 @@ subdirs-y += firmware all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/common/early_smbus.c similarity index 78% rename from src/southbridge/intel/bd82x6x/early_smbus.c rename to src/southbridge/intel/common/early_smbus.c index 7d8503bb7d..d65b4aaf81 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/common/early_smbus.c @@ -1,28 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include -#include "pch.h" +#include "early_smbus.h" uintptr_t smbus_base(void) { - return SMBUS_IO_BASE; + return CONFIG_FIXED_SMBUS_IO_BASE; } int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + const pci_devfn_t dev = PCI_DEV_SMBUS; /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h new file mode 100644 index 0000000000..d6a7cbbcce --- /dev/null +++ b/src/southbridge/intel/common/early_smbus.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H + +#include + +#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) + +#define SMB_BASE PCI_BASE_ADDRESS_4 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */ diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 00c3a0ef87..59d429747c 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include @@ -48,5 +48,5 @@ void intel_pch_finalize_smm(void) write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); - outb(POST_OS_BOOT, CONFIG_POST_IO_PORT); + post_code(POST_OS_BOOT); } diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index 5556aba3a0..247bf5df7f 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "pciehp.h" @@ -121,7 +122,7 @@ static void slot_dev_read_resources(struct device *dev) { struct resource *resource; - resource = new_resource(dev, 0x10); + resource = new_resource(dev, PCI_BASE_ADDRESS_0); resource->size = 1 << 23; resource->align = 22; resource->gran = 22; diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index d8196f8c72..02a8375e9a 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -94,7 +94,6 @@ void dump_smi_status(u32 smi_sts) printk(BIOS_DEBUG, "\n"); } - /** * @brief read and clear GPE0_STS * @return GPE0_STS register @@ -158,7 +157,6 @@ u32 reset_tco_status(void) return reg32; } - void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -190,7 +188,6 @@ void smi_set_eos(void) write_pmbase8(SMI_EN, reg8); } - void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 52b83dd264..c1756474ae 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -27,7 +27,6 @@ #define GPI_IS_SCI 0x02 #define GPI_IS_NMI 0x03 - #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 06d7c74e58..0dbc48cea5 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 49e306f667..7610aa1102 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -95,7 +95,6 @@ __weak void southbridge_smm_xhci_sleep(u8 slp_type) { } - static void southbridge_smi_sleep(void) { u8 reg8; @@ -388,8 +387,6 @@ static void southbridge_smi_mc(void) printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } - - static void southbridge_smi_tco(void) { u32 tco_sts; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 380940c739..757f0acc48 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -718,7 +718,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, return 0; } - static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index c302accb04..5aeff4ecc9 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -50,7 +50,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * 2 0: VGA is ok to probe * 3 1: MSI are not supported */ - fadt->iapc_boot_arch = 0xb; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042 | + ACPI_FADT_MSI_NOT_SUPPORTED; /* * bit meaning * 0 WBINVD @@ -101,30 +102,31 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) * 18 FORCE_APIC_CLUSTER_MODEL * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE */ - fadt->flags |= 0xa5; + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index e20cb5f1fb..2a3b167944 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -39,7 +39,7 @@ void i82371eb_early_init(void); #define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ -/* Power management (ACPI) */ +/* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ #define PWRBTN_EN (1<<8) @@ -49,8 +49,7 @@ void i82371eb_early_init(void); #define SUS_TYP_MSK (7<<10) #define SUS_TYP_S0 (5<<10) #define SUS_TYP_S1 (4<<10) -#define SUS_TYP_S2 (3<<10) -//#define SUS_TYP_S2>---(2<<10) +#define SUS_TYP_S2 (3<<10) /* S2 may also map as 2<<10 */ #define SUS_TYP_S3 (1<<10) #define SUS_TYP_S5 (0<<10) #define SCI_EN (1<<0) @@ -64,11 +63,11 @@ void i82371eb_early_init(void); #define EXTSMI_STS (1<<10) #define GSTBY_STS (1<<8) #define GP_STS (1<<7) -#define BM1_STS (1<<6) +#define PM1_STS (1<<6) #define APM_STS (1<<5) #define DEV_STS (1<<4) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define LEGACY_USB_STS (1<<1) +#define BIOS_STS (1<<0) #define DEVSTS 0x1c /* Device Status */ #define GLBEN 0x20 /* Global Enable */ #define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ @@ -86,10 +85,22 @@ void i82371eb_early_init(void); #define GPO2 0x36 #define GPO3 0x37 +/* Power management (ACPI) PCI registers */ #define PMBA 0x40 /* Power management base address */ #define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE +#define DEVRESA 0x5c /* Device resource A */ +#define DEVRESB 0x60 /* Device resource B */ +#define DEVRESC 0x64 /* Device resource C */ +#define DEVRESD 0x52 /* Device resource D */ +#define DEVRESE 0x68 /* Device resource E */ +#define DEVRESF 0x6c /* Device resource F */ +#define DEVRESG 0x70 /* Device resource G */ +#define DEVRESH 0x74 /* Device resource H */ +#define DEVRESI 0x78 /* Device resource I */ +#define DEVRESJ 0x7c /* Device resource J */ #define PMREGMISC 0x80 /* Miscellaneous power management */ +#define PMIOSE (1 << 0) /* PM I/O Space Enable */ /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ @@ -105,7 +116,5 @@ void i82371eb_early_init(void); #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ #define ISA (1 << 0) /* Select ISA */ -#define EIO (0 << 0) /* Select EIO */ -#define PMIOSE (1 << 0) /* PM I/O Space Enable */ #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 9064a1238c..988d7418d3 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -92,7 +92,6 @@ static void pwrmgt_read_resources(struct device *dev) IORESOURCE_RESERVE; } - static const struct smbus_bus_operations lops_smbus_bus = { }; diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 5bea98c6bd..840aeb42dc 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -6,6 +6,7 @@ config SOUTHBRIDGE_INTEL_I82801DX select IOAPIC select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index 7adfa9618d..d6a6bc9864 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -33,7 +33,6 @@ #define MBAR 0x14 #define SEC_CODEC 0x40 - /* FIXME. This table is probably mainboard specific */ static u16 ac97_function[16*2][4] = { { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }, diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6649c33b8b..76ef1b8a15 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include #include #include "i82801dx.h" @@ -9,22 +7,3 @@ void i82801dx_early_init(void) { enable_smbus(); } - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* set smbus iobase */ - pci_write_config32(dev, 0x20, base | 1); - /* Set smbus enable */ - pci_write_config8(dev, 0x40, 0x01); - /* Set smbus iospace enable */ - pci_write_config16(dev, 0x4, 0x01); - - return 0; -} diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index b99bd34947..84ea73ad9c 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -20,7 +20,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; if (permanent_smi_handler()) { @@ -46,37 +45,37 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; - fadt->iapc_boot_arch = 0x03; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0; } diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index cf852740f9..9864720ad0 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -46,8 +46,6 @@ void aseg_smm_lock(void); /* IDE_TIM bits */ #define IDE_DECODE_ENABLE (1 << 15) - - #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 #define GEN_CNTL 0xd0 @@ -93,9 +91,6 @@ void aseg_smm_lock(void); #define RTC_FAILED (1 <<2) - -#define SMBUS_IO_BASE 0x400 - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 3a71dbcf6b..dec12666fc 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -253,7 +253,9 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); i82801dx_enable_acpi(dev); /* IO APIC initialization. */ diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 26bbbe143d..dd993cedb0 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include #include #include @@ -13,7 +12,6 @@ #include #include "i82801dx.h" - void northbridge_write_smram(u8 smram); /* For intel/e7505. */ @@ -98,7 +96,6 @@ static void dump_smi_status(u32 smi_sts) printk(BIOS_DEBUG, "\n"); } - /** * @brief read and clear GPE0_STS * @return GPE0_STS register @@ -138,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts) printk(BIOS_DEBUG, "\n"); } - /** * @brief read and clear ALT_GP_SMI_STS * @return ALT_GP_SMI_STS register @@ -164,8 +160,6 @@ static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) printk(BIOS_DEBUG, "\n"); } - - /** * @brief read and clear TCOx_STS * @return TCOx_STS registers @@ -184,7 +178,6 @@ static u32 reset_tco_status(void) return reg32; } - static void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -204,8 +197,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } - - /** * @brief Set the EOS bit */ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index af56941407..19fe5bba2a 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -96,7 +96,6 @@ static void dump_smi_status(u32 smi_sts) printk(BIOS_DEBUG, "\n"); } - /** * @brief read and clear GPE0_STS * @return GPE0_STS register @@ -136,7 +135,6 @@ static void dump_gpe0_status(u32 gpe0_sts) printk(BIOS_DEBUG, "\n"); } - /** * @brief read and clear TCOx_STS * @return TCOx_STS registers @@ -155,7 +153,6 @@ static u32 reset_tco_status(void) return reg32; } - static void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -222,7 +219,6 @@ static void busmaster_disable_on_bus(int bus) } } - static void southbridge_smi_sleep(void) { u8 reg8; @@ -389,8 +385,6 @@ static void southbridge_smi_mc(void) printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } - - static void southbridge_smi_tco(void) { u32 tco_sts; diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 56a6fa989e..50f7c6093c 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -8,6 +8,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 1630f939d2..11a9c0007d 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -23,7 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c romstage-y += early_init.c -romstage-y += early_smbus.c romstage-y += early_cir.c endif diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index cc6e376130..5230ace8ef 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -34,7 +34,6 @@ #define MBAR 0x14 #define SEC_CODEC 0x40 - /* FIXME. This table is probably mainboard specific */ static u16 ac97_function[16*2][4] = { { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }, diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 5a1f204303..1f9e701e84 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -73,7 +73,7 @@ Device (LPCB) If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ Device (LPCB) { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } @@ -167,8 +167,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } @@ -216,32 +214,4 @@ Device (LPCB) Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 16db17595d..7c4ef345de 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -21,9 +21,9 @@ Device (USB1) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -40,7 +40,6 @@ Device (USB1) } } - // USB Controller 0:1d.1 Device (USB2) @@ -60,9 +59,9 @@ Device (USB2) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -80,7 +79,6 @@ Device (USB2) } - // USB Controller 0:1d.2 Device (USB3) @@ -100,9 +98,9 @@ Device (USB3) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -120,7 +118,6 @@ Device (USB3) } - // USB Controller 0:1d.3 Device (USB4) @@ -140,9 +137,9 @@ Device (USB4) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U4WE) + U4WE = 3 } Else { - Store (0, U4WE) + U4WE = 0 } } @@ -160,7 +157,6 @@ Device (USB4) } - // EHCI Controller 0:1d.7 Device (EHC1) diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index cea75bd901..99582b41d6 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801gx.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -46,16 +42,16 @@ static int codec_detect(u8 *base) { u32 reg32; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -75,12 +71,12 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -88,9 +84,9 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -108,23 +104,22 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -145,18 +140,21 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; - - reg32 = read32(base + 0x64); + } /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -171,7 +169,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -182,6 +180,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -194,37 +193,21 @@ static void azalia_init(struct device *dev) struct resource *res; u32 codec_mask; u8 reg8; - u32 reg32; // ESD - reg32 = pci_read_config32(dev, 0x134); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x134, reg32); + pci_update_config32(dev, 0x134, ~(0xff << 16), 2 << 16); // Link1 description - reg32 = pci_read_config32(dev, 0x140); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x140, reg32); + pci_update_config32(dev, 0x140, ~(0xff << 16), 2 << 16); // Port VC0 Resource Control Register - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~(0xff << 0), 1); // VCi traffic class - reg8 = pci_read_config8(dev, 0x44); - reg8 |= (7 << 0); // TC7 - pci_write_config8(dev, 0x44, reg8); + pci_or_config8(dev, 0x44, 7 << 0); // TC7 // VCi Resource Control - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - reg32 |= (1 << 24); // VCi ID - reg32 |= (0x80 << 0); // VCi map - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -244,21 +227,18 @@ static void azalia_init(struct device *dev) reg8 = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a913873348..72281ea5f3 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -61,12 +61,8 @@ void i82801gx_setup_bars(void) #if ENV_ROMSTAGE void i82801gx_early_init(void) { - uint8_t reg8; - uint32_t reg32; - enable_smbus(); - /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801gx_setup_bars(); @@ -84,22 +80,14 @@ void i82801gx_early_init(void) pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD); /* USB transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17)); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27)); /* Enable IOAPIC */ RCBA8(OIC) = 0x03; diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c deleted file mode 100644 index 48d9d58acc..0000000000 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "i82801gx.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, PCI_DEVICE_ID) != 0x27da) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index fbb6bf1868..86330f88e1 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -7,11 +7,10 @@ * It does not matter where we put the SMBus I/O base, as long as we * keep it consistent and don't interfere with other devices. Stage2 * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE * again. But handling static BARs is a generic problem that should be * solved in the device allocator. */ -#define SMBUS_IO_BASE 0x0400 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9b32f6cfd9..eb59eb031c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -247,18 +247,13 @@ static void i82801gx_power_options(struct device *dev) static void i82801gx_configure_cstates(struct device *dev) { - u8 reg8; - - reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration - reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown - pci_write_config8(dev, 0xa9, reg8); + // Enable Popup & Popdown + pci_or_config8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2)); // Set Deeper Sleep configuration to recommended values - reg8 = pci_read_config8(dev, 0xaa); - reg8 &= 0xf0; - reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us - reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us - pci_write_config8(dev, 0xaa, reg8); + // Deeper Sleep to Stop CPU: 34-40us + // Deeper Sleep to Sleep: 15us + pci_update_config8(dev, 0xaa, 0xf0, (2 << 2) | (2 << 0)); } static void i82801gx_rtc_init(struct device *dev) @@ -347,7 +342,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "i82801gx: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ i82801gx_enable_ioapic(dev); @@ -414,7 +411,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 74724383a2..d72bd81ebb 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -10,29 +10,21 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); - /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 &= ~PCI_BRIDGE_CTL_SERR; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + /* Disable parity error response and SERR */ + pci_and_config16(dev, PCI_BRIDGE_CONTROL, + ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR)); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); + pci_update_config8(dev, SMLT, 0x07, 0x04 << 3); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 6c0ca5d8e3..8650673557 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -41,7 +41,6 @@ static inline int root_port_number(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); @@ -52,39 +51,25 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Enable IO xAPIC on this PCIe port */ - reg32 = pci_read_config32(dev, 0xd8); - reg32 |= (1 << 7); - pci_write_config32(dev, 0xd8, reg32); + pci_or_config32(dev, 0xd8, 1 << 7); /* Enable Backbone Clock Gating */ - reg32 = pci_read_config32(dev, 0xe1); - reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); - pci_write_config32(dev, 0xe1, reg32); + pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); /* Set VC0 transaction class */ - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~0x000000ff, 1); /* Mask completion timeouts */ - reg32 = pci_read_config32(dev, 0x148); - reg32 |= (1 << 14); - pci_write_config32(dev, 0x148, reg32); + pci_or_config32(dev, 0x148, 1 << 14); /* Enable common clock configuration */ // Are there cases when we don't want that? - reg16 = pci_read_config16(dev, 0x50); - reg16 |= (1 << 6); - pci_write_config16(dev, 0x50, reg16); + pci_or_config16(dev, 0x50, 1 << 6); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16); diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 6efdef76cb..abb0e2e03e 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -59,11 +59,10 @@ void sata_enable(struct device *dev) if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ - pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); + pci_update_config8(dev, SATA_MAP, (u8)~0xc3, 0x40); } else { - /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); + /* Set map to ide */ + pci_and_config8(dev, SATA_MAP, (u8)~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -71,7 +70,6 @@ void sata_enable(struct device *dev) static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u8 ports; /* Get the chip configuration */ @@ -88,17 +86,17 @@ static void sata_init(struct device *dev) ports = get_ich7_sata_ports(); /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); switch (config->sata_mode) { case SATA_MODE_IDE_LEGACY_COMBINED: printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0); + /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); pci_write_config8(dev, 0x09, 0x80); @@ -147,9 +145,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -190,23 +186,15 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0xa0, 0x78); pci_write_config8(dev, 0xa6, 0x22); pci_write_config8(dev, 0xa0, 0x88); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0c0c0; - reg32 |= 0x1b1b1212; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0c0c0, 0x1b1b1212); pci_write_config8(dev, 0xa0, 0x8c); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0ff00; - reg32 |= 0x121200aa; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0ff00, 0x121200aa); pci_write_config8(dev, 0xa0, 0x00); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); /* Sata Initialization Register */ - reg32 = pci_read_config32(dev, SATA_IR); - reg32 |= SCRD; // due to some bug - pci_write_config32(dev, SATA_IR, reg32); + pci_or_config32(dev, SATA_IR, SCRD); // due to some bug } static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index e1e53c22de..5915f3d15b 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include "i82801gx.h" @@ -16,7 +17,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_read_byte(res->base, device, address); } @@ -29,7 +30,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_write_byte(res->base, device, address, data); } @@ -41,7 +42,7 @@ static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *bu device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_block_write(res->base, device, cmd, bytes, buf); } @@ -53,11 +54,10 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_block_read(res->base, device, cmd, bytes, buf); } - static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, @@ -68,7 +68,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 562dae3a97..f1be5c200b 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -58,7 +58,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8ce57dfd13..08ba3d7830 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -9,8 +9,6 @@ static void usb_init(struct device *dev) { - u8 reg8; - /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); @@ -20,9 +18,7 @@ static void usb_init(struct device *dev) pci_write_config8(dev, 0xca, 0x00); // Yes. Another Erratum - reg8 = pci_read_config8(dev, 0xca); - reg8 |= (1 << 0); - pci_write_config8(dev, 0xca, reg8); + pci_or_config8(dev, 0xca, 1 << 0); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7a0a..b01af96c60 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -7,6 +7,7 @@ #include "i82801gx.h" #include #include +#include #include static void usb_ehci_init(struct device *dev) @@ -14,30 +15,22 @@ static void usb_ehci_init(struct device *dev) struct resource *res; u8 *base; u32 reg32; - u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 31) | (1 << 27)); - reg32 = pci_read_config32(dev, 0xfc); - reg32 &= ~(3 << 2); - reg32 |= (2 << 2) | (1 << 29) | (1 << 17); - pci_write_config32(dev, 0xfc, reg32); + pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); base = res2mmio(res, 0, 0); reg32 = read32(base + 0x24) | (1 << 2); write32(base + 0x24, reg32); /* workaround */ - reg8 = pci_read_config8(dev, 0x84); - reg8 |= (1 << 4); - pci_write_config8(dev, 0x84, reg8); + pci_or_config8(dev, 0x84, 1 << 4); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index bd2cd0f4cb..e1405cfbe0 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -14,6 +14,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 91ac65b537..516a344e62 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -7,10 +7,9 @@ bootblock-y += early_init.c romstage-y += dmi_setup.c romstage-y += early_init.c -romstage-y += early_smbus.c +ramstage-y += azalia.c ramstage-y += fadt.c -ramstage-y += hdaudio.c ramstage-y += i82801ix.c ramstage-y += lpc.c ramstage-y += pci.c diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 5a1f204303..b93fa96d23 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -167,8 +167,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } @@ -216,32 +214,4 @@ Device (LPCB) Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/azalia.c similarity index 78% rename from src/southbridge/intel/i82801ix/hdaudio.c rename to src/southbridge/intel/i82801ix/azalia.c index c954f9c6cd..1d1405ea46 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801ix.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -46,16 +42,16 @@ static int codec_detect(u8 *base) { u32 reg32; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -75,12 +71,12 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -88,9 +84,9 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -108,23 +104,22 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -145,18 +140,21 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; - - reg32 = read32(base + 0x64); + } /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -171,7 +169,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -182,6 +180,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -191,7 +190,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; @@ -228,12 +227,12 @@ static void azalia_init(struct device *dev) /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index ffc57f2e1a..cbb52c4a6c 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_BCR) = 0x45; RCBA32(RCBA_CIR6) &= ~(1 << 7); - /* VC1 setup for isochronous transfers: */ /* Set VC1 virtual channel id to 1. */ @@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void) /* Enable VC1. */ RCBA32(RCBA_V1CTL) |= (1 << 31); - /* Setup RCRB: */ /* Set component id to 2 for southbridge, northbridge has id 1. */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 86c1a536d6..3c0f3aeff4 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -11,7 +11,7 @@ void i82801ix_lpc_setup(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_i82801ix_config *config = NULL; + const struct southbridge_intel_i82801ix_config *config; /* Configure serial IRQs.*/ pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); @@ -27,7 +27,10 @@ void i82801ix_lpc_setup(void) * - 0x200-0x207 GAMEL */ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); + pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); /* Set up generic decode ranges */ if (!dev || !dev->chip_info) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c deleted file mode 100644 index ba0b0c81f0..0000000000 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include "i82801ix.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != PCI_DEVICE_ID_INTEL_82801IB_SMB) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 16d0520bf9..846c9d8f57 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -35,7 +35,6 @@ static void i82801ix_pcie_init(const config_t *const info) { struct device *pciePort[6]; int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32; /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { @@ -44,8 +43,7 @@ static void i82801ix_pcie_init(const config_t *const info) printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_or_config32(pciePort[i], 0x300, 1 << 21); pci_write_config8(pciePort[i], 0x324, 0x40); } @@ -85,9 +83,8 @@ static void i82801ix_pcie_init(const config_t *const info) } /* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { + for (i = 0; i < 6; ++i) pci_update_config32(pciePort[i], 0x4c, ~0, 0); - } } static void i82801ix_ehci_init(void) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 08b94c7056..56f14b0d2f 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -20,11 +20,8 @@ #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 - #define APM_CNT 0xb2 - - #define GP_IO_USE_SEL 0x00 #define GP_IO_SEL 0x04 #define GP_LVL 0x0c @@ -55,6 +52,16 @@ #define D31F0_PIRQH_ROUT 0x6b #define D31F0_LPC_IODEC 0x80 #define D31F0_LPC_EN 0x82 +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define D31F0_GEN1_DEC 0x84 #define D31F0_GEN2_DEC 0x88 #define D31F0_GEN3_DEC 0x8c @@ -63,25 +70,19 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa - /* D31:F2 SATA */ #define D31F2_IDE_TIM_PRI 0x40 #define D31F2_IDE_TIM_SEC 0x42 #define D31F2_SIDX 0xa0 #define D31F2_SDAT 0xa4 - /* D30:F0 PCI-to-PCI bridge */ #define D30F0_SMLT 0x1b - /* D28:F0-5 PCIe root ports */ #define D28Fx_XCAP 0x42 #define D28Fx_SLCAP 0x54 - -#define SMBUS_IO_BASE 0x0400 - /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 @@ -146,7 +147,6 @@ #define FD_SD (1 << 3) /* SMBus */ #define FD_SAD1 (1 << 2) /* SATA #1 */ - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 883c96428f..ad7141ac49 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -97,7 +97,7 @@ static void i82801ix_pirq_init(struct device *dev) */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -160,8 +160,7 @@ static void i82801ix_power_options(struct device *dev) int nmi_option; /* BIOS must program... */ - reg32 = pci_read_config32(dev, 0xac); - pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8)); + pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8)); /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On @@ -357,7 +356,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "i82801ix: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ i82801ix_enable_apic(dev); @@ -424,7 +425,7 @@ static void i82801ix_lpc_read_resources(struct device *dev) * 0x00c0 ~ 0x00de....ISA DMA * 0x00c1 ~ 0x00df....ISA DMA aliases * 0x00f0.............Coprocessor Error - * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit) + * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit) * 0x04d0 - 0x04d1....PIC * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) @@ -475,7 +476,6 @@ void southbridge_inject_dsdt(const struct device *dev) } } - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a8e7b11179..3900e92bf5 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -23,8 +23,7 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, - PCI_BRIDGE_CTL_NO_ISA); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Enable IO xAPIC on this PCIe port */ pci_or_config32(dev, 0xd8, 1 << 7); diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index cac0375d27..8ac9beea09 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -23,7 +23,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, struct resource *res; /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); + res = probe_resource(dev, PCI_BASE_ADDRESS_5); if (!res) return; diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index c348ed846e..72c3110990 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -23,7 +24,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_read_byte(res->base, device, address); } @@ -36,7 +37,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_write_byte(res->base, device, address, val); } @@ -49,7 +50,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 4f47e34142..1abd8c5a55 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -114,7 +114,6 @@ static void aseg_smm_install(void) return; smm_handler_copied = 1; - /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f712..537e544f94 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -51,7 +51,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 3)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index c79b3682e8..6abeac1f49 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 8edbf4f8a2..9885bc0419 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -6,10 +6,9 @@ bootblock-y += bootblock.c bootblock-y += early_init.c romstage-y += early_init.c -romstage-y += early_smbus.c +ramstage-y += azalia.c ramstage-y += fadt.c -ramstage-y += hdaudio.c ramstage-y += i82801jx.c ramstage-y += lpc.c ramstage-y += pci.c diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 5a1f204303..b93fa96d23 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -167,8 +167,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } @@ -216,32 +214,4 @@ Device (LPCB) Return (0xf) } } - -#ifdef ENABLE_FDC - Device (FDC0) // Floppy controller - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) // FIXME - } - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - Name(_PRS, ResourceTemplate() - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - - } -#endif } diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/azalia.c similarity index 78% rename from src/southbridge/intel/i82801jx/hdaudio.c rename to src/southbridge/intel/i82801jx/azalia.c index ba20a6aae6..3fa344dd38 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801jx.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -46,16 +42,16 @@ static int codec_detect(u8 *base) { u32 reg32; - /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -75,12 +71,12 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -88,9 +84,9 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -108,23 +104,22 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -145,18 +140,21 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; - - reg32 = read32(base + 0x64); + } /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -171,7 +169,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -182,6 +180,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -191,7 +190,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; @@ -228,12 +227,12 @@ static void azalia_init(struct device *dev) /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 028d5c8bf0..e9632d25de 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -43,13 +43,10 @@ struct southbridge_intel_i82801jx_config { /* IDE configuration */ uint8_t sata_port_map : 6; int sata_clock_request : 1; - int sata_traffic_monitor : 1; int c4onc3_enable:1; int c5_enable : 1; int c6_enable : 1; - int c3_latency; - int docking_supported:1; int throttle_duty : 3; diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index bfc5ca9b10..771460955c 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -34,7 +34,6 @@ void i82801jx_lpc_setup(void) | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); - /* Set up generic decode ranges */ if (!dev || !dev->chip_info) return; diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c deleted file mode 100644 index 55b9854598..0000000000 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "i82801jx.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index f2b408b119..fd556615ca 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -5,13 +5,10 @@ #include #include #include -#include "chip.h" void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = pcidev_on_root(0x1f, 0); - struct southbridge_intel_i82801jx_config *chip = dev->chip_info; - u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; fadt->sci_int = 0x9; @@ -36,7 +33,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = chip->c3_latency; + fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */ fadt->duty_offset = 1; fadt->duty_width = 0; fadt->day_alrm = 0xd; @@ -46,8 +43,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_C2_MP_SUPPORTED); - if (chip->docking_supported) - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index a332ec079b..6f90301419 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -46,14 +46,6 @@ static void i82801jx_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { - for (i = 0; i < 6; ++i) { - if (pciePort[i]->enabled) { - pci_or_config32(pciePort[i], 0xe8, 1); - } - } - } - for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ pci_or_config32(pciePort[i], 0x300, 0x3 << 16); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index a88c19ed2f..22546897a7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -11,11 +11,8 @@ #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 - #define APM_CNT 0xb2 - - #define GP_IO_USE_SEL 0x00 #define GP_IO_SEL 0x04 #define GP_LVL 0x0c @@ -66,25 +63,19 @@ #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 - /* D31:F2 SATA */ #define D31F2_IDE_TIM_PRI 0x40 #define D31F2_IDE_TIM_SEC 0x42 #define D31F2_SIDX 0xa0 #define D31F2_SDAT 0xa4 - /* D30:F0 PCI-to-PCI bridge */ #define D30F0_SMLT 0x1b - /* D28:F0-5 PCIe root ports */ #define D28Fx_XCAP 0x42 #define D28Fx_SLCAP 0x54 - -#define SMBUS_IO_BASE 0x0400 - /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 @@ -166,17 +157,10 @@ #define FD_SD (1 << 3) /* SMBus */ #define FD_SAD1 (1 << 2) /* SATA #1 */ - #ifndef __ACPI__ #include -static inline int lpc_is_mobile(const u16 devid) -{ - return (devid == 0x2917) || (devid == 0x2919); -} -#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) - void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2533d8cc72..2f7b516a2a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -276,19 +276,6 @@ static void i82801jx_power_options(struct device *dev) outl(reg32, pmbase + 0x10); } -static void i82801jx_configure_cstates(struct device *dev) -{ - // Enable Popup & Popdown - pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2)); - - // Set Deeper Sleep configuration to recommended values - // Deeper Sleep to Stop CPU: 34-40us - // Deeper Sleep to Sleep: 15us - pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0)); - - /* We could enable slow-C4 exit here, if someone needs it? */ -} - static void i82801jx_rtc_init(struct device *dev) { u8 reg8; @@ -361,7 +348,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "i82801jx: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ i82801jx_enable_apic(dev); @@ -374,10 +363,6 @@ static void lpc_init(struct device *dev) /* Setup power options. */ i82801jx_power_options(dev); - /* Configure Cx state registers */ - if (LPC_IS_MOBILE(dev)) - i82801jx_configure_cstates(dev); - /* Initialize the real time clock. */ i82801jx_rtc_init(dev); @@ -423,7 +408,6 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - return current; } @@ -451,7 +435,7 @@ static void i82801jx_lpc_read_resources(struct device *dev) * 0x00c0 ~ 0x00de....ISA DMA * 0x00c1 ~ 0x00df....ISA DMA aliases * 0x00f0.............Coprocessor Error - * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit) + * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit) * 0x04d0 - 0x04d1....PIC * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 5195522217..18d2c72321 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -23,8 +23,7 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, - PCI_BRIDGE_CTL_NO_ISA); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Enable IO xAPIC on this PCIe port */ pci_or_config32(dev, 0xd8, 1 << 7); diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 0372460310..fa56654e47 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -15,8 +15,7 @@ typedef struct southbridge_intel_i82801jx_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) +static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map) { int i; u32 reg32; @@ -56,14 +55,12 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, /* Lock R/WO bits in Port command registers. */ for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; u8 *addr = abar + 0x118 + (i * 0x80); write32(addr, read32(addr)); } } -static void sata_program_indexed(struct device *const dev, const int is_mobile) +static void sata_program_indexed(struct device *const dev) { u32 reg32; @@ -82,31 +79,25 @@ static void sata_program_indexed(struct device *const dev, const int is_mobile) pci_write_config8(dev, D31F2_SIDX, 0x78); pci_write_config8(dev, D31F2_SDAT + 2, 0x22); - if (!is_mobile) { - pci_write_config8(dev, D31F2_SIDX, 0x84); - reg32 = pci_read_config32(dev, D31F2_SDAT); - reg32 &= ~((7 << 3) | (7 << 0)); - reg32 |= (3 << 3) | (3 << 0); - pci_write_config32(dev, D31F2_SDAT, reg32); - } + pci_write_config8(dev, D31F2_SIDX, 0x84); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); pci_write_config8(dev, D31F2_SIDX, 0x88); reg32 = pci_read_config32(dev, D31F2_SDAT); - if (!is_mobile) - reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); - reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); - if (!is_mobile) - reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); - reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); pci_write_config32(dev, D31F2_SDAT, reg32); pci_write_config8(dev, D31F2_SIDX, 0x8c); reg32 = pci_read_config32(dev, D31F2_SDAT); - if (!is_mobile) - reg32 &= ~((7 << 27) | (7 << 24)); + reg32 &= ~((7 << 27) | (7 << 24)); reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); - if (!is_mobile) - reg32 |= (2 << 27) | (2 << 24); + reg32 |= (2 << 27) | (2 << 24); reg32 |= (2 << 19) | (2 << 16) | 0x00aa; pci_write_config32(dev, D31F2_SDAT, reg32); @@ -138,9 +129,6 @@ static void sata_init(struct device *const dev) /* Get the chip configuration */ const config_t *const config = dev->chip_info; - - const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); - const int is_mobile = (devid == 0x2928) || (devid == 0x2929); u8 sata_mode; printk(BIOS_DEBUG, "i82801jx_sata: initializing...\n"); @@ -202,20 +190,10 @@ static void sata_init(struct device *const dev) sclkcg |= 0x193; pci_write_config32(dev, 0x94, sclkcg); - if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = pcidev_on_root(0x1f, 0); - if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { - u8 reg8 = pci_read_config8(dev, 0x9c); - reg8 &= ~(0x1f << 2); - reg8 |= 3 << 2; - pci_write_config8(dev, 0x9c, reg8); - } - } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + sata_enable_ahci_mmap(dev, config->sata_port_map); - sata_program_indexed(dev, is_mobile); + sata_program_indexed(dev); } static void sata_enable(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 32b64b89df..c92a2864a0 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -23,7 +24,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_read_byte(res->base, device, address); } @@ -36,7 +37,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_write_byte(res->base, device, address, val); } @@ -50,7 +51,7 @@ static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_block_write(res->base, device, cmd, bytes, buf); } @@ -62,7 +63,7 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_block_read(res->base, device, cmd, bytes, buf); } @@ -76,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 16ec025c15..7d79620114 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -52,7 +52,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 3)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 41013a3596..5fc9548e55 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -10,9 +10,6 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) - return; - u8 reg8; pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 691459e906..07f9b6b110 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -16,6 +16,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_PMCLIB diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index d8de593e93..a146187918 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -28,7 +28,6 @@ ramstage-y += madt.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c romstage-y += early_pch.c -romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a81e..011bde60b1 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -10,10 +10,6 @@ #include #include "pch.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -26,9 +22,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -48,15 +42,14 @@ static int codec_detect(u8 *base) u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) goto no_codec; @@ -66,22 +59,22 @@ static int codec_detect(u8 *base) no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -89,15 +82,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ - int timeout = 1000; while (timeout--) { @@ -110,28 +102,25 @@ static int wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 1msec timeout */ + int timeout = 1000; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 1msec timeout */ - - int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -155,16 +144,15 @@ static void codec_init(struct device *dev, u8 *base, int addr) } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) == -1) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } - reg32 = read32(base + 0x64); - /* 2 */ + reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); @@ -179,7 +167,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -190,6 +178,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -199,7 +188,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; @@ -220,10 +209,10 @@ static void azalia_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the Azalia get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); @@ -268,9 +257,9 @@ static void azalia_init(struct device *dev) /* Codec Initialization Programming Sequence */ /* Take controller out of reset */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); + reg32 = read32(base + HDA_GCTL_REG); + reg32 |= HDA_GCTL_CRST; + write32(base + HDA_GCTL_REG, reg32); /* Wait 1ms */ udelay(1000); diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 6ef14a3b08..944378eca4 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -74,7 +74,6 @@ static void early_lpc_init(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } - void bootblock_early_southbridge_init(void) { enable_spi_prefetching_and_caching(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f1c7bb10e1..d9ac0095ee 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -25,6 +25,27 @@ static void pch_default_disable(void) RCBA32(FD2) = 1; } +void ibexpeak_setup_bars(void) +{ + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); + + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + /* No reset */ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); + /* halt timer */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); + /* halt timer */ + outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); + printk(BIOS_DEBUG, " done.\n"); +} + void early_pch_init(void) { early_gpio_init(); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c deleted file mode 100644 index 7d8503bb7d..0000000000 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include "pch.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index a0dcee8931..ccd9f57b74 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -13,7 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->sci_int = 0x9; if (permanent_smi_handler()) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 7e99613a28..55dcb02d9b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -439,7 +439,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ pch_enable_ioapic(dev); @@ -571,7 +573,7 @@ void southbridge_inject_dsdt(const struct device *dev) /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); acpigen_pop_len(); } } @@ -616,7 +618,6 @@ static struct device_operations device_ops = { .ops_pci = &pci_dev_ops_pci, }; - static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_IBEXPEAK_LPC_QM57, PCI_DID_INTEL_IBEXPEAK_LPC_HM55, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 2c9c87cbcc..b355d9dbdb 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -359,7 +359,7 @@ static void intel_me7_finalize_smm(void) u32 reg32; u16 reg16; - mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ @@ -604,7 +604,6 @@ static const unsigned short pci_device_ids[] = { 0 }; - static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index beacd3358a..2466d02943 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -198,7 +198,6 @@ struct me_fw_version { u16 recovery_hot_fix; } __packed; - #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index d0f131482b..76d0ad6efb 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,11 +22,10 @@ * It does not matter where we put the SMBus I/O base, as long as we * keep it consistent and don't interfere with other devices. Stage2 * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE * again. But handling static BARs is a generic problem that should be * solved in the device allocator. */ -#define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 @@ -39,6 +38,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); +void ibexpeak_setup_bars(void); void early_pch_init(void); void early_thermal_init(void); @@ -148,8 +148,7 @@ void pch_enable(struct device *dev); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 357ad5fc99..d1485707f3 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -49,7 +49,8 @@ static void sata_init(struct device *dev) /* SATA configuration */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (sata_mode == 0) { /* AHCI */ @@ -89,7 +90,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 7e9aa57da8..7c9ac8240d 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_read_byte(res->base, device, address); } @@ -46,7 +47,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); return do_smbus_write_byte(res->base, device, address, val); } @@ -59,7 +60,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 2bc31cf0cf..cce464be6d 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -107,7 +107,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) @@ -151,7 +150,11 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 0b496dae55..142d3c7d6d 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "pch.h" #include @@ -13,7 +14,7 @@ static void thermal_init(struct device *dev) u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 7ad9929001..a2adc5aab7 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -66,7 +66,6 @@ static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, pci_write_config8(dev, 0x80, access_cntl); } - static struct pci_operations lops_pci = { .set_subsystem = &usb_ehci_set_subsystem, }; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2207028ee8..5abb286222 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -9,6 +9,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE @@ -23,7 +24,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SPI_CONSOLE_SUPPORT + select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT select RTC select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ @@ -50,15 +51,6 @@ config SERIRQ_CONTINUOUS_MODE If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config ME_MBP_CLEAR_LATE - bool "Defer wait for ME MBP Cleared" - default y - help - If you set this option to y, the Management Engine driver - will defer waiting for the MBP Cleared indicator until the - finalize step. This can speed up boot time if the ME takes - a long time to indicate this status. - config FINALIZE_USB_ROUTE_XHCI bool "Route all ports to XHCI controller in finalize step" default y @@ -66,4 +58,8 @@ config FINALIZE_USB_ROUTE_XHCI If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback. +config PCIEXP_AER + bool + default y + endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 48be615509..9694cc377f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) bootblock-y += bootblock.c ramstage-y += pch.c +ramstage-y += iobp.c ramstage-y += azalia.c ramstage-y += fadt.c ramstage-y += lpc.c @@ -33,7 +34,7 @@ smm-y += smihandler.c me_9.x.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c +romstage-y += early_usb.c early_me.c me_status.c early_pch.c romstage-y += pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 995943d46e..8fee16b378 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -26,7 +26,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ - addr->space_id = 0; /* Memory */ + addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; addr->bit_width = 64; addr->bit_offset = 0; addr->addrl = (unsigned long long)HPET_ADDR & 0xffffffff; diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 0f775129bc..1e9de3cb33 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -192,8 +192,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e1bd64f4fb..6d0428c464 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -7,11 +7,7 @@ Scope(\) // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) { - If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) { - Return (1) - } else { - Return (0) - } + Return (CONFIG(INTEL_LYNXPOINT_LP)) } // IO-Trap at 0x800. This is the ACPI->SMI communication interface. @@ -27,9 +23,6 @@ Scope(\) OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select , 5, diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 83bc6eb6b6..ce3a869a92 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -162,9 +162,8 @@ Device (I2C0) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -243,9 +242,8 @@ Device (I2C1) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -358,9 +356,8 @@ Device (SPI1) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -408,9 +405,8 @@ Device (UAR0) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f415170fc9..cf360ffc60 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -41,9 +41,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) pci_write_config32(dev, 0x120, reg32); if (!pch_is_lp()) { - reg16 = pci_read_config16(dev, 0x78); - reg16 &= ~(1 << 11); - pci_write_config16(dev, 0x78, reg16); + pci_and_config16(dev, 0x78, ~(1 << 11)); } } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); @@ -53,8 +51,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) reg32 &= ~(1UL << 31); @@ -70,11 +67,8 @@ static void azalia_pch_init(struct device *dev, u8 *base) reg8 |= (1 << 4); pci_write_config8(dev, 0x43, reg8); - if (!pch_is_lp()) { - reg32 = pci_read_config32(dev, 0xc0); - reg32 |= (1 << 17); - pci_write_config32(dev, 0xc0, reg32); - } + if (!pch_is_lp()) + pci_or_config32(dev, 0xc0, 1 << 17); /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); @@ -84,19 +78,14 @@ static void azalia_pch_init(struct device *dev, u8 *base) reg32 |= (1 << 14); pci_write_config32(dev, 0xc4, reg32); - if (!pch_is_lp()) { - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1UL << 31); - pci_write_config32(dev, 0xd0, reg32); - } + if (!pch_is_lp()) + pci_and_config32(dev, 0xd0, ~(1UL << 31)); - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status if (pch_is_lp()) { reg16 = read32(base + 0x0012); @@ -104,9 +93,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) write32(base + 0x0012, reg16); /* disable Auto Voltage Detector */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x42, reg8); + pci_or_config8(dev, 0x42, 1 << 2); } } diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2d65..e30d4b4c21 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -6,19 +6,6 @@ #include struct southbridge_intel_lynxpoint_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - /** * GPI Routing configuration for LynxPoint-H * @@ -104,5 +91,4 @@ struct southbridge_intel_lynxpoint_config { bool docking_supported; }; - #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 80b8939c5a..956d1d24de 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include "pch.h" @@ -34,14 +35,8 @@ enum pch_platform_type get_pch_platform_type(void) return PCH_TYPE_DESKTOP; } -int pch_is_lp(void) -{ - return get_pch_platform_type() == PCH_TYPE_ULT; -} - static void pch_enable_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); @@ -58,7 +53,7 @@ static void pch_generic_setup(void) { printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); } diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c deleted file mode 100644 index 7d8503bb7d..0000000000 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include "pch.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 2e4df72658..8146794aa3 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -36,7 +36,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } @@ -64,7 +64,7 @@ static void pch_log_gpe(void) gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } /* @@ -78,7 +78,7 @@ static void pch_log_gpe(void) if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, gpe0_high_gpios[i]); } } diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 9d264e00b6..b61115b02c 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include + #include "pch.h" #include "hda_verb.h" -/** - * Set bits in a register and wait for status - */ static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -21,9 +20,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -38,9 +35,6 @@ static int set_bits(void *port, u32 mask, u32 val) return 0; } -/** - * Probe for supported codecs - */ int hda_codec_detect(u8 *base) { u8 reg8; @@ -68,19 +62,17 @@ no_codec: return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -89,28 +81,24 @@ static int hda_wait_for_ready(u8 *base) return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int hda_wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -118,7 +106,7 @@ static int hda_wait_for_valid(u8 *base) return -1; } -/** +/* * Find a specific entry within a verb table * * @param verb_table_bytes: verb table size in bytes @@ -147,7 +135,7 @@ static u32 hda_find_verb(u32 verb_table_bytes, const u32 *verb_table_data, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (verb_table_bytes / sizeof(u32))) { u32 verb_size = 4 * verb_table_data[idx+2]; // in u32 @@ -163,9 +151,6 @@ static u32 hda_find_verb(u32 verb_table_bytes, return 0; } -/** - * Write a supplied verb table - */ int hda_codec_write(u8 *base, u32 size, const u32 *data) { int i; @@ -183,9 +168,6 @@ int hda_codec_write(u8 *base, u32 size, const u32 *data) return 0; } -/** - * Initialize codec, then find the verb table and write it - */ int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) { const u32 *verb; diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 483cd4c539..07ee513c3c 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -3,15 +3,7 @@ #ifndef LYNXPOINT_HDA_VERB_H #define LYNXPOINT_HDA_VERB_H -#define HDA_GCAP_REG 0x00 -#define HDA_GCTL_REG 0x08 -#define HDA_GCTL_CRST (1 << 0) -#define HDA_STATESTS_REG 0x0e -#define HDA_IC_REG 0x60 -#define HDA_IR_REG 0x64 -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) +#include int hda_codec_detect(u8 *base); int hda_codec_write(u8 *base, u32 size, const u32 *data); diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c new file mode 100644 index 0000000000..ad2527f00b --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "pch.h" +#include "iobp.h" + +#define IOBP_RETRY 1000 + +static inline int iobp_poll(void) +{ + unsigned int try; + + for (try = IOBP_RETRY; try > 0; try--) { + u16 status = RCBA16(IOBPS); + if ((status & IOBPS_READY) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); + return 0; +} + +u32 pch_iobp_read(u32 address) +{ + u16 status; + + if (!iobp_poll()) + return 0; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_READ; + RCBA16(IOBPS) = status; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return 0; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); + return 0; + } + + /* Read IOBP data */ + return RCBA32(IOBPD); +} + +void pch_iobp_write(u32 address, u32 data) +{ + u16 status; + + if (!iobp_poll()) + return; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* WRITE OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_WRITE; + RCBA16(IOBPS) = status; + + RCBA32(IOBPD) = data; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); + return; + } + + printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data); +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} diff --git a/src/southbridge/intel/lynxpoint/iobp.h b/src/southbridge/intel/lynxpoint/iobp.h new file mode 100644 index 0000000000..c8669bafd5 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H + +#include + +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#endif diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index c85ba2c616..448ee8bd68 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -19,7 +19,6 @@ static u16 get_gpio_base(void) #endif } - /* * This function will return a number that indicates which PIRQ * this GPIO maps to. If this is not a PIRQ capable GPIO then diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b00c9..e5614303cc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -16,6 +16,7 @@ #include #include #include "chip.h" +#include "iobp.h" #include "nvs.h" #include "pch.h" #include @@ -96,18 +97,18 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + const uint8_t pirq = 0x80; - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq); + pci_write_config8(dev, PIRQB_ROUT, pirq); + pci_write_config8(dev, PIRQC_ROUT, pirq); + pci_write_config8(dev, PIRQD_ROUT, pirq); + + pci_write_config8(dev, PIRQE_ROUT, pirq); + pci_write_config8(dev, PIRQF_ROUT, pirq); + pci_write_config8(dev, PIRQG_ROUT, pirq); + pci_write_config8(dev, PIRQH_ROUT, pirq); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -122,10 +123,12 @@ static void pch_pirq_init(struct device *dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ + case 2: /* INTB# */ + case 3: /* INTC# */ + case 4: /* INTD# */ + int_line = pirq; + break; } if (!int_line) @@ -332,8 +335,7 @@ static void lpt_lp_pm_init(struct device *dev) RCBA32_AND_OR(0x2b20, 0, 0x0005db01); /* Power Optimizer */ RCBA32_AND_OR(0x3a80, 0, 0x05145005); - pci_write_config32(dev, 0xac, - pci_read_config32(dev, 0xac) | (1 << 21)); + pci_or_config32(dev, 0xac, 1 << 21); pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0UL, 0x00c00000); @@ -422,9 +424,7 @@ static void enable_lp_clock_gating(struct device *dev) reg16 |= (1 << 2); // PCI CLKRUN# Enable pci_write_config16(dev, GEN_PMCON_1, reg16); - reg32 = pci_read_config32(dev, 0x64); - reg32 |= (1 << 6); - pci_write_config32(dev, 0x64, reg32); + pci_or_config32(dev, 0x64, 1 << 6); /* * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 @@ -475,22 +475,15 @@ static void pch_set_acpi_mode(void) static void pch_disable_smm_only_flashing(struct device *dev) { - u8 reg8; - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); + + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); } static void pch_fixups(struct device *dev) { - u8 gen_pmcon_2; - /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); - gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); /* * Enable DMI ASPM in the PCH @@ -505,7 +498,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ pch_enable_ioapic(dev); @@ -796,7 +791,6 @@ static struct device_operations device_ops = { .ops_pci = &pci_dev_ops_pci, }; - /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ static const unsigned short pci_device_ids[] = { 0x8c41, /* Mobile Full Featured Engineering Sample. */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 77b3573f2c..f32ee5bf67 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include "chip.h" @@ -32,7 +31,7 @@ #endif /* Path that the BIOS should take based on ME state */ -static const char *me_bios_path_values[] __unused = { +static const char *const me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", [ME_S3WAKE_BIOS_PATH] = "S3 Wake", [ME_ERROR_BIOS_PATH] = "Error", @@ -541,7 +540,6 @@ void intel_me_finalize_smm(void) { struct me_hfs hfs; u32 reg32; - u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -550,10 +548,8 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG(ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); -#endif /* Make sure ME is in a mode that expects EOP */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); @@ -569,9 +565,8 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + pci_and_config16(PCH_ME_DEV, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -847,9 +842,9 @@ static const unsigned short pci_device_ids[] = { }; static const struct pci_driver intel_me __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= pci_device_ids, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; #endif /* !__SIMPLE_DEVICE__ */ @@ -930,11 +925,6 @@ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device * host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG(ME_MBP_CLEAR_LATE) - /* Wait for the mbp_cleared indicator. */ - intel_me_mbp_clear(dev); -#endif - /* Dump out the MBP contents. */ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 0a0e489d6f..adc011bb7b 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -6,6 +6,7 @@ #include #include #include +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ @@ -56,11 +57,6 @@ enum pch_platform_type get_pch_platform_type(void) return PCH_TYPE_DESKTOP; } -int pch_is_lp(void) -{ - return get_pch_platform_type() == PCH_TYPE_ULT; -} - u16 get_pmbase(void) { static u16 pmbase; @@ -86,9 +82,7 @@ u16 get_gpiobase(void) /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); } /* Set bit in function disable register to hide this device */ @@ -185,114 +179,8 @@ void pch_disable_devfn(struct device *dev) } } -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try; - - for (try = IOBP_RETRY; try > 0; try--) { - u16 status = RCBA16(IOBPS); - if ((status & IOBPS_READY) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); - return 0; -} - -u32 pch_iobp_read(u32 address) -{ - u16 status; - - if (!iobp_poll()) - return 0; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_READ; - RCBA16(IOBPS) = status; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return 0; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); - return 0; - } - - /* Read IOBP data */ - return RCBA32(IOBPD); -} - -void pch_iobp_write(u32 address, u32 data) -{ - u16 status; - - if (!iobp_poll()) - return; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* WRITE OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_WRITE; - RCBA16(IOBPS) = status; - - RCBA32(IOBPD) = data; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - return; - } - - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data = pch_iobp_read(address); - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - pch_iobp_write(address, data); -} - void pch_enable(struct device *dev) { - u16 reg16; - /* PCH PCIe Root Ports are handled in PCIe driver. */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) return; @@ -301,9 +189,8 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index db3d92af26..1ecad62796 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -47,11 +47,10 @@ * It does not matter where we put the SMBus I/O base, as long as we * keep it consistent and don't interfere with other devices. Stage2 * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE * again. But handling static BARs is a generic problem that should be * solved in the device allocator. */ -#define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 #if CONFIG(INTEL_LYNXPOINT_LP) @@ -70,6 +69,11 @@ #ifndef __ACPI__ +static inline int pch_is_lp(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} + /* PCH platform types, safe for MRC consumption */ enum pch_platform_type { PCH_TYPE_MOBILE = 0, @@ -85,7 +89,6 @@ void usb_xhci_route_all(void); enum pch_platform_type get_pch_platform_type(void); int pch_silicon_revision(void); int pch_silicon_id(void); -int pch_is_lp(void); u16 get_pmbase(void); u16 get_gpiobase(void); @@ -116,9 +119,6 @@ void disable_gpe(u32 mask); void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); @@ -213,8 +213,7 @@ void mainboard_config_rcba(void); #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LGMR 0x98 /* LPC Generic Memory Range */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c @@ -406,40 +405,6 @@ void mainboard_config_rcba(void); #define PMBASE 0x40 -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 883dfc781b..0ede943ceb 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -9,9 +9,9 @@ #include #include #include +#include "iobp.h" #include "pch.h" #include -#include #include #include "chip.h" @@ -100,6 +100,38 @@ static void root_port_config_update_gbe_port(void) } } +static void update_num_ports(void) +{ + /* + * According to existing code in 'root_port_check_disable()', which does + * not agree with the confusing information on the datasheets, the last + * visible function depends on the strapped root port width as follows: + * + * +-----+----+----+----+----+ + * | RPC | #5 | #6 | #7 | #8 | + * +-----+----+----+----+----+ + * | 0 | x1 | x1 | x1 | x1 | + * | 1 | x2 | | x1 | x1 | + * | 2 | x2 | | x2 | | + * | 3 | x4 | | | | + * +-----+----+----+----+----+ + */ + switch ((rpc.strpfusecfg2 >> 14) & 0x3) { + case 0: + case 1: + break; + case 2: + rpc.num_ports = MIN(rpc.num_ports, 7); + break; + case 3: + rpc.num_ports = MIN(rpc.num_ports, 5); + break; + } + + printk(BIOS_DEBUG, "Adjusted number of PCIe root ports to %d as per strpfusecfg2\n", + rpc.num_ports); +} + static void root_port_init_config(struct device *dev) { int rp; @@ -137,6 +169,10 @@ static void root_port_init_config(struct device *dev) case 5: rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc); rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c); + + if (!pch_is_lp()) + update_num_ports(); + break; case 6: rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c); @@ -196,41 +232,40 @@ static void pcie_enable_clock_gating(void) rp = root_port_number(dev); if (!is_rp_enabled(rp)) { - static const uint32_t high_bit = (1UL << 31); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); if (!is_lp) { if (rp == 1 && !is_rp_enabled(2) && !is_rp_enabled(3) && !is_rp_enabled(4)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } if (rp == 5 && !is_rp_enabled(6) && !is_rp_enabled(7) && !is_rp_enabled(8)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } continue; } - pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pci_update_config32(dev, 0x420, ~high_bit, high_bit); + pci_or_config8(dev, 0xe2, 3 << 4); + pci_or_config32(dev, 0x420, 1 << 31); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pci_update_config32(dev, 0x420, ~0, (3 << 29)); + pci_or_config32(dev, 0x420, 3 << 29); /* Enable static clock gating. */ if (rp == 1 && !is_rp_enabled(2) && !is_rp_enabled(3) && !is_rp_enabled(4)) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } else if (rp == 5 || rp == 6) { - pci_update_config8(dev, 0xe2, ~1, 1); - pci_update_config8(dev, 0xe1, 0x7f, 0x80); + pci_or_config8(dev, 0xe2, 1); + pci_or_config8(dev, 0xe1, 1 << 7); } continue; } @@ -238,29 +273,30 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pci_update_config8(dev, 0xe1, 0xfc, 0x03); + pci_or_config8(dev, 0xe1, 0x03); if (is_lp) { - pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_or_config8(dev, 0xe2, 1 << 6); pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); } /* Update PECR1 register. */ - pci_update_config8(dev, 0xe8, ~0, 1); + pci_or_config8(dev, 0xe8, 1); + /* FIXME: Are we supposed to update this register with a constant boolean? */ pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pci_update_config32(dev, 0x420, ~0, (3 << 29)); + pci_or_config32(dev, 0x420, 3 << 29); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pci_update_config8(dev, 0xe1, 0xc3, 0x3c); + pci_or_config8(dev, 0xe1, 0x3c); } if (!enabled_ports && is_lp && rpc.ports[0]) - pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_or_config8(rpc.ports[0], 0xe1, 1 << 6); } static void root_port_commit_config(void) @@ -276,7 +312,6 @@ static void root_port_commit_config(void) for (i = 0; i < rpc.num_ports; i++) { struct device *dev; - u16 reg16; dev = rpc.ports[i]; @@ -291,9 +326,8 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -603,11 +637,11 @@ static void pch_pcie_early(struct device *dev) } } - pci_update_config32(dev, 0x338, ~(1 << 26), 0); + pci_and_config32(dev, 0x338, ~(1 << 26)); } /* Enable LTR in Root Port. */ - pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); + pci_or_config32(dev, 0x64, 1 << 11); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); @@ -618,29 +652,38 @@ static void pch_pcie_early(struct device *dev) else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pci_update_config32(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ - pci_update_config32(dev, 0xd8, ~0, (1 << 25)); + /* Set Invalid Receive Range Check Enable in MPC register. */ + pci_or_config32(dev, 0xd8, 1 << 25); - pci_update_config8(dev, 0xf5, 0x3f, 0); + pci_and_config8(dev, 0xf5, 0x3f); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) - pci_update_config8(dev, 0xf7, ~0xc, 0); + pci_and_config8(dev, 0xf7, ~0x0c); /* Set EOI forwarding disable. */ - pci_update_config32(dev, 0xd4, ~0, (1 << 1)); + pci_or_config32(dev, 0xd4, 1 << 1); - /* Set something involving advanced error reporting. */ - pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ + if (CONFIG(PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); + + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); if (is_lp) - pci_update_config32(dev, 0x100, ~0, (1 << 29)); + pci_or_config32(dev, 0x100, 1 << 29); /* Read and write back write-once capability registers. */ pci_update_config32(dev, 0x34, ~0, 0); @@ -651,8 +694,6 @@ static void pch_pcie_early(struct device *dev) static void pci_init(struct device *dev) { - u16 reg16; - printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ @@ -665,16 +706,11 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); - pci_write_config16(dev, 0x06, reg16); - reg16 = pci_read_config16(dev, 0x1e); - pci_write_config16(dev, 0x1e, reg16); + pci_update_config16(dev, 0x06, ~0, 0); + pci_update_config16(dev, 0x1e, ~0, 0); } static void pch_pcie_enable(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 8c4a8c1c90..af7a2b2b98 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -57,7 +57,6 @@ static void print_gpio_status(u32 status, int start) } } - /* * PM1_CNT */ @@ -78,7 +77,6 @@ void disable_pm1_control(u32 mask) outl(pm1_cnt, get_pmbase() + PM1_CNT); } - /* * PM1 */ @@ -127,7 +125,6 @@ void enable_pm1(u16 events) outw(events, get_pmbase() + PM1_EN); } - /* * SMI */ @@ -198,7 +195,6 @@ void disable_smi(u32 mask) outl(smi_en, get_pmbase() + SMI_EN); } - /* * ALT_GP_SMI */ @@ -298,7 +294,6 @@ void enable_alt_smi(u32 mask) } } - /* * TCO */ @@ -368,7 +363,6 @@ void enable_tco_sci(void) enable_gpe(TCOSCI_EN); } - /* * GPE0 */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 47e6f9be68..57824dfe90 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -8,6 +8,7 @@ #include #include #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; @@ -41,17 +42,17 @@ static void sata_init(struct device *dev) /* SATA configuration */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, 0x24, 0); + /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); pci_write_config8(dev, 0x09, 0x80); @@ -77,8 +78,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if (config->sata_ahci) { u32 *abar; @@ -128,10 +128,8 @@ static void sata_init(struct device *dev) } pci_write_config32(dev, 0x98, reg32); - /* Setup register 9Ch */ - reg16 = 0; /* Disable alternate ID */ - reg16 |= (1 << 5); /* BWG step 12 */ - pci_write_config16(dev, 0x9c, reg16); + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); /* SATA Initialization register */ reg32 = 0x183; @@ -169,15 +167,16 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, 0x24, 0); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); - /* Native mode capable on both primary and secondary (0xa) + /* + * Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf + * + * FIXME: Does not match the code. */ pci_write_config8(dev, 0x09, 0x8f); @@ -208,8 +207,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 08f69fbc63..224e0f4ef6 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -8,6 +8,7 @@ #include #include #include "chip.h" +#include "iobp.h" #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 39003f66a6..8498a6cdb1 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -15,6 +15,7 @@ static void pch_smbus_init(struct device *dev) u16 reg16; /* Enable clock gating */ + /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); pci_write_config32(dev, 0x80, reg16); @@ -58,7 +59,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 6e14985307..f5c5f2a80e 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -54,7 +54,6 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -64,9 +63,7 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); @@ -81,7 +78,6 @@ static void busmaster_disable_on_bus(int bus) } } - static void southbridge_smi_sleep(void) { u8 reg8; @@ -317,6 +313,10 @@ static void southbridge_smi_apmc(void) if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (struct global_nvs *)((u32)state->rbx); + if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } @@ -378,8 +378,6 @@ static void southbridge_smi_mc(void) printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } - - static void southbridge_smi_tco(void) { u32 tco_sts = clear_tco_status(); @@ -405,8 +403,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -431,7 +428,7 @@ static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; - u32 data, mask = 0; + u32 mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register @@ -443,7 +440,6 @@ static void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 2)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) @@ -458,8 +454,9 @@ static void southbridge_smi_monitor(void) if (IOTRAP(0)) { if (!(trap_cycle & (1 << 24))) { // It's a write printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; + (void)RCBA32(0x1e18); + // data = RCBA32(0x1e18); + // data &= mask; // if (smi1) // southbridge_smi_command(data); // return; @@ -478,8 +475,7 @@ static void southbridge_smi_monitor(void) if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", RCBA32(0x1e18)); } #undef IOTRAP } diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8b3e..a6bc5c6bcb 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -8,28 +8,25 @@ #include #include #include +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ void usb_ehci_disable(pci_devfn_t dev) { - u16 reg16; - /* Set 0xDC[0]=1 */ pci_or_config32(dev, 0xdc, (1 << 0)); /* Set D3Hot state and disable PME */ - reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); - reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); - reg16 |= PWR_CTL_SET_D3; - pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, EHCI_PWR_CTL_STS, ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK), + PWR_CTL_SET_D3); /* Clear memory and bus master */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable device */ switch (dev) { @@ -121,21 +118,15 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) static void usb_ehci_clock_gating(struct device *dev) { - u32 reg32; - /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 5) | (1 << 2) | (1 << 1); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 5) | (1 << 2) | (1 << 1)); /* Dx:F0:78h[1:0] = 11b */ - reg32 = pci_read_config32(dev, 0x78); - reg32 |= (1 << 1) | (1 << 0); - pci_write_config32(dev, 0x78, reg32); + pci_or_config32(dev, 0x78, (1 << 1) | (1 << 0)); } static void usb_ehci_init(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 1cfec1b476..60312a4fe7 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -8,6 +8,7 @@ #include #include #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; @@ -157,7 +158,6 @@ static void usb_xhci_reset_usb3(struct device *dev, int all) /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { - u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); @@ -166,15 +166,10 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) if (pch_is_lp()) { /* Set D0 state */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Clear PCI 0xB0[14:13] */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - pci_write_config32(dev, 0xb0, reg32); + pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); @@ -200,17 +195,13 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) void usb_xhci_route_all(void) { u32 port_mask, route; - u16 reg16; /* Skip if EHCI is already disabled */ if (RCBA32(FD) & PCH_DISABLE_EHCI1) return; /* Set D0 state */ - reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Set USB3 superspeed enable */ port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); @@ -242,7 +233,6 @@ void usb_xhci_route_all(void) static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; - u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); @@ -266,9 +256,7 @@ static void usb_xhci_clock_gating(struct device *dev) pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ - reg16 = pci_read_config16(dev, 0x44); - reg16 |= (1 << 9) | (1 << 7) | (1 << 3); - pci_write_config16(dev, 0x44, reg16); + pci_or_config16(dev, 0x44, (1 << 9) | (1 << 7) | (1 << 3)); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { @@ -281,23 +269,17 @@ static void usb_xhci_clock_gating(struct device *dev) pci_write_config32(dev, 0xa0, reg32); /* D20:F0:A4h[13] = 0 */ - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= ~(1 << 13); - pci_write_config32(dev, 0xa4, reg32); + pci_and_config32(dev, 0xa4, ~(1 << 13)); } static void usb_xhci_init(struct device *dev) { u32 reg32; - u16 reg16; u8 *mem_base = usb_xhci_mem_base(dev); config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~PWR_CTL_SET_MASK; - reg16 |= PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); /* Enable clock gating first */ usb_xhci_clock_gating(dev); @@ -321,10 +303,7 @@ static void usb_xhci_init(struct device *dev) write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - reg32 |= (1 << 17); - pci_write_config32(dev, 0xb0, reg32); + pci_update_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)), 1 << 17); } reg32 = pci_read_config32(dev, 0x50); @@ -340,15 +319,10 @@ static void usb_xhci_init(struct device *dev) pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1UL << 31); - pci_write_config32(dev, 0x44, reg32); + pci_or_config32(dev, 0x44, 1 << 31); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ - reg32 = pci_read_config32(dev, 0x40); - reg32 &= ~(1 << 23); /* unsupported request */ - reg32 |= (1UL << 31); - pci_write_config32(dev, 0x40, reg32); + pci_update_config32(dev, 0x40, ~(1 << 23), 1 << 31); /* unsupported request */ if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 73cb2e1fda..e0744b314e 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -107,11 +107,9 @@ static void rl5c476_init(struct device *dev) pc16->moffl0 = 0; pc16->moffh0 = 0x40; - /* set I/O width for Auto Data width */ pc16->ioctrl = 0x22; - /* enable I/O window 0 and 1 */ pc16->awinen = 0xc1; @@ -125,7 +123,6 @@ static void rl5c476_init(struct device *dev) pc16->igctrl = 0x69; - /* 16 bit CF always have first config byte at 0x200 into * Config structure, but CF+ may not according to spec - * should locate through reading tuple data, but this should diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 4f5ecdc8bf..e27e7a383f 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -2,10 +2,8 @@ /* rl5c476 routines and defines*/ - #include - /* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { u8 idrevs; diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 2b52ca47d8..e874f3403e 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -2,14 +2,12 @@ subdirs-y += aspeed subdirs-y += fintek -subdirs-y += intel subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas subdirs-y += serverengines subdirs-y += smsc -subdirs-y += via subdirs-y += winbond ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += common/conf_mode.c diff --git a/src/superio/aspeed/common/early_config.c b/src/superio/aspeed/common/early_config.c index fe780ff5aa..716a8968d3 100644 --- a/src/superio/aspeed/common/early_config.c +++ b/src/superio/aspeed/common/early_config.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include -#include #include #include #include diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 096b96d376..83f2fea2b2 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -9,6 +9,9 @@ static void generic_set_resources(struct device *dev) { struct resource *res; + if (!dev) + return; + if (dev->link_list) assign_resources(dev->link_list); diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 9a94aaf1d5..47fbf0cb8e 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 3d11d295c8..1c34f6d080 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -4,13 +4,11 @@ bootblock-$(CONFIG_SUPERIO_FINTEK_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_PRE_RAM) += common/early_serial.c -subdirs-y += f71805f subdirs-y += f71808a subdirs-y += f71859 subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 -subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d subdirs-y += f81803a diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 302f2f4ffe..4e2c525856 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -152,7 +152,7 @@ Device(SUPERIO_DEV) { ENTER_CONFIG_MODE (SUPERIO_UART_LDN) PNP_WRITE_IO(PNP_IO0, Arg0, IO0) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () } } @@ -221,7 +221,7 @@ Device(SUPERIO_DEV) { ENTER_CONFIG_MODE (SUPERIO_UART_LDN) PNP_WRITE_IO(PNP_IO0, Arg0, IO0) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () } } @@ -244,7 +244,7 @@ Device(SUPERIO_DEV) { { /* DBG0("SIO CPSI") */ ENTER_CONFIG_MODE(SUPERIO_PME_LDN) - Store(1, PSIN) + PSIN = 1 EXIT_CONFIG_MODE() } #endif diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index a682a158e3..a7ed96bb26 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -10,7 +10,6 @@ #include "fintek_internal.h" #include "chip.h" - /* Register addresses */ // Choose between AMD and Intel #define HWM_AMD_TSI_ADDR 0x08 @@ -37,7 +36,6 @@ #define HWM_FAN2_SEG4_SPEED_COUNT 0xBD #define HWM_FAN2_SEG5_SPEED_COUNT 0xBE - void f81866d_hwm_init(struct device *dev) { struct resource *res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index f2ebda05fb..8ff122bbdd 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -10,9 +10,7 @@ ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c subdirs-y += it8528e subdirs-y += it8613e subdirs-y += it8623e -subdirs-y += it8671f subdirs-y += it8712f -subdirs-y += it8716f subdirs-y += it8718f subdirs-y += it8720f subdirs-y += it8721f diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 13c8ff53d4..36c1496db0 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -42,4 +42,10 @@ config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG Slope PWM registers have no separate BIT6 and are set directly by 7-bit values instead. +config SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + bool + help + Temperature can be read to any TMPIN from an external sensor via SST/PECI + (instead of TMPIN3 only). + endif diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index d19548ebca..6b05a382e7 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -45,7 +45,6 @@ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) pnp_exit_conf_state(dev); } - /* * in romstage.c * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) @@ -94,6 +93,33 @@ void ite_enable_3vsbsw(pnp_devfn_t dev) pnp_exit_conf_state(dev); } +/* + * + * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge + * This can be needed for S3 resume. + * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked + * as reserved. + * + * Delay PWRGD3 assertion after setting 3VSBSW#. + * 0: There will be no extra delay before PWRGD3 is set. + * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased. + * + * in romstage.c + * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: GPIO_DEV + */ + +void ite_delay_pwrgd3(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC); + tmp |= 0x01; + pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp); + pnp_exit_conf_state(dev); +} + /* * in romstage.c * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index f63bfd3eea..9149c5828c 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -61,17 +61,40 @@ static void enable_tmpin(const u16 base, const u8 tmpin, const struct ite_ec_thermal_config *const conf) { u8 reg; + u8 reg_extra; reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); + reg_extra = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); switch (conf->mode) { case THERMAL_PECI: - if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) { - printk(BIOS_WARNING, "PECI specified for multiple TMPIN\n"); + /* Some chips can set any TMPIN as the target for PECI readings + while others can only read to TMPIN3. In the latter case a + different register is used for enabling it. */ + if (CONFIG(SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN)) { + /* IT8721F is an exception, it cannot use TMPIN2 for PECI. */ + if (CONFIG(SUPERIO_ITE_IT8721F) && tmpin == 2) { + printk(BIOS_WARNING, + "PECI to TMPIN2 not supported on IT8721F\n"); + return; + } + if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) { + printk(BIOS_WARNING, + "PECI specified for multiple TMPIN\n"); + return; + } + reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + } else if (tmpin == 3) { + reg_extra |= ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT; + pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, + reg_extra); + } else { + printk(BIOS_WARNING, "PECI to TMPIN%d not supported on this Super I/O", + tmpin); return; } enable_peci(base); - reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + break; case THERMAL_DIODE: reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin); @@ -113,6 +136,7 @@ static void fan_smartconfig(const u16 base, const u8 fan, u8 pwm_ctrl; u8 pwm_start = 0; u8 pwm_auto = 0; + u8 delta_temp; if (mode == FAN_SMART_SOFTWARE) { pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_SOFTWARE; @@ -127,13 +151,19 @@ static void fan_smartconfig(const u16 base, const u8 fan, pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC; pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); - pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - - if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { - pwm_auto = conf->slope & 0x7f; - } else { - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + if (conf->clsd_loop) { + pwm_ctrl |= ITE_EC_FAN_PWM_CLSD_LOOP; + pwm_start = ITE_EC_FAN_CTL_PWM_START_RPM(conf->rpm_start); pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } else { + pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } } if (conf->smoothing) @@ -145,8 +175,11 @@ static void fan_smartconfig(const u16 base, const u8 fan, /* Full speed above 127°C by default */ pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan), conf->tmp_full ? conf->tmp_full : 127); + + delta_temp = ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta); + delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt); pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), - ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); + delta_temp); } pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); @@ -260,6 +293,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) ITE_EC_INTERFACE_SMB_ENABLE); } + /* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */ + if (conf->smbus_24mhz) { + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_CLOCK_24MHZ); + } + /* Enable reading of voltage pins */ pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index e8fb1f5b01..5a31e7cfbc 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -91,6 +91,7 @@ ? (0x1e + ((x)-4)) \ : (0x15 + ((x)-1)) \ ) +#define ITE_EC_FAN_PWM_CLSD_LOOP (1 << 2) #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CTL_TEMPIN_MASK (7 << 3) @@ -110,6 +111,13 @@ ? ITE_EC_FAN_MAX_PWM \ : (_p * ITE_EC_FAN_MAX_PWM) / 100; \ }) +#define ITE_EC_FAN_CTL_PWM_RPM(p) \ + ({ \ + const unsigned int _p = p; \ + (_p >= 4080) \ + ? 0xFF \ + : (_p / 16); \ + }) #define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) #define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) @@ -121,6 +129,7 @@ #define ITE_EC_ADC_TEMP_RESISTOR_MODE(x) (1 << ((x)+2)) #define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1)) #define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55 +#define ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT (1 << 7) /* Matches length of ITE_EC_TMPIN_CNT */ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; @@ -178,6 +187,7 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; /* Common for ITE_EC_FAN_CTL_PWM_START */ #define ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(s) (((s) & 0x40) << 1) #define ITE_EC_FAN_CTL_PWM_START_DUTY(p) ITE_EC_FAN_CTL_PWM_DUTY(p) +#define ITE_EC_FAN_CTL_PWM_START_RPM(p) ITE_EC_FAN_CTL_PWM_RPM(p) /* Common for ITE_EC_FAN_CTL_PWM_AUTO */ #define ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) @@ -185,6 +195,7 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; /* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(x) (((x) & 0x1) << 6) #define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 6a027b90f1..2bb0780c53 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -50,15 +50,18 @@ enum ite_ec_fan_mode { }; struct ite_ec_fan_smartconfig { - u8 tmpin; /* select TMPINx (1, 2 or 3) */ - u8 tmp_off; /* turn fan off below (°C) */ - u8 tmp_start; /* turn fan on above (°C) */ - u8 tmp_full; /* 100% duty cycle above (°C) */ - u8 tmp_delta; /* adapt fan speed when temperature - changed by at least `tmp_delta`°C */ - u8 smoothing; /* enable smoothing */ - u8 pwm_start; /* start at this duty cycle (%) */ - u8 slope; /* increase duty cycle by `slope`%/°C */ + u8 tmpin; /* select TMPINx (1, 2 or 3) */ + u8 tmp_off; /* turn fan off below (°C) */ + u8 tmp_start; /* turn fan on above (°C) */ + u8 tmp_full; /* 100% duty cycle above (°C) */ + u8 tmp_delta; /* adapt fan speed when temperature changed by + at least `tmp_delta`°C */ + u8 full_lmt; /* force fan to full PWM at thermal limit */ + u8 smoothing; /* enable smoothing */ + u8 pwm_start; /* start at this duty cycle (%) */ + u8 slope; /* increase duty cycle by `slope`%/°C */ + u8 clsd_loop; /* tachometer closed-loop mode enable */ + u16 rpm_start; /* start at this RPM (clsd_loop = 1) */ }; struct ite_ec_fan_config { @@ -90,6 +93,11 @@ struct ite_ec_config { * Enable SMBus for external thermal sensor. */ bool smbus_en; + /* + * Select 24 MHz clock for external host instead of an + * internally generated 32 MHz clock. + */ + bool smbus_24mhz; }; /* Some shorthands for device trees */ diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index a0c20ff8e1..3e9b50289a 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -15,6 +15,7 @@ void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h index 13e723c9be..009f8666d9 100644 --- a/src/superio/ite/it8528e/it8528e.h +++ b/src/superio/ite/it8528e/it8528e.h @@ -19,5 +19,4 @@ #define IT8528E_PMC4 0x18 /* Power Management Channel 4 */ #define IT8528E_PMC5 0x19 /* Power Management Channel 5 */ - #endif /* SUPERIO_ITE_IT8528E_H */ diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index d5ccb65f60..e6f01c4cac 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -8,3 +8,4 @@ config SUPERIO_ITE_IT8613E select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8623e/Kconfig b/src/superio/ite/it8623e/Kconfig index ea57a35e0a..44a79ec723 100644 --- a/src/superio/ite/it8623e/Kconfig +++ b/src/superio/ite/it8623e/Kconfig @@ -7,3 +7,4 @@ config SUPERIO_ITE_IT8623E select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index 2c3051bce6..ec22a2d5a0 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -3,3 +3,7 @@ config SUPERIO_ITE_IT8721F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 46410af9f0..6d02c0b424 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -7,3 +7,6 @@ config SUPERIO_ITE_IT8728F select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl index b42e71eae9..5132df0762 100644 --- a/src/superio/ite/it8772f/acpi/superio.asl +++ b/src/superio/ite/it8772f/acpi/superio.asl @@ -39,33 +39,33 @@ Device (SIO) { Method (ENTR, 0, NotSerialized) { - Store (0x87, SI2E) - Store (0x01, SI2E) - Store (0x55, SI2E) - Store (0x55, SI2E) + SI2E = 0x87 + SI2E = 0x01 + SI2E = 0x55 + SI2E = 0x55 } Method (EXIT, 0, NotSerialized) { - Store (0x02, SCNT) + SCNT = 0x02 } /* Parse activate register for an LDN */ Method (ISEN, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (SACT, Local0) + SLDN = Arg0 + Local0 = SACT EXIT () /* Check if it exists */ - If (LEqual (Local0, 0xFF)) + If (Local0 == 0xFF) { Return (0x00) } /* Check if activated */ - If (LEqual (Local0, One)) + If (Local0 == 1) { Return (0x0F) } @@ -79,8 +79,8 @@ Device (SIO) { Method (SENA, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (One, SACT) + SLDN = Arg0 + SACT = 1 EXIT () } @@ -88,8 +88,8 @@ Device (SIO) { Method (SDIS, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (Zero, SACT) + SLDN = Arg0 + SACT = 0 EXIT () } diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index 0af3f30750..e41b206e8c 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include "it8772f.h" @@ -27,7 +28,7 @@ void it8772f_ac_resume_southbridge(pnp_devfn_t dev) { it8772f_enter_conf(dev); pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); - pnp_write_config(dev, 0xf4, 0x60); + pnp_write_config(dev, PNP_IDX_MSC4, 0x60); it8772f_exit_conf(dev); } diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 2663884eb7..949ec116f5 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -129,5 +129,4 @@ void it8772f_exit_conf(pnp_devfn_t dev); void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable, u8 led_pin_map, u8 led_freq); - #endif /* SUPERIO_ITE_IT8772F_H */ diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 332f6020c6..216d6f5bf8 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -7,3 +7,4 @@ config SUPERIO_ITE_IT8786E select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc index 1b5c395cd6..2419e47cd3 100644 --- a/src/superio/nsc/Makefile.inc +++ b/src/superio/nsc/Makefile.inc @@ -4,11 +4,7 @@ bootblock-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c -subdirs-y += pc87309 -subdirs-y += pc87360 -subdirs-y += pc87366 subdirs-y += pc87382 subdirs-y += pc87384 subdirs-y += pc87392 subdirs-y += pc87417 -subdirs-y += pc97317 diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index c3af2d7314..c0bb2efa27 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -27,7 +27,7 @@ void xbus_cfg(pnp_devfn_t dev) /* Select proper BIOS size (4MB). */ pnp_write_config(dev, PC87417_XMEMCNF2, (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04); - xbus_index = pnp_read_iobase(dev, 0x60); + xbus_index = pnp_read_iobase(dev, PNP_IDX_IO0); /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ for (i = 0; i <= 0xf; i++) diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 054c7bae77..e9ac2e37f1 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -4,9 +4,6 @@ bootblock-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c -## include generic Nuvoton HWM driver -ramstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_HWM) += common/hwm.c - subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d diff --git a/src/superio/nuvoton/common/hwm.c b/src/superio/nuvoton/common/hwm.c deleted file mode 100644 index fb7b79ce69..0000000000 --- a/src/superio/nuvoton/common/hwm.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Nuvoton is a Winbond spin-off, so this code is for both */ - -#include -#include -#include "hwm.h" - -#define HWM_BANK_SELECT 0x4e - -void nuvoton_hwm_select_bank(const u16 base, const u8 bank) -{ - pnp_write_hwm5_index(base, HWM_BANK_SELECT, bank); -} diff --git a/src/superio/nuvoton/common/hwm.h b/src/superio/nuvoton/common/hwm.h index 47d4e04e41..42e0f4af94 100644 --- a/src/superio/nuvoton/common/hwm.h +++ b/src/superio/nuvoton/common/hwm.h @@ -6,7 +6,13 @@ /* Nuvoton is a Winbond spin-off, so this code is for both */ #include +#include -void nuvoton_hwm_select_bank(const u16 base, const u8 bank); +#define HWM_BANK_SELECT 0x4e + +static inline void nuvoton_hwm_select_bank(const u16 base, const u8 bank) +{ + pnp_write_hwm5_index(base, HWM_BANK_SELECT, bank); +} #endif /* SUPERIO_NUVOTON_COMMON_HWM_H */ diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index 5ed4c5cdec..c5e9388ebd 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include "nct5104d.h" diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h index 46abf05c70..85f4081368 100644 --- a/src/superio/nuvoton/nct6779d/nct6779d.h +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -20,7 +20,6 @@ #define NCT6779D_PRT80 0x14 /* Port 80 UART */ #define NCT6779D_DSLP 0x16 /* Deep sleep */ - /* virtual LDN for GPIO */ #define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V) diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index ef50aa6c05..77058b0bc3 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -7,7 +7,6 @@ #include "nct6779d.h" - static void nct6779d_init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 543fc5ed1e..d974afef25 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -7,6 +7,7 @@ #include #include #include + #include "pilot.h" /* @@ -24,10 +25,10 @@ void pilot_early_init(pnp_devfn_t dev) pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_set_enable(dev, 0); - pnp_set_iobase(dev, 0x60, 0x0b00); - pnp_set_iobase(dev, 0x62, 0x0b80); - pnp_set_iobase(dev, 0x64, 0x0b84); - pnp_set_iobase(dev, 0x66, 0x0b86); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0b00); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x0b80); + pnp_set_iobase(dev, PNP_IDX_IO2, 0x0b84); + pnp_set_iobase(dev, PNP_IDX_IO3, 0x0b86); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 9442a9efde..86cf9c510f 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -1,9 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -subdirs-y += dme1737 subdirs-y += fdc37n972 -subdirs-y += lpc47b272 -subdirs-y += lpc47b397 subdirs-y += lpc47m10x subdirs-y += lpc47m15x subdirs-y += lpc47n207 @@ -15,5 +12,4 @@ subdirs-y += kbc1100 subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 -subdirs-y += sch4037 subdirs-y += sch5545 diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index 5027584527..2210c2bf59 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -46,8 +46,8 @@ void kbc1100_early_init(u16 port) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_irq(dev, PNP_IDX_IRQ0, 1); /* IRQ 1 */ + pnp_set_irq(dev, PNP_IDX_IRQ1, 12); /* IRQ 12 */ pnp_set_enable(dev, 1); /* Enable EC Channel 0 */ diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index b688697ace..f69232377d 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -37,30 +37,30 @@ Device (SIO) { Method (ENTR, 0, NotSerialized) { - Store (0x55, SI2E) + SI2E = 0x55 } Method (EXIT, 0, NotSerialized) { - Store (0xaa, SI2E) + SI2E = 0xaa } /* Parse activate register for an LDN */ Method (ISEN, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (SACT, Local0) + SLDN = Arg0 + Local0 = SACT EXIT () /* Check if it exists */ - If (LEqual (Local0, 0xFF)) + If (Local0 == 0xFF) { Return (0x00) } /* Check if activated */ - If (LEqual (Local0, One)) + If (Local0 == 1) { Return (0x0F) } @@ -74,8 +74,8 @@ Device (SIO) { Method (SENA, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (One, SACT) + SLDN = Arg0 + SACT = 1 EXIT () } @@ -83,8 +83,8 @@ Device (SIO) { Method (SDIS, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (Zero, SACT) + SLDN = Arg0 + SACT = 0 EXIT () } diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl index a8a24a5fd9..d5040e73b5 100644 --- a/src/superio/smsc/sch5147/acpi/superio.asl +++ b/src/superio/smsc/sch5147/acpi/superio.asl @@ -124,7 +124,7 @@ Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) { Method (_DIS) { ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) - Store (Zero, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 0 EXIT_CONFIG_MODE () #if defined(SUPERIO_KBC_PS2LDN) Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1) @@ -169,7 +169,7 @@ Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) { }) ENTER_CONFIG_MODE (SUPERIO_KBC_LDN) PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE () Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1) } diff --git a/src/superio/smsc/sch5545/sch5545.h b/src/superio/smsc/sch5545/sch5545.h index 464be1a106..9d5054efa0 100644 --- a/src/superio/smsc/sch5545/sch5545.h +++ b/src/superio/smsc/sch5545/sch5545.h @@ -131,7 +131,6 @@ #define SCH5545_IRQ_PARPORT 0x11 #define SCH5545_IRQ_DISABLED 0xff - /* runtime registers */ #define SCH5545_RR_PME_STS 0x00 #define SCH5545_GLOBAL_PME_STS 0x01 diff --git a/src/superio/smsc/sch5545/sch5545_early_init.c b/src/superio/smsc/sch5545/sch5545_early_init.c index 4841571113..ed4fa5337b 100644 --- a/src/superio/smsc/sch5545/sch5545_early_init.c +++ b/src/superio/smsc/sch5545/sch5545_early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include "sch5545.h" diff --git a/src/superio/smsc/sch5545/sch5545_emi.c b/src/superio/smsc/sch5545/sch5545_emi.c index 2bb150c69b..367148aef2 100644 --- a/src/superio/smsc/sch5545/sch5545_emi.c +++ b/src/superio/smsc/sch5545/sch5545_emi.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl index b42e71eae9..5132df0762 100644 --- a/src/superio/smsc/sio1007/acpi/superio.asl +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -39,33 +39,33 @@ Device (SIO) { Method (ENTR, 0, NotSerialized) { - Store (0x87, SI2E) - Store (0x01, SI2E) - Store (0x55, SI2E) - Store (0x55, SI2E) + SI2E = 0x87 + SI2E = 0x01 + SI2E = 0x55 + SI2E = 0x55 } Method (EXIT, 0, NotSerialized) { - Store (0x02, SCNT) + SCNT = 0x02 } /* Parse activate register for an LDN */ Method (ISEN, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (SACT, Local0) + SLDN = Arg0 + Local0 = SACT EXIT () /* Check if it exists */ - If (LEqual (Local0, 0xFF)) + If (Local0 == 0xFF) { Return (0x00) } /* Check if activated */ - If (LEqual (Local0, One)) + If (Local0 == 1) { Return (0x0F) } @@ -79,8 +79,8 @@ Device (SIO) { Method (SENA, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (One, SACT) + SLDN = Arg0 + SACT = 1 EXIT () } @@ -88,8 +88,8 @@ Device (SIO) { Method (SDIS, 1, NotSerialized) { ENTR () - Store (Arg0, SLDN) - Store (Zero, SACT) + SLDN = Arg0 + SACT = 0 EXIT () } diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 81ec0aab5c..b9f6e70fef 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -24,7 +24,6 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) outb(SMSC_EXIT_KEY, port); } - /** * Enable the specified serial port. * diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index f6b9d571df..f8ac8ac3c3 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -10,6 +10,5 @@ subdirs-y += w83627hf subdirs-y += w83627thg subdirs-y += w83627uhg subdirs-y += w83667hg-a -subdirs-y += w83697hf subdirs-y += w83977tf subdirs-y += wpcd376i diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 4667b13b28..298e9a7c0d 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -111,7 +111,7 @@ Device(SUPERIO_DEV) { /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) - Store (IPD, Local0) + Local0 = IPD EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } @@ -120,14 +120,14 @@ Device(SUPERIO_DEV) { /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) - Store (Zero, IPD) + IPD = 0 EXIT_CONFIG_MODE () } /* PM: Switch to D3 by setting IPD high */ Method (_PS3) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) - Store (One, IPD) + IPD = 1 EXIT_CONFIG_MODE () } @@ -145,10 +145,10 @@ Device(SUPERIO_DEV) { #define SUPERIO_SUSL_LDN 9 Method (SUSL, 1, Serialized) { ENTER_CONFIG_MODE (SUPERIO_SUSL_LDN) - Store (SULM, Local0) - And (Local0, 0x1f, Local0) - Or (Local0, ShiftLeft (Arg0, 5), Local0) - Store (Local0, SULM) + Local0 = SULM + Local0 &= 0x1f + Local0 |= (Arg0 << 5) + SULM = Local0 EXIT_CONFIG_MODE () } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 588cda4fb3..4b54bac98d 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -29,10 +29,10 @@ static void set_uart_clock_source(struct device *dev, u8 uart_clock) pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); - value = pnp_read_config(dev, 0xf0); + value = pnp_read_config(dev, PNP_IDX_MSC0); value &= ~0x03; value |= (uart_clock & 0x03); - pnp_write_config(dev, 0xf0, value); + pnp_write_config(dev, PNP_IDX_MSC0, value); pnp_exit_conf_mode(dev); } diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index 36d7681561..08d63da530 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -80,7 +80,7 @@ IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) /* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ Method (_PSC) { ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) - Store (IPD, Local0) + Local0 = IPD EXIT_CONFIG_MODE () If (Local0) { Return (3) } Else { Return (0) } @@ -118,11 +118,11 @@ Device (FDC0) PNP_READ_IO(PNP_IO0, BUF0, IO0) /* Store xx7 range first so the value isn't overwritten * for below */ - Add(IO0I, 7, IO1I) - Store(IO1I, IO1A) + IO1I += 7 + IO1A = IO1I /* Store xx2 range */ - Add(IO0I, 2, IO0I) - Store(IO0I, IO0A) + IO0I += 2 + IO0A = IO0I /* End OEM BIOS deficiency */ PNP_READ_IRQ(PNP_IRQ0, BUF0, Y08) PNP_READ_DMA(PNP_DMA0, BUF0, Y09) @@ -147,11 +147,11 @@ Device (FDC0) CreateByteField (Arg0, 0x15, DMAV) ENTER_CONFIG_MODE(W83977TF_FDC) /* FDC base port on 8-byte boundary. */ - And (IOLO, 0xF8, PNP_IO0_LOW_BYTE) - Store (IOHI, PNP_IO0_HIGH_BYTE) - Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) - Subtract (FindSetLeftBit (DMAV), 1, PNP_DMA0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_IO0_LOW_BYTE = IOLO & 0xF8 + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DMA0 = FindSetLeftBit (DMAV) - 1 + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE() } } @@ -165,11 +165,11 @@ Device (LPT) Method (_STA, 0, NotSerialized) { ENTER_CONFIG_MODE(W83977TF_PP) - And (OPT1, 0x02, Local0) - If (LOr (IO0H, IO0L)) + Local0 = OPT1 & 0x02 + If (IO0H || IO0L) { /* Report device not present if ECP is enabled */ - If (LEqual (Local0, 0x02)) + If (Local0 == 0x02) { EXIT_CONFIG_MODE() Return (0x00) @@ -239,10 +239,10 @@ Device (LPT) CreateByteField (Arg0, 0x03, IOHI) CreateWordField (Arg0, 0x09, IRQW) ENTER_CONFIG_MODE(W83977TF_PP) - Store (IOLO, PNP_IO0_LOW_BYTE) - Store (IOHI, PNP_IO0_HIGH_BYTE) - Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_IO0_LOW_BYTE = IOLO + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE() } } @@ -254,10 +254,10 @@ Device (ECP) Method (_STA, 0, NotSerialized) { ENTER_CONFIG_MODE(W83977TF_PP) - And (OPT1, 0x02, Local0) - If (LOr (IO0H, IO0L)) + Local0 = OPT1 & 0x02 + If (IO0H || IO0L) { - If (LEqual (Local0, 0x02)) + If (Local0 == 0x02) { If (PNP_DEVICE_ACTIVE) { @@ -339,11 +339,11 @@ Device (ECP) CreateByteField (Arg0, 0x15, DMAC) ENTER_CONFIG_MODE(W83977TF_PP) - Store (IOLO, PNP_IO0_LOW_BYTE) - Store (IOHI, PNP_IO0_HIGH_BYTE) - Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) - Subtract (FindSetLeftBit (DMAC), 1, PNP_DMA0) - Store (One, PNP_DEVICE_ACTIVE) + PNP_IO0_LOW_BYTE = IOLO + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DMA0 = FindSetLeftBit (DMAC) - 1 + PNP_DEVICE_ACTIVE = 1 EXIT_CONFIG_MODE() } } diff --git a/src/superio/winbond/wpcd376i/Kconfig b/src/superio/winbond/wpcd376i/Kconfig new file mode 100644 index 0000000000..6d7bc7a9b1 --- /dev/null +++ b/src/superio/winbond/wpcd376i/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_WINBOND_WPCD376I + bool + select SUPERIO_WINBOND_COMMON_PRE_RAM diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc new file mode 100644 index 0000000000..e8e5e72a58 --- /dev/null +++ b/src/superio/winbond/wpcd376i/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c new file mode 100644 index 0000000000..a692eeb25d --- /dev/null +++ b/src/superio/winbond/wpcd376i/superio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include "wpcd376i.h" + +static void init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case WPCD376I_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, WPCD376I_FDC, + PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC8, + 0x07f8, }, + { NULL, WPCD376I_LPT, + PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC8, + 0x03f8, }, + { NULL, WPCD376I_SP1, + PNP_IO0 | PNP_IRQ0 | PNP_MSC0, + 0x07f8, }, + { NULL, WPCD376I_SWC, + PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0xfff0, 0xfff0, }, + { NULL, WPCD376I_KBCM, + PNP_IRQ0, }, + { NULL, WPCD376I_KBCK, + PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07f8, 0x07f8, }, + { NULL, WPCD376I_GPIO, + PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | + PNP_MSC8, + 0xffe0, }, + { NULL, WPCD376I_ECIR, + PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0xfff0, 0xfff0, }, + { NULL, WPCD376I_IR, + PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1 | PNP_MSC0, + 0xfff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_winbond_wpcd376i_ops = { + CHIP_NAME("Winbond WPCD376I Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h new file mode 100644 index 0000000000..6d49303614 --- /dev/null +++ b/src/superio/winbond/wpcd376i/wpcd376i.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H +#define SUPERIO_WINBOND_WPCD376I_WPCD376I_H + +/* Logical Device Numbers (LDN). */ +#define WPCD376I_FDC 0x00 /* Floppy */ +#define WPCD376I_LPT 0x01 /* Parallel port */ +/* 0x02 Undefined */ +#define WPCD376I_SP1 0x03 /* UART1 */ +#define WPCD376I_SWC 0x04 /* System wake-up control */ +#define WPCD376I_KBCM 0x05 /* PS/2 mouse */ +#define WPCD376I_KBCK 0x06 /* PS/2 keyboard */ +#define WPCD376I_GPIO 0x07 /* General Purpose I/O */ +#define WPCD376I_ECIR 0x15 /* Enhanced Consumer Infrared Functions (ECIR) */ +#define WPCD376I_IR 0x16 /* UART3 & Infrared port */ + +#endif diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 03f1670049..e7d02fa9c5 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -1158,9 +1158,10 @@ typedef enum { /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; /// diff --git a/src/vendorcode/amd/agesa/f14/Include/Filecode.h b/src/vendorcode/amd/agesa/f14/Include/Filecode.h index 060e6ccb31..7420811fda 100644 --- a/src/vendorcode/amd/agesa/f14/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f14/Include/Filecode.h @@ -628,31 +628,31 @@ #define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) #define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_DR_MNDR_FILECODE (0xF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0xF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0xF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0xF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0xF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0xF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0xF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0xF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0xF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0xF21E) +#define PROC_MEM_NB_RB_MNRB_FILECODE (0xF220) +#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0xF221) +#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0xF222) +#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0xF223) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0xF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0xF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0xF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0xF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0xF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0xF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0xF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0xF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0xF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0xF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0xF23E) #define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) #define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) #define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) @@ -663,190 +663,190 @@ #define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) #define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) #define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0xF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0xF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0xF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0xF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0xF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0xF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0xF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0xF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0xF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0xF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0xF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0xF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0xF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0xF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0xF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0xF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0xF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0xF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0xF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0xF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0xF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0xF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0xF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0xF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0xF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0xF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0xF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0xF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0xF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0xF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0xF277) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0xF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0xF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0xF287) +#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0xF288) +#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0xF289) +#define PROC_MEM_NB_PH_MNPH_FILECODE (0xF28A) +#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0xF28B) +#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0xF28C) +#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0xF290) +#define PROC_MEM_NB_OR_MNOR_FILECODE (0xF291) +#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0xF292) +#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0xF293) +#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0xF294) +#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0xF295) +#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0xF296) +#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0xF297) +#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0xF298) +#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0xF299) +#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0xF29A) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0xF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0xF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0xF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0xF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0xF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0xF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0xF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0xF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0xF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0xF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0xF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0xF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0xF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0xF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0xF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0xF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0xF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0xF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0xF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0xF415) +#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0xF416) +#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0xF417) +#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0xF418) +#define PROC_MEM_PS_RB_MPURB3_FILECODE (0xF419) +#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0xF41A) +#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0xF41B) +#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0xF41C) +#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0xF41D) +#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0xF41E) +#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0xF41F) +#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0xF420) +#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0xF421) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_OR_MPOR3_FILECODE (0xF42C) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0xF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0xF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0xF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0xF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0xF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0xF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0xF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0xF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0xF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0xF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0xF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0xF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0xF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0xF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0xF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0xF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0xF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0xF853) #define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) #define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) #define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) #define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) #define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0xF8CD) +#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0xF8CE) +#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0xF8CF) +#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0xF8D0) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0xF8EA) +#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0xF8EB) +#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0xF8EC) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0xF8ED) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0xF8EE) +#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0xF8EF) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0xF8F0) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0xF8F1) +#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0xF8F2) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h index 2d33021ba3..6c047a1f44 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h @@ -474,7 +474,7 @@ typedef struct { } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h index 7d43c1751b..c2ffcb6122 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h @@ -203,7 +203,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031 -#define MSR_CPUID_NAME_STRING2 0XC0010032 +#define MSR_CPUID_NAME_STRING2 0xC0010032 #define MSR_CPUID_NAME_STRING3 0xC0010033 #define MSR_CPUID_NAME_STRING4 0xC0010034 #define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index 922a8ee633..d41a5eec77 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1546,9 +1546,10 @@ typedef enum { /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; /// diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h index 274ef1431f..670d7a9359 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h @@ -836,31 +836,31 @@ #define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) #define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_DR_MNDR_FILECODE (0xF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0xF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0xF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0xF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0xF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0xF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0xF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0xF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0xF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0xF21E) +#define PROC_MEM_NB_RB_MNRB_FILECODE (0xF220) +#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0xF221) +#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0xF222) +#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0xF223) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0xF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0xF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0xF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0xF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0xF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0xF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0xF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0xF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0xF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0xF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0xF23E) #define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) #define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) #define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) @@ -871,171 +871,171 @@ #define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) #define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) #define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0xF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0xF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0xF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0xF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0xF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0xF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0xF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0xF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0xF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0xF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0xF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0xF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0xF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0xF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0xF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0xF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0xF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0xF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0xF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0xF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0xF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0xF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0xF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0xF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0xF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0xF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0xF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0xF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0xF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0xF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0xF277) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0xF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0xF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0xF287) +#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0xF288) +#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0xF289) +#define PROC_MEM_NB_PH_MNPH_FILECODE (0xF28A) +#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0xF28B) +#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0xF28C) +#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0xF290) +#define PROC_MEM_NB_OR_MNOR_FILECODE (0xF291) +#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0xF292) +#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0xF293) +#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0xF294) +#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0xF295) +#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0xF296) +#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0xF297) +#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0xF298) +#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0xF299) +#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0xF29A) +#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0xF29B) +#define PROC_MEM_NB_TN_MNTN_FILECODE (0xF29C) +#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0xF29D) +#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0xF29E) +#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0xF29F) +#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0xF2A0) +#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0xF2A1) +#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0xF2A2) +#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0xF2A3) +#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0xF2A4) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF43F) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0xF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0xF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0xF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0xF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0xF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0xF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0xF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0xF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0xF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0xF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0xF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0xF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0xF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0xF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0xF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0xF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0xF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0xF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0xF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0xF415) +#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0xF416) +#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0xF417) +#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0xF418) +#define PROC_MEM_PS_RB_MPURB3_FILECODE (0xF419) +#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0xF41A) +#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0xF41B) +#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0xF41C) +#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0xF41D) +#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0xF41E) +#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0xF41F) +#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0xF420) +#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0xF421) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_OR_MPOR3_FILECODE (0xF42C) +#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0xF42D) +#define PROC_MEM_PS_TN_MPTN3_FILECODE (0xF42E) +#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0xF42F) +#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0xF430) +#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0xF431) +#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0xF432) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF43F) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0xF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0xF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0xF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0xF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0xF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0xF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0xF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0xF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0xF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0xF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0xF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0xF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0xF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0xF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0xF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0xF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0xF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0xF853) #define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) #define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) #define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) @@ -1044,43 +1044,43 @@ #define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) #define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) #define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0XF8FA) -#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0XF8FB) -#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0XF8FC) -#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0XF8FD) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FE) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0xF8CD) +#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0xF8CE) +#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0xF8CF) +#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0xF8D0) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0xF8F3) +#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0xF8F4) +#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0xF8F5) +#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0xF8F6) +#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0xF8F7) +#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0xF8F8) +#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0xF8F9) +#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0xF8FA) +#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0xF8FB) +#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0xF8FC) +#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0xF8FD) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FE) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h index c21cb9c845..ca44580533 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h @@ -490,7 +490,7 @@ typedef struct { } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h index 48fcb24efe..ecef9a7371 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -212,7 +212,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c index cd52636bef..1cfddbea63 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c @@ -154,8 +154,8 @@ REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] = // SMBUS Device (Bus 0, Dev 20, Func 0) // {0x00, SMBUS_BUS_DEV_FUN, 0}, - {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information - {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)}, + {FCH_CFG_REG10, 0x00, (FCH_VERSION & 0xFF)}, ///Program the version information + {FCH_CFG_REG11, 0x00, (FCH_VERSION >> 8)}, {0xFF, 0xFF, 0xFF}, }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c index ce50a975c7..6177d08ef1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c @@ -73,7 +73,7 @@ CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = { {0 , 0 , 0 , 0 , 333, 0, 400, 0 }, {0 , 0 , 533, 0 , 0 , 0 , 667, 0 }, -{0 , 0 , 800, 0 , 0 , 0 , 0 , 0 }, +{0 , 0 , 800, 0 , 0 , 0 , 933, 0 }, {0 , 1050, 1066, 0 , 0, 0 , 0, 1200} }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c index 17fc1a7535..5032eaf683 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c @@ -122,6 +122,7 @@ MemNSyncTargetSpeedNb ( { CONST UINT16 DdrMaxRateTab[] = { UNSUPPORTED_DDR_FREQUENCY, + DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY, diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02aff7..68eaed89f2 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -157,7 +157,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index 7e43de416c..853fdc99e6 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -1621,9 +1621,10 @@ typedef enum { /// /// SPD Data for each DIMM. /// +#define DDR3_SPD_SIZE 256 typedef struct _SPD_DEF_STRUCT { IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid - IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM + IN UINT8 Data[DDR3_SPD_SIZE]; ///< Buffer for 256 Bytes of SPD data from DIMM } SPD_DEF_STRUCT; /// diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h index dcec44372e..8f73399b19 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h @@ -515,67 +515,67 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_KB_MMFLOWKB_FILECODE (0xF124) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_KB_MNREGKB_FILECODE (0XF2B8) -#define PROC_MEM_NB_KB_MNKB_FILECODE (0XF2B9) -#define PROC_MEM_NB_KB_MNMCTKB_FILECODE (0XF2BA) -#define PROC_MEM_NB_KB_MNOTKB_FILECODE (0XF2BB) -#define PROC_MEM_NB_KB_MNDCTKB_FILECODE (0XF2BC) -#define PROC_MEM_NB_KB_MNPHYKB_FILECODE (0XF2BD) -#define PROC_MEM_NB_KB_MNS3KB_FILECODE (0XF2BE) -#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE (0XF2BF) -#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE (0XF2C0) -#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE (0XF2C1) +#define PROC_MEM_NB_KB_MNREGKB_FILECODE (0xF2B8) +#define PROC_MEM_NB_KB_MNKB_FILECODE (0xF2B9) +#define PROC_MEM_NB_KB_MNMCTKB_FILECODE (0xF2BA) +#define PROC_MEM_NB_KB_MNOTKB_FILECODE (0xF2BB) +#define PROC_MEM_NB_KB_MNDCTKB_FILECODE (0xF2BC) +#define PROC_MEM_NB_KB_MNPHYKB_FILECODE (0xF2BD) +#define PROC_MEM_NB_KB_MNS3KB_FILECODE (0xF2BE) +#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE (0xF2BF) +#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE (0xF2C0) +#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE (0xF2C1) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_KB_MPSKB3_FILECODE (0XF438) -#define PROC_MEM_PS_KB_MPKB3_FILECODE (0XF439) -#define PROC_MEM_PS_KB_MPUKB3_FILECODE (0XF43A) -#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE (0XF43B) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_KB_MPSKB3_FILECODE (0xF438) +#define PROC_MEM_PS_KB_MPKB3_FILECODE (0xF439) +#define PROC_MEM_PS_KB_MPUKB3_FILECODE (0xF43A) +#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE (0xF43B) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h index 1f6341abe9..85fb9e4197 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h @@ -508,7 +508,7 @@ typedef struct { } PACKAGE_TYPE_FEATURES; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Initializer Values for Ht Host Pci Config Registers #define HT_HOST_FEAT_COHERENT BIT0 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h index e59bb88d7e..b1df1841d6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h @@ -290,7 +290,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h index c370d4c9cf..67a0f4b2da 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h @@ -1580,12 +1580,12 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_SMB_POLL2BYTE BIT7 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c index 7e9b64eab1..3bc99bfad6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c @@ -92,8 +92,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM6L[] = { {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -111,8 +111,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = { {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -130,8 +130,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM4L[] = { {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d970bf..9c7bf47f43 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -151,7 +151,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 3be69c3360..56e1a5ea1b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -54,14 +54,17 @@ typedef struct __packed { /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; /** Offset 0x00C5**/ uint8_t unused5; /** Offset 0x00C6**/ uint8_t unused6; - /** Offset 0x00C7**/ uint8_t unused7; + /** Offset 0x00C7**/ uint8_t sata_enable; /** Offset 0x00C8**/ uint32_t tseg_size; /** Offset 0x00CC**/ uint8_t pspp_policy; /** Offset 0x00CD**/ uint8_t audio_soundwire; - /** Offset 0x00CE**/ uint8_t unused8; + /** Offset 0x00CE**/ uint8_t hd_audio_enable; /** Offset 0x00CF**/ uint8_t unused9; /** Offset 0x00D0**/ uint32_t bert_size; - /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0[44]; + /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0; + /** Offset 0x00D5**/ uint8_t ccx_down_core_mode; + /** Offset 0x00D6**/ uint8_t ccx_disable_smt; + /** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41]; /** Offset 0x0100**/ uint16_t Reserved100; /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 11e77bd3ff..491ea476de 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -9,36 +9,38 @@ #include -#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 6 +#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8 #define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4 +#define FSPS_UPD_USB2_PORT_COUNT 6 typedef struct __packed { /** Offset 0x0020**/ uint32_t emmc0_mode; - /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x0029**/ uint8_t unused0[7]; /** Offset 0x0030**/ uint8_t dxio_descriptor[FSPS_UPD_DXIO_DESCRIPTOR_COUNT][16]; - /** Offset 0x0090**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; - /** Offset 0x00A0**/ uint32_t unused1; - /** Offset 0x00A4**/ uint32_t unused2; - /** Offset 0x00A8**/ uint32_t unused3; - /** Offset 0x00AC**/ uint32_t unused4; - /** Offset 0x00B0**/ uint8_t fch_usb_version_major; - /** Offset 0x00B1**/ uint8_t fch_usb_version_minor; - /** Offset 0x00B2**/ uint8_t fch_usb_2_port0_phy_tune[9]; - /** Offset 0x00BB**/ uint8_t fch_usb_2_port1_phy_tune[9]; - /** Offset 0x00C4**/ uint8_t fch_usb_2_port2_phy_tune[9]; - /** Offset 0x00CD**/ uint8_t fch_usb_2_port3_phy_tune[9]; - /** Offset 0x00D6**/ uint8_t fch_usb_2_port4_phy_tune[9]; - /** Offset 0x00DF**/ uint8_t fch_usb_2_port5_phy_tune[9]; - /** Offset 0x00E8**/ uint8_t fch_usb_device_removable; - /** Offset 0x00E9**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x00EA**/ uint8_t fch_usb_u3_rx_det_wa_enable; - /** Offset 0x00EB**/ uint8_t fch_usb_u3_rx_det_wa_portmap; - /** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; - /** Offset 0x00ED**/ uint8_t unused8; - /** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; - /** Offset 0x00F2**/ uint8_t xhci0_force_gen1; - /** Offset 0x00F3**/ uint8_t UnusedUpdSpace0[45]; - /** Offset 0x0120**/ uint16_t UpdTerminator; + /** Offset 0x00B0**/ uint8_t unused1[16]; + /** Offset 0x00C0**/ uint32_t ddi_descriptor[FSPS_UPD_DDI_DESCRIPTOR_COUNT]; + /** Offset 0x00D0**/ uint8_t unused2[16]; + /** Offset 0x00E0**/ uint8_t fch_usb_version_major; + /** Offset 0x00E1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00E2**/ uint8_t fch_usb_2_port_phy_tune[FSPS_UPD_USB2_PORT_COUNT][9]; + /** Offset 0x0118**/ uint8_t fch_usb_device_removable; + /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x011D**/ uint8_t unused3; + /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; + /** Offset 0x0122**/ uint8_t xhci0_force_gen1; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[38]; + /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration diff --git a/src/vendorcode/amd/fsp/picasso/dmi_info.h b/src/vendorcode/amd/fsp/picasso/dmi_info.h index adab2f92a3..36ca7195ba 100644 --- a/src/vendorcode/amd/fsp/picasso/dmi_info.h +++ b/src/vendorcode/amd/fsp/picasso/dmi_info.h @@ -178,7 +178,6 @@ typedef struct { OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). - OUT UINT32 _Reserved1_; OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT CHAR8 SerialNumber[9]; ///< Serial Number. OUT CHAR8 PartNumber[21]; ///< Part Number. @@ -188,8 +187,7 @@ typedef struct { OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts - OUT UINT32 _Reserved2_; -} TYPE17_DMI_INFO; +}__packed TYPE17_DMI_INFO; /// Collection of pointers to the DMI records typedef struct { diff --git a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h index dc3f94608f..c477a4ff1f 100644 --- a/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h +++ b/src/vendorcode/amd/fsp/picasso/fsp_h_c99.h @@ -27,7 +27,7 @@ typedef enum { EnumInitPhaseEndOfFirmware = 0xF0 } FSP_INIT_PHASE; -typedef struct { +typedef struct __packed { uint64_t Signature; uint8_t Revision; uint8_t Reserved[23]; @@ -35,7 +35,7 @@ typedef struct { _Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); -typedef struct { +typedef struct __packed { uint8_t Revision; uint8_t Reserved[3]; void *NvsBufferPtr; diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 17913c0c46..93f987bfaa 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -35,6 +35,8 @@ #define SVC_EXIT 0x00 #define SVC_MAP_USER_STACK 0x01 #define SVC_DEBUG_PRINT 0x06 +#define SVC_MODEXP 0x0C +#define SVC_RSAPSS_VERIFY 0x0D #define SVC_DEBUG_PRINT_EX 0x1A #define SVC_WAIT_10NS_MULTIPLE 0x1B #define SVC_GET_BOOT_MODE 0x1C @@ -51,6 +53,45 @@ #define SVC_WRITE_POSTCODE 0x44 #define SVC_GET_MAX_WORKBUF_SIZE 0x45 #define SVC_SHA 0x46 +#define SVC_RSAPKCS_VERIFY 0x47 + +/* Bit definitions for the psp_info field in the PSP transfer_info_struct */ +#define PSP_INFO_PRODUCTION_MODE 0x00000001UL +#define PSP_INFO_PRODUCTION_SILICON 0x00000002UL +#define PSP_INFO_VALID 0x80000000UL + +typedef struct MOD_EXP_PARAMS_T +{ + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent size in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus size in bytes + char *pMessage; // Message address, same size as ModulusSize + char *pOutput; // Output address; Must be big enough to hold the + // data of ModulusSize +} MOD_EXP_PARAMS; + +typedef struct _RSAPSS_VERIFY_PARAMS_T +{ + char *pHash; // Message digest to verify the RSA signature + unsigned int HashLen; // hash length in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus length in bytes + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent length in bytes + char *pSig; // Signature to be verified, same size as ModulusSize +} RSAPSS_VERIFY_PARAMS; + +typedef struct RSAPKCS_VERIFY_PARAMS_T +{ + char *pHash; // Message digest to verify the RSA signature + unsigned int HashLen; // hash length in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus length in bytes + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent length in bytes + char *pSig; // Signature to be verified, same size as ModulusSize +} RSAPKCS_VERIFY_PARAMS; typedef enum _PSP_BOOT_MODE { @@ -62,24 +103,6 @@ typedef enum _PSP_BOOT_MODE PSP_BOOT_MODE_S5_WARM = 0x5, } PSP_BOOT_MODE; -/* TLB2_n settings for AWUSER and TLB3_n settings for ARUSER: - * USER[0] - ReqIO bit, 1'b1 for FCH MMIO address - * USER[1] - Compat bit, 1'b1 for FCH access, 0 for everything else - * USER[2] - ByPass_IOMMU bit, 1'b1 to always bypass IOMMU, 0 for IOMMU translation - */ -typedef enum SYSHUB_TARGET_TYPE_E -{ - // Target Type // Address // [2:0] =[Bypass,Compat,ReqIO] - AxUSER_PCIE_HT0 = 0x0, // PCIe HT (Bypass=0) // [2:0] =[0,0,0] - AxUSER_DRAM_VIA_IOMMU = 0x1, // DRAM ACCESS via IOMMU// [2:0] =[0,0,1] - AxUSER_PCIE_HT1 = 0x2, // PCIe HT (Bypass=1) // [2:0] =[0,1,0] - AxUSER_RSVD = 0x3, // - NOT USED ,INVALID // [2:0] =[0,1,1] - AxUSER_DRAM_BYPASS_IOMMU = 0x4, // GENERAL DRAM // [2:0] =[1,0,0] - AxUSER_PCIE_MMIO = 0x5, // PCIe MMIO // [2:0] =[1,0,1] - AxUSER_FCH_HT_IO = 0x6, // FCH HT (port80) // [2:0] =[1,1,0] - AxUSER_FCH_MMIO = 0x6 // FCH MMIO // [2:0] =[1,1,1] -} SYSHUB_TARGET_TYPE; - typedef enum FCH_IO_DEVICE { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, @@ -123,15 +146,6 @@ typedef struct SPIROM_INFO uint32_t SpiBiosSize; } SPIROM_INFO; -typedef struct SYSHUB_RW_PARMS_EX_E -{ - uint32_t SyshubAddressLo; - uint32_t SyshubAddressHi; - uint32_t *pValue; - uint32_t Size; - SYSHUB_TARGET_TYPE TargetType; -} SYSHUB_RW_PARMS_EX; - typedef enum PSP_TIMER_TYPE { PSP_TIMER_TYPE_CHRONO = 0, PSP_TIMER_TYPE_RTC = 1, @@ -362,6 +376,35 @@ uint32_t svc_get_max_workbuf_size(uint32_t *size); */ uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode); +/* + * RSA PSS Verification of signature and data + * + * Parameters: + * RSAPSS_VERIFY_PARAMS - Pointer to RSA PSS parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_rsa_pss_verify(const RSAPSS_VERIFY_PARAMS *params); + +/* + * RSA PKCS Verification of signature and data + * + * Parameters: + * RSAPKCS_VERIFY_PARAMS - Pointer to RSA PKCS parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); + +/* Calculate ModEx + * + * Parameters: + * mod_exp_param - ModExp parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param); + /* C entry point for the Bootloader Userspace Application */ void Main(void); diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 9765ea6f2e..c3a09ccb78 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -28,6 +28,14 @@ typedef enum { GEN_INVALID // Max Gen for boundary check } dxio_link_speed_cap; +/* Upstream Auto Speed Change Allowed */ +typedef enum { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISBLED, + SPDC_ENABLED, + SPDC_INVALID +} dxio_upstream_auto_speed_change; + /* SATA ChannelType initialization */ typedef enum { SATA_CHANNEL_OTHER = 0, // Default Channel Type @@ -109,35 +117,73 @@ typedef struct __packed { uint8_t reserved; } fsp_ddi_descriptor; -/* Picasso PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ -/* Beware that the lane numbers in here are the logical and not the physical lane numbers! */ +/* + * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure + * bifurcation and other settings. Beware that the lane numbers in here are the logical and not + * the physical lane numbers! + * + * Picasso DXIO lane mapping: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[7:0] | [15:8] | PCIe + * GPP[3:0] | [7:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | PCIe, SATA + * + * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port + * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 + * ports. The ports can only start at logical lane numbers that are integer multiples of the + * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. + * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the + * same width the one with a higher start logical lane number needs to be assigned to a higher + * PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe + * root ports though. + * + * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: + * + * physical | logical | protocol + * ---------|---------|----------- + * GFX[3:0] | [11:8] | PCIe + * GPP[1:0] | [5:4] | PCIe + * GPP[5:4] | [1:0] | PCIe, XGBE + * GPP[7:6] | [3:2] | SATA + * + * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane + * numbers differs to Picasso/Dali: + * + * physical | logical | protocol + * ---------|---------|---------- + * GPP[1:0] | [1:0] | PCIe + * GPP[3:2] | [5:4] | PCIe + */ typedef struct __packed { - uint8_t engine_type; - uint8_t start_lane; // Start lane of the pci device - uint8_t end_lane; // End lane of the pci device - uint8_t gpio_group_id; // FCH reset number. 0 is global reset + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // Currently unused by FSP uint32_t port_present :1; // Should be TRUE if train link uint32_t reserved_3 :7; uint32_t device_number :5; // Desired root port device number uint32_t function_number :3; // Desired root port function number - uint32_t link_speed_capability :2; - uint32_t auto_spd_change :2; - uint32_t eq_preset :4; - uint32_t link_aspm :2; - uint32_t link_aspm_L1_1 :1; - uint32_t link_aspm_L1_2 :1; - uint32_t clk_req :4; - uint8_t link_hotplug; - uint8_t slot_power_limit; - uint32_t slot_power_limit_scale :2; + uint32_t link_speed_capability :2; // See dxio_link_speed_cap + uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint32_t eq_preset :4; // Gen3 equalization preset + uint32_t link_aspm :2; // See dxio_aspm_type + uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint32_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint32_t slot_power_limit_scale :2; // Currently unused by FSP uint32_t reserved_4 :6; - uint32_t link_compliance_mode :1; - uint32_t link_safe_mode :1; - uint32_t sb_link :1; - uint32_t clk_pm_support :1; - uint32_t channel_type :3; - uint32_t turn_off_unused_lanes :1; + uint32_t link_compliance_mode :1; // Currently unused by FSP + uint32_t link_safe_mode :1; // Currently unused by FSP + uint32_t sb_link :1; // Currently unused by FSP + uint32_t clk_pm_support :1; // Currently unused by FSP + uint32_t channel_type :3; // See dxio_sata_channel_type + uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present uint8_t reserved[4]; -} fsp_pcie_descriptor; +} fsp_dxio_descriptor; #endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ diff --git a/src/vendorcode/amd/pi/00630F01/Include/Filecode.h b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h index af31c46ab1..3c46301e11 100644 --- a/src/vendorcode/amd/pi/00630F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h @@ -648,25 +648,25 @@ #define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) #define PROC_MEM_MAIN_KV_MMFLOWD3KV_FILECODE (0xF122) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) -#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) -#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) -#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) -#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) -#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) -#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) -#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) -#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) -#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) +#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0xF29B) +#define PROC_MEM_NB_TN_MNTN_FILECODE (0xF29C) +#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0xF29D) +#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0xF29E) +#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0xF29F) +#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0xF2A0) +#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0xF2A1) +#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0xF2A2) +#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0xF2A3) +#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0xF2A4) #define PROC_MEM_NB_KV_MNKV_FILECODE (0xF2AF) #define PROC_MEM_NB_KV_MNMCTKV_FILECODE (0xF2B0) #define PROC_MEM_NB_KV_MNDCTKV_FILECODE (0xF2B1) @@ -676,91 +676,91 @@ #define PROC_MEM_NB_KV_MNPROTOKV_FILECODE (0xF2B5) #define PROC_MEM_NB_KV_MNREGKV_FILECODE (0xF2B6) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0XF2C2) -#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0XF2D7) +#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0xF2C2) +#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0xF2D7) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) -#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) -#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) -#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) -#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) -#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_KV_MPKV3_FILECODE (0XF43E) -#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0XF43F) -#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0XF440) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0xF42D) +#define PROC_MEM_PS_TN_MPTN3_FILECODE (0xF42E) +#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0xF42F) +#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0xF430) +#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0xF431) +#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0xF432) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_KV_MPKV3_FILECODE (0xF43E) +#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0xF43F) +#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0xF440) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) -#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0XF58E) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) +#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0xF58E) #define PROC_MEM_TECH_GDDR5_MNDCTG5_FILECODE (0xF58F) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) -#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) -#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) -#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) -#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) -#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) -#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0xF8F3) +#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0xF8F4) +#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0xF8F5) +#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0xF8F6) +#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0xF8F7) +#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0xF8F8) +#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0xF8F9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) //Psp #define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00) diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h index e41226a770..4c8a0a268a 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h @@ -307,7 +307,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h index 6685c67e20..b64fb57d77 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h @@ -2234,12 +2234,12 @@ FCH_MISC_REGF0 EQU 0F0h #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index cecf5ca230..887bf9ae08 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -152,7 +152,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h index 0e01812626..e17ac02516 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h @@ -545,15 +545,15 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) #define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) #define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) @@ -565,82 +565,82 @@ #define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) #define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) #define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) -#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0xF2E3) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) -#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) -#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) -#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) -#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0xF445) +#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0xF446) +#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0xF447) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0xF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0xF44B) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) #define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) #define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) //Psp #define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20) diff --git a/src/vendorcode/amd/pi/00660F01/Include/Ids.h b/src/vendorcode/amd/pi/00660F01/Include/Ids.h index cb101869e3..b711345892 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Ids.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Ids.h @@ -1081,7 +1081,7 @@ typedef enum { TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea TpProcS3Init, ///< 56 Entry point S3Init - TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing + TpProcCpuProcessRegisterTables = 0x58, ///< 58 .. Register table processing TpProcCpuSetBrandID, ///< 59 .. Set brand ID TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC TpProcCpuLoadUcode, ///< 5B .. Load microcode patch diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index 889be764a1..c16371f0a8 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -332,7 +332,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 92201b8a49..d061b5bb96 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2545,12 +2545,12 @@ FCH_AOAC_REG4X-7x State field #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 88e1a7d1be..87aeb4fc7b 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -161,7 +161,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h index 1d53990b7d..3742c19059 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h @@ -317,7 +317,7 @@ typedef union { } PERFORMANCE_PROFILE_FEATS; // Initializer Values for Package Type -#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages +#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages // Core Range Initializer values. #define COUNT_RANGE_LOW 0ul diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h index 46906a8783..bafe84fd08 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h @@ -334,7 +334,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h index ee8c961e96..653d92c911 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h @@ -2553,12 +2553,12 @@ FCH_AOAC_REG4X-7x State field #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index 46946327ce..152e2799c6 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -161,7 +161,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/amd/pi/00730F01/Include/Filecode.h b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h index c2893a74c3..2e7398dcc2 100644 --- a/src/vendorcode/amd/pi/00730F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h @@ -703,105 +703,105 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_ML_MMFLOWML_FILECODE (0xF126) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) -#define PROC_MEM_NB_ML_MNREGML_FILECODE (0XF2CD) -#define PROC_MEM_NB_ML_MNML_FILECODE (0XF2CE) -#define PROC_MEM_NB_ML_MNMCTML_FILECODE (0XF2CF) -#define PROC_MEM_NB_ML_MNOTML_FILECODE (0XF2D0) -#define PROC_MEM_NB_ML_MNDCTML_FILECODE (0XF2D1) -#define PROC_MEM_NB_ML_MNPHYML_FILECODE (0XF2D2) -#define PROC_MEM_NB_ML_MNS3ML_FILECODE (0XF2D3) -#define PROC_MEM_NB_ML_MNIDENDIMMML_FILECODE (0XF2D4) -#define PROC_MEM_NB_ML_MNFLOWML_FILECODE (0XF2D5) -#define PROC_MEM_NB_ML_MNPROTOML_FILECODE (0XF2D6) -#define PROC_MEM_NB_ML_MNPSPML_FILECODE (0XF2E2) +#define PROC_MEM_NB_ML_MNREGML_FILECODE (0xF2CD) +#define PROC_MEM_NB_ML_MNML_FILECODE (0xF2CE) +#define PROC_MEM_NB_ML_MNMCTML_FILECODE (0xF2CF) +#define PROC_MEM_NB_ML_MNOTML_FILECODE (0xF2D0) +#define PROC_MEM_NB_ML_MNDCTML_FILECODE (0xF2D1) +#define PROC_MEM_NB_ML_MNPHYML_FILECODE (0xF2D2) +#define PROC_MEM_NB_ML_MNS3ML_FILECODE (0xF2D3) +#define PROC_MEM_NB_ML_MNIDENDIMMML_FILECODE (0xF2D4) +#define PROC_MEM_NB_ML_MNFLOWML_FILECODE (0xF2D5) +#define PROC_MEM_NB_ML_MNPROTOML_FILECODE (0xF2D6) +#define PROC_MEM_NB_ML_MNPSPML_FILECODE (0xF2E2) -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_ML_MPSML3_FILECODE (0XF441) -#define PROC_MEM_PS_ML_MPML3_FILECODE (0XF442) -#define PROC_MEM_PS_ML_MPUML3_FILECODE (0XF443) -#define PROC_MEM_PS_ML_FT3_MPSMLFT3_FILECODE (0XF444) +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_ML_MPSML3_FILECODE (0xF441) +#define PROC_MEM_PS_ML_MPML3_FILECODE (0xF442) +#define PROC_MEM_PS_ML_MPUML3_FILECODE (0xF443) +#define PROC_MEM_PS_ML_FT3_MPSMLFT3_FILECODE (0xF444) -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) -#define PROC_RECOVERY_MEM_NB_ML_MRNDCTML_FILECODE (0XF902) -#define PROC_RECOVERY_MEM_NB_ML_MRNML_FILECODE (0XF903) -#define PROC_RECOVERY_MEM_NB_ML_MRNMCTML_FILECODE (0XF904) -#define PROC_RECOVERY_MEM_NB_ML_MRNPROTOML_FILECODE (0XF905) -#define PROC_RECOVERY_MEM_PS_ML_MRPSML3_FILECODE (0XF906) -#define PROC_RECOVERY_MEM_PS_ML_MRPML3_FILECODE (0XF907) -#define PROC_RECOVERY_MEM_PS_ML_MRPUML3_FILECODE (0XF908) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) +#define PROC_RECOVERY_MEM_NB_ML_MRNDCTML_FILECODE (0xF902) +#define PROC_RECOVERY_MEM_NB_ML_MRNML_FILECODE (0xF903) +#define PROC_RECOVERY_MEM_NB_ML_MRNMCTML_FILECODE (0xF904) +#define PROC_RECOVERY_MEM_NB_ML_MRNPROTOML_FILECODE (0xF905) +#define PROC_RECOVERY_MEM_PS_ML_MRPSML3_FILECODE (0xF906) +#define PROC_RECOVERY_MEM_PS_ML_MRPML3_FILECODE (0xF907) +#define PROC_RECOVERY_MEM_PS_ML_MRPUML3_FILECODE (0xF908) //Psp #define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00) diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h index 601a643ce2..e01e0f29d4 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h @@ -307,7 +307,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h index ab6f3c0d2e..50e839f444 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h @@ -2257,12 +2257,12 @@ FCH_MISC_REGF0 EQU 0F0h #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc index c246b99395..ef08c87761 100644 --- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc @@ -151,7 +151,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ diff --git a/src/vendorcode/cavium/bdk/lame_string.c b/src/vendorcode/cavium/bdk/lame_string.c index 6d261bccb5..61e48c68b8 100644 --- a/src/vendorcode/cavium/bdk/lame_string.c +++ b/src/vendorcode/cavium/bdk/lame_string.c @@ -1,5 +1,4 @@ /* - * * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights * reserved. * Copyright 2018-present Facebook, Inc. diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c index f6b69571fb..630403d44c 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c @@ -1,5 +1,4 @@ /* - * * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights * reserved. * Copyright 2018-present Facebook, Inc. diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c index a7602de758..4eeeca3dae 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-errata-cn8xxx.c @@ -166,7 +166,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 4: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -200,7 +200,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Enable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x1; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X1); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x1); /* Step 10: Set GSER()_LANE(lane_n)_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ] = 1 Start the CTLIFC override state machine */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), @@ -219,7 +219,7 @@ int __bdk_qlm_errata_gser_26150(bdk_node_t node, int qlm, int baud_mhz) Disable Rx power state override */ BDK_CSR_MODIFY(c, node, BDK_GSERX_LANEX_PCS_CTLIFC_2(qlm, i), c.s.cfg_tx_pstate_req_ovrrd_en = 0x0; - c.s.cfg_rx_pstate_req_ovrrd_en = 0X0); + c.s.cfg_rx_pstate_req_ovrrd_en = 0x0); } /* Step 13: Poll GSER()_PLL_STAT.[PLL_LOCK] = 1 Poll and check that PLL is locked */ diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 306678759d..92cbe74a01 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -3148,7 +3148,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node, bank_bits = (2 + ((spd_banks >> 4) & 0x3)) + ((spd_banks >> 6) & 0x3); bank_bits = min((int)bank_bits, 4); /* Controller can only address 4 bits. */ - spd_package = 0XFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); + spd_package = 0xFF & read_spd(node, &dimm_config_table[0], DDR4_SPD_PACKAGE_TYPE); if (spd_package & 0x80) { // non-monolithic device is_stacked_die = (!disable_stacked_die) ? ((spd_package & 0x73) == 0x11) : 0; ddr_print("DDR4: Package Type 0x%x (%s), %d die\n", spd_package, diff --git a/src/vendorcode/cavium/include/bdk/bdk-minimal.h b/src/vendorcode/cavium/include/bdk/bdk-minimal.h index d3c9f58dc6..031b69a40a 100644 --- a/src/vendorcode/cavium/include/bdk/bdk-minimal.h +++ b/src/vendorcode/cavium/include/bdk/bdk-minimal.h @@ -1,5 +1,4 @@ /* - * * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights * reserved. * Copyright 2017-present Facebook, Inc. diff --git a/src/vendorcode/cavium/include/bdk/bdk.h b/src/vendorcode/cavium/include/bdk/bdk.h index 6464137537..567dcf2709 100644 --- a/src/vendorcode/cavium/include/bdk/bdk.h +++ b/src/vendorcode/cavium/include/bdk/bdk.h @@ -1,5 +1,4 @@ /* - * * Copyright 2017-present Facebook, Inc. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/src/vendorcode/cavium/include/bdk/lame_string.h b/src/vendorcode/cavium/include/bdk/lame_string.h index 0cdba8c3f2..a16197a3f3 100644 --- a/src/vendorcode/cavium/include/bdk/lame_string.h +++ b/src/vendorcode/cavium/include/bdk/lame_string.h @@ -1,5 +1,4 @@ /* - * * Copyright 2018-present Facebook, Inc. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h index 20ed3af737..25887b477c 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h @@ -17483,7 +17483,7 @@ union bdk_ap_id_aa64mmfr0_el1 uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size. @@ -17600,7 +17600,7 @@ union bdk_ap_id_aa64mmfr0_el1 uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t reserved_32_63 : 32; @@ -17614,7 +17614,7 @@ union bdk_ap_id_aa64mmfr0_el1 uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t tgran64 : 4; /**< [ 27: 24](RO) Support for 64KB memory translation granule size. @@ -17735,7 +17735,7 @@ union bdk_ap_id_aa64mmfr0_el1 uint64_t tgran4 : 4; /**< [ 31: 28](RO) Support for 4KB memory translation granule size. All other values are reserved. 0x0 = 4KB granule supported. - 0XF = 4KB granule not supported. + 0xF = 4KB granule not supported. In CNXXXX, supported. */ uint64_t reserved_32_63 : 32; @@ -23442,14 +23442,14 @@ union bdk_ap_pmceid1_el0 \ Bit Event number Event mnemonic - 24 0X0038 = REMOTE_ACCESS_RD. - 23 0X0037 = LL_CACHE_MISS_RD. - 22 0X0036 = LL_CACHE_RD. - 21 0X0035 = ITLB_WALK. - 20 0X0034 = DTLB_WALK. - 19 0X0033 = LL_CACHE MISS. - 18 0X0032 = LL_CACHE. - 17 0X0031 = REMOTE_ACCESS. + 24 0x0038 = REMOTE_ACCESS_RD. + 23 0x0037 = LL_CACHE_MISS_RD. + 22 0x0036 = LL_CACHE_RD. + 21 0x0035 = ITLB_WALK. + 20 0x0034 = DTLB_WALK. + 19 0x0033 = LL_CACHE MISS. + 18 0x0032 = LL_CACHE. + 17 0x0031 = REMOTE_ACCESS. 16 RAZ 15 0x002f = L2D_TLB. 14 0x002e = L2I_TLB_REFILL. @@ -23474,14 +23474,14 @@ union bdk_ap_pmceid1_el0 \ Bit Event number Event mnemonic - 24 0X0038 = REMOTE_ACCESS_RD. - 23 0X0037 = LL_CACHE_MISS_RD. - 22 0X0036 = LL_CACHE_RD. - 21 0X0035 = ITLB_WALK. - 20 0X0034 = DTLB_WALK. - 19 0X0033 = LL_CACHE MISS. - 18 0X0032 = LL_CACHE. - 17 0X0031 = REMOTE_ACCESS. + 24 0x0038 = REMOTE_ACCESS_RD. + 23 0x0037 = LL_CACHE_MISS_RD. + 22 0x0036 = LL_CACHE_RD. + 21 0x0035 = ITLB_WALK. + 20 0x0034 = DTLB_WALK. + 19 0x0033 = LL_CACHE MISS. + 18 0x0032 = LL_CACHE. + 17 0x0031 = REMOTE_ACCESS. 16 RAZ 15 0x002f = L2D_TLB. 14 0x002e = L2I_TLB_REFILL. diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h index fc28b58067..949a56008f 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h @@ -9446,7 +9446,7 @@ union bdk_usbdrdx_uctl_ctl [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -9814,7 +9814,7 @@ union bdk_usbdrdx_uctl_ctl 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10106,7 +10106,7 @@ union bdk_usbdrdx_uctl_ctl [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10458,7 +10458,7 @@ union bdk_usbdrdx_uctl_ctl 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index f48069ff86..9ed24a9924 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -92,5 +92,23 @@ config CHROMEOS_DSM_CALIB to ACPI DSD table in device driver. These parameters will be applied by kernel driver through device property at boot. +config CHROMEOS_CSE_BOARD_RESET_OVERRIDE + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + On some boards that run old firmware version in cr50, Embedded Controller (EC) needs + to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW + so that cr50 resets the TPM state. This is required on boards where the cr50 firmware + does not understand the new cr50 strap config (applicable only to boards using strap + config 0xe). Enabling this config will help to override the default global reset. + +config CHROMEOS_DRAM_PART_NUMBER_IN_CBI + def_bool n + depends on EC_GOOGLE_CHROMEEC + help + Some boards declare the DRAM part number in the CBI instead of the SPD. This option + allows those boards to declare that their DRAM part number is stored in the CBI. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index a25700f8bb..fb11e11c8d 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -10,7 +10,11 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c +ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c bootblock-y += watchdog.c verstage-y += watchdog.c +romstage-y += watchdog.c ramstage-y += watchdog.c + +romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c new file mode 100644 index 0000000000..65e09aeedb --- /dev/null +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void cse_board_reset(void) +{ + int ret; + struct cr50_firmware_version version; + + /* Initialize TPM and get the cr50 firmware version. */ + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + cr50_get_firmware_version(&version); + + /* + * Cr50 firmware versions 0.[3|4].20 or newer support strap config 0xe where PLTRST from + * AP is connected to cr50's PLTRST# signal. So return immediately and trigger a + * global reset. + */ + if (version.epoch != 0 || version.major > 4 || + (version.major >= 3 && version.minor >= 20)) + return; + + printk(BIOS_INFO, "Initiating request to EC to trigger cold reset\n"); + /* + * Clean the data cache and set the full reset bit, so that when EC toggles + * SYS_RESET# pin, AP makes a trip to S5 and then to S0. + */ + dcache_clean_all(); + outb(FULL_RST, RST_CNT); + if (!google_chromeec_ap_reset()) + halt(); +} diff --git a/src/vendorcode/google/chromeos/dram_part_num_override.c b/src/vendorcode/google/chromeos/dram_part_num_override.c new file mode 100644 index 0000000000..d624e13c7e --- /dev/null +++ b/src/vendorcode/google/chromeos/dram_part_num_override.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const char *mainboard_get_dram_part_num(void) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + static enum { + PART_NUM_NOT_READ, + PART_NUM_AVAILABLE, + PART_NUM_NOT_IN_CBI, + } part_num_state = PART_NUM_NOT_READ; + + if (part_num_state == PART_NUM_NOT_READ) { + if (google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, + "ERROR: Couldn't obtain DRAM part number from CBI\n"); + part_num_state = PART_NUM_NOT_IN_CBI; + } else { + part_num_state = PART_NUM_AVAILABLE; + } + } + + if (part_num_state == PART_NUM_NOT_IN_CBI) + return NULL; + + return part_num_store; +} diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index b07d41d3bd..2f73d39020 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -113,5 +113,5 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) __weak const char *get_wifi_sar_cbfs_filename(void) { - return NULL; + return WIFI_SAR_CBFS_FILENAME; } diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h index 1e966da338..45f9c3e10b 100644 --- a/src/vendorcode/google/chromeos/symbols.h +++ b/src/vendorcode/google/chromeos/symbols.h @@ -5,6 +5,6 @@ #include -DECLARE_REGION(watchdog_tombstone) +DECLARE_OPTIONAL_REGION(watchdog_tombstone) #endif /* __CHROMEOS_SYMBOLS_H */ diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index 5b3f1844a7..d3273cb442 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -14,8 +14,6 @@ #define WATCHDOG_TOMBSTONE_MAGIC 0x9d2f41a7 -DECLARE_OPTIONAL_REGION(watchdog_tombstone); - static void elog_handle_watchdog_tombstone(void *unused) { bool flag = false; diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h index eac2385bcb..4c1691f40e 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h @@ -21,7 +21,7 @@ #define __PEI_APRIORI_FILE_NAME_H__ #define PEI_APRIORI_FILE_NAME_GUID \ - { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } + { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0xAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } /// diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h index 697a2d7be4..066ce1641b 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm20.h @@ -486,7 +486,7 @@ typedef UINT16 TPM_EO; // Table 18 - TPM_ST Constants typedef UINT16 TPM_ST; #define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4) -#define TPM_ST_NULL (TPM_ST)(0X8000) +#define TPM_ST_NULL (TPM_ST)(0x8000) #define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) #define TPM_ST_SESSIONS (TPM_ST)(0x8002) #define TPM_ST_ATTEST_NV (TPM_ST)(0x8014) diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h index 7c71090148..eb9ce86124 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -99,12 +99,35 @@ typedef struct { /// UINT64 Signature; /// - /// Revision of the Data structure. For FSP v2.0 value is 1. + /// Revision of the Data structure. + /// For FSP spec 2.0/2.1 value is 1. + /// For FSP spec 2.2 value is 2. /// UINT8 Revision; UINT8 Reserved[23]; } FSP_UPD_HEADER; +/// +/// FSPT_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages + /// occurring during FSP execution. + /// + FSP_DEBUG_HANDLER FspDebugHandler; + UINT8 Reserved1[20]; +} FSPT_ARCH_UPD; + /// /// FSPM_ARCH_UPD Configuration. /// @@ -146,6 +169,32 @@ typedef struct { UINT8 Reserved1[4]; } FSPM_ARCH_UPD; +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspEventHandler Optional event handler for the bootloader to be informed of events + /// occurring during FSP execution. + /// + FSP_EVENT_HANDLER FspEventHandler; + /// + /// A FSP binary may optionally implement multi-phase silicon initialization, + /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER + /// is non-zero. + /// To enable multi-phase silicon initialization, the bootloader must set + /// EnableMultiPhaseSiliconInit to a non-zero value. + /// + UINT8 EnableMultiPhaseSiliconInit; + UINT8 Reserved1[19]; +} FSPS_ARCH_UPD; + /// /// FSPT_UPD_COMMON Configuration. /// @@ -156,6 +205,21 @@ typedef struct { FSP_UPD_HEADER FspUpdHeader; } FSPT_UPD_COMMON; +/// +/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPT_ARCH_UPD Configuration. + /// + FSPT_ARCH_UPD FsptArchUpd; +} FSPT_UPD_COMMON_FSP22; + /// /// FSPM_UPD_COMMON Configuration. /// @@ -180,6 +244,21 @@ typedef struct { FSP_UPD_HEADER FspUpdHeader; } FSPS_UPD_COMMON; +/// +/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPS_ARCH_UPD Configuration. + /// + FSPS_ARCH_UPD FspsArchUpd; +} FSPS_UPD_COMMON_FSP22; + /// /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h index ab34b17ea8..f899ed91f5 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h @@ -15,7 +15,7 @@ #define __PEI_APRIORI_FILE_NAME_H__ #define PEI_APRIORI_FILE_NAME_GUID \ - { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } + { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0xAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h index 39332b15e8..a294dcbc7c 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h @@ -480,7 +480,7 @@ typedef UINT16 TPM_EO; // Table 18 - TPM_ST Constants typedef UINT16 TPM_ST; #define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4) -#define TPM_ST_NULL (TPM_ST)(0X8000) +#define TPM_ST_NULL (TPM_ST)(0x8000) #define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) #define TPM_ST_SESSIONS (TPM_ST)(0x8002) #define TPM_ST_ATTEST_NV (TPM_ST)(0x8014) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000000..a7e029c802 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ \ No newline at end of file diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h new file mode 100644 index 0000000000..b6ac3deaad --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h new file mode 100644 index 0000000000..a42f01474f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -0,0 +1,947 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved0[2]; + +/** Offset 0x004C - MemorySpdPtr00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - MemorySpdPtr01 +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0054 - MemorySpdPtr02 +**/ + UINT32 MemorySpdPtr02; + +/** Offset 0x0058 - MemorySpdPtr03 +**/ + UINT32 MemorySpdPtr03; + +/** Offset 0x005C - MemorySpdPtr04 +**/ + UINT32 MemorySpdPtr04; + +/** Offset 0x0060 - MemorySpdPtr05 +**/ + UINT32 MemorySpdPtr05; + +/** Offset 0x0064 - MemorySpdPtr06 +**/ + UINT32 MemorySpdPtr06; + +/** Offset 0x0068 - MemorySpdPtr07 +**/ + UINT32 MemorySpdPtr07; + +/** Offset 0x006C - MemorySpdPtr08 +**/ + UINT32 MemorySpdPtr08; + +/** Offset 0x0070 - MemorySpdPtr09 +**/ + UINT32 MemorySpdPtr09; + +/** Offset 0x0074 - MemorySpdPtr10 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0078 - MemorySpdPtr11 +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x007C - MemorySpdPtr12 +**/ + UINT32 MemorySpdPtr12; + +/** Offset 0x0080 - MemorySpdPtr13 +**/ + UINT32 MemorySpdPtr13; + +/** Offset 0x0084 - MemorySpdPtr14 +**/ + UINT32 MemorySpdPtr14; + +/** Offset 0x0088 - MemorySpdPtr15 +**/ + UINT32 MemorySpdPtr15; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - DqsMapCpu2DramCh0 +**/ + UINT8 DqsMapCpu2DramCh0[2]; + +/** Offset 0x009A - DqsMapCpu2DramCh1 +**/ + UINT8 DqsMapCpu2DramCh1[2]; + +/** Offset 0x009C - DqsMapCpu2DramCh2 +**/ + UINT8 DqsMapCpu2DramCh2[2]; + +/** Offset 0x009E - DqsMapCpu2DramCh3 +**/ + UINT8 DqsMapCpu2DramCh3[2]; + +/** Offset 0x00A0 - DqsMapCpu2DramCh4 +**/ + UINT8 DqsMapCpu2DramCh4[2]; + +/** Offset 0x00A2 - DqsMapCpu2DramCh5 +**/ + UINT8 DqsMapCpu2DramCh5[2]; + +/** Offset 0x00A4 - DqsMapCpu2DramCh6 +**/ + UINT8 DqsMapCpu2DramCh6[2]; + +/** Offset 0x00A6 - DqsMapCpu2DramCh7 +**/ + UINT8 DqsMapCpu2DramCh7[2]; + +/** Offset 0x00A8 - DqMapCpu2DramCh0 +**/ + UINT8 DqMapCpu2DramCh0[16]; + +/** Offset 0x00B8 - DqMapCpu2DramCh1 +**/ + UINT8 DqMapCpu2DramCh1[16]; + +/** Offset 0x00C8 - DqMapCpu2DramCh2 +**/ + UINT8 DqMapCpu2DramCh2[16]; + +/** Offset 0x00D8 - DqMapCpu2DramCh3 +**/ + UINT8 DqMapCpu2DramCh3[16]; + +/** Offset 0x00E8 - DqMapCpu2DramCh4 +**/ + UINT8 DqMapCpu2DramCh4[16]; + +/** Offset 0x00F8 - DqMapCpu2DramCh5 +**/ + UINT8 DqMapCpu2DramCh5[16]; + +/** Offset 0x0108 - DqMapCpu2DramCh6 +**/ + UINT8 DqMapCpu2DramCh6[16]; + +/** Offset 0x0118 - DqMapCpu2DramCh7 +**/ + UINT8 DqMapCpu2DramCh7[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Reserved +**/ + UINT8 Reserved1[7]; + +/** Offset 0x0130 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0134 - Reserved +**/ + UINT8 Reserved2[3]; + +/** Offset 0x0137 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0138 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0148 - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), + 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x0149 - Reserved +**/ + UINT8 Reserved3[14]; + +/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x0158 - Reserved +**/ + UINT8 Reserved4[40]; + +/** Offset 0x0180 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0181 - Reserved +**/ + UINT8 Reserved5[4]; + +/** Offset 0x0185 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x0186 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x0187 - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x0188 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x0189 - Reserved +**/ + UINT8 Reserved7[3]; + +/** Offset 0x018C - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x018D - Reserved +**/ + UINT8 Reserved8[2]; + +/** Offset 0x018F - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control + Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch0; + +/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control + Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch1; + +/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control + Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch2; + +/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control + Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch3; + +/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control + Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch0; + +/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control + Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch1; + +/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control + Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch2; + +/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control + Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch3; + +/** Offset 0x0198 - Reserved +**/ + UINT8 Reserved9[2]; + +/** Offset 0x019A - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x019B - Reserved +**/ + UINT8 Reserved10[22]; + +/** Offset 0x01B1 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01B2 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01B3 - Reserved +**/ + UINT8 Reserved11[107]; + +/** Offset 0x021E - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x0224 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0228 - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x0229 - RpClockReqMsgEnable +**/ + UINT8 RpClockReqMsgEnable[3]; + +/** Offset 0x022C - RpPcieThresholdBytes +**/ + UINT8 RpPcieThresholdBytes[4]; + +/** Offset 0x0230 - Reserved +**/ + UINT8 Reserved13[2]; + +/** Offset 0x0232 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0233 - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x0234 - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x0235 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0236 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0237 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0238 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0239 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x023A - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x023B - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x023C - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x023D - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x023E - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x023F - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0240 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0241 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0242 - Reserved +**/ + UINT8 Reserved14[142]; + +/** Offset 0x02D0 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x02D8 - Reserved +**/ + UINT8 Reserved15[150]; + +/** Offset 0x036E - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x036F - Reserved +**/ + UINT8 Reserved16[5]; + +/** Offset 0x0374 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0375 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x0376 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0377 - Reserved +**/ + UINT8 Reserved18[2]; + +/** Offset 0x0379 - Processor Early Power On Configuration FCLK setting + 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x037A - Reserved +**/ + UINT8 Reserved19; + +/** Offset 0x037B - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x037C - Reserved +**/ + UINT8 Reserved20[34]; + +/** Offset 0x039E - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x039F +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x03A0 - Reserved +**/ + UINT8 Reserved21[4]; + +/** Offset 0x03A4 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x03A8 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x03AC - Reserved +**/ + UINT8 Reserved22[12]; + +/** Offset 0x03B8 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x03BC - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x03C0 - Reserved +**/ + UINT8 Reserved23[614]; + +/** Offset 0x0626 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0627 - Reserved +**/ + UINT8 Reserved24[4]; + +/** Offset 0x062B - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x063D - Reserved +**/ + UINT8 Reserved25[14]; + +/** Offset 0x064B - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x065D - Reserved +**/ + UINT8 Reserved26[19]; + +/** Offset 0x0670 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x0674 - Reserved +**/ + UINT8 Reserved27[2]; + +/** Offset 0x0676 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x0677 - Reserved +**/ + UINT8 Reserved28[3]; + +/** Offset 0x067A - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x067C - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x0684 - DMIC ClkB Pin Muxing + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x068C - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x068D - Reserved +**/ + UINT8 Reserved29[3]; + +/** Offset 0x0690 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0698 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x069E - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x06A2 - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x06A3 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x06A4 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x06A5 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x06A6 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x06A7 - Reserved +**/ + UINT8 Reserved30[13]; + +/** Offset 0x06B4 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x06B5 - Reserved +**/ + UINT8 Reserved31[4]; + +/** Offset 0x06B9 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x06BA - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x06BB - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x06BC - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x06BD - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x06BE - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x06BF - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x06C0 - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x06C1 - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x06C2 - Reserved +**/ + UINT8 Reserved32[2]; + +/** Offset 0x06C4 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x06C5 - Reserved +**/ + UINT8 Reserved33[65]; + +/** Offset 0x0706 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0708 - Reserved +**/ + UINT8 Reserved34[64]; + +/** Offset 0x0748 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0749 - Reserved +**/ + UINT8 Reserved35[2]; + +/** Offset 0x074B - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x074C - Reserved +**/ + UINT8 Reserved36[2]; + +/** Offset 0x074E - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x074F - Reserved +**/ + UINT8 Reserved37[50]; + +/** Offset 0x0781 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0782 - Reserved +**/ + UINT8 Reserved38; + +/** Offset 0x0783 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0784 - Reserved +**/ + UINT8 Reserved39[129]; + +/** Offset 0x0805 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0806 - Reserved +**/ + UINT8 Reserved40[292]; + +/** Offset 0x092A - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x092B - Reserved +**/ + UINT8 Reserved41[517]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + + +/** Offset 0x0B30 +**/ + UINT8 UnusedUpdSpace32[6]; + +/** Offset 0x0B36 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h new file mode 100644 index 0000000000..7ec577a7b5 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -0,0 +1,872 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Reserved +**/ + UINT8 Reserved0[16]; + +/** Offset 0x0050 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0054 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0055 - Reserved +**/ + UINT8 Reserved1[12]; + +/** Offset 0x0061 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0062 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x006A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0072 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0082 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x008C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x008D - Reserved +**/ + UINT8 Reserved2[28]; + +/** Offset 0x00A9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00AA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00AB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00B2 - Reserved +**/ + UINT8 Reserved3[35]; + +/** Offset 0x00D5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00DC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x00E3 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x00EA - Reserved +**/ + UINT8 Reserved4[65]; + +/** Offset 0x012B - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0132 - Reserved +**/ + UINT8 Reserved5[2]; + +/** Offset 0x0134 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x0150 - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x016C - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0188 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x01A4 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x01A5 - Reserved +**/ + UINT8 Reserved6[7]; + +/** Offset 0x01AC - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x01B4 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x01D4 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x01F4 - Reserved +**/ + UINT8 Reserved7[192]; + +/** Offset 0x02B4 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02C4 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02D4 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x02E4 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x02F4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02FE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x0308 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0312 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x031C - Reserved +**/ + UINT8 Reserved8[80]; + +/** Offset 0x036C - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x036D - Reserved +**/ + UINT8 Reserved9[11]; + +/** Offset 0x0378 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x0394 - Reserved +**/ + UINT8 Reserved10[81]; + +/** Offset 0x03E5 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x03E6 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x03E7 - Reserved +**/ + UINT8 Reserved11; + +/** Offset 0x03E8 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x03EA - Reserved +**/ + UINT8 Reserved12[50]; + +/** Offset 0x041C - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x041D - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x041E - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x041F - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x0420 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0424 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in + GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0428 - Reserved +**/ + UINT8 Reserved14[166]; + +/** Offset 0x04CE - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: + 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, + 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x04CF - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x04D0 - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x04D1 - Reserved +**/ + UINT8 Reserved15[3]; + +/** Offset 0x04D4 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl + = AlderLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x04F4 - Reserved +**/ + UINT8 Reserved16[8]; + +/** Offset 0x04FC - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x04FD - Reserved +**/ + UINT8 Reserved17[8]; + +/** Offset 0x0505 - Enable VMD controller + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0506 - Reserved +**/ + UINT8 Reserved18[108]; + +/** Offset 0x0572 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x0574 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x0576 - Reserved +**/ + UINT8 Reserved19[2]; + +/** Offset 0x0578 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x057C - Reserved +**/ + UINT8 Reserved20[2]; + +/** Offset 0x057E - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x0580 - Reserved +**/ + UINT8 Reserved21[7]; + +/** Offset 0x0587 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x058B - Reserved +**/ + UINT8 Reserved22[201]; + +/** Offset 0x0654 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x0655 - Reserved +**/ + UINT8 Reserved23[11]; + +/** Offset 0x0660 - CpuMpPpi + Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x0664 - Reserved +**/ + UINT8 Reserved24[68]; + +/** Offset 0x06A8 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x06A9 - Reserved +**/ + UINT8 Reserved25[33]; + +/** Offset 0x06CA - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x06CB - Reserved +**/ + UINT8 Reserved26[2]; + +/** Offset 0x06CD - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x06CE - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x06D0 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x06D3 - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[8]; + +/** Offset 0x06DB - Reserved +**/ + UINT8 Reserved27[2]; + +/** Offset 0x06DD - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x06DE - Reserved +**/ + UINT8 Reserved28[2]; + +/** Offset 0x06E0 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x06E1 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x06FD - Reserved +**/ + UINT8 Reserved29[56]; + +/** Offset 0x0735 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x0751 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x076D - Reserved +**/ + UINT8 Reserved30[196]; + +/** Offset 0x0831 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x084D - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 +**/ + UINT8 ThcPort0Assignment; + +/** Offset 0x084E - Reserved +**/ + UINT8 Reserved31[6]; + +/** Offset 0x0854 - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x0855 - Reserved +**/ + UINT8 Reserved32[91]; + +/** Offset 0x08B0 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x08CC - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x08E8 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x0904 - Reserved +**/ + UINT8 Reserved33[102]; + +/** Offset 0x096A - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x096B - Reserved +**/ + UINT8 Reserved34[50]; + +/** Offset 0x099D - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x09A5 - Reserved +**/ + UINT8 Reserved35; + +/** Offset 0x09A6 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x09B6 - Reserved +**/ + UINT8 Reserved36[62]; + +/** Offset 0x09F4 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x0A04 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0A0E - Reserved +**/ + UINT8 Reserved37[14]; + +/** Offset 0x0A1C - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0A1D - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0A1E - Reserved +**/ + UINT8 Reserved38; + +/** Offset 0x0A1F - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x0A20 - Reserved +**/ + UINT8 Reserved39[113]; + +/** Offset 0x0A91 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0A92 - Reserved +**/ + UINT8 Reserved40[310]; + +/** Offset 0x0BC8 - RpPtmBytes +**/ + UINT8 RpPtmBytes[4]; + +/** Offset 0x0BCC - Reserved +**/ + UINT8 Reserved41[99]; + +/** Offset 0x0C2F - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0C30 - Reserved +**/ + UINT8 Reserved42; + +/** Offset 0x0C31 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x0C32 - Reserved +**/ + UINT8 Reserved43[24]; + +/** Offset 0x0C4A - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x0C4B - Reserved +**/ + UINT8 Reserved44[8]; + +/** Offset 0x0C53 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + 10, For all other SKUs the recommended default are 0 +**/ + UINT8 TccActivationOffset; + +/** Offset 0x0C54 - Reserved +**/ + UINT8 Reserved45[34]; + +/** Offset 0x0C76 - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0C77 - Reserved +**/ + UINT8 Reserved46[197]; + +/** Offset 0x0D3C - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0D3D - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0D3E - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0D3F - Reserved +**/ + UINT8 Reserved47; + +/** Offset 0x0D40 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x0D70 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x0DA0 - Reserved +**/ + UINT8 Reserved48[289]; + +/** Offset 0x0EC1 - LpmStateEnableMask +**/ + UINT8 LpmStateEnableMask; + +/** Offset 0x0EC2 - Reserved +**/ + UINT8 Reserved49[766]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x11C0 +**/ + UINT8 UnusedUpdSpace49[6]; + +/** Offset 0x11C6 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h new file mode 100644 index 0000000000..816ce06f8c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -0,0 +1,293 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_TRACE_CACHE_TYPE 3 + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_WIO2 +#define MRC_DDR_TYPE_WIO2 4 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 5 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 PramSize; + UINT64 PramBase; + UINT64 DismLimit; + UINT64 DismBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; +// +// CPU:RestrictedBegin +// + UINT32 SharedMailboxBase; +// +// CPU:RestrictedEnd +// + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index 770390d606..05210d6801 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -683,7 +683,7 @@ typedef struct { /** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing + Disable SSC(0x1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC **/ UINT8 PegDisableSpreadSpectrumClocking; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 144db07078..37ff1bd620 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -167,507 +167,565 @@ typedef struct { **/ UINT8 SnoopThrottleConfig; -/** Offset 0x006A - Legacy VGA Soc +/** Offset 0x006A - Snoop Throttle Config + Set the Snoop All Core Config + 0:DIS, 1:EN, 2:Auto +**/ + UINT8 SnoopAllCores; + +/** Offset 0x006B - Legacy VGA Soc Socket that claims the legacy VGA range **/ UINT8 LegacyVgaSoc; -/** Offset 0x006B - Legacy VGA Stack +/** Offset 0x006C - Legacy VGA Stack Stack that claims the legacy VGA range **/ UINT8 LegacyVgaStack; -/** Offset 0x006C - Pcie P2P Performance Mode +/** Offset 0x006D - Pcie P2P Performance Mode Determine if to enable PCIe P2P Performance Mode $EN_DIS **/ UINT8 P2pRelaxedOrdering; -/** Offset 0x006D - Debug Print Level +/** Offset 0x006E - Debug Print Level Set Debug Print Level 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All **/ UINT8 DebugPrintLevel; -/** Offset 0x006E - SNC +/** Offset 0x006F - SNC Enable or Disable SNC $EN_DIS **/ UINT8 SncEn; -/** Offset 0x006F - UMA Clustering +/** Offset 0x0070 - UMA Clustering Set UMA Clusters 0:Disable, 2:Two Clusters, 4:Four Clusters **/ UINT8 UmaClustering; -/** Offset 0x0070 - IODC Mode +/** Offset 0x0071 - IODC Mode IODC Setup Option 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF **/ UINT8 IoDcMode; -/** Offset 0x0071 - Degrade Precedence +/** Offset 0x0072 - Degrade Precedence Setup Degrade Precedence 0:Topology, 1:Feature **/ UINT8 DegradePrecedence; -/** Offset 0x0072 - Degrade 4 Socket Preference +/** Offset 0x0073 - Degrade 4 Socket Preference Setup Degrade 4 Socket Preference 0:Fully Connect, 1:Dual Link Ring **/ UINT8 Degrade4SPreference; -/** Offset 0x0073 - Directory Mode +/** Offset 0x0074 - Directory Mode Enable or Disable Directory Mode $EN_DIS **/ UINT8 DirectoryModeEn; -/** Offset 0x0074 - XPT Prefetch Enable +/** Offset 0x0075 - XPT Prefetch Enable Enable or Disable XPT Prefetch **/ UINT8 XptPrefetchEn; -/** Offset 0x0075 - KTI Prefetch Enable +/** Offset 0x0076 - KTI Prefetch Enable Enable or Disable KTI Prefetch $EN_DIS **/ UINT8 KtiPrefetchEn; -/** Offset 0x0076 - XPT Remote Prefetch Enable +/** Offset 0x0077 - XPT Remote Prefetch Enable Enable or Disable XPT Remote Prefetch Enable $EN_DIS **/ UINT8 XptRemotePrefetchEn; -/** Offset 0x0077 - KTI FPGA +/** Offset 0x0078 - KTI FPGA Enable or Disable KTI FPGA $EN_DIS **/ UINT8 KtiFpgaEnable[8]; -/** Offset 0x007F - DDRT QoS Mode +/** Offset 0x0080 - DDRT QoS Mode Setup DDRT QoS **/ UINT8 DdrtQosMode; -/** Offset 0x0080 - KTI Link Speed Mode +/** Offset 0x0081 - KTI Link Speed Mode Choose KTI Link Speed Mode **/ UINT8 KtiLinkSpeedMode; -/** Offset 0x0081 - KTI Link Speed +/** Offset 0x0082 - KTI Link Speed Setup KTI Link Speed **/ UINT8 KtiLinkSpeed; -/** Offset 0x0082 - KTI Link L0p +/** Offset 0x0083 - KTI Link L0p Enable or Disable KTI Link L0p **/ UINT8 KtiLinkL0pEn; -/** Offset 0x0083 - KTI Link L1 +/** Offset 0x0084 - KTI Link L1 Enable or Disable KTI Link L1 **/ UINT8 KtiLinkL1En; -/** Offset 0x0084 - KTI Failover +/** Offset 0x0085 - KTI Failover Enable or Disable KTI Failover **/ UINT8 KtiFailoverEn; -/** Offset 0x0085 - KTI LB Enable +/** Offset 0x0086 - KTI LB Enable Enable or Disable KTI LB $EN_DIS **/ UINT8 KtiLbEn; -/** Offset 0x0086 - KTI CRC Mode +/** Offset 0x0087 - KTI CRC Mode Select KTI CRC Mode 0:16bit, 1:32bit, 2:Auto **/ UINT8 KtiCrcMode; -/** Offset 0x0087 - KTI CPU Socket Hotplug +/** Offset 0x0088 - KTI CPU Socket Hotplug Enable or Disable KTI CPU Socket Hotplug $EN_DIS **/ UINT8 KtiCpuSktHotPlugEn; -/** Offset 0x0088 - KTI CPU Socket HotPlug Topology +/** Offset 0x0089 - KTI CPU Socket HotPlug Topology Select KTI CPU Socket HotPlug Topology 0:4Socket, 1:8Socket **/ UINT8 KtiCpuSktHotPlugTopology; -/** Offset 0x0089 - KTI SKU Mismatch Check +/** Offset 0x008A - KTI SKU Mismatch Check Enable or Disable KTI SKU Mismatch Check $EN_DIS **/ UINT8 KtiSkuMismatchCheck; -/** Offset 0x008A - IRQ Threshold +/** Offset 0x008B - IRQ Threshold Select IRQ Threshold 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 IrqThreshold; -/** Offset 0x008B - IRQ Threshold +/** Offset 0x008C - IRQ Threshold Enable or Disable 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremNorm; -/** Offset 0x008C - TOR threshold - Loctorem threshold empty +/** Offset 0x008D - TOR threshold - Loctorem threshold empty Select TOR threshold - Loctorem threshold empty 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremEmpty; -/** Offset 0x008D - TSC Sync in Sockets +/** Offset 0x008E - MBA BW Calibration + MBA BW Calibration setting + 0:Linear, 1:Biased, 2:Legacy, 3:Auto +**/ + UINT8 MbeBwCal; + +/** Offset 0x008F - TSC Sync in Sockets Enable or Disable TSC Sync in Sockets **/ UINT8 TscSyncEn; -/** Offset 0x008E - HA A to S directory optimization +/** Offset 0x0090 - HA A to S directory optimization Enable or Disable HA A to S directory optimization **/ UINT8 StaleAtoSOptEn; -/** Offset 0x008F - LLC Deadline Allocation +/** Offset 0x0091 - LLC Deadline Allocation Enable or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; -/** Offset 0x0090 - Split Lock +/** Offset 0x0092 - Split Lock Enable or Disable Split Lock **/ UINT8 SplitLock; -/** Offset 0x0091 - MMCFG Base Address +/** Offset 0x0093 - MMCFG Base Address Setup MMCFG Base Address 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto **/ UINT8 mmCfgBase; -/** Offset 0x0092 - MMCFG Size +/** Offset 0x0094 - MMCFG Size Select MMCFG Size 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto **/ UINT8 mmCfgSize; -/** Offset 0x0093 +/** Offset 0x0095 **/ - UINT8 UnusedUpdSpace0; + UINT8 UnusedUpdSpace0[3]; -/** Offset 0x0094 - MMIO High Base Address +/** Offset 0x0098 - MMIO High Base Address MMIO High Base Address, a hex number for Bit[51:32] **/ UINT32 mmiohBase; -/** Offset 0x0098 - High Gap +/** Offset 0x009C - CPU Physical Address Limit + CPU Physical Address Limit + 0:Disable, 1:Enable +**/ + UINT8 CpuPaLimit; + +/** Offset 0x009D - High Gap Enable or Disable High Gap $EN_DIS **/ UINT8 highGap; -/** Offset 0x0099 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x009A - MMIO High Size +/** Offset 0x009E - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU. Range 1-1024 **/ UINT16 mmiohSize; -/** Offset 0x009C - } TYPE:{Combo +/** Offset 0x00A0 - } TYPE:{Combo Enable or Disable $EN_DIS **/ UINT8 isocEn; -/** Offset 0x009D - DCA +/** Offset 0x00A1 - DCA Enable or Disable DCA $EN_DIS **/ UINT8 dcaEn; -/** Offset 0x009E +/** Offset 0x00A2 **/ - UINT8 UnusedUpdSpace2[2]; - -/** Offset 0x00A0 - } TYPE:{Combo - Enable or Disable - $EN_DIS -**/ - UINT32 BoardTypeBitmask; + UINT8 UnusedUpdSpace1[2]; /** Offset 0x00A4 - } TYPE:{Combo Enable or Disable $EN_DIS **/ - UINT32 AllLanesPtr; + UINT32 BoardTypeBitmask; /** Offset 0x00A8 - } TYPE:{Combo Enable or Disable $EN_DIS **/ - UINT32 PerLanePtr; + UINT32 AllLanesPtr; /** Offset 0x00AC - } TYPE:{Combo Enable or Disable $EN_DIS **/ - UINT32 AllLanesSizeOfTable; + UINT32 PerLanePtr; /** Offset 0x00B0 - } TYPE:{Combo Enable or Disable $EN_DIS **/ - UINT32 PerLaneSizeOfTable; + UINT32 AllLanesSizeOfTable; /** Offset 0x00B4 - } TYPE:{Combo Enable or Disable $EN_DIS **/ - UINT32 WaitTimeForPSBP; + UINT32 PerLaneSizeOfTable; /** Offset 0x00B8 - } TYPE:{Combo Enable or Disable $EN_DIS +**/ + UINT32 WaitTimeForPSBP; + +/** Offset 0x00BC - } TYPE:{Combo + Enable or Disable + $EN_DIS **/ UINT8 IsKtiNvramDataReady; -/** Offset 0x00B9 - } TYPE:{Combo +/** Offset 0x00BD - } TYPE:{Combo Enable or Disable $EN_DIS **/ UINT8 BoardId; -/** Offset 0x00BA - } TYPE:{Combo +/** Offset 0x00BE - } TYPE:{Combo Enable or Disable $EN_DIS **/ UINT8 WaSerializationEn; -/** Offset 0x00BB - } TYPE:{Combo +/** Offset 0x00BF - } TYPE:{Combo Enable or Disable $EN_DIS **/ UINT8 KtiInEnableMktme; -/** Offset 0x00BC - Usage type for Processor VmxEnable Function +/** Offset 0x00C0 - Usage type for Processor VmxEnable Function Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00 $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x00BD - IIO ConfigIOU0 +/** Offset 0x00C1 - Usage type for Processor X2apic Function + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 X2apic; + +/** Offset 0x00C2 - Usage type for DDR frequency limit + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 DdrFreqLimit; + +/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 serialDebugMsgLvl; + +/** Offset 0x00C4 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8]; -/** Offset 0x00C5 - IIO ConfigIOU1 +/** Offset 0x00CC - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8]; -/** Offset 0x00CD - IIO ConfigIOU2 +/** Offset 0x00D4 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8]; -/** Offset 0x00D5 - IIO ConfigIOU3 +/** Offset 0x00DC - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8]; -/** Offset 0x00DD - IIO ConfigIOU4 +/** Offset 0x00E4 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00E5 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr +/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00EC - Usage type for IIO PCIE Config Table Number +/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number IIO PCIE Config Table Number **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F0 - Usage type for IIO PCIE Root Port Enable or Disable +/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F1 - Usage type for IIO DeEmphasis +/** Offset 0x00F5 - Usage type for IIO DeEmphasis IIO DeEmphasis **/ UINT8 DeEmphasis; -/** Offset 0x00F2 - Usage type for IIO PCIE Root Port link speed +/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed IIO root port link speed **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00F3 - Usage type for IIO PCIE Root Port Max Payload +/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload IIO Root Port Max Payload **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00F4 - Usage type for IIO DfxDnTxPreset +/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset IIO DfxDnTxPreset **/ UINT8 DfxDnTxPreset; -/** Offset 0x00F5 - Usage type for IIO DfxRxPreset +/** Offset 0x00F9 - Usage type for IIO DfxRxPreset IIO DfxRxPreset **/ UINT8 DfxRxPreset; -/** Offset 0x00F6 - Usage type for IIO DfxUpTxPreset +/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset IIO DfxUpTxPreset **/ UINT8 DfxUpTxPreset; -/** Offset 0x00F7 - Usage type for IIO PcieCommonClock +/** Offset 0x00FB - Usage type for IIO PcieCommonClock IIO PcieCommonClock **/ UINT8 PcieCommonClock; -/** Offset 0x00F8 - Usage type for IIO NtbPpd +/** Offset 0x00FC - Usage type for IIO NtbPpd IIO NtbPpd **/ UINT8 NtbPpd; -/** Offset 0x00F9 - Usage type for IIO NtbBarSizeOverride +/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride IIO NtbBarSizeOverride **/ UINT8 NtbBarSizeOverride; -/** Offset 0x00FA - Usage type for IIO NtbSplitBar +/** Offset 0x00FE - Usage type for IIO NtbSplitBar IIO NtbSplitBar **/ UINT8 NtbSplitBar; -/** Offset 0x00FB - Usage type for IIO NtbBarSizeImBar1 +/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1 IIO NtbBarSizeImBar1 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x00FC - Usage type for IIO NtbBarSizeImBar2 +/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2 IIO PNtbBarSizeImBar2 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x00FD - Usage type for IIO NtbBarSizeImBar2_0 +/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0 IIO PNtbBarSizeImBar2_0 **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x00FE - Usage type for IIO NtbBarSizeImBar2_1 +/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1 IIO NtbBarSizeImBar2_1 **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x00FF - Usage type for IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1 IIO NtbBarSizeEmBarSZ1 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0100 - Usage type for IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2 IIO NtbBarSizeEmBarSZ2 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0 IIO NtbBarSizeEmBarSZ2_0 **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x0102 - Usage type for IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1 IIO NtbBarSizeEmBarSZ2_1 **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x0103 - Usage type for IIO NtbXlinkCtlOverride +/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride IIO NtbXlinkCtlOverride **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0104 - Usage type for IIO VT-D Function +/** Offset 0x0108 - Usage type for IIO VT-D Function IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 **/ UINT8 VtdSupport; -/** Offset 0x0105 - PchSirqMode +/** Offset 0x0109 - Usage type for IIO Pcie Port Hide + Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible +**/ + UINT8 PEXPHIDE; + +/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide + Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +**/ + UINT8 HidePEXPMenu; + +/** Offset 0x010B - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; -/** Offset 0x0106 - PchAdrEn +/** Offset 0x010C - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x0107 - } TYPE:{Combo +/** Offset 0x010D - ThermalDeviceEnable + Enable or Disable ThermalDeviceEnable with PCI or ACPI mode +**/ + UINT8 ThermalDeviceEnable; + +/** Offset 0x010E - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x0108 - PCH PCIE PLL Ssc +/** Offset 0x010F - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0109 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x011D - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0131 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0145 - SerialIoUartDebugEnable +/** Offset 0x014C - PchDciEn + Enable or Disable Pch DciEn +**/ + UINT8 PchDciEn; + +/** Offset 0x014D - MeUmaEnable + Enable or disable ME UMA feature +**/ + UINT8 MeUmaEnable; + +/** Offset 0x014E - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x0146 - ISA Serial Base selection +/** Offset 0x014F +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x0150 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0148 +/** Offset 0x0152 +**/ + UINT8 UnusedUpdSpace3[2]; + +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -688,11 +746,11 @@ typedef struct { **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0158 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace4[6]; + UINT8 UnusedUpdSpace4[2]; -/** Offset 0x015E +/** Offset 0x0166 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 8dcac42bd3..9900a121f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -45,6 +45,7 @@ are permitted provided that the following conditions are met: #define MAX_IMC 2 #define MAX_CH 6 #define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) +#define MAX_CHA_MAP 4 // Maximum KTI PORTS to be used in structure definition #if (MAX_SOCKET == 1) @@ -90,45 +91,41 @@ typedef struct { IIO PCIe Ports **/ typedef enum { + // IOU0, CSTACK PORT_0 = 0, - // IOU0 + // IOU1, PSTACK0 PORT_1A, PORT_1B, PORT_1C, PORT_1D, - // IOU1 + // IOU2, PSTACK1 PORT_2A, PORT_2B, PORT_2C, PORT_2D, - // IOU2 - PORT_4A, - PORT_4B, - PORT_4C, - PORT_4D, - // MCP0 - PORT_5A, - PORT_5B, - PORT_5C, - PORT_5D, - // MCP1 - PORT_6A, - PORT_6B, - PORT_6C, - PORT_6D, + // IOU3, PSTACK2 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, MAX_PORTS } PCIE_PORTS; /** - IIO Stacks - **/ + * IIO Stacks + * + * Ports Stack Stack(HOB) IioConfigIou + * ================================================= + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ typedef enum { CSTACK = 0, PSTACK0, PSTACK1, - PSTACK2, - PSTACK3, - PSTACK4, + PSTACK2 = 4, MAX_STACKS } IIO_STACKS; @@ -155,11 +152,10 @@ typedef struct { uint8_t PcieSegment; UINT64_STRUCT SegMmcfgBase; uint16_t stackPresentBitmap; - uint16_t CxlPresentBitmap; uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha; - uint32_t ChaList; + uint32_t ChaList[MAX_CHA_MAP]; uint32_t SocId; QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info } QPI_CPU_DATA; @@ -200,23 +196,20 @@ typedef struct _STACK_RES { uint8_t Personality; // see STACK_TYPE for details uint8_t BusBase; uint8_t BusLimit; - uint16_t IoBase; // Base of IO configured for this stack - uint16_t IoLimit; // Limit of IO configured for this stack + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; uint32_t IoApicBase; // Base of IO configured for this stack uint32_t IoApicLimit; // Limit of IO configured for this stack uint32_t Mmio32Base; uint32_t Mmio32Limit; uint64_t Mmio64Base; uint64_t Mmio64Limit; - uint8_t PciResourceBusBase; // Base of Bus resource available for PCI devices - uint8_t PciResourceBusLimit; // Limit of Bus resource available for PCI devices - uint16_t PciResourceIoBase; // Base of IO resource available for PCI devices - uint16_t PciResourceIoLimit; // Limit of IO resource available for PCI devices uint32_t PciResourceMem32Base; uint32_t PciResourceMem32Limit; uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index df7787a330..dc870f1ad1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -40,6 +40,8 @@ are permitted provided that the following conditions are met: #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) +#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform + #define MAX_SAD_RULES 24 #define MAX_DRAM_CLUSTERS 1 #define MAX_IMC_PER_SOCKET 2 @@ -56,6 +58,9 @@ are permitted provided that the following conditions are met: #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 +#define NGN_MAX_SERIALNUMBER_STRLEN 4 +#define NGN_MAX_PARTNUMBER_STRLEN 20 +#define NGN_FW_VER_LEN 4 // // System Memory Map HOB information // @@ -83,9 +88,50 @@ typedef struct SystemMemoryMapElement { UINT32 ElementSize; } SYSTEM_MEMORY_MAP_ELEMENT; +typedef struct DimmDevice { + UINT8 Present; + UINT8 reserved1[1]; + UINT8 DcpmmPresent; + UINT8 reserved2[1]; + UINT8 NumRanks; + UINT8 reserved3[1]; + UINT8 actKeyByte2; + UINT8 reserved4[4]; + UINT16 nonVolCap; + UINT16 DimmSize; + UINT8 reserved5[4]; + UINT16 SPDMMfgId; // Module Mfg Id from SPD + UINT16 VendorID; + UINT16 DeviceID; + UINT8 reserved6[22]; + UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number + UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number + UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 + UINT8 reserved7[23]; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT8 reserved8[4]; + UINT8 DimmSku; // Dimm SKU info + UINT8 reserved9[3]; + INT32 commonTck; + UINT8 EnergyType; + UINT8 reserved10[1]; + UINT16 SPDRegVen; // Register Vendor ID in SPD +} MEMMAP_DIMM_DEVICE_INFO_STRUCT; + +struct ChannelDevice { + UINT8 reserved1[15]; + MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_IMC]; +}; + +typedef struct socket { + UINT8 reserved1[1114]; + struct ChannelDevice ChannelInfo[MAX_CH]; +} MEMMAP_SOCKET; + /* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { - UINT8 reserved1[58]; + UINT8 reserved1[61]; UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. @@ -94,16 +140,24 @@ typedef struct SystemMemoryMapHob { UINT32 memSize; // Total physical memory size UINT16 memFreq; // Mem Frequency - UINT8 reserved2[61]; + UINT8 reserved2[22]; + UINT8 DdrVoltage; + UINT8 reserved3[38]; + UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements - SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; + SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; + UINT8 reserved4[2213]; + MEMMAP_SOCKET Socket[MAX_SOCKET]; + UINT8 reserved5[1603]; - UINT8 reserved3[24514]; + UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS + + UINT8 reserved6[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved4[2]; + UINT8 reserved7[5]; } SYSTEM_MEMORY_MAP_HOB; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h new file mode 100644 index 0000000000..9241692b3a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -0,0 +1,83 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _PREV_BOOT_ERR_SRC_GUID_H_ +#define _PREV_BOOT_ERR_SRC_GUID_H_ + +#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { \ + 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, \ + 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 \ + } + +#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 + +typedef struct { +UINT16 Length; // Actual size of the error sources used in the HOB +UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO +}PREV_BOOT_ERR_SRC_HOB; + +typedef struct{ +UINT8 Type; // McBankType = 1; +UINT8 Segment; +UINT8 Socket; +UINT16 ApicId; // ApicId is Needed only if it a core McBank. +UINT16 McBankNum; +UINT64 McBankStatus; +UINT64 McbankAddr; +UINT64 McBankMisc; +} MCBANK_ERR_INFO; + +typedef struct { +UINT8 Type; // PciExType =2 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT32 AerUncErrSts; +UINT8 AerHdrLogData[16]; +} PCI_EX_ERR_INFO; + +typedef struct { +UINT8 Type; // Other Csr error type =3 ; +UINT8 Segment; +UINT8 Bus; +UINT8 Device; +UINT8 Function; +UINT16 offset; +UINT32 Value; +} CSR_ERR_INFO; + +typedef enum { + McBankType = 1, + PciExType, + CsrOtherType +} ERROR_ACCESS_TYPE; + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 97a40b6558..0d3902db48 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1715,33 +1715,33 @@ typedef struct { **/ UINT8 SkipSpiPCP; -/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration - Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset - (23:16) + OR Value (15:8) + AND Value (7:0) -**/ - UINT32 PmicPmcIpcCtrl; - -/** Offset 0x03AF - ModPhyIfValue +/** Offset 0x03AB - ModPhyIfValue Upd To modify the Integrated Filter (IF) value as 0x12(Default) for WIN and 0x16 for Chrome **/ UINT8 ModPhyIfValue; -/** Offset 0x03B0 - ModPhyVoltageBump - ModPhyVoltageBump. 1: enable, 0: disable - $EN_DIS +/** Offset 0x03AC - PMIC PCH_PWROK delay configuration - IPC Configuration + Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) **/ - UINT8 ModPhyVoltageBump; + UINT32 PmicPmcIpcCtrl; -/** Offset 0x03B1 - Vdd2 Voltage configuration +/** Offset 0x03B0 - Vdd2 Voltage configuration Upd for changing Vdd2 Voltage configuration : I2C_Slave_Address (31:23) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) **/ UINT32 PmicVdd2Voltage; +/** Offset 0x03B4 - ModPhyVoltageBump + ModPhyVoltageBump. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 ModPhyVoltageBump; + /** Offset 0x03B5 **/ - UINT8 ReservedFspsUpd[1]; + UINT8 ReservedFspsUpd[3]; } FSP_S_CONFIG; /** Fsp S SGX Configuration @@ -1810,9 +1810,9 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x03B6 +/** Offset 0x03B8 **/ - UINT8 UnusedUpdSpace7[10]; + UINT8 UnusedUpdSpace7[8]; /** Offset 0x03C0 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index 3af6fade3d..8155e85ea7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -2268,7 +2268,7 @@ typedef struct { UINT8 EpgEnable; /** Offset 0x0567 - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP + Type of method used to prevent Row Hammer. Default is 2x Refresh 0:Hardware RHP, 1:2x Refresh **/ UINT8 RhSolution; @@ -2526,189 +2526,189 @@ typedef struct { /** Offset 0x05B6 - Reserved **/ - UINT8 Reserved32[98]; + UINT8 Reserved32[100]; -/** Offset 0x0618 - TotalFlashSize +/** Offset 0x061A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable **/ UINT16 TotalFlashSize; -/** Offset 0x061A - BiosSize +/** Offset 0x061C - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR. **/ UINT16 BiosSize; -/** Offset 0x061C - TxtAcheckRequest +/** Offset 0x061E - TxtAcheckRequest Enable/Disable. When Enabled, after memory training is done MRC will request an ACHECK (Memory Alias Check) be done by TXT. $EN_DIS **/ UINT8 TxtAcheckRequest; -/** Offset 0x061D - Reserved +/** Offset 0x061F - Reserved **/ UINT8 Reserved33[11]; -/** Offset 0x0628 - Smbus dynamic power gating +/** Offset 0x062A - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x0629 - Disable and Lock Watch Dog Register +/** Offset 0x062B - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x062A - SMBUS SPD Write Disable +/** Offset 0x062C - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x062B - VC Type +/** Offset 0x062D - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. 0: VC0, 1: VC1 **/ UINT8 PchHdaVcType; -/** Offset 0x062C - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x062E - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x062D - Enable HD Audio Link +/** Offset 0x062F - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x062E - Reserved +/** Offset 0x0630 - Reserved **/ UINT8 Reserved34[3]; -/** Offset 0x0631 - Enable HD Audio DMIC_N Link +/** Offset 0x0633 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x0633 - Reserved +/** Offset 0x0635 - Reserved **/ - UINT8 Reserved35[17]; + UINT8 Reserved35[19]; -/** Offset 0x0644 - Enable HD Audio DSP +/** Offset 0x0648 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x0645 - Reserved +/** Offset 0x0649 - Reserved **/ UINT8 Reserved36[11]; -/** Offset 0x0650 - Enable HD Audio SSP0 Link +/** Offset 0x0654 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x0656 - Enable HD Audio SoundWire#N Link +/** Offset 0x065A - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x065A - iDisp-Link Frequency +/** Offset 0x065E - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x065B - iDisp-Link T-mode +/** Offset 0x065F - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x065C - iDisplay Audio Codec disconnection +/** Offset 0x0660 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x065D - Force ME DID Init Status +/** Offset 0x0661 - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x065E - CPU Replaced Polling Disable +/** Offset 0x0662 - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x065F - Check HECI message before send +/** Offset 0x0663 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x0660 - Skip MBP HOB +/** Offset 0x0664 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x0661 - HECI2 Interface Communication +/** Offset 0x0665 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x0662 - Enable KT device +/** Offset 0x0666 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x0663 - Skip CPU replacement check +/** Offset 0x0667 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0664 - Serial Io Uart Debug Mode +/** Offset 0x0668 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0665 - Reserved +/** Offset 0x0669 - Reserved **/ UINT8 Reserved37[19]; -/** Offset 0x0678 - Avx2 Voltage Guardband Scaling Factor +/** Offset 0x067C - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx2VoltageScaleFactor; -/** Offset 0x0679 - Avx512 Voltage Guardband Scaling Factor +/** Offset 0x067D - Avx512 Voltage Guardband Scaling Factor AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx512VoltageScaleFactor; -/** Offset 0x067A - Reserved +/** Offset 0x067E - Reserved **/ - UINT8 Reserved38[22]; + UINT8 Reserved38[18]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2729,7 +2729,7 @@ typedef struct { /** Offset 0x0690 **/ - UINT8 UnusedUpdSpace21[6]; + UINT8 UnusedUpdSpace22[6]; /** Offset 0x0696 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index 1328d391d1..34c29dc717 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -85,369 +85,369 @@ typedef struct { **/ typedef struct { -/** Offset 0x0020 - Logo Pointer +/** Offset 0x0040 - Logo Pointer Points to PEI Display Logo Image **/ UINT32 LogoPtr; -/** Offset 0x0024 - Logo Size +/** Offset 0x0044 - Logo Size Size of PEI Display Logo Image **/ UINT32 LogoSize; -/** Offset 0x0028 - Blt Buffer Address +/** Offset 0x0048 - Blt Buffer Address Address of Blt buffer **/ UINT32 BltBufferAddress; -/** Offset 0x002C - Blt Buffer Size +/** Offset 0x004C - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) **/ UINT32 BltBufferSize; -/** Offset 0x0030 - Graphics Configuration Ptr +/** Offset 0x0050 - Graphics Configuration Ptr Points to VBT **/ UINT32 GraphicsConfigPtr; -/** Offset 0x0034 - Enable Device 4 +/** Offset 0x0054 - Enable Device 4 Enable/disable Device 4 $EN_DIS **/ UINT8 Device4Enable; -/** Offset 0x0035 - Enable eMMC Controller +/** Offset 0x0055 - Enable eMMC Controller Enable/disable eMMC Controller. $EN_DIS **/ UINT8 ScsEmmcEnabled; -/** Offset 0x0036 - Enable eMMC HS400 Mode +/** Offset 0x0056 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. $EN_DIS **/ UINT8 ScsEmmcHs400Enabled; -/** Offset 0x0037 - Use DLL values from policy +/** Offset 0x0057 - Use DLL values from policy Set if FSP should use HS400 DLL values from policy $EN_DIS **/ UINT8 EmmcUseCustomDlls; -/** Offset 0x0038 - Emmc Tx CMD Delay control register value +/** Offset 0x0058 - Emmc Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help **/ UINT32 EmmcTxCmdDelayRegValue; -/** Offset 0x003C - Emmc Tx DATA Delay control 1 register value +/** Offset 0x005C - Emmc Tx DATA Delay control 1 register value Please see Tx DATA Delay control 1 register definition for help **/ UINT32 EmmcTxDataDelay1RegValue; -/** Offset 0x0040 - Emmc Tx DATA Delay control 2 register value +/** Offset 0x0060 - Emmc Tx DATA Delay control 2 register value Please see Tx DATA Delay control 2 register definition for help **/ UINT32 EmmcTxDataDelay2RegValue; -/** Offset 0x0044 - Emmc Rx CMD + DATA Delay control 1 register value +/** Offset 0x0064 - Emmc Rx CMD + DATA Delay control 1 register value Please see Rx CMD + DATA Delay control 1 register definition for help **/ UINT32 EmmcRxCmdDataDelay1RegValue; -/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 2 register value +/** Offset 0x0068 - Emmc Rx CMD + DATA Delay control 2 register value Please see Rx CMD + DATA Delay control 2 register definition for help **/ UINT32 EmmcRxCmdDataDelay2RegValue; -/** Offset 0x004C - Emmc Rx Strobe Delay control register value +/** Offset 0x006C - Emmc Rx Strobe Delay control register value Please see Rx Strobe Delay control register definition for help **/ UINT32 EmmcRxStrobeDelayRegValue; -/** Offset 0x0050 - Enable SdCard Controller +/** Offset 0x0070 - Enable SdCard Controller Enable/disable SD Card Controller. $EN_DIS **/ UINT8 ScsSdCardEnabled; -/** Offset 0x0051 - SdCard power enable polarity +/** Offset 0x0071 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high **/ UINT8 SdCardPowerEnableActiveHigh; -/** Offset 0x0052 - Use tuned DLL values from policy +/** Offset 0x0072 - Use tuned DLL values from policy Set if FSP should use HS400 DLL values from policy $EN_DIS **/ UINT8 SdCardUseCustomDlls; -/** Offset 0x0053 - Reserved +/** Offset 0x0073 - Reserved **/ UINT8 Reserved0; -/** Offset 0x0054 - SdCard Tx CMD Delay control register value +/** Offset 0x0074 - SdCard Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help **/ UINT32 SdCardTxCmdDelayRegValue; -/** Offset 0x0058 - SdCard Tx DATA Delay control 1 register value +/** Offset 0x0078 - SdCard Tx DATA Delay control 1 register value Please see Tx DATA Delay control 1 register definition for help **/ UINT32 SdCardTxDataDelay1RegValue; -/** Offset 0x005C - SdCard Tx DATA Delay control 2 register value +/** Offset 0x007C - SdCard Tx DATA Delay control 2 register value Please see Tx DATA Delay control 2 register definition for help **/ UINT32 SdCardTxDataDelay2RegValue; -/** Offset 0x0060 - SdCard Rx CMD + DATA Delay control 1 register value +/** Offset 0x0080 - SdCard Rx CMD + DATA Delay control 1 register value Please see Rx CMD + DATA Delay control 1 register definition for help **/ UINT32 SdCardRxCmdDataDelay1RegValue; -/** Offset 0x0064 - SdCard Rx CMD + DATA Delay control 2 register value +/** Offset 0x0084 - SdCard Rx CMD + DATA Delay control 2 register value Please see Rx CMD + DATA Delay control 2 register definition for help **/ UINT32 SdCardRxCmdDataDelay2RegValue; -/** Offset 0x0068 - Reserved +/** Offset 0x0088 - Reserved **/ UINT8 Reserved1[12]; -/** Offset 0x0074 - SdCard Command Pad Termination +/** Offset 0x0094 - SdCard Command Pad Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up **/ UINT8 SdCardGpioCmdPadTermination; -/** Offset 0x0075 - Reserved +/** Offset 0x0095 - Reserved **/ UINT8 Reserved2[124]; -/** Offset 0x00F1 - Show SPI controller +/** Offset 0x0111 - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x00F2 - Reserved +/** Offset 0x0112 - Reserved **/ UINT8 Reserved3[2]; -/** Offset 0x00F4 - MicrocodeRegionBase +/** Offset 0x0114 - MicrocodeRegionBase Memory Base of Microcode Updates **/ UINT32 MicrocodeRegionBase; -/** Offset 0x00F8 - MicrocodeRegionSize +/** Offset 0x0118 - MicrocodeRegionSize Size of Microcode Updates **/ UINT32 MicrocodeRegionSize; -/** Offset 0x00FC - Turbo Mode +/** Offset 0x011C - Turbo Mode Enable/Disable Turbo mode. 0: disable, 1: enable $EN_DIS **/ UINT8 TurboMode; -/** Offset 0x00FD - Enable SATA SALP Support +/** Offset 0x011D - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x00FE - Enable SATA ports +/** Offset 0x011E - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x0106 - Enable SATA DEVSLP Feature +/** Offset 0x0126 - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x010E - Enable USB2 ports +/** Offset 0x012E - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x011E - Enable USB3 ports +/** Offset 0x013E - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x0128 - Enable xDCI controller +/** Offset 0x0148 - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x0129 - Reserved +/** Offset 0x0149 - Reserved **/ UINT8 Reserved4[3]; -/** Offset 0x012C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x014C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x0130 - Number of DevIntConfig Entry +/** Offset 0x0150 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0131 - PIRQx to IRQx Map Config +/** Offset 0x0151 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x0139 - Select GPIO IRQ Route +/** Offset 0x0159 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x013A - Select SciIrqSelect +/** Offset 0x015A - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x013B - Select TcoIrqSelect +/** Offset 0x015B - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x013C - Enable/Disable Tco IRQ +/** Offset 0x015C - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x013D - PCH HDA Verb Table Entry Number +/** Offset 0x015D - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x013E - Reserved +/** Offset 0x015E - Reserved **/ UINT8 Reserved5[2]; -/** Offset 0x0140 - PCH HDA Verb Table Pointer +/** Offset 0x0160 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x0144 - PCH HDA Codec Sx Wake Capability +/** Offset 0x0164 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x0145 - Enable SATA +/** Offset 0x0165 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x0146 - SATA Mode +/** Offset 0x0166 - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x0147 - SPIn Device Mode +/** Offset 0x0167 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[7]; -/** Offset 0x014E - SPI Chip Select Polarity +/** Offset 0x016E - SPI Chip Select Polarity Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh **/ UINT8 SerialIoSpiCsPolarity[14]; -/** Offset 0x015C - Reserved +/** Offset 0x017C - Reserved **/ UINT8 Reserved6[14]; -/** Offset 0x016A - SPIn Default Chip Select Output +/** Offset 0x018A - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1 **/ UINT8 SerialIoSpiDefaultCsOutput[7]; -/** Offset 0x0171 - SPIn Default Chip Select Mode HW/SW +/** Offset 0x0191 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW **/ UINT8 SerialIoSpiCsMode[7]; -/** Offset 0x0178 - SPIn Default Chip Select State Low/High +/** Offset 0x0198 - SPIn Default Chip Select State Low/High Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High **/ UINT8 SerialIoSpiCsState[7]; -/** Offset 0x017F - UARTn Device Mode +/** Offset 0x019F - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x0186 - Reserved +/** Offset 0x01A6 - Reserved **/ UINT8 Reserved7[2]; -/** Offset 0x0188 - Default BaudRate for each Serial IO UART +/** Offset 0x01A8 - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[7]; -/** Offset 0x01A4 - Default ParityType for each Serial IO UART +/** Offset 0x01C4 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[7]; -/** Offset 0x01AB - Default DataBits for each Serial IO UART +/** Offset 0x01CB - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[7]; -/** Offset 0x01B2 - Default StopBits for each Serial IO UART +/** Offset 0x01D2 - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[7]; -/** Offset 0x01B9 - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x01D9 - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[7]; -/** Offset 0x01C0 - Enable Dma for each Serial IO UART that supports it +/** Offset 0x01E0 - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[7]; -/** Offset 0x01C7 - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x01E7 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x01CE - Reserved +/** Offset 0x01EE - Reserved **/ UINT8 Reserved8[114]; -/** Offset 0x0240 - UART Number For Debug Purpose +/** Offset 0x0260 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. @@ -455,426 +455,426 @@ typedef struct { **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x0241 - Serial IO UART DBG2 table +/** Offset 0x0261 - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[7]; -/** Offset 0x0248 - I2Cn Device Mode +/** Offset 0x0268 - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x0250 - Serial IO I2C SDA Pin Muxing +/** Offset 0x0270 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x0270 - Serial IO I2C SCL Pin Muxing +/** Offset 0x0290 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x0290 - PCH SerialIo I2C Pads Termination +/** Offset 0x02B0 - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. **/ UINT8 PchSerialIoI2cPadsTermination[8]; -/** Offset 0x0298 - USB Per Port HS Preemphasis Bias +/** Offset 0x02B8 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2PhyPetxiset[16]; -/** Offset 0x02A8 - USB Per Port HS Transmitter Bias +/** Offset 0x02C8 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2PhyTxiset[16]; -/** Offset 0x02B8 - USB Per Port HS Transmitter Emphasis +/** Offset 0x02D8 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2PhyPredeemp[16]; -/** Offset 0x02C8 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x02E8 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2PhyPehalfbit[16]; -/** Offset 0x02D8 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x02F8 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x02E2 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x0302 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x02EC - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x030C - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x02F6 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0316 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x0300 - Enable LAN +/** Offset 0x0320 - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x0301 - Reserved +/** Offset 0x0321 - Reserved **/ UINT8 Reserved9[72]; -/** Offset 0x0349 - USB PDO Programming +/** Offset 0x0369 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x034A - Reserved +/** Offset 0x036A - Reserved **/ UINT8 Reserved10[2]; -/** Offset 0x034C - Power button debounce configuration +/** Offset 0x036C - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x0350 - PCH eSPI Master and Slave BME enabled +/** Offset 0x0370 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS **/ UINT8 PchEspiBmeMasterSlaveEnabled; -/** Offset 0x0351 - Reserved +/** Offset 0x0371 - Reserved **/ UINT8 Reserved11; -/** Offset 0x0352 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states +/** Offset 0x0372 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtV1p05RailEnabledStates; -/** Offset 0x0353 - Reserved +/** Offset 0x0373 - Reserved **/ UINT8 Reserved12; -/** Offset 0x0354 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states +/** Offset 0x0374 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtV1p05RailVoltage; -/** Offset 0x0356 - External V1P05 Icc Max Value +/** Offset 0x0376 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtV1p05RailIccMax; -/** Offset 0x0357 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states +/** Offset 0x0377 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailEnabledStates; -/** Offset 0x0358 - External Vnn Voltage Value that will be used in S0ix/Sx states +/** Offset 0x0378 - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtVnnRailVoltage; -/** Offset 0x035A - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x037A - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailIccMax; -/** Offset 0x035B - Mask to enable the usage of external Vnn VR rail in Sx states +/** Offset 0x037B - Mask to enable the usage of external Vnn VR rail in Sx states Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 **/ UINT8 PchFivrExtVnnRailSxEnabledStates; -/** Offset 0x035C - External Vnn Voltage Value that will be used in Sx states +/** Offset 0x037C - External Vnn Voltage Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) **/ UINT16 PchFivrExtVnnRailSxVoltage; -/** Offset 0x035E - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x037E - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 200mA **/ UINT8 PchFivrExtVnnRailSxIccMax; -/** Offset 0x035F - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage +/** Offset 0x037F - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. **/ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; -/** Offset 0x0360 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage +/** Offset 0x0380 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; -/** Offset 0x0361 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage +/** Offset 0x0381 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; -/** Offset 0x0362 - Transition time in microseconds from Off (0V) to High Current Mode Voltage +/** Offset 0x0382 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x0364 - Trace Hub Memory Base +/** Offset 0x0384 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly. **/ UINT32 TraceHubMemBase; -/** Offset 0x0368 - PMC Debug Message Enable +/** Offset 0x0388 - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix $EN_DIS **/ UINT8 PmcDbgMsgEn; -/** Offset 0x0369 - Reserved +/** Offset 0x0389 - Reserved **/ UINT8 Reserved13[3]; -/** Offset 0x036C - Pointer of ChipsetInit Binary +/** Offset 0x038C - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT32 ChipsetInitBinPtr; -/** Offset 0x0370 - Length of ChipsetInit Binary +/** Offset 0x0390 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x0374 - FIVR Dynamic Power Management +/** Offset 0x0394 - FIVR Dynamic Power Management Enable/Disable FIVR Dynamic Power Management. $EN_DIS **/ UINT8 PchFivrDynPm; -/** Offset 0x0375 - Reserved +/** Offset 0x0395 - Reserved **/ UINT8 Reserved14[3]; -/** Offset 0x0378 - CNVi Configuration +/** Offset 0x0398 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x0379 - CNVi BT Core +/** Offset 0x0399 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x037A - CNVi BT Audio Offload +/** Offset 0x039A - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x037B - Reserved +/** Offset 0x039B - Reserved **/ UINT8 Reserved15; -/** Offset 0x037C - CNVi RF_RESET pin muxing +/** Offset 0x039C - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. ICP-N: GPP_H12 = 0x2746E40C(default) or GPP_H1 = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0380 - CNVi CLKREQ pin muxing +/** Offset 0x03A0 - CNVi CLKREQ pin muxing Select CNVi CLKREQ pin depending on board routing. ICP-N: GPP_H13 = 0x2746E60D(default) or GPP_H2 = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x0384 - Enable Host C10 reporting through eSPI +/** Offset 0x03A4 - Enable Host C10 reporting through eSPI Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire. $EN_DIS **/ UINT8 PchEspiHostC10ReportEnable; -/** Offset 0x0385 - PCH USB2 PHY Power Gating enable +/** Offset 0x03A5 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PmcUsb2PhySusPgEnable; -/** Offset 0x0386 - PCH USB OverCurrent mapping enable +/** Offset 0x03A6 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x0387 - Espi Lgmr Memory Range decode +/** Offset 0x03A7 - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x0388 - Reserved +/** Offset 0x03A8 - Reserved **/ UINT8 Reserved16[2]; -/** Offset 0x038A - PCHHOT# pin +/** Offset 0x03AA - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x038B - SATA LED +/** Offset 0x03AB - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x038C - VRAlert# Pin +/** Offset 0x03AC - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x038D - AMT Switch +/** Offset 0x03AD - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x038E - WatchDog Timer Switch +/** Offset 0x03AE - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x038F - Manageability Mode set by Mebx +/** Offset 0x03AF - Manageability Mode set by Mebx Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS **/ UINT8 ManageabilityMode; -/** Offset 0x0390 - PET Progress +/** Offset 0x03B0 - PET Progress Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 FwProgress; -/** Offset 0x0391 - SOL Switch +/** Offset 0x03B1 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x0392 - OS Timer +/** Offset 0x03B2 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x0394 - BIOS Timer +/** Offset 0x03B4 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x0396 - Remote Assistance Trigger Availablilty +/** Offset 0x03B6 - Remote Assistance Trigger Availablilty Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. $EN_DIS **/ UINT8 RemoteAssistance; -/** Offset 0x0397 - KVM Switch +/** Offset 0x03B7 - KVM Switch Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtKvmEnabled; -/** Offset 0x0398 - KVM Switch +/** Offset 0x03B8 - KVM Switch Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. $EN_DIS **/ UINT8 ForcMebxSyncUp; -/** Offset 0x0399 - PCH PCIe root port connection type +/** Offset 0x03B9 - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[24]; -/** Offset 0x03B1 - PCIE RP Access Control Services Extended Capability +/** Offset 0x03D1 - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[24]; -/** Offset 0x03C9 - PCIE RP Clock Power Management +/** Offset 0x03E9 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x03E1 - Reserved +/** Offset 0x0401 - Reserved **/ UINT8 Reserved17; -/** Offset 0x03E2 - PCIE RP Detect Timeout Ms +/** Offset 0x0402 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x0412 - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x0432 - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x0413 - Reserved +/** Offset 0x0433 - Reserved **/ UINT8 Reserved18[2]; -/** Offset 0x0415 - Enable/Disable PavpEnable +/** Offset 0x0435 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x0416 - CdClock Frequency selection +/** Offset 0x0436 - CdClock Frequency selection 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz @@ -883,141 +883,141 @@ typedef struct { **/ UINT8 CdClock; -/** Offset 0x0417 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x0437 - Enable/Disable PeiGraphicsPeimInit Enable: FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable(Default): FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x0418 - Enable or disable GNA device +/** Offset 0x0438 - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 GnaEnable; -/** Offset 0x0419 - Reserved +/** Offset 0x0439 - Reserved **/ UINT8 Reserved19[11]; -/** Offset 0x0424 - Enable/Disable CrashLog +/** Offset 0x0444 - Enable/Disable CrashLog Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog $EN_DIS **/ UINT8 CpuCrashLogEnable; -/** Offset 0x0425 - Advanced Encryption Standard (AES) feature +/** Offset 0x0445 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 AesEnable; -/** Offset 0x0426 - Power State 3 enable/disable +/** Offset 0x0446 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes **/ UINT8 Psi3Enable[5]; -/** Offset 0x042B - Power State 4 enable/disable +/** Offset 0x044B - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 Psi4Enable[5]; -/** Offset 0x0430 - Imon slope correction +/** Offset 0x0450 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT16 ImonSlope[5]; -/** Offset 0x043A - Imon offset correction +/** Offset 0x045A - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto **/ UINT16 ImonOffset[5]; -/** Offset 0x0444 - Enable/Disable BIOS configuration of VR +/** Offset 0x0464 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 VrConfigEnable[5]; -/** Offset 0x0449 - Thermal Design Current enable/disable +/** Offset 0x0469 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcEnable[5]; -/** Offset 0x044E - Reserved +/** Offset 0x046E - Reserved **/ UINT8 Reserved20[2]; -/** Offset 0x0450 - Thermal Design Current time window +/** Offset 0x0470 - Thermal Design Current time window PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Range 1ms to 448s **/ UINT32 TdcTimeWindow[5]; -/** Offset 0x0464 - Thermal Design Current Lock +/** Offset 0x0484 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcLock[5]; -/** Offset 0x0469 - Platform Psys slope correction +/** Offset 0x0489 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25 **/ UINT8 PsysSlope; -/** Offset 0x046A - Platform Psys offset correction +/** Offset 0x048A - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348. **/ UINT16 PsysOffset; -/** Offset 0x046C - Acoustic Noise Mitigation feature +/** Offset 0x048C - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x046D - Reserved +/** Offset 0x048D - Reserved **/ UINT8 Reserved21[21]; -/** Offset 0x0482 - AcLoadline +/** Offset 0x04A2 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU. **/ UINT16 AcLoadline[5]; -/** Offset 0x048C - DcLoadline +/** Offset 0x04AC - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU. **/ UINT16 DcLoadline[5]; -/** Offset 0x0496 - Power State 1 Threshold current +/** Offset 0x04B6 - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi1Threshold[5]; -/** Offset 0x04A0 - Power State 2 Threshold current +/** Offset 0x04C0 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi2Threshold[5]; -/** Offset 0x04AA - Power State 3 Threshold current +/** Offset 0x04CA - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi3Threshold[5]; -/** Offset 0x04B4 - Icc Max limit +/** Offset 0x04D4 - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A **/ UINT16 IccMax[5]; -/** Offset 0x04BE - Enable VR specific mailbox command +/** Offset 0x04DE - Enable VR specific mailbox command VR specific mailbox commands. 00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. @@ -1025,53 +1025,53 @@ typedef struct { **/ UINT8 SendVrMbxCmd; -/** Offset 0x04BF - Enable or Disable TXT +/** Offset 0x04DF - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TxtEnable; -/** Offset 0x04C0 - Skip Multi-Processor Initialization +/** Offset 0x04E0 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x04C1 - Reserved +/** Offset 0x04E1 - Reserved **/ UINT8 Reserved22; -/** Offset 0x04C2 - FIVR RFI Frequency +/** Offset 0x04E2 - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock. **/ UINT16 FivrRfiFrequency; -/** Offset 0x04C4 - FIVR RFI Spread Spectrum +/** Offset 0x04E4 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; Range: 0.0% to 10.0% (0-100). **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x04C5 - Reserved +/** Offset 0x04E5 - Reserved **/ UINT8 Reserved23[3]; -/** Offset 0x04C8 - CpuBistData +/** Offset 0x04E8 - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; -/** Offset 0x04CC - CpuMpPpi +/** Offset 0x04EC - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x04D0 - CpuMpHob +/** Offset 0x04F0 - CpuMpHob Optional pointer for CpuMpHob. If the boot loader is a UEFI boot loader using API mode instead of dispatch mode, and FspsUpd->FspsConfig.CpuMpPpi != NULL, then FspsUpd->FspsConfig.CpuMpHob must be != NULL. See section 5.1.4 of the FSP Integration @@ -1079,759 +1079,759 @@ typedef struct { **/ UINT32 CpuMpHob; -/** Offset 0x04D4 - Reserved +/** Offset 0x04F4 - Reserved **/ UINT8 Reserved24[16]; -/** Offset 0x04E4 - PpinSupport to view Protected Processor Inventory Number +/** Offset 0x0504 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this flag is set) for PPIN Support 0: Disable, 1: Enable, 2: Auto **/ UINT8 PpinSupport; -/** Offset 0x04E5 - Enable or Disable Minimum Voltage Override +/** Offset 0x0505 - Enable or Disable Minimum Voltage Override Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 EnableMinVoltageOverride; -/** Offset 0x04E6 - Min Voltage for Runtime +/** Offset 0x0506 - Min Voltage for Runtime PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV **/ UINT16 MinVoltageRuntime; -/** Offset 0x04E8 - Base of memory region allocated for Processor Trace +/** Offset 0x0508 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT64 ProcessorTraceMemBase; -/** Offset 0x04F0 - Memory region allocation for Processor Trace +/** Offset 0x0510 - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT32 ProcessorTraceMemLength; -/** Offset 0x04F4 - Min Voltage for C8 +/** Offset 0x0514 - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV **/ UINT16 MinVoltageC8; -/** Offset 0x04F6 - Reserved +/** Offset 0x0516 - Reserved **/ UINT8 Reserved25[8]; -/** Offset 0x04FE - Enable Power Optimizer +/** Offset 0x051E - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x04FF - PCH Flash Protection Ranges Write Enble +/** Offset 0x051F - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x0504 - PCH Flash Protection Ranges Read Enble +/** Offset 0x0524 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x0509 - Reserved +/** Offset 0x0529 - Reserved **/ UINT8 Reserved26; -/** Offset 0x050A - PCH Protect Range Limit +/** Offset 0x052A - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x0514 - PCH Protect Range Base +/** Offset 0x0534 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x051E - Enable Pme +/** Offset 0x053E - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x051F - HD Audio Link Frequency +/** Offset 0x053F - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x0520 - Enable PCH Io Apic Entry 24-119 +/** Offset 0x0540 - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x0521 - PCH Io Apic ID +/** Offset 0x0541 - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x0522 - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x0542 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x0523 - Enable LOCKDOWN BIOS LOCK +/** Offset 0x0543 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x0524 - PCH Compatibility Revision ID +/** Offset 0x0544 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x0525 - Reserved +/** Offset 0x0545 - Reserved **/ UINT8 Reserved27; -/** Offset 0x0526 - RTC Cmos Memory Lock +/** Offset 0x0546 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x0527 - Enable PCIE RP HotPlug +/** Offset 0x0547 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[24]; -/** Offset 0x053F - Enable PCIE RP Pm Sci +/** Offset 0x055F - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x0557 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x0577 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[24]; -/** Offset 0x056F - Enable PCIE RP Clk Req Detect +/** Offset 0x058F - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x0587 - PCIE RP Advanced Error Report +/** Offset 0x05A7 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[24]; -/** Offset 0x059F - PCIE RP Unsupported Request Report +/** Offset 0x05BF - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[24]; -/** Offset 0x05B7 - PCIE RP Fatal Error Report +/** Offset 0x05D7 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[24]; -/** Offset 0x05CF - PCIE RP No Fatal Error Report +/** Offset 0x05EF - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[24]; -/** Offset 0x05E7 - PCIE RP Correctable Error Report +/** Offset 0x0607 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[24]; -/** Offset 0x05FF - PCIE RP System Error On Fatal Error +/** Offset 0x061F - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[24]; -/** Offset 0x0617 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0637 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[24]; -/** Offset 0x062F - PCIE RP System Error On Correctable Error +/** Offset 0x064F - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[24]; -/** Offset 0x0647 - PCIE RP Max Payload +/** Offset 0x0667 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x065F - Reserved +/** Offset 0x067F - Reserved **/ UINT8 Reserved28[13]; -/** Offset 0x066C - PCIE RP Pcie Speed +/** Offset 0x068C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[24]; -/** Offset 0x0684 - PCIE RP Physical Slot Number +/** Offset 0x06A4 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[24]; -/** Offset 0x069C - PCIE RP Completion Timeout +/** Offset 0x06BC - PCIE RP Completion Timeout The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[24]; -/** Offset 0x06B4 - PCIE RP Aspm +/** Offset 0x06D4 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[24]; -/** Offset 0x06CC - PCIE RP L1 Substates +/** Offset 0x06EC - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[24]; -/** Offset 0x06E4 - PCIE RP Ltr Enable +/** Offset 0x0704 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[24]; -/** Offset 0x06FC - PCIE RP Ltr Config Lock +/** Offset 0x071C - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x0714 - Reserved +/** Offset 0x0734 - Reserved **/ UINT8 Reserved29[44]; -/** Offset 0x0740 - PCIE Enable Peer Memory Write +/** Offset 0x0760 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x0741 - PCIE Compliance Test Mode +/** Offset 0x0761 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0742 - PCIE Rp Function Swap +/** Offset 0x0762 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0743 - Reserved +/** Offset 0x0763 - Reserved **/ UINT8 Reserved30[2]; -/** Offset 0x0745 - PCH Pm PME_B0_S5_DIS +/** Offset 0x0765 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0746 - PCIE IMR +/** Offset 0x0766 - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0747 - PCIE IMR port number +/** Offset 0x0767 - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0748 - PCH Pm Wol Enable Override +/** Offset 0x0768 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x0749 - PCH Pm Pcie Wake From DeepSx +/** Offset 0x0769 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x074A - PCH Pm WoW lan Enable +/** Offset 0x076A - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x074B - PCH Pm WoW lan DeepSx Enable +/** Offset 0x076B - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x074C - PCH Pm Lan Wake From DeepSx +/** Offset 0x076C - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x074D - PCH Pm Deep Sx Pol +/** Offset 0x076D - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x074E - PCH Pm Slp S3 Min Assert +/** Offset 0x076E - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x074F - PCH Pm Slp S4 Min Assert +/** Offset 0x076F - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0750 - PCH Pm Slp Sus Min Assert +/** Offset 0x0770 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0751 - PCH Pm Slp A Min Assert +/** Offset 0x0771 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0752 - USB Overcurrent Override for DbC +/** Offset 0x0772 - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts. $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0753 - PCH Pm Slp Strch Sus Up +/** Offset 0x0773 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0754 - PCH Pm Slp Lan Low Dc +/** Offset 0x0774 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x0755 - PCH Pm Pwr Btn Override Period +/** Offset 0x0775 - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x0756 - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x0776 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x0757 - PCH Pm Disable Native Power Button +/** Offset 0x0777 - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x0758 - PCH Pm ME_WAKE_STS +/** Offset 0x0778 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x0759 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x0779 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x075A - PCH Pm Reset Power Cycle Duration +/** Offset 0x077A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x075B - PCH Pm Pcie Pll Ssc +/** Offset 0x077B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x075C - PCH Legacy IO Low Latency Enable +/** Offset 0x077C - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x075D - PCH Sata Pwr Opt Enable +/** Offset 0x077D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x075E - PCH Sata eSATA Speed Limit +/** Offset 0x077E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x075F - PCH Sata Speed Limit +/** Offset 0x077F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x0760 - Enable SATA Port HotPlug +/** Offset 0x0780 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x0768 - Enable SATA Port Interlock Sw +/** Offset 0x0788 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x0770 - Enable SATA Port External +/** Offset 0x0790 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x0778 - Enable SATA Port SpinUp +/** Offset 0x0798 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0780 - Enable SATA Port Solid State Drive +/** Offset 0x07A0 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x0788 - Enable SATA Port Enable Dito Config +/** Offset 0x07A8 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0790 - Enable SATA Port DmVal +/** Offset 0x07B0 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0798 - Enable SATA Port DmVal +/** Offset 0x07B8 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x07A8 - Enable SATA Port ZpOdd +/** Offset 0x07C8 - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x07B0 - PCH Sata Rst Raid Alternate Id +/** Offset 0x07D0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. $EN_DIS **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x07B1 - PCH Sata Rst Raid0 +/** Offset 0x07D1 - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x07B2 - PCH Sata Rst Raid1 +/** Offset 0x07D2 - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x07B3 - PCH Sata Rst Raid10 +/** Offset 0x07D3 - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x07B4 - PCH Sata Rst Raid5 +/** Offset 0x07D4 - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x07B5 - PCH Sata Rst Irrt +/** Offset 0x07D5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x07B6 - PCH Sata Rst Orom Ui Banner +/** Offset 0x07D6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x07B7 - PCH Sata Rst Orom Ui Delay +/** Offset 0x07D7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x07B8 - PCH Sata Rst Hdd Unlock +/** Offset 0x07D8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x07B9 - PCH Sata Rst Led Locate +/** Offset 0x07D9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x07BA - PCH Sata Rst Irrt Only +/** Offset 0x07DA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x07BB - PCH Sata Rst Smart Storage +/** Offset 0x07DB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x07BC - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x07DC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x07BF - PCH Sata Rst Pcie Storage Port +/** Offset 0x07DF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x07C2 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x07E2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x07C5 - UFS enable/disable +/** Offset 0x07E5 - UFS enable/disable PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x07C7 - Reserved +/** Offset 0x07E7 - Reserved **/ UINT8 Reserved31; -/** Offset 0x07C8 - Thermal Throttling Custimized T0Level Value +/** Offset 0x07E8 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x07CA - Thermal Throttling Custimized T1Level Value +/** Offset 0x07EA - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x07CC - Thermal Throttling Custimized T2Level Value +/** Offset 0x07EC - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x07CE - Enable The Thermal Throttle +/** Offset 0x07EE - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x07CF - PMSync State 13 +/** Offset 0x07EF - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x07D0 - Thermal Throttle Lock +/** Offset 0x07F0 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x07D1 - Thermal Throttling Suggested Setting +/** Offset 0x07F1 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x07D2 - Enable PCH Cross Throttling +/** Offset 0x07F2 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x07D3 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x07F3 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x07D4 - DMI Thermal Sensor Suggested Setting +/** Offset 0x07F4 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x07D5 - Thermal Sensor 0 Target Width +/** Offset 0x07F5 - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x07D6 - Thermal Sensor 1 Target Width +/** Offset 0x07F6 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x07D7 - Thermal Sensor 2 Target Width +/** Offset 0x07F7 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x07D8 - Thermal Sensor 3 Target Width +/** Offset 0x07F8 - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x07D9 - Port 0 T1 Multipler +/** Offset 0x07F9 - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x07DA - Port 0 T2 Multipler +/** Offset 0x07FA - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x07DB - Port 0 T3 Multipler +/** Offset 0x07FB - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x07DC - Port 0 Tdispatch +/** Offset 0x07FC - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x07DD - Port 1 T1 Multipler +/** Offset 0x07FD - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x07DE - Port 1 T2 Multipler +/** Offset 0x07FE - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x07DF - Port 1 T3 Multipler +/** Offset 0x07FF - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x07E0 - Port 1 Tdispatch +/** Offset 0x0800 - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x07E1 - Port 0 Tinactive +/** Offset 0x0801 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x07E2 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x0802 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x07E3 - Port 1 Tinactive +/** Offset 0x0803 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x07E4 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x0804 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x07E5 - Sata Thermal Throttling Suggested Setting +/** Offset 0x0805 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x07E6 - Enable Memory Thermal Throttling +/** Offset 0x0806 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x07E7 - Memory Thermal Throttling +/** Offset 0x0807 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x07E9 - Enable Memory Thermal Throttling +/** Offset 0x0809 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x07EB - Enable Memory Thermal Throttling +/** Offset 0x080B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x07ED - Reserved +/** Offset 0x080D - Reserved **/ UINT8 Reserved32; -/** Offset 0x07EE - Thermal Device Temperature +/** Offset 0x080E - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x07F0 - USB2 Port Over Current Pin +/** Offset 0x0810 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0800 - USB3 Port Over Current Pin +/** Offset 0x0820 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x080A - Enable 8254 Static Clock Gating +/** Offset 0x082A - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -1839,7 +1839,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x080B - Enable 8254 Static Clock Gating On S3 +/** Offset 0x082B - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -1847,19 +1847,19 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x080C - PCH Sata Rst Optane Memory +/** Offset 0x082C - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x080D - PCH Sata Rst CPU Attached Storage +/** Offset 0x082D - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x080E - Enable TCO timer. +/** Offset 0x082E - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -1867,73 +1867,73 @@ typedef struct { **/ UINT8 EnableTcoTimer; -/** Offset 0x080F - Reserved +/** Offset 0x082F - Reserved **/ UINT8 Reserved33; -/** Offset 0x0810 - BgpdtHash[4] +/** Offset 0x0830 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0830 - BiosGuardAttr +/** Offset 0x0850 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x0834 - Reserved +/** Offset 0x0854 - Reserved **/ UINT8 Reserved34[4]; -/** Offset 0x0838 - BiosGuardModulePtr +/** Offset 0x0858 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0840 - SendEcCmd +/** Offset 0x0860 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0848 - EcCmdProvisionEav +/** Offset 0x0868 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0849 - EcCmdLock +/** Offset 0x0869 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x084A - Reserved +/** Offset 0x086A - Reserved **/ UINT8 Reserved35[6]; -/** Offset 0x0850 - SVID SDID table Poniter. +/** Offset 0x0870 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT32 SiSsidTablePtr; -/** Offset 0x0854 - Number of ssid table. +/** Offset 0x0874 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x0856 - Reserved +/** Offset 0x0876 - Reserved **/ UINT8 Reserved36[16]; -/** Offset 0x0866 - SATA RST Interrupt Mode +/** Offset 0x0886 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x0867 - ME Unconfig on RTC clear +/** Offset 0x0887 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -1941,7 +1941,7 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0868 - Enable PS_ON. +/** Offset 0x0888 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -1949,116 +1949,116 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0869 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x0889 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x086A - Pch Dmi Aspm Ctrl +/** Offset 0x088A - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x086B - PchDmiCwbEnable +/** Offset 0x088B - PchDmiCwbEnable Central Write Buffer feature configurable and disabled by default $EN_DIS **/ UINT8 PchDmiCwbEnable; -/** Offset 0x086C - OS IDLE Mode Enable +/** Offset 0x088C - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x086D - Reserved +/** Offset 0x088D - Reserved **/ UINT8 Reserved37[307]; -/** Offset 0x09A0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x09C0 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x09AA - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x09CA - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x09B4 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x09D4 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x09BE - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x09DE - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x09C8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x09E8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x09D2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x09F2 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x09DC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x09FC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x09E6 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x0A06 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x09F0 - Skip PAM regsiter lock +/** Offset 0x0A10 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x09F1 - EDRAM Test Mode +/** Offset 0x0A11 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x09F2 - Enable/Disable IGFX RenderStandby +/** Offset 0x0A12 - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x09F3 - Enable/Disable IGFX PmSupport +/** Offset 0x0A13 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x09F4 - Enable/Disable CdynmaxClamp +/** Offset 0x0A14 - Enable/Disable CdynmaxClamp Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x09F5 - GT Frequency Limit +/** Offset 0x0A15 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2072,105 +2072,105 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x09F6 - Disable Turbo GT +/** Offset 0x0A16 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x09F7 - Enable/Disable CdClock Init +/** Offset 0x0A17 - Enable/Disable CdClock Init Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock if not initialized by Gfx PEIM $EN_DIS **/ UINT8 SkipCdClockInit; -/** Offset 0x09F8 - Reserved +/** Offset 0x0A18 - Reserved **/ UINT8 Reserved38[15]; -/** Offset 0x0A07 - 1-Core Ratio Limit +/** Offset 0x0A27 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 **/ UINT8 OneCoreRatioLimit; -/** Offset 0x0A08 - 2-Core Ratio Limit +/** Offset 0x0A28 - 2-Core Ratio Limit 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x0A09 - 3-Core Ratio Limit +/** Offset 0x0A29 - 3-Core Ratio Limit 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x0A0A - 4-Core Ratio Limit +/** Offset 0x0A2A - 4-Core Ratio Limit 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x0A0B - Enable or Disable HWP +/** Offset 0x0A2B - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0A0C - Hardware Duty Cycle Control +/** Offset 0x0A2C - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x0A0D - Package Long duration turbo mode time +/** Offset 0x0A2D - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x0A0E - Short Duration Turbo Mode +/** Offset 0x0A2E - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x0A0F - Turbo settings Lock +/** Offset 0x0A2F - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0A10 - Package PL3 time window +/** Offset 0x0A30 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x0A11 - Package PL3 Duty Cycle +/** Offset 0x0A31 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x0A12 - Package PL3 Lock +/** Offset 0x0A32 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x0A13 - Package PL4 Lock +/** Offset 0x0A33 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x0A14 - TCC Activation Offset +/** Offset 0x0A34 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -2178,7 +2178,7 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0A15 - Tcc Offset Clamp Enable/Disable +/** Offset 0x0A35 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2186,318 +2186,318 @@ typedef struct { **/ UINT8 TccOffsetClamp; -/** Offset 0x0A16 - Tcc Offset Lock +/** Offset 0x0A36 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x0A17 - Custom Ratio State Entries +/** Offset 0x0A37 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x0A18 - Custom Short term Power Limit time window +/** Offset 0x0A38 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x0A19 - Custom Turbo Activation Ratio +/** Offset 0x0A39 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x0A1A - Custom Config Tdp Control +/** Offset 0x0A3A - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x0A1B - Custom Short term Power Limit time window +/** Offset 0x0A3B - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x0A1C - Custom Turbo Activation Ratio +/** Offset 0x0A3C - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x0A1D - Custom Config Tdp Control +/** Offset 0x0A3D - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x0A1E - Custom Short term Power Limit time window +/** Offset 0x0A3E - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x0A1F - Custom Turbo Activation Ratio +/** Offset 0x0A3F - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x0A20 - Custom Config Tdp Control +/** Offset 0x0A40 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x0A21 - ConfigTdp mode settings Lock +/** Offset 0x0A41 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x0A22 - Load Configurable TDP SSDT +/** Offset 0x0A42 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x0A23 - PL1 Enable value +/** Offset 0x0A43 - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x0A24 - PL1 timewindow +/** Offset 0x0A44 - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x0A25 - PL2 Enable Value +/** Offset 0x0A45 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x0A26 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0A46 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0A27 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0A47 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0A28 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0A48 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0A29 - Enable or Disable initialization of machine check registers +/** Offset 0x0A49 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0A2A - AP Idle Manner of waiting for SIPI +/** Offset 0x0A4A - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x0A2B - Control on Processor Trace output scheme +/** Offset 0x0A4B - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0A2C - Enable or Disable Processor Trace feature +/** Offset 0x0A4C - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0A2D - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0A4D - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x0A2E - Enable or Disable Energy Efficient P-state +/** Offset 0x0A4E - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x0A2F - Enable or Disable Energy Efficient Turbo +/** Offset 0x0A4F - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0A30 - Enable or Disable T states +/** Offset 0x0A50 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0A31 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0A51 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x0A32 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x0A52 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x0A33 - Enable or Disable PROCHOT# Response +/** Offset 0x0A53 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x0A34 - Enable or Disable VR Thermal Alert +/** Offset 0x0A54 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0A35 - Reserved +/** Offset 0x0A55 - Reserved **/ UINT8 Reserved39; -/** Offset 0x0A36 - Enable or Disable Thermal Monitor +/** Offset 0x0A56 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x0A37 - Enable or Disable CPU power states (C-states) +/** Offset 0x0A57 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0A38 - Configure C-State Configuration Lock +/** Offset 0x0A58 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0A39 - Enable or Disable Enhanced C-states +/** Offset 0x0A59 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x0A3A - Enable or Disable Package Cstate Demotion +/** Offset 0x0A5A - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x0A3B - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0A5B - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x0A3C - Enable or Disable CState-Pre wake +/** Offset 0x0A5C - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x0A3D - Enable or Disable TimedMwait Support. +/** Offset 0x0A5D - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x0A3E - Enable or Disable IO to MWAIT redirection +/** Offset 0x0A5E - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x0A3F - Set the Max Pkg Cstate +/** Offset 0x0A5F - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0A40 - TimeUnit for C-State Latency Control0 +/** Offset 0x0A60 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0A41 - TimeUnit for C-State Latency Control1 +/** Offset 0x0A61 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x0A42 - TimeUnit for C-State Latency Control2 +/** Offset 0x0A62 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x0A43 - TimeUnit for C-State Latency Control3 +/** Offset 0x0A63 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x0A44 - TimeUnit for C-State Latency Control4 +/** Offset 0x0A64 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x0A45 - TimeUnit for C-State Latency Control5 +/** Offset 0x0A65 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x0A46 - Interrupt Redirection Mode Select +/** Offset 0x0A66 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x0A47 - Lock prochot configuration +/** Offset 0x0A67 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0A48 - Configuration for boot TDP selection +/** Offset 0x0A68 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x0A49 - Max P-State Ratio +/** Offset 0x0A69 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0A4A - P-state ratios for custom P-state table +/** Offset 0x0A6A - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0A72 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0A92 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -2506,125 +2506,125 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0A82 - Platform Power Pmax +/** Offset 0x0AA2 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0A84 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0AA4 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x0A86 - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0AA6 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x0A88 - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0AA8 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x0A8A - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0AAA - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0A8C - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0AAC - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0A8E - Reserved +/** Offset 0x0AAE - Reserved **/ UINT8 Reserved40[2]; -/** Offset 0x0A90 - Package Long duration turbo mode power limit +/** Offset 0x0AB0 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0A94 - Package Short duration turbo mode power limit +/** Offset 0x0AB4 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x0A98 - Package PL3 power limit +/** Offset 0x0AB8 - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0A9C - Package PL4 power limit +/** Offset 0x0ABC - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0AA0 - Tcc Offset Time Window for RATL +/** Offset 0x0AC0 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0AA4 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0AC4 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x0AA8 - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0AC8 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0AAC - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0ACC - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0AB0 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0AD0 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0AB4 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0AD4 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x0AB8 - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x0AD8 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0ABC - Platform PL1 power +/** Offset 0x0ADC - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0AC0 - Platform PL2 power +/** Offset 0x0AE0 - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0AC4 - Race To Halt +/** Offset 0x0AE4 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -2632,20 +2632,20 @@ typedef struct { **/ UINT8 RaceToHalt; -/** Offset 0x0AC5 - Set Three Strike Counter Disable +/** Offset 0x0AE5 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0AC6 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x0AE6 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x0AC7 - 5-Core Ratio Limit +/** Offset 0x0AE7 - 5-Core Ratio Limit 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2653,7 +2653,7 @@ typedef struct { **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x0AC8 - 6-Core Ratio Limit +/** Offset 0x0AE8 - 6-Core Ratio Limit 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2661,7 +2661,7 @@ typedef struct { **/ UINT8 SixCoreRatioLimit; -/** Offset 0x0AC9 - 7-Core Ratio Limit +/** Offset 0x0AE9 - 7-Core Ratio Limit 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2669,7 +2669,7 @@ typedef struct { **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x0ACA - 8-Core Ratio Limit +/** Offset 0x0AEA - 8-Core Ratio Limit 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2677,214 +2677,210 @@ typedef struct { **/ UINT8 EightCoreRatioLimit; -/** Offset 0x0ACB - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x0AEB - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x0ACC - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled +/** Offset 0x0AEC - Intel Turbo Boost Max Technology 3.0 Driver + @Deprecated : Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x0ACD - Enable or Disable C1 Cstate Demotion +/** Offset 0x0AED - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0ACE - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0AEE - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0ACF - Minimum Ring ratio limit override +/** Offset 0x0AEF - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0AD0 - Maximum Ring ratio limit override +/** Offset 0x0AF0 - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0AD1 - Enable or Disable Per Core P State OS control +/** Offset 0x0AF1 - Enable or Disable Per Core P State OS control Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnablePerCorePState; -/** Offset 0x0AD2 - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x0AF2 - Enable or Disable HwP Autonomous Per Core P State OS control Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x0AD3 - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x0AF3 - Enable or Disable HwP Autonomous EPP Grouping Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x0AD4 - Enable or Disable EPB override over PECI +/** Offset 0x0AF4 - Enable or Disable EPB override over PECI Enable or Disable EPB override over PECI. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableEpbPeciOverride; -/** Offset 0x0AD5 - Enable or Disable Fast MSR for IA32_HWP_REQUEST +/** Offset 0x0AF5 - Enable or Disable Fast MSR for IA32_HWP_REQUEST Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableFastMsrHwpReq; -/** Offset 0x0AD6 - Reserved +/** Offset 0x0AF6 - Reserved **/ - UINT8 Reserved41[33]; + UINT8 Reserved41[34]; -/** Offset 0x0AF7 - End of Post message +/** Offset 0x0B18 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0AF8 - D0I3 Setting for HECI Disable +/** Offset 0x0B19 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x0AF9 - Enable LOCKDOWN SMI +/** Offset 0x0B1A - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0AFA - Enable LOCKDOWN BIOS Interface +/** Offset 0x0B1B - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0AFB - Unlock all GPIO pads +/** Offset 0x0B1C - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0AFC - PCH Unlock SideBand access +/** Offset 0x0B1D - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x0AFD - Reserved -**/ - UINT8 Reserved42; - -/** Offset 0x0AFE - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0B1E - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x0B2E - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0B4E - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0B5E - PCIE RP Snoop Latency Override Mode +/** Offset 0x0B7E - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x0B76 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0B96 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0B8E - PCIE RP Snoop Latency Override Value +/** Offset 0x0BAE - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0BBE - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0BDE - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x0BD6 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0BF6 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0BEE - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0C0E - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x0C1E - PCIE RP Slot Power Limit Scale +/** Offset 0x0C3E - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x0C36 - PCIE RP Slot Power Limit Value +/** Offset 0x0C56 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0C66 - PCIE RP Enable Port8xh Decode +/** Offset 0x0C86 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0C67 - PCIE Port8xh Decode Port Index +/** Offset 0x0C87 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0C68 - PCH Energy Reporting +/** Offset 0x0C88 - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0C69 - PCH Sata Test Mode +/** Offset 0x0C89 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0C6A - PCH USB OverCurrent mapping lock enable +/** Offset 0x0C8A - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0C6B - Reserved +/** Offset 0x0C8B - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; -/** Offset 0x0C6C - Mctp Broadcast Cycle +/** Offset 0x0C8C - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0C6D - Reserved +/** Offset 0x0C8D - Reserved **/ - UINT8 Reserved44[83]; + UINT8 Reserved43[83]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -2896,14 +2892,18 @@ typedef struct { FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0CC0 +/** Offset 0x0CE0 **/ - UINT8 UnusedUpdSpace36[6]; + UINT8 UnusedUpdSpace35[6]; -/** Offset 0x0CC6 +/** Offset 0x0CE6 **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 8f40c14067..28592cd47c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -251,7 +251,7 @@ typedef struct { UINT8 Reserved1[3]; /** Offset 0x0130 - Intel Enhanced Debug - DEPRECATED + @deprecated - Not used and has no effect 0 : Disable, 0x400000 : Enable **/ UINT32 IedSize; @@ -310,8 +310,8 @@ typedef struct { **/ UINT8 DciDbcMode; -/** Offset 0x014F - Enable DCI ModPHY Pwoer Gate - Enable ModPHY Pwoer Gate when DCI is enabled +/** Offset 0x014F - Enable DCI ModPHY Power Gate + Enable ModPHY Power Gate when DCI is enabled $EN_DIS **/ UINT8 DciModphyPg; @@ -797,7 +797,7 @@ typedef struct { **/ UINT8 RealtimeMemoryTiming; -/** Offset 0x025A - This is policy to control iTBT PCIe Multiple Segment setting. +/** Offset 0x025A - iTBT PCIe Multiple Segment setting When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable. $EN_DIS @@ -1468,7 +1468,7 @@ typedef struct { **/ UINT8 PchSataHsioTxGen3DeEmph[8]; -/** Offset 0x056F - PCH LPC Enhance the port 8xh decoding +/** Offset 0x056F - PCH LPC Enhanced Port 80 Decoding Original LPC only decodes one byte of port 80h. $EN_DIS **/ @@ -1476,7 +1476,7 @@ typedef struct { /** Offset 0x0570 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS + 0:LPC, 1:PCI **/ UINT8 PchPort80Route; @@ -2036,7 +2036,7 @@ typedef struct { UINT16 ChHashMask; /** Offset 0x0630 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) + Base reference clock value, in Hertz(Default is 100Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz **/ UINT32 BClkFrequency; @@ -2487,7 +2487,18 @@ typedef struct { /** Offset 0x089F - Reserved **/ - UINT8 Reserved44[129]; + UINT8 Reserved44[124]; + +/** Offset 0x091B - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level + 2 - skips GpioSetNativePadByFunction and GpioSetPadMode +**/ + UINT8 GpioOverride; + +/** Offset 0x091C - Reserved +**/ + UINT8 Reserved45[12]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2506,11 +2517,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0920 +/** Offset 0x0928 **/ - UINT8 UnusedUpdSpace25[6]; + UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0926 +/** Offset 0x092E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index c7086cd4a6..b7ef0008f9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -828,8 +828,8 @@ typedef struct { **/ UINT8 AmtKvmEnabled; -/** Offset 0x040E - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. +/** Offset 0x040E - Force MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; @@ -923,9 +923,15 @@ typedef struct { **/ UINT8 D3ColdEnable; -/** Offset 0x04B9 - Reserved +/** Offset 0x04B9 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS **/ - UINT8 Reserved20[8]; + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x04BA - Reserved +**/ + UINT8 Reserved20[7]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -1186,11 +1192,21 @@ typedef struct { **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x054B - Reserved +/** Offset 0x054B - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS **/ - UINT8 Reserved28[10]; + UINT8 FastPkgCRampDisable[5]; -/** Offset 0x0555 - Enable multi phases silicon initial +/** Offset 0x0550 - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; + +/** Offset 0x0555 - Enable multi phases silicon initialization A switch to determine MultiPhaseSiInit will be executed or not $EN_DIS **/ @@ -1198,7 +1214,7 @@ typedef struct { /** Offset 0x0556 - Reserved **/ - UINT8 Reserved29[10]; + UINT8 Reserved28[10]; /** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1247,7 +1263,7 @@ typedef struct { /** Offset 0x05A7 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. @@ -1278,7 +1294,7 @@ typedef struct { /** Offset 0x05AD - Reserved **/ - UINT8 Reserved31[3]; + UINT8 Reserved30[3]; /** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1299,7 +1315,7 @@ typedef struct { /** Offset 0x05BC - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved31[16]; /** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1340,796 +1356,796 @@ typedef struct { /** Offset 0x05DE - Reserved **/ - UINT8 Reserved33[8]; + UINT8 Reserved32[10]; -/** Offset 0x05E6 - Enable Power Optimizer +/** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x05E7 - PCH Flash Protection Ranges Write Enble +/** Offset 0x05E9 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x05EC - PCH Flash Protection Ranges Read Enble +/** Offset 0x05EE - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x05F1 - Reserved +/** Offset 0x05F3 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33; -/** Offset 0x05F2 - PCH Protect Range Limit +/** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x05FC - PCH Protect Range Base +/** Offset 0x05FE - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x0606 - Enable Pme +/** Offset 0x0608 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x0607 - HD Audio Link Frequency +/** Offset 0x0609 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x0608 - Reserved +/** Offset 0x060A - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved34[3]; -/** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x060C - Enable PCH Io Apic Entry 24-119 +/** Offset 0x060E - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x060D - PCH Io Apic ID +/** Offset 0x060F - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x060E - Enable PCH ISH SPI pins assigned +/** Offset 0x0610 - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x060F - Enable PCH ISH UART pins assigned +/** Offset 0x0611 - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x0611 - Enable PCH ISH I2C pins assigned +/** Offset 0x0613 - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x0614 - Enable PCH ISH GP pins assigned +/** Offset 0x0616 - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[8]; -/** Offset 0x061C - PCH ISH PDT Unlock Msg +/** Offset 0x061E - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x061D - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x061F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x061E - Enable LOCKDOWN BIOS LOCK +/** Offset 0x0620 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x061F - PCH Compatibility Revision ID +/** Offset 0x0621 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x0620 - Reserved +/** Offset 0x0622 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; -/** Offset 0x0621 - RTC Cmos Memory Lock +/** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x0622 - Enable PCIE RP HotPlug +/** Offset 0x0624 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[24]; -/** Offset 0x063A - Enable PCIE RP Pm Sci +/** Offset 0x063C - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x0652 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x0654 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[24]; -/** Offset 0x066A - Enable PCIE RP Clk Req Detect +/** Offset 0x066C - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x0682 - PCIE RP Advanced Error Report +/** Offset 0x0684 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[24]; -/** Offset 0x069A - PCIE RP Unsupported Request Report +/** Offset 0x069C - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[24]; -/** Offset 0x06B2 - PCIE RP Fatal Error Report +/** Offset 0x06B4 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[24]; -/** Offset 0x06CA - PCIE RP No Fatal Error Report +/** Offset 0x06CC - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[24]; -/** Offset 0x06E2 - PCIE RP Correctable Error Report +/** Offset 0x06E4 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[24]; -/** Offset 0x06FA - PCIE RP System Error On Fatal Error +/** Offset 0x06FC - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[24]; -/** Offset 0x0712 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0714 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[24]; -/** Offset 0x072A - PCIE RP System Error On Correctable Error +/** Offset 0x072C - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[24]; -/** Offset 0x0742 - PCIE RP Max Payload +/** Offset 0x0744 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x075A - Touch Host Controller Port 0 Assignment +/** Offset 0x075C - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x075B - Reserved +/** Offset 0x075D - Reserved **/ - UINT8 Reserved37[5]; + UINT8 Reserved36[7]; -/** Offset 0x0760 - Touch Host Controller Port 1 Assignment +/** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x0761 - Reserved +/** Offset 0x0765 - Reserved **/ - UINT8 Reserved38[7]; + UINT8 Reserved37[7]; -/** Offset 0x0768 - PCIE RP Pcie Speed +/** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[24]; -/** Offset 0x0780 - PCIE RP Physical Slot Number +/** Offset 0x0784 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[24]; -/** Offset 0x0798 - PCIE RP Completion Timeout +/** Offset 0x079C - PCIE RP Completion Timeout The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[24]; -/** Offset 0x07B0 - PCIE RP Aspm +/** Offset 0x07B4 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[24]; -/** Offset 0x07C8 - PCIE RP L1 Substates +/** Offset 0x07CC - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[24]; -/** Offset 0x07E0 - PCIE RP Ltr Enable +/** Offset 0x07E4 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[24]; -/** Offset 0x07F8 - PCIE RP Ltr Config Lock +/** Offset 0x07FC - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x0810 - Reserved +/** Offset 0x0814 - Reserved **/ - UINT8 Reserved39[45]; + UINT8 Reserved38[45]; -/** Offset 0x083D - PCIE Enable Peer Memory Write +/** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x083E - PCIE Compliance Test Mode +/** Offset 0x0842 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x083F - PCIE Rp Function Swap +/** Offset 0x0843 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0840 - Reserved +/** Offset 0x0844 - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved39[2]; -/** Offset 0x0842 - PCH Pm PME_B0_S5_DIS +/** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0843 - PCIE IMR +/** Offset 0x0847 - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0844 - PCIE IMR port number +/** Offset 0x0848 - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0845 - PCH Pm Wol Enable Override +/** Offset 0x0849 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x0846 - PCH Pm Pcie Wake From DeepSx +/** Offset 0x084A - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x0847 - PCH Pm WoW lan Enable +/** Offset 0x084B - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x0848 - PCH Pm WoW lan DeepSx Enable +/** Offset 0x084C - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x0849 - PCH Pm Lan Wake From DeepSx +/** Offset 0x084D - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x084A - PCH Pm Deep Sx Pol +/** Offset 0x084E - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x084B - PCH Pm Slp S3 Min Assert +/** Offset 0x084F - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x084C - PCH Pm Slp S4 Min Assert +/** Offset 0x0850 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x084D - PCH Pm Slp Sus Min Assert +/** Offset 0x0851 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x084E - PCH Pm Slp A Min Assert +/** Offset 0x0852 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x084F - USB Overcurrent Override for DbC +/** Offset 0x0853 - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts. $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0850 - PCH Pm Slp Strch Sus Up +/** Offset 0x0854 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0851 - PCH Pm Slp Lan Low Dc +/** Offset 0x0855 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x0852 - PCH Pm Pwr Btn Override Period +/** Offset 0x0856 - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x0853 - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x0857 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x0854 - PCH Pm Disable Native Power Button +/** Offset 0x0858 - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x0855 - PCH Pm ME_WAKE_STS +/** Offset 0x0859 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x0856 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x085A - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x0857 - PCH Pm Reset Power Cycle Duration +/** Offset 0x085B - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x0858 - PCH Pm Pcie Pll Ssc +/** Offset 0x085C - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x0859 - PCH Legacy IO Low Latency Enable +/** Offset 0x085D - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x085A - PCH Sata Pwr Opt Enable +/** Offset 0x085E - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x085B - PCH Sata eSATA Speed Limit +/** Offset 0x085F - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x085C - PCH Sata Speed Limit +/** Offset 0x0860 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x085D - Enable SATA Port HotPlug +/** Offset 0x0861 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x0865 - Enable SATA Port Interlock Sw +/** Offset 0x0869 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x086D - Enable SATA Port External +/** Offset 0x0871 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x0875 - Enable SATA Port SpinUp +/** Offset 0x0879 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x087D - Enable SATA Port Solid State Drive +/** Offset 0x0881 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x0885 - Enable SATA Port Enable Dito Config +/** Offset 0x0889 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x088D - Enable SATA Port DmVal +/** Offset 0x0891 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0895 - Reserved +/** Offset 0x0899 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40; -/** Offset 0x0896 - Enable SATA Port DmVal +/** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x08A6 - Enable SATA Port ZpOdd +/** Offset 0x08AA - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x08AE - PCH Sata Rst Raid Alternate Id +/** Offset 0x08B2 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. $EN_DIS **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x08AF - PCH Sata Rst Raid0 +/** Offset 0x08B3 - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x08B0 - PCH Sata Rst Raid1 +/** Offset 0x08B4 - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x08B1 - PCH Sata Rst Raid10 +/** Offset 0x08B5 - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x08B2 - PCH Sata Rst Raid5 +/** Offset 0x08B6 - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x08B3 - PCH Sata Rst Irrt +/** Offset 0x08B7 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x08B4 - PCH Sata Rst Orom Ui Banner +/** Offset 0x08B8 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x08B5 - PCH Sata Rst Orom Ui Delay +/** Offset 0x08B9 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x08B6 - PCH Sata Rst Hdd Unlock +/** Offset 0x08BA - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x08B7 - PCH Sata Rst Led Locate +/** Offset 0x08BB - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x08B8 - PCH Sata Rst Irrt Only +/** Offset 0x08BC - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x08B9 - PCH Sata Rst Smart Storage +/** Offset 0x08BD - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x08BA - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x08BE - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x08BD - PCH Sata Rst Pcie Storage Port +/** Offset 0x08C1 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x08C0 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x08C4 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x08C3 - UFS enable/disable +/** Offset 0x08C7 - UFS enable/disable PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x08C5 - Reserved +/** Offset 0x08C9 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved41; -/** Offset 0x08C6 - Thermal Throttling Custimized T0Level Value +/** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x08C8 - Thermal Throttling Custimized T1Level Value +/** Offset 0x08CC - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x08CA - Thermal Throttling Custimized T2Level Value +/** Offset 0x08CE - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x08CC - Enable The Thermal Throttle +/** Offset 0x08D0 - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x08CD - PMSync State 13 +/** Offset 0x08D1 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x08CE - Thermal Throttle Lock +/** Offset 0x08D2 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x08CF - Thermal Throttling Suggested Setting +/** Offset 0x08D3 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x08D0 - Enable PCH Cross Throttling +/** Offset 0x08D4 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x08D1 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x08D5 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x08D2 - DMI Thermal Sensor Suggested Setting +/** Offset 0x08D6 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x08D3 - Thermal Sensor 0 Target Width +/** Offset 0x08D7 - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x08D4 - Thermal Sensor 1 Target Width +/** Offset 0x08D8 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x08D5 - Thermal Sensor 2 Target Width +/** Offset 0x08D9 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x08D6 - Thermal Sensor 3 Target Width +/** Offset 0x08DA - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x08D7 - Port 0 T1 Multipler +/** Offset 0x08DB - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x08D8 - Port 0 T2 Multipler +/** Offset 0x08DC - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x08D9 - Port 0 T3 Multipler +/** Offset 0x08DD - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x08DA - Port 0 Tdispatch +/** Offset 0x08DE - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x08DB - Port 1 T1 Multipler +/** Offset 0x08DF - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x08DC - Port 1 T2 Multipler +/** Offset 0x08E0 - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x08DD - Port 1 T3 Multipler +/** Offset 0x08E1 - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x08DE - Port 1 Tdispatch +/** Offset 0x08E2 - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x08DF - Port 0 Tinactive +/** Offset 0x08E3 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x08E0 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x08E4 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x08E1 - Port 1 Tinactive +/** Offset 0x08E5 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x08E2 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x08E6 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x08E3 - Sata Thermal Throttling Suggested Setting +/** Offset 0x08E7 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x08E4 - Enable Memory Thermal Throttling +/** Offset 0x08E8 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x08E5 - Memory Thermal Throttling +/** Offset 0x08E9 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x08E7 - Enable Memory Thermal Throttling +/** Offset 0x08EB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x08E9 - Enable Memory Thermal Throttling +/** Offset 0x08ED - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x08EB - Reserved +/** Offset 0x08EF - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; -/** Offset 0x08EC - Thermal Device Temperature +/** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x08EE - USB2 Port Over Current Pin +/** Offset 0x08F2 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x08FE - USB3 Port Over Current Pin +/** Offset 0x0902 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0908 - Enable xHCI LTR override +/** Offset 0x090C - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x0909 - Reserved +/** Offset 0x090D - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved43[3]; -/** Offset 0x090C - xHCI High Idle Time LTR override +/** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x0910 - xHCI Medium Idle Time LTR override +/** Offset 0x0914 - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x0914 - xHCI Low Idle Time LTR override +/** Offset 0x0918 - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x0918 - Enable 8254 Static Clock Gating +/** Offset 0x091C - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2137,7 +2153,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x0919 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x091D - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2145,19 +2161,19 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x091A - PCH Sata Rst Optane Memory +/** Offset 0x091E - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x091B - PCH Sata Rst CPU Attached Storage +/** Offset 0x091F - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x091C - Enable TCO timer. +/** Offset 0x0920 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2165,106 +2181,107 @@ typedef struct { **/ UINT8 EnableTcoTimer; -/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0921 - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x091E - Reserved +/** Offset 0x0922 - Reserved **/ - UINT8 Reserved45[2]; + UINT8 Reserved44[6]; -/** Offset 0x0920 - BgpdtHash[4] +/** Offset 0x0928 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0940 - BiosGuardAttr +/** Offset 0x0948 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x0944 - Reserved +/** Offset 0x094C - Reserved **/ - UINT8 Reserved46[4]; + UINT8 Reserved45[4]; -/** Offset 0x0948 - BiosGuardModulePtr +/** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0950 - SendEcCmd +/** Offset 0x0958 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0958 - EcCmdProvisionEav +/** Offset 0x0960 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0959 - EcCmdLock +/** Offset 0x0961 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x095A - Reserved +/** Offset 0x0962 - Reserved **/ - UINT8 Reserved47[6]; + UINT8 Reserved46[6]; -/** Offset 0x0960 - SgxEpoch0 +/** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values **/ UINT64 SgxEpoch0; -/** Offset 0x0968 - SgxEpoch1 +/** Offset 0x0970 - SgxEpoch1 SgxEpoch1 default values **/ UINT64 SgxEpoch1; -/** Offset 0x0970 - SgxSinitNvsData +/** Offset 0x0978 - SgxSinitNvsData SgxSinitNvsData default values **/ UINT8 SgxSinitNvsData; -/** Offset 0x0971 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. +/** Offset 0x0979 - Si Config CSM Flag. + @deprecated Platform specific common policies that used by several silicon + components. CSM status flag. $EN_DIS **/ UINT8 SiCsmFlag; -/** Offset 0x0972 - Reserved +/** Offset 0x097A - Reserved **/ - UINT8 Reserved48[6]; + UINT8 Reserved47[6]; -/** Offset 0x0978 - SVID SDID table Poniter. +/** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT32 SiSsidTablePtr; -/** Offset 0x097C - Number of ssid table. +/** Offset 0x0984 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x097E - USB2 Port Reset Message Enable +/** Offset 0x0986 - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message **/ UINT8 PortResetMessageEnable[16]; -/** Offset 0x098E - SATA RST Interrupt Mode +/** Offset 0x0996 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x098F - ME Unconfig on RTC clear +/** Offset 0x0997 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2272,7 +2289,7 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0990 - Enable PS_ON. +/** Offset 0x0998 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2280,124 +2297,124 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0991 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x0999 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x0992 - Pch Dmi Aspm Ctrl +/** Offset 0x099A - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x0993 - PchDmiCwbEnable +/** Offset 0x099B - PchDmiCwbEnable Central Write Buffer feature configurable and enabled by default $EN_DIS **/ UINT8 PchDmiCwbEnable; -/** Offset 0x0994 - OS IDLE Mode Enable +/** Offset 0x099C - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x0995 - Reserved +/** Offset 0x099D - Reserved **/ - UINT8 Reserved49[315]; + UINT8 Reserved48[315]; -/** Offset 0x0AD0 - RpPtmBytes +/** Offset 0x0AD8 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0AD4 - Reserved +/** Offset 0x0ADC - Reserved **/ - UINT8 Reserved50[16]; + UINT8 Reserved49[16]; -/** Offset 0x0AE4 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x0AEE - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x0AF6 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x0AF8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x0B00 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x0B02 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x0B0A - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x0B0C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x0B14 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x0B16 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x0B1E - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x0B20 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x0B28 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x0B2A - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x0B32 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x0B34 - Skip PAM regsiter lock +/** Offset 0x0B3C - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x0B35 - EDRAM Test Mode +/** Offset 0x0B3D - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x0B36 - Enable/Disable IGFX RenderStandby +/** Offset 0x0B3E - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x0B37 - Enable/Disable IGFX PmSupport +/** Offset 0x0B3F - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0B38 - Enable/Disable CdynmaxClamp +/** Offset 0x0B40 - Enable/Disable CdynmaxClamp Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x0B39 - GT Frequency Limit +/** Offset 0x0B41 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2411,105 +2428,105 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x0B3A - Disable Turbo GT +/** Offset 0x0B42 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x0B3B - Enable/Disable CdClock Init +/** Offset 0x0B43 - Enable/Disable CdClock Init Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock if not initialized by Gfx PEIM $EN_DIS **/ UINT8 SkipCdClockInit; -/** Offset 0x0B3C - Reserved +/** Offset 0x0B44 - Reserved **/ - UINT8 Reserved51[16]; + UINT8 Reserved50[16]; -/** Offset 0x0B4C - 1-Core Ratio Limit +/** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 **/ UINT8 OneCoreRatioLimit; -/** Offset 0x0B4D - 2-Core Ratio Limit +/** Offset 0x0B55 - 2-Core Ratio Limit 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x0B4E - 3-Core Ratio Limit +/** Offset 0x0B56 - 3-Core Ratio Limit 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x0B4F - 4-Core Ratio Limit +/** Offset 0x0B57 - 4-Core Ratio Limit 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x0B50 - Enable or Disable HWP +/** Offset 0x0B58 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0B51 - Hardware Duty Cycle Control +/** Offset 0x0B59 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x0B52 - Package Long duration turbo mode time +/** Offset 0x0B5A - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x0B53 - Short Duration Turbo Mode +/** Offset 0x0B5B - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x0B54 - Turbo settings Lock +/** Offset 0x0B5C - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0B55 - Package PL3 time window +/** Offset 0x0B5D - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x0B56 - Package PL3 Duty Cycle +/** Offset 0x0B5E - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x0B57 - Package PL3 Lock +/** Offset 0x0B5F - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x0B58 - Package PL4 Lock +/** Offset 0x0B60 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x0B59 - TCC Activation Offset +/** Offset 0x0B61 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -2517,7 +2534,7 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0B5A - Tcc Offset Clamp Enable/Disable +/** Offset 0x0B62 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2525,317 +2542,317 @@ typedef struct { **/ UINT8 TccOffsetClamp; -/** Offset 0x0B5B - Tcc Offset Lock +/** Offset 0x0B63 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x0B5C - Custom Ratio State Entries +/** Offset 0x0B64 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x0B5D - Custom Short term Power Limit time window +/** Offset 0x0B65 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x0B5E - Custom Turbo Activation Ratio +/** Offset 0x0B66 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x0B5F - Custom Config Tdp Control +/** Offset 0x0B67 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x0B60 - Custom Short term Power Limit time window +/** Offset 0x0B68 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x0B61 - Custom Turbo Activation Ratio +/** Offset 0x0B69 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x0B62 - Custom Config Tdp Control +/** Offset 0x0B6A - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x0B63 - Custom Short term Power Limit time window +/** Offset 0x0B6B - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x0B64 - Custom Turbo Activation Ratio +/** Offset 0x0B6C - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x0B65 - Custom Config Tdp Control +/** Offset 0x0B6D - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x0B66 - ConfigTdp mode settings Lock +/** Offset 0x0B6E - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x0B67 - Load Configurable TDP SSDT +/** Offset 0x0B6F - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x0B68 - PL1 Enable value +/** Offset 0x0B70 - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x0B69 - PL1 timewindow +/** Offset 0x0B71 - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x0B6A - PL2 Enable Value +/** Offset 0x0B72 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x0B6B - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0B73 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0B6C - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0B74 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0B6D - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0B75 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0B6E - Enable or Disable initialization of machine check registers +/** Offset 0x0B76 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0B6F - AP Idle Manner of waiting for SIPI +/** Offset 0x0B77 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x0B70 - Control on Processor Trace output scheme +/** Offset 0x0B78 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0B71 - Enable or Disable Processor Trace feature +/** Offset 0x0B79 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0B72 - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0B7A - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x0B73 - Enable or Disable Energy Efficient P-state +/** Offset 0x0B7B - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x0B74 - Enable or Disable Energy Efficient Turbo +/** Offset 0x0B7C - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0B75 - Enable or Disable T states +/** Offset 0x0B7D - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0B76 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0B7E - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x0B77 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x0B7F - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x0B78 - Enable or Disable PROCHOT# Response +/** Offset 0x0B80 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x0B79 - Enable or Disable VR Thermal Alert +/** Offset 0x0B81 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0B7A - Reserved +/** Offset 0x0B82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; -/** Offset 0x0B7B - Enable or Disable Thermal Monitor +/** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x0B7C - Enable or Disable CPU power states (C-states) +/** Offset 0x0B84 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0B7D - Configure C-State Configuration Lock +/** Offset 0x0B85 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0B7E - Enable or Disable Enhanced C-states +/** Offset 0x0B86 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x0B7F - Enable or Disable Package Cstate Demotion +/** Offset 0x0B87 - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x0B80 - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0B88 - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x0B81 - Enable or Disable CState-Pre wake +/** Offset 0x0B89 - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x0B82 - Enable or Disable TimedMwait Support. +/** Offset 0x0B8A - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x0B83 - Enable or Disable IO to MWAIT redirection +/** Offset 0x0B8B - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x0B84 - Set the Max Pkg Cstate +/** Offset 0x0B8C - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0B85 - TimeUnit for C-State Latency Control0 +/** Offset 0x0B8D - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0B86 - TimeUnit for C-State Latency Control1 +/** Offset 0x0B8E - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x0B87 - TimeUnit for C-State Latency Control2 +/** Offset 0x0B8F - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x0B88 - TimeUnit for C-State Latency Control3 +/** Offset 0x0B90 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x0B89 - TimeUnit for C-State Latency Control4 +/** Offset 0x0B91 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x0B8A - TimeUnit for C-State Latency Control5 +/** Offset 0x0B92 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x0B8B - Interrupt Redirection Mode Select +/** Offset 0x0B93 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x0B8C - Lock prochot configuration +/** Offset 0x0B94 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0B8D - Configuration for boot TDP selection +/** Offset 0x0B95 - Configuration for boot TDP selection Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; -/** Offset 0x0B8E - Max P-State Ratio +/** Offset 0x0B96 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0B8F - P-state ratios for custom P-state table +/** Offset 0x0B97 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0BB7 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0BBF - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -2844,125 +2861,125 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0BC7 - Reserved +/** Offset 0x0BCF - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved52; -/** Offset 0x0BC8 - Platform Power Pmax +/** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0BCA - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0BD2 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x0BCC - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0BD4 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x0BCE - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0BD6 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x0BD0 - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0BD8 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0BD2 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0BDA - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0BD4 - Package Long duration turbo mode power limit +/** Offset 0x0BDC - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0BD8 - Package Short duration turbo mode power limit +/** Offset 0x0BE0 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x0BDC - Package PL3 power limit +/** Offset 0x0BE4 - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0BE0 - Package PL4 power limit +/** Offset 0x0BE8 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0BE4 - Tcc Offset Time Window for RATL +/** Offset 0x0BEC - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0BE8 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0BF0 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x0BEC - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0BF4 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0BF0 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0BF8 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0BF4 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0BFC - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0BF8 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0C00 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x0BFC - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x0C04 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0C00 - Platform PL1 power +/** Offset 0x0C08 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0C04 - Platform PL2 power +/** Offset 0x0C0C - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0C08 - Race To Halt +/** Offset 0x0C10 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -2970,20 +2987,20 @@ typedef struct { **/ UINT8 RaceToHalt; -/** Offset 0x0C09 - Set Three Strike Counter Disable +/** Offset 0x0C11 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0C0A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x0C12 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x0C0B - 5-Core Ratio Limit +/** Offset 0x0C13 - 5-Core Ratio Limit 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2991,7 +3008,7 @@ typedef struct { **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x0C0C - 6-Core Ratio Limit +/** Offset 0x0C14 - 6-Core Ratio Limit 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -2999,7 +3016,7 @@ typedef struct { **/ UINT8 SixCoreRatioLimit; -/** Offset 0x0C0D - 7-Core Ratio Limit +/** Offset 0x0C15 - 7-Core Ratio Limit 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -3007,7 +3024,7 @@ typedef struct { **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x0C0E - 8-Core Ratio Limit +/** Offset 0x0C16 - 8-Core Ratio Limit 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 83 @@ -3015,219 +3032,219 @@ typedef struct { **/ UINT8 EightCoreRatioLimit; -/** Offset 0x0C0F - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x0C17 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x0C10 - Intel Turbo Boost Max Technology 3.0 Driver +/** Offset 0x0C18 - Intel Turbo Boost Max Technology 3.0 Driver @Deprecated: Intel Turbo Boost Max Technology 3.0 Driver doesn't support for TGL $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x0C11 - Enable or Disable C1 Cstate Demotion +/** Offset 0x0C19 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0C12 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0C1A - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0C13 - Minimum Ring ratio limit override +/** Offset 0x0C1B - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0C14 - Maximum Ring ratio limit override +/** Offset 0x0C1C - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0C15 - Enable or Disable Per Core P State OS control +/** Offset 0x0C1D - Enable or Disable Per Core P State OS control Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnablePerCorePState; -/** Offset 0x0C16 - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x0C1E - Enable or Disable HwP Autonomous Per Core P State OS control Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x0C17 - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x0C1F - Enable or Disable HwP Autonomous EPP Grouping Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x0C18 - Enable or Disable EPB override over PECI +/** Offset 0x0C20 - Enable or Disable EPB override over PECI Enable or Disable EPB override over PECI. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableEpbPeciOverride; -/** Offset 0x0C19 - Enable or Disable Fast MSR for IA32_HWP_REQUEST +/** Offset 0x0C21 - Enable or Disable Fast MSR for IA32_HWP_REQUEST Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableFastMsrHwpReq; -/** Offset 0x0C1A - Reserved +/** Offset 0x0C22 - Reserved **/ - UINT8 Reserved54[17]; + UINT8 Reserved53[17]; -/** Offset 0x0C2B - SgxSinitDataFromTpm +/** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x0C2C - Reserved +/** Offset 0x0C34 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16]; -/** Offset 0x0C3C - End of Post message +/** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0C3D - D0I3 Setting for HECI Disable +/** Offset 0x0C45 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x0C3E - Enable LOCKDOWN SMI +/** Offset 0x0C46 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0C3F - Enable LOCKDOWN BIOS Interface +/** Offset 0x0C47 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0C40 - Unlock all GPIO pads +/** Offset 0x0C48 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0C41 - PCH Unlock SideBand access +/** Offset 0x0C49 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0C4A - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x0C72 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0C7A - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0CA2 - PCIE RP Snoop Latency Override Mode +/** Offset 0x0CAA - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x0CBA - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0CC2 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0CD2 - PCIE RP Snoop Latency Override Value +/** Offset 0x0CDA - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0D02 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0D0A - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x0D1A - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0D22 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0D32 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0D3A - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x0D62 - PCIE RP Slot Power Limit Scale +/** Offset 0x0D6A - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x0D7A - PCIE RP Slot Power Limit Value +/** Offset 0x0D82 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0DAA - PCIE RP Enable Port8xh Decode +/** Offset 0x0DB2 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0DAB - PCIE Port8xh Decode Port Index +/** Offset 0x0DB3 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0DAC - PCH Energy Reporting +/** Offset 0x0DB4 - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0DAD - PCH Sata Test Mode +/** Offset 0x0DB5 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0DAE - PCH USB OverCurrent mapping lock enable +/** Offset 0x0DB6 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0DAF - LpmStateEnableMask +/** Offset 0x0DB7 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0DB0 - Mctp Broadcast Cycle +/** Offset 0x0DB8 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0DB1 - Reserved +/** Offset 0x0DB9 - Reserved **/ - UINT8 Reserved56[231]; + UINT8 Reserved55[239]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3242,11 +3259,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E98 +/** Offset 0x0EA8 **/ - UINT8 UnusedUpdSpace35[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0E9E +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/tests/device/Makefile.inc b/tests/device/Makefile.inc index 10223c52cc..4626c3cf3d 100644 --- a/tests/device/Makefile.inc +++ b/tests/device/Makefile.inc @@ -1,7 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only tests-y += i2c-test +tests-y += ddr4-test i2c-test-srcs += tests/device/i2c-test.c i2c-test-srcs += src/device/i2c.c i2c-test-mocks += platform_i2c_transfer + +ddr4-test-srcs += tests/device/ddr4-test.c +ddr4-test-srcs += tests/stubs/console.c +ddr4-test-srcs += src/device/dram/ddr4.c \ No newline at end of file diff --git a/tests/device/ddr4-test.c b/tests/device/ddr4-test.c new file mode 100644 index 0000000000..0a9831da75 --- /dev/null +++ b/tests/device/ddr4-test.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void ddr4_speed_mhz_to_mts_test(void **state) +{ + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(0)); + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(667)); + + assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(668)); + assert_int_equal(1600, ddr4_speed_mhz_to_reported_mts(800)); + + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(801)); + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(933)); + assert_int_equal(1866, ddr4_speed_mhz_to_reported_mts(934)); + + assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1066)); + assert_int_equal(2133, ddr4_speed_mhz_to_reported_mts(1067)); + + assert_int_equal(2400, ddr4_speed_mhz_to_reported_mts(1200)); + + assert_int_equal(2666, ddr4_speed_mhz_to_reported_mts(1333)); + + assert_int_equal(2933, ddr4_speed_mhz_to_reported_mts(1466)); + + assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1467)); + assert_int_equal(3200, ddr4_speed_mhz_to_reported_mts(1600)); + + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(1601)); + assert_int_equal(0, ddr4_speed_mhz_to_reported_mts(INT16_MAX)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(ddr4_speed_mhz_to_mts_test) + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} diff --git a/util/README.md b/util/README.md index 8b05f6f729..778c83efda 100644 --- a/util/README.md +++ b/util/README.md @@ -32,7 +32,7 @@ _coreboot.org-status_ and _docs.coreboot.org_ * __ectool__ - Dumps the RAM of a laptop's Embedded/Environmental Controller (EC). `C` * __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2). -`Python2` +`Python3` * __find_usbdebug__ - Help find USB debug ports * __futility__ - Firmware utility for signing ChromeOS images `Make` * __fuzz-tests__ - Create test cases that crash the jpeg code. `C` @@ -65,7 +65,7 @@ embedded controller and insert them to the firmware image. `C` partial deblobbing of Intel ME/TXE firmware images `Python` * __mma__ - Memory Margin Analysis automation tests `Bash` * __msrtool__ - Dumps chipset-specific MSR registers. `C` -* __mtkheader__ - Generate MediaTek bootload header. `Python2` +* __mtkheader__ - Generate MediaTek bootload header. `Python3` * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` @@ -83,7 +83,7 @@ devices on the board such as dGPU. `C` can be passed to SPIKE, the RISC-V reference emulator.`Bash` * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` -* __rockchip__ - Generate Rockchip idblock bootloader. `Python2` +* __rockchip__ - Generate Rockchip idblock bootloader. `Python3` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the diff --git a/util/abuild/abuild b/util/abuild/abuild index 903a569b3e..7561495d7b 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -263,10 +263,8 @@ function update_config # Disable all other payload config options { echo "# CONFIG_PAYLOAD_SEABIOS is not set" - echo "# CONFIG_PAYLOAD_BAYOU is not set" echo "# CONFIG_PAYLOAD_FILO is not set" echo "# CONFIG_PAYLOAD_GRUB2 is not set" - echo "# CONFIG_PAYLOAD_OPENBIOS is not set" echo "# CONFIG_PAYLOAD_DEPTHCHARGE is not set" echo "# CONFIG_PAYLOAD_LINUXBOOT is not set" echo "# CONFIG_PAYLOAD_UBOOT is not set" @@ -769,7 +767,7 @@ if ! mkdir -p "$TARGET"; then exit 1 fi -$MAKE -C"${ROOT}" .xcompile || exit 1 +$MAKE -C"${ROOT}" UPDATED_SUBMODULES=1 .xcompile || exit 1 customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then @@ -823,7 +821,7 @@ build_targets() printf "%s" "$configoptions" > "$TMPCFG" $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" allnoconfig printf "%s" "$configoptions" >> "$TMPCFG" - yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig 2>/dev/null |head > /dev/null + yes "" 2>/dev/null | $MAKE -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" oldconfig BUILDPREFIX= if [ "$scanbuild" = "true" ]; then scanbuild_out=$TARGET/sharedutils-scanbuild @@ -852,6 +850,7 @@ build_targets() junit "" junit "" echo "Shared Utilities - Log: $TARGET/sharedutils/make.log" >> "$FAILED_BOARDS" + rm "$TMPCFG" return fi diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e9fd91bb40..8f4208c354 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -1,16 +1,18 @@ -#***************************************************************************** -# -# All rights reserved. -# # SPDX-License-Identifier: BSD-3-Clause -#***************************************************************************** HOSTCC ?= cc -amdfwtool_exe : amdfwtool.c - $(HOSTCC) amdfwtool.c -o amdfwtool +SRC = amdfwtool.c +OBJ = $(SRC:%.c=%.o) +TARGET = amdfwtool +CFLAGS=-O2 -Wall -Wextra -Wshadow -amdfwtool : amdfwtool_exe + +$(TARGET): $(OBJ) + $(CC) $(OBJ) $(LDFLAGS) -o $@ + +%.o: %.c $(HEADER) + $(CC) $(CFLAGS) -c -o $@ $< clean: - @rm -f amdfwtool.o amdfwtool amdfwtool.exe + @rm -f $(TARGET) $(OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc new file mode 100644 index 0000000000..b1a21308fd --- /dev/null +++ b/util/amdfwtool/Makefile.inc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: BSD-3-Clause + +amdfwtoolobj = amdfwtool.o + +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow + +$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) + $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) + printf " AMDFWTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110856..f5030d381c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -57,10 +57,6 @@ #include #include -#ifndef CONFIG_ROM_SIZE -#define CONFIG_ROM_SIZE 0x400000 -#endif - #define AMD_ROMSIG_OFFSET 0x20000 #define MIN_ROM_KB 256 @@ -215,7 +211,31 @@ static void usage(void) printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("-C | --soc-name Specify SOC name. Supported names are\n"); + printf(" Stoneyridge, Raven, Picasso, Renoir or Lucienne"); printf("-h | --help show this help\n"); + printf("\nEmbedded Firmware Structure options used by the PSP:\n"); + printf("--spi-speed SPI fast speed to place in EFS Table\n"); + printf(" 0x0 66.66Mhz\n"); + printf(" 0x1 33.33MHz\n"); + printf(" 0x2 22.22MHz\n"); + printf(" 0x3 16.66MHz\n"); + printf(" 0x4 100MHz\n"); + printf(" 0x5 800KHz\n"); + printf("--spi-read-mode SPI read mode to place in EFS Table\n"); + printf(" 0x0 Normal Read (up to 33M)\n"); + printf(" 0x1 Reserved\n"); + printf(" 0x2 Dual IO (1-1-2)\n"); + printf(" 0x3 Quad IO (1-1-4)\n"); + printf(" 0x4 Dual IO (1-2-2)\n"); + printf(" 0x5 Quad IO (1-4-4)\n"); + printf(" 0x6 Normal Read (up to 66M)\n"); + printf(" 0x7 Fast Read\n"); + printf("--spi-micron-flag Micron SPI part support for RV and later SOC\n"); + printf(" 0x0 Micron parts are not used\n"); + printf(" 0x1 Micron parts are always used\n"); + printf(" 0x2 Micron parts optional, this option is only\n"); + printf(" supported with RN/LCN SOC\n"); } typedef enum _amd_bios_type { @@ -284,6 +304,7 @@ typedef enum _amd_fw_type { AMD_FW_PSP_WHITELIST = 0x3a, AMD_FW_L2_PTR = 0x40, AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, @@ -340,6 +361,7 @@ static amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, + { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, }; @@ -413,7 +435,26 @@ typedef struct _embedded_firmware { uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t reserved[0x2c]; /* 0x24 - 0x4f */ + uint32_t second_gen_efs; + uint32_t bios3_entry; + uint32_t reserved_2Ch; + uint32_t promontory_fw_ptr; + uint32_t lp_promontory_fw_ptr; + uint32_t reserved_38h; + uint32_t reserved_3Ch; + uint8_t spi_readmode_f15_mod_60_6f; + uint8_t fast_speed_new_f15_mod_60_6f; + uint8_t reserved_42h; + uint8_t spi_readmode_f17_mod_00_2f; + uint8_t spi_fastspeed_f17_mod_00_2f; + uint8_t qpr_dummy_cycle_f17_mod_00_2f; + uint8_t reserved_46h; + uint8_t spi_readmode_f17_mod_30_3f; + uint8_t spi_fastspeed_f17_mod_30_3f; + uint8_t micron_detect_f17_mod_30_3f; + uint8_t reserved_4Ah; + uint8_t reserved_4Bh; + uint32_t reserved_4Ch; } __attribute__((packed, aligned(16))) embedded_firmware; typedef struct _psp_directory_header { @@ -601,7 +642,7 @@ static ssize_t copy_blob(void *dest, const char *src_file, size_t room) return -2; } - if (fd_stat.st_size > room) { + if ((size_t)fd_stat.st_size > room) { printf("Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; @@ -622,7 +663,7 @@ static void integrate_firmwares(context *ctx, amd_fw_entry *fw_table) { ssize_t bytes; - int i; + uint32_t i; ctx->current += sizeof(embedded_firmware); ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); @@ -796,7 +837,7 @@ static void *new_bios_dir(context *ctx, int multi) static int locate_bdt2_bios(bios_directory_table *level2, uint64_t *source, uint32_t *size) { - int i; + uint32_t i; *source = 0; *size = 0; @@ -845,6 +886,8 @@ static void integrate_bios_firmwares(context *ctx, unsigned int i, count; int level; int apob_idx; + uint32_t size; + uint64_t source; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -875,26 +918,19 @@ static void integrate_bios_firmwares(context *ctx, /* BIOS Directory items may have additional requirements */ - /* APOB_NV must have a size if it has a source */ - if (fw_table[i].type == AMD_BIOS_APOB_NV && fw_table[i].src) { - if (!fw_table[i].size) { + /* Check APOB_NV requirements */ + if (fw_table[i].type == AMD_BIOS_APOB_NV) { + if (!fw_table[i].size && !fw_table[i].src) + continue; /* APOB_NV not used */ + if (fw_table[i].src && !fw_table[i].size) { printf("Error: APOB NV address provided, but no size\n"); free(ctx->rom); exit(1); } - } - /* APOB_NV needs a size, else no choice but to skip the item */ - if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size) { - /* Attempt to determine whether this is an error */ + /* If the APOB isn't used, APOB_NV isn't used either */ apob_idx = find_bios_entry(AMD_BIOS_APOB); - if (apob_idx < 0 || !fw_table[apob_idx].dest) { - /* APOV NV not expected to be used */ - continue; - } else { - printf("Error: APOB NV must have a size\n"); - free(ctx->rom); - exit(1); - } + if (apob_idx < 0 || !fw_table[apob_idx].dest) + continue; /* APOV NV not supported */ } /* APOB_DATA needs destination */ @@ -960,10 +996,11 @@ static void integrate_bios_firmwares(context *ctx, break; case AMD_BIOS_BIN: /* Don't make a 2nd copy, point to the same one */ - if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, - &biosdir->entries[count].source, - &biosdir->entries[count].size)) + if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { + biosdir->entries[count].source = source; + biosdir->entries[count].size = size; break; + } /* level 2, or level 1 and no copy found in level 2 */ biosdir->entries[count].source = fw_table[i].src; @@ -1038,8 +1075,16 @@ static void integrate_bios_firmwares(context *ctx, fill_dir_header(biosdir, count, cookie); } -// Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; + +enum { + /* begin after ASCII characters */ + LONGOPT_SPI_READ_MODE = 256, + LONGOPT_SPI_SPEED = 257, + LONGOPT_SPI_MICRON_FLAG = 258, +}; + +// Unused values: D +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1072,6 +1117,7 @@ static struct option long_options[] = { {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, {"verstage", required_argument, 0, 'Z' }, + {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ {"instance", required_argument, 0, 'I' }, {"apcb", required_argument, 0, 'a' }, @@ -1086,6 +1132,10 @@ static struct option long_options[] = { {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + /* Embedded Firmware Structure items*/ + {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, + {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, + {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, /* other */ {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, @@ -1093,13 +1143,14 @@ static struct option long_options[] = { {"anywhere", no_argument, 0, 'q' }, {"sharedmem", required_argument, 0, 'R' }, {"sharedmem-size", required_argument, 0, 'P' }, + {"soc-name", required_argument, 0, 'C' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } }; static void register_fw_fuse(char *str) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) @@ -1112,7 +1163,7 @@ static void register_fw_fuse(char *str) static void register_fw_token_unlock(void) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) @@ -1147,7 +1198,7 @@ static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { if (amd_bios_table[i].type == type @@ -1162,7 +1213,7 @@ static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) static void register_fw_addr(amd_bios_type type, char *src_str, char *dst_str, char *size_str) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { if (amd_bios_table[i].type != type) continue; @@ -1178,6 +1229,91 @@ static void register_fw_addr(amd_bios_type type, char *src_str, } } +enum platform { + PLATFORM_UNKNOWN, + PLATFORM_STONEYRIDGE, + PLATFORM_RAVEN, + PLATFORM_PICASSO, + PLATFORM_RENOIR, + PLATFORM_LUCIENNE, +}; + +static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, + uint8_t efs_spi_readmode, uint8_t efs_spi_speed, + uint8_t efs_spi_micron_flag) +{ + if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { + printf("Error: EFS read mode and SPI speed must be set\n"); + return 1; + } + switch (soc_id) { + case PLATFORM_STONEYRIDGE: + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; + amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; + break; + case PLATFORM_RAVEN: + case PLATFORM_PICASSO: + amd_romsig->second_gen_efs = 0; + amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; + switch (efs_spi_micron_flag) { + case 0: + amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff; + break; + case 1: + amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; + break; + default: + printf("Error: EFS Micron flag must be correctly set.\n\n"); + return 1; + } + break; + case PLATFORM_RENOIR: + case PLATFORM_LUCIENNE: + amd_romsig->second_gen_efs = 1; + amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; + amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; + switch (efs_spi_micron_flag) { + case 0: + amd_romsig->micron_detect_f17_mod_30_3f = 0xff; + break; + case 1: + amd_romsig->micron_detect_f17_mod_30_3f = 0xaa; + break; + case 2: + amd_romsig->micron_detect_f17_mod_30_3f = 0x55; + break; + default: + printf("Error: EFS Micron flag must be correctly set.\n\n"); + return 1; + } + break; + case PLATFORM_UNKNOWN: + default: + printf("Error: Invalid SOC name.\n\n"); + return 1; + } + return 0; +} + +static int identify_platform(char *soc_name) +{ + if (!strcasecmp(soc_name, "Stoneyridge")) + return PLATFORM_STONEYRIDGE; + else if (!strcasecmp(soc_name, "Raven")) + return PLATFORM_RAVEN; + else if (!strcasecmp(soc_name, "Picasso")) + return PLATFORM_PICASSO; + else if (!strcasecmp(soc_name, "Renoir")) + return PLATFORM_RENOIR; + else if (!strcasecmp(soc_name, "Lucienne")) + return PLATFORM_LUCIENNE; + else + return PLATFORM_UNKNOWN; + +} + int main(int argc, char **argv) { int c; @@ -1190,9 +1326,7 @@ int main(int argc, char **argv) int fuse_defined = 0; int targetfd; char *output = NULL; - context ctx = { - .rom_size = CONFIG_ROM_SIZE, - }; + context ctx = { 0 }; /* Values cleared after each firmware or parameter, regardless if N/A */ uint8_t sub = 0, instance = 0; int abl_image = 0; @@ -1200,6 +1334,11 @@ int main(int argc, char **argv) bool any_location = 0; uint32_t romsig_offset; uint32_t rom_base_address; + uint8_t soc_id = PLATFORM_UNKNOWN; + uint8_t efs_spi_readmode = 0xff; + uint8_t efs_spi_speed = 0xff; + uint8_t efs_spi_micron_flag = 0xff; + int multi = 0; while (1) { @@ -1394,6 +1533,30 @@ int main(int argc, char **argv) register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'E': + register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + sub = instance = 0; + break; + case 'C': + soc_id = identify_platform(optarg); + if (soc_id == PLATFORM_UNKNOWN) { + printf("Error: Invalid SOC name specified\n\n"); + retval = 1; + } + sub = instance = 0; + break; + case LONGOPT_SPI_READ_MODE: + efs_spi_readmode = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_SPEED: + efs_spi_speed = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; + case LONGOPT_SPI_MICRON_FLAG: + efs_spi_micron_flag = strtoull(optarg, NULL, 16); + sub = instance = 0; + break; case 'o': output = optarg; break; @@ -1512,6 +1675,17 @@ int main(int argc, char **argv) amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; + if (soc_id != PLATFORM_UNKNOWN) { + retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, + efs_spi_speed, efs_spi_micron_flag); + if (retval) { + printf("ERROR: Failed to initialize EFS table!\n"); + return retval; + } + } else { + printf("WARNING: No SOC name specified.\n"); + } + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ @@ -1573,7 +1747,12 @@ int main(int argc, char **argv) targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { - write(targetfd, amd_romsig, ctx.current - romsig_offset); + ssize_t bytes; + bytes = write(targetfd, amd_romsig, ctx.current - romsig_offset); + if (bytes != ctx.current - romsig_offset) { + fprintf(stderr, "Error: Writing to file %s failed\n", output); + retval = 1; + } close(targetfd); } else { printf("Error: could not open file: %s\n", output); diff --git a/util/apcb/apcb_edit.py b/util/apcb/apcb_edit.py index e5dd0cd586..599ef35d16 100755 --- a/util/apcb/apcb_edit.py +++ b/util/apcb/apcb_edit.py @@ -40,24 +40,28 @@ def parseargs(): help='APCB output file') parser.add_argument( '--spd_0_0', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 0, dimm 0') parser.add_argument( '--spd_0_1', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 0, dimm 1') parser.add_argument( '--spd_1_0', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 1, dimm 0') parser.add_argument( '--spd_1_1', - type=argparse.FileType('r'), + type=argparse.FileType('rb'), help='SPD input file for channel 1, dimm 1') parser.add_argument( '--hex', action='store_true', help='SPD input file is hex encoded, binary otherwise') + parser.add_argument( + '--strip_manufacturer_information', + action='store_true', + help='Strip all manufacturer information from SPD') parser.add_argument( '--board_id_gpio0', type=int, @@ -99,7 +103,7 @@ def inject(orig, insert, offset): def main(): args = parseargs() - print("Reading input APCB from %s\n" % (args.apcb_in.name)) + print("Reading input APCB from %s" % (args.apcb_in.name)) apcb = args.apcb_in.read() @@ -107,10 +111,10 @@ def main(): gpio_offset = apcb.find(GPIO_MAGIC) assert gpio_offset > 0, "GPIO magic number not found" - print('GPIO magic number found at offset 0x%x\n' % gpio_offset) + print('GPIO magic number found at offset 0x%x' % gpio_offset) gpio_array = (args.board_id_gpio0 + args.board_id_gpio1 + args.board_id_gpio2 + args.board_id_gpio3) - print('Writing SPD GPIO array %s\n' % gpio_array) + print('Writing SPD GPIO array %s' % gpio_array) apcb = inject(apcb, pack('BBBBBBBBBBBB', *gpio_array), gpio_offset) spd_offset = 0 @@ -130,7 +134,7 @@ def main(): "Unexpected channel number found in APCB" print("Found SPD magic number with channel %d and dimm %d " - "at offset 0x%x\n" % (spd_ssp.ChannelNumber, spd_ssp.DimmNumber, + "at offset 0x%x" % (spd_ssp.ChannelNumber, spd_ssp.DimmNumber, spd_offset)) dimm_channel = (spd_ssp.ChannelNumber, spd_ssp.DimmNumber) @@ -146,21 +150,27 @@ def main(): if spd: if args.hex: + spd = spd.decode() spd = re.sub(r'#.*', '', spd) spd = re.sub(r'\s+', '', spd) spd = bytes.fromhex(spd) - else: - spd = spd.encode() assert len(spd) == 512, \ "Expected SPD to be 512 bytes, got %d" % len(spd) - print("Enabling channel %d, dimm %d and injecting SPD\n" % + if args.strip_manufacturer_information: + print("Stripping manufacturer information from SPD") + spd = spd[0:320] + b'\x00'*64 + spd[320+64:] + + assert len(spd) == 512, \ + "Error while stripping SPD manufacurer information" + + print("Enabling channel %d, dimm %d and injecting SPD" % (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) spd_ssp = spd_ssp._replace(SpdValid=True, DimmPresent=True) else: - print("Disabling channel %d, dimm %d and clearing SPD\n" % + print("Disabling channel %d, dimm %d and clearing SPD" % (spd_ssp.ChannelNumber, spd_ssp.DimmNumber)) spd_ssp = spd_ssp._replace(SpdValid=False, DimmPresent=False) spd = EMPTY_SPD @@ -170,7 +180,7 @@ def main(): spd_offset += 512 - print("Fixing checksum and writing to %s\n" % (args.apcb_out.name)) + print("Fixing checksum and writing to %s" % (args.apcb_out.name)) apcb = inject(apcb, bytes([chksum(apcb)]), 16) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 1440abc236..5d943e43fe 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -294,8 +294,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { sb := Create(ctx, "early_init.c") defer sb.Close() Add_gpl(sb) - sb.WriteString(` + sb.WriteString(` #include #include #include @@ -364,18 +364,12 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) /* FIXME: check this function. */ void acpi_create_gnvs(struct global_nvs *gnvs) { - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* The lid is open by default. */ gnvs->lids = 1; + /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ gnvs->tpsv = 90; } `) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 3113a33fbc..6851d6d1ed 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -112,7 +112,7 @@ static void mainboard_smi_handle_ec_sci(void) return; event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); + printk(BIOS_DEBUG, "EC event %#02x\n", event); } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/util/autoport/main.go b/util/autoport/main.go index b2334e2b62..1a9050abd8 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -104,7 +104,6 @@ var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} var KconfigBool map[string]bool = map[string]bool{} var KconfigComment map[string]string = map[string]string{} var KconfigString map[string]string = map[string]string{} -var KconfigStringUnquoted map[string]string = map[string]string{} var KconfigHex map[string]uint32 = map[string]uint32{} var KconfigInt map[string]int = map[string]int{} var ROMSizeKB = 0 @@ -570,21 +569,6 @@ config %s%s `, name, makeComment(name)) } - keys = nil - for name, _ := range KconfigStringUnquoted { - keys = append(keys, name) - } - - sort.Strings(keys) - - for _, name := range keys { - fmt.Fprintf(kc, ` -config %s%s - string - default %s -`, name, makeComment(name), KconfigStringUnquoted[name]) - } - keys = nil for name, _ := range KconfigString { keys = append(keys, name) @@ -730,7 +714,7 @@ func main() { ctx.MoboID = ctx.SaneVendor + "/" + sanitize(ctx.Model) ctx.KconfigName = "BOARD_" + strings.ToUpper(ctx.SaneVendor+"_"+sanitize(ctx.Model)) ctx.BaseDirectory = *FlagOutDir + MoboDir + ctx.MoboID - KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_DIR"] = ctx.MoboID KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model os.MkdirAll(ctx.BaseDirectory, 0700) diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 1b3e93643e..f568e67461 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -19,6 +19,13 @@ gen-gbe-ich9m: cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin +# Use this target to generate GbE for X220/x230 +gen-gbe-82579LM: + ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + # Use this target to generate IFD for X200 gen-ifd-x200: ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin diff --git a/util/bincfg/gbe-82579LM.set b/util/bincfg/gbe-82579LM.set new file mode 100644 index 0000000000..01ae47023e --- /dev/null +++ b/util/bincfg/gbe-82579LM.set @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# Naming convention +# * Word groups separated by a blank line +# * Word groups with known meaning given a prefix +# * prefix will be defined in comment before group +# * Variable names to be named using a prefix, descriptive name and bit offset +# within the word, separated by an underscore. +# * Example: "prefix_description_0" +# * Unidentified reserved word groups will be named reserved and LAN Word +# * EXCEPTION: Word 0x24, Word 0x25, Word 0x26 also include bit offset +# within the word +# Offset hex address, separated by an underscore. +# * Example: "reserved_x03" +# * Nonprefixed names will be named reserved and LAN Word Offset hex address, +# separated by an underscore. +# * Example: "imageversioninfo_x05" +# * Unspecified words are prefixed with "offset_" + +# GbE values for 82579LM +{ + # This example sets MAC address to 00:DE:AD:C0:FF:EE + # USE YOUR DEVICES MAC ADDRESS!! + # prefix: "mac_" + "mac_address_0" = 0x00, + "mac_address_1" = 0xDE, + "mac_address_2" = 0xAD, + "mac_address_3" = 0xC0, + "mac_address_4" = 0xFF, + "mac_address_5" = 0xEE, + + # Reserved (Word 0x3) + "reserved_x03" = 0x0800, + + # Reserved (Word 0x04) + "reserved_x04" = 0xffff, + + # Image Version Information (Word 0x05) + "imageversioninfo_x05" = 0x00D3, + + "reserved_x06" = 0xffff, + "reserved_x07" = 0xffff, + + # PBA Low and PBA High (Words 0x08 and 0x09) + # prefix: "pba_" + "pba_low_x08" = 0xffff, + "pba_high_x09" = 0xffff, + + # PCI Init Control Word (Word 0x0A) + # prefix: "pci_" + "pci_loaddeviceid_0" = 1, + "pci_loadsubsystemid_1" = 1, + "pci_reserved_2" = 0, + "pci_reserved_3" = 0x0, + "pci_pmenable_6" = 1, + "pci_auxpwr_7" = 1, + "pci_reserved_8" = 0x10, + + # ************* Configurable PCI IDs **************** + # TODO: make command line switch for these + # Subsystem ID (Word 0x0B) + "subsystemid_x0B" = 0, + # Subsystem Vendor ID (Word 0x0C) + "subsystemvendorid_x0C" = 0x8086, + # Device ID (Word 0x0D) + # TODO: 82579V uses "deviceid_x0D" = 0x1503, + "deviceid_x0D" = 0x1502, + # ************* END Configurable PCI IDs **************** + + # Words 0x0E and 0x0F Are Reserved + "reserved_x0E" = 0x0, + "reserved_x0F" = 0x0, + + # LAN Power Consumption (Word 0x10) + # prefix: "lanpwr_" + "lanpwr_d3pwr_0" = 0x2, + "lanpwr_reserved_5" = 0, + "lanpwr_d0pwr_8" = 0x7, + + # Word 0x12 and Word 0x11 Are Reserved + "reserved_x11" = 0x0000, + "reserved_x12" = 0x0000, + + # Shared Init Control Word (Word 0x13) + # prefix: "sicw_" + "sicw_dynamicclock_0" = 1, + "sicw_clkcnt_1" = 0, + "sicw_reserved_2" = 1, + "sicw_fullduplex_3" = 0, + "sicw_forcespeed_4" = 0, + "sicw_reserved_5" = 0, + "sicw_phydeviceype_6" = 0, + "sicw_reserved_8" = 1, + "sicw_phy_enpwrdown_9" = 0, + "sicw_reserved_10" = 1, + "sicw_macsecdisable_13" = 1, + "sicw_sign_14" = 0x2, + + # Extended Configuration Word 1 (Word 0x14) + # prefix: "ecw1_" + "ecw1_extcfgptr_0" = 0x0028, + "ecw1_oemload_12" = 1, + "ecw1_phyload_13" = 1, + "ecw1_reserved_14" = 0, + + # Extended Configuration Word 2 (Word 0x15) + # prefix: "ecw2_" + "ecw2_reserved_0" = 0x00, + "ecw2_extphylen_8" = 0x12, + + # Extended Configuration Word 3 (Word 0x16) + # prefix: "ecw3_" + "ecw3_extcfg1_0" = 0x00, + + # OEM Configuration Defaults (Word 0x17) + # prefix: "oem_" + "oem_reserved_0" = 0x000, + "oem_lpluenind0a_9" = 0, + "oem_lplueninnond0a_10" = 1, + "oem_gbedisinnond0a_11" = 1, + "oem_reserved_12" = 0, + "oem_gbedis_14" = 0, + "oem_reserved_15" = 0, + + # LED 0 - 2 Configuration Defaults (Word 0x18) + # prefix: "l02_" + # Lenovo default values + "l02_led0mode_0" = 0x4, + "l02_led0invert_3" = 0, + "l02_led0blink_4" = 0, + "l02_led1mode_5" = 0x3, + "l02_led1invert_8" = 0, + "l02_led1blink_9" = 1, + "l02_led2mode_10" = 0x2, + "l02_led2invert_13" = 1, + "l02_led2blink_14" = 0, + "l02_blinkrate_15" = 0, + + # Intel default Values + #"l02_led0mode_0" = 0x4, + #"l02_led0invert_3" = 0, + #"l02_led0blink_4" = 1, + #"l02_led1mode_5" = 0x7, + #"l02_led1invert_8" = 0, + #"l02_led1blink_9" = 0, + #"l02_led2mode_10" = 0x6, + #"l02_led2invert_13" = 0, + #"l02_led2blink_14" = 0, + #"l02_blinkrate_15" = 0, + + + # Reserved (Word 0x19) + # NOTE: bit 6 must be 1 for validation. See datasheet. + "reserved_x19" = 0x2B40, + + # Reserved (Word 0x1A) + # Advanced Power Management Wake Up Enable + # prefix: "amp_" + "amp_enable_0" = 1, + "amp_reserved_1" = 0x0421, + + # Reserved (Word 0x1B) + "reserved_x1B" = 0x0113, + + # Reserved (Word 0x1C) + "reserved_x1C" = 0x1502, + + # Reserved (Word 0x1D) + "reserved_x1D" = 0xBAAD, + + # Reserved (Word 0x1E) + "reserved_x1E" = 0x1502, + + # Reserved (Word 0x1F) + "reserved_x1F" = 0x1503, + + # Reserved (Word 0x20) + "reserved_x20" = 0xBAAD, + + # Reserved (Word 0x21) + "reserved_x21" = 0xBAAD, + + # Reserved (Word 0x22) + "reserved_x22" = 0xBAAD, + + # Reserved (Word 0x23) + "reserved_x23" = 0x1502, + + # Reserved (Word 0x24) + "reserved_x24_0" = 0x0000, + "reserved_x24_14" = 0, + "reserved_x24_15" = 1, + + # Reserved (Word 0x25) + "reserved_x25_0" = 0x0000, + "reserved_x25_4" = 1, + "reserved_x25_5" = 0, + "reserved_x25_7" = 1, + "reserved_x25_8" = 0x00, + "reserved_x25_15" = 1, + + # Reserved (Word 0x26) + "reserved_x26_0" = 0x00, + "reserved_x26_9" = 1, + "reserved_x26_10" = 1, + "reserved_x26_11" = 1, + "reserved_x26_12" = 0, + "reserved_x26_14" = 1, + "reserved_x26_15" = 0, + + # Reserved (Word 0x27) + "reserved_x27" = 0x80, + + # Offsets 0x28-0x2F + "offset_x28" = 0x0000, + "offset_x29" = 0x0000, + "offset_x2A" = 0x0000, + "offset_x2B" = 0x0000, + "offset_x2C" = 0x0000, + "offset_x2D" = 0x0000, + "offset_x2E" = 0x0000, + "offset_x2F" = 0x0000, + + # Boot Agent Main Setup Options (Word 0x30) + # Hardcoded PXE setup (disabled) + # prefix: "pxe30_" + "pxe30_protocolsel_0" = 0, + "pxe30_reserved_2" = 0, + "pxe30_defbootsel_3" = 0x3, + "pxe30_reserved_5" = 0, + "pxe30_prompttime_6" = 0x3, + "pxe30_dispsetup_8" = 0, + "pxe30_reserved_9" = 0, + "pxe30_forcespeed_10" = 0, + "pxe30_forcefullduplex_12" = 0, + "pxe30_reserved_13" = 0, + "pxe30_reserved_14" = 0, + + # Boot Agent Configuration Customization Options (Word 0x31) + # prefix: "pxe31_" + "pxe31_disablemenu_0" = 1, + "pxe31_disabletitle_1" = 1, + "pxe31_disableprotsel_2" = 0, + "pxe31_disbootorder_3" = 0, + "pxe31_dislegacywak_4" = 0, + "pxe31_disableflasicwpro_5" = 0, + "pxe31_reserved_6" = 0, + "pxe31_ibootagentmode_8" = 0, + "pxe31_contretrydis_11" = 0, + "pxe31_reserved_12" = 0, + "pxe31_signature_14" = 10, + + # Boot Agent Configuration Customization Options (Word 0x32) + # prefix: "pxe32_" + "pxe32_buildnum_0" = 0x28, + "pxe32_minorversion_8" = 0x2, + "pxe32_majorversion_12" = 0x1, + + # IBA Capabilities (Word 0x33) + # prefix: "pxe33_" + "pxe33_basecodepresent_0" = 1, + "pxe33_undipresent_1" = 1, + "pxe33_reserved_2" = 1, + "pxe33_efiundipresent_3" = 0, + "pxe33_iscsi_4" = 0, + "pxe33_reserved_5" = 0, + "pxe33_signature_14" = 10, + + "pxe_padding"[11] = 0xffff, + + # Checksum is generated by bincfg + # "checksum_gbe" = xxx, + + # G3 -> S5 PHY Configuration + "g3_s5_phy_conf"[0x16] = 0, + + # Padding 0xf80 bytes + "padding"[0xf6a] = 0xff +} diff --git a/util/bincfg/gbe-82579LM.spec b/util/bincfg/gbe-82579LM.spec new file mode 100644 index 0000000000..0367aff024 --- /dev/null +++ b/util/bincfg/gbe-82579LM.spec @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-3.0-or-later +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# GbE SPEC for 82579LM/82579V +{ + "mac_address_"[6] : 8, + "reserved_x03" : 16, + "reserved_x04" : 16, + "imageversioninfo_x05" : 16, + "reserved_x06" : 16, + "reserved_x07" : 16, + "pba_low_x08" : 16, + "pba_high_x09" : 16, + "pci_loaddeviceid_0" : 1, + "pci_loadsubsystemid_1" : 1, + "pci_reserved_2" : 1, + "pci_reserved_3" : 3, + "pci_pmenable_6" : 1, + "pci_auxpwr_7" : 1, + "pci_reserved_8" : 8, + "subsystemid_x0B" : 16, + "subsystemvendorid_x0C" : 16, + "deviceid_x0D" : 16, + "reserved_x0E" : 16, + "reserved_x0F" : 16, + "lanpwr_d3pwr_0" : 5, + "lanpwr_reserved_5" : 3, + "lanpwr_d0pwr_8" : 8, + "reserved_x11" : 16, + "reserved_x12" : 16, + "sicw_dynamicclock_0" : 1, + "sicw_clkcnt_1" : 1, + "sicw_reserved_2" : 1, + "sicw_fullduplex_3" : 1, + "sicw_forcespeed_4" : 1, + "sicw_reserved_5" : 1, + "sicw_phydeviceype_6" : 2, + "sicw_reserved_8" : 1, + "sicw_phy_enpwrdown_9" : 1, + "sicw_reserved_10" : 3, + "sicw_macsecdisable_13" : 1, + "sicw_sign_14" : 2, + "ecw1_extcfgptr_0" : 12, + "ecw1_oemload_12" : 1, + "ecw1_phyload_13" : 1, + "ecw1_reserved_14" : 2, + "ecw2_reserved_0" : 8, + "ecw2_extphylen_8" : 8, + "ecw3_extcfg1_0" : 16, + "oem_reserved_0" : 9, + "oem_lpluenind0a_9" : 1, + "oem_lplueninnond0a_10" : 1, + "oem_gbedisinnond0a_11" : 1, + "oem_reserved_12" : 2, + "oem_gbedis_14" : 1, + "oem_reserved_15" : 1, + "l02_led0mode_0" : 3, + "l02_led0invert_3" : 1, + "l02_led0blink_4" : 1, + "l02_led1mode_5" : 3, + "l02_led1invert_8" : 1, + "l02_led1blink_9" : 1, + "l02_led2mode_10" : 3, + "l02_led2invert_13" : 1, + "l02_led2blink_14" : 1, + "l02_blinkrate_15" : 1, + "reserved_x19" : 16, + "amp_enable_0" : 1, + "amp_reserved_1" : 15, + "reserved_x1B" : 16, + "reserved_x1C" : 16, + "reserved_x1D" : 16, + "reserved_x1E" : 16, + "reserved_x1F" : 16, + "reserved_x20" : 16, + "reserved_x21" : 16, + "reserved_x22" : 16, + "reserved_x23" : 16, + "reserved_x24_0" : 14, + "reserved_x24_14" : 1, + "reserved_x24_15" : 1, + "reserved_x25_0" : 4, + "reserved_x25_4" : 1, + "reserved_x25_5" : 2, + "reserved_x25_7" : 1, + "reserved_x25_8" : 7, + "reserved_x25_15" : 1, + "reserved_x26_0" : 9, + "reserved_x26_9" : 1, + "reserved_x26_10" : 1, + "reserved_x26_11" : 1, + "reserved_x26_12" : 2, + "reserved_x26_14" : 1, + "reserved_x26_15" : 1, + "reserved_x27" : 16, + "offset_x28" : 16, + "offset_x29" : 16, + "offset_x2A" : 16, + "offset_x2B" : 16, + "offset_x2C" : 16, + "offset_x2D" : 16, + "offset_x2E" : 16, + "offset_x2F" : 16, + "pxe30_protocolsel_0" : 2, + "pxe30_reserved_2" : 1, + "pxe30_defbootsel_3" : 2, + "pxe30_reserved_5" : 1, + "pxe30_prompttime_6" : 2, + "pxe30_dispsetup_8" : 1, + "pxe30_reserved_9" : 1, + "pxe30_forcespeed_10" : 2, + "pxe30_forcefullduplex_12" : 1, + "pxe30_reserved_13" : 1, + "pxe30_reserved_14" : 2, + "pxe31_disablemenu_0" : 1, + "pxe31_disabletitle_1" : 1, + "pxe31_disableprotsel_2" : 1, + "pxe31_disbootorder_3" : 1, + "pxe31_dislegacywak_4" : 1, + "pxe31_disableflasicwpro_5" : 1, + "pxe31_reserved_6" : 2, + "pxe31_ibootagentmode_8" : 3, + "pxe31_contretrydis_11" : 1, + "pxe31_reserved_12" : 2, + "pxe31_signature_14" : 2, + "pxe32_buildnum_0" : 8, + "pxe32_minorversion_8" : 4, + "pxe32_majorversion_12" : 4, + "pxe33_basecodepresent_0" : 1, + "pxe33_undipresent_1" : 1, + "pxe33_reserved_2" : 1, + "pxe33_efiundipresent_3" : 1, + "pxe33_iscsi_4" : 1, + "pxe33_reserved_5" : 9, + "pxe33_signature_14" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "g3_s5_phy_conf"[0x16] : 8, + "padding"[0xf6a] : 8 +} diff --git a/util/cbfstool/fmaptool.c b/util/cbfstool/fmaptool.c index aace5aea33..9f5803d8ee 100644 --- a/util/cbfstool/fmaptool.c +++ b/util/cbfstool/fmaptool.c @@ -71,6 +71,29 @@ static void list_cbfs_section_names(FILE *out) fputc('\n', out); } +static void write_header_fmap_sections(FILE *header, const struct flashmap_descriptor *root, + unsigned int offset) +{ + assert(root); + /* + * The offset may only be unknown for the root node in a system where the flash isn't + * memory-mapped. + */ + if (!root->offset_known && offset != 0) + return; + + const unsigned int current_offset = offset + (root->offset_known ? root->offset : 0); + fprintf(header, "#define FMAP_SECTION_%s_START %#x\n", root->name, current_offset); + + if (!root->size_known) + return; + + fprintf(header, "#define FMAP_SECTION_%s_SIZE %#x\n", root->name, root->size); + + fmd_foreach_child(child, root) + write_header_fmap_sections(header, child, current_offset); +} + static bool write_header(const char *out_fname, const struct flashmap_descriptor *root, const int fmap_size) @@ -93,6 +116,9 @@ static bool write_header(const char *out_fname, fprintf(header, "#define %s %#x\n", HEADER_FMAP_OFFSET, fmap_offset); fprintf(header, "#define %s %#x\n\n", HEADER_FMAP_SIZE, fmap_size); + write_header_fmap_sections(header, root, 0); + fputs("\n", header); + fputs("#endif\n", header); fclose(header); diff --git a/util/cbfstool/fmd.h b/util/cbfstool/fmd.h index 8dfcb3c964..18463ff6d1 100644 --- a/util/cbfstool/fmd.h +++ b/util/cbfstool/fmd.h @@ -19,8 +19,8 @@ */ union flashmap_flags { struct { - int cbfs: 1; /* The section contains a CBFS area. */ - int preserve: 1; /* Preserve the section before update. */ + unsigned int cbfs: 1; /* The section contains a CBFS area. */ + unsigned int preserve: 1; /* Preserve the section before update. */ } f; int v; }; diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 34e79d368d..3a94f3e672 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -782,7 +782,8 @@ static void dump_console(int one_boot_only) #define BANNER_REGEX(stage) \ "\n\ncoreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" #define OVERFLOW_REGEX(stage) "\n\\*\\*\\* Pre-CBMEM " stage " console overflow" - const char *regex[] = { BANNER_REGEX("bootblock"), + const char *regex[] = { BANNER_REGEX("verstage-before-bootblock"), + BANNER_REGEX("bootblock"), BANNER_REGEX("verstage"), OVERFLOW_REGEX("romstage"), BANNER_REGEX("romstage"), diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index dc59ce1ebc..d5cca6cd6e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -33,20 +33,20 @@ BOOTSTRAP=0 THREADS=1 # GCC toolchain version numbers -GMP_VERSION=6.1.2 -MPFR_VERSION=4.0.2 -MPC_VERSION=1.1.0 +GMP_VERSION=6.2.0 +MPFR_VERSION=4.1.0 +MPC_VERSION=1.2.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.33.1 +BINUTILS_VERSION=2.35 GDB_VERSION=9.2 -IASL_VERSION=20200528 -PYTHON_VERSION=3.8.1 +IASL_VERSION=20200717 +PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number -CLANG_VERSION=9.0.0 -CMAKE_VERSION=3.16.2 -NASM_VERSION=2.14.02 +CLANG_VERSION=10.0.1 +CMAKE_VERSION=3.18.1 +NASM_VERSION=2.15.03 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if @@ -62,16 +62,16 @@ IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION} PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz" EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2" # CLANG toolchain archive locations -LLVM_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" -CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" -CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz" -CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz" -CMAKE_ARCHIVE="https://cmake.org/files/v3.16/cmake-${CMAKE_VERSION}.tar.gz" +LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" +CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz" +CRT_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz" +CTE_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz" +CMAKE_ARCHIVE="https://cmake.org/files/v3.18/cmake-${CMAKE_VERSION}.tar.gz" NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ - $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CFE_ARCHIVE \ + $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CLANG_ARCHIVE \ $CRT_ARCHIVE $CTE_ARCHIVE $CMAKE_ARCHIVE $NASM_ARCHIVE" # GCC toolchain directories @@ -88,7 +88,7 @@ PYTHON_DIR="Python-${PYTHON_VERSION}" EXPAT_DIR="expat-${EXPAT_VERSION}" # CLANG toolchain directories LLVM_DIR="llvm-${CLANG_VERSION}.src" -CFE_DIR="cfe-${CLANG_VERSION}.src" +CLANG_DIR="clang-${CLANG_VERSION}.src" CRT_DIR="compiler-rt-${CLANG_VERSION}.src" CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" CMAKE_DIR="cmake-${CMAKE_VERSION}" @@ -851,7 +851,7 @@ build_IASL() { build_LLVM() { cd .. || exit 1 - ln -sf "$PWD/$CFE_DIR" "$LLVM_DIR/tools/clang" + ln -sf "$PWD/$CLANG_DIR" "$LLVM_DIR/tools/clang" ln -sf "$PWD/$CTE_DIR" "$LLVM_DIR/tools/clang/tools/extra" ln -sf "$PWD/$CRT_DIR" "$LLVM_DIR/projects/compiler-rt" cd - || exit 1 @@ -863,8 +863,8 @@ build_LLVM() { $MAKE $JOBS || touch .failed $MAKE install || touch .failed - cp -a ../$CFE_DIR/tools/scan-build/* "$DESTDIR$TARGETDIR/bin" - cp -a ../$CFE_DIR/tools/scan-view/* "$DESTDIR$TARGETDIR/bin" + cp -a ../$CLANG_DIR/tools/scan-build/* "$DESTDIR$TARGETDIR/bin" + cp -a ../$CLANG_DIR/tools/scan-view/* "$DESTDIR$TARGETDIR/bin" # create symlinks to work around broken --print-librt-file-name # when used with -target. @@ -1014,7 +1014,7 @@ case "$PACKAGE" in CLANG|clang) NAME="LLVM clang" LLVM_VERSION=${CLANG_VERSION} - PACKAGES="CMAKE LLVM CFE CRT CTE" + PACKAGES="CMAKE LLVM CLANG CRT CTE" CMAKE=${DESTDIR}${TARGETDIR}/bin/cmake ;; IASL|iasl) @@ -1217,7 +1217,7 @@ export PATH=$DESTDIR$TARGETDIR/bin:$PATH # Download, unpack, patch and build all packages -printf "Downloading and verifing tarballs ...\n" +printf "Downloading and verifying tarballs ...\n" mkdir -p tarballs for P in $PACKAGES; do download "$P" || exit "$?" diff --git a/util/crossgcc/patches/acpica-unix2-20200528_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20200528_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200717_iasl.patch index 3fac35d9d3..01dec7c4f3 100644 --- a/util/crossgcc/patches/acpica-unix2-20200528_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20200528_/source/compiler/asloptions.c acpica-unix2-20200528/source/compiler/asloptions.c > acpica-unix2-20200528_iasl.patch ---- acpica-unix2-20200528_/source/compiler/asloptions.c -+++ acpica-unix2-20200528/source/compiler/asloptions.c +diff -Naur acpica-unix2-20200717_/source/compiler/asloptions.c acpica-unix2-20200717/source/compiler/asloptions.c > acpica-unix2-20200717_iasl.patch +--- acpica-unix2-20200717_/source/compiler/asloptions.c ++++ acpica-unix2-20200717/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch b/util/crossgcc/patches/binutils-2.35_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.35_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.33.1_mips-gold.patch b/util/crossgcc/patches/binutils-2.35_mips-gold.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_mips-gold.patch rename to util/crossgcc/patches/binutils-2.35_mips-gold.patch diff --git a/util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch rename to util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch diff --git a/util/crossgcc/patches/binutils-2.35_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.35_no-makeinfo.patch new file mode 100644 index 0000000000..4834016c3b --- /dev/null +++ b/util/crossgcc/patches/binutils-2.35_no-makeinfo.patch @@ -0,0 +1,236 @@ +It fails to compile when using "MAKEINFO = @MAKEINFO@": +binutils-gdb/missing: 81: makeinfo: not found +WARNING: 'makeinfo' is missing on your system. + You should only need it if you modified a '.texi' file, or + any other file indirectly affecting the aspect of the manual. + You might want to install the Texinfo package: + + The spurious makeinfo call might also be the consequence of + using a buggy 'make' (AIX, DU, IRIX), in which case you might + want to install GNU make: + +make[4]: *** [Makefile:507: as.info] Error 127 + +Current patch will change that to "MAKEINFO = true" + +diff --git binutils-2.34/Makefile.in binutils-2.34/Makefile.in +index af38671cbe..978d445825 100644 +--- binutils-2.34/Makefile.in ++++ binutils-2.34/Makefile.in +@@ -370,7 +370,7 @@ YACC = @YACC@ + FLEX = @FLEX@ + LEX = @LEX@ + M4 = @M4@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + EXPECT = @EXPECT@ + RUNTEST = @RUNTEST@ + +diff --git binutils-2.34/Makefile.tpl binutils-2.34/Makefile.tpl +index 5b118a8ba4..2b41fa28ce 100644 +--- binutils-2.34/Makefile.tpl ++++ binutils-2.34/Makefile.tpl +@@ -373,7 +373,7 @@ YACC = @YACC@ + FLEX = @FLEX@ + LEX = @LEX@ + M4 = @M4@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + EXPECT = @EXPECT@ + RUNTEST = @RUNTEST@ + +diff --git binutils-2.34/bfd/Makefile.in binutils-2.34/bfd/Makefile.in +index 7d3b9c1c5a..c062314063 100644 +--- binutils-2.34/bfd/Makefile.in ++++ binutils-2.34/bfd/Makefile.in +@@ -342,7 +342,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/bfd/Makefile.in.orig binutils-2.34/bfd/Makefile.in.orig +index 78555ccbbc..861fc3570d 100644 +--- binutils-2.34/bfd/Makefile.in.orig ++++ binutils-2.34/bfd/Makefile.in.orig +@@ -342,7 +342,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/bfd/doc/Makefile.in binutils-2.34/bfd/doc/Makefile.in +index 2c1ddd45b8..b3972192e7 100644 +--- binutils-2.34/bfd/doc/Makefile.in ++++ binutils-2.34/bfd/doc/Makefile.in +@@ -284,7 +284,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/binutils/Makefile.in binutils-2.34/binutils/Makefile.in +index 39f08563f9..91d2287c75 100644 +--- binutils-2.34/binutils/Makefile.in ++++ binutils-2.34/binutils/Makefile.in +@@ -463,7 +463,7 @@ LN_S = @LN_S@ + LTLIBICONV = @LTLIBICONV@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/binutils/doc/Makefile.in binutils-2.34/binutils/doc/Makefile.in +index b0e7b7b6c8..dbb21dd47a 100644 +--- binutils-2.34/binutils/doc/Makefile.in ++++ binutils-2.34/binutils/doc/Makefile.in +@@ -298,7 +298,7 @@ LN_S = @LN_S@ + LTLIBICONV = @LTLIBICONV@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/gas/Makefile.in binutils-2.34/gas/Makefile.in +index 85c7b04daa..882db6dd81 100644 +--- binutils-2.34/gas/Makefile.in ++++ binutils-2.34/gas/Makefile.in +@@ -318,7 +318,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/gas/doc/Makefile.in binutils-2.34/gas/doc/Makefile.in +index f2336ec8c9..d4c36366a1 100644 +--- binutils-2.34/gas/doc/Makefile.in ++++ binutils-2.34/gas/doc/Makefile.in +@@ -280,7 +280,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/gold/Makefile.in binutils-2.34/gold/Makefile.in +index f2906ede8b..ac4fad5d55 100644 +--- binutils-2.34/gold/Makefile.in ++++ binutils-2.34/gold/Makefile.in +@@ -558,7 +558,7 @@ LIBS = @LIBS@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@ + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ +diff --git binutils-2.34/gold/testsuite/Makefile.in binutils-2.34/gold/testsuite/Makefile.in +index 9f29dc638c..6907fe1f9a 100644 +--- binutils-2.34/gold/testsuite/Makefile.in ++++ binutils-2.34/gold/testsuite/Makefile.in +@@ -2625,7 +2625,7 @@ LIBS = @LIBS@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@ + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ +diff --git binutils-2.34/gprof/Makefile.in binutils-2.34/gprof/Makefile.in +index efc2b80eb8..012f186281 100644 +--- binutils-2.34/gprof/Makefile.in ++++ binutils-2.34/gprof/Makefile.in +@@ -349,7 +349,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/ld/Makefile.in binutils-2.34/ld/Makefile.in +index 46d9b14077..2f2b0ae3ce 100644 +--- binutils-2.34/ld/Makefile.in ++++ binutils-2.34/ld/Makefile.in +@@ -429,7 +429,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/libctf/Makefile.in binutils-2.34/libctf/Makefile.in +index 3e8a0172f7..32dc1f08f7 100644 +--- binutils-2.34/libctf/Makefile.in ++++ binutils-2.34/libctf/Makefile.in +@@ -328,7 +328,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + NM = @NM@ + NMEDIT = @NMEDIT@ +diff --git binutils-2.34/libiberty/Makefile.in binutils-2.34/libiberty/Makefile.in +index fe738d0db4..6d902c5b7b 100644 +--- binutils-2.34/libiberty/Makefile.in ++++ binutils-2.34/libiberty/Makefile.in +@@ -56,7 +56,7 @@ CC = @CC@ + CFLAGS = @CFLAGS@ + CPPFLAGS = @CPPFLAGS@ + RANLIB = @RANLIB@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + PERL = @PERL@ + + PICFLAG = @PICFLAG@ +diff --git binutils-2.34/opcodes/Makefile.in binutils-2.34/opcodes/Makefile.in +index 8564803fc7..fa790026ac 100644 +--- binutils-2.34/opcodes/Makefile.in ++++ binutils-2.34/opcodes/Makefile.in +@@ -322,7 +322,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + MKINSTALLDIRS = @MKINSTALLDIRS@ + MSGFMT = @MSGFMT@ +diff --git binutils-2.34/zlib/Makefile.in binutils-2.34/zlib/Makefile.in +index 062dc04e80..4abb5ceeaa 100644 +--- binutils-2.34/zlib/Makefile.in ++++ binutils-2.34/zlib/Makefile.in +@@ -304,7 +304,7 @@ LIPO = @LIPO@ + LN_S = @LN_S@ + LTLIBOBJS = @LTLIBOBJS@ + MAINT = @MAINT@ +-MAKEINFO = @MAKEINFO@ ++MAKEINFO = true + MKDIR_P = @MKDIR_P@ + NM = @NM@ + NMEDIT = @NMEDIT@ diff --git a/util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch new file mode 100644 index 0000000000..975cad8e1b --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch @@ -0,0 +1,109 @@ +From 41a82fb711f3637b4b7f57756492b628058f9d5f Mon Sep 17 00:00:00 2001 +From: Harshit Sharma +Date: Fri, 10 Jul 2020 13:06:08 -0700 +Subject: [PATCH] crossgcc: Enable GCC to get asan shadow offset at runtime + +Unlike Linux kernel which has a static shadow region layout, we have multiple stages in +coreboot and thus require a different shadow offset address. Unfortunately, GCC currently +only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. + +For this reason, we enable GCC to determine asan shadow offset address at runtime using a +callback function named __asan_shadow_offset(). This supersedes the need to specify this +address at compile time. GCC then makes use of this shadow offset to protect stack buffers +by inserting red zones around them. + +Some other benefits of having this GCC patch are: +a. We can place the shadow region in a separate linker section with all its advantages like + automatic fit insurance. This ensures if a platform doesn't have enough memory space to + hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a + platform that actually doesn't have enough memory, it may still build without any errors.) +b. We don't modify the memory layout compared to the current one, as we are placing the + shadow region at the end of the space already occupied by the program. +c. We can be much more flexible later if needed (thinking of other stages like bootblock). +d. Since we are appending the shadow buffer to the region already occupied, we make efficient + use of the limited memory available which is highly beneficial when using cache as ram. + +Further, we have made sure that if you compile you tree with ASan enabled but missed this +patch, it will end up in the following compilation error: +"invalid --param name 'asan-use-shadow-offset-callback'" +So, you cannot accidentally enable the feature without having your compiler patched. + +Signed-off-by: Harshit Sharma +--- + gcc/asan.c | 29 ++++++++++++++++++++++------- + gcc/params.def | 6 ++++++ + gcc/params.h | 2 ++ + 3 files changed, 30 insertions(+), 7 deletions(-) + +diff --git a/gcc/asan.c b/gcc/asan.c +index 235e21947..713bf994d 100644 +--- a/gcc/asan.c ++++ b/gcc/asan.c +@@ -1389,13 +1389,28 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, + TREE_ASM_WRITTEN (decl) = 1; + TREE_ASM_WRITTEN (id) = 1; + emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); +- shadow_base = expand_binop (Pmode, lshr_optab, base, +- gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), +- NULL_RTX, 1, OPTAB_DIRECT); +- shadow_base +- = plus_constant (Pmode, shadow_base, +- asan_shadow_offset () +- + (base_align_bias >> ASAN_SHADOW_SHIFT)); ++ if (ASAN_USE_SHADOW_OFFSET_CALLBACK) { ++ rtx addr, shadow_offset_rtx; ++ ret = init_one_libfunc ("__asan_shadow_offset"); ++ addr= convert_memory_address (ptr_mode, base); ++ ret = emit_library_call_value (ret, NULL_RTX, LCT_NORMAL, ptr_mode, ++ addr, ptr_mode); ++ shadow_offset_rtx = convert_memory_address (Pmode, ret); ++ shadow_base = expand_binop (Pmode, lshr_optab, base, ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); ++ shadow_base = expand_binop (Pmode, add_optab, shadow_base, ++ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); ++ shadow_base = plus_constant (Pmode, shadow_base, ++ (base_align_bias >> ASAN_SHADOW_SHIFT)); ++ } else { ++ shadow_base = expand_binop (Pmode, lshr_optab, base, ++ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), ++ NULL_RTX, 1, OPTAB_DIRECT); ++ shadow_base = plus_constant (Pmode, shadow_base, ++ asan_shadow_offset () ++ + (base_align_bias >> ASAN_SHADOW_SHIFT)); ++ } + gcc_assert (asan_shadow_set != -1 + && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); + shadow_mem = gen_rtx_MEM (SImode, shadow_base); +diff --git a/gcc/params.def b/gcc/params.def +index dad47ec2b..bfe6eaa0b 100644 +--- a/gcc/params.def ++++ b/gcc/params.def +@@ -1203,6 +1203,12 @@ DEFPARAM (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD, + "in function becomes greater or equal to this number.", + 7000, 0, INT_MAX) + ++DEFPARAM (PARAM_ASAN_USE_SHADOW_OFFSET_CALLBACK, ++ "asan-use-shadow-offset-callback", ++ "Use shadow offset callback function at runtime instead of " ++ "fixed value at compile time at the cost of runtime overhead.", ++ 0, 0, 1) ++ + DEFPARAM (PARAM_USE_AFTER_SCOPE_DIRECT_EMISSION_THRESHOLD, + "use-after-scope-direct-emission-threshold", + "Use direct poisoning/unpoisoning instructions for variables " +diff --git a/gcc/params.h b/gcc/params.h +index 98249d2a1..d3bd6be38 100644 +--- a/gcc/params.h ++++ b/gcc/params.h +@@ -246,6 +246,8 @@ extern void init_param_values (int *params); + PARAM_VALUE (PARAM_ASAN_USE_AFTER_RETURN) + #define ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD \ + PARAM_VALUE (PARAM_ASAN_INSTRUMENTATION_WITH_CALL_THRESHOLD) ++#define ASAN_USE_SHADOW_OFFSET_CALLBACK \ ++ PARAM_VALUE (PARAM_ASAN_USE_SHADOW_OFFSET_CALLBACK) + #define ASAN_PARAM_USE_AFTER_SCOPE_DIRECT_EMISSION_THRESHOLD \ + ((unsigned) PARAM_VALUE (PARAM_USE_AFTER_SCOPE_DIRECT_EMISSION_THRESHOLD)) + +-- +2.17.1 diff --git a/util/crossgcc/patches/gcc-8.3.0_libcpp.patch b/util/crossgcc/patches/gcc-8.3.0_libcpp.patch new file mode 100644 index 0000000000..124637e001 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_libcpp.patch @@ -0,0 +1,56 @@ +GCC with `-Wformat-security -Werror=format-security` hardening options enabled +by default rejects some codes in libcpp. This patch fixes them. + +--- gcc-8.3.0/libcpp/expr.c.bak 2020-09-11 15:44:45.770000000 +0900 ++++ gcc-8.3.0/libcpp/expr.c 2020-09-11 15:46:22.370000000 +0900 +@@ -794,10 +794,10 @@ + + if (CPP_OPTION (pfile, c99)) + cpp_warning_with_line (pfile, CPP_W_LONG_LONG, virtual_location, +- 0, message); ++ 0, "%s", message); + else + cpp_pedwarning_with_line (pfile, CPP_W_LONG_LONG, +- virtual_location, 0, message); ++ virtual_location, 0, "%s", message); + } + + result |= CPP_N_INTEGER; +--- gcc-8.3.0/libcpp/macro.c.bak 2020-09-11 16:01:42.550000000 +0900 ++++ gcc-8.3.0/libcpp/macro.c 2020-09-11 16:03:47.850000000 +0900 +@@ -160,7 +160,7 @@ + if (m_state == 2 && token->type == CPP_PASTE) + { + cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, +- vaopt_paste_error); ++ "%s", vaopt_paste_error); + return ERROR; + } + /* Advance states before further considering this token, in +@@ -189,7 +189,7 @@ + if (was_paste) + { + cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, +- vaopt_paste_error); ++ "%s", vaopt_paste_error); + return ERROR; + } + +@@ -3361,7 +3361,7 @@ + function-like macros, but not at the end. */ + if (following_paste_op) + { +- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ++ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); + return false; + } + break; +@@ -3374,7 +3374,7 @@ + function-like macros, but not at the beginning. */ + if (macro->count == 1) + { +- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ++ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); + return false; + } + diff --git a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch b/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch deleted file mode 100644 index 5770af6921..0000000000 --- a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- gmp-6.1.2.orig/configure 2016-12-16 16:45:32.000000000 +0100 -+++ gmp-6.1.2/configure 2017-03-08 14:26:11.194245000 +0100 -@@ -6776,7 +6776,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { -@@ -8394,7 +8394,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { diff --git a/util/crossgcc/patches/gmp-6.2.0_generic-build.patch b/util/crossgcc/patches/gmp-6.2.0_generic-build.patch new file mode 100644 index 0000000000..a05635f1d1 --- /dev/null +++ b/util/crossgcc/patches/gmp-6.2.0_generic-build.patch @@ -0,0 +1,20 @@ +Ensure that GMP is built for a generic CPU on x86 + +While GMP supports fat builds on x86 that adapt to the CPU's +capabilities, by default it builds for the CPU of the builder. +Running that binary on an older CPU then can fail. +--- gmp-6.2.0/config.guess~ 2020-09-02 19:23:01.817510842 +0200 ++++ gmp-6.2.0/config.guess 2020-09-02 19:24:55.742325907 +0200 +@@ -1029,6 +1029,12 @@ + virtualisers allow guests to set a broken state. */ + suffix = "noavx"; + ++ if (cpuid_64bit) { ++ modelstr="x86_64"; ++ } else { ++ modelstr="pentium"; ++ } ++ suffix=""; + printf ("%s%s", modelstr, suffix); + return 0; + } diff --git a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum deleted file mode 100644 index e899a451ed..0000000000 --- a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -a48fd28a037c0bcd7b7fc4d914c023f584e910ed tarballs/Python-3.8.1.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum new file mode 100644 index 0000000000..2f4d4ad795 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum @@ -0,0 +1 @@ +68d6c7f948801cc755905162f5ee7589595edee4 tarballs/Python-3.8.5.tar.xz diff --git a/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum deleted file mode 100644 index d2265e1869..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -27afd4c05c966e9390fcc30bdf1f53ddb7d69033 tarballs/acpica-unix2-20200528.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum new file mode 100644 index 0000000000..9bcfe83104 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum @@ -0,0 +1 @@ +92b0177f36b5209e6a667808ca58ef7462c4a6c7 tarballs/acpica-unix2-20200717.tar.gz diff --git a/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum deleted file mode 100644 index 3a2f076400..0000000000 --- a/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -06598868f5fa8efc98427dcb790d42c664f1a1a4 tarballs/binutils-2.33.1.tar.xz diff --git a/util/crossgcc/sum/binutils-2.35.tar.xz.cksum b/util/crossgcc/sum/binutils-2.35.tar.xz.cksum new file mode 100644 index 0000000000..06c29b0b3e --- /dev/null +++ b/util/crossgcc/sum/binutils-2.35.tar.xz.cksum @@ -0,0 +1 @@ +6bdd090ce268b6d6c3442516021c4e4b5019e303 tarballs/binutils-2.35.tar.xz diff --git a/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum deleted file mode 100644 index e39bea12bb..0000000000 --- a/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6977cf7a802a053c57fa74138d3648b563e71e88 tarballs/cfe-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..6e0d86371d --- /dev/null +++ b/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +0e61e92b22a620fe7f833fa8b2a56f2db96f7335 tarballs/clang-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..1b880c7ce4 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +26c996da082677aca1016bcf2141dbff01dc7300 tarballs/clang-tools-extra-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 47eba2cca0..0000000000 --- a/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ac64403321d8486699d8bea5376b2438663dbb41 tarballs/clang-tools-extra-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum deleted file mode 100644 index c5190b2373..0000000000 --- a/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -f514dbd9aa8332a28ba62dd8ce97b0aa0b099491 tarballs/cmake-3.16.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.18.1.tar.gz.cksum b/util/crossgcc/sum/cmake-3.18.1.tar.gz.cksum new file mode 100644 index 0000000000..c4f3ed29d3 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.18.1.tar.gz.cksum @@ -0,0 +1 @@ +60c36386d0df016adc96c8bb3215d02de3777869 tarballs/cmake-3.18.1.tar.gz diff --git a/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..2efb4136b1 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +ee6077b4728b3c750e476938cead11cea45b49ff tarballs/compiler-rt-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 15f1a61e70..0000000000 --- a/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -4e00cb231ff87fd4f970f35b2da86185a612e0e2 tarballs/compiler-rt-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum deleted file mode 100644 index 774658cb30..0000000000 --- a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -9dc6981197a7d92f339192eea974f5eca48fcffe tarballs/gmp-6.1.2.tar.xz diff --git a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum new file mode 100644 index 0000000000..b00b669fe7 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum @@ -0,0 +1 @@ +052a5411dc74054240eec58132d2cf41211d0ff6 tarballs/gmp-6.2.0.tar.xz diff --git a/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..a6919e89ad --- /dev/null +++ b/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +25d07260f3b7bf4f647e115c4a663fdeda130fbd tarballs/llvm-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 4fb1c2daad..0000000000 --- a/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7ef2527ba3da7603a41ce3592a8cd890f8d27ffa tarballs/llvm-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/mpc-1.1.0.tar.gz.cksum b/util/crossgcc/sum/mpc-1.1.0.tar.gz.cksum deleted file mode 100644 index 08e295f16b..0000000000 --- a/util/crossgcc/sum/mpc-1.1.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -b019d9e1d27ec5fb99497159d43a3164995de2d0 tarballs/mpc-1.1.0.tar.gz diff --git a/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum b/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum new file mode 100644 index 0000000000..ed98cc0298 --- /dev/null +++ b/util/crossgcc/sum/mpc-1.2.0.tar.gz.cksum @@ -0,0 +1 @@ +0abdc94acab0c9bfdaa391347cdfd7bbdb1cf017 tarballs/mpc-1.2.0.tar.gz diff --git a/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum deleted file mode 100644 index 62ede96ee6..0000000000 --- a/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -52c1f2a4c9a202f46cf3275a8d46b562aa584208 tarballs/mpfr-4.0.2.tar.xz diff --git a/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum new file mode 100644 index 0000000000..b4fcdf7e1a --- /dev/null +++ b/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum @@ -0,0 +1 @@ +159c3a58705662bfde4dc93f2617f3660855ead6 tarballs/mpfr-4.1.0.tar.xz diff --git a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum deleted file mode 100644 index f3b9de9d29..0000000000 --- a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -fe098ee4dc9c4c983696c4948e64b23e4098b92b tarballs/nasm-2.14.02.tar.bz2 diff --git a/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum new file mode 100644 index 0000000000..6033faeff4 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum @@ -0,0 +1 @@ +513ac3b800377f10833a02bc7f3fa8b84ca4f2b6 tarballs/nasm-2.15.03.tar.bz2 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 7c87056a7b..007e9afc7b 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -63,7 +63,8 @@ RUN \ openssl \ patch \ pkg-config \ - python \ + python2 \ + python3 \ qemu \ rsync \ shellcheck \ diff --git a/util/exynos/description.md b/util/exynos/description.md index 26cd20d3a4..c039c913f3 100644 --- a/util/exynos/description.md +++ b/util/exynos/description.md @@ -1 +1 @@ -Computes and fills Exynos ROM checksum (for BL1 or BL2). `Python2` +Computes and fills Exynos ROM checksum (for BL1 or BL2). `Python3` diff --git a/util/exynos/fixed_cksum.py b/util/exynos/fixed_cksum.py index c6a9ddae61..0ae7e4f6f8 100755 --- a/util/exynos/fixed_cksum.py +++ b/util/exynos/fixed_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause @@ -28,7 +28,7 @@ def main(argv): checksum_size = struct.calcsize(checksum_format) data_size = size - checksum_size assert len(data) <= data_size - checksum = struct.pack(checksum_format, sum(map(ord, data))) + checksum = struct.pack(checksum_format, sum(data)) out_file.write(data + bytearray(data_size - len(data)) + checksum) diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py index 62a76cc045..4321f8e53c 100755 --- a/util/exynos/variable_cksum.py +++ b/util/exynos/variable_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause @@ -27,7 +27,7 @@ def main(argv): data = in_file.read() header = struct.pack(header_format, struct.calcsize(header_format) + len(data), - sum(map(ord, data)), + sum(data), 0, 0) out_file.write(header + data) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 3db3977bf5..220c140417 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -59,6 +59,7 @@ static const char *const ich_chipset_names[] = { "ICH8", "ICH9", "ICH10", + "Unknown PCH", "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", @@ -68,7 +69,10 @@ static const char *const ich_chipset_names[] = { "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", - "100 series Sunrise Point", + "Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx", + "100/200 series Sunrise Point", + "300 series Cannon Point/ 400 series Ice Point", + "500 series Tiger Point/ 600 series Alder Point", "C620 series Lewisburg", NULL }; @@ -161,14 +165,42 @@ static fmsba_t *find_fmsba(char *image, int size) return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL; } +static enum ich_chipset guess_ifd_2_chipset(const fpsba_t *fpsba) +{ + uint32_t pchstrp_22 = fpsba->pchstrp[22]; + uint32_t pchstrp_23 = fpsba->pchstrp[23]; + + /* Offset 0x5B is the last PCH descriptor record */ + if (pchstrp_23 == 0xFFFFFFFF) + return CHIPSET_N_J_SERIES; + + /* Offset 0x58 is PCH descriptor record is reserved */ + if (pchstrp_22 == 0x0) + return CHIPSET_300_400_SERIES_CANNON_ICE_POINT; + + /* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */ + if (((pchstrp_22 & 0x07) == 0x4) && + ((pchstrp_22 & 0xFF0000) >> 16 == 0x58)) + return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; + + return CHIPSET_PCH_UNKNOWN; +} + /* port from flashrom */ -static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb) +static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb, const fpsba_t *fpsba) { uint32_t iccriba = (fdb->flmap2 >> 16) & 0xff; uint32_t msl = (fdb->flmap2 >> 8) & 0xff; uint32_t isl = (fdb->flmap1 >> 24); uint32_t nm = (fdb->flmap1 >> 8) & 0x7; + int temp_chipset; + /* Check for IFD2 chipset type */ + temp_chipset = guess_ifd_2_chipset(fpsba); + if (temp_chipset != CHIPSET_PCH_UNKNOWN) + return temp_chipset; + + /* Rest for IFD1 chipset type */ if (iccriba == 0x00) { if (msl == 0 && isl <= 2) return CHIPSET_ICH8; @@ -192,7 +224,7 @@ static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb) } else if (nm == 6) { return CHIPSET_C620_SERIES_LEWISBURG; } else { - return CHIPSET_100_SERIES_SUNRISE_POINT; + return CHIPSET_100_200_SERIES_SUNRISE_POINT; } } @@ -210,6 +242,7 @@ static int is_platform_ifd_2(void) PLATFORM_ICL, PLATFORM_TGL, PLATFORM_JSL, + PLATFORM_ADL, }; unsigned int i; @@ -231,10 +264,11 @@ static int get_ifd_version_from_fcba(char *image, int size) int read_freq; const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); - if (!fcba || !fdb) + const fpsba_t *fpsba = find_fpsba(image, size); + if (!fcba || !fdb || !fpsba) exit(EXIT_FAILURE); - chipset = guess_ich_chipset(fdb); + chipset = guess_ich_chipset(fdb, fpsba); /* TODO: port ifd_version and max_regions * against guess_ich_chipset() */ @@ -372,8 +406,14 @@ static void dump_region_layout(char *buf, size_t bufsize, unsigned int num, static void dump_frba(const frba_t *frba) { unsigned int i; + region_t region; printf("Found Region Section\n"); for (i = 0; i < max_regions; i++) { + region = get_region(frba, i); + /* Skip unused & reserved Flash Region */ + if (region.size < 1 && !strcmp(region_name(i), "Reserved")) + continue; + printf("FLREG%u: 0x%08x\n", i, frba->flreg[i]); dump_region(i, frba); } @@ -408,7 +448,7 @@ static void dump_frba_layout(const frba_t *frba, const char *layout_fname) printf("Wrote layout to %s\n", layout_fname); } -static void decode_spi_frequency(unsigned int freq) +static void _decode_spi_frequency(unsigned int freq) { switch (freq) { case SPI_FREQUENCY_20MHZ: @@ -438,6 +478,94 @@ static void decode_spi_frequency(unsigned int freq) } } +static void _decode_spi_frequency_500_series(unsigned int freq) +{ + switch (freq) { + case SPI_FREQUENCY_100MHZ: + printf("100MHz"); + break; + case SPI_FREQUENCY_50MHZ: + printf("50MHz"); + break; + case SPI_FREQUENCY_500SERIES_33MHZ: + printf("33MHz"); + break; + case SPI_FREQUENCY_25MHZ: + printf("25MHz"); + break; + case SPI_FREQUENCY_14MHZ: + printf("14MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_spi_frequency(unsigned int freq) +{ + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) + _decode_spi_frequency_500_series(freq); + else + _decode_spi_frequency(freq); +} + +static void _decode_espi_frequency(unsigned int freq) +{ + switch (freq) { + case ESPI_FREQUENCY_20MHZ: + printf("20MHz"); + break; + case ESPI_FREQUENCY_24MHZ: + printf("24MHz"); + break; + case ESPI_FREQUENCY_30MHZ: + printf("30MHz"); + break; + case ESPI_FREQUENCY_48MHZ: + printf("48MHz"); + break; + case ESPI_FREQUENCY_60MHZ: + printf("60MHz"); + break; + case ESPI_FREQUENCY_17MHZ: + printf("17MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void _decode_espi_frequency_500_series(unsigned int freq) +{ + switch (freq) { + case ESPI_FREQUENCY_500SERIES_20MHZ: + printf("20MHz"); + break; + case ESPI_FREQUENCY_500SERIES_24MHZ: + printf("24MHz"); + break; + case ESPI_FREQUENCY_500SERIES_25MHZ: + printf("25MHz"); + break; + case ESPI_FREQUENCY_500SERIES_48MHZ: + printf("48MHz"); + break; + case ESPI_FREQUENCY_500SERIES_60MHZ: + printf("60MHz"); + break; + default: + printf("unknown<%x>MHz", freq); + } +} + +static void decode_espi_frequency(unsigned int freq) +{ + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) + _decode_espi_frequency_500_series(freq); + else + _decode_espi_frequency(freq); +} + static void decode_component_density(unsigned int density) { switch (density) { @@ -473,8 +601,28 @@ static void decode_component_density(unsigned int density) } } -static void dump_fcba(const fcba_t *fcba) +static int is_platform_with_pch(void) { + if (chipset >= CHIPSET_5_SERIES_IBEX_PEAK) + return 1; + + return 0; +} + +/* FLMAP0 register bit 24 onwards are reserved from SPT PCH */ +static int is_platform_with_100x_series_pch(void) +{ + if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && + chipset <= CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) + return 1; + + return 0; +} + +static void dump_fcba(const fcba_t *fcba, const fpsba_t *fpsba) +{ + unsigned int freq; + printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", @@ -487,8 +635,18 @@ static void dump_fcba(const fcba_t *fcba) decode_spi_frequency((fcba->flcomp >> 21) & 7); printf("\n Fast Read Support: %ssupported", (fcba->flcomp & (1 << 20))?"":"not "); - printf("\n Read Clock Frequency: "); - decode_spi_frequency((fcba->flcomp >> 17) & 7); + if (is_platform_with_100x_series_pch() && + chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { + printf("\n Read eSPI/EC Bus Frequency: "); + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) + freq = (fpsba->pchstrp[22] & 0x38) >> 3; + else + freq = (fcba->flcomp >> 17) & 7; + decode_espi_frequency(freq); + } else { + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + } switch (ifd_version) { case IFD_VERSION_1: @@ -515,9 +673,21 @@ static void dump_fcba(const fcba_t *fcba) (fcba->flill >> 8) & 0xff); printf(" Invalid Instruction 0: 0x%02x\n", fcba->flill & 0xff); - printf("FLPB 0x%08x\n", fcba->flpb); - printf(" Flash Partition Boundary Address: 0x%06x\n\n", - (fcba->flpb & 0xfff) << 12); + if (is_platform_with_100x_series_pch()) { + printf("FLILL1 0x%08x\n", fcba->flpb); + printf(" Invalid Instruction 7: 0x%02x\n", + (fcba->flpb >> 24) & 0xff); + printf(" Invalid Instruction 6: 0x%02x\n", + (fcba->flpb >> 16) & 0xff); + printf(" Invalid Instruction 5: 0x%02x\n", + (fcba->flpb >> 8) & 0xff); + printf(" Invalid Instruction 4: 0x%02x\n", + fcba->flpb & 0xff); + } else { + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); + } } static void dump_fpsba(const fdbar_t *fdb, const fpsba_t *fpsba) @@ -719,22 +889,33 @@ static void dump_fd(char *image, int size) if (!fdb) exit(EXIT_FAILURE); - printf("ICH Revision: %s\n", ich_chipset_names[chipset]); + printf("%s", is_platform_with_pch() ? "PCH" : "ICH"); + printf(" Revision: %s\n", ich_chipset_names[chipset]); printf("FLMAP0: 0x%08x\n", fdb->flmap0); - printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + if (!is_platform_with_100x_series_pch()) + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4); printf("FLMAP1: 0x%08x\n", fdb->flmap1); - printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + printf(" %s: ", is_platform_with_100x_series_pch() ? "PSL" : "ISL"); + printf("0x%02x\n", (fdb->flmap1 >> 24) & 0xff); printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4); - printf("FLMAP2: 0x%08x\n", fdb->flmap2); - printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); - printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + if (!is_platform_with_100x_series_pch()) { + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + } + + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) { + printf("FLMAP3: 0x%08x\n", fdb->flmap3); + printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); + printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); + } char *flumap = find_flumap(image, size); uint32_t flumap1 = *(uint32_t *)flumap; @@ -756,7 +937,7 @@ static void dump_fd(char *image, int size) if (frba && fcba && fpsba && fmba && fmsba) { dump_frba(frba); - dump_fcba(fcba); + dump_fcba(fcba, fpsba); dump_fpsba(fdb, fpsba); dump_fmba(fmba); dump_fmsba(fmsba); @@ -1017,6 +1198,8 @@ static void lock_descriptor(const char *filename, char *image, int size) case PLATFORM_ICL: case PLATFORM_SKLKBL: case PLATFORM_TGL: + case PLATFORM_JSL: + case PLATFORM_ADL: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1447,10 +1630,14 @@ static void print_usage(const char *name) " -M | --altmedisable <0|1> Set the MeDisable and AltMeDisable (or HAP for skylake or newer platform)\n" " bits to disable ME\n" " -p | --platform Add platform-specific quirks\n" - " aplk - Apollo Lake\n" - " cnl - Cannon Lake\n" - " glk - Gemini Lake\n" - " sklkbl - Skylake/Kaby Lake\n" + " adl - Alder Lake\n" + " aplk - Apollo Lake\n" + " cnl - Cannon Lake\n" + " glk - Gemini Lake\n" + " icl - Ice Lake\n" + " jsl - Jasper Lake\n" + " sklkbl - Sky Lake/Kaby Lake\n" + " tgl - Tiger Lake\n" " -S | --setpchstrap Write a PCH strap\n" " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" @@ -1688,6 +1875,8 @@ int main(int argc, char *argv[]) platform = PLATFORM_SKLKBL; } else if (!strcmp(optarg, "tgl")) { platform = PLATFORM_TGL; + } else if (!strcmp(optarg, "adl")) { + platform = PLATFORM_ADL; } else { fprintf(stderr, "Unknown platform: %s\n", optarg); exit(EXIT_FAILURE); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 3b16d4984a..ced4f2b062 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -23,6 +23,7 @@ enum ich_chipset { CHIPSET_ICH8, CHIPSET_ICH9, CHIPSET_ICH10, + CHIPSET_PCH_UNKNOWN, CHIPSET_5_SERIES_IBEX_PEAK, CHIPSET_6_SERIES_COUGAR_POINT, CHIPSET_7_SERIES_PANTHER_POINT, @@ -34,9 +35,11 @@ enum ich_chipset { CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, CHIPSET_9_SERIES_WILDCAT_POINT_LP, - CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) - * variants - */ + CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */ + CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */ + CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */ + CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) + * variants onwards */ CHIPSET_C620_SERIES_LEWISBURG, }; @@ -48,6 +51,7 @@ enum platform { PLATFORM_JSL, PLATFORM_SKLKBL, PLATFORM_TGL, + PLATFORM_ADL, }; #define LAYOUT_LINELEN 80 @@ -60,6 +64,31 @@ enum spi_frequency { SPI_FREQUENCY_17MHZ = 6, }; +enum spi_frequency_500_series { + SPI_FREQUENCY_100MHZ = 0, + SPI_FREQUENCY_50MHZ = 1, + SPI_FREQUENCY_500SERIES_33MHZ = 3, + SPI_FREQUENCY_25MHZ = 4, + SPI_FREQUENCY_14MHZ = 6, +}; + +enum espi_frequency { + ESPI_FREQUENCY_20MHZ = 0, + ESPI_FREQUENCY_24MHZ = 1, + ESPI_FREQUENCY_30MHZ = 2, + ESPI_FREQUENCY_48MHZ = 3, + ESPI_FREQUENCY_60MHZ = 4, + ESPI_FREQUENCY_17MHZ = 6, +}; + +enum espi_frequency_500_series { + ESPI_FREQUENCY_500SERIES_20MHZ = 0, + ESPI_FREQUENCY_500SERIES_24MHZ = 1, + ESPI_FREQUENCY_500SERIES_25MHZ = 2, + ESPI_FREQUENCY_500SERIES_48MHZ = 3, + ESPI_FREQUENCY_500SERIES_60MHZ = 4, +}; + enum component_density { COMPONENT_DENSITY_512KB = 0, COMPONENT_DENSITY_1MB = 1, @@ -78,6 +107,7 @@ typedef struct { uint32_t flmap0; uint32_t flmap1; uint32_t flmap2; + uint32_t flmap3; // Exist for 500 series onwards } __attribute__((packed)) fdbar_t; // regions diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 482fd5b183..9105d3b82b 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -314,12 +314,16 @@ out: rehide_me(); } +static void print_btg_bool_param(const char *name, u8 state) +{ + printf("%-20s : %s\n", name, state ? "ON" : "OFF"); +} + static void dump_bootguard_info(void) { struct pci_dev *dev; char namebuf[1024]; const char *name = NULL; - uint64_t bootguard = 0; if (pci_platform_scan()) return; @@ -342,59 +346,74 @@ static void dump_bootguard_info(void) if (ME_major_ver && (ME_major_ver < 9 || (ME_major_ver == 9 && ME_minor_ver < 5))) { - print_cap("BootGuard ", 0); - printf(CGRN "\nYour system isn't bootguard ready. You can " - "flash other firmware!\n" RESET); + printf(CGRN "Your system isn't BootGuard ready.\n" + "You can flash other firmware!\n" RESET); rehide_me(); return; } - if (msr_bootguard(&bootguard, debug) < 0) { - printf("ME Capability: %-43s: " CCYN "%s\n" RESET, - "BootGuard Mode", "Unknown"); - rehide_me(); - return; - } - - if (debug) { - printf("BootGuard MSR Output: 0x%" PRIx64 "\n", bootguard); - bootguard &= ~0xff; - } - - print_cap("BootGuard ", 1); if (pci_read_long(dev, 0x40) & 0x10) - printf(CYEL "Your southbridge configuration is insecure!! " + printf(CYEL "Your southbridge configuration is insecure!!\n" "BootGuard keys can be overwritten or wiped, or you are " "in developer mode.\n" RESET); rehide_me(); - switch (bootguard) { - case BOOTGUARD_DISABLED: - printf("ME Capability: %-43s: " CGRN "%s\n" RESET, - "BootGuard Mode", "Disabled"); - printf(CGRN "\nYour system is bootguard ready but your vendor " - "disabled it. You can flash other firmware!\n" RESET); - break; - case BOOTGUARD_ENABLED_COMBI_MODE: - printf("ME Capability: %-43s: " CGRN "%s\n" RESET, - "BootGuard Mode", "Verified & Measured Boot"); - printf(CRED "\nVerified boot is enabled. You can't flash other " - "firmware. !\n" RESET); - break; - case BOOTGUARD_ENABLED_MEASUREMENT_MODE: - printf("ME Capability: %-43s: " CGRN "%s\n" RESET, - "BootGuard Mode", "Measured Boot"); - printf(CGRN "\nYour system is bootguard ready but only running " - "the measured boot mode. You can flash other firmware!\n" - RESET); - break; - case BOOTGUARD_ENABLED_VERIFIED_MODE: - printf("ME Capability: %-43s: " CGRN "%s\n" RESET, - "BootGuard Mode", "Verified Boot"); - printf(CRED "\nVerified boot is enabled! You can't flash other " - "firmware.\n" RESET); - break; + union { + struct { + u8 nem_enabled : 1; /* [ 0.. 0] */ + u8 tpm_type : 2; /* [ 2.. 1] */ + u8 tpm_success : 1; /* [ 3.. 3] */ + u8 facb_fpf : 1; /* [ 4.. 4] */ + u8 measured_boot : 1; /* [ 5.. 5] */ + u8 verified_boot : 1; /* [ 6.. 6] */ + u8 module_revoked : 1; /* [ 7.. 7] */ + u32 : 24; + u8 btg_capability : 1; /* [32..32] */ + u32 : 31; + }; + u64 raw; + } btg; + + if (msr_bootguard(&btg.raw) < 0) { + printf("Could not read the BOOTGUARD_SACM_INFO MSR.\n"); + return; + } + + printf("BootGuard MSR Output : 0x%" PRIx64 "\n", btg.raw); + + if (!btg.btg_capability) { + printf(CGRN "Your system isn't BootGuard ready.\n" + "You can flash other firmware!\n" RESET); + return; + } + + print_btg_bool_param("Measured boot", btg.measured_boot); + print_btg_bool_param("Verified boot", btg.verified_boot); + print_btg_bool_param("FACB in FPFs", btg.facb_fpf); + print_btg_bool_param("Module revoked", btg.module_revoked); + if (btg.measured_boot) { + const char *const tpm_type_strs[] = { + "None", + "TPM 1.2", + "TPM 2.0", + "PTT", + }; + printf("%-20s : %s\n", "TPM type", tpm_type_strs[btg.tpm_type]); + print_btg_bool_param("TPM success", btg.tpm_success); + } + if (btg.verified_boot) { + print_btg_bool_param("NEM enabled", btg.nem_enabled); + if (btg.nem_enabled) + printf(CRED "Verified boot is enabled and ACM has enabled " + "Cache-As-RAM.\nYou can't flash other firmware!\n" RESET); + else + printf(CYEL "Verified boot is enabled, but ACM did not enable " + "Cache-As-RAM.\nIt might be possible to flash other firmware.\n" + RESET); + } else { + printf(CGRN "Your system is BootGuard ready but verified boot is disabled.\n" + "You can flash other firmware!\n" RESET); } } diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 47b892ed25..d6dd3b2d1e 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -48,11 +48,6 @@ #define ME_MESSAGE_LEN 256 extern int debug; -static inline void print_cap(const char *name, int state) -{ - printf("ME Capability: %-30s : %s\n", - name, state ? CRED "ON" RESET : CGRN "OFF" RESET); -} #define PCI_VENDOR_ID_INTEL 0x8086 @@ -431,6 +426,7 @@ static inline void print_cap(const char *name, int state) #define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */ #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP 0x9de0 /* Cannon Point-LP */ +#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP 0x02e0 /* Comet Point-LP (Cometlake-U) */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME 0xa13a /* SUNRISE Point-H 1 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME 0xa13b /* SUNRISE Point-H 2 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME 0xA13E /* SUNRISE Point-H 3 */ @@ -484,6 +480,7 @@ static inline void print_cap(const char *name, int state) ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \ ((x) == PCI_DEVICE_ID_INTEL_CANNONPOINT_LP) || \ + ((x) == PCI_DEVICE_ID_INTEL_COMETPOINT_LP) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME) || \ ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME) || \ @@ -495,13 +492,3 @@ static inline void print_cap(const char *name, int state) ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \ ((x) == PCI_DEVICE_ID_INTEL_CANNONLAKE) || \ 0) - -#define BOOTGUARD_DISABLED 0x400000000 -#define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000 -#define BOOTGUARD_ENABLED_MEASUREMENT_MODE 0x200000000 -#define BOOTGUARD_ENABLED_COMBI_MODE 0x300000000 -#define BOOTGUARD_CAPABILITY(x) ( \ - ((x) == BOOTGUARD_DISABLED) || \ - ((x) == BOOTGUARD_ENABLED_VERIFIED_MODE) || \ - ((x) == BOOTGUARD_ENABLED_MEASUREMENT_MODE) || \ - ((x) == BOOTGUARD_ENABLED_COMBI_MODE)) diff --git a/util/intelmetool/me.c b/util/intelmetool/me.c index 694d733464..72430afc90 100644 --- a/util/intelmetool/me.c +++ b/util/intelmetool/me.c @@ -413,6 +413,12 @@ int mkhi_get_fw_version(int *major, int *minor) return 0; } +static void print_cap(const char *name, int state) +{ + printf("ME Capability: %-30s : %s\n", + name, state ? CRED "ON" RESET : CGRN "OFF" RESET); +} + /* Get ME Firmware Capabilities */ int mkhi_get_fwcaps(void) { diff --git a/util/intelmetool/msr.c b/util/intelmetool/msr.c index 263a8202bb..1a5ead9737 100644 --- a/util/intelmetool/msr.c +++ b/util/intelmetool/msr.c @@ -39,7 +39,7 @@ static int rdmsr(int addr, uint64_t *msr) } #endif -int msr_bootguard(uint64_t *msr, int debug) +int msr_bootguard(uint64_t *msr) { #ifndef __DARWIN__ @@ -54,8 +54,5 @@ int msr_bootguard(uint64_t *msr, int debug) return -1; #endif - if (!debug) - *msr &= ~0xff; - return 0; } diff --git a/util/intelmetool/msr.h b/util/intelmetool/msr.h index 44008d50c6..952b0c0a24 100644 --- a/util/intelmetool/msr.h +++ b/util/intelmetool/msr.h @@ -13,5 +13,5 @@ typedef struct { unsigned int ecx; } regs_t; -extern int msr_bootguard(uint64_t *msr, int debug); +extern int msr_bootguard(uint64_t *msr); #endif diff --git a/util/intelp2m/Makefile b/util/intelp2m/Makefile new file mode 100644 index 0000000000..1d9ba70ce3 --- /dev/null +++ b/util/intelp2m/Makefile @@ -0,0 +1,11 @@ +# simple makefile for the project + +OUTPUT_DIR = generate +PROJECT_NAME = intelp2m + +default: + go version + go build -v -o $(PROJECT_NAME) + +clean: + rm -Rf $(PROJECT_NAME) $(OUTPUT_DIR) diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go new file mode 100644 index 0000000000..16fb4d6e01 --- /dev/null +++ b/util/intelp2m/config/config.go @@ -0,0 +1,127 @@ +package config + +import "os" + +const ( + TempInteltool int = 0 + TempGpioh int = 1 + TempSpec int = 2 +) + +var template int = 0 + +func TemplateSet(temp int) bool { + if temp > TempSpec { + return false + } else { + template = temp + return true + } +} + +func TemplateGet() int { + return template +} + +const ( + SunriseType uint8 = 0 + LewisburgType uint8 = 1 + ApolloType uint8 = 2 + CannonType uint8 = 3 +) + +var key uint8 = SunriseType + +var platform = map[string]uint8{ + "snr": SunriseType, + "lbg": LewisburgType, + "apl": ApolloType, + "cnl": CannonType} +func PlatformSet(name string) int { + if platformType, valid := platform[name]; valid { + key = platformType + return 0 + } + return -1 +} +func PlatformGet() uint8 { + return key +} +func IsPlatform(platformType uint8) bool { + return platformType == key +} +func IsPlatformApollo() bool { + return IsPlatform(ApolloType) +} +func IsPlatformSunrise() bool { + return IsPlatform(SunriseType) +} +func IsPlatformLewisburg() bool { + return IsPlatform(LewisburgType) +} +func IsPlatformCannonLake() bool { + return IsPlatform(CannonType) +} + +var InputRegDumpFile *os.File = nil +var OutputGenFile *os.File = nil + +var ignoredFieldsFormat bool = false +func IgnoredFieldsFlagSet(flag bool) { + ignoredFieldsFormat = flag +} +func AreFieldsIgnored() bool { + return ignoredFieldsFormat +} + +var nonCheckingFlag bool = false +func NonCheckingFlagSet(flag bool) { + nonCheckingFlag = flag +} +func IsNonCheckingFlagUsed() bool { + return nonCheckingFlag +} + + +var infolevel int = 0 +func InfoLevelSet(lvl int) { + infolevel = lvl +} +func InfoLevelGet() int { + return infolevel +} + +var fldstyle uint8 = CbFlds +const ( + NoFlds uint8 = 0 + CbFlds uint8 = 1 // coreboot style + FspFlds uint8 = 2 // FSP/edk2 style + RawFlds uint8 = 3 // raw DW0/1 values +) +var fldstylemap = map[string]uint8{ + "none" : NoFlds, + "cb" : CbFlds, + "fsp" : FspFlds, + "raw" : RawFlds} +func FldStyleSet(name string) int { + if style, valid := fldstylemap[name]; valid { + fldstyle = style + return 0 + } + return -1 +} +func FldStyleGet() uint8 { + return fldstyle +} +func IsFieldsMacroUsed() bool { + return FldStyleGet() != NoFlds +} +func IsCbStyleMacro() bool { + return FldStyleGet() == CbFlds +} +func IsFspStyleMacro() bool { + return FldStyleGet() == FspFlds +} +func IsRawFields() bool { + return FldStyleGet() == RawFlds +} diff --git a/util/intelp2m/config/gopackages.png b/util/intelp2m/config/gopackages.png new file mode 100644 index 0000000000..fb81a1ce1f Binary files /dev/null and b/util/intelp2m/config/gopackages.png differ diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md new file mode 100644 index 0000000000..9ca56b979e --- /dev/null +++ b/util/intelp2m/description.md @@ -0,0 +1,176 @@ +Intel Pad to Macro (intelp2m) converter +======================================= + +This utility allows to convert the configuration DW0/1 registers value +from [inteltool](../inteltool/description.md) dump to coreboot macros. + +```bash +(shell)$ make +(shell)$ ./intelp2m -h +(shell)$ ./intelp2m -file /path/to/inteltool.log +``` + +### Platforms + +It is possible to use templates for parsing files of excellent inteltool.log. +To specify such a pattern, use the option -t