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siemens/mc_apl4: Enable all PCIe root ports

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Enable all PCIe root ports for this mainboard.

Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
2018-11-09 10:25:15 +01:00
committed by Werner Zeh
parent fe7367801c
commit 3a499725f0
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
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@@ -60,12 +60,12 @@ chip soc/intel/apollolake
device pci 0e.0 off end # - Audio device pci 0e.0 off end # - Audio
device pci 11.0 on end # - ISH device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY device pci 13.0 on end # - RP 2 - PCIe A 0
device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY device pci 13.1 on end # - RP 3 - PCIe A 1
device pci 13.2 off end # - RP 4 - PCIe-A 2 device pci 13.2 on end # - RP 4 - PCIe-A 2
device pci 13.3 off end # - RP 5 - PCIe-A 3 device pci 13.3 on end # - RP 5 - PCIe-A 3
device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge device pci 14.0 on end # - RP 0 - PCIe-B 0
device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA device pci 14.1 on end # - RP 1 - PCIe-B 1
device pci 15.0 on end # - XHCI device pci 15.0 on end # - XHCI
device pci 15.1 off end # - XDCI device pci 15.1 off end # - XDCI
device pci 16.0 on # - I2C 0 device pci 16.0 on # - I2C 0