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nb/intel/gm45: Switch to POSTCAR_STAGE

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Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26788
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-06-03 12:42:10 +02:00
parent 4ff675ebd0
commit 3a4edb6ea8
5 changed files with 11 additions and 15 deletions
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4
src/cpu/intel/socket_BGA956/Makefile.inc
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@@ -8,11 +8,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c

4
src/cpu/intel/socket_mPGA478MN/Makefile.inc
View File

@@ -9,11 +9,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c