sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/gm45: Switch to POSTCAR_STAGE

Browse Source 
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26788
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-06-03 12:42:10 +02:00
parent 4ff675ebd0
commit 3a4edb6ea8
5 changed files with 11 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/intel/socket_BGA956/Makefile.inc
View File

@ -8,11 +8,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c

4
src/cpu/intel/socket_mPGA478MN/Makefile.inc
View File

@ -9,11 +9,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c

2
src/northbridge/intel/gm45/Kconfig
View File

@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select RELOCATABLE_RAMSTAGE select RELOCATABLE_RAMSTAGE
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select POSTCAR_CONSOLE
config CBFS_SIZE config CBFS_SIZE
hex hex

2
src/northbridge/intel/gm45/Makefile.inc
View File

@ -36,4 +36,6 @@ ramstage-y += gma.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
postcar-y += ram_calc.c
endif endif

14
src/northbridge/intel/gm45/ram_calc.c
View File

@ -118,9 +118,10 @@ void *cbmem_top(void)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* setup_stack_and_mtrrs() determines the stack to use after /* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */ * cache-as-ram is torn down as well as the MTRR settings to use,
void *setup_stack_and_mtrrs(void) * and continues execution in postcar stage. */
void platform_enter_postcar(void)
{ {
struct postcar_frame pcf; struct postcar_frame pcf;
uintptr_t top_of_ram; uintptr_t top_of_ram;
@ -143,8 +144,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
/* Save the number of MTRRs to setup. Return the stack location run_postcar_phase(&pcf);
* pointing to the number of MTRRs.
*/ /* We do not return here. */
return postcar_commit_mtrrs(&pcf);
} }