timestamps: Switch from tsc_t to uint64_t

Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.

Timestamp implementation for ARMv7

Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.

The ARM implementation uses the monotonic timer.

Original-Signed-off-by: Stefan Reinauer <reinauer@google.com>

BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps

Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)

Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/arch/arm/armv7/Makefile.inc

@@ -57,6 +57,7 @@ romstage-y += cpu.S
 romstage-y += exception.c
 romstage-y += exception_asm.S
 romstage-y += mmu.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 romstage-c-ccopts += $(armv7_flags)
 romstage-S-ccopts += $(armv7_asm_flags)
@@ -74,6 +75,7 @@ ramstage-y += cpu.S
 ramstage-y += exception.c
 ramstage-y += exception_asm.S
 ramstage-y += mmu.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-c-ccopts += $(armv7_flags)
 ramstage-S-ccopts += $(armv7_asm_flags)

src/arch/arm/armv7/timestamp.c

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <timestamp.h>
+#include <timer.h>
+
+uint64_t timestamp_get(void)
+{
+	struct mono_time timestamp;
+	timer_monotonic_get(&timestamp);
+	return (uint64_t)timestamp.microseconds;
+}
+

src/arch/x86/lib/Makefile.inc

@@ -24,6 +24,9 @@ ramstage-y += ebda.c
 ramstage-y += rom_media.c
 ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
 ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 smm-y += memset.c
 smm-y += memcpy.c

src/arch/x86/lib/timestamp.c

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <cpu/x86/tsc.h>
+#include <timestamp.h>
+
+uint64_t timestamp_get(void)
+{
+	return rdtscll();
+}
+

src/include/cpu/x86/tsc.h

@@ -53,6 +53,11 @@ static inline unsigned long long rdtscll(void)
 	);
 	return val;
 }
+
+static inline uint64_t tsc_to_uint64(tsc_t tstamp)
+{
+       return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
+}
 #endif
 
 #if CONFIG_TSC_CONSTANT_RATE

src/include/timestamp.h

@@ -20,6 +20,8 @@
 #ifndef __TIMESTAMP_H__
 #define __TIMESTAMP_H__
 
+#include <stdint.h>
+
 struct timestamp_entry {
 	uint32_t	entry_id;
 	uint64_t	entry_stamp;
@@ -59,12 +61,10 @@ enum timestamp_id {
 };
 
 #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__))
-#include <cpu/x86/tsc.h>
+void timestamp_init(uint64_t base);
-void timestamp_init(tsc_t base);
+void timestamp_add(enum timestamp_id id, uint64_t ts_time);
-void timestamp_add(enum timestamp_id id, tsc_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
 void timestamp_reinit(void);
-tsc_t get_initial_timestamp(void);
 #else
 #define timestamp_init(base)
 #define timestamp_add(id, time)
@@ -72,4 +72,8 @@ tsc_t get_initial_timestamp(void);
 #define timestamp_reinit()
 #endif
 
+/* Implemented by the architecture code */
+uint64_t timestamp_get(void);
+uint64_t get_initial_timestamp(void);
+
 #endif

src/lib/hardwaremain.c

@@ -452,7 +452,7 @@ static void boot_state_schedule_static_entries(void)
 void main(void)
 {
 	/* Record current time, try to locate timestamps in CBMEM. */
-	timestamp_init(rdtsc());
+	timestamp_init(timestamp_get());
 
 	timestamp_add_now(TS_START_RAMSTAGE);
 	post_code(POST_ENTRY_RAMSTAGE);

src/lib/timestamp.c

@@ -28,16 +28,11 @@
 #define MAX_TIMESTAMPS 30
 
 static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL;
-static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 };
+static uint64_t ts_basetime CAR_GLOBAL = 0;
 
-static void timestamp_stash(enum timestamp_id id, tsc_t ts_time);
+static void timestamp_stash(enum timestamp_id id, uint64_t ts_time);
 
-static uint64_t tsc_to_uint64(tsc_t tstamp)
+static void timestamp_real_init(uint64_t base)
-{
-	return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
-}
-
-static void timestamp_real_init(tsc_t base)
 {
 	struct timestamp_table* tst;
 
@@ -50,14 +45,14 @@ static void timestamp_real_init(tsc_t base)
 		return;
 	}
 
-	tst->base_time = tsc_to_uint64(base);
+	tst->base_time = base;
 	tst->max_entries = MAX_TIMESTAMPS;
 	tst->num_entries = 0;
 
 	car_set_var(ts_table_p, tst);
 }
 
-void timestamp_add(enum timestamp_id id, tsc_t ts_time)
+void timestamp_add(enum timestamp_id id, uint64_t ts_time)
 {
 	struct timestamp_entry *tse;
 	struct timestamp_table *ts_table = NULL;
@@ -75,18 +70,18 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time)
 
 	tse = &ts_table->entries[ts_table->num_entries++];
 	tse->entry_id = id;
-	tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time;
+	tse->entry_stamp = ts_time - ts_table->base_time;
 }
 
 void timestamp_add_now(enum timestamp_id id)
 {
-	timestamp_add(id, rdtsc());
+	timestamp_add(id, timestamp_get());
 }
 
 #define MAX_TIMESTAMP_CACHE 8
 struct timestamp_cache {
 	enum timestamp_id id;
-	tsc_t time;
+	uint64_t time;
 } timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL;
 
 static int timestamp_entries CAR_GLOBAL = 0;
@@ -99,7 +94,7 @@ static int timestamp_entries CAR_GLOBAL = 0;
  * part of CAR migration for romstage, and in ramstage main().
  */
 
-static void timestamp_stash(enum timestamp_id id, tsc_t ts_time)
+static void timestamp_stash(enum timestamp_id id, uint64_t ts_time)
 {
 	struct timestamp_cache *ts_cache = car_get_var(timestamp_cache);
 	int ts_entries = car_get_var(timestamp_entries);
@@ -124,7 +119,7 @@ static void timestamp_do_sync(void)
 	car_set_var(timestamp_entries, 0);
 }
 
-void timestamp_init(tsc_t base)
+void timestamp_init(uint64_t base)
 {
 	if (!boot_cpu())
 		return;

src/mainboard/emulation/qemu-i440fx/romstage.c

@@ -50,7 +50,7 @@ void main(unsigned long bist)
 
 	cbmem_was_initted = !cbmem_recovery(0);
 
-	timestamp_init(rdtsc());
+	timestamp_init(timestamp_get());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 }

src/mainboard/emulation/qemu-q35/romstage.c

@@ -52,7 +52,7 @@ void main(unsigned long bist)
 
 	cbmem_was_initted = !cbmem_recovery(0);
 
-	timestamp_init(rdtsc());
+	timestamp_init(timestamp_get());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 }

src/mainboard/intel/cougar_canyon2/romstage.c

@@ -183,14 +183,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 	post_code(0x40);
 
 #if CONFIG_COLLECT_TIMESTAMPS
-	tsc_t start_romstage_time;
+	uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4);
-	tsc_t before_initram_time;
-
-	start_romstage_time = rdtsc();
-
 	/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
-	pci_write_config32(PCI_DEV(0, 27, 0), 0x2c,  start_romstage_time.lo >> 4 |
+	pci_write_config32(PCI_DEV(0, 27, 0), 0x2c,  start_romstage_time);
-			start_romstage_time.lo << 28);
 #endif
 
 	pch_enable_lpc();
@@ -240,11 +235,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
 	post_code(0x48);
 
 #if CONFIG_COLLECT_TIMESTAMPS
-	before_initram_time= rdtsc();
+	uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4);
 	/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
-	pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time.lo >> 4 |
+	pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time);
-			before_initram_time.lo << 28);
-
 #endif
 
   /*
@@ -267,20 +260,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	void *cbmem_hob_ptr;
 
 #if CONFIG_COLLECT_TIMESTAMPS
-	tsc_t start_romstage_time;
+	uint64_t after_initram_time = timestamp_get();
-	tsc_t base_time;
+	uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4;
-	tsc_t before_initram_time;
+	uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4;
-	tsc_t after_initram_time = rdtsc();
-	u32 timebase = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0);
-	u32 time_romstage_start = pci_read_config32(PCI_DEV(0, 27, 0), 0x2c);
-	u32 time_before_initram = pci_read_config32(PCI_DEV(0, 27, 0), 0x14);
-
-	base_time.lo = timebase << 4;
-	base_time.hi = timebase >> 28;
-	start_romstage_time.lo = time_romstage_start << 4;
-	start_romstage_time.hi = time_romstage_start >> 28;
-	before_initram_time.lo = time_before_initram << 4;
-	before_initram_time.hi = time_before_initram >> 28;
 #endif
 
 	/*
@@ -335,13 +317,11 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
 	post_code(0x4f);
 
-#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(get_initial_timestamp());
-	timestamp_init(base_time);
 	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
 	timestamp_add(TS_BEFORE_INITRAM, before_initram_time );
 	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
-#endif
 
 	/* Load the ramstage. */
 	copy_and_run();
@@ -353,3 +333,8 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 	/* No overrides needed */
 	return;
 }
+
+uint64_t get_initial_timestamp(void)
+{
+	return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4;
+}

src/mainboard/lenovo/x201/romstage.c

@@ -190,7 +190,7 @@ void main(unsigned long bist)
 	int s3resume = 0;
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
 
-	timestamp_init(rdtsc ());
+	timestamp_init(timestamp_get());
 
 	timestamp_add_now(TS_START_ROMSTAGE);
 

src/mainboard/packardbell/ms2290/romstage.c

@@ -175,7 +175,7 @@ void main(unsigned long bist)
 	int s3resume = 0;
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
 
-	timestamp_init(rdtsc ());
+	timestamp_init(timestamp_get());
 
 	/* SERR pin is confused on reset. Clear NMI.  */
 	outb(4, 0x61);

src/mainboard/via/epia-m850/romstage.c

@@ -46,7 +46,7 @@ void main(unsigned long bist)
 {
 	u32 tolm;
 
-	timestamp_init(rdtsc());
+	timestamp_init(timestamp_get());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* First thing we need to do on the VX900, before anything else */

src/soc/intel/baytrail/romstage/romstage.c

@@ -44,20 +44,6 @@
 #include <baytrail/smm.h>
 #include <baytrail/spi.h>
 
-static inline uint64_t timestamp_get(void)
-{
-	return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
-	tsc_t tsc = {
-		.lo = ts,
-		.hi = ts >> 32,
-	};
-	return tsc;
-}
-
 /* The cache-as-ram assembly file calls romstage_main() after setting up
  * cache-as-ram.  romstage_main() will then call the mainboards's
  * mainboard_romstage_entry() function. That function then calls
@@ -274,10 +260,10 @@ void romstage_common(struct romstage_params *params)
 	chromeos_init(prev_sleep_state);
 
 	/* Save timestamp information. */
-	timestamp_init(ts64_to_tsc(params->ts.times[0]));
+	timestamp_init(params->ts.times[0]);
-	timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
+	timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
-	timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
+	timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
-	timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+	timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
 }
 
 void asmlinkage romstage_after_car(void)

src/soc/intel/broadwell/romstage/romstage.c

@@ -38,20 +38,6 @@
 #include <broadwell/romstage.h>
 #include <broadwell/spi.h>
 
-static inline uint64_t timestamp_get(void)
-{
-	return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
-	tsc_t tsc = {
-		.lo = ts,
-		.hi = ts >> 32,
-	};
-	return tsc;
-}
-
 static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
 {
 	struct romstage_timestamps *rt = &rp->ts;
@@ -142,10 +128,10 @@ void romstage_common(struct romstage_params *params)
 	chromeos_init(params->power_state->prev_sleep_state);
 
 	/* Save timestamp information. */
-	timestamp_init(ts64_to_tsc(params->ts.times[0]));
+	timestamp_init(params->ts.times[0]);
-	timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
+	timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
-	timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
+	timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
-	timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+	timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
 }
 
 void asmlinkage romstage_after_car(void)

src/soc/intel/fsp_baytrail/romstage/romstage.c

@@ -221,10 +221,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	struct romstage_handoff *handoff;
 
 #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	tsc_t after_initram_time = rdtsc();
+	uint64_t after_initram_time = timestamp_get();
-	tsc_t base_time;
-	base_time.hi = 0;
-	base_time.lo = 0;
 #endif
 
 	post_code(0x4a);
@@ -244,9 +241,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 
 	report_platform_info();
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	after_initram_time = rdtsc();
-#endif
 	post_code(0x4b);
 
 	late_mainboard_romstage_entry();
@@ -271,13 +265,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-
+	timestamp_init(get_initial_timestamp());
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	timestamp_init(base_time);
-	timestamp_reinit();
 	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
-#endif
 
 	post_code(0x4f);
 
@@ -285,3 +275,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	copy_and_run();
 	while (1);
 }
+
+uint64_t get_initial_timestamp(void)
+{
+	return 0;
+}

src/southbridge/intel/bd82x6x/early_pch.c

@@ -20,21 +20,19 @@
 
 #include <arch/io.h>
 #include <timestamp.h>
+#include <cpu/x86/tsc.h>
 #include "pch.h"
 #include <arch/acpi.h>
 #include <console/console.h>
 
-#if CONFIG_COLLECT_TIMESTAMPS
+uint64_t get_initial_timestamp(void)
-tsc_t get_initial_timestamp(void)
 {
 	tsc_t base_time = {
 		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
 		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
 	};
-	return base_time;
+	return tsc_to_uint64(base_time);
 }
-#endif
-
 
 int southbridge_detect_s3_resume(void)
 {

src/southbridge/intel/fsp_rangeley/romstage.c

@@ -95,11 +95,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	void *cbmem_hob_ptr;
 
 #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
-	tsc_t after_initram_time = rdtsc();
+	uint64_t after_initram_time = timestamp_get();
-	tsc_t base_time;
-	base_time.hi = 0;
-	base_time.lo = 0;
 #endif
+
 	post_code(0x48);
 	printk(BIOS_DEBUG, "%s status: %x  hob_list_ptr: %x\n",
 		__func__, (u32) status, (u32) hob_list_ptr);
@@ -129,12 +127,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+	timestamp_init(get_initial_timestamp());
-	timestamp_init(base_time);
-	timestamp_reinit();
 	timestamp_add(TS_AFTER_INITRAM, after_initram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
-#endif
 
 	post_code(0x4f);
 
@@ -142,3 +137,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	copy_and_run();
 	while (1);
 }
+
+uint64_t get_initial_timestamp(void)
+{
+	return 0;
+}

src/southbridge/intel/i82801gx/early_lpc.c

@@ -20,20 +20,19 @@
 
 #include <arch/io.h>
 #include <timestamp.h>
+#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801gx.h"
 
-#if CONFIG_COLLECT_TIMESTAMPS
+uint64_t get_initial_timestamp(void)
-tsc_t get_initial_timestamp(void)
 {
 	tsc_t base_time = {
 		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
 		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
 	};
-	return base_time;
+	return tsc_to_uint64(base_time);
 }
-#endif
 
 int southbridge_detect_s3_resume(void)
 {

src/southbridge/intel/lynxpoint/early_pch.c

@@ -23,6 +23,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <timestamp.h>
+#include <cpu/x86/tsc.h>
 #include <elog.h>
 #include "pch.h"
 #include "chip.h"
@@ -71,16 +72,14 @@ static void pch_generic_setup(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-#if CONFIG_COLLECT_TIMESTAMPS
+uint64_t get_initial_timestamp(void)
-tsc_t get_initial_timestamp(void)
 {
 	tsc_t base_time = {
 		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
 		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
 	};
-	return base_time;
+	return tsc_to_uint64(base_time);
 }
-#endif
 
 static int sleep_type_s3(void)
 {