From f710bf65dcd824854a5d0c2020ebd636dd08a861 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 3 Oct 2020 08:57:57 +0200 Subject: [PATCH 001/354] superio/nuvoton/common: Collapse two if statements There are more devices requiring this code, so avoid duplicating the if block over and over. Change-Id: Ib4f787e3c883b1fec941de77bc8e19ccf0d5224c Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/45970 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/superio/nuvoton/common/early_serial.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 22d882ef1a..cc21f40d2a 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -52,11 +52,8 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) nuvoton_pnp_enter_conf_state(dev); - if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A)) - /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x40); - - if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) + if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || + CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x40); From 288426d35cd7f3dcf75524d2228f06267da288f2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Oct 2020 16:52:26 +0200 Subject: [PATCH 002/354] include/acpi/acpi.h: Add ACPI_DSDT_REV_1 macro Change-Id: Ie044f786e5deae3a1317091de67dc03c74531bfb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45786 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/include/acpi/acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 7b0f339bc5..a9ec07754d 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -41,6 +41,7 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ +#define ACPI_DSDT_REV_1 0x01 /* DSDT revision: ACPI v1 */ #define ACPI_DSDT_REV_2 0x02 /* DSDT revision: ACPI v2.0 and greater */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) From a1ddd2a15d3238befdf257c33e569e6e5773f93f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 12:42:09 -0700 Subject: [PATCH 003/354] drivers/wifi/generic: Add support for generating SMBIOS data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change adds support in generic WiFi driver in coreboot to generate SMBIOS data for the WiFi device. Currently, this is used only for Intel WiFi devices and the function is copied over from Intel WiFi driver in coreboot. This change is done in preparation for getting rid of the separate chip driver for Intel WiFi in coreboot. BUG=b:169802515 BRANCH=zork Change-Id: If3c056718bdc57f6976ce8e3f8acc7665ec3ccd7 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46034 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/drivers/wifi/generic/generic.c | 41 ++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 0705731e58..e551bf3637 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -6,8 +6,10 @@ #include #include #include +#include #include #include +#include #include #include #include "chip.h" @@ -244,6 +246,42 @@ static void wifi_pci_dev_init(struct device *dev) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current) +{ + struct smbios_type_intel_wifi { + u8 type; + u8 length; + u16 handle; + u8 str; + u8 eos[2]; + } __packed; + + struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + int len = sizeof(struct smbios_type_intel_wifi); + + memset(t, 0, sizeof(struct smbios_type_intel_wifi)); + t->type = 0x85; + t->length = len - 2; + t->handle = *handle; + /* Intel wifi driver expects this string to be in the table 0x85. */ + t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + *handle += 1; + return len; +} + +static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) +{ + if (dev->vendor == PCI_VENDOR_ID_INTEL) + return smbios_write_intel_wifi(dev, handle, current); + + return 0; +} +#endif + struct device_operations wifi_generic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -252,6 +290,9 @@ struct device_operations wifi_generic_ops = { .ops_pci = &pci_dev_ops_pci, .acpi_name = wifi_generic_acpi_name, .acpi_fill_ssdt = wifi_generic_fill_ssdt_generator, +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = smbios_write_wifi, +#endif }; static void wifi_generic_enable(struct device *dev) From a266d1e63a3e695e85e922a853da928f1807e534 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 12:52:54 -0700 Subject: [PATCH 004/354] mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Michael Niewöhner --- src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 4 ++-- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +- .../google/dedede/variants/waddledoo/overridetree.cb | 2 +- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 +- src/mainboard/google/eve/devicetree.cb | 2 +- src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/glados/devicetree.cb | 2 +- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 4 ++-- src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 4 ++-- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 2 +- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/reef/variants/coral/devicetree.cb | 2 +- src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- src/mainboard/google/reef/variants/sand/devicetree.cb | 2 +- src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 +- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 2 +- .../intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 2 +- .../intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 2 +- .../intel/coffeelake_rvp/variants/cfl_s/overridetree.cb | 2 +- .../intel/coffeelake_rvp/variants/cfl_u/overridetree.cb | 2 +- .../intel/coffeelake_rvp/variants/cml_u/overridetree.cb | 2 +- .../intel/coffeelake_rvp/variants/whl_u/overridetree.cb | 2 +- src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb | 4 ++-- src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 4 ++-- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- .../prodrive/hermes/variants/baseboard/overridetree.cb | 2 +- src/mainboard/system76/lemp9/devicetree.cb | 4 ++-- src/soc/intel/tigerlake/chipset.cb | 2 +- 41 files changed, 47 insertions(+), 47 deletions(-) diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3ee20e9c4b..8f256ad7fb 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -89,7 +89,7 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi # CNVi wifi + chip drivers/wifi/generic # CNVi wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end end @@ -141,7 +141,7 @@ chip soc/intel/cannonlake end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 - chip drivers/intel/wifi + chip drivers/wifi/generic device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) end register "PcieRpEnable[7]" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2b7a5139c6..b7aa11da31 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 969bebba53..c306b523ea 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -247,7 +247,7 @@ chip soc/intel/jasperlake end end device pci 1c.7 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" device pci 00.0 on end end diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 52e689c177..775c54815e 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -245,7 +245,7 @@ chip soc/intel/tigerlake device pci 14.1 off end # USB 3.2 1x1 xDCI HC device pci 14.2 on end # Shared SRAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi WiFi end diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index ed7eb95d0d..aa6af87c3a 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -328,7 +328,7 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index d9415212d7..a2550bb475 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -380,7 +380,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index bc29dc63af..9c11e807e8 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -400,7 +400,7 @@ chip soc/intel/skylake end end # PCI Express Port 3 device pci 1c.3 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 98b678a5cf..12312e980a 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -118,7 +118,7 @@ chip soc/intel/skylake device pci 19.1 off end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a4e07e9556..10ad029e40 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -297,7 +297,7 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end @@ -333,7 +333,7 @@ chip soc/intel/cannonlake device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express port 13 device pci 1d.5 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" device pci 00.0 on end end diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 3fef757dc9..6d77116c89 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -114,7 +114,7 @@ chip soc/intel/apollolake device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Gaussian Mixture Model (GMM) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0A_CNVI_PME_STS" device pci 0c.0 on end # - CNVi end @@ -136,7 +136,7 @@ chip soc/intel/apollolake device pci 11.0 off end # - ISH device pci 12.0 off end # - SATA device pci 13.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_11" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4496dd9af6..9f9d9518d6 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -344,7 +344,7 @@ chip soc/intel/skylake end end # I2C #4 - Audio device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 14b8b09923..0dc9131aaf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -359,7 +359,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 57444a92a5..167bd036d6 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -427,7 +427,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 025b82b70a..ed21492946 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -388,7 +388,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 21f0b80274..0a29601c39 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -402,7 +402,7 @@ chip soc/intel/skylake end end # I2C #4 - Audio device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW2_01" device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 0d31bca856..591e0fb478 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -354,7 +354,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 off end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 477166a422..b3570d73b2 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -333,7 +333,7 @@ chip soc/intel/skylake end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index da80b8ea9a..a1b7a4c335 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -147,7 +147,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index f2fc3a61fa..fd456ebb54 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -147,7 +147,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 920431b8d2..0dbaa29552 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -156,7 +156,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index aba1227de1..ba19369f18 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -143,7 +143,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index ad8c808d88..1a007e6545 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -152,7 +152,7 @@ chip soc/intel/apollolake device pci 13.2 off end # - Root Port 4 - PCIe-A 2 device pci 13.3 off end # - Root Port 5 - PCIe-A 3 device pci 14.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW3_00" device pci 00.0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9a4c6dda10..b1d9a36159 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index a76e2ed2e9..e1ee6c9be8 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -317,7 +317,7 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 898b5ae271..330accca40 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -432,7 +432,7 @@ chip soc/intel/tigerlake device ref cnvi_bt on end device ref south_xhci on end device ref shared_ram on end - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device ref cnvi_wifi on end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index a6b0039d0e..47a2e91cb5 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -90,7 +90,7 @@ chip soc/intel/alderlake end # USB3.1 xHCI device pci 14.1 off end # USB3.1 xDCI device pci 14.2 off end # Shared RAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi: WiFi end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index f24e191256..e10059887e 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -94,7 +94,7 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 1bd4bfec28..bf7aa1e962 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -75,7 +75,7 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index 37b86c6be0..77e475aa9d 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -92,7 +92,7 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[10]" = "10" device domain 0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index f48c9b49a8..433a03a9e7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -61,7 +61,7 @@ chip soc/intel/cannonlake }" device domain 0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 28b33cf5f4..560a7c2dad 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -80,7 +80,7 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 89d60366a7..9592e90b5d 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -65,7 +65,7 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 40f17cebe5..49303da030 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -280,7 +280,7 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end @@ -309,7 +309,7 @@ chip soc/intel/icelake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index b12c0f7b6c..a1c32c99be 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -280,7 +280,7 @@ chip soc/intel/icelake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end @@ -309,7 +309,7 @@ chip soc/intel/icelake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fc96719643..b9aec378fb 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -299,7 +299,7 @@ chip soc/intel/jasperlake end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2b7a0e3482..3afff4506e 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -243,7 +243,7 @@ chip soc/intel/skylake end end # I2C #4 device pci 1c.0 on - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" device pci 00.0 on end end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 384bc1bb6e..2abdce4c72 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -230,7 +230,7 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 410d06b38a..b46a1cf401 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -234,7 +234,7 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 01b9537e13..071fc5fc95 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -166,7 +166,7 @@ chip soc/intel/cannonlake device pci 02.0 on # Integrated Graphics Device register "InternalGfx" = "1" end - chip drivers/intel/wifi + chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi end diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index b1899417b9..277570ece9 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -89,7 +89,7 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi # CNVi wifi + chip drivers/wifi/generic # CNVi wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end end @@ -148,7 +148,7 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" - chip drivers/intel/wifi + chip drivers/wifi/generic device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 0d2b7a231f..4f55125528 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -26,7 +26,7 @@ chip soc/intel/tigerlake device pci 14.0 alias south_xhci off end device pci 14.1 alias south_xdci off end device pci 14.2 alias shared_ram off end - chip drivers/intel/wifi + chip drivers/wifi/generic device pci 14.3 alias cnvi_wifi off end end device pci 15.0 alias i2c0 off end From 5e0033987eb8e8ba3897bb8a3d0fecc66e5be82e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 17:34:04 -0700 Subject: [PATCH 005/354] drivers/{wifi/generic,intel/wifi}: Drop dependency on HAVE_ACPI_TABLES MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change drops the dependency of DRIVERS_WIFI_GENERIC on HAVE_ACPI_TABLES as the driver provides operations other than the ACPI support for WiFi devices. Since the dependency is now dropped, ACPI operations in generic.c are guarded by CONFIG(HAVE_ACPI_TABLES). BUG=b:169802515 BRANCH=zork Change-Id: I16444a9d842a6742e3c97ef04c4f18e93e6cdaa9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46037 Reviewed-by: Michael Niewöhner Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/drivers/intel/wifi/Kconfig | 2 +- src/drivers/wifi/generic/Kconfig | 1 - src/drivers/wifi/generic/generic.c | 4 ++++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 83df82233e..5454e9768e 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -2,7 +2,7 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on PCI default y if PCIEXP_PLUGIN_SUPPORT - select DRIVERS_WIFI_GENERIC if HAVE_ACPI_TABLES + select DRIVERS_WIFI_GENERIC help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/wifi/generic/Kconfig b/src/drivers/wifi/generic/Kconfig index 049a952e71..ddd2be9504 100644 --- a/src/drivers/wifi/generic/Kconfig +++ b/src/drivers/wifi/generic/Kconfig @@ -1,7 +1,6 @@ config DRIVERS_WIFI_GENERIC bool default n - depends on HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI tables that are common to WiFi chipsets from multiple vendors. diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index e551bf3637..bb36861cba 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -37,6 +37,7 @@ */ #define WIFI_ACPI_NAME_MAX_LEN 5 +#if CONFIG(HAVE_ACPI_TABLES) __weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { @@ -239,6 +240,7 @@ static void wifi_generic_fill_ssdt_generator(const struct device *dev) { wifi_generic_fill_ssdt(dev, dev->chip_info); } +#endif static void wifi_pci_dev_init(struct device *dev) { @@ -288,8 +290,10 @@ struct device_operations wifi_generic_ops = { .enable_resources = pci_dev_enable_resources, .init = wifi_pci_dev_init, .ops_pci = &pci_dev_ops_pci, +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = wifi_generic_acpi_name, .acpi_fill_ssdt = wifi_generic_fill_ssdt_generator, +#endif #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = smbios_write_wifi, #endif From f223863261bbe73113f94ec3fee200b19fdce24c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 17:45:22 -0700 Subject: [PATCH 006/354] wifi: Move addition of CBFS SAR file to wifi/generic/Makefile.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change moves the addition of CBFS SAR file from intel/wifi/Makefile.inc to wifi/generic/Makefile.inc to keep it in the same sub-directory as the Kconfig definition. BUG=b:169802515 BRANCH=zork Change-Id: I7ee33232b6a07bbf929f3a79fabe89130fb6fa6f Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46039 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Martin Roth Reviewed-by: Rob Barnes Reviewed-by: Karthik Ramasubramanian --- src/drivers/intel/wifi/Makefile.inc | 4 ---- src/drivers/wifi/generic/Makefile.inc | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/wifi/Makefile.inc b/src/drivers/intel/wifi/Makefile.inc index 57f60afb99..9bfdd79376 100644 --- a/src/drivers/intel/wifi/Makefile.inc +++ b/src/drivers/intel/wifi/Makefile.inc @@ -1,7 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c - -cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex -wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH)) -wifi_sar_defaults.hex-type := raw diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc index 6240c7146a..407041afce 100644 --- a/src/drivers/wifi/generic/Makefile.inc +++ b/src/drivers/wifi/generic/Makefile.inc @@ -1 +1,5 @@ ramstage-$(CONFIG_DRIVERS_WIFI_GENERIC) += generic.c + +cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex +wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH)) +wifi_sar_defaults.hex-type := raw From c766d7ca56f2a995c8b5ea14446883590cf50cf1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 8 Oct 2020 09:35:37 +0200 Subject: [PATCH 007/354] mb/google/zork: Convert to ASL 2.0 syntax Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../include/baseboard/acpi/thermal.asl | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl index 8f5aa6ab5e..dec33ec5dd 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -21,10 +21,10 @@ Scope (\_TZ) /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -50,23 +50,23 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { /* Get temperature from EC in deci-kelvin */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) /* Critical temperature in deci-kelvin */ - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 /* Wait 1 second for EC to re-poll */ Sleep (1000) /* Re-read temperature from EC */ - Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) From 4744ca7d056648198fd73cf4bb4c0bca44e27acc Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 12 Oct 2020 17:58:45 +0800 Subject: [PATCH 008/354] volteer: Create elemi variant Create the elemi variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:170604353 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELEMI Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- src/mainboard/google/volteer/Kconfig | 2 ++ src/mainboard/google/volteer/Kconfig.name | 4 ++++ .../volteer/variants/elemi/include/variant/ec.h | 8 ++++++++ .../volteer/variants/elemi/include/variant/gpio.h | 15 +++++++++++++++ .../google/volteer/variants/elemi/overridetree.cb | 6 ++++++ 5 files changed, 35 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/elemi/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/elemi/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 58ff4eb270..edc9c91034 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -92,6 +92,7 @@ config MAINBOARD_PART_NUMBER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR + default "Elemi" if BOARD_GOOGLE_ELEMI config MAX_CPUS int @@ -129,6 +130,7 @@ config VARIANT_DIR default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR + default "elemi" if BOARD_GOOGLE_ELEMI config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 2817448452..f59d82b850 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -67,3 +67,7 @@ config BOARD_GOOGLE_VOXEL config BOARD_GOOGLE_BOLDAR bool "-> Boldar" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_ELEMI + bool "-> Elemi" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h b/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h b/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From 2d49f220ea8e67da6ed8049a71c9415d16420cd0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 12 Oct 2020 10:01:28 -0600 Subject: [PATCH 009/354] vendorcode/google/dram_part_num: Lower the severity of debug statement DRAM part number may not be provisioned in CBI during early stages of development. Logging the debug statement with error severity interferes with some of the test tools. Lower the severity of debug statement to BIOS_DEBUG. BUG=b:170529094 TEST=Build and boot to ChromeOS in Drawlat. Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46299 Reviewed-by: Angel Pons Reviewed-by: Justin TerAvest Tested-by: build bot (Jenkins) --- src/vendorcode/google/chromeos/dram_part_num_override.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/google/chromeos/dram_part_num_override.c b/src/vendorcode/google/chromeos/dram_part_num_override.c index d624e13c7e..4b934fe8ef 100644 --- a/src/vendorcode/google/chromeos/dram_part_num_override.c +++ b/src/vendorcode/google/chromeos/dram_part_num_override.c @@ -16,8 +16,8 @@ const char *mainboard_get_dram_part_num(void) if (part_num_state == PART_NUM_NOT_READ) { if (google_chromeec_cbi_get_dram_part_num(part_num_store, sizeof(part_num_store)) < 0) { - printk(BIOS_ERR, - "ERROR: Couldn't obtain DRAM part number from CBI\n"); + printk(BIOS_DEBUG, + "Couldn't obtain DRAM part number from CBI\n"); part_num_state = PART_NUM_NOT_IN_CBI; } else { part_num_state = PART_NUM_AVAILABLE; From 90d00dea55073a9c2d0d39c78a40840cdb17feaf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 5 Oct 2020 16:38:53 +0200 Subject: [PATCH 010/354] {src/mb,util/autoport}: Use macro for DSDT revision Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/51nb/x210/dsdt.asl | 2 +- src/mainboard/acer/g43t-am3/dsdt.asl | 2 +- src/mainboard/amd/gardenia/dsdt.asl | 2 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/mandolin/dsdt.asl | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/padmelon/dsdt.asl | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/union_station/dsdt.asl | 2 +- src/mainboard/aopen/dxplplusu/dsdt.asl | 2 +- src/mainboard/apple/macbook21/dsdt.asl | 2 +- src/mainboard/apple/macbookair4_2/dsdt.asl | 2 +- src/mainboard/asrock/b75pro3-m/dsdt.asl | 2 +- src/mainboard/asrock/b85m_pro4/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- src/mainboard/asrock/g41c-gs/dsdt.asl | 2 +- src/mainboard/asrock/h110m/dsdt.asl | 2 +- src/mainboard/asrock/h81m-hds/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asus/a88xm-e/dsdt.asl | 2 +- src/mainboard/asus/am1i-a/dsdt.asl | 2 +- src/mainboard/asus/f2a85-m/dsdt.asl | 2 +- src/mainboard/asus/h61m-cs/dsdt.asl | 2 +- src/mainboard/asus/maximus_iv_gene-z/dsdt.asl | 2 +- src/mainboard/asus/p2b/dsdt.asl | 10 +++++++++- src/mainboard/asus/p5gc-mx/dsdt.asl | 2 +- src/mainboard/asus/p5qc/dsdt.asl | 2 +- src/mainboard/asus/p5ql-em/dsdt.asl | 2 +- src/mainboard/asus/p5qpl-am/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_lx/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl | 2 +- src/mainboard/asus/p8h61-m_pro/dsdt.asl | 2 +- src/mainboard/asus/p8z77-m_pro/dsdt.asl | 2 +- src/mainboard/asus/p8z77-v_lx2/dsdt.asl | 2 +- src/mainboard/bap/ode_e20XX/dsdt.asl | 2 +- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 +- src/mainboard/biostar/am1ml/dsdt.asl | 2 +- src/mainboard/biostar/th61-itx/dsdt.asl | 2 +- src/mainboard/bostentech/gbyt4/dsdt.asl | 2 +- src/mainboard/clevo/cml-u/dsdt.asl | 2 +- src/mainboard/compulab/intense_pc/dsdt.asl | 2 +- src/mainboard/dell/optiplex_9010/dsdt.asl | 2 +- src/mainboard/elmex/pcm205400/dsdt.asl | 2 +- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 2 +- src/mainboard/emulation/qemu-q35/dsdt.asl | 2 +- src/mainboard/facebook/fbg1701/dsdt.asl | 2 +- src/mainboard/facebook/monolith/dsdt.asl | 2 +- src/mainboard/foxconn/d41s/dsdt.asl | 2 +- src/mainboard/foxconn/g41s-k/dsdt.asl | 2 +- src/mainboard/getac/p470/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 2 +- src/mainboard/gigabyte/ga-h61m-series/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 +- src/mainboard/google/auron/dsdt.asl | 2 +- src/mainboard/google/beltino/dsdt.asl | 2 +- src/mainboard/google/butterfly/dsdt.asl | 2 +- src/mainboard/google/cyan/dsdt.asl | 2 +- src/mainboard/google/dedede/dsdt.asl | 2 +- src/mainboard/google/deltaur/dsdt.asl | 2 +- src/mainboard/google/drallion/dsdt.asl | 2 +- src/mainboard/google/eve/dsdt.asl | 2 +- src/mainboard/google/fizz/dsdt.asl | 2 +- src/mainboard/google/glados/dsdt.asl | 2 +- src/mainboard/google/hatch/dsdt.asl | 2 +- src/mainboard/google/jecht/dsdt.asl | 2 +- src/mainboard/google/kahlee/dsdt.asl | 2 +- src/mainboard/google/link/dsdt.asl | 2 +- src/mainboard/google/octopus/dsdt.asl | 2 +- src/mainboard/google/parrot/dsdt.asl | 2 +- src/mainboard/google/poppy/dsdt.asl | 2 +- src/mainboard/google/rambi/dsdt.asl | 2 +- src/mainboard/google/reef/dsdt.asl | 2 +- src/mainboard/google/sarien/dsdt.asl | 2 +- src/mainboard/google/slippy/dsdt.asl | 2 +- src/mainboard/google/stout/dsdt.asl | 2 +- src/mainboard/google/volteer/dsdt.asl | 2 +- src/mainboard/google/zork/dsdt.asl | 2 +- src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 +- src/mainboard/hp/snb_ivb_laptops/dsdt.asl | 2 +- src/mainboard/hp/z220_sff_workstation/dsdt.asl | 2 +- src/mainboard/ibase/mb899/dsdt.asl | 2 +- src/mainboard/intel/apollolake_rvp/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/dsdt.asl | 2 +- src/mainboard/intel/cannonlake_rvp/dsdt.asl | 2 +- src/mainboard/intel/cedarisland_crb/dsdt.asl | 2 +- src/mainboard/intel/coffeelake_rvp/dsdt.asl | 2 +- src/mainboard/intel/d510mo/dsdt.asl | 2 +- src/mainboard/intel/d945gclf/dsdt.asl | 2 +- src/mainboard/intel/dcp847ske/dsdt.asl | 2 +- src/mainboard/intel/dg41wv/dsdt.asl | 2 +- src/mainboard/intel/dg43gt/dsdt.asl | 2 +- src/mainboard/intel/emeraldlake2/dsdt.asl | 2 +- src/mainboard/intel/galileo/dsdt.asl | 2 +- src/mainboard/intel/glkrvp/dsdt.asl | 2 +- src/mainboard/intel/harcuvar/dsdt.asl | 2 +- src/mainboard/intel/icelake_rvp/dsdt.asl | 2 +- src/mainboard/intel/jasperlake_rvp/dsdt.asl | 2 +- src/mainboard/intel/kblrvp/dsdt.asl | 2 +- src/mainboard/intel/kunimitsu/dsdt.asl | 2 +- src/mainboard/intel/leafhill/dsdt.asl | 2 +- src/mainboard/intel/minnow3/dsdt.asl | 2 +- src/mainboard/intel/saddlebrook/dsdt.asl | 2 +- src/mainboard/intel/strago/dsdt.asl | 2 +- src/mainboard/intel/tglrvp/dsdt.asl | 2 +- src/mainboard/intel/wtm2/dsdt.asl | 2 +- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 2 +- src/mainboard/kontron/986lcd-m/dsdt.asl | 2 +- src/mainboard/kontron/ktqm77/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lenovo/l520/dsdt.asl | 2 +- src/mainboard/lenovo/s230u/dsdt.asl | 2 +- src/mainboard/lenovo/t400/dsdt.asl | 2 +- src/mainboard/lenovo/t410/dsdt.asl | 2 +- src/mainboard/lenovo/t420/dsdt.asl | 2 +- src/mainboard/lenovo/t420s/dsdt.asl | 2 +- src/mainboard/lenovo/t430/dsdt.asl | 2 +- src/mainboard/lenovo/t430s/dsdt.asl | 2 +- src/mainboard/lenovo/t440p/dsdt.asl | 2 +- src/mainboard/lenovo/t520/dsdt.asl | 2 +- src/mainboard/lenovo/t530/dsdt.asl | 2 +- src/mainboard/lenovo/t60/dsdt.asl | 2 +- src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | 2 +- src/mainboard/lenovo/x131e/dsdt.asl | 2 +- src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 2 +- src/mainboard/lenovo/x200/dsdt.asl | 2 +- src/mainboard/lenovo/x201/dsdt.asl | 2 +- src/mainboard/lenovo/x220/dsdt.asl | 2 +- src/mainboard/lenovo/x230/dsdt.asl | 2 +- src/mainboard/lenovo/x60/dsdt.asl | 2 +- src/mainboard/libretrend/lt1000/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/msi/ms7707/dsdt.asl | 2 +- src/mainboard/msi/ms7721/dsdt.asl | 2 +- src/mainboard/ocp/deltalake/dsdt.asl | 2 +- src/mainboard/ocp/tiogapass/dsdt.asl | 2 +- src/mainboard/packardbell/ms2290/dsdt.asl | 2 +- src/mainboard/pcengines/apu1/dsdt.asl | 2 +- src/mainboard/pcengines/apu2/dsdt.asl | 2 +- src/mainboard/portwell/m107/dsdt.asl | 2 +- src/mainboard/prodrive/hermes/dsdt.asl | 2 +- src/mainboard/protectli/vault_bsw/dsdt.asl | 2 +- src/mainboard/protectli/vault_kbl/dsdt.asl | 2 +- src/mainboard/purism/librem_bdw/dsdt.asl | 2 +- src/mainboard/purism/librem_skl/dsdt.asl | 2 +- src/mainboard/purism/librem_whl/dsdt.asl | 2 +- src/mainboard/razer/blade_stealth_kbl/dsdt.asl | 6 +++--- src/mainboard/roda/rk886ex/dsdt.asl | 2 +- src/mainboard/roda/rk9/dsdt.asl | 2 +- src/mainboard/roda/rv11/dsdt.asl | 2 +- src/mainboard/samsung/lumpy/dsdt.asl | 2 +- src/mainboard/samsung/stumpy/dsdt.asl | 2 +- src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 2 +- src/mainboard/scaleway/tagada/dsdt.asl | 2 +- src/mainboard/siemens/mc_apl1/dsdt.asl | 2 +- src/mainboard/supermicro/x10slm-f/dsdt.asl | 9 ++++++++- src/mainboard/supermicro/x11-lga1151-series/dsdt.asl | 2 +- src/mainboard/supermicro/x9scl/dsdt.asl | 2 +- src/mainboard/system76/lemp9/dsdt.asl | 2 +- src/mainboard/up/squared/dsdt.asl | 2 +- util/autoport/main.go | 2 +- 168 files changed, 185 insertions(+), 170 deletions(-) diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index d56fccbde1..58f5511510 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v5.0 + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/acer/g43t-am3/dsdt.asl b/src/mainboard/acer/g43t-am3/dsdt.asl index cf2395cf9a..dacd76cc46 100644 --- a/src/mainboard/acer/g43t-am3/dsdt.asl +++ b/src/mainboard/acer/g43t-am3/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090811 // OEM revision diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index a2de6351c1..5606bed05b 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index a395d248cf..8dadb3a9b6 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 06612a8904..062620285f 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 716c7919e5..0be106aaa6 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index b04567a948..f9d9af2c04 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index a395d248cf..8dadb3a9b6 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index a395d248cf..8dadb3a9b6 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index b04567a948..f9d9af2c04 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index a395d248cf..8dadb3a9b6 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 613de6ff66..4227ff2b06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20111103 // OEM revision diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 9b5ba55018..4ea20e5be5 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index e68c018226..a25c8b64cb 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 20cca3e259..2f919170ad 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index bbc9630a28..ea6dde65c1 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index d1896adf22..137796c57c 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 457c927397..3820b945b1 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 8fec596fe1..dd55ba8bbd 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v3.0 */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181031 /* OEM Revision */ diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl index aac9c84cd5..a4f49b94fd 100644 --- a/src/mainboard/asus/a88xm-e/dsdt.asl +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 13e97dc73c..00b78cf52c 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index 634a92861e..a6e4726929 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index ded71a1548..38604c5583 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index 60d6dc5a63..ec3b9ea140 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20171231 /* OEM Revision */ diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index e1bda176a9..16278aa757 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -9,7 +9,15 @@ #define SUPERIO_SHOW_LPT #include -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 1 + ) { /* \_SB scope defining the main processor is generated in SSDT. */ diff --git a/src/mainboard/asus/p5gc-mx/dsdt.asl b/src/mainboard/asus/p5gc-mx/dsdt.asl index 0a9ab0fe41..4e43cc47c3 100644 --- a/src/mainboard/asus/p5gc-mx/dsdt.asl +++ b/src/mainboard/asus/p5gc-mx/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index cd885c8f05..fa8820855e 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00000001 // OEM revision diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl index 2981dc6326..e0290979af 100644 --- a/src/mainboard/asus/p5ql-em/dsdt.asl +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00000001 // OEM revision diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index 60d6dc5a63..ec3b9ea140 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20171231 /* OEM Revision */ diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl index fba6cc78eb..f83653051f 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 01d1fe633d..6a248b24dd 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index a5ab91d611..ba58cf2412 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl index 6fa3b5576c..c49090e154 100644 --- a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 01502b2839..69625ad9c9 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/biostar/th61-itx/dsdt.asl b/src/mainboard/biostar/th61-itx/dsdt.asl index 18908d38a7..60a74677fb 100644 --- a/src/mainboard/biostar/th61-itx/dsdt.asl +++ b/src/mainboard/biostar/th61-itx/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/bostentech/gbyt4/dsdt.asl b/src/mainboard/bostentech/gbyt4/dsdt.asl index 56e01c4d1e..5d9a8de8f5 100644 --- a/src/mainboard/bostentech/gbyt4/dsdt.asl +++ b/src/mainboard/bostentech/gbyt4/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl index bffb6683ac..7555246700 100644 --- a/src/mainboard/clevo/cml-u/dsdt.asl +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/dell/optiplex_9010/dsdt.asl b/src/mainboard/dell/optiplex_9010/dsdt.asl index 6a6dcb4c36..bd2229bd8f 100644 --- a/src/mainboard/dell/optiplex_9010/dsdt.asl +++ b/src/mainboard/dell/optiplex_9010/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index a395d248cf..8dadb3a9b6 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 5a341b49f4..6b3061bdbd 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "dsdt.aml", // Output Filename "DSDT", // Signature - 0x01, // DSDT Compliance Revision + ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, 0x1 // OEM Revision diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index a9c96be8bc..41065df0fb 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock ( "dsdt.aml", // Output Filename "DSDT", // Signature - 0x01, // DSDT Compliance Revision + ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, 0x2 // OEM Revision diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl index b8270bcd85..345ce570d6 100644 --- a/src/mainboard/facebook/fbg1701/dsdt.asl +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 2fd7851638..40a2a7df3e 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl index 6e4ecfc7ea..5e74be86e9 100644 --- a/src/mainboard/foxconn/d41s/dsdt.asl +++ b/src/mainboard/foxconn/d41s/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 3fdc1581ec..4686db1b95 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl index 94684d093a..80c5ff44c6 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 2fd748f1f9..7a965176e7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl index f9d158e8a3..40f5faf465 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-series/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index ef0855517f..7ded6af826 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index c0f4d9f1ce..32c71dee97 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index e262af9772..07a1d03fca 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 23f437019c..7bccd7f4b4 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index beb355a0e4..b751fa3eea 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index bbdbd3bc00..1698c881f1 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 8666ec7f7e..206119f380 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2fbff26c00..a6abdb86ad 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 0009d9540a..0fface13f8 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 965770c583..04c0d17a05 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 707c84cec8..42332428e4 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 3ca98ab028..d2170d0eca 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 77701987e5..3746d4bb35 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index ebee0f7d07..667cf24fb7 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 23f437019c..7bccd7f4b4 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 315cf7c30f..f87b96282e 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 3164c8134a..16f16dc0ea 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index ed25bebdd9..10e17d9b86 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index a54a646f13..1a6a1b922e 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 315cf7c30f..f87b96282e 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index aafade4f44..98aa54a808 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 805363fce2..71b7863ac2 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 96bbb9c565..5aef3604d7 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 18c975e483..cf733676e3 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 08ea5cf1c7..06f6ae1e8f 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index 24b54c9ef9..ef0a87ffc8 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 4cd6a31844..273e5b3c04 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/snb_ivb_laptops/dsdt.asl +++ b/src/mainboard/hp/snb_ivb_laptops/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/hp/z220_sff_workstation/dsdt.asl +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 98113bfc5e..a8e94fe38a 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 32852629f3..6806a8d1b9 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 388d109ef0..7fdd69bc60 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 280844d64a..21faf11af9 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 72a0ec1d04..d880d5416d 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 5dd84cf8e5..b415336ec1 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index 6e4ecfc7ea..5e74be86e9 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 94684d093a..80c5ff44c6 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index 737f02f7d4..abbb01c7df 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index de548d1939..71f501bba8 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 8b9744f60a..8cd857fa68 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl index d18004d82b..0f4cc02689 100644 --- a/src/mainboard/intel/galileo/dsdt.asl +++ b/src/mainboard/intel/galileo/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20160220 // OEM revision diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 315cf7c30f..f87b96282e 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index 4cab4cdf8a..875e664ecc 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 861ccb13b2..4beeabae4d 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 5da2c1221c..83ef3af4e8 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 256dda039a..4f3773a3ee 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 17d4165256..4bf179351b 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index bda108ed1b..0d6a863e44 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index bda108ed1b..0d6a863e44 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index d8690764bf..b5e9a0b076 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index e059c8266d..309a21721f 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index 5b76bd49ba..a93f008b08 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index f9d4fe8c3a..b3b2ca6766 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -6,7 +6,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 69553cbaef..f647f0576b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 9b5ba55018..4ea20e5be5 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index f736688289..434a1de2c7 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index fde51d906d..16b0c1dbd5 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index df39d49f72..b0f258ec4d 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 7633c91bf5..fb51412bd8 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index a1325fb27a..3967a90536 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index b794cb69a8..8751f0248c 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20130325 /* OEM revision */ diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 87eab8c120..0287cd9027 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 8f89092d09..426d8017ed 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index bddbb775b5..7875dc6374 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index fe69e954bf..05a0534ea4 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 3affa49bd3..10dc4ceb0c 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 85a9767d1e..a798424146 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -10,7 +10,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 8ab71c8ca1..c05f138c89 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index b794cb69a8..8751f0248c 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20130325 /* OEM revision */ diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index b83fe38daa..79bbd11d83 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 8919ead3d5..4d6f0840bb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -8,7 +8,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl index 2a3876bd79..3de4e26b22 100644 --- a/src/mainboard/libretrend/lt1000/dsdt.asl +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 8c9a6b57f0..e5d6917103 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index 0a57964b1f..3dfe2e35d3 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI 2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 7c8f6aa91f..86dea1c9dd 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 9fff558c46..6afd4cb74f 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 769396f454..4aff668cff 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index f175707cf0..591cc1ddf5 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20140108 /* OEM revision */ diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 592c6ba6f2..a3eebc2409 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 7e106c25cf..88abfc9b04 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -5,7 +5,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM Revision */ diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl index ec105e4295..b9722ea1c5 100644 --- a/src/mainboard/portwell/m107/dsdt.asl +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index ef84928231..9eb91c529c 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/protectli/vault_bsw/dsdt.asl b/src/mainboard/protectli/vault_bsw/dsdt.asl index c5e2ed3111..35173835cc 100644 --- a/src/mainboard/protectli/vault_bsw/dsdt.asl +++ b/src/mainboard/protectli/vault_bsw/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 /* OEM revision */ diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl index 2a3876bd79..3de4e26b22 100644 --- a/src/mainboard/protectli/vault_kbl/dsdt.asl +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 5053a7d3fe..4d81e1530f 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20160115 /* OEM revision */ diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 0039e6bdd0..dac162d20a 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl index fdef72df66..567a8c01d1 100644 --- a/src/mainboard/purism/librem_whl/dsdt.asl +++ b/src/mainboard/purism/librem_whl/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 /* OEM revision */ diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index 001eae99d0..b00b6253af 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -5,9 +5,9 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v5.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ){ //Platform diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index 997db33a0d..2890dc2fc1 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index 52784af2d5..25d85c0a8d 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20090419 // OEM revision diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index c87a947af2..97ca42a044 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 0d9c7ddf2a..73cbb9e9de 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 84c50eb97f..6232ea16a4 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index 94ff3031cb..30d8b2b75e 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 // OEM revision diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index 4cab4cdf8a..875e664ecc 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index bbce6ab12c..b0dd6b92fa 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index fc0ca022af..08a26ab088 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -2,7 +2,14 @@ #include -DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220) +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20181220 + ) { #include "acpi/platform.asl" #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index d8690764bf..b5e9a0b076 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl index a46e27f3d5..4b415892b0 100644 --- a/src/mainboard/supermicro/x9scl/dsdt.asl +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT Revision: ACPI v2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20171231 /* OEM Revision */ diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index bffb6683ac..7555246700 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/src/mainboard/up/squared/dsdt.asl b/src/mainboard/up/squared/dsdt.asl index bda108ed1b..0d6a863e44 100644 --- a/src/mainboard/up/squared/dsdt.asl +++ b/src/mainboard/up/squared/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision diff --git a/util/autoport/main.go b/util/autoport/main.go index 1a9050abd8..6b02a64e6c 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -833,7 +833,7 @@ func main() { DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20141018 /* OEM revision */ From 2bfaabc6109fee0d7964f3504ba71bb5582b1e73 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Oct 2020 17:03:55 +0200 Subject: [PATCH 011/354] mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniform Make output AML file name uniform. Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/amd/gardenia/dsdt.asl | 2 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/mandolin/dsdt.asl | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/padmelon/dsdt.asl | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/union_station/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asus/a88xm-e/dsdt.asl | 2 +- src/mainboard/asus/am1i-a/dsdt.asl | 2 +- src/mainboard/asus/f2a85-m/dsdt.asl | 2 +- src/mainboard/asus/p2b/dsdt.asl | 2 +- src/mainboard/bap/ode_e20XX/dsdt.asl | 2 +- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 +- src/mainboard/biostar/am1ml/dsdt.asl | 2 +- src/mainboard/elmex/pcm205400/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 +- src/mainboard/google/kahlee/dsdt.asl | 2 +- src/mainboard/google/zork/dsdt.asl | 2 +- src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 +- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/msi/ms7721/dsdt.asl | 2 +- src/mainboard/pcengines/apu1/dsdt.asl | 2 +- src/mainboard/pcengines/apu2/dsdt.asl | 2 +- 32 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 5606bed05b..42136e60db 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -5,7 +5,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 8dadb3a9b6..16d12edf0b 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 062620285f..bb4d6c9f13 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -5,7 +5,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 0be106aaa6..9ef76c4d01 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index f9d9af2c04..f9327764cf 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 8dadb3a9b6..16d12edf0b 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 8dadb3a9b6..16d12edf0b 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index f9d9af2c04..f9327764cf 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 8dadb3a9b6..16d12edf0b 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 137796c57c..1267ddc740 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl index a4f49b94fd..7de3281257 100644 --- a/src/mainboard/asus/a88xm-e/dsdt.asl +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 00b78cf52c..67b39b1a24 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index a6e4726929..76d7983466 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 16278aa757..384f8de2b4 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -11,7 +11,7 @@ #include DefinitionBlock ( - "DSDT.aml", + "dsdt.aml", "DSDT", ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 69625ad9c9..2e49953d48 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index 8dadb3a9b6..16d12edf0b 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index 7ded6af826..34304a8ea7 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 667cf24fb7..f7f20cdc0e 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -5,7 +5,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 06f6ae1e8f..97907379b8 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index ef0a87ffc8..924db51d4b 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index 273e5b3c04..f7f4ef83bc 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -5,7 +5,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index f647f0576b..43a3971133 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index 16b0c1dbd5..f41aab5c03 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -5,7 +5,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index e5d6917103..0a442d8128 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 86dea1c9dd..93cd02a1d1 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index a3eebc2409..71b82c9ea3 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 88abfc9b04..f33c5240d9 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -3,7 +3,7 @@ /* DefinitionBlock Statement */ #include DefinitionBlock ( - "DSDT.AML", /* Output filename */ + "dsdt.aml", "DSDT", /* Signature */ ACPI_DSDT_REV_2, OEM_ID, From 37509d7b0caf07fa0377db0aab6aa6d211225417 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Oct 2020 17:11:56 +0200 Subject: [PATCH 012/354] mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock() Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/amd/gardenia/dsdt.asl | 2 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/mandolin/dsdt.asl | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/padmelon/dsdt.asl | 2 +- src/mainboard/amd/parmer/dsdt.asl | 2 +- src/mainboard/amd/persimmon/dsdt.asl | 2 +- src/mainboard/amd/south_station/dsdt.asl | 2 +- src/mainboard/amd/thatcher/dsdt.asl | 2 +- src/mainboard/amd/union_station/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- src/mainboard/asrock/imb-a180/dsdt.asl | 2 +- src/mainboard/asus/a88xm-e/dsdt.asl | 2 +- src/mainboard/asus/am1i-a/dsdt.asl | 2 +- src/mainboard/asus/f2a85-m/dsdt.asl | 2 +- src/mainboard/bap/ode_e20XX/dsdt.asl | 2 +- src/mainboard/biostar/a68n_5200/dsdt.asl | 2 +- src/mainboard/biostar/am1ml/dsdt.asl | 2 +- src/mainboard/elmex/pcm205400/dsdt.asl | 2 +- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 4 ++-- src/mainboard/emulation/qemu-q35/dsdt.asl | 4 ++-- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 +- src/mainboard/gizmosphere/gizmo2/dsdt.asl | 2 +- src/mainboard/google/kahlee/dsdt.asl | 2 +- src/mainboard/google/zork/dsdt.asl | 2 +- src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl | 2 +- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/msi/ms7721/dsdt.asl | 2 +- src/mainboard/pcengines/apu1/dsdt.asl | 2 +- src/mainboard/pcengines/apu2/dsdt.asl | 2 +- 33 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 42136e60db..38cd34cd12 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 16d12edf0b..92591d75ff 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index bb4d6c9f13..d2fa4add7b 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 9ef76c4d01..f4cb15fc16 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index f9327764cf..940487f20b 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 16d12edf0b..92591d75ff 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 16d12edf0b..92591d75ff 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index f9327764cf..940487f20b 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 16d12edf0b..92591d75ff 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 1267ddc740..27f9de0f6a 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl index 7de3281257..a72fa36df7 100644 --- a/src/mainboard/asus/a88xm-e/dsdt.asl +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index 67b39b1a24..d5e1e18128 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index 76d7983466..3f72eb105e 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl index 2e49953d48..e8b99f4018 100644 --- a/src/mainboard/biostar/am1ml/dsdt.asl +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl index 16d12edf0b..92591d75ff 100644 --- a/src/mainboard/elmex/pcm205400/dsdt.asl +++ b/src/mainboard/elmex/pcm205400/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index 6b3061bdbd..6fd44672e7 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -3,8 +3,8 @@ #include DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature + "dsdt.aml", + "DSDT", ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 41065df0fb..d89d67f998 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -7,8 +7,8 @@ #include DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature + "dsdt.aml", + "DSDT", ACPI_DSDT_REV_1, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index 34304a8ea7..c5ad8c850f 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/gizmosphere/gizmo2/dsdt.asl b/src/mainboard/gizmosphere/gizmo2/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/gizmosphere/gizmo2/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo2/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index f7f20cdc0e..c3ffd5bc56 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 97907379b8..a96d47c089 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index 924db51d4b..59677a7360 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl index f7f4ef83bc..da03899e09 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 43a3971133..17462ac4f4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index f41aab5c03..57b535afc5 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -6,7 +6,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 0a442d8128..ffae0d932f 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 93cd02a1d1..25d5ef29ff 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 71b82c9ea3..047750da62 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index f33c5240d9..94bfe63360 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -4,7 +4,7 @@ #include DefinitionBlock ( "dsdt.aml", - "DSDT", /* Signature */ + "DSDT", ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, From 8262a2c71872cc439ef522ce2e9252f6ec976ee3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 10 Oct 2020 19:53:00 -0700 Subject: [PATCH 013/354] drivers/{intel/wifi,wifi/generic}: Drop separate Intel WiFi driver Currently, drivers/intel/wifi is a PCI driver (provides `struct pci_driver`) as well as a chip driver (provides `struct chip_operations`). However, there is no need for a separate chip driver for the WiFi device since drivers/wifi/generic already provides one. Having two separate chip drivers makes it difficult to multi-source WiFi devices and share the same firmware target without having to add a probe property for each of these devices. This is unnecessary since the WiFi driver in coreboot is primarily responsible for: 1. PCI resource allocation 2. ACPI SSDT node generation to expose wake property and SAR tables 3. SMBIOS table generation For the most part, coreboot can perform the above operations without really caring about the specifics of which WiFi device is being used by the mainboard. Thus, this change drops the driver for intel/wifi and moves the PCI driver support required for Intel WiFi chips into drivers/wifi/generic. The PCI driver is retained for backward compatibility with boards that never utilized the chip driver to support Intel WiFi device. For these devices, the PCI driver helps perform the same operations as above (except exposing the wake property) by utilizing the same `wifi_generic_ops`. This change also moves DRIVERS_INTEL_WIFI config to wifi/generic/Kconfig. BUG=b:169802515 BRANCH=zork Change-Id: I780a7d1a87f387d5e01e6b35aac7cca31a2033ac Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46036 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/drivers/intel/wifi/Kconfig | 8 -- src/drivers/intel/wifi/Makefile.inc | 3 - src/drivers/intel/wifi/chip.h | 10 -- src/drivers/intel/wifi/wifi.c | 146 ---------------------------- src/drivers/wifi/generic/Kconfig | 9 ++ src/drivers/wifi/generic/generic.c | 64 ++++++++++++ 6 files changed, 73 insertions(+), 167 deletions(-) delete mode 100644 src/drivers/intel/wifi/Kconfig delete mode 100644 src/drivers/intel/wifi/Makefile.inc delete mode 100644 src/drivers/intel/wifi/chip.h delete mode 100644 src/drivers/intel/wifi/wifi.c diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig deleted file mode 100644 index 5454e9768e..0000000000 --- a/src/drivers/intel/wifi/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config DRIVERS_INTEL_WIFI - bool "Support Intel PCI-e WiFi adapters" - depends on PCI - default y if PCIEXP_PLUGIN_SUPPORT - select DRIVERS_WIFI_GENERIC - help - When enabled, add identifiers in ACPI and SMBIOS tables to - make OS drivers work with certain Intel PCI-e WiFi chipsets. diff --git a/src/drivers/intel/wifi/Makefile.inc b/src/drivers/intel/wifi/Makefile.inc deleted file mode 100644 index 9bfdd79376..0000000000 --- a/src/drivers/intel/wifi/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h deleted file mode 100644 index 966573f2f4..0000000000 --- a/src/drivers/intel/wifi/chip.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _INTEL_WIFI_CHIP_H_ -#define _INTEL_WIFI_CHIP_H_ - -struct drivers_intel_wifi_config { - unsigned int wake; /* Wake pin for ACPI _PRW */ -}; - -#endif /* _INTEL_WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c deleted file mode 100644 index 3c90dde5d3..0000000000 --- a/src/drivers/intel/wifi/wifi.c +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "drivers/wifi/generic/chip.h" - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int smbios_write_wifi(struct device *dev, int *handle, - unsigned long *current) -{ - struct smbios_type_intel_wifi { - u8 type; - u8 length; - u16 handle; - u8 str; - u8 eos[2]; - } __packed; - - struct smbios_type_intel_wifi *t = - (struct smbios_type_intel_wifi *)*current; - int len = sizeof(struct smbios_type_intel_wifi); - - memset(t, 0, sizeof(struct smbios_type_intel_wifi)); - t->type = 0x85; - t->length = len - 2; - t->handle = *handle; - /* - * Intel wifi driver expects this string to be in the table 0x85 - * with PCI IDs enumerated below. - */ - t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); - - len = t->length + smbios_string_table_len(t->eos); - *current += len; - *handle += 1; - return len; -} -#endif - -#if CONFIG(HAVE_ACPI_TABLES) -static void intel_wifi_fill_ssdt(const struct device *dev) -{ - struct drivers_intel_wifi_config *config = dev->chip_info; - struct drivers_wifi_generic_config generic_config; - - if (config) - generic_config.wake = config->wake; - - wifi_generic_fill_ssdt(dev, config ? &generic_config : NULL); -} -#endif - -static void wifi_pci_dev_init(struct device *dev) -{ - if (pci_dev_is_wake_source(dev)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0); -} - -struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = wifi_pci_dev_init, -#if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = smbios_write_wifi, -#endif - .ops_pci = &pci_dev_ops_pci, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = wifi_generic_acpi_name, - .acpi_fill_ssdt = intel_wifi_fill_ssdt, -#endif -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_1000_SERIES_WIFI, - PCI_DEVICE_ID_6005_SERIES_WIFI, - PCI_DEVICE_ID_6005_I_SERIES_WIFI, - PCI_DEVICE_ID_1030_SERIES_WIFI, - PCI_DEVICE_ID_6030_I_SERIES_WIFI, - PCI_DEVICE_ID_6030_SERIES_WIFI, - PCI_DEVICE_ID_6150_SERIES_WIFI, - PCI_DEVICE_ID_2030_SERIES_WIFI, - PCI_DEVICE_ID_2000_SERIES_WIFI, - PCI_DEVICE_ID_0135_SERIES_WIFI, - PCI_DEVICE_ID_0105_SERIES_WIFI, - PCI_DEVICE_ID_6035_SERIES_WIFI, - PCI_DEVICE_ID_5300_SERIES_WIFI, - PCI_DEVICE_ID_5100_SERIES_WIFI, - PCI_DEVICE_ID_6000_SERIES_WIFI, - PCI_DEVICE_ID_6000_I_SERIES_WIFI, - PCI_DEVICE_ID_5350_SERIES_WIFI, - PCI_DEVICE_ID_5150_SERIES_WIFI, - /* Wilkins Peak 2 */ - PCI_DEVICE_ID_WP_7260_SERIES_1_WIFI, - PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI, - /* Stone Peak 2 */ - PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI, - PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI, - /* Stone Field Peak */ - PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI, - PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, - /* Windstorm Peak */ - PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, - /* Jefferson Peak */ - PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, - /* Thunder Peak 2 */ - PCI_DEVICE_ID_TP_9260_SERIES_WIFI, - /* Harrison Peak */ - PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, - PCI_DEVICE_ID_HrP_6SERIES_WIFI, - /* Cyclone Peak */ - PCI_DEVICE_ID_CyP_6SERIES_WIFI, - /* Typhoon Peak */ - PCI_DEVICE_ID_TyP_6SERIES_WIFI, - /* Garfiled Peak */ - PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, - PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, - 0 -}; - -static const struct pci_driver pch_intel_wifi __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -static void intel_wifi_enable(struct device *dev) -{ - dev->ops = &device_ops; -} - -struct chip_operations drivers_intel_wifi_ops = { - CHIP_NAME("Intel WiFi") - .enable_dev = intel_wifi_enable -}; diff --git a/src/drivers/wifi/generic/Kconfig b/src/drivers/wifi/generic/Kconfig index ddd2be9504..43c7d9ee1b 100644 --- a/src/drivers/wifi/generic/Kconfig +++ b/src/drivers/wifi/generic/Kconfig @@ -5,6 +5,15 @@ config DRIVERS_WIFI_GENERIC When enabled, add identifiers in ACPI tables that are common to WiFi chipsets from multiple vendors. +config DRIVERS_INTEL_WIFI + bool "Support Intel PCI-e WiFi adapters" + depends on PCI + default y if PCIEXP_PLUGIN_SUPPORT + select DRIVERS_WIFI_GENERIC + help + When enabled, add identifiers in ACPI and SMBIOS tables to + make OS drivers work with certain Intel PCI-e WiFi chipsets. + if DRIVERS_WIFI_GENERIC config USE_SAR diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index bb36861cba..ba061d0e8e 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -313,3 +313,67 @@ struct chip_operations drivers_wifi_generic_ops = { CHIP_NAME("WIFI Device") .enable_dev = wifi_generic_enable }; + +static const unsigned short intel_pci_device_ids[] = { + PCI_DEVICE_ID_1000_SERIES_WIFI, + PCI_DEVICE_ID_6005_SERIES_WIFI, + PCI_DEVICE_ID_6005_I_SERIES_WIFI, + PCI_DEVICE_ID_1030_SERIES_WIFI, + PCI_DEVICE_ID_6030_I_SERIES_WIFI, + PCI_DEVICE_ID_6030_SERIES_WIFI, + PCI_DEVICE_ID_6150_SERIES_WIFI, + PCI_DEVICE_ID_2030_SERIES_WIFI, + PCI_DEVICE_ID_2000_SERIES_WIFI, + PCI_DEVICE_ID_0135_SERIES_WIFI, + PCI_DEVICE_ID_0105_SERIES_WIFI, + PCI_DEVICE_ID_6035_SERIES_WIFI, + PCI_DEVICE_ID_5300_SERIES_WIFI, + PCI_DEVICE_ID_5100_SERIES_WIFI, + PCI_DEVICE_ID_6000_SERIES_WIFI, + PCI_DEVICE_ID_6000_I_SERIES_WIFI, + PCI_DEVICE_ID_5350_SERIES_WIFI, + PCI_DEVICE_ID_5150_SERIES_WIFI, + /* Wilkins Peak 2 */ + PCI_DEVICE_ID_WP_7260_SERIES_1_WIFI, + PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI, + /* Stone Peak 2 */ + PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI, + PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI, + /* Stone Field Peak */ + PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI, + PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, + /* Windstorm Peak */ + PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, + /* Jefferson Peak */ + PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, + PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, + PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, + /* Thunder Peak 2 */ + PCI_DEVICE_ID_TP_9260_SERIES_WIFI, + /* Harrison Peak */ + PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, + PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, + PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, + PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, + PCI_DEVICE_ID_HrP_6SERIES_WIFI, + /* Cyclone Peak */ + PCI_DEVICE_ID_CyP_6SERIES_WIFI, + /* Typhoon Peak */ + PCI_DEVICE_ID_TyP_6SERIES_WIFI, + /* Garfield Peak */ + PCI_DEVICE_ID_GrP_6SERIES_1_WIFI, + PCI_DEVICE_ID_GrP_6SERIES_2_WIFI, + 0 +}; + +/* + * The PCI driver is retained for backward compatibility with boards that never utilized the + * chip driver to support Intel WiFi device. For these devices, the PCI driver helps perform the + * same operations as above (except exposing the wake property) by utilizing the same + * `wifi_generic_ops`. + */ +static const struct pci_driver intel_wifi_pci_driver __pci_driver = { + .ops = &wifi_generic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = intel_pci_device_ids, +}; From 44f14509ed33c572ed5268f96c58c06d4348e84a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 18:05:28 -0700 Subject: [PATCH 014/354] drivers/wifi/generic: Limit scope of ACPI-related functions to generic.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change limits the scope of `wifi_generic_fill_ssdt()` and `wifi_generic_acpi_name()` to generic.c since they are not used outside of this file anymore. Also, since there is no need to split SSDT generator into two separate functions, `wifi_generic_fill_ssdt_generator()` is dropped and `.acpi_fill_ssdt` directly points to `wifi_generic_fill_ssdt()`. BUG=b:169802515 BRANCH=zork Change-Id: I2cbb97f43d2d9f9ed6d3cf8f0a9b13a7f30e922e Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46038 Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Reviewed-by: Rob Barnes Tested-by: build bot (Jenkins) --- src/drivers/wifi/generic/chip.h | 22 ---------------------- src/drivers/wifi/generic/generic.c | 13 ++++--------- 2 files changed, 4 insertions(+), 31 deletions(-) diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index 02ab504daf..e3b0ba5698 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -11,26 +11,4 @@ struct drivers_wifi_generic_config { unsigned int wake; }; -/** - * wifi_generic_fill_ssdt() - Fill ACPI SSDT table for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * @config: Generic wifi config required to fill ACPI SSDT table. - * - * This function implements common device operation to help fill ACPI SSDT - * table for WiFi controller. - */ -void wifi_generic_fill_ssdt(const struct device *dev, - const struct drivers_wifi_generic_config *config); - -/** - * wifi_generic_acpi_name() - Get ACPI name for WiFi controller - * @dev: Device structure corresponding to WiFi controller. - * - * This function implements common device operation to get the ACPI name for - * WiFi controller. - * - * Return: string representing the ACPI name for WiFi controller. - */ -const char *wifi_generic_acpi_name(const struct device *dev); - #endif /* _GENERIC_WIFI_H_ */ diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index ba061d0e8e..1b152111c9 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -163,11 +163,11 @@ static void emit_sar_acpi_structures(void) acpigen_pop_len(); } -void wifi_generic_fill_ssdt(const struct device *dev, - const struct drivers_wifi_generic_config *config) +static void wifi_generic_fill_ssdt(const struct device *dev) { const char *path; u32 address; + const struct drivers_wifi_generic_config *config = dev->chip_info; if (!dev->enabled) return; @@ -226,7 +226,7 @@ void wifi_generic_fill_ssdt(const struct device *dev, dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); } -const char *wifi_generic_acpi_name(const struct device *dev) +static const char *wifi_generic_acpi_name(const struct device *dev) { static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; @@ -235,11 +235,6 @@ const char *wifi_generic_acpi_name(const struct device *dev) (dev_path_encode(dev) & 0xff)); return wifi_acpi_name; } - -static void wifi_generic_fill_ssdt_generator(const struct device *dev) -{ - wifi_generic_fill_ssdt(dev, dev->chip_info); -} #endif static void wifi_pci_dev_init(struct device *dev) @@ -292,7 +287,7 @@ struct device_operations wifi_generic_ops = { .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = wifi_generic_acpi_name, - .acpi_fill_ssdt = wifi_generic_fill_ssdt_generator, + .acpi_fill_ssdt = wifi_generic_fill_ssdt, #endif #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = smbios_write_wifi, From e31506cd51a29f77c34e2e524801b2d0db1a5798 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 17:48:48 -0700 Subject: [PATCH 015/354] drivers/wifi/generic: Do not generate SAR tables for non-Intel WiFi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CBFS SAR and SAR tables in ACPI are currently supported only by Intel WiFi devices. This change adds a check in `emit_sar_acpi_structures()` to ensure that the PCI vendor for the device is Intel before generating the SAR tables. BUG=b:169802515 BRANCH=zork Change-Id: Ibff437893a61ac9557cff243a70230f101089834 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46040 Reviewed-by: Michael Niewöhner Reviewed-by: Duncan Laurie Reviewed-by: Rob Barnes Tested-by: build bot (Jenkins) --- src/drivers/wifi/generic/generic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 1b152111c9..e8184d8c13 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -44,12 +44,16 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) return -1; } -static void emit_sar_acpi_structures(void) +static void emit_sar_acpi_structures(const struct device *dev) { int i, j, package_size; struct wifi_sar_limits sar_limits; struct wifi_sar_delta_table *wgds; + /* CBFS SAR and SAR ACPI tables are currently used only by Intel WiFi devices. */ + if (dev->vendor != PCI_VENDOR_ID_INTEL) + return; + /* Retrieve the sar limits data */ if (get_wifi_sar_limits(&sar_limits) < 0) { printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); @@ -217,7 +221,7 @@ static void wifi_generic_fill_ssdt(const struct device *dev) /* Fill Wifi sar related ACPI structures */ if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(); + emit_sar_acpi_structures(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ From 63c0dc9dba17973ad7a39895919929e118242b3b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 1 Oct 2020 20:23:18 +0200 Subject: [PATCH 016/354] nb/intel/sandybridge: Improve cbmem_top_chipset calculation Lock bit in TSEGMB register wasn't accounted for in `cbmem_top_chipset`. Align down TSEG base to 1 MiB granularity to avoid surprises. Change-Id: I74882db99502ae77c94d43d850533a4f76da2773 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45923 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/memmap.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index b0a5149dbf..7f46d6663e 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -13,20 +13,10 @@ #include #include -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - return pci_read_config32(HOST_BRIDGE, TSEGMB); -} - -void *cbmem_top_chipset(void) -{ - return (void *)smm_region_start(); -} - static uintptr_t northbridge_get_tseg_base(void) { - return ALIGN_DOWN(smm_region_start(), 1 * MiB); + /* TSEG has 1 MiB granularity, and bit 0 is a lock */ + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEGMB), 1 * MiB); } static size_t northbridge_get_tseg_size(void) @@ -34,6 +24,14 @@ static size_t northbridge_get_tseg_size(void) return CONFIG_SMM_TSEG_SIZE; } +void *cbmem_top_chipset(void) +{ + /* If DPR is disabled, base of TSEG is top of usable DRAM */ + uintptr_t top_of_ram = northbridge_get_tseg_base(); + + return (void *)top_of_ram; +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); From 587699822c9891c80848b7c97b7e2087d63173a0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 00:36:15 +0200 Subject: [PATCH 017/354] nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate files Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ib1da100ba24de30256b3e80e380deb9c9ef4879e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45382 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/ironlake.h | 60 +------------------ .../intel/ironlake/registers/dmibar.h | 48 +++++++++++++++ .../intel/ironlake/registers/epbar.h | 24 ++++++++ 3 files changed, 74 insertions(+), 58 deletions(-) create mode 100644 src/northbridge/intel/ironlake/registers/dmibar.h create mode 100644 src/northbridge/intel/ironlake/registers/epbar.h diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 93653c9658..86c6054556 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -120,23 +120,7 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCAP2 0x008 /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ +#include "registers/epbar.h" /* * DMIBAR @@ -146,47 +130,7 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ -#define DMIPVCCAP2 0x008 /* 32bit */ - -#define DMIPVCCCTL 0x00c /* 16bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIVCPRCAP 0x028 /* 32bit */ -#define DMIVCPRCTL 0x02c /* 32bit */ -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP (1 << 1) - -#define DMIVCMRCAP 0x034 /* 32bit */ -#define DMIVCMRCTL 0x038 /* 32bit */ -#define DMIVCMRSTS 0x03e /* 16bit */ -#define VCMNP (1 << 1) - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMIUESTS 0x1c4 /* 32bit */ -#define DMICESTS 0x1d0 /* 32bit */ - -#define DMICC 0x208 /* 32bit */ - -#define DMILLTC 0x238 /* 32bit */ +#include "registers/dmibar.h" #ifndef __ASSEMBLER__ diff --git a/src/northbridge/intel/ironlake/registers/dmibar.h b/src/northbridge/intel/ironlake/registers/dmibar.h new file mode 100644 index 0000000000..f1c8645f5b --- /dev/null +++ b/src/northbridge/intel/ironlake/registers/dmibar.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_REGISTERS_DMIBAR_H__ +#define __IRONLAKE_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ + +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMILLTC 0x238 /* 32bit */ + +#endif /* __IRONLAKE_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/ironlake/registers/epbar.h b/src/northbridge/intel/ironlake/registers/epbar.h new file mode 100644 index 0000000000..8335160716 --- /dev/null +++ b/src/northbridge/intel/ironlake/registers/epbar.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_REGISTERS_EPBAR_H__ +#define __IRONLAKE_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#endif /* __IRONLAKE_REGISTERS_EPBAR_H__ */ From 63975f0e68d90722b4aa312bbd4b4baca7418f13 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Oct 2020 21:47:43 +0000 Subject: [PATCH 018/354] MAINTAINERS: Add Felix Singer to mb/clevo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1d4547d02cf0d27db5c3b0c0ae46b730a198c814 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46316 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4020accc0c..8198be4af6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -208,6 +208,13 @@ F: src/mainboard/asus/p8z77-v_lx2/ +CLEVO MAINBOARDS +M: Felix Singer +S: Supported +F: src/mainboard/clevo + + + FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks M: Wim Vervoorn From b73d2476dc2c52ec3310ee50b86b25186f98d25c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 12 Oct 2020 20:03:59 +0200 Subject: [PATCH 019/354] soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current Kconfig help text is confusing because it talks about enabling the Kconfig for disabling a UPD for disabling power gating. Rewrite and clarify the help text. Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/timer/Kconfig | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef016b..42613a8f84 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -8,7 +8,11 @@ config USE_LEGACY_8254_TIMER default y if PAYLOAD_SEABIOS || VGA_ROM_RUN default n help - This sets the FSP UPD to enable Legacy 8254 clock gating. As per - the FSP Integration guide Legacy 8254 timer clock gating UPD needs - to be disabled in order to boot SeaBIOS or run OpRom, - but should otherwise be enabled. + Setting this makes the Legacy 8254 Timer available by disabling + clock gating. This needs to be enabled in order to boot a legacy + BIOS or OS not supporting other timers like PM timer or TSC. + + While SeaBIOS does not require this timer anymore, it is needed + when OpRoms are being used. + + Disable this setting to save power, when the timer is not needed. From 6b8305d24054a452716b748e406c0263607d3bcb Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 12 Oct 2020 15:32:52 -0700 Subject: [PATCH 020/354] drivers: snsn65dsi86: Fix link rate parsing DP link rates are reported in an array of LE16 values. The current code tries to parse them as 8-bit which doesn't get very far, causing us to always drop into the fallback path. This patch should fix the issue (+minor whitespace cleanup). BUG=b:170630766 Signed-off-by: Julius Werner Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318 Tested-by: build bot (Jenkins) Reviewed-by: Douglas Anderson --- src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 5a6eb496ea..44a80884aa 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -259,11 +259,11 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); if (dpcd_val >= DP_BRIDGE_14) { /* eDP 1.4 devices must provide a custom table */ - uint8_t sink_rates[DP_MAX_SUPPORTED_RATES * 2]; + uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, sizeof(sink_rates), - DPCD_READ, sink_rates); + DPCD_READ, (void *)sink_rates); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { rate_per_200khz = le16_to_cpu(sink_rates[i]); @@ -288,14 +288,12 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate } /* On older versions best we can do is use DP_MAX_LINK_RATE */ - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); switch (dpcd_val) { default: - printk(BIOS_ERR, - "Unexpected max rate (%#x); assuming 5.4 GHz\n", - (int)dpcd_val); + printk(BIOS_ERR, "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); /* fall through */ case DP_LINK_BW_5_4: rate_valid[7] = 1; From 87feced195e70e37d7977a394b4b9779ccdfc064 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 29 Sep 2020 19:23:36 -0700 Subject: [PATCH 021/354] sc7180: Enable bootblock compression This patch enables bootblock compression on SC7180. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Signed-off-by: Julius Werner Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/arm64/Makefile.inc | 1 + src/soc/qualcomm/sc7180/Kconfig | 1 + src/soc/qualcomm/sc7180/Makefile.inc | 4 ++++ src/soc/qualcomm/sc7180/bootblock.c | 2 -- src/soc/qualcomm/sc7180/decompressor.c | 9 +++++++++ src/soc/qualcomm/sc7180/memlayout.ld | 2 +- 6 files changed, 16 insertions(+), 3 deletions(-) create mode 100644 src/soc/qualcomm/sc7180/decompressor.c diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 920ff5db51..44517cb577 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,6 +31,7 @@ bootblock-y += id.S $(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h +decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 570b68a119..c66dc92768 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -18,6 +18,7 @@ config SOC_QUALCOMM_SC7180 select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select CACHE_MRC_SETTINGS + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a0d3bc6cda..7f52a9a178 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += timer.c + ################################################################################ bootblock-y += bootblock.c bootblock-y += mmu.c diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 7dbaeecdf7..cfeb6f94f2 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -2,13 +2,11 @@ #include #include -#include #include #include void bootblock_soc_init(void) { - sc7180_mmu_init(); clock_init(); quadspi_init(37500 * KHz); qupv3_fw_init(); diff --git a/src/soc/qualcomm/sc7180/decompressor.c b/src/soc/qualcomm/sc7180/decompressor.c new file mode 100644 index 0000000000..ac55150600 --- /dev/null +++ b/src/soc/qualcomm/sc7180/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void decompressor_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 9b0adc4d5d..ce084780c6 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -22,7 +22,7 @@ SECTIONS AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) SSRAM_END(0x146AE000) From 72464a47950987fd8f615a122a6a5665f5fa016a Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Tue, 6 Oct 2020 10:42:45 +0800 Subject: [PATCH 022/354] mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS) Enable ALS ACPI devices for dooly. BUG=b:168426118 BRANCH=puff TEST=Ensure that ALS devices are enabled in ACPI tables. Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/variants/dooly/include/variant/ec.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h index 59fb3783c5..7d280c6edf 100644 --- a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h @@ -5,4 +5,7 @@ #include +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + #endif From 950305de0a21d4505e45229d25eb576c687554a1 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 7 Oct 2020 13:47:33 -0600 Subject: [PATCH 023/354] soc/intel/common: Add PCI driver for USB4 ports In order to enable SSDT generation for the DMA component of Intel USB4 ports, a PCI driver is required. This patch more or less adds a `scan_bus` callback that will handle non-PCI devices downstream. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/usb4/Kconfig | 6 +++++ src/soc/intel/common/block/usb4/Makefile.inc | 1 + src/soc/intel/common/block/usb4/usb4.c | 25 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 src/soc/intel/common/block/usb4/Kconfig create mode 100644 src/soc/intel/common/block/usb4/Makefile.inc create mode 100644 src/soc/intel/common/block/usb4/usb4.c diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig new file mode 100644 index 0000000000..1516e758c7 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BLOCK_USB4 + bool + default n + help + Minimal PCI Driver for enabling SSDT generation for the DMA component + of Intel Thunderbolt/USB4 ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc new file mode 100644 index 0000000000..7dad4ba972 --- /dev/null +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c new file mode 100644 index 0000000000..a0afc20f5b --- /dev/null +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, + PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, + 0 +}; + +static struct device_operations usb4_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_generic_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver usb4_driver __pci_driver = { + .ops = &usb4_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; From d6331e0884ceb6a17f7fd446b287b7cb5e50fcc1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Aug 2020 18:09:56 +0000 Subject: [PATCH 024/354] soc/intel/common/block: Add common support for USB4/Thunderbolt This common intel driver will add the requried ACPI _DSD entries for enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using hardcoded values in the DSDT. Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Signed-off-by: Duncan Laurie Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/usb4/usb4.c | 51 ++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index a0afc20f5b..7c545f6043 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -1,8 +1,55 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include #include #include +#include #include +#include + +#define INTEL_TBT_IMR_VALID_UUID "C44D002F-69F9-4E7D-A904-A7BAABDF43F7" +#define INTEL_TBT_WAKE_SUPPORTED_UUID "6C501103-C189-4296-BA72-9BF5A26EBE5D" + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *tbt_dma_acpi_name(const struct device *dev) +{ + switch (dev->path.pci.devfn) { + case SA_DEV_TCSS_DMA0: + return "TDM0"; + case SA_DEV_TCSS_DMA1: + return "TDM1"; + default: + return NULL; + } +} + +static void tbt_dma_fill_ssdt(const struct device *dev) +{ + struct acpi_dp *dsd, *pkg; + + if (!dev->enabled) + return; + + acpigen_write_scope(acpi_device_path(dev)); + + dsd = acpi_dp_new_table("_DSD"); + + /* Indicate that device has valid IMR. */ + pkg = acpi_dp_new_table(INTEL_TBT_IMR_VALID_UUID); + acpi_dp_add_integer(pkg, "IMR_VALID", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that device is wake capable. */ + pkg = acpi_dp_new_table(INTEL_TBT_WAKE_SUPPORTED_UUID); + acpi_dp_add_integer(pkg, "WAKE_SUPPORTED", 1); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ +} +#endif static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, @@ -16,6 +63,10 @@ static struct device_operations usb4_dev_ops = { .enable_resources = pci_dev_enable_resources, .scan_bus = scan_generic_bus, .ops_pci = &pci_dev_ops_pci, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = tbt_dma_acpi_name, + .acpi_fill_ssdt = tbt_dma_fill_ssdt, +#endif }; static const struct pci_driver usb4_driver __pci_driver = { From ce3a9740f1b753b20c7a09f215d8ff21cc91646e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 13 Aug 2020 16:17:57 -0700 Subject: [PATCH 025/354] soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/usb4/Kconfig | 7 ++ src/soc/intel/common/block/usb4/Makefile.inc | 1 + src/soc/intel/common/block/usb4/chip.h | 13 +++ src/soc/intel/common/block/usb4/pcie.c | 97 ++++++++++++++++++++ 4 files changed, 118 insertions(+) create mode 100644 src/soc/intel/common/block/usb4/chip.h create mode 100644 src/soc/intel/common/block/usb4/pcie.c diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index 1516e758c7..be0b3782b0 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -4,3 +4,10 @@ config SOC_INTEL_COMMON_BLOCK_USB4 help Minimal PCI Driver for enabling SSDT generation for the DMA component of Intel Thunderbolt/USB4 ports. + +config SOC_INTEL_COMMON_BLOCK_USB4_PCIE + bool + default n + help + Chip driver for adding PCI ops and SSDT generation for common Intel + USB4/Thunderbolt root ports. diff --git a/src/soc/intel/common/block/usb4/Makefile.inc b/src/soc/intel/common/block/usb4/Makefile.inc index 7dad4ba972..89ce426ae2 100644 --- a/src/soc/intel/common/block/usb4/Makefile.inc +++ b/src/soc/intel/common/block/usb4/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4) += usb4.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_USB4_PCIE) += pcie.c diff --git a/src/soc/intel/common/block/usb4/chip.h b/src/soc/intel/common/block/usb4/chip.h new file mode 100644 index 0000000000..f2eee4d34c --- /dev/null +++ b/src/soc/intel/common/block/usb4/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_PCIE_H__ +#define __DRIVERS_INTEL_USB4_PCIE_H__ + +struct soc_intel_common_block_usb4_config { + const char *desc; + + /* Pointer to USB4 device that this PCIe root port is routed to. */ + DEVTREE_CONST struct device *usb4_port; +}; + +#endif /* __DRIVERS_INTEL_USB4_PCIE_H__ */ diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c new file mode 100644 index 0000000000..e37d5f4125 --- /dev/null +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" +#define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" + +#if CONFIG(HAVE_ACPI_TABLES) +static void usb4_pcie_fill_ssdt(const struct device *dev) +{ + const struct soc_intel_common_block_usb4_config *config; + const struct device *parent; + struct acpi_dp *dsd, *pkg; + const char *usb4_path; + int port_id; + + /* Get parent PCI device */ + parent = dev->bus->dev; + if (!parent) { + printk(BIOS_ERR, "%s: Unable to find parent device\n", __func__); + return; + } + + if (!dev->enabled || !parent->enabled) + return; + + config = config_of(dev); + if (!config->usb4_port) { + printk(BIOS_ERR, "%s: Unable to find reference to usb4_port\n", __func__); + return; + } + + /* Get ACPI path to USB4 device. */ + usb4_path = acpi_device_path(config->usb4_port); + if (!usb4_path) { + printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port\n", __func__); + return; + } + + usb4_path = strdup(usb4_path); + port_id = dev->path.generic.id; + + acpigen_write_scope(acpi_device_path(dev)); + + /* Add pointer to USB4 port controller. */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_reference(dsd, "usb4-host-interface", usb4_path); + acpi_dp_add_integer(dsd, "usb4-port-number", port_id); + + /* Indicate that device supports hotplug in D3. */ + pkg = acpi_dp_new_table(PCI_HOTPLUG_IN_D3_UUID); + acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1); + acpi_dp_add_package(dsd, pkg); + + /* Indicate that port is external. */ + pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); + acpi_dp_add_integer(pkg, "UID", port_id); + + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); +} +#endif + +static struct device_operations usb4_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = usb4_pcie_fill_ssdt, +#endif +}; + +static void pcie_enable(struct device *dev) +{ + dev->ops = &usb4_dev_ops; +} + +struct chip_operations soc_intel_common_block_usb4_ops = { + CHIP_NAME("Intel USB4 Root Port") + .enable_dev = pcie_enable +}; From 6f58b991de606e0a1faa8b7da626eda5e8d73909 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Aug 2020 19:44:42 +0000 Subject: [PATCH 026/354] soc/intel/tigerlake: Enable and use USB4 PCIe driver This change enables the USB4/Thunderbolt common layer for Intel SOC, and enables the Intel USB4 PCIe driver. This moves the _DSD variables from the DSDT into the SSDT and allows them to be configured for each board if necessary. Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd Signed-off-by: Duncan Laurie Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 2 + src/soc/intel/tigerlake/acpi/tcss_dma.asl | 27 ------- src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 79 -------------------- src/soc/intel/tigerlake/chipset.cb | 28 ++++++- 4 files changed, 26 insertions(+), 110 deletions(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 4df2e852ca..9433080eda 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -48,6 +48,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index f7c4117dcf..085990dbfd 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -92,30 +92,3 @@ Method (_PRW, 0) { Return (Package() { 0x6D, 4 }) } - -Method (_DSD, 0) -{ - Return( - Package() - { - /* Thunderbolt GUID for IMR_VALID at ../drivers/acpi/property.c */ - ToUUID("C44D002F-69F9-4E7D-A904-A7BAABDF43F7"), - Package () - { - Package (2) { "IMR_VALID", 1 } - }, - - /* Thunderbolt GUID for WAKE_SUPPORTED at ../drivers/acpi/property.c */ - ToUUID("6C501103-C189-4296-BA72-9BF5A26EBE5D"), - Package () - { - Package (2) { "WAKE_SUPPORTED", 1 } - } - } - ) -} - -Method (_DSM, 4, Serialized) -{ - Return (Buffer() { 0 }) -} diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index b4c0cefa1e..08d890087c 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -220,85 +220,6 @@ Method (_PS3, 0, Serialized) } } -Method (_DSD, 0) { - If ((TUID == 0) || (TUID == 1)) { - Return ( Package() { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 }, - Package (2) { "usb4-port-number", TUID }, - } - }) - } ElseIf (TUID == 2) { - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 0 }, - } - }) - } Else { /* TUID == 3 */ - Return ( Package () { - /* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */ - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () - { - Package (2) { "HotPlugSupportInD3", 1 }, - }, - - /* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */ - ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"), - Package () { - Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */ - /* - * UID of the TBT RP on platform, range is: 0, 1 ..., - * (NumOfTBTRP - 1). - */ - Package (2) { "UID", TUID }, - }, - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 }, - Package (2) { "usb4-port-number", 1 }, - } - }) - } -} - Method (_S0W, 0x0, NotSerialized) { Return (0x4) diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 4f55125528..b60801c347 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -5,10 +5,30 @@ chip soc/intel/tigerlake device pci 04.0 alias dptf off end device pci 05.0 alias ipu off end device pci 06.0 alias peg off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tbt_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tbt_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tbt_dma1 as usb4_port + device generic 0 on end + end + end + device pci 07.3 alias tbt_pcie_rp3 off + chip soc/intel/common/block/usb4 + use tbt_dma1 as usb4_port + device generic 1 on end + end + end device pci 08.0 alias gna off end device pci 09.0 alias npk off end device pci 0a.0 alias crashlog off end From 8e251f7fceb8df1438be23165bed127fc8b91750 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 12 Oct 2020 17:22:16 +0530 Subject: [PATCH 027/354] vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01 List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295 Reviewed-by: Tim Wawrzynczak Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 54 +++++++++++-------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index a42f01474f..8c4582a4ea 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -586,7 +586,17 @@ typedef struct { /** Offset 0x037C - Reserved **/ - UINT8 Reserved20[34]; + UINT8 Reserved20[20]; + +/** Offset 0x0390 - Enable or Disable TME + Enable or Disable TME; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x0391 - Reserved +**/ + UINT8 Reserved21[13]; /** Offset 0x039E - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -600,7 +610,7 @@ typedef struct { /** Offset 0x03A0 - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved22[4]; /** Offset 0x03A4 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -614,7 +624,7 @@ typedef struct { /** Offset 0x03AC - Reserved **/ - UINT8 Reserved22[12]; + UINT8 Reserved23[12]; /** Offset 0x03B8 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -628,7 +638,7 @@ typedef struct { /** Offset 0x03C0 - Reserved **/ - UINT8 Reserved23[614]; + UINT8 Reserved24[614]; /** Offset 0x0626 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -637,7 +647,7 @@ typedef struct { /** Offset 0x0627 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved25[4]; /** Offset 0x062B - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -647,7 +657,7 @@ typedef struct { /** Offset 0x063D - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved26[14]; /** Offset 0x064B - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -656,7 +666,7 @@ typedef struct { /** Offset 0x065D - Reserved **/ - UINT8 Reserved26[19]; + UINT8 Reserved27[19]; /** Offset 0x0670 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -666,7 +676,7 @@ typedef struct { /** Offset 0x0674 - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; /** Offset 0x0676 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -676,7 +686,7 @@ typedef struct { /** Offset 0x0677 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved29[3]; /** Offset 0x067A - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -701,7 +711,7 @@ typedef struct { /** Offset 0x068D - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved30[3]; /** Offset 0x0690 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -751,7 +761,7 @@ typedef struct { /** Offset 0x06A7 - Reserved **/ - UINT8 Reserved30[13]; + UINT8 Reserved31[13]; /** Offset 0x06B4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -761,7 +771,7 @@ typedef struct { /** Offset 0x06B5 - Reserved **/ - UINT8 Reserved31[4]; + UINT8 Reserved32[4]; /** Offset 0x06B9 - MRC Safe Config Enables/Disable MRC Safe Config @@ -819,7 +829,7 @@ typedef struct { /** Offset 0x06C2 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x06C4 - Early Command Training Enables/Disable Early Command Training @@ -829,7 +839,7 @@ typedef struct { /** Offset 0x06C5 - Reserved **/ - UINT8 Reserved33[65]; + UINT8 Reserved34[65]; /** Offset 0x0706 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -839,7 +849,7 @@ typedef struct { /** Offset 0x0708 - Reserved **/ - UINT8 Reserved34[64]; + UINT8 Reserved35[64]; /** Offset 0x0748 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -852,7 +862,7 @@ typedef struct { /** Offset 0x0749 - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved36[2]; /** Offset 0x074B - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -862,7 +872,7 @@ typedef struct { /** Offset 0x074C - Reserved **/ - UINT8 Reserved36[2]; + UINT8 Reserved37[2]; /** Offset 0x074E - TCSS USB Port Enable Bitmap for per port enabling @@ -871,7 +881,7 @@ typedef struct { /** Offset 0x074F - Reserved **/ - UINT8 Reserved37[50]; + UINT8 Reserved38[50]; /** Offset 0x0781 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -882,7 +892,7 @@ typedef struct { /** Offset 0x0782 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0783 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -892,7 +902,7 @@ typedef struct { /** Offset 0x0784 - Reserved **/ - UINT8 Reserved39[129]; + UINT8 Reserved40[129]; /** Offset 0x0805 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -902,7 +912,7 @@ typedef struct { /** Offset 0x0806 - Reserved **/ - UINT8 Reserved40[292]; + UINT8 Reserved41[292]; /** Offset 0x092A - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -913,7 +923,7 @@ typedef struct { /** Offset 0x092B - Reserved **/ - UINT8 Reserved41[517]; + UINT8 Reserved42[517]; } FSP_M_CONFIG; /** Fsp M UPD Configuration From 0aed4e577df03a3c9c790fddebb1a9c413a0abcb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 12 Oct 2020 17:27:31 +0530 Subject: [PATCH 028/354] soc/intel/alderlake: Enable TME for Alder Lake List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296 Reviewed-by: Angel Pons Reviewed-by: V Sowmya Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/romstage/fsp_params.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3f500f33cf..2d21a61193 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select INTEL_TME select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 80420f0948..38c1a1b279 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -155,6 +155,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) From d1095c7ed79d7bed958c6e446fe4ea2def5c2102 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Fri, 25 Sep 2020 14:16:46 -0600 Subject: [PATCH 029/354] mb/google/zork: Enable wake on wireless lan MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up BRANCH=zork Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745 Reviewed-by: Furquan Shaikh Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../google/zork/variants/baseboard/devicetree_dalboz.cb | 7 ++++++- .../google/zork/variants/baseboard/devicetree_trembyle.cb | 7 ++++++- .../google/zork/variants/baseboard/gpio_baseboard_dalboz.c | 4 ++-- .../zork/variants/baseboard/gpio_baseboard_trembyle.c | 4 ++-- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index cbb812d220..58e25e6ba3 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -210,7 +210,12 @@ chip soc/amd/picasso device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 7288d6e32d..3ab70a2945 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -210,7 +210,12 @@ chip soc/amd/picasso device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 696c733189..2398d07d74 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -14,8 +14,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 549cc589bb..a436d1c3d0 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -14,8 +14,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ From 7377cda6089210068b9d163083e6084439aa3e88 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 28 Aug 2020 10:50:47 -0700 Subject: [PATCH 030/354] mb/intel/tglrvp: Enable Pcie WWAN m.2 Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration. BUG=none TEST=Boot to OS, check WWAN functionality Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 9 +++++++++ .../intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c | 9 +++++++++ 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 2abdce4c72..09ab2583c1 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/tigerlake register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index c9de9c602c..51b301d3cf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -104,6 +104,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b46a1cf401..25c229332a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/tigerlake register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 303350be27..77da5cce5c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -100,6 +100,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) From 9faab3122e13d767bd95dd0887235a368e94d573 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Thu, 19 Dec 2019 23:36:47 -0800 Subject: [PATCH 031/354] soc/intel/common/block: Enable PMC IPC driver In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../block/include/intelblocks/pmc_ipc.h | 49 ++++++++++ src/soc/intel/common/block/pmc/Makefile.inc | 2 +- src/soc/intel/common/block/pmc/pmc_ipc.c | 96 +++++++++++++++++++ 3 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 src/soc/intel/common/block/include/intelblocks/pmc_ipc.h create mode 100644 src/soc/intel/common/block/pmc/pmc_ipc.c diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h new file mode 100644 index 0000000000..0c90cd7df6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PMC_IPC_H +#define SOC_INTEL_COMMON_BLOCK_PMC_IPC_H + +#include + +#define PMC_IPC_BUF_COUNT 4 + +#define PMC_IPC_CMD_COMMAND_SHIFT 0 +#define PMC_IPC_CMD_COMMAND_MASK 0xff +#define PMC_IPC_CMD_MSI_SHIFT 8 +#define PMC_IPC_CMD_MSI_MASK 0x01 +#define PMC_IPC_CMD_SUB_COMMAND_SHIFT 12 +#define PMC_IPC_CMD_SUB_COMMAND_MASK 0x0f +#define PMC_IPC_CMD_SIZE_SHIFT 16 +#define PMC_IPC_CMD_SIZE_MASK 0xff + +#define PMC_IPC_CMD_FIELD(name, val) \ + (((val) & PMC_IPC_CMD_##name##_MASK << PMC_IPC_CMD_##name##_SHIFT)) + +#define PMC_IPC_CMD_NO_MSI 0 + +/* + * Create the IPC CMD to send to PMC + */ +static inline uint32_t pmc_make_ipc_cmd(uint32_t cmd, uint32_t subcmd, + uint32_t size) +{ + return PMC_IPC_CMD_FIELD(COMMAND, cmd) | + PMC_IPC_CMD_FIELD(SUB_COMMAND, subcmd) | + PMC_IPC_CMD_FIELD(MSI, PMC_IPC_CMD_NO_MSI) | + PMC_IPC_CMD_FIELD(SIZE, size); +} + +/* + * Buffer for holding write and read buffers of IPC commands + */ +struct pmc_ipc_buffer { + uint32_t buf[PMC_IPC_BUF_COUNT]; +}; + +/* + * Send PMC IPC command + */ +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf); + +#endif /* SOC_INTEL_COMMON_BLOCK_PMC_IPC_H */ diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 965721714d..796a039aed 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -2,7 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y) bootblock-y += pmclib.c romstage-y += pmclib.c ramstage-y += pmc.c -ramstage-y += pmclib.c +ramstage-y += pmclib.c pmc_ipc.c smm-y += pmclib.c verstage-y += pmclib.c postcar-y += pmclib.c diff --git a/src/soc/intel/common/block/pmc/pmc_ipc.c b/src/soc/intel/common/block/pmc/pmc_ipc.c new file mode 100644 index 0000000000..7decf790a9 --- /dev/null +++ b/src/soc/intel/common/block/pmc/pmc_ipc.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * WBUF register block offset 0x80..0x8f there are 4 consecutive + * 32 bit registers + */ +#define IPC_WBUF0 0x80 + +/* + * RBUF registers block offset 0x90..0x9f there are 4 consecutive + * 32 bit registers + */ +#define IPC_RBUF0 0x90 + +/* + * From Intel 500 Series PCH EDS vol2 s4.4 + */ +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_STS_OFFSET 0x4 +#define PMC_IPC_STS_BUSY BIT(0) +#define PMC_IPC_STS_ERR BIT(1) +#define PMC_IPC_ERR_CODE_SHIFT 16 +#define PMC_IPC_ERR_CODE_MASK 0xff + +#define PMC_IPC_XFER_TIMEOUT_MS (1 * MSECS_PER_SEC) /* max 1s */ +#define IS_IPC_STS_BUSY(status) ((status) & PMC_IPC_STS_BUSY) +#define IPC_STS_HAS_ERROR(status) ((status) & PMC_IPC_STS_ERR) +#define IPC_STS_ERROR_CODE(sts) (((sts) >> PMC_IPC_ERR_CODE_SHIFT & \ + PMC_IPC_ERR_CODE_MASK)) + +static void *pmc_reg(unsigned int pmc_reg_offset) +{ + const uintptr_t pmcbase = soc_read_pmc_base(); + return (void *)(pmcbase + pmc_reg_offset); +} + +static const void *pmc_rbuf(unsigned int ix) +{ + return pmc_reg(IPC_RBUF0 + ix * sizeof(uint32_t)); +} + +static void *pmc_wbuf(unsigned int ix) +{ + return pmc_reg(IPC_WBUF0 + ix * sizeof(uint32_t)); +} + +static int check_ipc_sts(void) +{ + struct stopwatch sw; + uint32_t ipc_sts; + + stopwatch_init_msecs_expire(&sw, PMC_IPC_XFER_TIMEOUT_MS); + do { + ipc_sts = read32(pmc_reg(PMC_IPC_STS_OFFSET)); + if (!(IS_IPC_STS_BUSY(ipc_sts))) { + if (IPC_STS_HAS_ERROR(ipc_sts)) { + printk(BIOS_ERR, "IPC_STS.error_code 0x%x\n", + IPC_STS_ERROR_CODE(ipc_sts)); + return -1; + } + return 0; + } + udelay(50); + + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "PMC IPC timeout after %u ms\n", PMC_IPC_XFER_TIMEOUT_MS); + return -1; +} + +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf) +{ + for (int i = 0; i < PMC_IPC_BUF_COUNT; ++i) + write32(pmc_wbuf(i), wbuf->buf[i]); + + write32(pmc_reg(PMC_IPC_CMD_OFFSET), cmd); + + if (check_ipc_sts()) { + printk(BIOS_ERR, "PMC IPC command 0x%x failed\n", cmd); + return CB_ERR; + } + + for (int i = 0; i < PMC_IPC_BUF_COUNT; ++i) + rbuf->buf[i] = read32(pmc_rbuf(i)); + + return CB_SUCCESS; +} From 49d74de9690b448e16497483365a94f500f97e7f Mon Sep 17 00:00:00 2001 From: Divya Sasidharan Date: Tue, 22 Oct 2019 13:41:15 -0700 Subject: [PATCH 032/354] src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/ec/google/chromeec/ec.c | 63 +++++++++++++++++++++++++++++++- src/ec/google/chromeec/ec.h | 11 +++++- src/ec/google/chromeec/ec_acpi.c | 3 +- 3 files changed, 73 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 40285dc81d..82de088401 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1380,11 +1380,11 @@ enum ec_image google_chromeec_get_current_image(void) return ec_image_type; } -int google_chromeec_get_num_pd_ports(int *num_ports) +int google_chromeec_get_num_pd_ports(unsigned int *num_ports) { struct ec_response_charge_port_count resp = {}; struct chromeec_command cmd = { - .cmd_code = EC_CMD_CHARGE_PORT_COUNT, + .cmd_code = EC_CMD_USB_PD_PORTS, .cmd_version = 0, .cmd_data_out = &resp, .cmd_size_in = 0, @@ -1441,6 +1441,65 @@ int google_ec_running_ro(void) return (google_chromeec_get_current_image() == EC_IMAGE_RO); } +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +{ + struct ec_params_usb_pd_control pd_control = { + .port = port, + .role = USB_PD_CTRL_ROLE_NO_CHANGE, + .mux = USB_PD_CTRL_ROLE_NO_CHANGE, + .swap = USB_PD_CTRL_SWAP_NONE, + }; + struct ec_response_usb_pd_control_v2 resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_CONTROL, + .cmd_version = 2, + .cmd_data_in = &pd_control, + .cmd_size_in = sizeof(pd_control), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); + *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *dp_mode = resp.dp_mode; + + return 0; +} + +/** + * Check for the current mux state in EC. Flags representing the mux state found + * in ec_commands.h + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) +{ + struct ec_params_usb_pd_mux_info req_mux = { + .port = port, + }; + struct ec_response_usb_pd_mux_info resp_mux = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_MUX_INFO, + .cmd_version = 0, + .cmd_data_in = &req_mux, + .cmd_size_in = sizeof(req_mux), + .cmd_data_out = &resp_mux, + .cmd_size_out = sizeof(resp_mux), + .cmd_dev_index = 0, + }; + + if (port < 0) + return -1; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *flags = resp_mux.flags; + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 9d4e58842e..ad3768c025 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -27,6 +27,15 @@ int google_ec_running_ro(void); enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); +/* Check for the current mux state in EC + * in: int port physical port number of the type-c port + * out: uint8_t flags flags representing the status of the mux such as + * usb capability, dp capability, cable type, etc + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); +/* Returns data role and type of device connected */ +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, + uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ @@ -306,7 +315,7 @@ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); * of PD-capable USB ports according to the EC. * @return 0 on success, -1 on error */ -int google_chromeec_get_num_pd_ports(int *num_ports); +int google_chromeec_get_num_pd_ports(unsigned int *num_ports); /* Structure representing the capabilities of a USB-PD port */ struct usb_pd_port_caps { diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 8a76805407..b7683167af 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -144,7 +144,8 @@ static bool match_connector(DEVTREE_CONST struct device *dev) static void fill_ssdt_typec_device(const struct device *dev) { int rv; - int i, num_ports; + int i; + unsigned int num_ports; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; From ae763de649d7d8ebcc00f2e6792b37c4766e1047 Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 28 Sep 2020 16:12:26 +0800 Subject: [PATCH 033/354] mb/google/dedede/var/madoo: Update DPTF setting Add tcc, critical, passive policy, and pl values from thermal team. BUG=b:169215576 TEST=build and verify by thermal tool Signed-off-by: John Su Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: EricR Lai Reviewed-by: Sumeet R Pawnikar --- .../dedede/variants/madoo/overridetree.cb | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 257f91722e..c284f7a643 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -53,7 +53,34 @@ chip soc/intel/jasperlake }, }, }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "5" # TCC of 95C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 65, 1000)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "controls.power_limits.pl1" = "{ + .min_power = 4800, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on From 685dbe14e93104847f2a3b885d58aef4f8e67192 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 5 Oct 2020 10:44:50 -0600 Subject: [PATCH 034/354] acpi/device: Add GPIO binding property for an array of GPIOs This change is required for use-cases like GPIO based I2C multiplexer where more than one GPIOs are used as select lines. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the GPIO bindings for an array of GPIOs are added to the ACPI table as follows: Device (MUX0) { ... Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0126 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "mux-gpios", Package (0x08) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero, \_SB.PCI0.I2C3.MUX0, One, Zero, Zero } } } }) } Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46056 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/acpi/device.c | 83 +++++++++++++++++++++++++--------- src/include/acpi/acpi_device.h | 16 +++++++ 2 files changed, 77 insertions(+), 22 deletions(-) diff --git a/src/acpi/device.c b/src/acpi/device.c index 450427d47c..5de31b7776 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -1019,33 +1019,72 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, return dp_array; } +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const struct acpi_gpio_res_params *params, + size_t param_count) +{ + struct acpi_dp *gpio; + uint32_t i; + + if (!dp || !param_count) + return NULL; + + gpio = acpi_dp_new_table(name); + if (!gpio) + return NULL; + + /* + * Generate ACPI identifiers as follows: + * Package () { + * name, // e.g. cs-gpios + * Package() { + * ref, index, pin, active_low, // GPIO-0 (params[0]) + * ref, index, pin, active_low, // GPIO-1 (params[1]) + * ... + * } + * } + */ + for (i = 0; i < param_count; i++, params++) { + /* + * If refs is NULL, leave a hole in the gpio array. This can be used in + * conditions where some controllers use both GPIOs and native signals. + */ + if (!params->ref) { + acpi_dp_add_integer(gpio, NULL, 0); + continue; + } + + /* The device that has _CRS containing GpioIO()/GpioInt() */ + acpi_dp_add_reference(gpio, NULL, params->ref); + + /* Index of the GPIO resource in _CRS starting from zero */ + acpi_dp_add_integer(gpio, NULL, params->index); + + /* Pin in the GPIO resource, typically zero */ + acpi_dp_add_integer(gpio, NULL, params->pin); + + /* Set if pin is active low */ + acpi_dp_add_integer(gpio, NULL, params->active_low); + } + acpi_dp_add_array(dp, gpio); + + return gpio; + +} + + struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low) { - if (!dp) - return NULL; + struct acpi_gpio_res_params param = { + .ref = ref, + .index = index, + .pin = pin, + .active_low = active_low, + }; - struct acpi_dp *gpio = acpi_dp_new_table(name); - - if (!gpio) - return NULL; - - /* The device that has _CRS containing GpioIO()/GpioInt() */ - acpi_dp_add_reference(gpio, NULL, ref); - - /* Index of the GPIO resource in _CRS starting from zero */ - acpi_dp_add_integer(gpio, NULL, index); - - /* Pin in the GPIO resource, typically zero */ - acpi_dp_add_integer(gpio, NULL, pin); - - /* Set if pin is active low */ - acpi_dp_add_integer(gpio, NULL, active_low); - - acpi_dp_add_array(dp, gpio); - - return gpio; + return acpi_dp_add_gpio_array(dp, name, ¶m, 1); } /* diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index be13bd7ec8..301f9b0156 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -545,6 +545,22 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low); +struct acpi_gpio_res_params { + /* Reference to the parent device. */ + const char *ref; + /* Index to the GpioIo resource within the _CRS. */ + int index; + /* Index to the pin within the GpioIo resource, usually 0. */ + int pin; + /* Flag to indicate if pin is active low. */ + int active_low; +}; + +/* Add a GPIO binding device property for array of GPIOs */ +struct acpi_dp *acpi_dp_add_gpio_array(struct acpi_dp *dp, const char *name, + const struct acpi_gpio_res_params *params, + size_t param_count); + /* Add a child table of Device Properties */ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, struct acpi_dp *child); From 9bf45b43ee81ceed6c6545c6ccfb791cc28c8993 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 01:12:06 +0200 Subject: [PATCH 035/354] soc/intel/broadwell/igd.c: Rename to gma.c This makes comparisons against Haswell a bit simpler. Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Tim Wawrzynczak --- src/soc/intel/broadwell/Makefile.inc | 2 +- src/soc/intel/broadwell/{igd.c => gma.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename src/soc/intel/broadwell/{igd.c => gma.c} (100%) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 28b7c2961e..786fe2ae5e 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -28,7 +28,7 @@ ramstage-y += gpio.c romstage-y += gpio.c smm-y += gpio.c ramstage-y += hda.c -ramstage-y += igd.c +ramstage-y += gma.c ramstage-y += iobp.c romstage-y += iobp.c ramstage-y += fadt.c diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/gma.c similarity index 100% rename from src/soc/intel/broadwell/igd.c rename to src/soc/intel/broadwell/gma.c From 2ead36334050ac692e64adc59a97320d8792adcc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 24 Sep 2020 16:50:05 +0200 Subject: [PATCH 036/354] soc/intel/broadwell: Align cosmetics with Haswell/Lynx Point Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change. Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697 Reviewed-by: Matt DeVillier Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/acpi/lpc.asl | 8 ++---- src/soc/intel/broadwell/cpu.c | 2 +- src/soc/intel/broadwell/fadt.c | 13 +++++---- src/soc/intel/broadwell/memmap.c | 1 + src/soc/intel/broadwell/minihd.c | 43 ++++++++++++++-------------- src/soc/intel/broadwell/pch.c | 4 +-- src/soc/intel/broadwell/pcie.c | 23 ++++++--------- src/soc/intel/broadwell/pmutil.c | 10 +++---- src/soc/intel/broadwell/smbus.c | 1 + src/soc/intel/broadwell/smihandler.c | 31 ++++++++------------ 10 files changed, 60 insertions(+), 76 deletions(-) diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 33c8dc92a0..5bdfea24ce 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -81,9 +81,7 @@ Device (LPCB) Method (_CRS, 0, Serialized) // Current resources { If (HPTE) { - CreateDWordField (BUF0, - \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - + CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } @@ -153,8 +151,7 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff) }) Method (_CRS, 0, NotSerialized) @@ -169,7 +166,6 @@ Device (LPCB) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) - //IRQNoFlags() { 8 } }) } diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 8a38137b9d..c64af02bba 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -400,7 +400,7 @@ static void cpu_core_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local CPU apics */ + /* Enable the local CPU APICs */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/fadt.c index f39ad801e0..8fbd0c45ad 100644 --- a/src/soc/intel/broadwell/fadt.c +++ b/src/soc/intel/broadwell/fadt.c @@ -38,10 +38,13 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + fadt->flags |= ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; @@ -82,5 +85,5 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; + fadt->x_gpe0_blk.addrh = 0x0; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 4673cceca0..fb9a834f6c 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ #include diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index b91d73d216..a39c496ce5 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -12,30 +12,30 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of jacks */ /* Enable 3rd Pin and Converter Widget */ 0x00878101, /* Pin Widget 5 - PORT B */ - 0x00571C10, - 0x00571D00, - 0x00571E56, - 0x00571F18, + 0x00571c10, + 0x00571d00, + 0x00571e56, + 0x00571f18, /* Pin Widget 6 - PORT C */ - 0x00671C20, - 0x00671D00, - 0x00671E56, - 0x00671F18, + 0x00671c20, + 0x00671d00, + 0x00671e56, + 0x00671f18, /* Pin Widget 7 - PORT D */ - 0x00771C30, - 0x00771D00, - 0x00771E56, - 0x00771F18, + 0x00771c30, + 0x00771d00, + 0x00771e56, + 0x00771f18, /* Disable 3rd Pin and Converter Widget */ 0x00878100, @@ -48,8 +48,8 @@ static const u32 minihd_verb_table[] = { static void minihd_init(struct device *dev) { struct resource *res; - u8 *base; u32 reg32; + u8 *base; int codec_mask, i; /* Find base address */ @@ -80,8 +80,7 @@ static void minihd_init(struct device *dev) if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - sizeof(minihd_verb_table), + hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } @@ -92,10 +91,10 @@ static void minihd_init(struct device *dev) } static struct device_operations minihd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &minihd_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = minihd_init, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 479323dd56..2a27d92152 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -64,9 +64,7 @@ u32 pch_read_soft_strap(int id) /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); } /* RCBA function disable and posting read to flush the transaction */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 00a8595eeb..01ee06895f 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -18,7 +18,7 @@ #include /* Low Power variant has 6 root ports. */ -#define NUM_ROOT_PORTS 6 +#define MAX_NUM_ROOT_PORTS 6 struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ @@ -34,7 +34,7 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - struct device *ports[NUM_ROOT_PORTS]; + struct device *ports[MAX_NUM_ROOT_PORTS]; }; static struct root_port_config rpc; @@ -110,7 +110,7 @@ static void root_port_init_config(struct device *dev) if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); rpc.new_rpfn = rpc.orig_rpfn; - rpc.num_ports = NUM_ROOT_PORTS; + rpc.num_ports = MAX_NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ pci_update_config8(dev, 0xf5, ~0xa, 0x5); @@ -473,8 +473,7 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pci_update_config32(dev, 0xd4, ~(0x3 << 2), - (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); @@ -526,7 +525,7 @@ static void pch_pcie_early(struct device *dev) else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pci_update_config32(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); @@ -572,8 +571,6 @@ static void pch_pcie_early(struct device *dev) static void pch_pcie_init(struct device *dev) { - u16 reg16; - printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ @@ -585,15 +582,11 @@ static void pch_pcie_init(struct device *dev) /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); - pci_write_config16(dev, 0x06, reg16); - reg16 = pci_read_config16(dev, 0x1e); - pci_write_config16(dev, 0x1e, reg16); + pci_update_config16(dev, 0x06, ~0, 0); + pci_update_config16(dev, 0x1e, ~0, 0); } static void pch_pcie_enable(struct device *dev) diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 92cf3637f9..c96ed18b8a 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -312,7 +312,7 @@ void enable_tco_sci(void) */ /* Clear a GPE0 status and return events that are enabled and active */ -static u32 reset_gpe(u16 sts_reg, u16 en_reg) +static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); @@ -366,10 +366,10 @@ u32 clear_gpe_status(void) [18] = "WADT" }; - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); - return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); + print_gpe_gpio(reset_gpe_status(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); + return print_gpe_status(reset_gpe_status(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), gpe0_sts_3_bits); } diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 562db4e4cc..31715c7182 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -18,6 +18,7 @@ static void pch_smbus_init(struct device *dev) u16 reg16; /* Enable clock gating */ + /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); pci_write_config32(dev, 0x80, reg16); diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 1732ef7803..4a12d786dd 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -58,25 +58,22 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u16 reg16; - pci_devfn_t dev = PCI_DEV(bus, slot, func); + val = pci_read_config32(dev, PCI_VENDOR_ID); if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) + val == 0x0000ffff || val == 0xffff0000) continue; /* Disable Bus Mastering for this one device */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr &= 0x7f; if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { + hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int buses; buses = pci_read_config32(dev, PCI_PRIMARY_BUS); busmaster_disable_on_bus((buses >> 8) & 0xff); @@ -249,11 +246,11 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) for (node = 0; node < CONFIG_MAX_CPUS; node++) { state = smm_get_save_state(node); - /* Check for Synchronous IO (bit0==1) */ + /* Check for Synchronous IO (bit0 == 1) */ if (!(state->io_misc_info & (1 << 0))) continue; - /* Make sure it was a write (bit4==0) */ + /* Make sure it was a write (bit4 == 0) */ if (state->io_misc_info & (1 << 4)) continue; @@ -429,8 +426,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, - (bios_cntl & ~1)); + pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -453,7 +449,7 @@ static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; - u32 data, mask = 0; + u32 mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register @@ -480,8 +476,9 @@ static void southbridge_smi_monitor(void) // It's a write if (!(trap_cycle & (1 << 24))) { printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; + (void)RCBA32(0x1e18); + // data = RCBA32(0x1e18); + // data &= mask; // if (smi1) // southbridge_smi_command(data); // return; @@ -501,8 +498,7 @@ static void southbridge_smi_monitor(void) if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", RCBA32(0x1e18)); } #undef IOTRAP } @@ -546,10 +542,7 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map */ - void southbridge_smi_handler(void) { int i; From 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 24 Sep 2020 18:03:18 +0200 Subject: [PATCH 037/354] haswell/lynxpoint: Align cosmetics with Broadwell Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/acpi.c | 94 +++++++++---------- src/cpu/intel/haswell/smmrelocate.c | 6 +- .../intel/lynxpoint/acpi/globalnvs.asl | 11 ++- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 28 +++--- src/southbridge/intel/lynxpoint/acpi/pch.asl | 17 ++-- .../intel/lynxpoint/acpi/serialio.asl | 16 ++-- src/southbridge/intel/lynxpoint/chip.h | 10 +- src/southbridge/intel/lynxpoint/elog.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 11 +-- src/southbridge/intel/lynxpoint/me_status.c | 2 +- src/southbridge/intel/lynxpoint/pcie.c | 46 +++++---- src/southbridge/intel/lynxpoint/pmutil.c | 6 +- src/southbridge/intel/lynxpoint/smihandler.c | 52 +++++----- 13 files changed, 151 insertions(+), 150 deletions(-) diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 676acce9dd..6dd8559d22 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -65,50 +65,6 @@ static void generate_cstate_entries(acpi_cstate_t *cstates, acpigen_pop_len(); } -static void generate_C_state_entries(void) -{ - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -161,6 +117,50 @@ static void generate_T_state_entries(int core, int cores_per_package) ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static void generate_C_state_entries(void) +{ + struct cpu_info *info; + struct cpu_driver *cpu; + struct device *lapic; + struct cpu_intel_haswell_config *conf = NULL; + + /* Find the SpeedStep CPU in the device tree using magic APIC ID */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic) + return; + conf = lapic->chip_info; + if (!conf) + return; + + /* Find CPU map of supported C-states */ + info = cpu_info(); + if (!info) + return; + cpu = find_cpu_driver(info->cpu); + if (!cpu || !cpu->cstates) + return; + + acpigen_emit_byte(0x14); /* MethodOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("_CST"); + acpigen_emit_byte(0x00); /* No Arguments */ + + /* If running on AC power */ + acpigen_emit_byte(0xa0); /* IfOp */ + acpigen_write_len_f(); /* PkgLength */ + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_pop_len(); + + /* Else on battery power */ + acpigen_emit_byte(0xa4); /* ReturnOp */ + generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_pop_len(); +} + static int calculate_power(int tdp, int p1_ratio, int ratio) { u32 m; @@ -307,19 +307,19 @@ void generate_cpu_entries(const struct device *device) /* Generate processor \_SB.CPUx */ acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, + (cpuID - 1) * cores_per_package+coreID - 1, pcontrol_blk, plen); /* Generate P-state tables */ generate_P_state_entries( - coreID-1, cores_per_package); + coreID - 1, cores_per_package); /* Generate C-state tables */ generate_C_state_entries(); /* Generate T-state tables */ generate_T_state_entries( - cpuID-1, cores_per_package); + cpuID - 1, cores_per_package); acpigen_pop_len(); } diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index abc005c6f0..2fc20aab3d 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -156,7 +156,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; size_t tseg_size; - u32 prmrr_base; u32 prmrr_size; int phys_bits; @@ -197,7 +196,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) params->uncore_prmrr_base.lo = prmrr_base; params->uncore_prmrr_base.hi = 0; params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + MTRR_PHYS_MASK_VALID; params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; } @@ -282,6 +281,5 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 16c4b75f96..ee2d8000bc 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -2,9 +2,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name (\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. @@ -31,9 +32,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit + TLVL, 8, // 0x11 - Throttle Level Limit FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold + TCRT, 8, // 0x13 - Critical Threshold TPSV, 8, // 0x14 - Passive Threshold TMAX, 8, // 0x15 - CPU Tj_max F0OF, 8, // 0x16 - FAN 0 OFF Threshold @@ -51,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 1e9de3cb33..bc1d73cddf 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -4,7 +4,7 @@ Device (LPCB) { - Name(_ADR, 0x001f0000) + Name (_ADR, 0x001f0000) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -14,7 +14,7 @@ Device (LPCB) Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), - GPBS, 16, // GPIOBASE + GPBS, 16, // GPIOBASE Offset (0x60), // Interrupt Routing Registers PRTA, 8, PRTB, 8, @@ -40,10 +40,10 @@ Device (LPCB) #include "acpi/ec.asl" - Device (DMAC) // DMA Controller + Device (DMAC) // DMA Controller { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -53,7 +53,7 @@ Device (LPCB) }) } - Device (FWH) // Firmware Hub + Device (FWH) // Firmware Hub { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -67,7 +67,7 @@ Device (LPCB) Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Name(BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate() { Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) @@ -90,7 +90,7 @@ Device (LPCB) Method (_CRS, 0, Serialized) // Current resources { If (HPTE) { - CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) } @@ -110,8 +110,8 @@ Device (LPCB) Device(PIC) // 8259 Interrupt Controller { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() + Name (_HID,EISAID("PNP0000")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -160,8 +160,7 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, - 0x1, 0xff) + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff) // GPIO region may be 128 bytes or 4096 bytes IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1) @@ -197,9 +196,8 @@ Device (LPCB) Device (TIMR) // Intel 8254 timer { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { + Name (_HID, EISAID("PNP0100")) + Name (_CRS, ResourceTemplate() { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) IRQNoFlags() {0} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 6d0428c464..bace058387 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel Cougar Point PCH support */ +/* Intel Lynx Point PCH support */ -Scope(\) +Scope (\) { // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) @@ -11,17 +11,16 @@ Scope(\) } // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) + OperationRegion (IO_T, SystemIO, 0x800, 0x10) + Field (IO_T, ByteAcc, NoLock, Preserve) { - Offset(0x8), + Offset (0x8), TRP0, 8 // IO-Trap at 0x808 } - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) + // Root Complex Register Block + OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field (RCRB, DWordAcc, Lock, Preserve) { Offset(0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index ce3a869a92..8956563cd9 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -116,7 +116,7 @@ Device (SDMA) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) Method (_CRS, 0, NotSerialized) @@ -156,7 +156,7 @@ Device (I2C0) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -236,7 +236,7 @@ Device (I2C1) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -313,7 +313,7 @@ Device (SPI0) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) Method (_CRS, 0, NotSerialized) @@ -350,7 +350,7 @@ Device (SPI1) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -399,7 +399,7 @@ Device (UAR0) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} }) // DMA channels are only used if Serial IO DMA controller is enabled @@ -448,7 +448,7 @@ Device (UAR1) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} }) Method (_CRS, 0, NotSerialized) @@ -485,7 +485,7 @@ Device (SDIO) Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} }) Method (_CRS, 0, NotSerialized) diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e30d4b4c21..40d0460419 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -47,7 +47,8 @@ struct southbridge_intel_lynxpoint_config { uint32_t sata_port0_gen3_dtle; uint32_t sata_port1_gen3_dtle; - /* SATA DEVSLP Mux + /* + * SATA DEVSLP Mux * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 */ @@ -67,12 +68,13 @@ struct southbridge_intel_lynxpoint_config { /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; - /* Serial IO configuration */ - /* Put devices into ACPI mode instead of a PCI device */ + /* Put SerialIO devices into ACPI mode instead of a PCI device */ uint8_t sio_acpi_mode; + /* I2C voltage select: 0=3.3V 1=1.8V */ uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; @@ -91,4 +93,4 @@ struct southbridge_intel_lynxpoint_config { bool docking_supported; }; -#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 8146794aa3..3ce765d1f5 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -46,7 +46,7 @@ static void pch_log_gpe(void) u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { - [0] = 27, + [0] = 27, [24] = 17, [25] = 19, [26] = 21, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e5614303cc..fad83b1612 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -115,7 +115,7 @@ static void pch_pirq_init(struct device *dev) */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -446,7 +446,7 @@ static void enable_lp_clock_gating(struct device *dev) reg32 &= ~(1 << 29); // LPC Dynamic else reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1UL << 31); // LP LPC + reg32 |= (1 << 31); // LP LPC reg32 |= (1 << 30); // LP BLA reg32 |= (1 << 28); // GPIO Dynamic reg32 |= (1 << 27); // HPET Dynamic @@ -565,7 +565,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } /* Check LPC Memory Decode register. */ @@ -577,7 +577,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->base = reg; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } } } @@ -645,8 +645,7 @@ static void pch_lpc_add_io_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 045d960a9e..82a8f8ed0a 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -11,7 +11,7 @@ static const char *me_cws_values[] = { [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", }; /* HFS1[8:6] Current Operation State Values */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0ede943ceb..112c9d3fa3 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -502,14 +502,10 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - int rp; - int do_aspm; - int is_lp; struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - - rp = root_port_number(dev); - do_aspm = 0; - is_lp = pch_is_lp(); + int do_aspm = 0; + int rp = root_port_number(dev); + int is_lp = pch_is_lp(); if (is_lp) { switch (rp) { @@ -517,18 +513,24 @@ static void pch_pcie_early(struct device *dev) case 2: case 3: case 4: - /* Bits 31:28 of b0d28f0 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bits 31:28 of b0d28f0 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: - /* Bit 28 of b0d28f4 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bit 28 of b0d28f4 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: - /* Bit 28 of b0d28f5 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bit 28 of b0d28f5 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); break; } @@ -538,16 +540,20 @@ static void pch_pcie_early(struct device *dev) case 2: case 3: case 4: - /* Bits 31:28 of b0d28f0 0x32c register correspnd to - * Root Ports 4:1. */ + /* + * Bits 31:28 of b0d28f0 0x32c register correspond to + * Root Ports 4:1. + */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: case 6: case 7: case 8: - /* Bit 31:28 of b0d28f4 0x32c register correspnd to - * Root Ports 8:5. */ + /* + * Bits 31:28 of b0d28f4 0x32c register correspond to + * Root Ports 8:5. + */ do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5))); break; } @@ -644,7 +650,7 @@ static void pch_pcie_early(struct device *dev) pci_or_config32(dev, 0x64, 1 << 11); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) @@ -692,7 +698,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x90, ~0, 0); } -static void pci_init(struct device *dev) +static void pch_pcie_init(struct device *dev) { printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); @@ -737,7 +743,7 @@ static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, + .init = pch_pcie_init, .enable = pch_pcie_enable, .scan_bus = pciexp_scan_bridge, .ops_pci = &pci_dev_ops_pci, diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index af7a2b2b98..7b8468934f 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -33,8 +33,8 @@ static void print_status_bits(u32 status, const char *bit_names[]) if (!status) return; - for (i=31; i>=0; i--) { - if (status & (1UL << i)) { + for (i = 31; i >= 0; i--) { + if (status & (1 << i)) { if (bit_names[i]) printk(BIOS_DEBUG, "%s ", bit_names[i]); else @@ -51,7 +51,7 @@ static void print_gpio_status(u32 status, int start) if (!status) return; - for (i=31; i>=0; i--) { + for (i = 31; i >= 0; i--) { if (status & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", start + i); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index f5c5f2a80e..9a5e5c0561 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -86,7 +86,7 @@ static void southbridge_smi_sleep(void) u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; u16 pmbase = get_pmbase(); - // save and recover RTC port values + /* save and recover RTC port values */ u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); @@ -145,11 +145,10 @@ static void southbridge_smi_sleep(void) * "KEEP", switch to "OFF" - KEEP is software emulated */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { + if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; - } else { + else reg8 |= 1; - } pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ @@ -160,7 +159,8 @@ static void southbridge_smi_sleep(void) break; } - /* Write back to the SLP register to cause the originally intended + /* + * Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ @@ -170,7 +170,8 @@ static void southbridge_smi_sleep(void) if (slp_typ >= ACPI_S3) halt(); - /* In most sleep states, the code flow of this function ends at + /* + * In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ @@ -228,11 +229,11 @@ static void southbridge_smi_gsmi(void) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32 *)&io_smi->rax; sub_command = (u8)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32 *)&io_smi->rbx; /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -345,7 +346,7 @@ static void southbridge_smi_pm1(void) * on a power button event. */ if (pm1_sts & PWRBTN_STS) { - // power button pressed + /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); @@ -367,9 +368,7 @@ static void southbridge_smi_gpi(void) static void southbridge_smi_mc(void) { - u32 reg32; - - reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -386,17 +385,16 @@ static void southbridge_smi_tco(void) if (!tco_sts) return; - if (tco_sts & (1 << 8)) { // BIOSWR - u8 bios_cntl; - - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + // BIOSWR + if (tco_sts & (1 << 8)) { + u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a + /* + * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone + * + * This is the place where we notice someone * is trying to tinker with the BIOS. We are * trying to be nice and just ignore it. A more * resolute answer would be to power down the @@ -413,9 +411,7 @@ static void southbridge_smi_tco(void) static void southbridge_smi_periodic(void) { - u32 reg32; - - reg32 = inl(get_pmbase() + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -435,7 +431,7 @@ static void southbridge_smi_monitor(void) RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -452,7 +448,8 @@ static void southbridge_smi_monitor(void) /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write + // It's a write + if (!(trap_cycle & (1 << 24))) { printk(BIOS_DEBUG, "SMI1 command\n"); (void)RCBA32(0x1e18); // data = RCBA32(0x1e18); @@ -466,8 +463,9 @@ static void southbridge_smi_monitor(void) printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) - if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", From d5689dd289d1108249d8c7ed779ae62fbd8963bf Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 00:32:44 +0200 Subject: [PATCH 038/354] soc/intel/broadwell/pcie.c: Add some null checks These are present in Lynx Point. Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715 Reviewed-by: Matt DeVillier Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pcie.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 01ee06895f..0d41d42525 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -182,7 +182,7 @@ static void pch_pcie_device_set_func(int index, int pci_func) /* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func); - if (dev->path.pci.devfn != new_devfn) { + if (dev && dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", PCI_SLOT(dev->path.pci.devfn), @@ -204,6 +204,9 @@ static void pcie_enable_clock_gating(void) int rp; dev = rpc.ports[i]; + if (!dev) + continue; + rp = root_port_number(dev); if (!dev->enabled) { From 3b8b00fd39b3dbbf42b41a018e2bdf264479fc97 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 00:37:06 +0200 Subject: [PATCH 039/354] soc/intel/broadwell/smi.c: Drop unused functions These aren't used anywhere, so get rid of them. Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716 Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/smi.c | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 317da0cc2d..d7704fd8fa 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -54,35 +54,3 @@ void global_smi_enable(void) { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -static void __unused southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static void __unused southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} From 8b8b271f12941742c723c136d8a3a901302e7856 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 01:04:51 +0200 Subject: [PATCH 040/354] soc/intel/broadwell/xhci.c: Align with Lynx Point Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721 Reviewed-by: Matt DeVillier Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/xhci.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 319c9b125b..526781d1c4 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -129,7 +129,6 @@ static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { - u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); @@ -138,18 +137,13 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) return; /* Set D0 state */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~XHCI_PWR_CTL_SET_MASK; - reg16 |= XHCI_PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~XHCI_PWR_CTL_SET_MASK, XHCI_PWR_CTL_SET_D0); if (!is_broadwell) { /* This WA is only for lpt */ /* Clear PCI 0xB0[14:13] */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - pci_write_config32(dev, 0xb0, reg32); + pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); From a5314b62b69d2305fbc88882db2b270a3326096b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 13:08:26 +0200 Subject: [PATCH 041/354] nb/intel/x4x: Clean up DMIBAR/EPBAR definitions Several registers have been copy-pasted from i945 and do not exist on Eagle Lake. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/x4x/early_init.c | 64 +++++++++++------------ src/northbridge/intel/x4x/x4x.h | 72 +++++++++++++++++++++----- 2 files changed, 92 insertions(+), 44 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 81752cdd9f..279a38fcd6 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -60,59 +60,59 @@ static void init_egress(void) u32 reg32; /* VC0: TC0 only */ - EPBAR8(0x14) = 1; - EPBAR8(0x4) = 1; + EPBAR8(EPVC0RCTL) = 1; + EPBAR8(EPPVCCAP1) = 1; switch (MCHBAR32(0xc00) & 0x7) { case 0x0: /* FSB 1066 */ - EPBAR32(0x2c) = 0x0001a6db; + EPBAR32(EPVC1ITC) = 0x0001a6db; break; case 0x2: /* FSB 800 */ - EPBAR32(0x2c) = 0x00014514; + EPBAR32(EPVC1ITC) = 0x00014514; break; default: case 0x4: /* FSB 1333 */ - EPBAR32(0x2c) = 0x00022861; + EPBAR32(EPVC1ITC) = 0x00022861; break; } - EPBAR32(0x28) = 0x0a0a0a0a; - EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2; - EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000; + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2; + EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000; MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; /* VC1: ID1, TC7 */ - reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); + reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); reg32 = (reg32 & ~0xfe) | (1 << 7); - EPBAR32(0x20) = reg32; + EPBAR32(EPVC1RCTL) = reg32; /* Init VC1 port arbitration table */ - EPBAR32(0x100) = 0x001000001; - EPBAR32(0x104) = 0x000040000; - EPBAR32(0x108) = 0x000001000; - EPBAR32(0x10c) = 0x000000040; - EPBAR32(0x110) = 0x001000001; - EPBAR32(0x114) = 0x000040000; - EPBAR32(0x118) = 0x000001000; - EPBAR32(0x11c) = 0x000000040; + EPBAR32(EP_PORTARB(0)) = 0x001000001; + EPBAR32(EP_PORTARB(1)) = 0x000040000; + EPBAR32(EP_PORTARB(2)) = 0x000001000; + EPBAR32(EP_PORTARB(3)) = 0x000000040; + EPBAR32(EP_PORTARB(4)) = 0x001000001; + EPBAR32(EP_PORTARB(5)) = 0x000040000; + EPBAR32(EP_PORTARB(6)) = 0x000001000; + EPBAR32(EP_PORTARB(7)) = 0x000000040; /* Load table */ - reg32 = EPBAR32(0x20) | (1 << 16); - EPBAR32(0x20) = reg32; + reg32 = EPBAR32(EPVC1RCTL) | (1 << 16); + EPBAR32(EPVC1RCTL) = reg32; asm("nop"); - EPBAR32(0x20) = reg32; + EPBAR32(EPVC1RCTL) = reg32; /* Wait for table load */ - while ((EPBAR8(0x26) & (1 << 0)) != 0) + while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0) ; /* VC1: enable */ - EPBAR32(0x20) |= 1 << 31; + EPBAR32(EPVC1RCTL) |= 1 << 31; /* Wait for VC1 */ - while ((EPBAR8(0x26) & (1 << 1)) != 0) + while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0) ; printk(BIOS_DEBUG, "Done Egress Port\n"); @@ -125,12 +125,12 @@ static void init_dmi(void) /* Assume IGD present */ /* Clear error status */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) = 1; - DMIBAR8(0x4) = 1; + DMIBAR8(DMIPVCCAP1) = 1; /* VC1: ID1, TC7 */ reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); @@ -203,17 +203,17 @@ static void init_dmi(void) /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; - while ((DMIBAR32(0x26) & (1 << 1)) != 0) + while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0) ; printk(BIOS_DEBUG, "Done DMI setup\n"); /* ASPM on DMI */ DMIBAR32(0x200) &= ~(0x3 << 26); DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; - DMIBAR32(0x88) &= ~0x3; - DMIBAR32(0x88) |= 0x3; - /* FIXME: Do we need to read RCBA16(0x88)? */ - DMIBAR16(0x88); + DMIBAR32(DMILCTL) &= ~0x3; + DMIBAR32(DMILCTL) |= 0x3; + /* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */ + DMIBAR16(DMILCTL); } static void x4x_prepare_resume(int s3resume) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index ff157add29..c62428705f 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -93,14 +93,42 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ /* * EPBAR @@ -110,10 +138,30 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + + #define NOP_CMD 0x2 #define PRECHARGE_CMD 0x4 From 4cee40a19d286b8c77598cc8d6325c17418527fb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 9 Oct 2020 23:19:51 +0200 Subject: [PATCH 042/354] mb/purism/librem_skl: Drop DQ and DQS byte maps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These settings are not necessary for DDR4 and can be dropped. Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46251 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Michael Niewöhner --- src/mainboard/purism/librem_skl/romstage.c | 26 ---------------------- 1 file changed, 26 deletions(-) diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 7be8325176..4982836c66 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -5,28 +5,6 @@ #include #include -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) { /* Rcomp resistor */ @@ -54,10 +32,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); From fd19075045b6834cab2b01e04e6192e6ca71f429 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 12:38:17 +0200 Subject: [PATCH 043/354] nb/intel/x4x: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45421 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../x4x/{hostbridge_regs.h => registers/host_bridge.h} | 6 +++--- src/northbridge/intel/x4x/x4x.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) rename src/northbridge/intel/x4x/{hostbridge_regs.h => registers/host_bridge.h} (88%) diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/registers/host_bridge.h similarity index 88% rename from src/northbridge/intel/x4x/hostbridge_regs.h rename to src/northbridge/intel/x4x/registers/host_bridge.h index 00b496dca8..f09240416f 100644 --- a/src/northbridge/intel/x4x/hostbridge_regs.h +++ b/src/northbridge/intel/x4x/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __X4X_HOSTBRIDGE_REGS_H__ -#define __X4X_HOSTBRIDGE_REGS_H__ +#ifndef __X4X_REGISTERS_HOSTBRIDGE_H__ +#define __X4X_REGISTERS_HOSTBRIDGE_H__ #define D0F0_EPBAR_LO 0x40 #define D0F0_EPBAR_HI 0x44 @@ -37,4 +37,4 @@ #define D0F0_SKPD 0xdc /* Scratchpad Data */ #define D0F0_CAPID0 0xe0 -#endif /* __X4X_HOSTBRIDGE_REGS_H__ */ +#endif /* __X4X_REGISTERS_HOSTBRIDGE_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c62428705f..25345756e0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -11,7 +11,7 @@ */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* * D1:F0 PEG From 41e66ac38fdca75a982756b8478bd5ec1e3b9c72 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 13:17:23 +0200 Subject: [PATCH 044/354] nb/intel/x4x: Place raminit definitions in raminit.h There's no need to have implementation details in a public header. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I04d8c610d3e52adecfe96cc435f0523bedf3060a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45424 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/x4x/dq_dqs.c | 1 + src/northbridge/intel/x4x/raminit.c | 1 + src/northbridge/intel/x4x/raminit.h | 247 +++++++++++++++++++++ src/northbridge/intel/x4x/raminit_ddr23.c | 1 + src/northbridge/intel/x4x/raminit_tables.c | 2 +- src/northbridge/intel/x4x/rcven.c | 1 + src/northbridge/intel/x4x/romstage.c | 4 +- src/northbridge/intel/x4x/x4x.h | 247 +-------------------- 8 files changed, 259 insertions(+), 245 deletions(-) create mode 100644 src/northbridge/intel/x4x/raminit.h diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 1535452c1f..4362bd6307 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -5,6 +5,7 @@ #include #include #include +#include "raminit.h" #include "x4x.h" static void print_dll_setting(const struct dll_setting *dll_setting, diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index a1be5aa449..00cc6096a3 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -14,6 +14,7 @@ #include #include +#include "raminit.h" #include "x4x.h" #define MRC_CACHE_VERSION 0 diff --git a/src/northbridge/intel/x4x/raminit.h b/src/northbridge/intel/x4x/raminit.h new file mode 100644 index 0000000000..ca58b1f5c0 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_RAMINIT_H__ +#define __X4X_RAMINIT_H__ + +#include + +#define NOP_CMD 0x2 +#define PRECHARGE_CMD 0x4 +#define MRS_CMD 0x6 +#define EMRS_CMD 0x8 +#define EMRS1_CMD (EMRS_CMD | 0x10) +#define EMRS2_CMD (EMRS_CMD | 0x20) +#define EMRS3_CMD (EMRS_CMD | 0x30) +#define ZQCAL_CMD 0xa +#define CBR_CMD 0xc +#define NORMALOP_CMD 0xe + +#define TOTAL_CHANNELS 2 +#define TOTAL_DIMMS 4 +#define TOTAL_BYTELANES 8 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) +#define RAW_CARD_UNPOPULATED 0xff +#define RAW_CARD_POPULATED 0 + +#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) +#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) +#define FOR_EACH_DIMM(idx) \ + for (idx = 0; idx < TOTAL_DIMMS; ++idx) +#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ + FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) +#define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ + for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) +#define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ + FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) +#define CHANNEL_IS_POPULATED(dimms, idx) \ + ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) +#define CHANNEL_IS_CARDF(dimms, idx) \ + ((dimms[idx<<1].card_type == 0xf) \ + || (dimms[(idx<<1) + 1].card_type == 0xf)) +#define IF_CHANNEL_POPULATED(dimms, idx) \ + if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) +#define FOR_EACH_CHANNEL(idx) \ + for (idx = 0; idx < TOTAL_CHANNELS; ++idx) +#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ + FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) + +#define RANKS_PER_CHANNEL 4 +#define RANK_IS_POPULATED(dimms, ch, r) \ + (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ + ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define IF_RANK_POPULATED(dimms, ch, r) \ + if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) < dimms[ch<<1].ranks)) \ + || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define FOR_EACH_RANK_IN_CHANNEL(r) \ + for (r = 0; r < RANKS_PER_CHANNEL; ++r) +#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ + FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_RANK(ch, r) \ + FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) +#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ + FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_BYTELANE(l) \ + for (l = 0; l < TOTAL_BYTELANES; l++) +#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ + FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) + +#define DDR3_MAX_CAS 18 + +enum fsb_clock { + FSB_CLOCK_800MHz = 0, + FSB_CLOCK_1066MHz = 1, + FSB_CLOCK_1333MHz = 2, +}; + +enum mem_clock { + MEM_CLOCK_400MHz = 0, + MEM_CLOCK_533MHz = 1, + MEM_CLOCK_667MHz = 2, + MEM_CLOCK_800MHz = 3, + MEM_CLOCK_1066MHz = 4, + MEM_CLOCK_1333MHz = 5, +}; + +enum ddr { + DDR2 = 2, + DDR3 = 3, +}; + +enum ddrxspd { + DDR2SPD = 0x8, + DDR3SPD = 0xb, +}; + +enum chip_width { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +}; + +enum chip_cap { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +}; + +struct dll_setting { + u8 tap; + u8 pi; + u8 db_en; + u8 db_sel; + u8 clk_delay; + u8 coarse; +}; + +struct rt_dqs_setting { + u8 tap; + u8 pi; +}; + +enum n_banks { + N_BANKS_4 = 0, + N_BANKS_8 = 1, +}; + +struct timings { + unsigned int CAS; + unsigned int tclk; + enum fsb_clock fsb_clk; + enum mem_clock mem_clk; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tWR; + unsigned int tRFC; + unsigned int tWTR; + unsigned int tRRD; + unsigned int tRTP; +}; + +struct dimminfo { + unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ + enum chip_width width; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + enum n_banks n_banks; + unsigned int ranks; + unsigned int rows; + unsigned int cols; + u16 spd_crc; + u8 mirrored; +}; + +struct rcven_timings { + u8 min_common_coarse; + u8 coarse_offset[TOTAL_BYTELANES]; + u8 medium[TOTAL_BYTELANES]; + u8 tap[TOTAL_BYTELANES]; + u8 pi[TOTAL_BYTELANES]; +}; + +/* The setup is up to two DIMMs per channel */ +struct sysinfo { + int boot_path; + enum fsb_clock max_fsb; + + int dimm_config[2]; + int spd_type; + int channel_capacity[2]; + struct timings selected_timings; + struct dimminfo dimms[4]; + u8 spd_map[4]; + struct rcven_timings rcven_t[TOTAL_CHANNELS]; + /* + * The rt_dqs delay register for rank 0 seems to be used + * for all other ranks on the channel, so only save that + */ + struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; + struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; + struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; + u8 nmode; + u8 stacked_mode; +}; + +enum ddr2_signals { + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, +}; + +void sdram_initialize(int boot_path, const u8 *spd_map); +void do_raminit(struct sysinfo *, int fast_boot); +void rcven(struct sysinfo *s); +u32 fsb_to_mhz(u32 speed); +u32 ddr_to_mhz(u32 speed); +u32 test_address(int channel, int rank); +void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); +void dqset(u8 ch, u8 lane, const struct dll_setting *setting); +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); +int do_write_training(struct sysinfo *s); +int do_read_training(struct sysinfo *s); +void search_write_leveling(struct sysinfo *s); +void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); + +extern const struct dll_setting default_ddr2_667_ctrl[7]; +extern const struct dll_setting default_ddr2_800_ctrl[7]; +extern const struct dll_setting default_ddr3_800_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; +extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; +extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; +extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; +extern const u8 post_jedec_tab[3][4][2]; +extern const u32 ddr3_c2_tab[2][3][6][2]; +extern const u8 ddr3_c2_x264[3][6]; +extern const u16 ddr3_c2_x23c[3][6]; + +#endif /* __X4X_RAMINIT_H__ */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 617ce11581..43b9b90cfe 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -13,6 +13,7 @@ #include #endif #include +#include "raminit.h" #include "x4x.h" #define ME_UMA_SIZEMB 0 diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index e4a80d8441..2ae3c06054 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include "x4x.h" +#include "raminit.h" const struct dll_setting default_ddr2_667_ctrl[7] = { /* tap pi db delay coarse*/ diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 82481abe30..8a86ce9cb5 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -3,6 +3,7 @@ #include #include #include +#include "raminit.h" #include "x4x.h" #define MAX_COARSE 15 diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 5a30a8040a..648520c038 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) @@ -11,6 +10,9 @@ #include #endif +#include "raminit.h" +#include "x4x.h" + __weak void mb_pre_raminit_setup(int s3_resume) { } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 25345756e0..ea34fe0b7a 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -6,6 +6,10 @@ #include #include "memmap.h" +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_WARM_RESET 1 +#define BOOT_PATH_RESUME 2 + /* * D0:F0 */ @@ -161,215 +165,6 @@ #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ - - -#define NOP_CMD 0x2 -#define PRECHARGE_CMD 0x4 -#define MRS_CMD 0x6 -#define EMRS_CMD 0x8 -#define EMRS1_CMD (EMRS_CMD | 0x10) -#define EMRS2_CMD (EMRS_CMD | 0x20) -#define EMRS3_CMD (EMRS_CMD | 0x30) -#define ZQCAL_CMD 0xa -#define CBR_CMD 0xc -#define NORMALOP_CMD 0xe - -#define TOTAL_CHANNELS 2 -#define TOTAL_DIMMS 4 -#define TOTAL_BYTELANES 8 -#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) -#define RAW_CARD_UNPOPULATED 0xff -#define RAW_CARD_POPULATED 0 - -#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) -#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) -#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ - !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) -#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ - !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) -#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ - (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) -#define FOR_EACH_DIMM(idx) \ - for (idx = 0; idx < TOTAL_DIMMS; ++idx) -#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ - FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) -#define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ - for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) -#define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ - FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) -#define CHANNEL_IS_POPULATED(dimms, idx) \ - ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) -#define CHANNEL_IS_CARDF(dimms, idx) \ - ((dimms[idx<<1].card_type == 0xf) \ - || (dimms[(idx<<1) + 1].card_type == 0xf)) -#define IF_CHANNEL_POPULATED(dimms, idx) \ - if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) -#define FOR_EACH_CHANNEL(idx) \ - for (idx = 0; idx < TOTAL_CHANNELS; ++idx) -#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ - FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) - -#define RANKS_PER_CHANNEL 4 -#define RANK_IS_POPULATED(dimms, ch, r) \ - (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ - ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) -#define IF_RANK_POPULATED(dimms, ch, r) \ - if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) < dimms[ch<<1].ranks)) \ - || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) -#define FOR_EACH_RANK_IN_CHANNEL(r) \ - for (r = 0; r < RANKS_PER_CHANNEL; ++r) -#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ - FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) -#define FOR_EACH_RANK(ch, r) \ - FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) -#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ - FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) -#define FOR_EACH_BYTELANE(l) \ - for (l = 0; l < TOTAL_BYTELANES; l++) -#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \ - FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l) - -#define DDR3_MAX_CAS 18 - -enum fsb_clock { - FSB_CLOCK_800MHz = 0, - FSB_CLOCK_1066MHz = 1, - FSB_CLOCK_1333MHz = 2, -}; - -enum mem_clock { - MEM_CLOCK_400MHz = 0, - MEM_CLOCK_533MHz = 1, - MEM_CLOCK_667MHz = 2, - MEM_CLOCK_800MHz = 3, - MEM_CLOCK_1066MHz = 4, - MEM_CLOCK_1333MHz = 5, -}; - -enum ddr { - DDR2 = 2, - DDR3 = 3, -}; - -enum ddrxspd { - DDR2SPD = 0x8, - DDR3SPD = 0xb, -}; - -enum chip_width { /* as in DDR3 spd */ - CHIP_WIDTH_x4 = 0, - CHIP_WIDTH_x8 = 1, - CHIP_WIDTH_x16 = 2, - CHIP_WIDTH_x32 = 3, -}; - -enum chip_cap { /* as in DDR3 spd */ - CHIP_CAP_256M = 0, - CHIP_CAP_512M = 1, - CHIP_CAP_1G = 2, - CHIP_CAP_2G = 3, - CHIP_CAP_4G = 4, - CHIP_CAP_8G = 5, - CHIP_CAP_16G = 6, -}; - -struct dll_setting { - u8 tap; - u8 pi; - u8 db_en; - u8 db_sel; - u8 clk_delay; - u8 coarse; -}; - -struct rt_dqs_setting { - u8 tap; - u8 pi; -}; - -enum n_banks { - N_BANKS_4 = 0, - N_BANKS_8 = 1, -}; - -struct timings { - unsigned int CAS; - unsigned int tclk; - enum fsb_clock fsb_clk; - enum mem_clock mem_clk; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tWR; - unsigned int tRFC; - unsigned int tWTR; - unsigned int tRRD; - unsigned int tRTP; -}; - -struct dimminfo { - unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ - enum chip_width width; - unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ - enum n_banks n_banks; - unsigned int ranks; - unsigned int rows; - unsigned int cols; - u16 spd_crc; - u8 mirrored; -}; - -struct rcven_timings { - u8 min_common_coarse; - u8 coarse_offset[TOTAL_BYTELANES]; - u8 medium[TOTAL_BYTELANES]; - u8 tap[TOTAL_BYTELANES]; - u8 pi[TOTAL_BYTELANES]; -}; - -/* The setup is up to two DIMMs per channel */ -struct sysinfo { - int boot_path; - enum fsb_clock max_fsb; - - int dimm_config[2]; - int spd_type; - int channel_capacity[2]; - struct timings selected_timings; - struct dimminfo dimms[4]; - u8 spd_map[4]; - struct rcven_timings rcven_t[TOTAL_CHANNELS]; - /* - * The rt_dqs delay register for rank 0 seems to be used - * for all other ranks on the channel, so only save that - */ - struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES]; - struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; - struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; - u8 nmode; - u8 stacked_mode; -}; -#define BOOT_PATH_NORMAL 0 -#define BOOT_PATH_WARM_RESET 1 -#define BOOT_PATH_RESUME 2 - -enum ddr2_signals { - CLKSET0 = 0, - CTRL0, - CLKSET1, - CMD, - CTRL1, - CTRL2, - CTRL3, -}; - void x4x_early_init(void); void x4x_late_init(int s3resume); void mb_get_spd_map(u8 spd_map[4]); @@ -378,40 +173,6 @@ u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); int decode_pcie_bar(u32 *const base, u32 *const len); -void sdram_initialize(int boot_path, const u8 *spd_map); -void do_raminit(struct sysinfo *, int fast_boot); -void rcven(struct sysinfo *s); -u32 fsb_to_mhz(u32 speed); -u32 ddr_to_mhz(u32 speed); -u32 test_address(int channel, int rank); -void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); -void dqset(u8 ch, u8 lane, const struct dll_setting *setting); -void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); -int do_write_training(struct sysinfo *s); -int do_read_training(struct sysinfo *s); -void search_write_leveling(struct sysinfo *s); -void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); - -extern const struct dll_setting default_ddr2_667_ctrl[7]; -extern const struct dll_setting default_ddr2_800_ctrl[7]; -extern const struct dll_setting default_ddr3_800_ctrl[2][7]; -extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; -extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; -extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES]; -extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES]; -extern const u8 ddr3_emrs1_rtt_nom_config[16][4]; -extern const u8 post_jedec_tab[3][4][2]; -extern const u32 ddr3_c2_tab[2][3][6][2]; -extern const u8 ddr3_c2_x264[3][6]; -extern const u16 ddr3_c2_x23c[3][6]; #include struct acpi_rsdp; From 04bf41b5aa3001395e6d89ab1b0a0531b85c626f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 01:07:27 +0200 Subject: [PATCH 045/354] util/lint: Capitalise lint descriptions Most test descriptions are capitalised already. Follow suit. Change-Id: I756331323a39643244c4adea4c440f305424d6d1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46321 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- util/lint/lint-008-kconfig | 2 +- util/lint/lint-stable-008-kconfig | 2 +- util/lint/lint-stable-009-old-licenses | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/lint/lint-008-kconfig b/util/lint/lint-008-kconfig index 1adb68fafa..31aba55e92 100755 --- a/util/lint/lint-008-kconfig +++ b/util/lint/lint-008-kconfig @@ -2,7 +2,7 @@ # # SPDX-License-Identifier: GPL-2.0-only -# DESCR: check Kconfig files for warnings and errors +# DESCR: Check Kconfig files for warnings and errors LC_ALL=C export LC_ALL diff --git a/util/lint/lint-stable-008-kconfig b/util/lint/lint-stable-008-kconfig index 79e2a86c0c..3b204fbd57 100755 --- a/util/lint/lint-stable-008-kconfig +++ b/util/lint/lint-stable-008-kconfig @@ -2,7 +2,7 @@ # # SPDX-License-Identifier: GPL-2.0-only -# DESCR: check Kconfig files for errors +# DESCR: Check Kconfig files for errors LC_ALL=C export LC_ALL diff --git a/util/lint/lint-stable-009-old-licenses b/util/lint/lint-stable-009-old-licenses index f5c1f4143e..d2aff3a83a 100755 --- a/util/lint/lint-stable-009-old-licenses +++ b/util/lint/lint-stable-009-old-licenses @@ -2,7 +2,7 @@ # # SPDX-License-Identifier: GPL-2.0-only -# DESCR: verify that files don't have the old style header +# DESCR: Verify that files don't have the old style header # regex list of files and directories to exclude from the search HEADER_EXCLUDED="\ From c004ae565609d61dd1de739953f64060c2350fb3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 01:20:28 +0200 Subject: [PATCH 046/354] .gitignore: Do not let git track '*.fd' These files are usually binaries, and should never be committed. Change-Id: I9df80f777020632e4c82a06ae3ae73c95234f3b5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46322 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 2fabfeef4b..97cc9ce95d 100644 --- a/.gitignore +++ b/.gitignore @@ -59,6 +59,7 @@ site-local *.debug !Kconfig.debug *.elf +*.fd *.o *.o.d *.out From 522ba1ba27bcfef8166fc1345160a32e250c01ca Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 22 Jul 2020 14:15:36 +0530 Subject: [PATCH 047/354] soc/intel/jasperlake: Enable CAR NEM enhanced mode TEST=Build and boot waddledoo board Signed-off-by: Aamir Bohra Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43705 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 2da4284ba1..8efa361c11 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select COS_MAPPED_TO_MSB select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB @@ -20,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING + select USE_CAR_NEM_ENHANCED_V1 select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM From 9b4f221026d16cc4b6dc0eadad074ef44ff1ffed Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 10 Oct 2020 15:53:33 +0530 Subject: [PATCH 048/354] mb/intel/adlrvp: Add ADL-P ramstage mainboard code List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/Makefile.inc | 5 + src/mainboard/intel/adlrvp/ec.c | 19 ++ src/mainboard/intel/adlrvp/mainboard.c | 40 +++ src/mainboard/intel/adlrvp/smihandler.c | 30 ++ .../adlrvp/variants/adlrvp_p/Makefile.inc | 2 + .../adlrvp/variants/adlrvp_p/devicetree.cb | 129 +++++++- .../intel/adlrvp/variants/adlrvp_p/gpio.c | 297 ++++++++++++++++++ .../variants/baseboard/include/baseboard/ec.h | 73 +++++ .../baseboard/include/baseboard/variants.h | 3 +- 9 files changed, 594 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/intel/adlrvp/ec.c create mode 100644 src/mainboard/intel/adlrvp/mainboard.c create mode 100644 src/mainboard/intel/adlrvp/smihandler.c create mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c create mode 100644 src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index e8a0eca790..2ca32f3760 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -11,7 +11,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c +ramstage-y += board_id.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/adlrvp/ec.c b/src/mainboard/intel/adlrvp/ec.c new file mode 100644 index 0000000000..14760017ef --- /dev/null +++ b/src/mainboard/intel/adlrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c new file mode 100644 index 0000000000..fb2557836a --- /dev/null +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board_id.h" + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/adlrvp/smihandler.c b/src/mainboard/intel/adlrvp/smihandler.c new file mode 100644 index 0000000000..a3b43231ec --- /dev/null +++ b/src/mainboard/intel/adlrvp/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc index 8c0572163b..513963ebd5 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc @@ -3,3 +3,5 @@ bootblock-y += early_gpio.c romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 47a2e91cb5..7025b7654f 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -4,6 +4,34 @@ chip soc/intel/alderlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + # Enable Speed Shift Technology/HWP support + register "speed_shift_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" @@ -41,6 +69,101 @@ chip soc/intel/alderlake # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[6]" = "0xff" + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics @@ -107,7 +230,7 @@ chip soc/intel/alderlake device pci 17.0 on end # SATA device pci 19.0 off end # I2C4 device pci 19.1 on end # I2C5 - device pci 19.2 on end # UART2 + device pci 19.2 off end # UART2 device pci 1c.0 on end # RP1 device pci 1c.1 off end # RP2 device pci 1c.2 off end # RP3 @@ -120,9 +243,9 @@ chip soc/intel/alderlake device pci 1d.1 off end # RP10 device pci 1d.2 off end # RP11 device pci 1d.3 off end # RP12 - device pci 1e.0 off end # UART0 + device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 - device pci 1e.2 off end # GSPI0 + device pci 1e.2 on end # GSPI0 device pci 1e.3 off end # GSPI1 device pci 1f.0 on end # eSPI device pci 1f.1 on end # P2SB diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c new file mode 100644 index 0000000000..5a2199203f --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM1-IRQ */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(0) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(0) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 0) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* I2C_SCL(6) */ + PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), + /* I2C_SCL(7) */ + PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* I2C_SDA(6) */ + PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), + /* I2C_SDA(7) */ + PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC1 pins */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* USB2 OC2 pins */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..4303faf0d2 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 5288b6f832..005ec83a56 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,7 +20,8 @@ enum adl_boardid { /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct cros_gpio *variant_cros_gpios(size_t *num); - +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void); size_t variant_memory_sku(void); From 7223bfa47ea831fca634550ad7e7a534d0fe8ec9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 10 Oct 2020 16:37:44 +0530 Subject: [PATCH 049/354] mb/intel/adlrvp: Add ADL-P mainboard ASL code Add required ASL files into dsdt.asl TEST=Dump and disassemble DSDT and verify all ACPI devices are present. Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/dsdt.asl | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 6163d01d3c..d4fb7a4273 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include DefinitionBlock( "dsdt.aml", @@ -11,5 +13,35 @@ DefinitionBlock( 0x20110725 /* OEM revision */ ) { + #include + /* global NVS and variables */ + #include + + #include + + Device (\_SB.PCI0) { + #include + #include + #include + #include + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +#endif + + #include } From 7ded1afe0a518c65c5f2850984419287ac880fa1 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 1 Oct 2020 15:36:42 -0600 Subject: [PATCH 050/354] lib and libpayload: add 64-bit versions of clz, __ffs and log2 Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`, and `log2_64`. Signed-off-by: Tim Wawrzynczak Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- payloads/libpayload/include/libpayload.h | 8 ++++++++ src/include/lib.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 01d71b8e61..475fe0f3fc 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -454,6 +454,14 @@ static inline int clz(u32 x) static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } + +static inline int clz64(u64 x) +{ + return x ? __builtin_clzll(x) : sizeof(x) * 8; +} + +static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } +static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } /** @} */ /** diff --git a/src/include/lib.h b/src/include/lib.h index 46d8b02112..a0003d3e29 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -56,4 +56,8 @@ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } +static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } +static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } + #endif /* __LIB_H__ */ From b27b0fd2ac06e9aa8bafb8f780e5859da5bf6420 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 22 Sep 2020 23:09:24 -0700 Subject: [PATCH 051/354] mb/google/volteer: Disable HybridStorageMode for volteer baseboard HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/volteer/variants/volteer/overridetree.cb | 2 ++ src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 330accca40..28d903f7a3 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -87,7 +87,7 @@ chip soc/intel/tigerlake # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" - register "HybridStorageMode" = "1" + register "HybridStorageMode" = "0" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 5079493437..2c120d59c7 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -47,6 +47,8 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "HybridStorageMode" = "1" + device domain 0 on device ref ipu on end device ref i2c0 on diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index f8dcd58cc2..d49a52a89b 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -5,6 +5,8 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + register "HybridStorageMode" = "1" + device domain 0 on device ref dptf on chip drivers/intel/dptf From 3e314636a63e5f981eb038a2767bd606fea9f468 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 14 Oct 2020 22:27:51 +0200 Subject: [PATCH 052/354] soc/intel/skylake/cpu.c: Fix comment coding style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1fa5..f1b40f6d01 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@ static void configure_isst(void) if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ From adcb870837518283fac6eac24a628d42912fd4a3 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Sat, 14 Mar 2020 01:53:25 +0000 Subject: [PATCH 053/354] soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/skylake/chip.c | 2 ++ src/soc/intel/skylake/chip.h | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index dfbdfb812d..4139570f64 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -212,6 +212,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; if (config->PcieRpAspm[i]) params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_l1substates[i]) + params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } /* diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fa30c1dfcf..5befb01a91 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -264,6 +264,14 @@ struct soc_intel_skylake_config { AspmAutoConfig, } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ + enum { + L1SS_Default, + L1SS_Disabled, + L1SS_L1_1, + L1SS_L1_2, + } pcie_rp_l1substates[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; From 11334729c9aa3f09b3e01a491a2d007a0aea7201 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 5 Oct 2020 16:34:03 +0200 Subject: [PATCH 054/354] security/intel/txt: Use `smm_region()` to get TSEG base This function is available for all TXT-capable platforms. Use it. As it also provides the size of TSEG, display it when logging is on. Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46055 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/logging.c | 10 ++++++++-- src/security/intel/txt/ramstage.c | 11 ++++++++--- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 24def330f9..7d8dcf7979 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -211,7 +212,12 @@ void txt_dump_chipset_info(void) void txt_dump_regions(void) { struct txt_biosdataregion *bdr = NULL; - uintptr_t tseg = 0; + + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + uint64_t reg64; reg64 = read64((void *)TXT_HEAP_BASE); @@ -219,7 +225,7 @@ void txt_dump_regions(void) (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); - printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx\n", tseg * MiB); + printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx, size %zu MiB\n", tseg_base, tseg_size / MiB); printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index bc30da5c13..263bc9daa6 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -204,7 +205,11 @@ static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length) static void lockdown_intel_txt(void *unused) { const uint64_t status = read64((void *)TXT_SPAD); - uintptr_t tseg = 0; + + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); if (status & ACMSTS_TXT_DISABLED) return; @@ -232,7 +237,7 @@ static void lockdown_intel_txt(void *unused) union dpr_register dpr = { .lock = 1, .size = 3, - .top = tseg, + .top = tseg_base / MiB, }; write64((void *)TXT_DPR, dpr.raw); @@ -248,7 +253,7 @@ static void lockdown_intel_txt(void *unused) */ write64((void *)TXT_HEAP_SIZE, 0xE0000); write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN((tseg * MiB) - read64((void *)TXT_HEAP_SIZE), 4096)); + ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); /* * Document Number: 558294 From 4b290b7b6f763f369b78cb83054e6ad65d83c4a3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 24 Sep 2020 23:38:53 +0200 Subject: [PATCH 055/354] nb/intel/haswell: Account for DPR region in memory map While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/haswell/memmap.c | 45 +++++++++++++++---- src/northbridge/intel/haswell/northbridge.c | 25 +++++++++-- .../intel/haswell/registers/host_bridge.h | 3 ++ 3 files changed, 62 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 807ee2a358..ac36e25999 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -9,27 +9,56 @@ #include #include #include +#include + #include "haswell.h" -static uintptr_t smm_region_start(void) +static uintptr_t northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); +} + +static size_t northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +/* + * Return the topmost memory address below 4 GiB available for general + * use, from software's view of memory. Do not confuse this with TOLUD, + * which applies to the DRAM as viewed by the memory controller itself. + */ +static uintptr_t top_of_low_usable_memory(void) { /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignment. + * Base of DPR is top of usable DRAM below 4 GiB. However, DPR + * isn't always enabled. Unlike most memory map registers, the + * DPR register stores top of DPR instead of its base address. + * Unless binary-patched, Haswell MRC.bin does not enable DPR. + * Top of DPR is R/O, and mirrored from TSEG base by hardware. */ - uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); - return ALIGN_DOWN(tom, 1 * MiB); + uintptr_t tolum = northbridge_get_tseg_base(); + + const union dpr_register dpr = { + .raw = pci_read_config32(HOST_BRIDGE, DPR), + }; + + /* Subtract DMA Protected Range size if enabled */ + if (dpr.epm) + tolum -= dpr.size * MiB; + + return tolum; } void *cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (void *)top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) { - *start = smm_region_start(); - *size = CONFIG_SMM_TSEG_SIZE; + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d162c..5619d95728 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "chip.h" #include "haswell.h" @@ -162,7 +163,8 @@ static void mc_add_fixed_mmio_resources(struct device *dev) } } -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ TOUUD * | | @@ -175,6 +177,8 @@ static void mc_add_fixed_mmio_resources(struct device *dev) * +--------------------------+ BGSM * | TSEG | * +--------------------------+ TSEGMB + * | DPR | + * +--------------------------+ (DPR top - DPR size) * | Usage DRAM | * +--------------------------+ 0 * @@ -285,6 +289,12 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); + /* The DPR register is special */ + const union dpr_register dpr = { + .raw = pci_read_config32(dev, DPR), + }; + printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw); + /* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable @@ -318,11 +328,20 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xc0000 -> TSEG */ + /* 0xc0000 -> DPR base */ base_k = 0xc0000 >> 10; - size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - (base_k + dpr.size); ram_resource(dev, index++, base_k, size_k); + /* DPR base -> TSEG */ + if (dpr.size) { + resource = new_resource(dev, index++); + resource->base = (dpr.top - dpr.size) * MiB; + resource->size = dpr.size * MiB; + resource->flags = IORESOURCE_MEM | IORESOURCE_STORED | IORESOURCE_CACHEABLE | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + /* TSEG -> BGSM */ resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG]; diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h index d348fd4a61..7746801804 100644 --- a/src/northbridge/intel/haswell/registers/host_bridge.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -25,6 +25,9 @@ #define PAVPC 0x58 #define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 #define PCIEXBAR 0x60 #define DMIBAR 0x68 From 7af8aca2460c5ad138484bc3f37891fac454d8b1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 14 Oct 2020 09:51:29 +0200 Subject: [PATCH 056/354] sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPE This needs to be saved and restored, otherwise the BSP might have an inconsistent MTRR setup with regards to the AP's which results in weird errors and slowdowns in the operating system. TESTED: Fixes booting OCP/Deltalake with Linux 5.8. Change-Id: Iace636ec6fca3b4d7b2856f0f054947c5b3bc8de Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46375 Reviewed-by: Angel Pons Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/security/intel/txt/getsec_enteraccs.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 3135de79b2..563dc08a15 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -58,6 +58,7 @@ getsec_enteraccs: /* Reserve space on stack for GDT */ subl $8, %esp + PUSH_MSR MTRR_DEF_TYPE_MSR PUSH_MSR IA32_MISC_ENABLE PUSH_MSR MTRR_FIX_64K_00000 PUSH_MSR MTRR_FIX_16K_80000 @@ -290,12 +291,7 @@ cond_pop_var_mtrrs: POP_MSR MTRR_FIX_16K_80000 POP_MSR MTRR_FIX_64K_00000 POP_MSR IA32_MISC_ENABLE - - /* Enable fixed MTRRs */ - movl $(MTRR_DEF_TYPE_MSR), %ecx - rdmsr - orl $(MTRR_DEF_TYPE_FIX_EN), %eax - wrmsr + POP_MSR MTRR_DEF_TYPE_MSR /* Enable cache */ movl %cr0, %eax From e4478637bda90e6cf566594f9edfc24bb3f18dad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 19 Jul 2020 22:56:35 +0200 Subject: [PATCH 057/354] =?UTF-8?q?MAINTAINERS:=20add=20Michael=20Niew?= =?UTF-8?q?=C3=B6hner=20to=20mb/clevo?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Michael Niewöhner as another maintainer for Clevo mainboards. Signed-off-by: Michael Niewöhner Change-Id: Id3b35ddda13119149321e8c883e151176d8c520d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43655 Reviewed-by: Angel Pons Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8198be4af6..d867c78465 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -210,6 +210,7 @@ F: src/mainboard/asus/p8z77-v_lx2/ CLEVO MAINBOARDS M: Felix Singer +M: Michael Niewöhner S: Supported F: src/mainboard/clevo From 232d8a8eb57a0e343369ba869d71ca27b4b1ad88 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 23 Jun 2020 12:25:24 +0800 Subject: [PATCH 058/354] Update bit field helpers to support more bit field operate Signed-off-by: Huayang Duan Change-Id: I8f182fff45806912da2390939a6652932501d7c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44705 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/include/device/mmio.h | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h index b4461e05e7..9b79d79bb5 100644 --- a/src/include/device/mmio.h +++ b/src/include/device/mmio.h @@ -150,21 +150,44 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo, _BF_APPLY6(op, __VA_ARGS__)) #define _BF_APPLY8(op, name, value, ...) ((op(name, value)) | \ _BF_APPLY7(op, __VA_ARGS__)) +#define _BF_APPLY9(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY8(op, __VA_ARGS__)) +#define _BF_APPLY10(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY9(op, __VA_ARGS__)) +#define _BF_APPLY11(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY10(op, __VA_ARGS__)) +#define _BF_APPLY12(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY11(op, __VA_ARGS__)) +#define _BF_APPLY13(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY12(op, __VA_ARGS__)) +#define _BF_APPLY14(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY13(op, __VA_ARGS__)) +#define _BF_APPLY15(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY14(op, __VA_ARGS__)) +#define _BF_APPLY16(op, name, value, ...) ((op(name, value)) | \ + _BF_APPLY15(op, __VA_ARGS__)) #define _BF_APPLYINVALID(...) \ _Static_assert(0, "Invalid arguments for {WRITE,SET}*_BITFIELDS") #define _BF_IMPL2(op, addr, \ n1, v1, n2, v2, n3, v3, n4, v4, n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, n13, v13, n14, v14, n15, v15, n16, v16, \ NARGS, ...) \ \ op(addr, \ _BF_APPLY##NARGS(_BF_MASK, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8), \ + n5, v5, n6, v6, n7, v7, n8, v8, \ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16), \ _BF_APPLY##NARGS(_BF_VALUE, n1, v1, n2, v2, n3, v3, n4, v4, \ - n5, v5, n6, v6, n7, v7, n8, v8)) + n5, v5, n6, v6, n7, v7, n8, v8,\ + n9, v9, n10, v10, n11, v11, n12, v12, \ + n13, v13, n14, v14, n15, v15, n16, v16)) #define _BF_IMPL(op, addr, ...) \ _BF_IMPL2(op, addr, __VA_ARGS__, \ + 16, INVALID, 15, INVALID, 14, INVALID, 13, INVALID, \ + 12, INVALID, 11, INVALID, 10, INVALID, 9, INVALID, \ 8, INVALID, 7, INVALID, 6, INVALID, 5, INVALID, \ 4, INVALID, 3, INVALID, 2, INVALID, 1, INVALID) From 42f795904c550215fc53706155ceb82f1f720117 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Mon, 21 Sep 2020 18:04:10 +0800 Subject: [PATCH 059/354] ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db. The change also drops unneeded empty lines and coverts license header to SPDX style. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/46403 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu --- src/ec/google/chromeec/ec_commands.h | 228 ++++++++++++++++++++++++++- 1 file changed, 226 insertions(+), 2 deletions(-) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4c3d0bb838..4e40c6dee5 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -2520,6 +2520,12 @@ enum motionsense_command { */ MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* + * Activity management + * Retrieve current status of given activity. + */ + MOTIONSENSE_CMD_GET_ACTIVITY = 20, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2572,6 +2578,8 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, MOTIONSENSE_CHIP_LIS2DS = 23, + MOTIONSENSE_CHIP_BMI260 = 24, + MOTIONSENSE_CHIP_ICM426XX = 25, MOTIONSENSE_CHIP_MAX, }; @@ -2592,6 +2600,8 @@ struct ec_response_motion_sensor_data { /* Each sensor is up to 3-axis. */ union { int16_t data[3]; + /* for sensors using unsigned data */ + uint16_t udata[3]; struct __ec_todo_packed { uint16_t reserved; uint32_t timestamp; @@ -2637,6 +2647,7 @@ enum motionsensor_activity { MOTIONSENSE_ACTIVITY_SIG_MOTION = 1, MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2, MOTIONSENSE_ACTIVITY_ORIENTATION = 3, + MOTIONSENSE_ACTIVITY_BODY_DETECTION = 4, }; struct ec_motion_sense_activity { @@ -2820,6 +2831,7 @@ struct ec_params_motion_sense { uint32_t max_data_vector; } fifo_read; + /* Used for MOTIONSENSE_CMD_SET_ACTIVITY */ struct ec_motion_sense_activity set_activity; /* Used for MOTIONSENSE_CMD_LID_ANGLE */ @@ -2874,6 +2886,13 @@ struct ec_params_motion_sense { uint8_t sensor_num; } online_calib_read; + /* + * Used for MOTIONSENSE_CMD_GET_ACTIVITY. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + uint8_t activity; /* enum motionsensor_activity */ + } get_activity; }; } __ec_todo_packed; @@ -3025,6 +3044,10 @@ struct ec_response_motion_sense { uint16_t hys_degree; } tablet_mode_threshold; + /* USED for MOTIONSENSE_CMD_GET_ACTIVITY. */ + struct __ec_todo_unpacked { + uint8_t state; + } get_activity; }; } __ec_todo_packed; @@ -4429,6 +4452,7 @@ struct ec_params_charge_state { uint32_t value; /* value to set */ } set_param; }; + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4982,6 +5006,7 @@ enum ec_codec_i2s_rx_subcmd { EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2, EC_CODEC_I2S_RX_SET_DAIFMT = 0x3, EC_CODEC_I2S_RX_SET_BCLK = 0x4, + EC_CODEC_I2S_RX_RESET = 0x5, EC_CODEC_I2S_RX_SUBCMD_COUNT, }; @@ -5094,6 +5119,33 @@ struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm { uint32_t len; }; +/*****************************************************************************/ +/* Commands for PoE PSE controller */ + +#define EC_CMD_PSE 0x00C0 + +enum ec_pse_subcmd { + EC_PSE_STATUS = 0x0, + EC_PSE_ENABLE = 0x1, + EC_PSE_DISABLE = 0x2, + EC_PSE_SUBCMD_COUNT, +}; + +struct __ec_align1 ec_params_pse { + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ +}; + +enum ec_pse_status { + EC_PSE_STATUS_DISABLED = 0x0, + EC_PSE_STATUS_ENABLED = 0x1, + EC_PSE_STATUS_POWERED = 0x2, +}; + +struct __ec_align1 ec_response_pse_status { + uint8_t status; /* enum ec_pse_status */ +}; + /*****************************************************************************/ /* System commands */ @@ -5112,7 +5164,7 @@ enum ec_reboot_cmd { EC_REBOOT_COLD = 4, /* Cold-reboot */ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ - EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */ + EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5330,7 +5382,8 @@ struct ec_response_usb_pd_control_v2 { uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - uint8_t cable_speed; /* TBT_SS_* cable speed */ + /* TODO: b:158234949 Add definitions for cable speed */ + uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5386,6 +5439,7 @@ struct ec_response_usb_pd_power_info { uint32_t max_power; } __ec_align4; + /* * This command will return the number of USB PD charge port + the number * of dedicated port present. @@ -5587,6 +5641,7 @@ struct ec_params_pd_write_log_entry { uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __ec_align1; + /* Control USB-PD chip */ #define EC_CMD_PD_CONTROL 0x0119 @@ -5711,6 +5766,8 @@ enum cbi_data_tag { CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + /* Second Source Factory Cache */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_COUNT, }; @@ -5775,6 +5832,9 @@ struct ec_params_set_cbi { #define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This * enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ struct ec_response_uptime_info { /* @@ -5870,6 +5930,7 @@ struct ec_response_rollback_info { int32_t rw_rollback_version; } __ec_align4; + /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -5911,6 +5972,7 @@ struct ec_params_locate_chip { }; } __ec_align2; + struct ec_response_locate_chip { uint8_t bus_type; /* enum ec_bus_type */ uint8_t reserved; /* Aligning the following union to 2 bytes */ @@ -6035,6 +6097,7 @@ enum keyboard_button_type { KEYBOARD_BUTTON_COUNT }; + /*****************************************************************************/ /* * "Get the Keyboard Config". An EC implementing this command is expected to be @@ -6113,6 +6176,164 @@ struct ec_response_keybd_config { } __ec_align1; +/* + * Configure smart discharge + */ +#define EC_CMD_SMART_DISCHARGE 0x012B + +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) + +/* Discharge rates when the system is in cutoff or hibernation. */ +struct discharge_rate { + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ +}; + +struct smart_discharge_zone { + /* When the capacity (mAh) goes below this, EC cuts off the battery. */ + int cutoff; + /* When the capacity (mAh) is below this, EC stays up. */ + int stayup; +}; + +struct ec_params_smart_discharge { + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + /* + * Desired hours for the battery to survive before reaching 0%. Set to + * zero to disable smart discharging. That is, the system hibernates as + * soon as the G3 idle timer expires. + */ + uint16_t hours_to_zero; + /* Set both to zero to keep the current rates. */ + struct discharge_rate drate; +}; + +struct ec_response_smart_discharge { + uint16_t hours_to_zero; + struct discharge_rate drate; + struct smart_discharge_zone dzone; +}; + +/*****************************************************************************/ +/* Voltage regulator controls */ + +/* + * Get basic info of voltage regulator for given index. + * + * Returns the regulator name and supported voltage list in mV. + */ +#define EC_CMD_REGULATOR_GET_INFO 0x012C + +/* Maximum length of regulator name */ +#define EC_REGULATOR_NAME_MAX_LEN 16 + +/* Maximum length of the supported voltage list. */ +#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16 + +struct ec_params_regulator_get_info { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_info { + char name[EC_REGULATOR_NAME_MAX_LEN]; + uint16_t num_voltages; + uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT]; +} __ec_align2; + +/* + * Configure the regulator as enabled / disabled. + */ +#define EC_CMD_REGULATOR_ENABLE 0x012D + +struct ec_params_regulator_enable { + uint32_t index; + uint8_t enable; +} __ec_align4; + +/* + * Query if the regulator is enabled. + * + * Returns 1 if the regulator is enabled, 0 if not. + */ +#define EC_CMD_REGULATOR_IS_ENABLED 0x012E + +struct ec_params_regulator_is_enabled { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_is_enabled { + uint8_t enabled; +} __ec_align1; + +/* + * Set voltage for the voltage regulator within the range specified. + * + * The driver should select the voltage in range closest to min_mv. + * + * Also note that this might be called before the regulator is enabled, and the + * setting should be in effect after the regulator is enabled. + */ +#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F + +struct ec_params_regulator_set_voltage { + uint32_t index; + uint32_t min_mv; + uint32_t max_mv; +} __ec_align4; + +/* + * Get the currently configured voltage for the voltage regulator. + * + * Note that this might be called before the regulator is enabled, and this + * should return the configured output voltage if the regulator is enabled. + */ +#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130 + +struct ec_params_regulator_get_voltage { + uint32_t index; +} __ec_align4; + +struct ec_response_regulator_get_voltage { + uint32_t voltage_mv; +} __ec_align4; + +/* + * Gather all discovery information for the given port and partner type. + * + * Note that if discovery has not yet completed, only the currently completed + * responses will be filled in. If the discovery data structures are changed + * in the process of the command running, BUSY will be returned. + * + * VDO field sizes are set to the maximum possible number of VDOs a VDM may + * contain, while the number of SVIDs here is selected to fit within the PROTO2 + * maximum parameter size. + */ +#define EC_CMD_TYPEC_DISCOVERY 0x0131 + +enum typec_partner_type { + TYPEC_PARTNER_SOP = 0, + TYPEC_PARTNER_SOP_PRIME = 1, +}; + +struct ec_params_typec_discovery { + uint8_t port; + uint8_t partner_type; /* enum typec_partner_type */ +} __ec_align1; + +struct svid_mode_info { + uint16_t svid; + uint16_t mode_count; /* Number of modes partner sent */ + uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ +}; + +struct ec_response_typec_discovery { + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ + uint16_t reserved; + uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ + struct svid_mode_info svids[0]; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6156,6 +6377,8 @@ struct ec_params_fp_passthru { #define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ #define FP_MODE_RESET_SENSOR BIT(7) +/* Sensor maintenance for dead pixels. */ +#define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ #define FP_MODE_DONT_CHANGE BIT(31) @@ -6167,6 +6390,7 @@ struct ec_params_fp_passthru { FP_MODE_ENROLL_IMAGE | \ FP_MODE_MATCH | \ FP_MODE_RESET_SENSOR | \ + FP_MODE_SENSOR_MAINTENANCE | \ FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ From e1db55b43ea2e450a215efad1228498493dd6086 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 28 Sep 2020 16:53:19 -0600 Subject: [PATCH 060/354] soc/intel/xeon_sp: Add get_system_memory_map() Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847 Reviewed-by: Angel Pons Reviewed-by: Jay Talbott Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/skx/include/soc/soc_util.h | 1 + src/soc/intel/xeon_sp/skx/soc_acpi.c | 8 +++----- src/soc/intel/xeon_sp/skx/soc_util.c | 11 +++++++++++ 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index c7f7383731..0eac8368e0 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -30,6 +30,7 @@ void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); +const struct SystemMemoryMapHob *get_system_memory_map(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index c986214b3c..9c07ec7021 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -179,13 +179,11 @@ unsigned long acpi_create_srat_lapics(unsigned long current) static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) { const struct SystemMemoryMapHob *memory_map; - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; unsigned int mmap_index; - memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memory_map != NULL && hob_size != 0); - printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + memory_map = get_system_memory_map(); + assert(memory_map != NULL); + printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); mmap_index = 0; for (int e = 0; e < memory_map->numberEntries; ++e) { diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index e21edbc8f7..50f091ec94 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -373,6 +373,17 @@ void get_iiostack_info(struct iiostack_resource *info) } #if ENV_RAMSTAGE +const struct SystemMemoryMapHob *get_system_memory_map(void) +{ + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob *memmap_addr; + + memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memmap_addr != NULL && hob_size != 0); + + return memmap_addr; +} void xeonsp_init_cpu_config(void) { From e0ce60c744f0ebea16bd6a1665f23ccf4461c7c3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 14 Oct 2020 17:48:05 +0200 Subject: [PATCH 061/354] lib and libpayload: Add popcnt functions Add 32-bit `popcnt` and 64-bit `popcnt64` helpers. Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- payloads/libpayload/include/libpayload.h | 3 +++ src/include/lib.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 475fe0f3fc..b761f042b9 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -445,6 +445,8 @@ u8 hex2bin(u8 h); void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__((noreturn)); +/* Population Count: number of bits that are one */ +static inline int popcnt(u32 x) { return __builtin_popcount(x); } /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { @@ -455,6 +457,7 @@ static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; diff --git a/src/include/lib.h b/src/include/lib.h index a0003d3e29..5c6eef2a70 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -46,6 +46,8 @@ void hexdump32(char LEVEL, const void *d, size_t len); */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); +/* Population Count: number of bits that are one */ +static inline int popcnt(u32 x) { return __builtin_popcount(x); } /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ @@ -56,6 +58,7 @@ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } From bf38d58420340faac5acf595120c6bca35175ffe Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 21:53:59 +0530 Subject: [PATCH 062/354] mb/intel/adlrvp: Program GPIO for M.2 PCH SSD This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index 5a2199203f..e142e88e57 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -70,7 +70,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* Sata direct Power */ PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* THC0 SPI1 CLK */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), /* THC0 SPI1 IO 1 */ From 604a104a1c1df55345f5a90c577cbce4b52de323 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 22:02:48 +0530 Subject: [PATCH 063/354] mb/intel/adlrvp: Fix SSD detection issue on ADL RVP Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 7025b7654f..afa4c19098 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -43,7 +43,7 @@ chip soc/intel/alderlake # Enable PCH PCIE RP 5 using CLK 2 register "PcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcUsage[2]" = "0x4" register "PcieRpClkReqDetect[4]" = "1" @@ -55,7 +55,7 @@ chip soc/intel/alderlake # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" From 6147314344ae257081ec91dd709b18da283878fc Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 22:06:48 +0530 Subject: [PATCH 064/354] mb/intel/adlrvp: Enable PCIE RP11 for optane A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index afa4c19098..fadf602536 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -59,6 +59,9 @@ chip soc/intel/alderlake register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" + # Enable PCH PCIE RP 11 for optane + register "PcieRpEnable[10]" = "1" + # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" @@ -241,7 +244,7 @@ chip soc/intel/alderlake device pci 1c.7 off end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 - device pci 1d.2 off end # RP11 + device pci 1d.2 on end # RP11 device pci 1d.3 off end # RP12 device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 From 3f561a8e081f1256dcd6be1a0f4107b114a14ea1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 22:12:12 +0530 Subject: [PATCH 065/354] mb/intel/adlrvp: Enable Hybrid storage mode TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index fadf602536..818f32f9fa 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -61,6 +61,8 @@ chip soc/intel/alderlake # Enable PCH PCIE RP 11 for optane register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" From efe581254e010353bf340731b4a251c3edf777bc Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 12 Oct 2020 15:53:56 +0800 Subject: [PATCH 066/354] mb/google/zork: disable eMMC per FW_CONFIG for berknip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Berknip has SSD/eMMC SKU, we should turn off eMMC　if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Rob Barnes --- .../google/zork/variants/berknip/Makefile.inc | 1 + .../google/zork/variants/berknip/variant.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 src/mainboard/google/zork/variants/berknip/variant.c diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc index 57e7136ddc..51d19fe9ba 100644 --- a/src/mainboard/google/zork/variants/berknip/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/berknip/variant.c b/src/mainboard/google/zork/variants/berknip/variant.c new file mode 100644 index 0000000000..092ff260b3 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/variant.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + /* + * Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned. + */ + if (!(variant_has_emmc() || boot_is_factory_unprovisioned())) + cfg->emmc_config.timing = SD_EMMC_DISABLE; +} From 3f1de9add900305730a28be919a21a682ae6b224 Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Wed, 14 Oct 2020 13:38:29 -0600 Subject: [PATCH 067/354] acpi/acpigen_dsm: fix I2C HID DSM to report correct function support Fix DSM function 0 (query function) to correctly report function support for its revision. Revision 1 should return 0x3 because I2C HID supports only 1 additional function. All other revisions should return 0. BUG=b:170862147 BRANCH=Zork TEST=ensure no dmesg errors; disassemble and verify SSDT Signed-off-by: Josie Nordrum Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46429 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/acpi/acpigen_dsm.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/acpi/acpigen_dsm.c b/src/acpi/acpigen_dsm.c index 2336537d0b..fc53ddff4d 100644 --- a/src/acpi/acpigen_dsm.c +++ b/src/acpi/acpigen_dsm.c @@ -7,28 +7,27 @@ #define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" +/* I2C HID currently supports revision 1 only, for which, only 1 additional + * function is supported. Thus, the query function should return 0x3: + * bit 0 = additional function supported + * bit 1 = function with index 1 supported + * All other revisions do not support additional functions and hence return 0 +*/ + static void i2c_hid_func0_cb(void *arg) { /* ToInteger (Arg1, Local2) */ acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); - /* If (LEqual (Local2, 0x0)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x0); - /* Return (Buffer (One) { 0x1f }) */ - acpigen_write_return_singleton_buffer(0x1f); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3 }) */ + acpigen_write_return_singleton_buffer(0x3); acpigen_pop_len(); /* Pop : If */ /* Else */ acpigen_write_else(); - /* If (LEqual (Local2, 0x1)) */ - acpigen_write_if_lequal_op_int(LOCAL2_OP, 0x1); - /* Return (Buffer (One) { 0x3f }) */ - acpigen_write_return_singleton_buffer(0x3f); - acpigen_pop_len(); /* Pop : If */ - /* Else */ - acpigen_write_else(); /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); /* Pop : Else */ - acpigen_pop_len(); /* Pop : Else */ } static void i2c_hid_func1_cb(void *arg) From b53858bacee1b3561ab0c70e3f82196f4e7eb6cb Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Mon, 12 Oct 2020 04:19:42 +0000 Subject: [PATCH 068/354] soc/intel/skylake: Rename PcieRpAspm devicetree config This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/facebook/monolith/devicetree.cb | 6 +++--- src/soc/intel/skylake/chip.c | 4 ++-- src/soc/intel/skylake/chip.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 95e2565a80..bb11d064b3 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -151,7 +151,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[2]" = "1" # Disable Aspm - register "PcieRpAspm[2]" = "AspmDisabled" + register "pcie_rp_aspm[2]" = "AspmDisabled" # PCIE Port 4 disabled # PCIE Port 5 x1 -> MODULE i219 @@ -166,7 +166,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Disable Aspm - register "PcieRpAspm[5]" = "AspmDisabled" + register "pcie_rp_aspm[5]" = "AspmDisabled" # PCIE Port 7 Disabled # PCIE Port 8 Disabled @@ -184,7 +184,7 @@ chip soc/intel/skylake # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[8]" = "1" # Disable Aspm - register "PcieRpAspm[8]" = "AspmDisabled" + register "pcie_rp_aspm[8]" = "AspmDisabled" # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4139570f64..549f403384 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -210,8 +210,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; - if (config->PcieRpAspm[i]) - params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + if (config->pcie_rp_aspm[i]) + params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1; if (config->pcie_rp_l1substates[i]) params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5befb01a91..2584d5d809 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -262,7 +262,7 @@ struct soc_intel_skylake_config { AspmL1, AspmL0sL1, AspmAutoConfig, - } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum { From d32bb116f063d04e0c5f72e6fd0367d6e542c9fb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 11 Oct 2020 22:32:58 +0200 Subject: [PATCH 069/354] libpayload/x86: Add some more CPUID helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic88defd30c6d3791a51b78a14135aff55e89394d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46285 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- payloads/libpayload/include/x86/arch/cpuid.h | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h index 83733016fe..c77be9cff2 100644 --- a/payloads/libpayload/include/x86/arch/cpuid.h +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -32,4 +32,36 @@ #define cpuid(fn, eax, ebx, ecx, edx) \ asm("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "0"(fn)) +#define _declare_cpuid(reg) \ + static inline unsigned int cpuid_##reg(unsigned int fn) \ + { \ + unsigned int eax, ebx, ecx, edx; \ + cpuid(fn, eax, ebx, ecx, edx); \ + return reg; \ + } + +_declare_cpuid(eax) +_declare_cpuid(ebx) +_declare_cpuid(ecx) +_declare_cpuid(edx) + +#undef _declare_cpuid + +static inline unsigned int cpuid_max(void) +{ + return cpuid_eax(0); +} + +static inline unsigned int cpuid_family(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xff00000) >> (20 - 4) | (eax & 0xf00) >> 8; +} + +static inline unsigned int cpuid_model(void) +{ + const unsigned int eax = cpuid_eax(1); + return (eax & 0xf0000) >> (16 - 4) | (eax & 0xf0) >> 4; +} + #endif From 90df9166834f26a7600d089bc2fade0f34fd6681 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 13 Oct 2020 22:58:28 +0200 Subject: [PATCH 070/354] include/cpu/x86: introduce new helper for (un)setting MSRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/finalize.c | 3 +- src/cpu/intel/model_2065x/finalize.c | 7 +-- src/cpu/intel/model_206ax/finalize.c | 7 +-- src/include/cpu/x86/msr.h | 49 ++++++++++++++----- src/soc/intel/common/block/cpu/cpulib.c | 2 +- .../common/block/include/intelblocks/msr.h | 2 +- 6 files changed, 48 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1832e63967..3bf9225a1f 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include "haswell.h" @@ -7,5 +8,5 @@ void intel_cpu_haswell_finalize_smm(void) { /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index d530fba5e7..d19ddf7a34 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,12 +14,12 @@ void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); + msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15)); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); + msr_set(MSR_FEATURE_CONFIG, BIT(0)); /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 37fbefdf13..98be012746 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include "model_206ax.h" @@ -13,11 +14,11 @@ void intel_model_206ax_finalize_smm(void) { /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); + msr_set(MSR_FEATURE_CONFIG, BIT(0)); /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 3deb133240..058419fd1e 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -299,23 +299,46 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } -/* Helper for setting single MSR bits */ -static inline void msr_set_bit(unsigned int reg, unsigned int bit) +/** + * Helper for (un)setting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] unset Bitmask with ones to the bits to unset from the MSR. + * @param[in] set Bitmask with ones to the bits to set from the MSR. + */ +static inline void msr_unset_and_set(unsigned int reg, uint64_t unset, uint64_t set) { - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } + msr_t msr; + msr = rdmsr(reg); + msr.lo &= (unsigned int)~unset; + msr.hi &= (unsigned int)~(unset >> 32); + msr.lo |= (unsigned int)set; + msr.hi |= (unsigned int)(set >> 32); wrmsr(reg, msr); } +/** + * Helper for setting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] set Bitmask with ones to the bits to set from the MSR. + */ +static inline void msr_set(unsigned int reg, uint64_t set) +{ + msr_unset_and_set(reg, 0, set); +} + +/** + * Helper for unsetting MSR bitmasks + * + * @param[in] reg The MSR. + * @param[in] unset Bitmask with ones to the bits to unset from the MSR. + */ +static inline void msr_unset(unsigned int reg, uint64_t unset) +{ + msr_unset_and_set(reg, unset, 0); +} + #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index cbf9b1b9dd..9092df1796 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -337,7 +337,7 @@ void mca_configure(void) void cpu_lt_lock_memory(void *unused) { - msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); + msr_set(MSR_LT_CONTROL, LT_CONTROL_LOCK); } int get_valid_prmrr_size(void) diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 4aa069e068..2ef4561341 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -56,7 +56,7 @@ #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 -#define LT_CONTROL_LOCK_BIT (0) +#define LT_CONTROL_LOCK (1 << 0) #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define SMM_FEATURE_CONTROL_MSR 0x4e0 From 46a8cbd92d16f3365cd3a8c3b7ac4c24cebf5121 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 9 Sep 2020 15:04:21 -0700 Subject: [PATCH 071/354] trogdor/sc7180: Clarify USE_QC_BLOBS requirements This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) Reviewed-by: Philip Chen --- src/mainboard/google/trogdor/Kconfig.name | 17 ++++++++++++----- src/soc/qualcomm/sc7180/Kconfig | 1 + 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index ea1230716a..174c795d87 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,21 +1,28 @@ comment "Trogdor" +if USE_QC_BLOBS + config BOARD_GOOGLE_BUBS - bool "Bubs" + bool "-> Bubs" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_COACHZ - bool "Coachz" + bool "-> Coachz" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_LAZOR - bool "Lazor" + bool "-> Lazor" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_POMPOM - bool "Pompom" + bool "-> Pompom" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_TROGDOR - bool "Trogdor" + bool "-> Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON + +endif + +comment "(Trogdor requires 'Allow QC blobs repository')" + depends on !USE_QC_BLOBS diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index c66dc92768..c37aff9db3 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -2,6 +2,7 @@ config SOC_QUALCOMM_SC7180 bool default n + depends on USE_QC_BLOBS select ARCH_BOOTBLOCK_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 From 038cef9dffdd0df89e50799826e521b1e26b3081 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 14 Oct 2020 17:58:36 +0200 Subject: [PATCH 072/354] sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM When caching the BIOS ACM, one must cache less than a page (4 KiB) of unused memory past the end of the BIOS ACM. Failure to do so on Haswell will result in a lovely TXT reset with Class Code 5, Major Error Code 2. The current approach uses a single variable MTRR to cache the whole BIOS ACM. Before fighting with the variable MTRRs in assembly code, ensure that enough variable MTRRs exist to cache the BIOS ACM's size. Since the code checks that the ACM base is aligned to its size, each `one` bit in the ACM size will require one variable MTRR to properly cache the ACM. One of the several BIOS ACMs for Haswell has a size of 101504 bytes. This is 0x18c80 in hexadecimal, and 0001 1000 1100 1000 0000 in binary. After aligning up the BIOS ACM size to a page boundary, the resulting size is 0x19000 in hexadecimal, and 0001 1001 0000 0000 0000 in binary. To successfully invoke said ACM, its base must be a multiple of 0x20000 and three variable MTRRs must be used to cache the ACM. The MTRR ranges must be contiguous and cover 0x10000, 0x8000, 0x1000 bytes, in order. The assembly code is updated in a follow-up, and relies on these checks. Change-Id: I480dc3e4a9e4a59fbb73d571fd62b0257abc65b3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46422 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/security/intel/txt/common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index e73defb912..5f8a976946 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -266,6 +267,17 @@ int intel_txt_run_bios_acm(const u8 input_params) return -1; } + /* + * When setting up the MTRRs to cache the BIOS ACM, one must cache less than + * a page (4 KiB) of unused memory after the BIOS ACM. On Haswell, failure + * to do so will cause a TXT reset with Class Code 5, Major Error Code 2. + */ + if (popcnt(ALIGN_UP(acm_len, 4096)) > get_var_mtrr_count()) { + printk(BIOS_ERR, "TEE-TXT: Not enough MTRRs to cache this BIOS ACM's size.\n"); + rdev_munmap(&acm, acm_data); + return -1; + } + if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_acm_info(acm_data); From 578a4d2b6a0ac96d70ea3b8490872a21dcf19df2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 28 Aug 2020 00:59:14 +0200 Subject: [PATCH 073/354] security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] The BIOS ACM will check that enabled variable MTRRs do not cover more than the ACM's size, rounded up to 4 KiB. If that is not the case, launching the ACM will result in a lovely TXT reset. How boring. The new algorithm simply performs a reverse bit scan in a loop, and allocates one MTRR for each set bit in the rounded-up size to cache. Before allocating anything, it checks if there are enough variable MTRRs; if not, it will refuse to cache anything. This will result in another TXT reset, initiated by the processor, with error type 5: Load memory type error in Authenticated Code Execution Area. This can only happen if the ACM has specific caching requirements that the current code does not know about, or something has been compromised. Therefore, causing a TXT reset should be a reasonable enough approach. Also, disable all MTRRs before clearing the variable MTRRs and only enable them again once they have been set up with the new values. Tested on Asrock B85M Pro4 with a BIOS ACM whose size is 101504 bytes. Without this patch, launching the ACM would result in a TXT reset. This no longer happens when this patch is applied. Change-Id: I8d411f6450928357544be20250262c2005d1e75d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44880 Reviewed-by: Arthur Heymans Reviewed-by: Christian Walter Tested-by: build bot (Jenkins) --- src/security/intel/txt/getsec_enteraccs.S | 105 ++++++++++++++++++---- 1 file changed, 87 insertions(+), 18 deletions(-) diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 563dc08a15..be038b0607 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -108,10 +108,10 @@ cond_push_var_mtrrs: orl $(CR0_CD | CR0_NW), %eax movl %eax, %cr0 - /* Disable fixed MTRRs */ + /* Disable all MTRRs */ movl $(MTRR_DEF_TYPE_MSR), %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_FIX_EN), %eax + xorl %eax, %eax + xorl %edx, %edx wrmsr /* @@ -165,24 +165,93 @@ cond_clear_var_mtrrs: * Chapter A.1.1 * Intel TXT Software Development Guide (Document: 315168-015) */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl 12(%ebp), %eax /* %eax = acmbase */ - orl $(6), %eax /* MTRR_TYPE_WB */ - movl $0, %edx - wrmsr - /* Round acmsize to next power of two. Required for MTRR programming. */ + /* + * Important note: The MTRRs must cache less than a page (4 KiB) + * of unused memory after the BIOS ACM. Failure to do so will + * result in a TXT reset with Class Code 5, Major Error Code 2. + * + * The caller must have checked that there are enough variable + * MTRRs to cache the ACM size prior to invoking this routine. + */ + + /* Determine size of AC module */ + movl 12(%ebp), %eax /* %eax = acmbase */ movl $1, %ebx - movl 16(%ebp), %ecx /* %ebx = acmsize */ - dec %ecx - bsr %ecx, %ecx /* find MSB */ - inc %ecx - shl %cl, %ebx - movl $(MTRR_PHYS_MASK(0)), %ecx - xorl %eax, %eax - subl %ebx, %eax /* %eax = 4GIB - log2_ceil(ACM SIZE) */ - orl $((1 << 11)), %eax /* MTRR_PHYS_MASK_VALID */ + movl 16(%ebp), %ebx /* %ebx = acmsize */ + + /* Round up to page size */ + addl $(0xfff), %ebx + andl $(~0xfff), %ebx /* Aligned to a page (4 KiB) */ + + /* + * Use XMM to store local variables. This code will need to be + * used in romstage, and CAR will have been torn down by then. + */ + movd %eax, %xmm0 /* XMM0: Base address of next MTRR */ + movd %ebx, %xmm1 /* XMM1: Remaining size to cache */ + + /* Get the number of variable MTRRs */ + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + + /* Initialize ECX */ + movl $(MTRR_PHYS_BASE(0)), %ecx + + jmp cond_allocate_var_mtrrs + +body_allocate_var_mtrrs: + + /* Program MTRR base */ + xorl %edx, %edx + movd %xmm0, %eax + orl $(MTRR_TYPE_WRBACK), %eax + wrmsr + incl %ecx /* Move index to MTRR_PHYS_MASK */ + + /* Temporarily transfer MSR index to EDX so that CL can be used */ + movl %ecx, %edx + + /* Determine next size to cache */ + bsr %ebx, %ecx + movl $(1), %ebx + shl %cl, %ebx /* Can only use CL here */ + + /* Restore ECX */ + movl %edx, %ecx + + /* Update saved base address */ + addl %ebx, %eax + movd %eax, %xmm0 + + /* Update saved remaining size */ + movd %xmm1, %eax + subl %ebx, %eax + movd %eax, %xmm1 + + /* Program MTRR mask */ movl MTRR_HIGH_MASK, %edx + xorl %eax, %eax + subl %ebx, %eax /* %eax = 4GIB - size to cache */ + orl $(MTRR_PHYS_MASK_VALID), %eax + wrmsr + incl %ecx /* Move index to next MTRR_PHYS_BASE */ + +cond_allocate_var_mtrrs: + + /* Check if we still need to cache something */ + movd %xmm1, %ebx + andl %ebx, %ebx + + jnz body_allocate_var_mtrrs + + /* + * Now that the variable MTRRs have been set up, enable them. + */ + movl $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + orl $(MTRR_DEF_TYPE_EN), %eax wrmsr /* Enable cache - GPF# if not done */ From ffbb4b2b11f2bb875fbaca0137615b592ba0cd9c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 15 Oct 2020 23:25:58 +0200 Subject: [PATCH 074/354] intel/txt: Add `txt_get_chipset_dpr` function Due to platform-specific constraints, it is not possible to enable DPR by programming the MCH's DPR register in ramstage. Instead, assume it has been programmed earlier and check that its value is valid. If it is, then simply configure DPR in TXT public base with the same parameters. Note that some bits only exist on MCH DPR, and thus need to be cleared. Implement this function on most client platforms. For Skylake and newer, place it in common System Agent code. Also implement it for Haswell, for which the rest of Intel TXT support will be added in subsequent commits. Do not error out if DPR is larger than expected. On some platforms, such as Haswell, MRC decides the size of DPR, and cannot be changed easily. Reimplementing MRC is easier than working around its limitations anyway. Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/memmap.c | 10 +++-- src/security/intel/txt/ramstage.c | 41 +++++++++++++++---- src/security/intel/txt/txt_platform.h | 12 ++++++ .../block/systemagent/systemagent_early.c | 7 ++++ 4 files changed, 60 insertions(+), 10 deletions(-) create mode 100644 src/security/intel/txt/txt_platform.h diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index ac36e25999..02d120b119 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "haswell.h" @@ -23,6 +24,11 @@ static size_t northbridge_get_tseg_size(void) return CONFIG_SMM_TSEG_SIZE; } +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; +} + /* * Return the topmost memory address below 4 GiB available for general * use, from software's view of memory. Do not confuse this with TOLUD, @@ -39,9 +45,7 @@ static uintptr_t top_of_low_usable_memory(void) */ uintptr_t tolum = northbridge_get_tseg_base(); - const union dpr_register dpr = { - .raw = pci_read_config32(HOST_BRIDGE, DPR), - }; + const union dpr_register dpr = txt_get_chipset_dpr(); /* Subtract DMA Protected Range size if enabled */ if (dpr.epm) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 263bc9daa6..f532a2fbd8 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -13,6 +13,7 @@ #include #include "txt.h" +#include "txt_platform.h" #include "txt_register.h" #include "txt_getsec.h" @@ -233,16 +234,42 @@ static void lockdown_intel_txt(void *unused) printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); if (dpr_capable) { - /* Protect 3 MiB below TSEG and lock register */ - union dpr_register dpr = { - .lock = 1, - .size = 3, - .top = tseg_base / MiB, - }; - write64((void *)TXT_DPR, dpr.raw); + /* Verify the DPR settings on the MCH and mirror them to TXT public space */ + union dpr_register dpr = txt_get_chipset_dpr(); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n", + (dpr.top - dpr.size) * MiB, dpr.size); // DPR TODO: implement SA_ENABLE_DPR in the intelblocks + if (!dpr.lock) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n"); + return; + } + + if (!dpr.epm || !dpr.prs) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n"); + return; + } + + if (dpr.size < 3) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); + return; + } + + if (dpr.top * MiB != tseg_base) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n"); + return; + } + + /* Clear reserved bits */ + dpr.prs = 0; + dpr.epm = 0; + + write64((void *)TXT_DPR, dpr.raw); + printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", read32((void *)TXT_DPR)); } diff --git a/src/security/intel/txt/txt_platform.h b/src/security/intel/txt/txt_platform.h new file mode 100644 index 0000000000..8881cab331 --- /dev/null +++ b/src/security/intel/txt/txt_platform.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SECURITY_INTEL_TXT_PLATFORM_H__ +#define __SECURITY_INTEL_TXT_PLATFORM_H__ + +#include +#include "txt_register.h" + +/* Prototypes to be defined in chipset code */ +union dpr_register txt_get_chipset_dpr(void); + +#endif /* __SECURITY_INTEL_TXT_PLATFORM_H__ */ diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index ffb6404aa2..53d6077e5f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -145,3 +147,8 @@ size_t sa_get_tseg_size(void) { return sa_get_gsm_base() - sa_get_tseg_base(); } + +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(SA_DEV_ROOT, DPR) }; +} From 138c1b864bf9745f084e2b7035204aaa3b5b983c Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 12 Oct 2020 01:29:12 +0200 Subject: [PATCH 075/354] superio/nuvoton: Only set bit 7 of global CR 0x2a for COM A Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Fixes: f95daa510d ("superio/nuvoton: Add back Nuvoton NCT6776 support") Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46286 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/superio/nuvoton/common/early_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index cc21f40d2a..ed5fdbab1f 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -55,7 +55,7 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x40); + pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0); if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A)) /* Route COM A to GPIO8 pin group */ From 62a5ca484367a8016371ab20971779643b519153 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 17 Oct 2020 10:34:14 +0200 Subject: [PATCH 076/354] vc/amd/Kconfig: Add missing dot in AMD domain www.amd.com Fixes: b266c6b5 ("AMD Steppe Eagle: Add binary PI vendorcode files") Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46517 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/vendorcode/amd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index e080170bf5..c7f48ac340 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -20,7 +20,7 @@ config CPU_AMD_AGESA_BINARY_PI Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group - (http://www.amdcom/embedded). + (http://www.amd.com/embedded). config CPU_AMD_AGESA_OPENSOURCE bool "open-source AGESA" From d354c08f9c320714c68b699d2bcb9ecf51b8e673 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 17 Oct 2020 13:10:32 +0200 Subject: [PATCH 077/354] AGESA mb: Replace tab with space in macro definition for consistency With a tabulator length of eight spaces, the alignment is the same, but the other macro definitions are using a space, so do the same for consistency, better alignment in diff views. git grep -l -P 'define\tBLD' | xargs sed -i 's,define\tBLD,define BLD,g' Change-Id: Ib71057c84dc897028cb0ceac29952e67bc541d2e Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46518 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/amd/olivehill/buildOpts.c | 2 +- src/mainboard/amd/parmer/buildOpts.c | 2 +- src/mainboard/amd/thatcher/buildOpts.c | 2 +- src/mainboard/asrock/imb-a180/buildOpts.c | 2 +- src/mainboard/asus/a88xm-e/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/bap/ode_e20XX/buildOpts.c | 2 +- src/mainboard/biostar/a68n_5200/buildOpts.c | 2 +- src/mainboard/biostar/am1ml/buildOpts.c | 2 +- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 2 +- src/mainboard/lenovo/g505s/buildOpts.c | 2 +- src/mainboard/msi/ms7721/buildOpts.c | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 0e09739f03..7a1f3590de 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 5ab39a13b2..030634605d 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 433a9f428e..72390c0ae2 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -15,7 +15,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c index 76fafca604..25e7d3aed2 100644 --- a/src/mainboard/asus/a88xm-e/buildOpts.c +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -26,7 +26,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 6b57711507..8600c27df9 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/a68n_5200/buildOpts.c b/src/mainboard/biostar/a68n_5200/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/biostar/a68n_5200/buildOpts.c +++ b/src/mainboard/biostar/a68n_5200/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 461561d2e0..808bacec7c 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -11,7 +11,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE //#define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index d7558f0091..f5c21819b4 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -11,7 +11,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE /* Build configuration values here. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 3aad89c15e..a3553c0dc7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here. */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index c0a87ddb21..19add3ac9b 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -29,7 +29,7 @@ //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 5740382985..3a0ac1c3eb 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -27,7 +27,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE /* Build configuration values here */ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE From 30935b60389a8cf264226b3885f37dda8d98fe2b Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 6 Oct 2020 08:53:57 +0200 Subject: [PATCH 078/354] vendorcode/amd: Fix typo in *is defined* in comments The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. $ git grep -l "is define at" src/vendorcode/amd/ | xargs sed -i 's/is define at/is defined at/' Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46065 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../f15tn/Proc/Fch/Common/FchCommonCfg.h | 6 +-- .../f16kb/Proc/Fch/Common/FchCommonCfg.h | 6 +-- src/vendorcode/amd/cimx/sb800/SBTYPE.h | 44 +++++++++---------- src/vendorcode/amd/cimx/sb900/SbType.h | 44 +++++++++---------- .../00630F01/Proc/Fch/Common/FchCommonCfg.h | 6 +-- .../00660F01/Proc/Fch/Common/FchCommonCfg.h | 6 +-- .../00670F00/Proc/Fch/Common/FchCommonCfg.h | 6 +-- .../00730F01/Proc/Fch/Common/FchCommonCfg.h | 6 +-- 8 files changed, 62 insertions(+), 62 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h index be373c7794..bc755f04d3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h @@ -140,19 +140,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h index 9009f6bdb6..b31866581e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h @@ -145,19 +145,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index b897950033..2fa79238c1 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -538,25 +538,25 @@ typedef struct _SATAST { /** _USBST Controller structure * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -578,25 +578,25 @@ typedef struct _USBST { typedef struct _AZALIAPIN { unsigned char AzaliaSdin0:2; /**< AzaliaSdin0 * @par - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin1:2; /**< AzaliaSdin1 * @par - * SDIN0 is define at BIT2 & BIT3 + * SDIN0 is defined at BIT2 & BIT3 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin2:2; /**< AzaliaSdin2 * @par - * SDIN0 is define at BIT4 & BIT5 + * SDIN0 is defined at BIT4 & BIT5 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin3:2; /**< AzaliaSdin3 * @par - * SDIN0 is define at BIT6 & BIT7 + * SDIN0 is defined at BIT6 & BIT7 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ @@ -718,25 +718,25 @@ typedef struct _AMDSBCFG { /** USBDeviceConfig - USB Controller Configuration * - * - Usb Ohci1 Contoller is define at BIT0 + * - Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * - Usb Ehci1 Contoller is define at BIT1 + * - Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * - Usb Ohci2 Contoller is define at BIT2 + * - Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * - Usb Ehci2 Contoller is define at BIT3 + * - Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * - Usb Ohci3 Contoller is define at BIT4 + * - Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * - Usb Ehci3 Contoller is define at BIT5 + * - Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * - Usb Ohci4 Contoller is define at BIT6 + * - Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -816,16 +816,16 @@ typedef struct _AMDSBCFG { { /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration * - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * - 00: GPIO PIN * - 01: Reserved * - 10: As a Azalia SDIN pin * - * SDIN1 is define at BIT2 & BIT3 + * SDIN1 is defined at BIT2 & BIT3 * * Config same as SDIN0 - * SDIN2 is define at BIT4 & BIT5 + * SDIN2 is defined at BIT4 & BIT5 * * Config same as SDIN0 - * SDIN3 is define at BIT6 & BIT7 + * SDIN3 is defined at BIT6 & BIT7 * * Config same as SDIN0 */ unsigned char AzaliaSdinPin; diff --git a/src/vendorcode/amd/cimx/sb900/SbType.h b/src/vendorcode/amd/cimx/sb900/SbType.h index 87f49bd22f..eeedbba5d8 100644 --- a/src/vendorcode/amd/cimx/sb900/SbType.h +++ b/src/vendorcode/amd/cimx/sb900/SbType.h @@ -613,25 +613,25 @@ typedef struct _SATAST { /** _USBST Controller structure * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -684,25 +684,25 @@ typedef struct _AZALIAPIN { unsigned char AzaliaSdinPin; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry unsigned char AzaliaSdin0; /**< AzaliaSdin0 * @par - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin1; /**< AzaliaSdin1 * @par - * SDIN0 is define at BIT2 & BIT3 + * SDIN0 is defined at BIT2 & BIT3 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin2; /**< AzaliaSdin2 * @par - * SDIN0 is define at BIT4 & BIT5 + * SDIN0 is defined at BIT4 & BIT5 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ unsigned char AzaliaSdin3; /**< AzaliaSdin3 * @par - * SDIN0 is define at BIT6 & BIT7 + * SDIN0 is defined at BIT6 & BIT7 * @li 00 - GPIO PIN * @li 10 - As a Azalia SDIN pin */ @@ -927,25 +927,25 @@ typedef struct _AMDSBCFG { /** USBDeviceConfig - USB Controller Configuration * - * Usb Ohci1 Contoller is define at BIT0 + * Usb Ohci1 Contoller is defined at BIT0 * - 0:disable 1:enable * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is define at BIT1 + * Usb Ehci1 Contoller is defined at BIT1 * - 0:disable 1:enable * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is define at BIT2 + * Usb Ohci2 Contoller is defined at BIT2 * - 0:disable 1:enable * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is define at BIT3 + * Usb Ehci2 Contoller is defined at BIT3 * - 0:disable 1:enable * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is define at BIT4 + * Usb Ohci3 Contoller is defined at BIT4 * - 0:disable 1:enable * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is define at BIT5 + * Usb Ehci3 Contoller is defined at BIT5 * - 0:disable 1:enable * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is define at BIT6 + * Usb Ohci4 Contoller is defined at BIT6 * - 0:disable 1:enable * (Bus 0 Dev 20 Func5) * */ @@ -1021,16 +1021,16 @@ typedef struct _AMDSBCFG { { /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration 00-51 * - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * - 00: GPIO PIN * - 01: Reserved * - 10: As a Azalia SDIN pin * - * SDIN1 is define at BIT2 & BIT3 + * SDIN1 is defined at BIT2 & BIT3 * * Config same as SDIN0 - * SDIN2 is define at BIT4 & BIT5 + * SDIN2 is defined at BIT4 & BIT5 * * Config same as SDIN0 - * SDIN3 is define at BIT6 & BIT7 + * SDIN3 is defined at BIT6 & BIT7 * * Config same as SDIN0 */ unsigned char AzaliaSdinPin; diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h index 39a11ba7e6..b10eca7947 100644 --- a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h @@ -148,19 +148,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h index 35a76d20fd..8c557bc30e 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -177,19 +177,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h index 21f73a3a66..6dcfb7e2fa 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h @@ -182,19 +182,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h index 72e6aeb857..f96dfdb535 100644 --- a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h @@ -152,19 +152,19 @@ typedef struct _AZALIA_PIN { UINT8 AzaliaSdin1; ///< AzaliaSdin1 /// @par - /// SDIN1 is define at BIT2 & BIT3 + /// SDIN1 is defined at BIT2 & BIT3 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin2; ///< AzaliaSdin2 /// @par - /// SDIN2 is define at BIT4 & BIT5 + /// SDIN2 is defined at BIT4 & BIT5 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin UINT8 AzaliaSdin3; ///< AzaliaSdin3 /// @par - /// SDIN3 is define at BIT6 & BIT7 + /// SDIN3 is defined at BIT6 & BIT7 /// @li 00 - GPIO PIN /// @li 10 - As a Azalia SDIN pin } AZALIA_PIN; From 227225b4ac46e085d72d51e698aecd73159e1f18 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Tue, 6 Oct 2020 09:01:30 +0200 Subject: [PATCH 079/354] mb: AMD CIMx boards: Fix typo in *is defined* in comments The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/' Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/amd/inagua/platform_cfg.h | 22 +++++++++---------- src/mainboard/amd/persimmon/platform_cfg.h | 22 +++++++++---------- .../amd/south_station/platform_cfg.h | 22 +++++++++---------- .../amd/union_station/platform_cfg.h | 22 +++++++++---------- src/mainboard/asrock/e350m1/platform_cfg.h | 22 +++++++++---------- src/mainboard/elmex/pcm205400/platform_cfg.h | 22 +++++++++---------- .../gizmosphere/gizmo/platform_cfg.h | 22 +++++++++---------- .../jetway/nf81-t56n-lf/platform_cfg.h | 22 +++++++++---------- .../lippert/frontrunner-af/platform_cfg.h | 22 +++++++++---------- src/mainboard/pcengines/apu1/platform_cfg.h | 22 +++++++++---------- 10 files changed, 110 insertions(+), 110 deletions(-) diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 38447ac9b7..85a60e251b 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index d472ad036b..32c22bcfa1 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 38447ac9b7..85a60e251b 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 38447ac9b7..85a60e251b 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6d3ea82233..6994575985 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -36,13 +36,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -138,13 +138,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h index b621f60b81..7926249ff0 100644 --- a/src/mainboard/elmex/pcm205400/platform_cfg.h +++ b/src/mainboard/elmex/pcm205400/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 2ea529ffcc..af7da08234 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -40,13 +40,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -143,13 +143,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index bacb7b11aa..9c8d0f6e47 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -140,13 +140,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 9f51c40462..ba6f0bb0cf 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -37,13 +37,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define USB_CONFIG 0x3F @@ -148,13 +148,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ #if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF) #define AZALIA_SDIN_PIN 0x02 diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index ef6f5baeaa..44172f67d6 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -39,13 +39,13 @@ * @brief bit[0-6] used to control USB * 0 - Disable * 1 - Enable - * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 - * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 - * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 - * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 - * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 - * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 - * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 + * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0 + * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1 + * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2 + * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3 + * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4 + * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5 + * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6 */ #define USB_CONFIG 0x7F @@ -141,13 +141,13 @@ /** * @def AZALIA_SDIN_PIN * @brief - * SDIN0 is define at BIT0 & BIT1 + * SDIN0 is defined at BIT0 & BIT1 * 00 - GPIO PIN * 01 - Reserved * 10 - As a Azalia SDIN pin - * SDIN1 is define at BIT2 & BIT3 - * SDIN2 is define at BIT4 & BIT5 - * SDIN3 is define at BIT6 & BIT7 + * SDIN1 is defined at BIT2 & BIT3 + * SDIN2 is defined at BIT4 & BIT5 + * SDIN3 is defined at BIT6 & BIT7 */ //#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A From e1194ae6b6b9b02371d1e9e9c3b00aa658f30213 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 28 Sep 2020 23:18:21 +0200 Subject: [PATCH 080/354] superio: Add newline to log message about disabled mouse controller A newline is missing at the end of the informational message. PNP: 002e.5 init nct5572d_init: Disable mouse controller.PNP: 002e.5 init finished in 0 msecs PNP: 002e.307 init Change-Id: Ic73ed97be0993637be1e97040784d5a8e70a22ae Fixes: 6ff1078990 ("superio: Log if mouse controller is disabled") Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/45805 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/superio/nuvoton/nct5572d/superio.c | 2 +- src/superio/winbond/w83667hg-a/superio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 351181c0f5..c0a71186af 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -36,7 +36,7 @@ static void nct5572d_init(struct device *dev) mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index bea21016f5..828fe9af04 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -36,7 +36,7 @@ static void w83667hg_a_init(struct device *dev) mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); if (!mouse_detected) { - printk(BIOS_INFO, "%s: Disable mouse controller.", + printk(BIOS_INFO, "%s: Disable mouse controller.\n", __func__); pnp_enter_conf_mode(dev); byte = pnp_read_config(dev, 0x2a); From d2ec82d137448dc9b851d2d60b715fabdc6e78ec Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 13 Oct 2020 17:27:19 +0200 Subject: [PATCH 081/354] libpayload/libpci: Clean up pci_alloc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up pci_alloc() and return pointer to allocated memory directly. Change-Id: Ib2ee8dbfaabbf7a824b4fd75ad7c779393af2900 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46345 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- payloads/libpayload/libpci/libpci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 27347e3bf8..3e3513ccb0 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -72,8 +72,7 @@ int pci_write_long(struct pci_dev *dev, int pos, u32 data) struct pci_access *pci_alloc(void) { - struct pci_access *pacc = malloc(sizeof(*pacc)); - return pacc; + return malloc(sizeof(struct pci_access)); } void pci_init(struct pci_access *pacc) From 4c9622a7d033e92a214a8534012ff40e2f4bb6e4 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 13 Oct 2020 18:00:24 +0200 Subject: [PATCH 082/354] libpayload/libpci: Introduce device class attribute in pci_dev The device class is read at different places and it is read from the hardware directly. Therefore, and in preparation to CB:46416, introduce the device class attribute in the pci_dev struct. With this, there is only one interaction with the hardware and it's also more user friendly. Change-Id: I5d56be96f3f0da471246f031ea619e3df8e54cfb Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46347 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- payloads/libpayload/include/pci/pci.h | 1 + payloads/libpayload/libpci/libpci.c | 1 + 2 files changed, 2 insertions(+) diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 8c11d6b33f..7ec9491d95 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -74,6 +74,7 @@ struct pci_dev { u16 domain; u8 bus, dev, func; u16 vendor_id, device_id; + u16 device_class; struct pci_dev *next; }; diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 3e3513ccb0..200ae18435 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -178,6 +178,7 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, uint8_t bus) dev->func = func; dev->vendor_id = val & 0xffff; dev->device_id = (uint16_t)(val >> 16); + dev->device_class = pci_read_config16(PCI_DEV(bus, slot, func), PCI_CLASS_DEVICE); dev->next = 0; hdr = pci_read_config8(PCI_DEV(bus, slot, func), From cfb0b6a8ff5bcd7d36f7e83a5c0f72c6a963f0da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 16 Oct 2020 22:16:12 +0200 Subject: [PATCH 083/354] cpu/intel,soc/intel: drop Kconfig for hyperthreading MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the Kconfig for hyperthreading to be always able to check at runtime if hyperthreading is supported. Having a Kconfig for this doesn't have any benefit. Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak --- src/cpu/intel/common/Kconfig | 3 --- src/cpu/intel/common/Makefile.inc | 2 +- src/cpu/intel/model_f2x/Kconfig | 1 - src/cpu/intel/model_f3x/Kconfig | 1 - src/soc/intel/alderlake/Kconfig | 1 - src/soc/intel/common/block/sgx/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/tigerlake/Kconfig | 1 - 8 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 0f2a65238c..064e67b6db 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,9 +22,6 @@ config SET_IA32_FC_LOCK_BIT config CPU_INTEL_COMMON_TIMEBASE bool -config CPU_INTEL_COMMON_HYPERTHREADING - bool - endif config CPU_INTEL_COMMON_SMM diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 161201244c..8b81a121d3 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,5 @@ ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c -ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 876be2dd22..afa93711b8 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 4d5e395d54..61923b8165 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_F3X select ARCH_ALL_STAGES_X86_32 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2d21a61193..b8a2a136f3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 48ba1fc411..92959ffe9c 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -1,7 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_SGX bool select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING default n help Intel Processor common SGX support diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index c6e3a229de..4abe29eebe 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 9433080eda..d1689dacb3 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_HYPERTHREADING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP From b9365ef377ff4fb7957dcb05e02c30f5817444f9 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Sun, 11 Oct 2020 15:00:36 -0600 Subject: [PATCH 084/354] soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb platform_fsp_silicon_init_params_cb is called by the fsp driver and calls mainboard_silicon_init_params which sets the mainboard PCH GPIOs. Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309 Reviewed-by: Jonathan Zhang Reviewed-by: Bryant Ou Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/chip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 11fe44b1b2..c5a8c1cb1c 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -488,9 +488,11 @@ static void xeonsp_cpx_pci_domain_set_resources(struct device *dev) DEV_FUNC_EXIT(dev); } +/* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { - /* not implemented yet */ + + mainboard_silicon_init_params(silupd); } #if CONFIG(HAVE_ACPI_TABLES) From d6ffbf0e43004d7458194d9641efd07569b800a7 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Tue, 6 Oct 2020 16:30:32 +0530 Subject: [PATCH 085/354] soc/intel/tigerlake: Reflow long lines Use the 96 character limit. Signed-off-by: Sridhar Siricilla Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/meminit.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0f88..7e830f051f 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -441,12 +441,10 @@ void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, { switch (board_cfg->mem_type) { case MEMTYPE_DDR4: - meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, - half_populated); + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, half_populated); break; case MEMTYPE_LPDDR4X: - meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, - half_populated); + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, half_populated); break; default: die("Unsupported memory type = %d!\n", board_cfg->mem_type); From 965439be12f8808a47fad3611f6a75d3d2870004 Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 5 Oct 2020 18:32:03 +0800 Subject: [PATCH 086/354] mb/google/zork/var/vilboz: update dptc stapm time Update dptc setting: Stapm_time_constant 1400 BUG=b:170696020 BRANCH=zork TEST=emerge coreboot and check "Stapm_time_constant" Signed-off-by: John Su Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048 Tested-by: build bot (Jenkins) Reviewed-by: Chris Wang Reviewed-by: EricR Lai --- src/mainboard/google/zork/variants/vilboz/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index b75beafa34..a93beb5bd8 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -13,7 +13,7 @@ chip soc/amd/picasso register "slow_ppt_limit" = "6000" # mW register "fast_ppt_limit" = "9000" # mW register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "2500" # second + register "stapm_time_constant" = "1400" # second register "sustained_power_limit" = "4800" # mW # End : OPN Performance Configuration From 42aa2cb94ab0b7fefc8204fcf128f6953af00b9a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 9 Oct 2020 23:24:31 +0200 Subject: [PATCH 087/354] mb/purism/librem_skl: Clean up FSP-M RCOMP settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to use static functions to fill these settings in. Also, add missing include for and initialize `mem_cfg` in one line. Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46252 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/romstage.c | 29 ++++++++-------------- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 4982836c66..1c907716c4 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -3,37 +3,30 @@ #include #include #include +#include #include -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; + const u16 rcomp_resistors[3] = { 121, 81, 100 }; + + const u16 rcomp_targets[5] = { 100, 40, 20, 20, 26 }; + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50 }, }; - mem_cfg = &mupd->FspmConfig; + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); get_spd_smbus(&blk); dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; From f580d9ffef93243509e84d558e42a8722d0ad6e7 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Wed, 14 Oct 2020 16:25:11 +0800 Subject: [PATCH 088/354] mb/google/volteer/elemi: Add memory.c for DDR4 Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- .../volteer/variants/elemi/Makefile.inc | 3 ++ .../google/volteer/variants/elemi/memory.c | 31 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/elemi/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/elemi/memory.c diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc new file mode 100644 index 0000000000..9064208bff --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c new file mode 100644 index 0000000000..d3de4be711 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg elemi_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &elemi_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} From e68ef7d75ca82f08dabe5848e816800462a66806 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 7 Sep 2020 17:24:26 +0800 Subject: [PATCH 089/354] drivers/camera: Add config CHROMEOS_CAMERA Add cros_camera_info struct for camera information, and check_cros_camera_info() for checking the magic, CRC and version. BUG=b:144820097 TEST=emerge-kukui coreboot BRANCH=kukui Change-Id: I1215fec76643b0cf7e09433e1190e8bd387e6953 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46042 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/drivers/camera/Kconfig | 7 ++++++ src/drivers/camera/Makefile.inc | 1 + src/drivers/camera/cros_camera.c | 39 ++++++++++++++++++++++++++++++++ src/drivers/camera/cros_camera.h | 27 ++++++++++++++++++++++ 4 files changed, 74 insertions(+) create mode 100644 src/drivers/camera/Kconfig create mode 100644 src/drivers/camera/Makefile.inc create mode 100644 src/drivers/camera/cros_camera.c create mode 100644 src/drivers/camera/cros_camera.h diff --git a/src/drivers/camera/Kconfig b/src/drivers/camera/Kconfig new file mode 100644 index 0000000000..1c0c0a3634 --- /dev/null +++ b/src/drivers/camera/Kconfig @@ -0,0 +1,7 @@ +config CHROMEOS_CAMERA + bool + default n + help + Camera with identifiers following Chrome OS Camera Info. The info is + usually available on MIPI camera EEPROM for identifying correct + drivers and config. diff --git a/src/drivers/camera/Makefile.inc b/src/drivers/camera/Makefile.inc new file mode 100644 index 0000000000..1a6e609465 --- /dev/null +++ b/src/drivers/camera/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_CHROMEOS_CAMERA) += cros_camera.c diff --git a/src/drivers/camera/cros_camera.c b/src/drivers/camera/cros_camera.c new file mode 100644 index 0000000000..ff39678033 --- /dev/null +++ b/src/drivers/camera/cros_camera.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "cros_camera.h" + +int check_cros_camera_info(const struct cros_camera_info *info) +{ + if (memcmp(info->magic, CROS_CAMERA_INFO_MAGIC, sizeof(info->magic))) { + printk(BIOS_ERR, "Invalid magic in camera info\n"); + return -1; + } + + const uint8_t *ptr = (void *)(&info->crc16 + 1); + uint16_t crc16 = 0; + while (ptr < (uint8_t *)info + sizeof(struct cros_camera_info)) + crc16 = crc16_byte(crc16, *ptr++); + + if (info->crc16 != crc16) { + printk(BIOS_ERR, "Incorrect CRC16: expected %#06x, got %#06x\n", + crc16, info->crc16); + return -1; + } + + if (info->version != CROS_CAMERA_INFO_VERSION) { + printk(BIOS_ERR, "Unknown camera info version: %u\n", + info->version); + return -1; + } + if (info->size < CROS_CAMERA_INFO_SIZE_MIN) { + printk(BIOS_ERR, "Size of camera info is too small: %u\n", + info->size); + return -1; + } + + return 0; +} diff --git a/src/drivers/camera/cros_camera.h b/src/drivers/camera/cros_camera.h new file mode 100644 index 0000000000..f69e77d3e5 --- /dev/null +++ b/src/drivers/camera/cros_camera.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H +#define __VENDORCODE_GOOGLE_CHROMEOS_CAMERA_H + +#include + +#define CROS_CAMERA_INFO_MAGIC "CrOS" +#define CROS_CAMERA_INFO_VERSION 1 +#define CROS_CAMERA_INFO_SIZE_MIN 0x0a + +struct cros_camera_info { + uint8_t magic[4]; /* CROS_CAMERA_INFO_MAGIC */ + uint16_t crc16; + uint8_t version; + uint8_t size; + uint16_t data_format; + uint16_t module_pid; + uint8_t module_vid[2]; + uint8_t sensor_vid[2]; + uint16_t sensor_pid; +}; + +/* Returns 0 on success, non-zero on errors. */ +int check_cros_camera_info(const struct cros_camera_info *info); + +#endif From b22dc1daf43f935254787daf16fb72755e2a2526 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 24 Jun 2020 17:09:26 +0800 Subject: [PATCH 090/354] mb/google/kukui: Support SKU from camera EEPROM To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/Kconfig | 1 + src/mainboard/google/kukui/Makefile.inc | 1 - src/mainboard/google/kukui/boardid.c | 104 +++++++++++++++++++++++- 3 files changed, 103 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 4e308ef873..2237efa076 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_CAMERA select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 532712a6c1..7e065a3d8d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += sdram_params/ subdirs-y += panel_params/ -bootblock-y += boardid.c bootblock-y += bootblock.c bootblock-y += reset.c diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 548f36bc9d..47b0d9bcd7 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -3,8 +3,14 @@ #include #include #include -#include +#include +#include +#include #include +#include +#include +#include +#include /* For CBI un-provisioned/corrupted Flapjack board. */ #define FLAPJACK_UNDEF_SKU_ID 0 @@ -72,6 +78,97 @@ static uint32_t get_adc_index(unsigned int channel) return id; } +static uint8_t eeprom_random_read(uint8_t bus, uint8_t slave, uint16_t offset, + uint8_t *data, uint16_t len) +{ + struct i2c_msg seg[2]; + uint8_t address[2]; + + address[0] = offset >> 8; + address[1] = offset & 0xff; + + seg[0].flags = 0; + seg[0].slave = slave; + seg[0].buf = address; + seg[0].len = sizeof(address); + seg[1].flags = I2C_M_RD; + seg[1].slave = slave; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + +/* Regulator for world facing camera. */ +#define PMIC_LDO_VCAMIO_CON0 0x1cb0 + +#define CROS_CAMERA_INFO_OFFSET 0x1f80 +#define MT8183_FORMAT 0x8183 +#define KODAMA_PID 0x00c7 + +/* Returns the ID for world facing camera. */ +static uint8_t wfc_id(void) +{ + if (!CONFIG(BOARD_GOOGLE_KODAMA)) + return 0; + + int i, ret; + uint8_t bus = 2; + uint8_t dev_addr = 0x50; /* at24c32/64 device address */ + + struct cros_camera_info data = {0}; + + const uint16_t sensor_pids[] = { + [0] = 0x5965, /* OV5965 */ + [1] = 0x5035, /* GC5035 */ + }; + + mtk_i2c_bus_init(bus); + + /* Turn on camera sensor EEPROM */ + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x1); + udelay(270); + + ret = eeprom_random_read(bus, dev_addr, CROS_CAMERA_INFO_OFFSET, + (uint8_t *)&data, sizeof(data)); + pwrap_write(PMIC_LDO_VCAMIO_CON0, 0x0); + + if (ret) { + printk(BIOS_ERR, + "Failed to read from EEPROM; using default WFC id 0\n"); + return 0; + } + + if (check_cros_camera_info(&data)) { + printk(BIOS_ERR, + "Failed to check camera info; using default WFC id 0\n"); + return 0; + } + + if (data.data_format != MT8183_FORMAT) { + printk(BIOS_ERR, "Incompatible camera format: %#04x\n", + data.data_format); + return 0; + } + if (data.module_pid != KODAMA_PID) { + printk(BIOS_ERR, "Incompatible module pid: %#04x\n", + data.module_pid); + return 0; + } + + printk(BIOS_DEBUG, "Camera sensor pid: %#04x\n", data.sensor_pid); + + for (i = 0; i < ARRAY_SIZE(sensor_pids); i++) { + if (data.sensor_pid == sensor_pids[i]) { + printk(BIOS_INFO, "Detected WFC id: %d\n", i); + return i; + } + } + + printk(BIOS_WARNING, "Unknown WFC id; using default id 0\n"); + return 0; +} + /* board_id is provided by ec/google/chromeec/ec_boardid.c */ uint32_t sku_id(void) @@ -98,11 +195,14 @@ uint32_t sku_id(void) /* * The SKU (later used for device tree matching) is combined from: + * World facing camera (WFC) ID. * ADC2[4bit/H] = straps on LCD module (type of panel). * ADC4[4bit/L] = SKU ID from board straps. */ - cached_sku_id = (get_adc_index(LCM_ID_CHANNEL) << 4 | + cached_sku_id = (wfc_id() << 8 | + get_adc_index(LCM_ID_CHANNEL) << 4 | get_adc_index(SKU_ID_CHANNEL)); + return cached_sku_id; } From 2cc126be2c3018b09f893e3426c76ad68325c4e8 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Aug 2020 19:46:35 +0000 Subject: [PATCH 091/354] drivers/intel/usb4: Add driver for USB4 retimer device The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/drivers/retimer.md | 40 ++++++ Makefile.inc | 2 +- src/Kconfig | 1 + src/drivers/intel/usb4/retimer/Kconfig | 8 ++ src/drivers/intel/usb4/retimer/Makefile.inc | 1 + src/drivers/intel/usb4/retimer/chip.h | 13 ++ src/drivers/intel/usb4/retimer/retimer.c | 136 ++++++++++++++++++++ 7 files changed, 200 insertions(+), 1 deletion(-) create mode 100644 Documentation/drivers/retimer.md create mode 100644 src/drivers/intel/usb4/retimer/Kconfig create mode 100644 src/drivers/intel/usb4/retimer/Makefile.inc create mode 100644 src/drivers/intel/usb4/retimer/chip.h create mode 100644 src/drivers/intel/usb4/retimer/retimer.c diff --git a/Documentation/drivers/retimer.md b/Documentation/drivers/retimer.md new file mode 100644 index 0000000000..d83b50b26f --- /dev/null +++ b/Documentation/drivers/retimer.md @@ -0,0 +1,40 @@ +# USB4 Retimers + +# Introduction +As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in +newer revisions of the spec), it becomes more difficult to maintain signal +integrity for longer traces. Devices such as retimers and redrivers can be used +to help signals maintain their integrity over long distances. + +A redriver is a device that boosts the high-frequency content of a signal in +order to compensate for the attenuation typically caused by travelling through +various circuit components (PCB, connectors, CPU, etc.). Redrivers are not +protocol-aware, which makes them relatively simple. However, their effectiveness +is limited, and may not work at all in some scenarios. + +A retimer is a device that retransmits a fresh copy of the signal it receives, +by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since +this is a digital component, it may have firmware. + + +# Driver Usage + +Some operating systems may have the ability to update firmware on USB4 retimers, +and ultimately will need some way to power the device on and off so that its new +firmware can be loaded. This is achieved by providing a GPIO signal that can be +used for this purpose; its active state must be the one in which power is +applied to the retimer. This driver will generate the required ACPI AML code +which will toggle the GPIO in response to the kernel's request (through the +`_DSM` ACPI method). Simply put something like the following in your devicetree: + +``` +device pci 0.0 on + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A0)" + device generic 0 on end + end +end +``` + +replacing the GPIO with the appropriate pin and polarity. + diff --git a/Makefile.inc b/Makefile.inc index 882673b4c9..297f7b1a16 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -80,7 +80,7 @@ subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio -subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) +subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro diff --git a/src/Kconfig b/src/Kconfig index 9cc9d31e64..d265da7797 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -554,6 +554,7 @@ source "src/device/Kconfig" menu "Generic Drivers" source "src/drivers/*/Kconfig" source "src/drivers/*/*/Kconfig" +source "src/drivers/*/*/*/Kconfig" source "src/commonlib/storage/Kconfig" endmenu diff --git a/src/drivers/intel/usb4/retimer/Kconfig b/src/drivers/intel/usb4/retimer/Kconfig new file mode 100644 index 0000000000..eee8fe1bed --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_INTEL_USB4_RETIMER + bool + depends on HAVE_ACPI_TABLES + help + A retimer is a device that retransmits a fresh copy of the signal it + receives, by doing CDR and retransmitting the data (i.e., it is + protocol-aware). If your mainboard has a USB4 retimer (usually + located close to the USB4 ports), then select this driver. diff --git a/src/drivers/intel/usb4/retimer/Makefile.inc b/src/drivers/intel/usb4/retimer/Makefile.inc new file mode 100644 index 0000000000..bca23aa3bf --- /dev/null +++ b/src/drivers/intel/usb4/retimer/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_RETIMER) += retimer.c diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h new file mode 100644 index 0000000000..789d824a81 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __DRIVERS_INTEL_USB4_RETIMER_H__ +#define __DRIVERS_INTEL_USB4_RETIMER_H__ + +#include + +struct drivers_intel_usb4_retimer_config { + /* GPIO used to control power of retimer device. */ + struct acpi_gpio power_gpio; +}; + +#endif /* __DRIVERS_INTEL_USB4_RETIMER_H__ */ diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c new file mode 100644 index 0000000000..be9ec35230 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* Unique ID for the retimer _DSM. */ +#define INTEL_USB4_RETIMER_DSM_UUID "61788900-C470-42BB-80F0-23A313864593" + +/* + * Arg0: UUID + * Arg1: Revision ID (set to 1) + * Arg2: Function Index + * 0: Query command implemented + * 1: Query force power enable state + * 2: Set force power state + * Arg3: A package containing parameters for the function specified + * by the UUID, revision ID and function index. + */ + +static void usb4_retimer_cb_standard_query(void *arg) +{ + /* + * ToInteger (Arg1, Local2) + * If (Local2 == 1) { + * Return(Buffer() {0x07}) + * } + * Return (Buffer() {0x01}) + */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + + /* Revision 1 supports 2 Functions beyond the standard query */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0x07); + acpigen_pop_len(); /* If */ + + /* Other revisions support no additional functions */ + acpigen_write_return_singleton_buffer(0); +} + +static void usb4_retimer_cb_get_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Read power gpio into Local0 + * Store (\_SB.PCI0.GTXS (power_gpio), Local0) + * Return (Local0) + */ + acpigen_get_tx_gpio(power_gpio); + acpigen_write_return_op(LOCAL0_OP); +} + +static void usb4_retimer_cb_set_power_state(void *arg) +{ + struct acpi_gpio *power_gpio = arg; + + /* + * // Get argument for on/off from Arg3[0] + * Local0 = DeRefOf (Arg3[0]) + */ + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); + + /* + * If (Local0 == 0) { + * // Turn power off + * \_SB.PCI0.CTXS (power_gpio) + * } + */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + acpigen_disable_tx_gpio(power_gpio); + acpigen_pop_len(); /* If */ + + /* + * Else { + * // Turn power on + * \_SB.PCI0.STXS (power_gpio) + * } + */ + acpigen_write_else(); + acpigen_enable_tx_gpio(power_gpio); + acpigen_pop_len(); + + /* Return (Zero) */ + acpigen_write_return_integer(0); +} + +static void (*usb4_retimer_callbacks[3])(void *) = { + usb4_retimer_cb_standard_query, /* Function 0 */ + usb4_retimer_cb_get_power_state, /* Function 1 */ + usb4_retimer_cb_set_power_state, /* Function 2 */ +}; + +static void usb4_retimer_fill_ssdt(const struct device *dev) +{ + const struct drivers_intel_usb4_retimer_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + + if (!dev->enabled || !scope || !config) + return; + + if (!config->power_gpio.pin_count) { + printk(BIOS_ERR, "%s: Power GPIO required for %s\n", __func__, dev_path(dev)); + return; + } + + /* Write the _DSM that toggles power with provided GPIO. */ + acpigen_write_scope(scope); + acpigen_write_dsm(INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, + ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->power_gpio); + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static struct device_operations usb4_retimer_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = usb4_retimer_fill_ssdt, +}; + +static void usb4_retimer_enable(struct device *dev) +{ + dev->ops = &usb4_retimer_dev_ops; +} + +struct chip_operations drivers_intel_usb4_retimer_ops = { + CHIP_NAME("Intel USB4 Retimer") + .enable_dev = usb4_retimer_enable +}; From 5b6ec3e4dcd63baea3355dd1af075ae44b4cd091 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Aug 2020 19:50:09 +0000 Subject: [PATCH 092/354] mb/google/volteer: Enable USB4 retimer driver Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/google/volteer/Kconfig | 1 + src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index edc9c91034..69f58b5082 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 28d903f7a3..7486aef84c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -426,6 +426,10 @@ chip soc/intel/tigerlake device ref tbt_dma0 on probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 + chip drivers/intel/usb4/retimer + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + device generic 0 on end + end end device ref gna on end device ref north_xhci on end From 362ec8dee21950b1f5e7f209c22311d7bebfb435 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Fri, 2 Oct 2020 16:12:02 +1000 Subject: [PATCH 093/354] amd/picasso/verstage: replace rsa accel with modexp Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp. Instead of using hardware acceleration for whole RSA process, acclerating only calculation part(modexp) increases transparency without affecting boot time. BUG=b:169157796 BRANCH=zork TEST=build and flash, check time spent on RSA is not changed Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546 Signed-off-by: Kangheui Won Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- .../amd/picasso/psp_verstage/vboot_crypto.c | 57 ++++++++++--------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c index 0bb9066f9c..d9364d0ebe 100644 --- a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c @@ -8,6 +8,7 @@ #include "psp_verstage.h" #include #include +#include #include static struct SHA_GENERIC_DATA_T sha_op; @@ -103,48 +104,50 @@ vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size return VB2_SUCCESS; } -vb2_error_t vb2ex_hwcrypto_rsa_verify_digest(const struct vb2_public_key *key, - const uint8_t *sig, const uint8_t *digest) +vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key, + uint8_t *inout, + uint32_t *workbuf32, int exp) { - RSAPKCS_VERIFY_PARAMS RSAParams; + /* workbuf32 is guaranteed to be a length of + * 3 * key->arrsize * sizeof(uint32_t). + * Since PSP expects everything in LE and *inout is BE array, + * we'll use workbuf for temporary buffer for endian conversion. + */ + MOD_EXP_PARAMS mod_exp_param; + unsigned int key_bytes = key->arrsize * sizeof(uint32_t); + uint32_t *sig_swapped = workbuf32; + uint32_t *output_buffer = &workbuf32[key->arrsize]; + uint32_t *inout_32 = (uint32_t *)inout; uint32_t retval; - uint32_t exp = 65537; - uint32_t sig_size; - size_t digest_size; + uint32_t i; - /* PSP only supports 2K and 4K RSA */ + /* PSP only supports 2K and 4K moduli */ if (key->sig_alg != VB2_SIG_RSA2048 && key->sig_alg != VB2_SIG_RSA2048_EXP3 && key->sig_alg != VB2_SIG_RSA4096) { return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } - /* PSP only supports SHA256, SHA384 and SHA512*/ - if (key->hash_alg != VB2_HASH_SHA256 && - key->hash_alg != VB2_HASH_SHA384 && - key->hash_alg != VB2_HASH_SHA512) { - return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; - } + for (i = 0; i < key->arrsize; i++) + sig_swapped[i] = swab32(inout_32[key->arrsize - i - 1]); - if (key->sig_alg == VB2_SIG_RSA2048_EXP3) - exp = 3; - sig_size = vb2_rsa_sig_size(key->sig_alg); - digest_size = vb2_digest_size(key->hash_alg); + mod_exp_param.pExponent = (char *)&exp; + mod_exp_param.ExpSize = sizeof(exp); + mod_exp_param.pModulus = (char *)key->n; + mod_exp_param.ModulusSize = key_bytes; + mod_exp_param.pMessage = (char *)sig_swapped; + mod_exp_param.pOutput = (char *)output_buffer; - RSAParams.pHash = (char *)digest; - RSAParams.HashLen = digest_size; - RSAParams.pModulus = (char *)key->n; - RSAParams.ModulusSize = sig_size; - RSAParams.pExponent = (char *)&exp; - RSAParams.ExpSize = sizeof(exp); - RSAParams.pSig = (char *)sig; - - retval = svc_rsa_pkcs_verify(&RSAParams); + retval = svc_modexp(&mod_exp_param); if (retval) { printk(BIOS_ERR, "ERROR: HW crypto failed - errorcode: %#x\n", retval); - return VB2_ERROR_RSA_VERIFY_DIGEST; + return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } + /* vboot expects results in *inout with BE, so copy & convert. */ + for (i = 0; i < key->arrsize; i++) + inout_32[i] = swab32(output_buffer[key->arrsize - i - 1]); + return VB2_SUCCESS; } From 72cd6b0d01a8027f3b00d408c25db1ca6bb9d770 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 1 Oct 2020 16:35:58 +0530 Subject: [PATCH 094/354] vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 The headers added are generated as per FSP v2376. Previous FSP version was 2295. Changes Include: - add GpioOverride UPD in Fspm.h - add new header FirmwareVersionInfo.h Cq-Depend: TBD Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../fsp2_0/jasperlake/FirmwareVersionInfo.h | 72 +++++++++++++++++++ .../intel/fsp/fsp2_0/jasperlake/FspmUpd.h | 12 +++- 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h new file mode 100644 index 0000000000..c375feeef0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h @@ -0,0 +1,72 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index 8155e85ea7..fc167c5b14 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -2708,7 +2708,17 @@ typedef struct { /** Offset 0x067E - Reserved **/ - UINT8 Reserved38[18]; + UINT8 Reserved38; + +/** Offset 0x067F - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable;1: Level 1 +**/ + UINT8 GpioOverride; + +/** Offset 0x0680 - Reserved +**/ + UINT8 Reserved39[16]; } FSP_M_CONFIG; /** Fsp M UPD Configuration From a01138b7a4c5c4d6078d5995d81f5f3c31364db2 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Mon, 5 Oct 2020 10:20:29 +0200 Subject: [PATCH 095/354] lib/imd: move struct definitions to a new header file Make IMD private structures definitions accessible by other units. To test IMD API correctness there is a need to access its internal structure. It is only possible when private implementation is visible in testing scope. Signed-off-by: Jakub Czapiga Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46216 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- src/include/imd_private.h | 38 ++++++++++++++++++++++++++++++++++++++ src/lib/imd.c | 33 ++------------------------------- 2 files changed, 40 insertions(+), 31 deletions(-) create mode 100644 src/include/imd_private.h diff --git a/src/include/imd_private.h b/src/include/imd_private.h new file mode 100644 index 0000000000..43c3b7d50b --- /dev/null +++ b/src/include/imd_private.h @@ -0,0 +1,38 @@ +#ifndef _IMD_PRIVATE_H_ +#define _IMD_PRIVATE_H_ + +#include + +/* In-memory data structures. */ +struct imd_root_pointer { + uint32_t magic; + /* Relative to upper limit/offset. */ + int32_t root_offset; +} __packed; + +struct imd_entry { + uint32_t magic; + /* start is located relative to imd_root */ + int32_t start_offset; + uint32_t size; + uint32_t id; +} __packed; + +struct imd_root { + uint32_t max_entries; + uint32_t num_entries; + uint32_t flags; + uint32_t entry_align; + /* Used for fixing the size of an imd. Relative to the root. */ + int32_t max_offset; + struct imd_entry entries[0]; +} __packed; + +#define IMD_ROOT_PTR_MAGIC 0xc0389481 +#define IMD_ENTRY_MAGIC (~0xc0389481) +#define SMALL_REGION_ID CBMEM_ID_IMD_SMALL +#define LIMIT_ALIGN 4096 + +#define IMD_FLAG_LOCKED 1 + +#endif /* _IMD_PRIVATE_H */ diff --git a/src/lib/imd.c b/src/lib/imd.c index 02779651c9..ac19d76f52 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -7,40 +7,11 @@ #include #include #include +#include + /* For more details on implementation and usage please see the imd.h header. */ -static const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; -static const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; -static const uint32_t SMALL_REGION_ID = CBMEM_ID_IMD_SMALL; - -/* In-memory data structures. */ -struct imd_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __packed; - -struct imd_entry { - uint32_t magic; - /* start is located relative to imd_root */ - int32_t start_offset; - uint32_t size; - uint32_t id; -} __packed; - -struct imd_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - /* Used for fixing the size of an imd. Relative to the root. */ - int32_t max_offset; - struct imd_entry entries[0]; -} __packed; - -#define IMD_FLAG_LOCKED 1 - static void *relative_pointer(void *base, ssize_t offset) { intptr_t b = (intptr_t)base; From eac283fb0c57398611f73dd9bdee7e0c598d2821 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 24 Sep 2020 20:07:15 +0200 Subject: [PATCH 096/354] soc/amd/common/acpi: Convert to ASL 2.0 syntax Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45700 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/amd/common/acpi/gpio_bank_lib.asl | 18 +++++++++--------- src/soc/amd/common/acpi/lpc.asl | 8 ++++---- src/soc/amd/common/acpi/thermal_zone.asl | 22 +++++++++++----------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f73340cc4d..9686ddc1c9 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -6,14 +6,14 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) + Return ((Arg0 * 4) + ACPIMMIO_GPIO0_BASE) } /* Read pin control dword */ Method (GPRD, 0x1, Serialized) { /* Arg0 - GPIO pin control MMIO address */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (GPDW, SystemMemory, Local0, 4) Field (GPDW, AnyAcc, NoLock, Preserve) { TEMP, 32 @@ -26,12 +26,12 @@ Method (GPWR, 0x2, Serialized) { /* Arg0 - GPIO pin control MMIO address */ /* Arg1 - Value for control register */ - Store (Arg0, Local0) + Local0 = Arg0 OperationRegion (GPDW, SystemMemory, Local0, 4) Field (GPDW, AnyAcc, NoLock, Preserve) { TEMP,32 } - Store (Arg1, TEMP) + TEMP = Arg1 } Method (GPGB, 0x2) @@ -41,8 +41,8 @@ Method (GPGB, 0x2) * Arg0 - GPIO pin control MMIO address * Arg1 - Desired byte (0 through 3) */ - Store (Multiply(Arg1, 8), Local2) - Return (And(ShiftRight(GPRD(Arg0), Local2), 0x000000FF)) + Local2 = Arg1 * 8 + Return ((GPRD (Arg0) >> Local2) & 0x000000FF) } Method (GPSB, 0x3) @@ -53,9 +53,9 @@ Method (GPSB, 0x3) * Arg1 - Desired byte (0 through 3) * Arg2 - Value */ - Store (Multiply(Arg1, 8), Local2) - And(ShiftRight(GPRD(Arg0), Local2), 0xFFFFFF00, Local3) - ShiftLeft (Or(And(Arg2, 0x000000FF),Local3), Local2, Local4) + Local2 = Arg1 * 8 + Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 + Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 GPWR (Arg0, Local4) } diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index e4b0689bd2..d2224e8f13 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -41,10 +41,10 @@ Device(LPCB) { { CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address CreateDwordField(^CRS,^BAR1._BAS,ESPB) // Field to hold eSPI base address - And(BAR, 0xffffff00, Local0) - Store(Local0, SPIB) // SPI base address mapped - Add(Local0, 0x10000, Local1) - Store(Local1, ESPB) // eSPI base address mapped + Local0 = BAR & 0xffffff00 + SPIB = Local0 // SPI base address mapped + Local1 = Local0 + 0x10000 + ESPB = Local1 // eSPI base address mapped Return(CRS) } } diff --git a/src/soc/amd/common/acpi/thermal_zone.asl b/src/soc/amd/common/acpi/thermal_zone.asl index b33ba97489..c80f3bf95d 100644 --- a/src/soc/amd/common/acpi/thermal_zone.asl +++ b/src/soc/amd/common/acpi/thermal_zone.asl @@ -48,16 +48,16 @@ ThermalZone (TZ00) { Name (_STR, Unicode ("AMD CPU Core Thermal Sensor")) Method (_STA) { - If (LEqual (HTCE, One)) { + If (HTCE == 1) { Return (0x0F) } - Return (Zero) + Return (0) } Method (_TMP) { /* Current temp in tenths degree Kelvin. */ - Multiply (TNOW, 10, Local0) - ShiftRight (Local0, 3, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + Local0 = TNOW * 10 + Local0 >>= 3 + Return (Local0 + K10TEMP_KELVIN_OFFSET) } /* @@ -65,17 +65,17 @@ ThermalZone (TZ00) { * P-State and power consumption in order to cool down. */ Method (_PSV) { /* Passive temp in tenths degree Kelvin. */ - Multiply (TLMT, 10, Local0) - ShiftRight (Local0, 1, Local0) - Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) + Local0 = TLMT * 10 + Local0 >>= 1 + Local0 += K10TEMP_TLIMIT_OFFSET + Return (Local0 + K10TEMP_KELVIN_OFFSET) } Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ - Return (Add (_PSV, K10TEMP_HOT_OFFSET)) + Return (_PSV + K10TEMP_HOT_OFFSET) } Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ - Return (Add (_HOT, K10TEMP_HOT_OFFSET)) + Return (_HOT + K10TEMP_HOT_OFFSET) } } From cbc29a2160d93f077098a022de3f8b8971ed85a2 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 30 Sep 2020 17:04:15 -0600 Subject: [PATCH 097/354] drivers/i2c: Add chip driver for GPIO based I2C multiplexer Add identifiers in ACPI tables for GPIO based I2C multiplexer. The multiplexer device defines the GPIO resource used to select the adapter/bus lines. The multiplexer adapter device defines the address to select the adapter/client lines. These ACPI identifiers are consumed by the i2c-mux-gpio kernel driver: https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Here is the output SSDT: Scope (\_SB.PCI0.I2C3) { Device (MUX0) { Name (_HID, "PRP0001") // _HID: Hardware ID Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x02) { Package (0x02) { "compatible", "i2c-mux-gpio" }, Package (0x02) { "mux-gpios", Package (0x04) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero } } } }) } } Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/45911 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/i2c/gpiomux/Kconfig | 6 ++ src/drivers/i2c/gpiomux/Makefile.inc | 1 + src/drivers/i2c/gpiomux/mux/Makefile.inc | 1 + src/drivers/i2c/gpiomux/mux/chip.h | 17 +++++ src/drivers/i2c/gpiomux/mux/mux.c | 82 ++++++++++++++++++++++++ 5 files changed, 107 insertions(+) create mode 100644 src/drivers/i2c/gpiomux/Kconfig create mode 100644 src/drivers/i2c/gpiomux/Makefile.inc create mode 100644 src/drivers/i2c/gpiomux/mux/Makefile.inc create mode 100644 src/drivers/i2c/gpiomux/mux/chip.h create mode 100644 src/drivers/i2c/gpiomux/mux/mux.c diff --git a/src/drivers/i2c/gpiomux/Kconfig b/src/drivers/i2c/gpiomux/Kconfig new file mode 100644 index 0000000000..f09a641eb7 --- /dev/null +++ b/src/drivers/i2c/gpiomux/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_GPIO_MUX + bool + default n + depends on HAVE_ACPI_TABLES + help + When enabled, add identifiers in ACPI tables for GPIO based I2C multiplexer. diff --git a/src/drivers/i2c/gpiomux/Makefile.inc b/src/drivers/i2c/gpiomux/Makefile.inc new file mode 100644 index 0000000000..fec8d5b00f --- /dev/null +++ b/src/drivers/i2c/gpiomux/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux diff --git a/src/drivers/i2c/gpiomux/mux/Makefile.inc b/src/drivers/i2c/gpiomux/mux/Makefile.inc new file mode 100644 index 0000000000..e51f706eda --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux.c diff --git a/src/drivers/i2c/gpiomux/mux/chip.h b/src/drivers/i2c/gpiomux/mux/chip.h new file mode 100644 index 0000000000..9906b258db --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/chip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_MUX_CHIP_H__ +#define __I2C_GPIOMUX_MUX_CHIP_H__ + +#include +#include + +#define MAX_NUM_MUX_GPIOS 4 + +struct drivers_i2c_gpiomux_mux_config { + /* GPIOs used to select the mux lines */ + uint32_t mux_gpio_count; + struct acpi_gpio mux_gpio[MAX_NUM_MUX_GPIOS]; +}; + +#endif /* __I2C_GPIOMUX_MUX_CHIP_H__ */ diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c new file mode 100644 index 0000000000..66c8cc5cc3 --- /dev/null +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *i2c_gpiomux_mux_acpi_name(const struct device *dev) +{ + static char name[ACPI_NAME_BUFFER_SIZE]; + + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MUX%01.1X", dev->path.generic.id); + return name; +} + +static void i2c_gpiomux_mux_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + struct drivers_i2c_gpiomux_mux_config *config = config_of(dev); + struct acpi_dp *dsd = NULL; + const char *compat_string = "i2c-mux-gpio"; + struct acpi_gpio_res_params param[MAX_NUM_MUX_GPIOS]; + int i; + + if (!dev->enabled || !scope || !path) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + for (i = 0; i < config->mux_gpio_count; i++) { + acpi_device_write_gpio(&config->mux_gpio[i]); + param[i].ref = path; + param[i].index = i; + param[i].pin = 0; + param[i].active_low = config->mux_gpio[i].active_low; + } + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "compatible", compat_string); + acpi_dp_add_gpio_array(dsd, "mux-gpios", param, config->mux_gpio_count); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_mux_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_mux_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_mux_fill_ssdt, +}; + +static void i2c_gpiomux_mux_enable(struct device *dev) +{ + if (!dev) + return; + + dev->ops = &i2c_gpiomux_mux_ops; +} + +struct chip_operations drivers_i2c_gpiomux_mux_ops = { + CHIP_NAME("I2C GPIO MUX Device") + .enable_dev = i2c_gpiomux_mux_enable +}; From bf089d2a6286eae4e25b7cb51e92633ae39252d4 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 7 Oct 2020 12:42:44 -0600 Subject: [PATCH 098/354] drivers/i2c/gpiomux: Add chip driver for multiplexed I2C bus This chip driver adds ACPI identifiers for multiplexed I2C bus that are selected using GPIO. The multiplexed bus device defines the address to select the I2C lines. These ACPI identifiers are consumed by the i2c-mux-gpio kernel driver: https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html BUG=b:169444894 TEST=Build and boot to OS in waddledee. Ensure that the ACPI identifiers are added in appropriate context. Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA0) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, Zero) // _ADR: Address } } Scope (\_SB.PCI0.I2C3.MUX0) { Device (MXA1) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_ADR, One) // _ADR: Address } } Change-Id: If8b983bc8ce212ce05fe6b7f01a6d9092468e582 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/i2c/gpiomux/Makefile.inc | 1 + src/drivers/i2c/gpiomux/bus/Makefile.inc | 1 + src/drivers/i2c/gpiomux/bus/bus.c | 60 ++++++++++++++++++++++++ src/drivers/i2c/gpiomux/bus/chip.h | 9 ++++ 4 files changed, 71 insertions(+) create mode 100644 src/drivers/i2c/gpiomux/bus/Makefile.inc create mode 100644 src/drivers/i2c/gpiomux/bus/bus.c create mode 100644 src/drivers/i2c/gpiomux/bus/chip.h diff --git a/src/drivers/i2c/gpiomux/Makefile.inc b/src/drivers/i2c/gpiomux/Makefile.inc index fec8d5b00f..5c328cba40 100644 --- a/src/drivers/i2c/gpiomux/Makefile.inc +++ b/src/drivers/i2c/gpiomux/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += mux +subdirs-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus diff --git a/src/drivers/i2c/gpiomux/bus/Makefile.inc b/src/drivers/i2c/gpiomux/bus/Makefile.inc new file mode 100644 index 0000000000..1c462dc094 --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GPIO_MUX) += bus.c diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c new file mode 100644 index 0000000000..66aef8e8c0 --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *i2c_gpiomux_bus_acpi_name(const struct device *dev) +{ + static char name[ACPI_NAME_BUFFER_SIZE]; + + snprintf(name, ACPI_NAME_BUFFER_SIZE, "MXA%01.1X", dev->path.generic.id); + return name; +} + +static void i2c_gpiomux_bus_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *path = acpi_device_path(dev); + + if (!dev || !dev->enabled || !scope || !path) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_ADR(dev->path.generic.id); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", path, dev->chip_ops->name, dev_path(dev)); +} + +static struct device_operations i2c_gpiomux_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = i2c_gpiomux_bus_acpi_name, + .acpi_fill_ssdt = i2c_gpiomux_bus_fill_ssdt, +}; + +static void i2c_gpiomux_bus_enable(struct device *dev) +{ + if (!dev) + return; + + dev->ops = &i2c_gpiomux_bus_ops; +} + +struct chip_operations drivers_i2c_gpiomux_bus_ops = { + CHIP_NAME("I2C GPIO MUX Bus Device") + .enable_dev = i2c_gpiomux_bus_enable +}; diff --git a/src/drivers/i2c/gpiomux/bus/chip.h b/src/drivers/i2c/gpiomux/bus/chip.h new file mode 100644 index 0000000000..2baf334a6c --- /dev/null +++ b/src/drivers/i2c/gpiomux/bus/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __I2C_GPIOMUX_BUS_CHIP_H__ +#define __I2C_GPIOMUX_BUS_CHIP_H__ + +struct drivers_i2c_gpiomux_bus_config { +}; + +#endif /* __I2C_GPIOMUX_BUS_CHIP_H__ */ From 94ce8c3b3d1b7997dbad020eb955ea3b3038a5f2 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 1 Oct 2020 10:22:57 -0600 Subject: [PATCH 099/354] mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer The camera sensor component chosen for UFC and WFC have an address conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also configure the GPIO that is used as select line. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers are added for I2C devices multiplexed using I2C MUX under the appropriate scope. Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/Kconfig | 1 + .../dedede/variants/waddledee/Makefile.inc | 1 + .../google/dedede/variants/waddledee/gpio.c | 16 ++++++++++++++++ .../dedede/variants/waddledee/overridetree.cb | 14 ++++++++++++++ 4 files changed, 32 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/waddledee/gpio.c diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2892dd16f0..377702da45 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index eda535c992..93f34f81e0 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -2,4 +2,5 @@ romstage-y += memory.c +ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c new file mode 100644 index 0000000000..0905e8f217 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* E5 : AP_SUB_IO_2 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index 22a08a060e..b67b8702c6 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -119,6 +119,20 @@ chip soc/intel/jasperlake device i2c 0x5d on end end end # I2C 2 + device pci 15.3 on + chip drivers/i2c/gpiomux/mux + register "mux_gpio_count" = "1" + register "mux_gpio[0]" = "ACPI_GPIO_OUTPUT(GPP_E5)" + device generic 0 on + chip drivers/i2c/gpiomux/bus + device generic 0 on end # I2C Mux Bus 0 + end + chip drivers/i2c/gpiomux/bus + device generic 1 on end # I2C Mux Bus 1 + end + end # I2C MUX + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" From e5397bd1165c12d5c09c9504ed31bb5daea81a15 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Thu, 15 Oct 2020 21:15:19 +0000 Subject: [PATCH 100/354] Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency" This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51. Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible. TEST=Boot Dalboz BUG=b:159823235, b:169940175 BRANCH=zork Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/zork/variants/dalboz/overridetree.cb | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index e5608d9091..1ddb17bdf4 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -37,12 +37,6 @@ chip soc/amd/picasso .early_init = true, }" - register "emmc_config" = "{ - .timing = SD_EMMC_EMMC_HS400, - .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, - .init_khz_preset = 400, - }" - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit From b37d4b95d3821a4f83067f8db0c652456f33f10c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 17:32:10 +0200 Subject: [PATCH 101/354] soc/intel/common/acpi: correct indentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Test: built google/volteer with `abuild --timeless` - SHA1 hashes match Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/acpi/lpit.asl | 138 ++++++++++++++--------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl index 348ae5612c..6159685b53 100644 --- a/src/soc/intel/common/acpi/lpit.asl +++ b/src/soc/intel/common/acpi/lpit.asl @@ -24,80 +24,80 @@ Scope(\_SB) Method(_DSM, 4) { If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) - } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(1) - } - - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(1) - } - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + * Enum functions */ - If (CondRefOf (\_SB.PCI0.EGPM)) - { - \_SB.PCI0.EGPM () + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } } } - /* - * Function 6 - Low Power S0 Exit Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(0) - } - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (\_SB.PCI0.RGPM)) - { - \_SB.PCI0.RGPM () - } - } - } - - Return(Buffer(One) {0x00}) + Return(Buffer(One) {0x00}) } // Method(_DSM) } // Device (LPID) } // End Scope(\_SB) From 33f234e3561c8cc5b9426fdf88067f2c9ced1052 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 16 Oct 2020 10:09:35 -0700 Subject: [PATCH 102/354] soc/intel/cannonlake: Fix memory corruptions Coverity detects source memory is overrun. Fix this issue by using the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption. Found-by: Coverity CID 1429762 1429774 TEST=None Signed-off-by: John Zhao Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/fsp_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d66e890a9e..fe7641f27b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -355,14 +355,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + sizeof(config->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented, sizeof(config->PcieRpSlotImplemented)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + sizeof(config->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; From dc667980f8ab78296e77b53d4afd1ce8d21dd2a6 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Fri, 16 Oct 2020 18:07:13 +0000 Subject: [PATCH 103/354] soc/intel/skylake: Do not let FSP set the subsystem IDs The subsystem ID registers are read/write-once. Writes by coreboot will not take effect if FSP sets them. Note that FSP sets one device ID for the SA devices and another for PCH devices. coreboot will copy individual vendor and device IDs if subsystem is not provided. Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/soc/intel/skylake/chip.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 549f403384..89eaef5b56 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -320,16 +320,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) */ params->SpiFlashCfgLockDown = 0; } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } + /* FSP should let coreboot set subsystem IDs, which are read/write-once */ + params->DefaultSvid = 0; + params->PchSubSystemVendorId = 0; + params->DefaultSid = 0; + params->PchSubSystemId = 0; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; From d5faa90df50c820ed3b79d4a5e479767efd73287 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Oct 2020 10:55:07 -0700 Subject: [PATCH 104/354] security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.h As ongoing work for generalizing mrc_cache to be used by all platforms, we are pulling it out from fsp 2.0 and renaming it as mrc_cache_hash_tpm.h in security/vboot. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46508 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/memory_init.c | 2 +- src/security/vboot/mrc_cache_hash_tpm.c | 2 +- .../memory_init.h => security/vboot/mrc_cache_hash_tpm.h} | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) rename src/{drivers/intel/fsp2_0/include/fsp/memory_init.h => security/vboot/mrc_cache_hash_tpm.h} (78%) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1ef9324d40..14aec98d43 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -20,8 +20,8 @@ #include #include #include +#include #include -#include #include static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index bc500a29f5..24e7aafaa7 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/security/vboot/mrc_cache_hash_tpm.h similarity index 78% rename from src/drivers/intel/fsp2_0/include/fsp/memory_init.h rename to src/security/vboot/mrc_cache_hash_tpm.h index e100efbeaa..a1ecd8bfca 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h +++ b/src/security/vboot/mrc_cache_hash_tpm.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _FSP2_0_MEMORY_INIT_H_ -#define _FSP2_0_MEMORY_INIT_H_ +#ifndef _MRC_CACHE_HASH_TPM_H_ +#define _MRC_CACHE_HASH_TPM_H_ #include @@ -16,4 +16,4 @@ void mrc_cache_update_hash(const uint8_t *data, size_t size); */ int mrc_cache_verify_hash(const uint8_t *data, size_t size); -#endif /* _FSP2_0_MEMORY_INIT_H_ */ +#endif /* _MRC_CACHE_HASH_TPM_H_ */ From 5c80519466863ae7b8579f1edb90829f7f9ee03d Mon Sep 17 00:00:00 2001 From: Jes Klinke Date: Wed, 14 Oct 2020 13:24:32 -0700 Subject: [PATCH 105/354] volteer+vendorcode: Retrieve Cr50 version only via SPI No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- src/mainboard/google/volteer/mainboard.c | 3 +- .../google/chromeos/cse_board_reset.c | 35 ++++++++++--------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1fcd5eb5ac..03a78fd777 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -51,7 +51,8 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) return; } - if (cr50_is_long_interrupt_pulse_enabled()) { + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && + cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c index 65e09aeedb..0b213a66de 100644 --- a/src/vendorcode/google/chromeos/cse_board_reset.c +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -16,24 +16,27 @@ void cse_board_reset(void) int ret; struct cr50_firmware_version version; - /* Initialize TPM and get the cr50 firmware version. */ - ret = tlcl_lib_init(); - if (ret != VB2_SUCCESS) { - printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); - return; + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* Initialize TPM and get the cr50 firmware version. */ + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + cr50_get_firmware_version(&version); + + /* + * Cr50 firmware versions 0.[3|4].20 or newer support strap + * config 0xe where PLTRST from AP is connected to cr50's + * PLTRST# signal. So return immediately and trigger a global + * reset. + */ + if (version.epoch != 0 || version.major > 4 || + (version.major >= 3 && version.minor >= 20)) + return; } - cr50_get_firmware_version(&version); - - /* - * Cr50 firmware versions 0.[3|4].20 or newer support strap config 0xe where PLTRST from - * AP is connected to cr50's PLTRST# signal. So return immediately and trigger a - * global reset. - */ - if (version.epoch != 0 || version.major > 4 || - (version.major >= 3 && version.minor >= 20)) - return; - printk(BIOS_INFO, "Initiating request to EC to trigger cold reset\n"); /* * Clean the data cache and set the full reset bit, so that when EC toggles From e16971ac64dc36375e5d606cd51950f2807c5bdb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 27 May 2020 18:08:56 +0200 Subject: [PATCH 106/354] util/supermicro: Always include commonlib/bsd/compiler.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We rely on `compiler.h` for definitions like `__packed`. Without it, `smcbiosinfo.c` simply declared a global struct with that name, but nothing was packed. Found-by: reproducibility test Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41784 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons --- util/supermicro/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/supermicro/Makefile.inc b/util/supermicro/Makefile.inc index 1aa5bcb437..316cb48864 100644 --- a/util/supermicro/Makefile.inc +++ b/util/supermicro/Makefile.inc @@ -1,9 +1,11 @@ +TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + SMCBIOSINFOTOOL:= $(objutil)/supermicro/smcbiosinfo $(SMCBIOSINFOTOOL): $(dir)/smcbiosinfo/smcbiosinfo.c printf " HOSTCC Creating SMCBIOSINFO tool\n" mkdir -p $(objutil)/supermicro - $(HOSTCC) $< -o $@ + $(HOSTCC) $(TOOLCPPFLAGS) $< -o $@ ifeq ($(CONFIG_VENDOR_SUPERMICRO),y) ifneq ($(call strip_quotes, $(CONFIG_SUPERMICRO_BOARDID)),) From 9357ac38606a2b928692a1251b7c9f4aef289334 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 14:57:39 +0200 Subject: [PATCH 107/354] superio/nuvoton: Correct NCT6791D COM A mux toggle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like on the other two Nuvoton Super I/Os, so fold the conditionals together. Change-Id: I8cebe35587ae68cac93ed392342662678621efd6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46521 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner --- src/superio/nuvoton/common/early_serial.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index ed5fdbab1f..398678983a 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -53,14 +53,11 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) nuvoton_pnp_enter_conf_state(dev); if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || + CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A) || CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0); - if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A)) - /* Route COM A to GPIO8 pin group */ - pnp_write_config(dev, 0x2a, 0x00); - pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); From 00e58c35c62dbd6c2b20980d594b2b9d1153aa45 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 15:06:40 +0200 Subject: [PATCH 108/354] superio/nuvoton: Factor out equivalent Kconfig option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no need to have multiple Kconfig symbols which do the same thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use the new symbol. To preserve alphabetical order in mainboard Kconfig, place the new symbol above the Super I/O symbol (instead of below). Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h110m/Kconfig | 2 +- src/mainboard/asrock/h81m-hds/Kconfig | 2 +- src/mainboard/asus/p8h61-m_lx/Kconfig | 2 +- src/mainboard/intel/saddlebrook/Kconfig | 2 +- src/mainboard/supermicro/x10slm-f/Kconfig | 2 +- src/mainboard/supermicro/x9scl/Kconfig | 2 +- src/superio/nuvoton/common/Kconfig | 7 +++++++ src/superio/nuvoton/common/early_serial.c | 4 +--- src/superio/nuvoton/nct5539d/Kconfig | 5 ----- src/superio/nuvoton/nct6776/Kconfig | 5 ----- src/superio/nuvoton/nct6791d/Kconfig | 5 ----- 11 files changed, 14 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index a80b5954df..d923c30d3c 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -11,8 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 6406417ac0..af723a3e04 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -17,8 +17,8 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE hex diff --git a/src/mainboard/asus/p8h61-m_lx/Kconfig b/src/mainboard/asus/p8h61-m_lx/Kconfig index 069800ade8..a108c3bc0c 100644 --- a/src/mainboard/asus/p8h61-m_lx/Kconfig +++ b/src/mainboard/asus/p8h61-m_lx/Kconfig @@ -17,8 +17,8 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select USE_NATIVE_RAMINIT config MAINBOARD_DIR diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index f81dbee976..873f25727c 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -11,8 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 598fbbeb1a..5e09349d61 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -13,8 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE hex diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index 9968d34cb5..626172609d 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -9,8 +9,8 @@ config BOARD_SPECIFIC_OPTIONS select RAMINIT_ENABLE_ECC select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_COMMON_COM_A select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A select SUPERIO_NUVOTON_WPCM450 select MAINBOARD_USES_IFD_GBE_REGION select IPMI_KCS diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig index 413b6a6882..78523c1b7e 100644 --- a/src/superio/nuvoton/common/Kconfig +++ b/src/superio/nuvoton/common/Kconfig @@ -5,6 +5,13 @@ config SUPERIO_NUVOTON_COMMON_PRE_RAM bool +config SUPERIO_NUVOTON_COMMON_COM_A + bool + depends on SUPERIO_NUVOTON_COMMON_PRE_RAM + help + When enabled, the 'nuvoton_enable_serial()' function will unset + global CR 0x2a bit 7 to route COM A to the GPIO8 pin group. + # Generic Nuvoton HWM driver config SUPERIO_NUVOTON_COMMON_HWM bool diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 398678983a..f86e7a27d0 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -52,9 +52,7 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) nuvoton_pnp_enter_conf_state(dev); - if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) || - CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A) || - CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) + if (CONFIG(SUPERIO_NUVOTON_COMMON_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0); diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig index 440775f13e..dc48246668 100644 --- a/src/superio/nuvoton/nct5539d/Kconfig +++ b/src/superio/nuvoton/nct5539d/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT5539D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT5539D_COM_A - bool - depends on SUPERIO_NUVOTON_NCT5539D - default n diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig index caa89b37fb..9f5e0843f5 100644 --- a/src/superio/nuvoton/nct6776/Kconfig +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT6776 bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT6776_COM_A - bool - depends on SUPERIO_NUVOTON_NCT6776 - default n diff --git a/src/superio/nuvoton/nct6791d/Kconfig b/src/superio/nuvoton/nct6791d/Kconfig index b06ee31a0f..a5364916c9 100644 --- a/src/superio/nuvoton/nct6791d/Kconfig +++ b/src/superio/nuvoton/nct6791d/Kconfig @@ -3,8 +3,3 @@ config SUPERIO_NUVOTON_NCT6791D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM - -config SUPERIO_NUVOTON_NCT6791D_COM_A - bool - depends on SUPERIO_NUVOTON_NCT6791D - default n From 5c2d1906d928f9ff388779a0a21141daea5d19e3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 18:42:49 +0200 Subject: [PATCH 109/354] sb/intel/ibexpeak: Use ARRAY_SIZE macro Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46529 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/southbridge/intel/ibexpeak/lpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 55dcb02d9b..d4f1925c2a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -293,7 +293,7 @@ static void mobile5_pm_init(struct device *dev) /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 }; - for (i = 0; i < sizeof(rcba2010) / sizeof(rcba2010[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2010); i++) { RCBA32 (0x2010 + 4 * i) = rcba2010[i]; RCBA32 (0x2010 + 4 * i); @@ -331,7 +331,7 @@ static void mobile5_pm_init(struct device *dev) /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 }; - for (i = 0; i < sizeof(rcba2210) / sizeof(rcba2210[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { RCBA32 (0x2210 + 4 * i) = rcba2210[i]; RCBA32 (0x2210 + 4 * i); @@ -344,7 +344,7 @@ static void mobile5_pm_init(struct device *dev) /* 2320: */ 0xcccc0cfc, 0x0fbb0fff }; - for (i = 0; i < sizeof(rcba2300) / sizeof(rcba2300[0]); i++) + for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { RCBA32 (0x2300 + 4 * i) = rcba2300[i]; RCBA32 (0x2300 + 4 * i); From b9a5152cfab79ebdc539bc467a743c4198870747 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 24 Jun 2019 18:39:43 +0200 Subject: [PATCH 110/354] Documentation: Fix spelling of *assumptions* Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/arch/x86/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 11d8a4f77b..d22d31de1a 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -19,7 +19,7 @@ In order to add support for x86_64 the following assumptions were made: * x86 payloads are loaded below 4GiB in physical memory and are jumped to in *protected mode* -## Assuptions for all stages using the reference implementation +## Assumptions for all stages using the reference implementation * 0-4GiB are identity mapped using 2MiB-pages as WB * Memory above 4GiB isn't accessible * page tables reside in memory mapped ROM From 4eedd938fa2882f0847d60b29c89bb98f435a37d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 22 Sep 2020 17:20:23 +0200 Subject: [PATCH 111/354] util/abuild/abuild: Do not check out submodules This force-downloads the qc_blobs repository, whose license is then automatically accepted. This may also cause race conditions with git. Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45607 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/abuild/abuild | 2 -- 1 file changed, 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 7561495d7b..2ba2f72d1f 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -794,8 +794,6 @@ if [ "$cpus" != "1" ]; then echo | xargs -P ${cpus:-0} -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 fi -git submodule update --checkout --init - if [ "$USE_XARGS" = "0" ]; then test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus" export MAKEFLAGS="$MAKEFLAGS UPDATED_SUBMODULES=1" # no need to re-download From 4b6ff98e84832bbdaab002dc6d5c860ec3b37ad5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 5 Oct 2020 16:56:31 +0000 Subject: [PATCH 112/354] Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit e5269a8fd975fa0cba0655cd41f7f8cc99a1feb8. Reason for revert: BIOS spec says, it's recommended to always enable emulation (regardless of the OS version). Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/cpu.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0c24535816..3d97c56404 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -112,14 +112,8 @@ static void configure_dca_cap(void) */ static void enable_pm_timer_emulation(void) { - const struct soc_intel_cannonlake_config *config; msr_t msr; - config = config_of_soc(); - - /* Enable PM timer emulation only if ACPI PM timer is disabled */ - if (!config->PmTimerDisabled) - return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. From 4e8baf9202a3de5dafeb1e26f95ded999ed5c667 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 4 Oct 2020 14:34:41 +0200 Subject: [PATCH 113/354] soc/intel/*: drop useless XTAL shutdown qualification code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/finalize.c | 4 ---- src/soc/intel/cannonlake/finalize.c | 15 +++++---------- .../common/block/include/intelblocks/pmclib.h | 3 --- src/soc/intel/common/block/pmc/pmclib.c | 7 ------- src/soc/intel/elkhartlake/finalize.c | 4 ---- src/soc/intel/icelake/finalize.c | 4 ---- src/soc/intel/jasperlake/finalize.c | 4 ---- src/soc/intel/skylake/finalize.c | 4 ---- src/soc/intel/tigerlake/finalize.c | 4 ---- 9 files changed, 5 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 24dbbd6ab7..b18d72bb6e 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -64,10 +64,6 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 9eb9cbea8c..6ef43b97f8 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -73,16 +73,11 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - if (config->s0ix_enable) { - /* Disable XTAL shutdown qualification for low power idle. */ - pmc_ignore_xtal_shutdown(); - - if (config->cppmvric2_adsposcdis) { - /* Enable Audio DSP OSC qualification for S0ix */ - reg32 = read32(pmcbase + CPPMVRIC2); - reg32 &= ~ADSPOSCDIS; - write32(pmcbase + CPPMVRIC2, reg32); - } + if (config->s0ix_enable && config->cppmvric2_adsposcdis) { + /* Enable Audio DSP OSC qualification for S0ix */ + reg32 = read32(pmcbase + CPPMVRIC2); + reg32 &= ~ADSPOSCDIS; + write32(pmcbase + CPPMVRIC2, reg32); } pch_handle_sideband(config); diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fa063f293e..2acc275b2f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -232,7 +232,4 @@ uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, /* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ void pmc_disable_acpi_timer(void); -/* Disable XTAL shutdown qualification for low power idle. */ -void pmc_ignore_xtal_shutdown(void); - #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 8825bbe441..a5dff2d75b 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -708,11 +708,4 @@ void pmc_disable_acpi_timer(void) setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } - -void pmc_ignore_xtal_shutdown(void) -{ - uint8_t *pmcbase = pmc_mmio_regs(); - - setbits8(pmcbase + CPPMVRIC, XTALSDQDIS); -} #endif /* PMC_LOW_POWER_MODE_PROGRAM */ diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index bae8bcf5a8..a1cfd8be29 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -45,10 +45,6 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 363f579b0f..395bd395c4 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -70,10 +70,6 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 1badad3425..61b8e33527 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -63,10 +63,6 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index ff3218981a..9edc7a2e18 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -73,10 +73,6 @@ static void pch_finalize_script(struct device *dev) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 2cc9671c30..44e6806162 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -51,10 +51,6 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); - /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) - pmc_ignore_xtal_shutdown(); - pmc_clear_pmcon_sts(); } From 1d9b059c52e05d2af7b75f93ba74f16ecbfc0da4 Mon Sep 17 00:00:00 2001 From: James Chao Date: Tue, 13 Oct 2020 22:45:48 +0800 Subject: [PATCH 114/354] mb/google/octopus/variants/ampton: Add G2Touch touchscreen support BUG=b:170703029 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: James Chao Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- .../google/octopus/variants/ampton/overridetree.cb | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 10ff7d74f7..3d14bea71d 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -121,6 +121,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end end From 819d8726067462742280c062830e2b5bb8e9c7a2 Mon Sep 17 00:00:00 2001 From: Thomas Heijligen Date: Mon, 18 Mar 2019 11:32:34 +0100 Subject: [PATCH 115/354] mb/siemens/chili: Add new mainboard The Chili base board is a ruggedized laptop with additional industrial interfaces. So far, only booting and basic interfaces (USB, UART, Video) are working with the original model, the "base" variant. No further development is planned for this variant, as our primary target was another one that will be added in a follow-up. Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c Signed-off-by: Thomas Heijligen Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/siemens/chili/Kconfig | 59 ++++++++ src/mainboard/siemens/chili/Kconfig.name | 6 + src/mainboard/siemens/chili/Makefile.inc | 12 ++ src/mainboard/siemens/chili/board_info.txt | 5 + src/mainboard/siemens/chili/cmos.layout | 59 ++++++++ src/mainboard/siemens/chili/dsdt.asl | 22 +++ src/mainboard/siemens/chili/ec.c | 99 +++++++++++++ src/mainboard/siemens/chili/ec.h | 8 ++ src/mainboard/siemens/chili/mainboard.c | 20 +++ src/mainboard/siemens/chili/romstage.c | 42 ++++++ src/mainboard/siemens/chili/variant.h | 8 ++ .../siemens/chili/variants/base/Makefile.inc | 5 + .../chili/variants/base/board_info.txt | 1 + .../siemens/chili/variants/base/data.vbt | Bin 0 -> 6144 bytes .../siemens/chili/variants/base/devicetree.cb | 136 ++++++++++++++++++ .../chili/variants/base/gma-mainboard.ads | 19 +++ .../siemens/chili/variants/base/gpio.c | 129 +++++++++++++++++ 17 files changed, 630 insertions(+) create mode 100644 src/mainboard/siemens/chili/Kconfig create mode 100644 src/mainboard/siemens/chili/Kconfig.name create mode 100644 src/mainboard/siemens/chili/Makefile.inc create mode 100644 src/mainboard/siemens/chili/board_info.txt create mode 100644 src/mainboard/siemens/chili/cmos.layout create mode 100644 src/mainboard/siemens/chili/dsdt.asl create mode 100644 src/mainboard/siemens/chili/ec.c create mode 100644 src/mainboard/siemens/chili/ec.h create mode 100644 src/mainboard/siemens/chili/mainboard.c create mode 100644 src/mainboard/siemens/chili/romstage.c create mode 100644 src/mainboard/siemens/chili/variant.h create mode 100644 src/mainboard/siemens/chili/variants/base/Makefile.inc create mode 100644 src/mainboard/siemens/chili/variants/base/board_info.txt create mode 100644 src/mainboard/siemens/chili/variants/base/data.vbt create mode 100644 src/mainboard/siemens/chili/variants/base/devicetree.cb create mode 100644 src/mainboard/siemens/chili/variants/base/gma-mainboard.ads create mode 100644 src/mainboard/siemens/chili/variants/base/gpio.c diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig new file mode 100644 index 0000000000..8c919b5631 --- /dev/null +++ b/src/mainboard/siemens/chili/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SIEMENS_CHILI_BASE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + +config MAINBOARD_DIR + string + default "siemens/chili" + +config MAINBOARD_FAMILY + string + default "Chili" + +config MAINBOARD_PART_NUMBER + string + default "Chili base board" + +config VARIANT_DIR + string + default "base" if BOARD_SIEMENS_CHILI_BASE + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" + +config DIMM_SPD_SIZE + int + default 512 + +config CBFS_SIZE + hex + default 0xb00000 + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name new file mode 100644 index 0000000000..a96a28c1e3 --- /dev/null +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "CHILI" + +config BOARD_SIEMENS_CHILI_BASE + bool "-> Base board" diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc new file mode 100644 index 0000000000..abeedf3a85 --- /dev/null +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +romstage-y += romstage.c + +ramstage-y += mainboard.c +ramstage-y += ec.c + +smm-y += ec.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/chili/board_info.txt b/src/mainboard/siemens/chili/board_info.txt new file mode 100644 index 0000000000..cb5b428331 --- /dev/null +++ b/src/mainboard/siemens/chili/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/siemens/chili/cmos.layout b/src/mainboard/siemens/chili/cmos.layout new file mode 100644 index 0000000000..4a758d9956 --- /dev/null +++ b/src/mainboard/siemens/chili/cmos.layout @@ -0,0 +1,59 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 2 hyper_threading +401 1 e 2 vtd + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +784 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/siemens/chili/dsdt.asl b/src/mainboard/siemens/chili/dsdt.asl new file mode 100644 index 0000000000..6fd12b15f2 --- /dev/null +++ b/src/mainboard/siemens/chili/dsdt.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c new file mode 100644 index 0000000000..bc0eb7d9ff --- /dev/null +++ b/src/mainboard/siemens/chili/ec.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "ec.h" + +#define EC_STATUS 0x50 +#define EC_RUNNING (1 << 1) +#define EC_DEVICE_CONTROL_1 0x80 +#define EC_DEVICE_CONTROL_1_PROGAS_ON (1 << 0) +#define EC_DEVICE_CONTROL_1_BOOMER_ON (1 << 1) +#define EC_DEVICE_CONTROL_1_BT_RF_ON (1 << 2) +#define EC_DEVICE_CONTROL_1_TP_ON (1 << 3) +#define EC_DEVICE_CONTROL_1_LAN2_RST (1 << 6) +#define EC_DEVICE_CONTROL_2 0x81 +#define EC_DEVICE_CONTROL_2_LAN_1_ON (1 << 0) +#define EC_DEVICE_CONTROL_2_LAN_2_ON (1 << 1) +#define EC_DEVICE_CONTROL_2_WLAN_ON (1 << 2) +#define EC_DEVICE_CONTROL_2_USB_ON (1 << 3) +#define EC_DEVICE_CONTROL_2_IDE1_ON (1 << 4) +#define EC_DEVICE_CONTROL_2_IDE2_ON (1 << 5) +#define EC_DEVICE_CONTROL_2_COM1_ON (1 << 6) +#define EC_DEVICE_CONTROL_2_MPI_ON (1 << 7) + +#define RUNNING_TIMEOUT_MS 3333 + +static bool ec_running(void) +{ + struct stopwatch sw; + uint8_t ec_status; + + stopwatch_init_msecs_expire(&sw, RUNNING_TIMEOUT_MS); + do + ec_status = ec_read(EC_STATUS); + while (!(ec_status & EC_RUNNING) && !stopwatch_expired(&sw)); + + if (!(ec_status & EC_RUNNING)) + printk(BIOS_WARNING, "EC not ready after %dms\n", RUNNING_TIMEOUT_MS); + + return !!(ec_status & EC_RUNNING); +} + +void ec_enable_devices(bool enable_usb) +{ + uint8_t control_1, control_2; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BT_RF_ON); + control_1 |= EC_DEVICE_CONTROL_1_BOOMER_ON; + + control_2 &= ~(EC_DEVICE_CONTROL_2_WLAN_ON | EC_DEVICE_CONTROL_2_USB_ON); + control_2 |= EC_DEVICE_CONTROL_2_MPI_ON; + if (enable_usb) + control_2 |= EC_DEVICE_CONTROL_2_USB_ON; + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} + +void mainboard_smi_sleep(const uint8_t slp_typ) +{ + uint8_t control_1, control_2; + + if (slp_typ != ACPI_S5) + return; + + if (!ec_running()) + return; + + control_1 = ec_read(EC_DEVICE_CONTROL_1); + control_2 = ec_read(EC_DEVICE_CONTROL_2); + + printk(BIOS_INFO, "EC previous EDC1: 0x%02x\n", control_1); + printk(BIOS_INFO, "EC previous EDC2: 0x%02x\n", control_2); + + control_1 &= ~(EC_DEVICE_CONTROL_1_BOOMER_ON); + control_2 &= ~(EC_DEVICE_CONTROL_2_USB_ON | EC_DEVICE_CONTROL_2_MPI_ON); + + ec_write(EC_DEVICE_CONTROL_1, control_1); + ec_write(EC_DEVICE_CONTROL_2, control_2); + + printk(BIOS_INFO, "EC current EDC1: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_1)); + printk(BIOS_INFO, "EC current EDC2: 0x%02x\n", ec_read(EC_DEVICE_CONTROL_2)); +} diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/ec.h new file mode 100644 index 0000000000..50d724ff38 --- /dev/null +++ b/src/mainboard/siemens/chili/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SIEMENS_CHILI_EC_H +#define _SIEMENS_CHILI_EC_H + +void ec_enable_devices(bool enable_usb); + +#endif /* _SIEMENS_CHILI_EC_H */ diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c new file mode 100644 index 0000000000..42e132dcf9 --- /dev/null +++ b/src/mainboard/siemens/chili/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "ec.h" + +static void mainboard_dev_init(struct device *dev) +{ + const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE); + ec_enable_devices(enable_usb); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_dev_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c new file mode 100644 index 0000000000..9c941c27fd --- /dev/null +++ b/src/mainboard/siemens/chili/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "variant.h" + +static void mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + uint8_t vtd = 1; + const struct cnl_mb_cfg cfg = { + .spd = { + [0] = { READ_SMBUS, { 0x50 << 1 } }, + [2] = { READ_SMBUS, { 0x52 << 1 } }, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, + .ect = 0, + }; + cannonlake_memcfg_init(&memupd->FspmConfig, &cfg); + memupd->FspmConfig.EccSupport = 1; + memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; + + get_option(&vtd, "vtd"); + memupd->FspmTestConfig.VtdDisable = !vtd; + get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + + mainboard_init(); +} diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/variant.h new file mode 100644 index 0000000000..423608f641 --- /dev/null +++ b/src/mainboard/siemens/chili/variant.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_H_ +#define _VARIANT_H_ + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/variants/base/Makefile.inc b/src/mainboard/siemens/chili/variants/base/Makefile.inc new file mode 100644 index 0000000000..86b9433353 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/siemens/chili/variants/base/board_info.txt b/src/mainboard/siemens/chili/variants/base/board_info.txt new file mode 100644 index 0000000000..a5d0991f51 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Chili base board diff --git a/src/mainboard/siemens/chili/variants/base/data.vbt b/src/mainboard/siemens/chili/variants/base/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..f79a60052594b56c0b16eb0e6dbf793b3865d11c GIT binary patch literal 6144 zcmeHKYiv_>6hF7O&wuaj+B<}<;5;IaZs2x1SOuJNyLPa$Zf(~wOEg&rEwWhH*oGOt zsBtDFKGF|r&=6hX7lVl*Q9l_Yeo#q>LX5%}6Zv9-M5BoqzX0{z2kl^iRiYqCPka97 z{2%vs&pH2d|Bq#ZodcNa*%k}+bfH06kYStWB$aciGa63~MM49iq0U%5+=Ji2LhySo zp9jctT!Rph&-lxrrwxN5?P`j$&xXj$A%BK0KMrVrp=6 z2vtmxb?zIGddlS)E zXdoKz!+1YNqNz|S)z#Y>+lGn$cz3ijI?xpnS=o*7=-B@8k;ivUqCeb(ZS;=&HBilD z43CbFwO}Zp$9{Fp1or19a^p|tvMnN0L5_jl%mHu~s8fK0OKkvl1iM1bUv}?%?rgqLm9V_f$_0H}kcwVd1v*mU|`EnPy-Ef}ZRkG;P9*>rC&NxhBW&jVFv*+XIer~1H6I7N17VfJ4G$A1iBDJ3JRP)6$OtmC2ljk+60BeM*Cr--SNAg z1nl zHU6uTod8N?ol2!UT@&hI3w_VLy<>Wb=F3)q-`){geys@4O;LvSbe(d zwhmp+EpKO!PhArh|6)32V{poLfje0Lf6$P>z@6jA7FBFfqvoFHr$@GuYI?m^)*^6q z1eSEeX-A=mXYY2~GfVZp#+z%o=P}Ajlbsd@1&~w$y1@@#h`=&f02xSV=O+7=Ex2Mw zbxnv+SKhQM56{;8K5)Ur>=sQwLIlwC8t@M?9A?r4W6v^tmq{Np_8G&UnDiH8oD)|% zrS(o0cH)RrdfLfebmIF?=~E~B%89=^rIM351Z)+gkidEb+$%^g2<#OBKNO@d1a?xu zKLyDqGLMK4h*DH!DG~RJ(n}(HUBpjB>1&al5%H2J)wx)M3pcu?q>DZ35}PGU!E}}@ zcwE}C!#*z1+LJa3n!LcdNm}Yw(k?f5Qi2C)vsXP7kWZWDN0_NY2&9*wzpy}$QDg9c zzTwea(Q-aNLbd^v5Uh~B2ZK6-H+X>8PfKJbm{o)hIx}703%MB%B|%o?vHG$N^q{H> zQx;!U2veB!xfS;;1g>cL2MF)APMuBqRw(I16&tvsRYOp$N2{=*d!r(6KiZ}!$0`U` z{RAWoTB?cU&U*)sB%x8>R5a#7jbu^VJIR!4;_ysMaVFzyRAe;ff@afP)J~^D!B&kI z{*J=T*wOn4p;`4EfDkN2?VKXaSf;DUhqsz$P9>+8%854@l@WMws=A<9t3i;PmE)P| ztn5u1w*s<(r*u>iZZan|1W`w@U=?1R_rXj87s-MgR-e-1z!&LzBpV90by_~CNq+sT z{^-HNmc8rNDv97ONPkXO1+VzQnY&bgj?)?a$iH0vU@2pkt|8Mk zw0a@Dyot<=(#d@*ZC+Ve&AkEVcxaJ1I9R4TL)F85<>GP6<(fH{<{Qs{t+y6|S_Enl Ns70U_f!h>;zX6wy%^v^& literal 0 HcmV?d00001 diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb new file mode 100644 index 0000000000..505e9a4852 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + register "speed_shift_enable" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # PCIe x16 + device pci 01.1 off end # PCIe x8 + device pci 01.2 off end # PCIe x4 + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # Imaging Processing Unit + device pci 08.0 off end # Gaussian mixture model, Neural network accelerator + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi Wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" # HDD / SSD + register "SataPortsEnable[1]" = "1" # ODD + register "SataPortsEnable[3]" = "1" # HDD / SSD + + register "SataPortsDevSlp[0]" = "1" # M.2 + register "SataPortsDevSlp[2]" = "1" # HDD / SSD + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 i219 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcUsage[4]" = "0x70" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[4]" = "0" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 i210 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[5]" = "0" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on end # x1 M.2 (WLAN / BT) + register "PcieRpEnable[6]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + end + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on # PCI Express Port 17 + device pci 00.0 on end # x4 M.2/M + register "PcieRpEnable[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieRpSlotImplemented[16]" = "1" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + device pci 1f.7 off end # TraceHub + end +end diff --git a/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads new file mode 100644 index 0000000000..42a2f2cea4 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- VGA (DVI-I) + HDMI2, -- DVI-I + DP3, -- DP++ + HDMI3, -- DP++ + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c new file mode 100644 index 0000000000..65ea037a3a --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* I2S1_SFRM GPIO */ PAD_NC(I2S1_SFRM, NONE), +/* I2S1_TXD GPIO */ PAD_NC(I2S1_TXD, NONE), +/* GPD0 BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} From 59143bbebdcb1e0c12af720858c1d73af8e4d680 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 13 Oct 2020 12:14:09 +0200 Subject: [PATCH 116/354] src/soc/samsung: Move common headers to "common/include/soc" Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- .../include/soc/alternate_cbfs.h | 6 +- .../{exynos5250 => common}/include/soc/dsim.h | 6 +- src/soc/samsung/common/include/soc/i2c.h | 8 ++ .../include/soc/i2s-regs.h | 6 +- .../include/soc/sysreg.h | 6 +- .../{exynos5250 => common}/include/soc/tmu.h | 6 +- .../include/soc/trustzone.h | 6 +- .../{exynos5250 => common}/include/soc/uart.h | 6 +- .../include/soc/wakeup.h | 6 +- src/soc/samsung/exynos5250/Makefile.inc | 1 + src/soc/samsung/exynos5250/include/soc/i2c.h | 8 -- .../samsung/exynos5250/include/soc/i2s-regs.h | 125 ------------------ .../samsung/exynos5250/include/soc/sysreg.h | 26 ---- .../exynos5250/include/soc/trustzone.h | 65 --------- .../samsung/exynos5250/include/soc/wakeup.h | 26 ---- src/soc/samsung/exynos5420/Makefile.inc | 1 + .../exynos5420/include/soc/alternate_cbfs.h | 22 --- src/soc/samsung/exynos5420/include/soc/dsim.h | 92 ------------- src/soc/samsung/exynos5420/include/soc/i2c.h | 8 -- src/soc/samsung/exynos5420/include/soc/tmu.h | 118 ----------------- src/soc/samsung/exynos5420/include/soc/uart.h | 24 ---- 21 files changed, 34 insertions(+), 538 deletions(-) rename src/soc/samsung/{exynos5250 => common}/include/soc/alternate_cbfs.h (81%) rename src/soc/samsung/{exynos5250 => common}/include/soc/dsim.h (93%) create mode 100644 src/soc/samsung/common/include/soc/i2c.h rename src/soc/samsung/{exynos5420 => common}/include/soc/i2s-regs.h (95%) rename src/soc/samsung/{exynos5420 => common}/include/soc/sysreg.h (77%) rename src/soc/samsung/{exynos5250 => common}/include/soc/tmu.h (95%) rename src/soc/samsung/{exynos5420 => common}/include/soc/trustzone.h (88%) rename src/soc/samsung/{exynos5250 => common}/include/soc/uart.h (74%) rename src/soc/samsung/{exynos5420 => common}/include/soc/wakeup.h (78%) delete mode 100644 src/soc/samsung/exynos5250/include/soc/i2c.h delete mode 100644 src/soc/samsung/exynos5250/include/soc/i2s-regs.h delete mode 100644 src/soc/samsung/exynos5250/include/soc/sysreg.h delete mode 100644 src/soc/samsung/exynos5250/include/soc/trustzone.h delete mode 100644 src/soc/samsung/exynos5250/include/soc/wakeup.h delete mode 100644 src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h delete mode 100644 src/soc/samsung/exynos5420/include/soc/dsim.h delete mode 100644 src/soc/samsung/exynos5420/include/soc/i2c.h delete mode 100644 src/soc/samsung/exynos5420/include/soc/tmu.h delete mode 100644 src/soc/samsung/exynos5420/include/soc/uart.h diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/common/include/soc/alternate_cbfs.h similarity index 81% rename from src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h rename to src/soc/samsung/common/include/soc/alternate_cbfs.h index b978e0c026..63edc6a902 100644 --- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h +++ b/src/soc/samsung/common/include/soc/alternate_cbfs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H -#define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H /* These are pointers to function pointers. Double indirection! */ static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; @@ -19,4 +19,4 @@ static u32 *const iram_secondary_base = (u32 *)0x02020018; #define OM_STAT_SPI 0x14 #define OM_STAT_MASK 0x7f -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_ALTERNATE_CBFS_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/dsim.h b/src/soc/samsung/common/include/soc/dsim.h similarity index 93% rename from src/soc/samsung/exynos5250/include/soc/dsim.h rename to src/soc/samsung/common/include/soc/dsim.h index d85180252b..541c72a3c0 100644 --- a/src/soc/samsung/exynos5250/include/soc/dsim.h +++ b/src/soc/samsung/common/include/soc/dsim.h @@ -2,8 +2,8 @@ /* Register map for Exynos5 MIPI-DSIM */ -#ifndef CPU_SAMSUNG_EXYNOS5250_DSIM_H -#define CPU_SAMSUNG_EXYNOS5250_DSIM_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H /* DSIM register map */ struct exynos5_dsim { @@ -89,4 +89,4 @@ check_member(exynos5_dsim, phyacchr1, 0x54); #define DSIM_STOP_STATE_CLK (1 << 8) #define DSIM_TX_READY_HS_CLK (1 << 10) -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_DSIM_H */ diff --git a/src/soc/samsung/common/include/soc/i2c.h b/src/soc/samsung/common/include/soc/i2c.h new file mode 100644 index 0000000000..44feb6b046 --- /dev/null +++ b/src/soc/samsung/common/include/soc/i2c.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H + +void i2c_init(unsigned int bus, int speed, int slaveadd); + +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2C_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h b/src/soc/samsung/common/include/soc/i2s-regs.h similarity index 95% rename from src/soc/samsung/exynos5420/include/soc/i2s-regs.h rename to src/soc/samsung/common/include/soc/i2s-regs.h index 696eb2fab8..012ca693bb 100644 --- a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h +++ b/src/soc/samsung/common/include/soc/i2s-regs.h @@ -2,8 +2,8 @@ /* Taken from the kernel code */ -#ifndef CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H -#define CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H #define I2SCON 0x0 #define I2SMOD 0x4 @@ -122,4 +122,4 @@ #define I2SSIZE_TRNMSK (0xffff) #define I2SSIZE_SHIFT (16) -#endif /* CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_I2S_REGS_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/sysreg.h b/src/soc/samsung/common/include/soc/sysreg.h similarity index 77% rename from src/soc/samsung/exynos5420/include/soc/sysreg.h rename to src/soc/samsung/common/include/soc/sysreg.h index 91ddf3142b..501d6d5af4 100644 --- a/src/soc/samsung/exynos5420/include/soc/sysreg.h +++ b/src/soc/samsung/common/include/soc/sysreg.h @@ -2,8 +2,8 @@ /* Register map for Exynos5 sysreg */ -#ifndef CPU_SAMSUNG_EXYNOS5420_SYSREG_H -#define CPU_SAMSUNG_EXYNOS5420_SYSREG_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H #include @@ -23,4 +23,4 @@ static struct exynos5_sysreg * const exynos_sysreg = #define FIMDBYPASS_DISP1 (1 << 15) #define USB20_PHY_CFG_EN (1 << 0) -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_SYSREG_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/tmu.h b/src/soc/samsung/common/include/soc/tmu.h similarity index 95% rename from src/soc/samsung/exynos5250/include/soc/tmu.h rename to src/soc/samsung/common/include/soc/tmu.h index cb7e47284c..44996f6fdf 100644 --- a/src/soc/samsung/exynos5250/include/soc/tmu.h +++ b/src/soc/samsung/common/include/soc/tmu.h @@ -2,8 +2,8 @@ /* EXYNOS - Thermal Management Unit */ -#ifndef CPU_SAMSUNG_EXYNOS5250_TMU_H -#define CPU_SAMSUNG_EXYNOS5250_TMU_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H struct tmu_reg { unsigned int triminfo; @@ -115,4 +115,4 @@ enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp); */ int tmu_init(struct tmu_info *info); -#endif /* CPU_SAMSUNG_EXYNOS5250_TMU_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TMU_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/trustzone.h b/src/soc/samsung/common/include/soc/trustzone.h similarity index 88% rename from src/soc/samsung/exynos5420/include/soc/trustzone.h rename to src/soc/samsung/common/include/soc/trustzone.h index 21f8a0eed9..c95e98db16 100644 --- a/src/soc/samsung/exynos5420/include/soc/trustzone.h +++ b/src/soc/samsung/common/include/soc/trustzone.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H -#define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H #include @@ -62,4 +62,4 @@ check_member(exynos_tzpc, pcellid3, 0xffc); void trustzone_init(void); -#endif /* CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_TRUSTZONE_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/uart.h b/src/soc/samsung/common/include/soc/uart.h similarity index 74% rename from src/soc/samsung/exynos5250/include/soc/uart.h rename to src/soc/samsung/common/include/soc/uart.h index 0ac4ba1139..b530e075e5 100644 --- a/src/soc/samsung/exynos5250/include/soc/uart.h +++ b/src/soc/samsung/common/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5250_UART_H -#define CPU_SAMSUNG_EXYNOS5250_UART_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H struct s5p_uart { unsigned int ulcon; @@ -21,4 +21,4 @@ struct s5p_uart { }; check_member(s5p_uart, ubrdiv, 0x28); -#endif +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_UART_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/wakeup.h b/src/soc/samsung/common/include/soc/wakeup.h similarity index 78% rename from src/soc/samsung/exynos5420/include/soc/wakeup.h rename to src/soc/samsung/common/include/soc/wakeup.h index a9b8fc51fc..bc678004d0 100644 --- a/src/soc/samsung/exynos5420/include/soc/wakeup.h +++ b/src/soc/samsung/common/include/soc/wakeup.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_SAMSUNG_EXYNOS5420_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5420_WAKEUP_H +#ifndef SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H +#define SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,4 +23,4 @@ int get_wakeup_state(void); void wakeup(void); void wakeup_enable_uart(void); -#endif /* CPU_SAMSUNG_EXYNOS5420_WAKEUP_H */ +#endif /* SOC_SAMSUNG_COMMON_INCLUDE_SOC_WAKEUP_H */ diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 6a595f4b82..861c0bb8fb 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += dp-reg.c ramstage-y += fb.c ramstage-y += usb.c +CPPFLAGS_common += -Isrc/soc/samsung/common/include/ CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin diff --git a/src/soc/samsung/exynos5250/include/soc/i2c.h b/src/soc/samsung/exynos5250/include/soc/i2c.h deleted file mode 100644 index 76c4cbb6d3..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/i2c.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H -#define CPU_SAMSUNG_EXYNOS5250_I2C_H - -void i2c_init(unsigned int bus, int speed, int slaveadd); - -#endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h b/src/soc/samsung/exynos5250/include/soc/i2s-regs.h deleted file mode 100644 index 6b494daf41..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/i2s-regs.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Taken from the kernel code */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H -#define CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H - -#define I2SCON 0x0 -#define I2SMOD 0x4 -#define I2SFIC 0x8 -#define I2SPSR 0xc -#define I2STXD 0x10 -#define I2SRXD 0x14 -#define I2SFICS 0x18 -#define I2STXDS 0x1c -#define I2SAHB 0x20 -#define I2SSTR0 0x24 -#define I2SSIZE 0x28 -#define I2STRNCNT 0x2c -#define I2SLVL0ADDR 0x30 -#define I2SLVL1ADDR 0x34 -#define I2SLVL2ADDR 0x38 -#define I2SLVL3ADDR 0x3c - -#define CON_RSTCLR (1 << 31) -#define CON_FRXOFSTATUS (1 << 26) -#define CON_FRXORINTEN (1 << 25) -#define CON_FTXSURSTAT (1 << 24) -#define CON_FTXSURINTEN (1 << 23) -#define CON_TXSDMA_PAUSE (1 << 20) -#define CON_TXSDMA_ACTIVE (1 << 18) - -#define CON_FTXURSTATUS (1 << 17) -#define CON_FTXURINTEN (1 << 16) -#define CON_TXFIFO2_EMPTY (1 << 15) -#define CON_TXFIFO1_EMPTY (1 << 14) -#define CON_TXFIFO2_FULL (1 << 13) -#define CON_TXFIFO1_FULL (1 << 12) - -#define CON_LRINDEX (1 << 11) -#define CON_TXFIFO_EMPTY (1 << 10) -#define CON_RXFIFO_EMPTY (1 << 9) -#define CON_TXFIFO_FULL (1 << 8) -#define CON_RXFIFO_FULL (1 << 7) -#define CON_TXDMA_PAUSE (1 << 6) -#define CON_RXDMA_PAUSE (1 << 5) -#define CON_TXCH_PAUSE (1 << 4) -#define CON_RXCH_PAUSE (1 << 3) -#define CON_TXDMA_ACTIVE (1 << 2) -#define CON_RXDMA_ACTIVE (1 << 1) -#define CON_ACTIVE (1 << 0) - -#define MOD_OPCLK_CDCLK_OUT (0 << 30) -#define MOD_OPCLK_CDCLK_IN (1 << 30) -#define MOD_OPCLK_BCLK_OUT (2 << 30) -#define MOD_OPCLK_PCLK (3 << 30) -#define MOD_OPCLK_MASK (3 << 30) -#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */ - -#define MOD_BLCS_SHIFT 26 -#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT) -#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT) -#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT) -#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT) - -#define MOD_BLCP_SHIFT 24 -#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) -#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) -#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) -#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) - -#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */ -#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */ -#define MOD_C1DD_HHALF (1 << 19) -#define MOD_C1DD_LHALF (1 << 18) -#define MOD_DC2_EN (1 << 17) -#define MOD_DC1_EN (1 << 16) -#define MOD_BLC_16BIT (0 << 13) -#define MOD_BLC_8BIT (1 << 13) -#define MOD_BLC_24BIT (2 << 13) -#define MOD_BLC_MASK (3 << 13) - -#define MOD_IMS_SYSMUX (1 << 10) -#define MOD_SLAVE (1 << 11) -#define MOD_TXONLY (0 << 8) -#define MOD_RXONLY (1 << 8) -#define MOD_TXRX (2 << 8) -#define MOD_MASK (3 << 8) -#define MOD_LR_LLOW (0 << 7) -#define MOD_LR_RLOW (1 << 7) -#define MOD_SDF_IIS (0 << 5) -#define MOD_SDF_MSB (1 << 5) -#define MOD_SDF_LSB (2 << 5) -#define MOD_SDF_MASK (3 << 5) -#define MOD_RCLK_256FS (0 << 3) -#define MOD_RCLK_512FS (1 << 3) -#define MOD_RCLK_384FS (2 << 3) -#define MOD_RCLK_768FS (3 << 3) -#define MOD_RCLK_MASK (3 << 3) -#define MOD_BCLK_32FS (0 << 1) -#define MOD_BCLK_48FS (1 << 1) -#define MOD_BCLK_16FS (2 << 1) -#define MOD_BCLK_24FS (3 << 1) -#define MOD_BCLK_MASK (3 << 1) -#define MOD_8BIT (1 << 0) - -#define MOD_CDCLKCON (1 << 12) - -#define PSR_PSREN (1 << 15) - -#define FIC_TXFLUSH (1 << 15) -#define FIC_RXFLUSH (1 << 7) - -#define AHB_INTENLVL0 (1 << 24) -#define AHB_LVL0INT (1 << 20) -#define AHB_CLRLVL0INT (1 << 16) -#define AHB_DMARLD (1 << 5) -#define AHB_INTMASK (1 << 3) -#define AHB_DMAEN (1 << 0) -#define AHB_LVLINTMASK (0xf << 20) - -#define I2SSIZE_TRNMSK (0xffff) -#define I2SSIZE_SHIFT (16) - -#endif /* CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/sysreg.h b/src/soc/samsung/exynos5250/include/soc/sysreg.h deleted file mode 100644 index 3219264ebd..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/sysreg.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Register map for Exynos5 sysreg */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_SYSREG_H -#define CPU_SAMSUNG_EXYNOS5250_SYSREG_H - -#include - -/* sysreg map */ -struct exynos5_sysreg { - /* Add registers as and when required */ - unsigned char res1[0x214]; - unsigned int disp1blk_cfg; - unsigned char res2[0x18]; - unsigned int usb20_phy_cfg; -}; -check_member(exynos5_sysreg, usb20_phy_cfg, 0x230); - -static struct exynos5_sysreg * const exynos_sysreg = - (void *)EXYNOS5_SYSREG_BASE; - -#define FIMDBYPASS_DISP1 (1 << 15) -#define USB20_PHY_CFG_EN (1 << 0) - -#endif diff --git a/src/soc/samsung/exynos5250/include/soc/trustzone.h b/src/soc/samsung/exynos5250/include/soc/trustzone.h deleted file mode 100644 index c867d0832c..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/trustzone.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H -#define CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H - -#include - -/* Distance between each Trust Zone PC register set */ -#define TZPC_BASE_OFFSET 0x10000 -/* TZPC : Register Offsets */ -#define TZPC0_BASE 0x10100000 -#define TZPC1_BASE 0x10110000 -#define TZPC2_BASE 0x10120000 -#define TZPC3_BASE 0x10130000 -#define TZPC4_BASE 0x10140000 -#define TZPC5_BASE 0x10150000 -#define TZPC6_BASE 0x10160000 -#define TZPC7_BASE 0x10170000 -#define TZPC8_BASE 0x10180000 -#define TZPC9_BASE 0x10190000 -#define TZPC10_BASE 0x100E0000 -#define TZPC11_BASE 0x100F0000 - -/* - * TZPC Register Value : - * R0SIZE: 0x0 : Size of secured ram - */ -#define R0SIZE 0x0 - -/* - * TZPC Decode Protection Register Value : - * DECPROTXSET: 0xFF : Set Decode region to non-secure - */ -#define DECPROTXSET 0xFF - -struct exynos_tzpc { - u32 r0size; - u8 res1[0x7FC]; - u32 decprot0stat; - u32 decprot0set; - u32 decprot0clr; - u32 decprot1stat; - u32 decprot1set; - u32 decprot1clr; - u32 decprot2stat; - u32 decprot2set; - u32 decprot2clr; - u32 decprot3stat; - u32 decprot3set; - u32 decprot3clr; - u8 res2[0x7B0]; - u32 periphid0; - u32 periphid1; - u32 periphid2; - u32 periphid3; - u32 pcellid0; - u32 pcellid1; - u32 pcellid2; - u32 pcellid3; -}; -check_member(exynos_tzpc, pcellid3, 0xffc); - -void trustzone_init(void); - -#endif /* CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H */ diff --git a/src/soc/samsung/exynos5250/include/soc/wakeup.h b/src/soc/samsung/exynos5250/include/soc/wakeup.h deleted file mode 100644 index 1d4f44a751..0000000000 --- a/src/soc/samsung/exynos5250/include/soc/wakeup.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5250_WAKEUP_H -#define CPU_SAMSUNG_EXYNOS5250_WAKEUP_H - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -enum { - // A normal boot (not suspend/resume) - IS_NOT_WAKEUP, - // A wake up event that can be resumed any time - WAKEUP_DIRECT, - // A wake up event that must be resumed only after - // clock and memory controllers are re-initialized - WAKEUP_NEED_CLOCK_RESET, -}; - -int wakeup_need_reset(void); -int get_wakeup_state(void); -void wakeup(void); -void wakeup_enable_uart(void); - -#endif /* CPU_SAMSUNG_EXYNOS5250_WAKEUP_H */ diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index dc25919ff6..f455558bfe 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += usb.c rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c +CPPFLAGS_common += -Isrc/soc/samsung/common/include/ CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h deleted file mode 100644 index 4e49b84f1f..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H -#define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H - -/* These are pointers to function pointers. Double indirection! */ -static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030; -static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044; -static void **const irom_msh_end_boot_op_emmc_ptr = (void **)0x02020048; -static void **const irom_spi_sf_read_ptr = (void **)0x02020058; -static void **const irom_load_image_from_usb_ptr = (void **)0x02020070; - -#define SECONDARY_BASE_BOOT_USB 0xfeed0002 -static u32 *const iram_secondary_base = (u32 *)0x02020018; - -/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */ -#define OM_STAT_SDMMC 0x4 -#define OM_STAT_EMMC 0x8 -#define OM_STAT_SPI 0x14 -#define OM_STAT_MASK 0x7f - -#endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/exynos5420/include/soc/dsim.h deleted file mode 100644 index b6b7ee9a12..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/dsim.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Register map for Exynos5 MIPI-DSIM */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_DSIM_H -#define CPU_SAMSUNG_EXYNOS5420_DSIM_H - -/* DSIM register map */ -struct exynos5_dsim { - unsigned int status; - unsigned int swrst; - unsigned int clkctrl; - unsigned int timeout; - unsigned int config; - unsigned int escmode; - unsigned int mdresol; - unsigned int mvporch; - unsigned int mhporch; - unsigned int msync; - unsigned int sdresol; - unsigned int intsrc; - unsigned int intmsk; - unsigned int pkthdr; - unsigned int payload; - unsigned int rxfifo; - unsigned int res1; - unsigned int fifoctrl; - unsigned int res2; - unsigned int pllctrl; - unsigned int plltmr; - unsigned int phyacchr; - unsigned int phyacchr1; -}; -check_member(exynos5_dsim, phyacchr1, 0x54); - -#define ENABLE 1 -#define DISABLE 0 - -#define DSIM_SWRST (1 << 0) -#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5) -#define DATA_LANE_0_EN (1 << 0) -#define DATA_LANE_1_EN (1 << 1) -#define DATA_LANE_2_EN (1 << 2) -#define DATA_LANE_3_EN (1 << 3) -#define CLK_LANE_EN (1 << 4) -#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \ - DATA_LANE_1_EN | \ - DATA_LANE_2_EN | \ - DATA_LANE_3_EN -#define MAIN_PIX_FORMAT_OFFSET 12 -#define RGB_565_16_BIT 0x4 -#define VIDEO_MODE (1 << 25) -#define BURST_MODE (1 << 26) - -#define DSIM_PHYACCHR_AFC_EN (1 << 14) -#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 - -#define DSIM_PLLCTRL_PMS_OFFSET 1 -#define DSIM_FREQ_BAND_OFFSET 24 - -#define LANE_ESC_CLK_EN_ALL (0x1f << 19) -#define BYTE_CLK_EN (1 << 24) -#define DSIM_ESC_CLK_EN (1 << 28) -#define TXREQUEST_HS_CLK_ON (1 << 31) - -#define LP_MODE_ENABLE (1 << 7) -#define STOP_STATE_CNT_OFFSET 21 - -#define MAIN_VBP_OFFSET 0 -#define STABLE_VFP_OFFSET 16 -#define CMD_ALLOW_OFFSET 28 - -#define MAIN_HBP_OFFSET 0 -#define MAIN_HFP_OFFSET 16 - -#define MAIN_HSA_OFFSET 0 -#define MAIN_VSA_OFFSET 22 - -#define MAIN_STANDBY (1 << 31) -#define MAIN_VRESOL_OFFSET 16 -#define MAIN_HRESOL_OFFSET 0 - -#define SFR_FIFO_EMPTY (1 << 29) - -#define DSIM_PLL_EN_SHIFT (1 << 23) -#define PLL_STABLE (1 << 31) - -#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) - -#endif diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h deleted file mode 100644 index 8b2f019c41..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/i2c.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H -#define CPU_SAMSUNG_EXYNOS5420_I2C_H - -void i2c_init(unsigned int bus, int speed, int slaveadd); - -#endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/exynos5420/include/soc/tmu.h deleted file mode 100644 index e65d69df21..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/tmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* EXYNOS - Thermal Management Unit */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_TMU_H -#define CPU_SAMSUNG_EXYNOS5420_TMU_H - -struct tmu_reg { - unsigned int triminfo; - unsigned int rsvd1; - unsigned int rsvd2; - unsigned int rsvd3; - unsigned int rsvd4; - unsigned int triminfo_control; - unsigned int rsvd5; - unsigned int rsvd6; - unsigned int tmu_control; - unsigned int rsvd7; - unsigned int tmu_status; - unsigned int sampling_internal; - unsigned int counter_value0; - unsigned int counter_value1; - unsigned int rsvd8; - unsigned int rsvd9; - unsigned int current_temp; - unsigned int rsvd10; - unsigned int rsvd11; - unsigned int rsvd12; - unsigned int threshold_temp_rise; - unsigned int threshold_temp_fall; - unsigned int rsvd13; - unsigned int rsvd14; - unsigned int past_temp3_0; - unsigned int past_temp7_4; - unsigned int past_temp11_8; - unsigned int past_temp15_12; - unsigned int inten; - unsigned int intstat; - unsigned int intclear; - unsigned int rsvd15; - unsigned int emul_con; -}; -check_member(tmu_reg, emul_con, 0x80); - -enum tmu_status_t { - TMU_STATUS_INIT = 0, - TMU_STATUS_NORMAL, - TMU_STATUS_WARNING, - TMU_STATUS_TRIPPED, -}; - -/* Temperature threshold values for various thermal events */ -struct temperature_params { - /* minimum value in temperature code range */ - unsigned int min_val; - /* maximum value in temperature code range */ - unsigned int max_val; - /* temperature threshold to start warning */ - unsigned int start_warning; - /* temperature threshold CPU tripping */ - unsigned int start_tripping; - /* temperature threshold for HW tripping */ - unsigned int hardware_tripping; -}; - -/* Pre-defined values and thresholds for calibration of current temperature */ -struct tmu_data { - /* pre-defined temperature thresholds */ - struct temperature_params ts; - /* pre-defined efuse range minimum value */ - unsigned int efuse_min_value; - /* pre-defined efuse value for temperature calibration */ - unsigned int efuse_value; - /* pre-defined efuse range maximum value */ - unsigned int efuse_max_value; - /* current temperature sensing slope */ - unsigned int slope; -}; - -/* TMU device specific details and status */ -struct tmu_info { - /* base Address for the TMU */ - unsigned int tmu_base; - /* mux Address for the TMU */ - int tmu_mux; - /* pre-defined values for calibration and thresholds */ - struct tmu_data data; - /* value required for triminfo_25 calibration */ - unsigned int te1; - /* value required for triminfo_85 calibration */ - unsigned int te2; - /* TMU DC value for threshold calculation */ - int dc_value; - /* enum value indicating status of the TMU */ - int tmu_state; -}; - -extern struct tmu_info *tmu_info; - -/* - * Monitors status of the TMU device and exynos temperature - * - * @info pointer to TMU info struct - * @temp pointer to the current temperature value - * @return enum tmu_status_t value, code indicating event to execute - * and -1 on error - */ -enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp); - -/* - * Initialize TMU device - * - * @info pointer to TMU info struct - * @return int value, 0 for success - */ -int tmu_init(struct tmu_info *info); - -#endif /* CPU_SAMSUNG_EXYNOS5420_TMU_H */ diff --git a/src/soc/samsung/exynos5420/include/soc/uart.h b/src/soc/samsung/exynos5420/include/soc/uart.h deleted file mode 100644 index de9975c34a..0000000000 --- a/src/soc/samsung/exynos5420/include/soc/uart.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CPU_SAMSUNG_EXYNOS5420_UART_H -#define CPU_SAMSUNG_EXYNOS5420_UART_H - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - unsigned char res3[0xffd0]; -}; -check_member(s5p_uart, ubrdiv, 0x28); - -#endif From 78efb84509080508d71c1348dd39718bdec90a61 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 13 Oct 2020 11:13:59 +0200 Subject: [PATCH 117/354] soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46330 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3288/gpio.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 885b41902e..ed09d02fc4 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -1,21 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include struct rockchip_gpio_regs *gpio_port[] = { - (struct rockchip_gpio_regs *)0xff750000, - (struct rockchip_gpio_regs *)0xff780000, - (struct rockchip_gpio_regs *)0xff790000, - (struct rockchip_gpio_regs *)0xff7a0000, - (struct rockchip_gpio_regs *)0xff7b0000, - (struct rockchip_gpio_regs *)0xff7c0000, - (struct rockchip_gpio_regs *)0xff7d0000, - (struct rockchip_gpio_regs *)0xff7e0000, - (struct rockchip_gpio_regs *)0xff7f0000 + (struct rockchip_gpio_regs *)GPIO0_BASE, + (struct rockchip_gpio_regs *)GPIO1_BASE, + (struct rockchip_gpio_regs *)GPIO2_BASE, + (struct rockchip_gpio_regs *)GPIO3_BASE, + (struct rockchip_gpio_regs *)GPIO4_BASE, + (struct rockchip_gpio_regs *)GPIO5_BASE, + (struct rockchip_gpio_regs *)GPIO6_BASE, + (struct rockchip_gpio_regs *)GPIO7_BASE, + (struct rockchip_gpio_regs *)GPIO8_BASE }; #define PMU_GPIO_PORT 0 From fa2db84a470eb15099e126f5cd7dca6c25796150 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 13 Oct 2020 11:01:16 +0200 Subject: [PATCH 118/354] soc/rockchip/rk3288/include/soc/display.h: Add missing includes Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46329 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/rockchip/rk3288/include/soc/display.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h index 9883799614..3cff4e990d 100644 --- a/src/soc/rockchip/rk3288/include/soc/display.h +++ b/src/soc/rockchip/rk3288/include/soc/display.h @@ -3,6 +3,9 @@ #ifndef __SOC_ROCKCHIP_RK3288_DISPLAY_H__ #define __SOC_ROCKCHIP_RK3288_DISPLAY_H__ +#include +#include + /* * this bit select edp phy pll, this bit define different between * rk3288 and rk3399 in edp phy, so implement it in soc specific code From e4ab31bc7f45ac78fad24be0e2d6b89c3c232264 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 10 Jul 2019 16:42:55 +0200 Subject: [PATCH 119/354] mb/siemens/chili: Add Chili variant This Chili mainboard is used in an all-in-one PC. For more information see https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995 Reviewed-by: Nico Huber Reviewed-by: Thomas Heijligen Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/siemens/chili/Kconfig | 19 +- src/mainboard/siemens/chili/Kconfig.name | 3 + src/mainboard/siemens/chili/mainboard.c | 3 +- src/mainboard/siemens/chili/romstage.c | 6 + src/mainboard/siemens/chili/variant.h | 4 + .../siemens/chili/variants/chili/Makefile.inc | 7 + .../chili/variants/chili/board_info.txt | 2 + .../siemens/chili/variants/chili/data.vbt | Bin 0 -> 6144 bytes .../chili/variants/chili/devicetree.cb | 194 ++++++++++++++++++ .../chili/variants/chili/gma-mainboard.ads | 19 ++ .../siemens/chili/variants/chili/gpio.c | 128 ++++++++++++ .../siemens/chili/variants/chili/hda_verb.c | 81 ++++++++ .../siemens/chili/variants/chili/romstage.c | 18 ++ 13 files changed, 481 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/siemens/chili/variants/chili/Makefile.inc create mode 100644 src/mainboard/siemens/chili/variants/chili/board_info.txt create mode 100644 src/mainboard/siemens/chili/variants/chili/data.vbt create mode 100644 src/mainboard/siemens/chili/variants/chili/devicetree.cb create mode 100644 src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads create mode 100644 src/mainboard/siemens/chili/variants/chili/gpio.c create mode 100644 src/mainboard/siemens/chili/variants/chili/hda_verb.c create mode 100644 src/mainboard/siemens/chili/variants/chili/romstage.c diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index 8c919b5631..fda571dcfe 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -1,24 +1,29 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_SIEMENS_CHILI_BASE +if BOARD_SIEMENS_CHILI_BASE || BOARD_SIEMENS_CHILI_CHILI config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_CHILI_CHILI select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_SIEMENS_CHILI_CHILI select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION + select SMBIOS_PROVIDED_BY_MOBO if BOARD_SIEMENS_CHILI_CHILI select SOC_INTEL_CANNONLAKE_PCH_H select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_SIEMENS_CHILI_CHILI + select SECUNET_DMI if BOARD_SIEMENS_CHILI_CHILI config MAINBOARD_DIR string @@ -30,11 +35,13 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string - default "Chili base board" + default "Chili base board" if BOARD_SIEMENS_CHILI_BASE + default "Chili" if BOARD_SIEMENS_CHILI_CHILI config VARIANT_DIR string default "base" if BOARD_SIEMENS_CHILI_BASE + default "chili" if BOARD_SIEMENS_CHILI_CHILI config DEVICETREE string @@ -56,4 +63,12 @@ config POST_DEVICE bool default n +config SIEMENS_CHILI_DEBUG_USB + bool "Enable debug USB port" + depends on BOARD_SIEMENS_CHILI_CHILI + +config DRIVERS_INTEL_WIFI + bool + default n if BOARD_SIEMENS_CHILI_CHILI + endif diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name index a96a28c1e3..ac4e31eef4 100644 --- a/src/mainboard/siemens/chili/Kconfig.name +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -4,3 +4,6 @@ comment "CHILI" config BOARD_SIEMENS_CHILI_BASE bool "-> Base board" + +config BOARD_SIEMENS_CHILI_CHILI + bool "-> Chili (AiO)" diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c index 42e132dcf9..91395eac07 100644 --- a/src/mainboard/siemens/chili/mainboard.c +++ b/src/mainboard/siemens/chili/mainboard.c @@ -6,7 +6,8 @@ static void mainboard_dev_init(struct device *dev) { - const bool enable_usb = CONFIG(BOARD_SIEMENS_CHILI_BASE); + const bool enable_usb = + CONFIG(BOARD_SIEMENS_CHILI_BASE) || CONFIG(SIEMENS_CHILI_DEBUG_USB); ec_enable_devices(enable_usb); } diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index 9c941c27fd..c1ec7e4982 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -38,5 +38,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmTestConfig.VtdDisable = !vtd; get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + variant_romstage_params(memupd); + mainboard_init(); } + +__weak void variant_romstage_params(FSPM_UPD *const mupd) +{ +} diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/variant.h index 423608f641..2bbe7d7926 100644 --- a/src/mainboard/siemens/chili/variant.h +++ b/src/mainboard/siemens/chili/variant.h @@ -3,6 +3,10 @@ #ifndef _VARIANT_H_ #define _VARIANT_H_ +#include + +void variant_romstage_params(FSPM_UPD *); + const struct pad_config *variant_gpio_table(size_t *num); #endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/variants/chili/Makefile.inc b/src/mainboard/siemens/chili/variants/chili/Makefile.inc new file mode 100644 index 0000000000..251a2916a2 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += romstage.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += hda_verb.c diff --git a/src/mainboard/siemens/chili/variants/chili/board_info.txt b/src/mainboard/siemens/chili/variants/chili/board_info.txt new file mode 100644 index 0000000000..f5d6b2f14a --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/board_info.txt @@ -0,0 +1,2 @@ +Board name: Chili +Category: misc diff --git a/src/mainboard/siemens/chili/variants/chili/data.vbt b/src/mainboard/siemens/chili/variants/chili/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..7c5b273c9dadbb8b279ff8f2d16d773ea46780af GIT binary patch literal 6144 zcmeHKYiv_>6hF7O&wuaj+B<}<;5;IaZs2x1SmiP0_Ayvlx3=q;Bbuy(7FjH8Y{Lv+ z)HstRKGF|r&=6hX7lVl*Q9l_Yeo#q>N{qr66Zv9-M5BoqzX0{z$JW6Dt3*MPp7#9D z`9JROo^$@^{vRv)!o8U8+!+sbwxdB=kYT51C6)6j9807JqM_c`}*zVNY%>H~K^_+axj-jT{+aj>;>*M~ zD+3SlQsR}w&BPmtBg9?A4-*d(TMxpelBr-!L4nh!qTn&6#BGLG8lZ60Xg_MSJAT)* zfEm(h$V$UjD%ossrS!EIN+tV)ss#!mklS3;K7EzAd|)zdxqgVO!|niPZ|Eiq`w&BoVeO4 zZFI7T6NjAAQ%?4R6W?=6pE%iD8)pU7V(fMy(qHRMEqEkz7pA45ig5Ujf>T}aEnVyx!5Bvu~D)VOy{_Q z$E6)R?4ts$J^dy@lNUKRNlVRY+U4d?O7Jjk_Ns>h^8KcT5vFSp0{zR-Us$Bas6KdD z-|%RzXgOaPAzKGZ2v*77si2PF4Ibw8(-N5pW)-20&P><$LT-d3DUcO;q;}Q@dQjDc z35%~Hgb7Uf+=_b+0#~&B1B7>*C(fmOtCapDWgEDnRYOp$$1AX*V~Zm1I^LovC&~y` z{RAZRSt^O-o_qU_rJ!EkS~TWDjbu^VJIRzv;_!4+aXRCxS7bEif@afP)J~^D!B&YE z{Whc_FhPp2lA%gHyE%p&mMRCPhIR)QcmDkn3O zS=pO1ZUtlmPwA*4++Lqa3SRO3vv;WgE9>Y6WL@~XXiy+ifZB}P?NJ}oZJ|ZW_u!u95rEAD^ z4Xs@aFKs0=V{~%gL7P_=)^e}Ic^;Z%4yI=5&QSGm&s;oixm-8z(tP9jul80WP>nz} N0@VmqBXFA{@HfI_%pU*% literal 0 HcmV?d00001 diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb new file mode 100644 index 0000000000..5a2fc01e37 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + register "speed_shift_enable" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # PCIe x16 + device pci 01.1 off end # PCIe x8 + device pci 01.2 off end # PCIe x4 + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # Imaging Processing Unit + device pci 08.0 off end # Gaussian mixture model, Neural network accelerator + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi Wifi + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/secunet/dmi + device i2c 0x57 on end # Serial EEPROM + end + chip drivers/i2c/lm96000 + device i2c 0x2e on end + register "vin[0].low" = " 1900 * 95/100" + register "vin[0].high" = " 1900 * 105/100" + register "vin[1].low" = " 1200 * 95/100" + register "vin[1].high" = " 1200 * 105/100" + register "vin[2].low" = " 3300 * 95/100" + register "vin[2].high" = " 3300 * 105/100" + register "vin[3].low" = " 5000 * 95/100" + register "vin[3].high" = " 5000 * 105/100" + register "vin[4].low" = "12000 * 95/100" + register "vin[4].high" = "12000 * 105/100" + + register "temp_in[0].low" = "-25" + register "temp_in[0].high" = " 85" + register "temp_in[1].low" = "-25" + register "temp_in[1].high" = " 85" + register "temp_in[2].low" = "-25" + register "temp_in[2].high" = " 85" + + register "fan[0]" = "{ + .mode = LM96000_FAN_HOTTEST_123, + .spinup = LM96000_SPINUP_2000MS, + .freq = LM96000_PWM_27_7KHZ, + .min_duty = 23, + }" + register "fan[1]" = "{ + .mode = LM96000_FAN_HOTTEST_123, + .spinup = LM96000_SPINUP_2000MS, + .freq = LM96000_PWM_27_7KHZ, + .min_duty = 23, + }" + + register "zone[0]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + register "zone[1]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + register "zone[2]" = "{ + .low_temp = 54, + .target_temp = 81, + .panic_temp = 65, + .min_off = LM96000_LOW_TEMP_MIN, + .hysteresis = 3, + }" + end + end + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off # PCI Express Port 1 + device pci 00.0 on end # Debug (x1) + register "PcieRpEnable[0]" = "0" + register "PcieClkSrcUsage[2]" = "0" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # CORE (x1) + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # i210 (x1) + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[5]" = "0" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on end # VL805 Front Rack/UIB (x1) + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[1]" = "6" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "0" + end + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # VL805 Back MB (x1) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[0]" = "7" + register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[7]" = "0" + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on # PCI Express Port 17 + device pci 00.0 on end # NVMe (x4) + register "PcieRpEnable[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieRpSlotImplemented[16]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TraceHub + end +end diff --git a/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads new file mode 100644 index 0000000000..fdb364c1b8 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP2, + DP3, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c new file mode 100644 index 0000000000..4b18e79e29 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO 0x0000002444000300 */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B8 GPIO 0x0000003844000300 */ PAD_NC(GPP_B8, NONE), +/* GPP_B14 SPKR 0x0000003e44000600 */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO 0x0000004244000300 */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO 0x0000004644000300 */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO 0x0000004d44000300 */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK 0x0000004e44000703 */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA 0x0000004f44000703 */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 UART0A_RXD 0x0000005044000702 */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* GPP_C9 UART0A_TXD 0x0000005144000700 */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GPP_C10 UART0A_RTS# 0x0000005244000700 */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* GPP_C11 UART0A_CTS# 0x0000005344000702 */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* GPP_C12 GPIO 0x0000005444000102 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO 0x0000005544000102 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO 0x0000005644000102 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO 0x0000005744000100 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA 0x0000005844000402 */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* GPP_C17 I2C0_SCL 0x0000005944000602 */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# 0x0000005e44000500 */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# 0x0000005f44000502 */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO 0x0000006144000102 */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO 0x0000006244800102 */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO 0x0000006344000201 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO 0x0000006784000102 */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO 0x0000006884000100 */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 0x0000007144000700 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 0x0000007244000700 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 0x0000007344000700 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 0x0000007444000700 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO 0x0000007544000300 */ PAD_NC(GPP_D21, NONE), +/* GPP_D22 GPIO 0x0000007644000300 */ PAD_NC(GPP_D22, NONE), +/* GPP_G1 GPIO 0x0000006d44000300 */ PAD_NC(GPP_G1, NONE), +/* GPP_G2 GPIO 0x0000006e44000300 */ PAD_NC(GPP_G2, NONE), +/* GPP_G3 GPIO 0x0000006f40880102 */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* I2S1_SFRM GPIO 0x0000000040000300 */ PAD_NC(I2S1_SFRM, NONE), +/* I2S1_TXD GPIO 0x0000000040000300 */ PAD_NC(I2S1_TXD, NONE), +/* GPD0 BATLOW# 0x0000006044000702 */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT 0x00003c6144000502 */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO 0x0000006704000200 */ PAD_NC(GPD7, DN_20K), /* unused, formerly USB always on */ +/* GPD9 GPIO 0x0000006904000200 */ PAD_CFG_GPO(GPD9, 0, PWROK), +/* GPD11 GPIO 0x0000006b04000200 */ PAD_CFG_GPO(GPD11, 0, PWROK), +/* GPP_K0 GPIO 0x0000001884000102 */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO 0x0000001984000100 */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO 0x0000001a84000100 */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO 0x0000001b84000102 */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO 0x0000001c44000300 */ PAD_NC(GPP_K4, NONE), +/* GPP_K5 GPIO 0x0000001d44000300 */ PAD_NC(GPP_K5, NONE), +/* GPP_K8 GPIO 0x0000002044000300 */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO 0x0000002144000300 */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO 0x0000002244000300 */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO 0x0000002344000300 */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO 0x0000002c84000201 */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO 0x0000002d44000300 */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO 0x0000004844000300 */ PAD_NC(GPP_H0, NONE), +/* GPP_H2 GPIO 0x0000004a44000300 */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO 0x0000004b44000300 */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO 0x0000005244000300 */ PAD_NC(GPP_H10, NONE), +/* GPP_H15 GPIO 0x0000005744000300 */ PAD_NC(GPP_H15, NONE), +/* GPP_H17 GPIO 0x0000005944000300 */ PAD_NC(GPP_H17, NONE), +/* GPP_E0 SATAXPCIE0 0x0000001844800502 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO 0x0000001944000300 */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO 0x0000001a44000300 */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 0x0000001c44000600 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO 0x0000301d44800102 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO 0x0000001e44800102 */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# 0x0000002044000700 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# 0x0000302144000702 */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# 0x0000302244000702 */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# 0x0000302344000702 */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO 0x0000002484000200 */ PAD_CFG_GPO(GPP_E12, 0, PLTRST), +/* GPP_F1 GPIO 0x0000003144000300 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO 0x0000003244000300 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO 0x0000003344000300 */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO 0x0000003444000300 */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO 0x0000003544000300 */ PAD_NC(GPP_F5, NONE), +/* GPP_F6 SATA_DEVSLP4 0x0000003644000700 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO 0x0000003844000300 */ PAD_NC(GPP_F8, NONE), +/* GPP_F9 GPIO 0x0000003944000300 */ PAD_NC(GPP_F9, NONE), +/* GPP_F10 GPIO 0x0000003a84000100 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO 0x0000003d82800102 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO 0x0000003e44000300 */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# 0x0000303f44000702 */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# 0x0000304044000702 */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# 0x0000304144000702 */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO 0x0000004240880102 */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN 0x0000004344000700 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN 0x0000004444000700 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL 0x0000004544000700 */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 GPIO 0x0000004644000300 */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 GPIO 0x0000004744000300 */ PAD_NC(GPP_F23, NONE), +/* GPP_I0 DDPB_HPD0 0x00003c0040000700 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 0x00003c0040000700 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 0x00003c0040000700 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 0x0000000040000700 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD 0x0000000040000700 */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA 0x0000000040000702 */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK 0x0000000040000700 */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA 0x0000000040000700 */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK 0x0000100040000700 */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA 0x0000100040000700 */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a 0x0000003044000700 */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a 0x0000003144000700 */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT 0x0000003244000702 */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 GPIO 0x0000003344000300 */ PAD_NC(GPP_J5, NONE), +/* GPP_J6 CNV_RGI_DT 0x0000003444000700 */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP 0x0000003544000700 */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD 0x0000003644000602 */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD 0x0000003744000702 */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a 0x0000003844000602 */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/siemens/chili/variants/chili/hda_verb.c b/src/mainboard/siemens/chili/variants/chili/hda_verb.c new file mode 100644 index 0000000000..f0e403acd0 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/hda_verb.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0xffffffff, /* Subsystem ID */ + 12, /* Number of entries below */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x110a4097), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x14, /* 0x14 Speaker OUT */ + (AZALIA_PINCFG_PORT_FIXED << 30) | + (AZALIA_PINCFG_LOCATION_INTERNAL << 24) | + (AZALIA_PINCFG_DEVICE_SPEAKER << 20) | + (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16) | + (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | + (1 << 4) | 0 + ), + AZALIA_PIN_CFG(0, 0x21, /* 0x21 Headphone OUT */ + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_FRONT << 24) | + (AZALIA_PINCFG_DEVICE_HP_OUT << 20) | + (AZALIA_PINCFG_CONN_COMBINATION << 16) | + (AZALIA_PINCFG_COLOR_BLACK << 12) | + (2 << 4) | 0 + ), + AZALIA_PIN_CFG(0, 0x19, /* 0x19 MIC2 */ + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_FRONT << 24) | + (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) | + (AZALIA_PINCFG_CONN_COMBINATION << 16) | + (AZALIA_PINCFG_COLOR_BLACK << 12) | + (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) | + (3 << 4) | 0 + ), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* 0x12 Digital MIC */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(1)), /* 0x17 Mono OUT */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(2)), /* 0x18 MIC1 */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(3)), /* 0x1a LINE1 */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(4)), /* 0x1b LINE2 */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(5)), /* 0x1d PCBEEP */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(6)), /* 0x1e S/PDIF OUT */ + + /* HDMI/DP audio codec */ + 0x8086280b, /* Codec Vendor / Device ID: Intel Kabylake HDMI */ + 0xffffffff, /* Subsystem ID */ + 5, /* Number of entries below */ + + /* Enable 2nd & 3rd pin widgets first */ + 0x20878101, + 0x20878101, + 0x20878101, + 0x20878101, + AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_CFG_NC(1)), + AZALIA_PIN_CFG(2, 0x07, + (AZALIA_PINCFG_PORT_JACK << 30) | + (AZALIA_PINCFG_LOCATION_REAR_PANEL << 24) | + (AZALIA_PINCFG_DEVICE_DIGITAL_OUT << 20) | + (AZALIA_PINCFG_CONN_OTHER_DIGITAL << 16) | + (1 << 4) | 0 + ), + /* Disable 2nd & 3rd pin widgets again */ + 0x20878100, + 0x20878100, + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c new file mode 100644 index 0000000000..ebffc8d39d --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "../../variant.h" + +void variant_romstage_params(FSPM_UPD *const mupd) +{ + uint8_t eth_enable = 1; + + get_option(ð_enable, "ethernet1"); + if (!eth_enable) { + printk(BIOS_DEBUG, "Disabling ethernet1.\n"); + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 5); + } +} From 188f1bd5b84e22763680f2bb9b1908835537b3d7 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 16 Oct 2020 11:29:06 -0600 Subject: [PATCH 120/354] soc/amd/picasso: Fix typo in SMU argument base Correct the base address. This should have no noticeable effect, as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The argument writes were not getting to any target. BUG=b:171037051 TEST=Run SST on morphius BRANCH=Zork Signed-off-by: Marshall Dawson Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/picasso/include/soc/smu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index 128f4c4ed7..eb7573c52b 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -11,7 +11,7 @@ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 -#define REG_ADDR_MESG_ARGS_BASE 0x0b10998 +#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 /* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6 From 5dbe45e0f5608794e03634aed28530ddb2ab9ac5 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Aug 2020 13:04:51 -0600 Subject: [PATCH 121/354] soc/amd/picasso: Skip SmmInfo to PSP on S3 resume The PSP does not accept the SmmInfo command during a resume so remove the call. BUG=b:163017485 TEST=Run SST on trembyle, verify error message goes away BRANCH=Zork Signed-off-by: Marshall Dawson Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/smi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index 125dde601c..58221513a1 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -4,6 +4,7 @@ * Utilities for SMM setup */ +#include #include #include #include @@ -19,5 +20,6 @@ void global_smi_enable(void) reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); - outb(APM_CNT_SMMINFO, APM_CNT); + if (!acpi_is_wakeup_s3()) + outb(APM_CNT_SMMINFO, APM_CNT); } From 70d73a85bf96b9c91c8878cef721d513b41fadc4 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 18 Oct 2020 20:15:21 +0000 Subject: [PATCH 122/354] libpayload/storage: Enable all AHCI controllers by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the list of tested controllers is not actively maintained, enable all AHCI controllers by default. Also, improve the readability of its help text by adding a comma to it. Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner --- payloads/libpayload/drivers/storage/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index fea52c8903..8dffd3b230 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -45,7 +45,7 @@ config STORAGE_AHCI config STORAGE_AHCI_ONLY_TESTED bool "Only enable tested controllers" depends on STORAGE_AHCI - default y + default n help - If this option is selected only AHCI controllers which are known + If this option is selected, only AHCI controllers which are known to work will be used. From e92c84050b7841c1ccb9303b1c01ace9586812e3 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 17 Oct 2020 21:06:48 +0000 Subject: [PATCH 123/354] libpayload/storage: Enable STORAGE_64BIT_LBA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB capacity. Therefore, enable the 64-bit support. Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michael Niewöhner --- payloads/libpayload/drivers/storage/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig index 8dffd3b230..0c2cc8a665 100644 --- a/payloads/libpayload/drivers/storage/Kconfig +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -12,7 +12,7 @@ config STORAGE config STORAGE_64BIT_LBA bool "Use 64-bit integers to address sectors" depends on STORAGE - default n + default y help If this is selected, sectors will be addressed by an 64-bit integer. Select this to support LBA-48 for ATA drives. From 8b4a9380b54220a352cbc5eb55f600f5dce8475b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 13:00:27 +0200 Subject: [PATCH 124/354] soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/cpu/intel/common/common.h | 6 ++++++ src/cpu/intel/common/common_init.c | 20 ++++++++++++++++++++ src/include/cpu/intel/msr.h | 11 +++++++++++ 3 files changed, 37 insertions(+) create mode 100644 src/include/cpu/intel/msr.h diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index df14668095..aaeca1da10 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -27,4 +27,10 @@ bool intel_ht_supported(void); */ bool intel_ht_sibling(void); +/* + * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling + * as suggested in Intel document 325384-070US. + */ +void set_aesni_lock(void); + #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 3e5b578d22..e532c975cb 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "common.h" @@ -264,3 +265,22 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) config->regs[CPPC_AUTO_SELECT] = msr; } } + +/* + * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling + * as suggested in Intel document 325384-070US. + */ +void set_aesni_lock(void) +{ + msr_t msr; + + /* Only run once per core as specified in the MSR datasheet */ + if (intel_ht_sibling()) + return; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h new file mode 100644 index 0000000000..73dd32091b --- /dev/null +++ b/src/include/cpu/intel/msr.h @@ -0,0 +1,11 @@ +#ifndef CPU_INTEL_MSR_H +#define CPU_INTEL_MSR_H + +/* + * Common MSRs for Intel CPUs + */ + +#define MSR_FEATURE_CONFIG 0x13c +#define AESNI_LOCK_BIT 0 + +#endif /* CPU_INTEL_MSR_H */ From 13b9149bab28c24798507b152c4d212dd9512175 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 15:56:21 +0200 Subject: [PATCH 125/354] cpu/intel/common: rework AES-NI locking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify the AES-NI code by using msr_set and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/cpu/intel/common/common.h | 4 ++-- src/cpu/intel/common/common_init.c | 12 ++++-------- src/include/cpu/intel/msr.h | 2 +- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index aaeca1da10..57a51e5538 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -28,8 +28,8 @@ bool intel_ht_supported(void); bool intel_ht_sibling(void); /* - * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling - * as suggested in Intel document 325384-070US. + * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes + * to the enablement state as suggested in Intel document 325384-070US. */ void set_aesni_lock(void); diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index e532c975cb..f189c598ac 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -266,10 +266,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) } } -/* - * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling - * as suggested in Intel document 325384-070US. - */ void set_aesni_lock(void) { msr_t msr; @@ -279,8 +275,8 @@ void set_aesni_lock(void) return; msr = rdmsr(MSR_FEATURE_CONFIG); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; - wrmsr(MSR_FEATURE_CONFIG, msr); - } + if (msr.lo & AESNI_LOCK) + return; + + msr_set(MSR_FEATURE_CONFIG, AESNI_LOCK); } diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 73dd32091b..0d11b5eece 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -6,6 +6,6 @@ */ #define MSR_FEATURE_CONFIG 0x13c -#define AESNI_LOCK_BIT 0 +#define AESNI_LOCK (1 << 0) #endif /* CPU_INTEL_MSR_H */ From 469a99b5c8886e2855ebf8f714f08501c55def77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 16:15:04 +0200 Subject: [PATCH 126/354] cpu/intel/common: only lock AES-NI when supported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a check to only lock AES-NI when AES is supported. Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/cpu/intel/common/common_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index f189c598ac..fc5360d001 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -270,6 +270,9 @@ void set_aesni_lock(void) { msr_t msr; + if (cpu_get_feature_flags_ecx() & CPUID_AES) + return; + /* Only run once per core as specified in the MSR datasheet */ if (intel_ht_sibling()) return; From 2ffd2198863fe8e971b56fc146339cc4dbd56295 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 16:59:13 +0200 Subject: [PATCH 127/354] cpu/intel/common: add a Kconfig to control AES-NI locking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a Kconfig to be able to disable locking of AES-NI for e.g debugging, testing, ... Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/cpu/intel/common/Kconfig | 8 ++++++++ src/cpu/intel/common/common_init.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 064e67b6db..01f2721b59 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -19,6 +19,14 @@ config SET_IA32_FC_LOCK_BIT However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V. +config SET_MSR_AESNI_LOCK_BIT + bool "Lock the AES-NI enablement state" + default y + help + This config sets the AES-NI lock bit, if available, to prevent any + further change of AES-NI enablement. This may be disabled for e.g. + testing or debugging. + config CPU_INTEL_COMMON_TIMEBASE bool diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index fc5360d001..45680146ad 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -270,6 +270,9 @@ void set_aesni_lock(void) { msr_t msr; + if (!CONFIG(SET_MSR_AESNI_LOCK_BIT)) + return; + if (cpu_get_feature_flags_ecx() & CPUID_AES) return; From 5611cfd55f6ad558a000a02e84e65af42316edd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 13:04:02 +0200 Subject: [PATCH 128/354] soc/intel/cnl: lock AES-NI feature if selected MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of AES-NI enablement as precaution, as suggested in Intel document 325384-070US. Locking is enabled by default (as already done in SKL and Arrandale) and may be disabled by the newly introduced Kconfig in the parent change. Tested by checking the MSR. Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 3d97c56404..ddedb3fed2 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -199,6 +199,8 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); + set_aesni_lock(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); From 79a812e5366586eaacb36b09d592adfaace3dafc Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Mon, 21 Sep 2020 20:25:54 +0800 Subject: [PATCH 129/354] ec/google/chromeec: Add wrappers to get/set the voltage Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/ec/google/chromeec/ec.c | 47 +++++++++++++++++++++++++++++++++++++ src/ec/google/chromeec/ec.h | 18 ++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 82de088401..39cf89512f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1616,3 +1616,50 @@ int google_chromeec_ap_reset(void) return 0; } + +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv) +{ + struct ec_params_regulator_set_voltage params = { + .index = index, + .min_mv = min_mv, + .max_mv = max_mv, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_SET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) +{ + struct ec_params_regulator_get_voltage params = { + .index = index, + }; + struct ec_response_regulator_get_voltage resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_GET_VOLTAGE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *voltage_mv = resp.voltage_mv; + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ad3768c025..c2ceff831f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,6 +353,24 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); */ int google_chromeec_ap_reset(void); +/** + * Set voltage for the voltage regulator within the range specified. + * @param index Regulator ID + * @param min_mv Minimum voltage + * @param max_mv Maximum voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, + uint32_t max_mv); + +/** + * Get the currently configured voltage for the voltage regulator. + * @param index Regulator ID + * @param *voltage_mv If successful, voltage_mv is filled with current voltage + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT From c90a9e68b77caf5c909b4b10120374d50dd7ce66 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 22 Jun 2020 19:52:45 +0800 Subject: [PATCH 130/354] soc/mediatek/mt8192: Do dram fast calibration Load params from flash and use those params to do dram fast calibration. Signed-off-by: Huayang Duan Signed-off-by: Yidi Lin Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/Kconfig | 23 ++++ src/soc/mediatek/mt8192/Makefile.inc | 2 + src/soc/mediatek/mt8192/emi.c | 4 + .../mediatek/mt8192/include/soc/dramc_param.h | 2 +- src/soc/mediatek/mt8192/include/soc/emi.h | 5 +- src/soc/mediatek/mt8192/memory.c | 121 ++++++++++++++++++ 6 files changed, 155 insertions(+), 2 deletions(-) create mode 100644 src/soc/mediatek/mt8192/memory.c diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 24122048b6..1d1cf7b79e 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -15,4 +15,27 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config DEBUG_DRAM + bool "Output verbose DRAM related debug messages" + default y + help + This option enables additional DRAM related debug messages. + +config MT8192_DRAM_EMCP + bool + default y + help + The eMCP platform should select this option to run at different DRAM + frequencies. + +config MT8192_DRAM_DVFS + bool + default n + help + This options enables DRAM calibration with multiple frequencies (low, + medium and high) for DVFS feature. + +config MEMORY_TEST + bool + default y endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 533eae294d..b047ce9394 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -20,6 +20,8 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/mmu_operations.c +romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 7b1d3c2113..9e48918f66 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -8,3 +8,7 @@ size_t sdram_size(void) return dram_size; } + +void mt_set_emi(const struct dramc_data *dparam) +{ +} diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h index 89ff628bde..b4e982fdff 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -8,7 +8,7 @@ #include enum { - DRAMC_PARAM_HEADER_VERSION = 2, + DRAMC_PARAM_HEADER_VERSION = 3, }; enum DRAMC_PARAM_STATUS_CODES { diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h index 0348573bd0..02a90be789 100644 --- a/src/soc/mediatek/mt8192/include/soc/emi.h +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -3,8 +3,11 @@ #ifndef SOC_MEDIATEK_MT8192_EMI_H #define SOC_MEDIATEK_MT8192_EMI_H -#include +#include size_t sdram_size(void); +void mt_set_emi(const struct dramc_data *dparam); +void mt_mem_init(struct dramc_param_ops *dparam_ops); +int complex_mem_test(u8 *start, unsigned int len); #endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c new file mode 100644 index 0000000000..b5363b0712 --- /dev/null +++ b/src/soc/mediatek/mt8192/memory.c @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static int mt_mem_test(const struct dramc_data *dparam) +{ + if (CONFIG(MEMORY_TEST)) { + u8 *addr = _dram; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { + int i = complex_mem_test(addr, 0x2000); + + printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s\n", + (i == 0) ? "pass" : "fail"); + + if (i != 0) { + printk(BIOS_ERR, "DRAM memory test failed\n"); + return -1; + } + + addr += ddr_info->rank_size[rank]; + } + } + + return 0; +} + +static u32 compute_checksum(const struct dramc_param *dparam) +{ + return (u32)compute_ip_checksum(&dparam->dramc_datas, + sizeof(dparam->dramc_datas)); +} + +static int dram_run_fast_calibration(const struct dramc_param *dparam) +{ + if (!is_valid_dramc_param(dparam)) { + printk(BIOS_WARNING, "Invalid DRAM calibration data from flash\n"); + dump_param_header((void *)dparam); + return -1; + } + + const u32 checksum = compute_checksum(dparam); + if (dparam->header.checksum != checksum) { + printk(BIOS_ERR, + "Invalid DRAM calibration checksum from flash " + "(expected: %#x, saved: %#x)\n", + checksum, dparam->header.checksum); + return DRAMC_ERR_INVALID_CHECKSUM; + } + + const u16 config = CONFIG(MT8192_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; + if (dparam->dramc_datas.ddr_info.config_dvfs != config) { + printk(BIOS_WARNING, + "Incompatible config for calibration data from flash " + "(expected: %#x, saved: %#x)\n", + config, dparam->dramc_datas.ddr_info.config_dvfs); + return -1; + } + + printk(BIOS_INFO, "DRAM calibration data valid pass\n"); + mt_set_emi(&dparam->dramc_datas); + if (mt_mem_test(&dparam->dramc_datas) == 0) + return 0; + + return DRAMC_ERR_FAST_CALIBRATION; +} + +static void mem_init_set_default_config(struct dramc_param *dparam, + u32 ddr_geometry) +{ + memset(dparam, 0, sizeof(*dparam)); + + if (CONFIG(MT8192_DRAM_EMCP)) + dparam->dramc_datas.ddr_info.ddr_type = DDR_TYPE_EMCP; + + if (CONFIG(MT8192_DRAM_DVFS)) + dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS; + dparam->dramc_datas.ddr_info.ddr_geometry = ddr_geometry; + + printk(BIOS_INFO, "DRAM-K: ddr_type: %d, config_dvfs: %d, ddr_geometry: %d\n", + dparam->dramc_datas.ddr_info.ddr_type, + dparam->dramc_datas.ddr_info.config_dvfs, + dparam->dramc_datas.ddr_info.ddr_geometry); +} + +static void mt_mem_init_run(struct dramc_param_ops *dparam_ops, u32 ddr_geometry) +{ + struct dramc_param *dparam = dparam_ops->param; + + /* Load calibration params from flash and run fast calibration */ + mem_init_set_default_config(dparam, ddr_geometry); + if (dparam_ops->read_from_flash(dparam)) { + printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); + if (dram_run_fast_calibration(dparam) != 0) { + printk(BIOS_ERR, "Failed to run fast calibration\n"); + + /* Erase flash data after fast calibration failed */ + memset(dparam, 0xa5, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } else { + printk(BIOS_INFO, "Fast calibration passed\n"); + return; + } + } else { + printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); + } +} + +void mt_mem_init(struct dramc_param_ops *dparam_ops) +{ + const struct sdram_info *sdram_param = get_sdram_config(); + + mt_mem_init_run(dparam_ops, sdram_param->ddr_geometry); +} From 075ad63a4fd344ed213f24aad0d810a9bd1f48e3 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Fri, 3 Jul 2020 10:18:58 +0800 Subject: [PATCH 131/354] mb/google/asurada: Init dram in romstage Signed-off-by: Huayang Duan Signed-off-by: Yidi Lin Change-Id: Ied350570a695cca1424a6562e41120bcaf467797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568 Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/asurada/Makefile.inc | 1 + src/mainboard/google/asurada/romstage.c | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 src/mainboard/google/asurada/romstage.c diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 8395e4a35b..c74253994c 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -8,6 +8,7 @@ verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += memlayout.ld diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c new file mode 100644 index 0000000000..a0e0818e01 --- /dev/null +++ b/src/mainboard/google/asurada/romstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* This must be defined in chromeos.fmd in same name and size. */ +#define CALIBRATION_REGION "RW_DDR_TRAINING" +#define CALIBRATION_REGION_SIZE 0x2000 + +_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, + "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); + +static bool read_calibration_data_from_flash(struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "read data from flash, ret=%#zx, length=%#zx\n", ret, length); + + return ret == length; +} + +static bool write_calibration_data_to_flash(const struct dramc_param *dparam) +{ + const size_t length = sizeof(*dparam); + size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length); + printk(BIOS_DEBUG, "write data from flash, ret=%#zx, length=%#zx\n", ret, length); + + return ret == length; +} + +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dramc_parameter; + +static struct dramc_param_ops dparam_ops = { + .param = &dramc_parameter, + .read_from_flash = &read_calibration_data_from_flash, + .write_to_flash = &write_calibration_data_to_flash, +}; + +void platform_romstage_main(void) +{ + mt_mem_init(&dparam_ops); + mtk_mmu_after_dram(); +} From 14ee0f94f3881dd281fb80483446eb016b8ee18c Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Thu, 3 Sep 2020 17:58:44 +0800 Subject: [PATCH 132/354] mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- .../x11-lga1151-series/x11ssh-f/x11ssh-f.md | 103 ++++++++ .../supermicro/x11-lga1151-series/Kconfig | 3 + .../x11-lga1151-series/Kconfig.name | 4 + .../variants/x11ssh-f/board_info.txt | 7 + .../variants/x11ssh-f/include/variant/gpio.h | 242 ++++++++++++++++++ .../variants/x11ssh-f/overridetree.cb | 129 ++++++++++ 6 files changed, 488 insertions(+) create mode 100644 Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md new file mode 100644 index 0000000000..f009bbe2ae --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md @@ -0,0 +1,103 @@ +# Supermicro X11SSH-F + +This section details how to run coreboot on the [Supermicro X11SSH-F]. + +## Flashing coreboot + +The board can be flashed externally. [STM32-based programmers] worked. + +The flash IC "W25Q128.V" (detected by flashrom) can be found near PCH PCIe Slot 4. It is sometime +socketed, and covered by a sticker, hindering the observation of its precise model. + +It can be programmed in-system with a clip like pomona 5250. + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. + +## IGD + +If an IGD is integrated with CPU, it will be enabled on this board. Though there is no video output +for it (The onboard VGA port is connected to BMC), it is said to be capable of being used for compute +tasks, or for offloading graphics rendering via "muxless" [vga_witcheroo]. + +## Tested and working + +- SeaBIOS payload to boot Kali Linux live USB +- ECC ram (Linux' ie31200 driver works) +- Integrated graphics device available without output +- USB ports +- Ethernet +- SATA ports +- RS232 external +- PCIe slots +- BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header + +## Known issues + +- See general issue section +- S3 resume not working (vendor and coreboot) +- SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled) + +## ToDo + +- Fix known issues +- Testing other payloads + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 1x 3.0 x4 (in x8) | +| | 1x 3.0 x2 (in M.2 slot with key M) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port (connector may absent) | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Supermicro X11SSH-F] +- [Board manual] + +[Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[IPMI]: ../../../../drivers/ipmi_kcs.md +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[STM32-based programmers]: https://github.com/dword1511/stm32-vserprog +[vga_switcheroo]: https://01.org/linuxgraphics/gfx-docs/drm/gpu/vga-switcheroo.html diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index a446835a75..c4df48489d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -25,6 +25,7 @@ config MAINBOARD_PART_NUMBER string default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F + default "X11SSH-F" if BOARD_SUPERMICRO_X11SSH_F config MAINBOARD_DIR string @@ -34,6 +35,7 @@ config VARIANT_DIR string default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F + default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F config OVERRIDE_DEVICETREE string @@ -89,5 +91,6 @@ config SUPERMICRO_BOARDID string default "0896" if BOARD_SUPERMICRO_X11SSM_F default "089C" if BOARD_SUPERMICRO_X11SSH_TF + default "0884" if BOARD_SUPERMICRO_X11SSH_F endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name index 7b2eaaffcb..7cb19aea90 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SUPERMICRO_X11SSH_TF config BOARD_SUPERMICRO_X11SSM_F bool "X11SSM-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES + +config BOARD_SUPERMICRO_X11SSH_F + bool "X11SSH-F" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt new file mode 100644 index 0000000000..bf0cd992bc --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SSH-F +Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h new file mode 100644 index 0000000000..93e0574409 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _GPIO_X11SSH_F_H +#define _GPIO_X11SSH_F_H + +#include +#include + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_NC(GPP_F9, NONE), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H4, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +#endif /* _GPIO_X11SSH_F_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb new file mode 100644 index 0000000000..c3f4bf1e6f --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -0,0 +1,129 @@ +chip soc/intel/skylake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + + # Additional FSP Configuration + # This board has an IGD with no output. + register "PrimaryDisplay" = "Display_Auto" + + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device pci 01.0 on + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" + end # CPU PCIE Slot (JPCIE3) + device pci 01.1 on # CPU PCIE Slot (JPCIE2) + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" + end + device pci 02.0 on end # Integrated Graphics Device (No Output) + device pci 1c.0 on # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.1 on # PCI Express Port 2 + register "PcieRpEnable[1]" = "1" + device pci 00.0 on end # GbE + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" + end + device pci 1c.6 on # PCI Express Port 7 + register "PcieRpEnable[6]" = "1" + device pci 00.0 on # Aspeed PCI Bridge + device pci 00.0 on end # Aspeed 2400 VGA + end + end + device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + register "PcieRpEnable[8]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" + end + device pci 1f.0 on # LPC Interface + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + drq 0xf0 = 0x00 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + drq 0xf0 = 0x00 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # KBC + device pnp 2e.7 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 + device pnp 2e.d on # iLPC2AHB + irq 0x70 = 0x00 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + end + end +end From dbe8415245ebf31336b11c31cf8dcbb247e33384 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 15 Oct 2020 20:57:17 +0200 Subject: [PATCH 133/354] mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I often find myself having to increase the CBFS size so that TianoCore fits. Raise the default CBFS size to 2 MiB to alleviate this issue. Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488 Reviewed-by: Arthur Heymans Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/asrock/b85m_pro4/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index 844604afc8..f55cf09423 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 +config CBFS_SIZE + hex + default 0x200000 + config MAINBOARD_DIR string default "asrock/b85m_pro4" From 3704b6d4abda30756d765211ea534c3c4a7d4323 Mon Sep 17 00:00:00 2001 From: "alec.wang" Date: Tue, 29 Sep 2020 11:10:28 +0800 Subject: [PATCH 134/354] mb/google/dedede: add PEN for Boten Update devicetree of boten that enable stylus BUG=b:160752604 BRANCH=NONE TEST=build bios and verify function for boten Signed-off-by: alec.wang Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Jamie Chen Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/Kconfig | 1 + src/mainboard/google/dedede/variants/boten/gpio.c | 2 ++ .../google/dedede/variants/boten/overridetree.cb | 14 +++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 377702da45..597516cd88 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 05a567f65c..f889c7fd69 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), /* C19 : AP_I2C_EMR_SCL */ diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 2ba6d9d665..fa6cf226d7 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/jasperlake #| | before memory is up | #| I2C0 | Trackpad | #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | + #| I2C2 | Touchscreen, Stylus | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -107,6 +107,18 @@ chip soc/intel/jasperlake end end # I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_C12)" + register "key.wake_gpe" = "GPE0_DW1_12" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" From e26e9b556deb86564b5f1cfe70e2095a03c964dc Mon Sep 17 00:00:00 2001 From: "alec.wang" Date: Tue, 13 Oct 2020 18:16:12 +0800 Subject: [PATCH 135/354] mb/google/dedede: Add P-sensor for Boten Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: alec.wang Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Jamie Chen Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/boten/overridetree.cb | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index fa6cf226d7..4ec64579c2 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -12,6 +12,7 @@ chip soc/intel/jasperlake #| I2C1 | Digitizer | #| I2C2 | Touchscreen, Stylus | #| I2C4 | Audio | + #| I2C5 | P-Sensor | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -30,6 +31,9 @@ chip soc/intel/jasperlake .i2c[4] = { .speed = I2C_SPEED_FAST, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }" # USB Port Configuration @@ -161,7 +165,16 @@ chip soc/intel/jasperlake register "uid" = "1" device i2c 29 on end end - end + end # I2C 4 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + device i2c 28 on end + end + end # I2C 5 device pci 1f.3 on end # Intel HDA end end From 77f340a707a868d56d8348cd9ab03308f4902bd9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 18:39:04 +0200 Subject: [PATCH 136/354] sb/intel/ibexpeak: Align to coreboot's coding style Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/southbridge/intel/ibexpeak/early_usb.c | 9 +- src/southbridge/intel/ibexpeak/lpc.c | 149 ++++++++++---------- src/southbridge/intel/ibexpeak/madt.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 13 +- src/southbridge/intel/ibexpeak/pch.c | 2 +- src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 7 +- 7 files changed, 92 insertions(+), 92 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c index 8957bfe404..e76ef7e8a1 100644 --- a/src/southbridge/intel/ibexpeak/early_usb.c +++ b/src/southbridge/intel/ibexpeak/early_usb.c @@ -35,21 +35,24 @@ void early_usb_init(const struct southbridge_usb_port *portmap) RCBA32(0x3598) = 0; reg32 = 0; - for (i = 0; i < TOTAL_USB_PORTS; i++) + for (i = 0; i < TOTAL_USB_PORTS; i++) { if (!portmap[i].enabled) reg32 |= (1 << i); + } RCBA32(USBPDO) = reg32; reg32 = 0; /* The OC pins of the first 8 USB ports are mapped in USBOCM1 */ - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + } RCBA32(USBOCM1) = reg32; reg32 = 0; /* The OC pins of the remainder 6 USB ports are mapped in USBOCM2 */ - for (i = 8; i < TOTAL_USB_PORTS; i++) + for (i = 8; i < TOTAL_USB_PORTS; i++) { if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + } RCBA32(USBOCM2) = reg32; /* Relock registers. */ diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d4f1925c2a..8269dd9f22 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -89,12 +89,13 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Interrupt 11 is not used by legacy devices and so can always be used for - PCI interrupts. Full legacy IRQ routing is complicated and hard to - get right. Fortunately all modern OS use MSI and so it's not that big of - an issue anyway. Still we have to provide a reasonable default. Using - interrupt 11 for it everywhere is a working default. ACPI-aware OS can - move it to any interrupt and others will just leave them at default. + /* + * Interrupt 11 is not used by legacy devices and so can always be used for + * PCI interrupts. Full legacy IRQ routing is complicated and hard to + * get right. Fortunately all modern OS use MSI and so it's not that big of + * an issue anyway. Still we have to provide a reasonable default. Using + * interrupt 11 for it everywhere is a working default. ACPI-aware OS can + * move it to any interrupt and others will just leave them at default. */ const u8 pirq_routing = 11; @@ -279,87 +280,81 @@ static void mobile5_pm_init(struct device *dev) printk(BIOS_DEBUG, "Mobile 5 PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32 (0x1d44) = 0x00000000; - (void) RCBA32 (0x1d44); - RCBA32 (0x1d48) = 0x00030000; - (void) RCBA32 (0x1d48); - RCBA32 (0x1e80) = 0x000c0801; - (void) RCBA32 (0x1e80); - RCBA32 (0x1e84) = 0x000200f0; - (void) RCBA32 (0x1e84); + RCBA32(0x1d44) = 0x00000000; + (void)RCBA32(0x1d44); + RCBA32(0x1d48) = 0x00030000; + (void)RCBA32(0x1d48); + RCBA32(0x1e80) = 0x000c0801; + (void)RCBA32(0x1e80); + RCBA32(0x1e84) = 0x000200f0; + (void)RCBA32(0x1e84); - const u32 rcba2010[] = - { - /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, - /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 - }; - for (i = 0; i < ARRAY_SIZE(rcba2010); i++) - { - RCBA32 (0x2010 + 4 * i) = rcba2010[i]; - RCBA32 (0x2010 + 4 * i); + const u32 rcba2010[] = { + /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, + /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 + }; + for (i = 0; i < ARRAY_SIZE(rcba2010); i++) { + RCBA32(0x2010 + 4 * i) = rcba2010[i]; + RCBA32(0x2010 + 4 * i); } - RCBA32 (0x2100) = 0x00000000; - (void) RCBA32 (0x2100); - RCBA32 (0x2104) = 0x00000757; - (void) RCBA32 (0x2104); - RCBA32 (0x2108) = 0x00170001; - (void) RCBA32 (0x2108); + RCBA32(0x2100) = 0x00000000; + (void)RCBA32(0x2100); + RCBA32(0x2104) = 0x00000757; + (void)RCBA32(0x2104); + RCBA32(0x2108) = 0x00170001; + (void)RCBA32(0x2108); - RCBA32 (0x211c) = 0x00000000; - (void) RCBA32 (0x211c); - RCBA32 (0x2120) = 0x00010000; - (void) RCBA32 (0x2120); + RCBA32(0x211c) = 0x00000000; + (void)RCBA32(0x211c); + RCBA32(0x2120) = 0x00010000; + (void)RCBA32(0x2120); - RCBA32 (0x21fc) = 0x00000000; - (void) RCBA32 (0x21fc); - RCBA32 (0x2200) = 0x20000044; - (void) RCBA32 (0x2200); - RCBA32 (0x2204) = 0x00000001; - (void) RCBA32 (0x2204); - RCBA32 (0x2208) = 0x00003457; - (void) RCBA32 (0x2208); + RCBA32(0x21fc) = 0x00000000; + (void)RCBA32(0x21fc); + RCBA32(0x2200) = 0x20000044; + (void)RCBA32(0x2200); + RCBA32(0x2204) = 0x00000001; + (void)RCBA32(0x2204); + RCBA32(0x2208) = 0x00003457; + (void)RCBA32(0x2208); - const u32 rcba2210[] = - { - /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, - /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, - /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, - /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, - /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, - /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 - }; + const u32 rcba2210[] = { + /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, + /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, + /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, + /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, + /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 + }; - for (i = 0; i < ARRAY_SIZE(rcba2210); i++) - { - RCBA32 (0x2210 + 4 * i) = rcba2210[i]; - RCBA32 (0x2210 + 4 * i); + for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { + RCBA32(0x2210 + 4 * i) = rcba2210[i]; + RCBA32(0x2210 + 4 * i); } - const u32 rcba2300[] = - { - /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, - /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, - /* 2320: */ 0xcccc0cfc, 0x0fbb0fff - }; + const u32 rcba2300[] = { + /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, + /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, + /* 2320: */ 0xcccc0cfc, 0x0fbb0fff + }; - for (i = 0; i < ARRAY_SIZE(rcba2300); i++) - { - RCBA32 (0x2300 + 4 * i) = rcba2300[i]; - RCBA32 (0x2300 + 4 * i); + for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { + RCBA32(0x2300 + 4 * i) = rcba2300[i]; + RCBA32(0x2300 + 4 * i); } - RCBA32 (0x37fc) = 0x00000000; - (void) RCBA32 (0x37fc); - RCBA32 (0x3dfc) = 0x00000000; - (void) RCBA32 (0x3dfc); - RCBA32 (0x3e7c) = 0xffffffff; - (void) RCBA32 (0x3e7c); - RCBA32 (0x3efc) = 0x00000000; - (void) RCBA32 (0x3efc); - RCBA32 (0x3f00) = 0x0000010b; - (void) RCBA32 (0x3f00); + RCBA32(0x37fc) = 0x00000000; + (void)RCBA32(0x37fc); + RCBA32(0x3dfc) = 0x00000000; + (void)RCBA32(0x3dfc); + RCBA32(0x3e7c) = 0xffffffff; + (void)RCBA32(0x3e7c); + RCBA32(0x3efc) = 0x00000000; + (void)RCBA32(0x3efc); + RCBA32(0x3f00) = 0x0000010b; + (void)RCBA32(0x3f00); } static void enable_hpet(void) @@ -573,7 +568,7 @@ void southbridge_inject_dsdt(const struct device *dev) /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); acpigen_pop_len(); } } @@ -610,7 +605,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, - .write_acpi_tables = acpi_write_hpet, + .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 472f8e9382..0c58f7f92d 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -12,7 +12,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index b355d9dbdb..bff8d24510 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -119,13 +119,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); + write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -261,9 +261,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); return -1; } @@ -298,8 +297,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); return -1; } diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 4d48eba10d..958d1db4af 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -68,7 +68,7 @@ void pch_enable(struct device *dev) u16 reg16; if (!dev->enabled) { - printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ reg16 = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 7c9ac8240d..56da504465 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -17,7 +17,7 @@ static void pch_smbus_init(struct device *dev) /* Enable clock gating */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index cce464be6d..0c5e954c72 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -102,7 +102,7 @@ void southbridge_smi_monitor(void) RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -131,7 +131,10 @@ void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) { + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + } printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); From 944d00b28ccd10985ee93a27139d4810fbe7955e Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Mon, 17 Aug 2020 11:11:48 +0800 Subject: [PATCH 137/354] soc/amd/picasso: Use readelf to find bootblock size and location The Picasso build describes the DRAM region where the PSP places our bootblock. Rather than relying on Kconfig values, make the build more robust by using the actual size and target base address from the boot block's ELF file. Sample output of "readelf -l bootblock.elf" is: ------------------ Elf file type is EXEC (Executable file) Entry point 0x203fff0 There is 1 program header, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000 Section to Segment mapping: Segment Sections... 00 .text .data .bss .reset ------------------ We can extract the information from here. BUG=b:154957411 TEST=Build & boot on mandolin Change-Id: I5a26047726f897c57325387cb304fddbc73f6504 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9757160d19..514b313a6d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -209,12 +209,8 @@ PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) # type = 0x62 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img PSP_ELF_FILE=$(objcbfs)/bootblock.elf -# TODO(b/154957411): Refactor amdfwtool to extract the address and size from -# the elf file. -PSP_BIOSBIN_SIZE=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) -# This address must match the BOOTBLOCK logic in arch/x86/memlayout.ld. -PSP_BIOSBIN_DEST=$(shell printf "%x" $(call int-subtract, $(call int-add, $(CONFIG_X86_RESET_VECTOR) 0x10) $(PSP_BIOSBIN_SIZE))) - +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}') From 7f8767de635cdebe45d45bc68a0c3c2001226682 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 18 Oct 2020 00:45:38 +0200 Subject: [PATCH 138/354] cpu/intel/model_{2065x,206ax}: fix AES-NI locking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped, not package-scoped. Thus, move locking from SMM to core init, where the code gets executed once per core. Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_2065x/finalize.c | 4 ---- src/cpu/intel/model_2065x/model_2065x_init.c | 6 ++++++ src/cpu/intel/model_206ax/finalize.c | 4 ---- src/cpu/intel/model_206ax/model_206ax_init.c | 6 ++++++ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index d19ddf7a34..e1fa968d9c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -16,10 +16,6 @@ void intel_model_2065x_finalize_smm(void) /* Lock C-State MSR */ msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15)); - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - /* Lock TM interrupts - route thermal events to all processors */ msr_set(MSR_MISC_PWR_MGMT, BIT(22)); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index ff4a255dfd..b4a91ea658 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -216,6 +216,12 @@ static void model_2065x_init(struct device *cpu) /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); + if (!intel_ht_sibling()) { + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set(MSR_FEATURE_CONFIG, BIT(0)); + } + /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 98be012746..2298684421 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -12,10 +12,6 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - /* Lock TM interrupts - route thermal events to all processors */ msr_set(MSR_MISC_PWR_MGMT, BIT(22)); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cd828e8199..d23772a23f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -470,6 +470,12 @@ static void model_206ax_init(struct device *cpu) /* Thermal throttle activation offset */ configure_thermal_target(); + if (!intel_ht_sibling()) { + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set(MSR_FEATURE_CONFIG, BIT(0)); + } + /* Enable Direct Cache Access */ configure_dca_cap(); From 059c7910ebc28a0779cf45f7e0830391ee9f1aff Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 19 Oct 2020 16:48:16 +0200 Subject: [PATCH 139/354] 3rdparty/blobs: advance submodule pointer The 3 commits commits from the blob repository this patch pulls in remove executable flags from files in the repo that shouldn't have those flags set: * pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit * Remove execute permission from all binaries * Remove execute permission from plaintext files Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 1aff9c32eb..a59fb6e389 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21 +Subproject commit a59fb6e3892f0629d43769a07ee7f1048a0ae1f8 From d888990cdc6387845c5cbe3d8f073de53483ba86 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 13 Oct 2020 17:01:46 +0000 Subject: [PATCH 140/354] mb/google/volteer/variants/lillipup: add generic SPDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add generic LPDDR4x SPD support for the following three memory parts: • K4U6E3S4AA-MGCR • H9HCNNNBKMMLXR-NEE • MT53E512M32D2NP-046 WT:F BUG=b:170264065 TEST=none Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/volteer/variants/lillipup/memory/Makefile.inc | 5 +++++ .../volteer/variants/lillipup/memory/dram_id.generated.txt | 4 ++++ .../volteer/variants/lillipup/memory/mem_list_variant.txt | 3 +++ 3 files changed, 12 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc new file mode 100644 index 0000000000..b7e69440fd --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt new file mode 100644 index 0000000000..dc87e04ace --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:F 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt new file mode 100644 index 0000000000..d0273dc39b --- /dev/null +++ b/src/mainboard/google/volteer/variants/lillipup/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D2NP-046 WT:F From ec1926aaffa7087d6de8f82ee42678c231ebab48 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 16 Oct 2020 16:54:40 +0800 Subject: [PATCH 141/354] mb/google/volteer/var/terrador: Configure board specific DPTF parameters Configure board specific DPTF parameters for terrador and todor BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/terrador/overridetree.cb | 43 +++++++++++++++++++ .../volteer/variants/todor/overridetree.cb | 43 +++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87ab5..001d5f6835 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -17,6 +17,49 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 1ccdb87ab5..001d5f6835 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -17,6 +17,49 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 3-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 ranges from 9 to 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 9000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 }}" + + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" From 6034b0f184e0fd4063891f24b71ac4dc85751274 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 19 Oct 2020 17:42:59 +0200 Subject: [PATCH 142/354] payloads/coreinfo: Rename pci_scan_bus() Rename pci_scan_bus() since the name is already used in libpayload. Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/coreinfo/pci_module.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 0385e9d73a..ff01770868 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -151,7 +151,7 @@ static int pci_module_redraw(WINDOW *win) return 0; } -static void pci_scan_bus(int bus) +static void ci_pci_scan_bus(int bus) { int slot, func; unsigned int val; @@ -196,7 +196,7 @@ static void pci_scan_bus(int bus) busses = pci_read_config32(dev, REG_PRIMARY_BUS); - pci_scan_bus((busses >> 8) & 0xff); + ci_pci_scan_bus((busses >> 8) & 0xff); } } @@ -240,7 +240,7 @@ static int pci_module_handle(int key) static int pci_module_init(void) { - pci_scan_bus(0); + ci_pci_scan_bus(0); return 0; } From 9e5bc74cc7c2a6ced08163418299cc753b8357f0 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 13 Oct 2020 18:05:03 +0200 Subject: [PATCH 143/354] libpayload/arch/x86: Introduce pacc pointer in sysinfo_t struct Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/arch/x86/sysinfo.c | 5 +++++ payloads/libpayload/include/sysinfo.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c index ffa57bb08f..5dd606746f 100644 --- a/payloads/libpayload/arch/x86/sysinfo.c +++ b/payloads/libpayload/arch/x86/sysinfo.c @@ -78,5 +78,10 @@ int lib_get_sysinfo(void) lib_sysinfo.memrange[1].type = CB_MEM_RAM; } +#if CONFIG(LP_PCI) + pci_init(&lib_sysinfo.pacc); + pci_scan_bus(&lib_sysinfo.pacc); +#endif + return ret; } diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index fe3d3304c4..a3f61e7ffa 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -29,6 +29,7 @@ #ifndef _SYSINFO_H #define _SYSINFO_H +#include #include /* Maximum number of memory range definitions. */ @@ -130,6 +131,10 @@ struct sysinfo_t { /* Pointer to FMAP cache in CBMEM */ uintptr_t fmap_cache; + +#if CONFIG(LP_PCI) + struct pci_access pacc; +#endif }; extern struct sysinfo_t lib_sysinfo; From b4b73d49958184c833844a3a6f6a3777dd469ceb Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 14 Oct 2020 18:44:49 +0200 Subject: [PATCH 144/354] libpayload/storage/ahci: Use pacc pointer to read device class The PCI bus gets already scanned while gathering system information. Therefore, use the pacc pointer from sysinfo_t to read the device class of PCI devices instead of rescanning the bus. Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/drivers/storage/ahci.c | 19 ++----------------- payloads/libpayload/drivers/storage/storage.c | 14 +++++++++++++- payloads/libpayload/include/pci/pci.h | 1 + payloads/libpayload/include/storage/ahci.h | 2 +- 4 files changed, 17 insertions(+), 19 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index ff22b19b71..e54bfbfef0 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -227,7 +227,8 @@ static u32 working_controllers[] = { 0x8086 | 0x5ae3 << 16, /* Apollo Lake */ }; #endif -static void ahci_init_pci(pcidev_t dev) + +void ahci_initialize(pcidev_t dev) { int i; @@ -282,19 +283,3 @@ static void ahci_init_pci(pcidev_t dev) ahci_port_probe(ctrl, &ports[i], i + 1); } } - -void ahci_initialize(void) -{ - int bus, dev, func; - - for (bus = 0; bus < 256; ++bus) { - for (dev = 0; dev < 32; ++dev) { - const u16 class = - pci_read_config16(PCI_DEV(bus, dev, 0), 0xa); - if (class != 0xffff) { - for (func = 0; func < 8; ++func) - ahci_init_pci(PCI_DEV(bus, dev, func)); - } - } - } -} diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index 24b9024a93..addf8d2bd3 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -27,6 +27,7 @@ */ #include +#include #if CONFIG(LP_STORAGE_AHCI) # include #endif @@ -108,7 +109,18 @@ ssize_t storage_read_blocks512(const size_t dev_num, */ void storage_initialize(void) { +#if CONFIG(LP_PCI) + struct pci_dev *dev; + for (dev = lib_sysinfo.pacc.devices; dev; dev = dev->next) { + switch (dev->device_class) { #if CONFIG(LP_STORAGE_AHCI) - ahci_initialize(); + case PCI_CLASS_STORAGE_AHCI: + ahci_initialize(PCI_DEV(dev->bus, dev->dev, dev->func)); + break; +#endif + default: + break; + } + } #endif } diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 7ec9491d95..5e21060130 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -66,6 +66,7 @@ #define PCI_ROM_ADDRESS1 0x38 // on bridges #define PCI_ROM_ADDRESS_MASK ~0x7ff +#define PCI_CLASS_STORAGE_AHCI 0x0106 #define PCI_CLASS_MEMORY_OTHER 0x0580 #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 0aa032297a..28436249f8 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -29,6 +29,6 @@ #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(void); +void ahci_initialize(pcidev_t dev); #endif From 320ad9351bb78c09ffd15fccd1ecc3089f068ab6 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 14 Oct 2020 15:07:51 -0700 Subject: [PATCH 145/354] cpu/x86/mtrr: add support for address space higher than 16TiB On DeltaLake server, there are following entry in MTRR address space: 0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0 In this case, the base address (with 4k granularity) cannot be held in uint32_t. This results incorrect MTRR register setup. As the consequence UEFI forum FWTS reports following critical error: Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached. Change appropriate variables' data type from uint32_t to uint64_t. Add fls64() to find least significant bit set in a 64-bit word. Add fms64() to find most significant bit set in a 64-bit word. Signed-off-by: Jonathan Zhang Signed-off-by: Marc Jones Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/x86/mtrr/mtrr.c | 56 ++++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 77525a7907..284a1139ab 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -104,9 +104,7 @@ static void enable_var_mtrr(unsigned char deftype) #define MTRR_VERBOSE_LEVEL BIOS_NEVER -/* MTRRs are at a 4KiB granularity. Therefore all address calculations can - * be done with 32-bit numbers. This allows for the MTRR code to handle - * up to 2^44 bytes (16 TiB) of address space. */ +/* MTRRs are at a 4KiB granularity. */ #define RANGE_SHIFT 12 #define ADDR_SHIFT_TO_RANGE_SHIFT(x) \ (((x) > RANGE_SHIFT) ? ((x) - RANGE_SHIFT) : RANGE_SHIFT) @@ -115,18 +113,18 @@ static void enable_var_mtrr(unsigned char deftype) #define NUM_FIXED_MTRRS (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR) /* Helpful constants. */ -#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20) -#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) +#define RANGE_1MB PHYS_TO_RANGE_ADDR(1ULL << 20) +#define RANGE_4GB (1ULL << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) #define MTRR_ALGO_SHIFT (8) #define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1) -static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_base_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_base(r)); } -static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) +static inline uint64_t range_entry_end_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } @@ -402,7 +400,7 @@ static void clear_var_mtrr(int index) } static void prep_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { struct var_mtrr_regs *regs; resource_t rbase; @@ -444,16 +442,43 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state, regs->mask.hi = rsize >> 32; } +/* + * fls64: find least significant bit set in a 64-bit word + * As samples, fls64(0x0) = 64; fls64(0x4400) = 10; + * fls64(0x40400000000) = 34. + */ +static uint32_t fls64(uint64_t x) +{ + uint32_t lo = (uint32_t)x; + if (lo) + return fls(lo); + uint32_t hi = x >> 32; + return fls(hi) + 32; +} + +/* + * fms64: find most significant bit set in a 64-bit word + * As samples, fms64(0x0) = 0; fms64(0x4400) = 14; + * fms64(0x40400000000) = 42. + */ +static uint32_t fms64(uint64_t x) +{ + uint32_t hi = (uint32_t)(x >> 32); + if (!hi) + return fms((uint32_t)x); + return fms(hi) + 32; +} + static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint64_t base, uint64_t size, int mtrr_type) { while (size != 0) { uint32_t addr_lsb; uint32_t size_msb; - uint32_t mtrr_size; + uint64_t mtrr_size; - addr_lsb = fls(base); - size_msb = fms(size); + addr_lsb = fls64(base); + size_msb = fms64(size); /* All MTRR entries need to have their base aligned to the mask * size. The maximum size is calculated by a function of the @@ -472,8 +497,8 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, } } -static uint32_t optimize_var_mtrr_hole(const uint32_t base, - const uint32_t hole, +static uint64_t optimize_var_mtrr_hole(const uint64_t base, + const uint64_t hole, const uint64_t limit, const int carve_hole) { @@ -531,7 +556,7 @@ static uint32_t optimize_var_mtrr_hole(const uint32_t base, static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, struct range_entry *r) { - uint32_t a1, a2, b1, b2; + uint64_t a1, a2, b1, b2; int mtrr_type, carve_hole; /* @@ -671,6 +696,7 @@ static void __calc_var_mtrrs(struct memranges *addr_space, wb_deftype_count += var_state.mtrr_index; } } + *num_def_wb_mtrrs = wb_deftype_count; *num_def_uc_mtrrs = uc_deftype_count; } From 09917e10cb520b6d492e7661e48db629504b58a1 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 14 Oct 2020 18:15:21 +0000 Subject: [PATCH 146/354] libpayload/storage/ahci: Use pci_dev struct in ahci_initialize() Clean up ahci_initialize() by using pci_dev struct. Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/libpayload/drivers/storage/ahci.c | 23 +++++++------------ payloads/libpayload/drivers/storage/storage.c | 2 +- payloads/libpayload/include/storage/ahci.h | 4 +++- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index e54bfbfef0..6a6fbfd418 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -228,34 +228,27 @@ static u32 working_controllers[] = { }; #endif -void ahci_initialize(pcidev_t dev) +void ahci_initialize(struct pci_dev *dev) { int i; - const u16 class = pci_read_config16(dev, 0xa); - if (class != 0x0106) - return; - const u16 vendor = pci_read_config16(dev, 0x00); - const u16 device = pci_read_config16(dev, 0x02); - #if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED) - const u32 vendor_device = pci_read_config32(dev, 0x0); + const u32 vendor_device = dev->vendor_id | dev->device_id << 16; for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) break; if (i == ARRAY_SIZE(working_controllers)) { printf("ahci: Not using untested SATA controller " - "%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev), - PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + "%02x:%02x.%02x (%04x:%04x).\n", dev->bus, + dev->dev, dev->func, dev->vendor_id, dev->device_id); return; } #endif printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n", - PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device); + dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id); - hba_ctrl_t *const ctrl = phys_to_virt( - pci_read_config32(dev, 0x24) & ~0x3ff); + hba_ctrl_t *const ctrl = phys_to_virt(pci_read_long(dev, 0x24) & ~0x3ff); hba_port_t *const ports = ctrl->ports; /* Reset host controller. */ @@ -274,8 +267,8 @@ void ahci_initialize(pcidev_t dev) ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; /* Enable bus mastering. */ - const u16 command = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + const u16 command = pci_read_word(dev, PCI_COMMAND); + pci_write_word(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); /* Probe for devices. */ for (i = 0; i < 32; ++i) { diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index addf8d2bd3..a3b31c598d 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -115,7 +115,7 @@ void storage_initialize(void) switch (dev->device_class) { #if CONFIG(LP_STORAGE_AHCI) case PCI_CLASS_STORAGE_AHCI: - ahci_initialize(PCI_DEV(dev->bus, dev->dev, dev->func)); + ahci_initialize(dev); break; #endif default: diff --git a/payloads/libpayload/include/storage/ahci.h b/payloads/libpayload/include/storage/ahci.h index 28436249f8..18a0920a61 100644 --- a/payloads/libpayload/include/storage/ahci.h +++ b/payloads/libpayload/include/storage/ahci.h @@ -26,9 +26,11 @@ * SUCH DAMAGE. */ +#include + #ifndef _STORAGE_AHCI_H #define _STORAGE_AHCI_H -void ahci_initialize(pcidev_t dev); +void ahci_initialize(struct pci_dev *dev); #endif From 9eabeb53abcf2c27ac2286d30859ccdf7556a8bd Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 30 Sep 2020 13:18:20 -0600 Subject: [PATCH 147/354] acpi: Skip writing references for disabled devices in Type-C config When emitting ACPI tables for the Type-C connector class, skip writing out a device reference if it is to a disabled device. Signed-off-by: Tim Wawrzynczak Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45877 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh --- src/acpi/acpigen_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 90a9b77c60..7448b3b569 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -71,7 +71,7 @@ static void add_device_ref(struct acpi_dp *dsd, const char *path; char *fresh; - if (!dev) + if (!dev || !dev->enabled) return; /* From 9f8ac64baef21dc0be7d1b54c998561dcced0d89 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Oct 2020 12:20:16 -0700 Subject: [PATCH 148/354] mrc_cache: Add config MRC_SAVE_HASH_IN_TPM Use this config to specify whether we want to save a hash of the MRC_CACHE in the TPM NVRAM space. Replace all uses of FSP2_0_USES_TPM_MRC_HASH with MRC_SAVE_HASH_IN_TPM and remove the FSP2_0_USES_TPM_MRC_HASH config. Note that TPM1 platforms will not select MRC_SAVE_HASH_IN_TPM as none of them use FSP2.0 and have recovery MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic5ffcdba27cb1f09c39c3835029c8d9cc3453af1 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46509 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/Kconfig | 17 ----------------- src/drivers/intel/fsp2_0/memory_init.c | 8 ++++---- src/drivers/mrc_cache/Kconfig | 8 ++++++++ src/security/vboot/Kconfig | 1 + src/security/vboot/Makefile.inc | 2 +- 5 files changed, 14 insertions(+), 22 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1a1da6c1e9..ad7afd8045 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -141,23 +141,6 @@ config FSP_TEMP_RAM_SIZE own stack that will be placed in DRAM and not in CAR, this is the amount of memory the FSP needs for its stack and heap. -config FSP2_0_USES_TPM_MRC_HASH - bool - depends on TPM1 || TPM2 - depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK - default y if HAS_RECOVERY_MRC_CACHE - default n - select VBOOT_HAS_REC_HASH_SPACE - help - Store hash of trained recovery MRC cache in NVRAM space in TPM. - Use the hash to validate recovery MRC cache before using it. - This hash needs to be updated every time recovery mode training - is recomputed, or if the hash does not match recovery MRC cache. - Selecting this option requires that TPM already be setup by this - point in time. Thus it is only compatible when the option - VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and - TPM setup to occur prior to memory initialization. - config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS bool help diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 14aec98d43..09aad6be81 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -19,15 +19,15 @@ #include #include #include -#include #include +#include #include #include static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); /* TPM MRC hash functionality depends on vboot starting before memory init. */ -_Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || +_Static_assert(!CONFIG(MRC_SAVE_HASH_IN_TPM) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "for TPM MRC hash functionality, vboot must start in bootblock"); @@ -55,7 +55,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) + if (CONFIG(MRC_SAVE_HASH_IN_TPM)) mrc_cache_update_hash(mrc_data, mrc_data_size); } @@ -121,7 +121,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) if (data == NULL) return; - if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && + if (CONFIG(MRC_SAVE_HASH_IN_TPM) && !mrc_cache_verify_hash(data, mrc_size)) return; diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index e09c5d8859..b09c19672e 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -49,4 +49,12 @@ config MRC_STASH_TO_CBMEM that need to write back the MRC data in late ramstage boot states (MRC_WRITE_NV_LATE). +config MRC_SAVE_HASH_IN_TPM + bool "Save a hash of the MRC_CACHE data in TPM NVRAM" + depends on VBOOT_STARTS_IN_BOOTBLOCK && TPM2 && !TPM1 + default y + help + Store a hash of the MRC_CACHE training data in a TPM NVRAM + space to ensure that it cannot be tampered with. + endif # CACHE_MRC_SETTINGS diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ee8d36ae7b..094cbb9642 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -159,6 +159,7 @@ config VBOOT_ALWAYS_ALLOW_UDC config VBOOT_HAS_REC_HASH_SPACE bool + default y if MRC_SAVE_HASH_IN_TPM && HAS_RECOVERY_MRC_CACHE default n help Set this option to indicate to vboot that recovery data hash space diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index e92396d926..d4dabe2493 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -118,7 +118,7 @@ romstage-y += common.c ramstage-y += common.c postcar-y += common.c -romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c +romstage-$(CONFIG_MRC_SAVE_HASH_IN_TPM) += mrc_cache_hash_tpm.c ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) From 1fed53f08a8099e03e352034b1265cc7b2fd427a Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Oct 2020 12:30:05 -0700 Subject: [PATCH 149/354] mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driver This CL would remove these calls from fsp 2.0. Platforms that select MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from romstage (when data stashed to CBMEM) to ramstage (when data is written back to SPI flash. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner --- src/drivers/intel/fsp2_0/memory_init.c | 13 ------------- src/drivers/mrc_cache/mrc_cache.c | 11 +++++++++++ src/security/vboot/Makefile.inc | 1 + 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 09aad6be81..68cc1215a5 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -19,18 +19,12 @@ #include #include #include -#include #include #include #include static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); -/* TPM MRC hash functionality depends on vboot starting before memory init. */ -_Static_assert(!CONFIG(MRC_SAVE_HASH_IN_TPM) || - CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), - "for TPM MRC hash functionality, vboot must start in bootblock"); - static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -54,9 +48,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - - if (CONFIG(MRC_SAVE_HASH_IN_TPM)) - mrc_cache_update_hash(mrc_data, mrc_data_size); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -121,10 +112,6 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) if (data == NULL) return; - if (CONFIG(MRC_SAVE_HASH_IN_TPM) && - !mrc_cache_verify_hash(data, mrc_size)) - return; - /* MRC cache found */ arch_upd->NvsBufferPtr = data; diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index a083655a2f..95abc4f1f8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -82,6 +83,11 @@ static const struct cache_region *cache_regions[] = { &variable_data, }; +/* TPM MRC hash functionality depends on vboot starting before memory init. */ +_Static_assert(!CONFIG(MRC_SAVE_HASH_IN_TPM) || + CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), + "for TPM MRC hash functionality, vboot must start in bootblock"); + static int lookup_region_by_name(const char *name, struct region *r) { if (fmap_locate_area(name, r) == 0) @@ -185,6 +191,9 @@ static int mrc_data_valid(const struct mrc_metadata *md, return -1; } + if (CONFIG(MRC_SAVE_HASH_IN_TPM) && !mrc_cache_verify_hash(data, data_size)) + return -1; + return 0; } @@ -443,6 +452,8 @@ static void update_mrc_cache_by_type(int type, } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); + if (CONFIG(MRC_SAVE_HASH_IN_TPM)) + mrc_cache_update_hash(new_data, new_data_size); } } diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d4dabe2493..4cf809016a 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -119,6 +119,7 @@ ramstage-y += common.c postcar-y += common.c romstage-$(CONFIG_MRC_SAVE_HASH_IN_TPM) += mrc_cache_hash_tpm.c +ramstage-$(CONFIG_MRC_SAVE_HASH_IN_TPM) += mrc_cache_hash_tpm.c ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) From a79803cf299a2c4912d5368951c6356df2dcd906 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Oct 2020 13:15:59 -0700 Subject: [PATCH 150/354] security/vboot: Make mrc_cache hash functions generic We need to extend the functionality of the mrc_cache hash functions to work for both recovery and normal mrc_cache data. Updating the API of these functions to pass in an index to identify the hash indices for recovery and normal mode. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I9c0bb25eafc731ca9c7a95113ab940f55997fc0f Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46432 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/mrc_cache/mrc_cache.c | 7 ++- src/security/vboot/antirollback.h | 31 ++++++++---- src/security/vboot/mrc_cache_hash_tpm.c | 26 +++++----- src/security/vboot/mrc_cache_hash_tpm.h | 4 +- src/security/vboot/secdata_mock.c | 6 +-- src/security/vboot/secdata_tpm.c | 63 ++++++++++++------------- src/security/vboot/vboot_logic.c | 2 +- 7 files changed, 78 insertions(+), 61 deletions(-) diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 95abc4f1f8..8d4df8f9b8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -179,6 +180,7 @@ static int mrc_data_valid(const struct mrc_metadata *md, void *data, size_t data_size) { uint16_t checksum; + uint32_t hash_idx = MRC_REC_HASH_NV_INDEX; if (md->data_size != data_size) return -1; @@ -191,7 +193,7 @@ static int mrc_data_valid(const struct mrc_metadata *md, return -1; } - if (CONFIG(MRC_SAVE_HASH_IN_TPM) && !mrc_cache_verify_hash(data, data_size)) + if (CONFIG(MRC_SAVE_HASH_IN_TPM) && !mrc_cache_verify_hash(hash_idx, data, data_size)) return -1; return 0; @@ -393,6 +395,7 @@ static void update_mrc_cache_by_type(int type, const struct region_device *backing_rdev; struct region_device latest_rdev; const bool fail_bad_data = false; + uint32_t hash_idx = MRC_REC_HASH_NV_INDEX; cr = lookup_region(®ion, type); @@ -453,7 +456,7 @@ static void update_mrc_cache_by_type(int type, printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); if (CONFIG(MRC_SAVE_HASH_IN_TPM)) - mrc_cache_update_hash(new_data, new_data_size); + mrc_cache_update_hash(hash_idx, new_data, new_data_size); } } diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 595205da29..8b183da9a5 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -22,8 +22,9 @@ enum vb2_pcr_digest; * want to use 0x1009 for something else. */ #define BACKUP_NV_INDEX 0x1009 #define FWMP_NV_INDEX 0x100a -#define REC_HASH_NV_INDEX 0x100b -#define REC_HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE +/* 0x100b: Hash of MRC_CACHE training data for recovery boot */ +#define MRC_REC_HASH_NV_INDEX 0x100b +#define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE /* Structure definitions for TPM spaces */ @@ -55,11 +56,25 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx); */ uint32_t antirollback_lock_space_firmware(void); -/* Read recovery hash data from TPM. */ -uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size); -/* Write new hash data to recovery space in TPM. */ -uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size); -/* Lock down recovery hash space in TPM. */ -uint32_t antirollback_lock_space_rec_hash(void); +/* + * Read recovery hash data from TPM. + * @param index index into TPM NVRAM where hash is stored + * @param data pointer to buffer where hash from TPM read into + * @param size size of buffer + */ +uint32_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size); +/* + * Write new hash data to recovery space in TPM.\ + * @param index index into TPM NVRAM where hash is stored + * @param data pointer to buffer of hash value to be written + * @param size size of buffer +*/ +uint32_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, + uint32_t size); +/* + * Lock down recovery hash space in TPM. + * @param index index into TPM NVRAM where hash is stored +*/ +uint32_t antirollback_lock_space_mrc_hash(uint32_t index); #endif /* ANTIROLLBACK_H_ */ diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index 24e7aafaa7..fede488e85 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -9,7 +9,7 @@ #include #include -void mrc_cache_update_hash(const uint8_t *data, size_t size) +void mrc_cache_update_hash(uint32_t index, const uint8_t *data, size_t size) { uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = { @@ -40,26 +40,26 @@ void mrc_cache_update_hash(const uint8_t *data, size_t size) printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. " "Not updating TPM hash space.\n"); /* - * Since data is being updated in recovery cache, the hash - * currently stored in TPM recovery hash space is no longer - * valid. If we are not able to calculate hash of the data being - * updated, reset all the bits in TPM recovery hash space to - * pre-defined hash pattern. + * Since data is being updated in mrc cache, the hash + * currently stored in TPM hash space is no longer + * valid. If we are not able to calculate hash of the + * data being updated, reset all the bits in TPM hash + * space to pre-defined hash pattern. */ hash_ptr = dead_hash; } /* Write hash of data to TPM space. */ - if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE) + if (antirollback_write_space_mrc_hash(index, hash_ptr, VB2_SHA256_DIGEST_SIZE) != TPM_SUCCESS) { printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); return; } - printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); + printk(BIOS_INFO, "MRC: TPM MRC hash idx 0x%x updated successfully.\n", index); } -int mrc_cache_verify_hash(const uint8_t *data, size_t size) +int mrc_cache_verify_hash(uint32_t index, const uint8_t *data, size_t size) { uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; @@ -68,7 +68,7 @@ int mrc_cache_verify_hash(const uint8_t *data, size_t size) if (!vboot_recovery_mode_enabled()) return 1; - /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ + /* Calculate hash of data read from MRC_CACHE. */ if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, sizeof(data_hash))) { printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); @@ -82,7 +82,7 @@ int mrc_cache_verify_hash(const uint8_t *data, size_t size) } /* Read hash of MRC data saved in TPM. */ - if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash)) + if (antirollback_read_space_mrc_hash(index, tpm_hash, sizeof(tpm_hash)) != TPM_SUCCESS) { printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); return 0; @@ -93,7 +93,7 @@ int mrc_cache_verify_hash(const uint8_t *data, size_t size) return 0; } - printk(BIOS_INFO, "MRC: Hash comparison successful. " - "Using data from RECOVERY_MRC_CACHE\n"); + printk(BIOS_INFO, "MRC: Hash idx 0x%x comparison successful.\n", index); + return 1; } diff --git a/src/security/vboot/mrc_cache_hash_tpm.h b/src/security/vboot/mrc_cache_hash_tpm.h index a1ecd8bfca..cf443f291b 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.h +++ b/src/security/vboot/mrc_cache_hash_tpm.h @@ -8,12 +8,12 @@ /* * Updates mrc cache hash if it differs. */ -void mrc_cache_update_hash(const uint8_t *data, size_t size); +void mrc_cache_update_hash(uint32_t index, const uint8_t *data, size_t size); /* * Verifies mrc cache hash which is stored somewhere. * return 1 verification was successful and 0 for error. */ -int mrc_cache_verify_hash(const uint8_t *data, size_t size); +int mrc_cache_verify_hash(uint32_t index, const uint8_t *data, size_t size); #endif /* _MRC_CACHE_HASH_TPM_H_ */ diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index ae124dadf4..78cb3e6063 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -42,17 +42,17 @@ vb2_error_t antirollback_lock_space_firmware(void) return VB2_SUCCESS; } -vb2_error_t antirollback_lock_space_rec_hash(void) +vb2_error_t antirollback_lock_space_mrc_hash(uint32_t index) { return VB2_SUCCESS; } -vb2_error_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) +vb2_error_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size) { return VB2_SUCCESS; } -vb2_error_t antirollback_write_space_rec_hash(const uint8_t *data, +vb2_error_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, uint32_t size) { return VB2_SUCCESS; diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 691d2c0e96..451f0438f3 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -71,10 +71,10 @@ uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) return TPM_SUCCESS; } -static uint32_t read_space_rec_hash(uint8_t *data) +static uint32_t read_space_mrc_hash(uint32_t index, uint8_t *data) { - RETURN_ON_FAILURE(tlcl_read(REC_HASH_NV_INDEX, data, - REC_HASH_NV_SIZE)); + RETURN_ON_FAILURE(tlcl_read(index, data, + HASH_NV_SIZE)); return TPM_SUCCESS; } @@ -83,7 +83,7 @@ static uint32_t read_space_rec_hash(uint8_t *data) * it. Since there is no data available to calculate hash at the point where TPM * space is defined, initialize it to all 0s. */ -static const uint8_t rec_hash_data[REC_HASH_NV_SIZE] = { }; +static const uint8_t mrc_hash_data[HASH_NV_SIZE] = { }; #if CONFIG(TPM2) /* @@ -162,10 +162,9 @@ static uint32_t set_kernel_space(const void *kernel_blob) VB2_SECDATA_KERNEL_SIZE, rw_space_attributes, NULL, 0); } -static uint32_t set_rec_hash_space(const uint8_t *data) +static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) { - return set_space("MRC Hash", REC_HASH_NV_INDEX, data, - REC_HASH_NV_SIZE, + return set_space("MRC Hash", index, data, HASH_NV_SIZE, ro_space_attributes, pcr0_unchanged_policy, sizeof(pcr0_unchanged_policy)); } @@ -185,7 +184,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(set_kernel_space(ctx->secdata_kernel)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) - RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); + RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); RETURN_ON_FAILURE(set_firmware_space(ctx->secdata_firmware)); @@ -197,9 +196,9 @@ uint32_t antirollback_lock_space_firmware(void) return tlcl_lock_nv_write(FIRMWARE_NV_INDEX); } -uint32_t antirollback_lock_space_rec_hash(void) +uint32_t antirollback_lock_space_mrc_hash(uint32_t index) { - return tlcl_lock_nv_write(REC_HASH_NV_INDEX); + return tlcl_lock_nv_write(index); } #else @@ -239,14 +238,14 @@ static uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) } } -static uint32_t set_rec_hash_space(const uint8_t *data) +static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) { - RETURN_ON_FAILURE(safe_define_space(REC_HASH_NV_INDEX, + RETURN_ON_FAILURE(safe_define_space(index, TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, - REC_HASH_NV_SIZE)); - RETURN_ON_FAILURE(safe_write(REC_HASH_NV_INDEX, data, - REC_HASH_NV_SIZE)); + HASH_NV_SIZE)); + RETURN_ON_FAILURE(safe_write(index, data, + HASH_NV_SIZE)); return TPM_SUCCESS; } @@ -307,7 +306,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) /* Define and set rec hash space, if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) - RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); + RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); return TPM_SUCCESS; } @@ -317,7 +316,7 @@ uint32_t antirollback_lock_space_firmware(void) return tlcl_set_global_lock(); } -uint32_t antirollback_lock_space_rec_hash(void) +uint32_t antirollback_lock_space_mrc_hash(uint32_t index) { /* * Nothing needs to be done here, since global lock is already set while @@ -417,43 +416,43 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx) return safe_write(KERNEL_NV_INDEX, ctx->secdata_kernel, size); } -uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) +uint32_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size) { - if (size != REC_HASH_NV_SIZE) { - VBDEBUG("TPM: Incorrect buffer size for rec hash. " - "(Expected=0x%x Actual=0x%x).\n", REC_HASH_NV_SIZE, + if (size != HASH_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " + "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, size); return TPM_E_READ_FAILURE; } - return read_space_rec_hash(data); + return read_space_mrc_hash(index, data); } -uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size) +uint32_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, uint32_t size) { - uint8_t spc_data[REC_HASH_NV_SIZE]; + uint8_t spc_data[HASH_NV_SIZE]; uint32_t rv; - if (size != REC_HASH_NV_SIZE) { - VBDEBUG("TPM: Incorrect buffer size for rec hash. " - "(Expected=0x%x Actual=0x%x).\n", REC_HASH_NV_SIZE, + if (size != HASH_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " + "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, size); return TPM_E_WRITE_FAILURE; } - rv = read_space_rec_hash(spc_data); + rv = read_space_mrc_hash(index, spc_data); if (rv == TPM_E_BADINDEX) { /* - * If space is not defined already for recovery hash, define + * If space is not defined already for hash, define * new space. */ - VBDEBUG("TPM: Initializing recovery hash space.\n"); - return set_rec_hash_space(data); + VBDEBUG("TPM: Initializing hash space.\n"); + return set_mrc_hash_space(index, data); } if (rv != TPM_SUCCESS) return rv; - return safe_write(REC_HASH_NV_INDEX, data, size); + return safe_write(index, data, size); } vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 0f18f9a20f..dbaa883080 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -404,7 +404,7 @@ void verstage_main(void) /* Lock rec hash space if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) { - rv = antirollback_lock_space_rec_hash(); + rv = antirollback_lock_space_mrc_hash(MRC_REC_HASH_NV_INDEX); if (rv) { printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", rv); From df0481e9e1f46193a9f456602987a1a3694102f3 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 16 Oct 2020 13:37:09 -0700 Subject: [PATCH 151/354] security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEX Add new index for MRC_CACHE data in RW. Also update antirollback functions to handle this new index where necessary. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I2de3c23aa56d3b576ca54dbd85c75e5b80199560 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46511 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/security/vboot/antirollback.h | 24 ++++++++++++++++++------ src/security/vboot/secdata_tpm.c | 26 ++++++++++++++++++++++---- 2 files changed, 40 insertions(+), 10 deletions(-) diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 8b183da9a5..fcfa7a270c 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -24,6 +24,9 @@ enum vb2_pcr_digest; #define FWMP_NV_INDEX 0x100a /* 0x100b: Hash of MRC_CACHE training data for recovery boot */ #define MRC_REC_HASH_NV_INDEX 0x100b +/* 0x100c: OOBE autoconfig public key hashes */ +/* 0x100d: Hash of MRC_CACHE training data for non-recovery boot */ +#define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE /* Structure definitions for TPM spaces */ @@ -57,23 +60,32 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx); uint32_t antirollback_lock_space_firmware(void); /* - * Read recovery hash data from TPM. - * @param index index into TPM NVRAM where hash is stored + * Read MRC hash data from TPM. + * @param index index into TPM NVRAM where hash is stored The index + * can be set to either MRC_REC_HASH_NV_INDEX or + * MRC_RW_HASH_NV_INDEX depending upon whether we are + * booting in recovery or normal mode. * @param data pointer to buffer where hash from TPM read into * @param size size of buffer */ uint32_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size); /* - * Write new hash data to recovery space in TPM.\ - * @param index index into TPM NVRAM where hash is stored + * Write new hash data to MRC space in TPM.\ + * @param index index into TPM NVRAM where hash is stored The index + * can be set to either MRC_REC_HASH_NV_INDEX or + * MRC_RW_HASH_NV_INDEX depending upon whether we are + * booting in recovery or normal mode. * @param data pointer to buffer of hash value to be written * @param size size of buffer */ uint32_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, uint32_t size); /* - * Lock down recovery hash space in TPM. - * @param index index into TPM NVRAM where hash is stored + * Lock down MRC hash space in TPM. + * @param index index into TPM NVRAM where hash is stored The index + * can be set to either MRC_REC_HASH_NV_INDEX or + * MRC_RW_HASH_NV_INDEX depending upon whether we are + * booting in recovery or normal mode. */ uint32_t antirollback_lock_space_mrc_hash(uint32_t index); diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 451f0438f3..0304b923fb 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -164,9 +164,14 @@ static uint32_t set_kernel_space(const void *kernel_blob) static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) { - return set_space("MRC Hash", index, data, HASH_NV_SIZE, - ro_space_attributes, pcr0_unchanged_policy, - sizeof(pcr0_unchanged_policy)); + if (index == MRC_REC_HASH_NV_INDEX) { + return set_space("RO MRC Hash", index, data, HASH_NV_SIZE, + ro_space_attributes, pcr0_unchanged_policy, + sizeof(pcr0_unchanged_policy)); + } else { + return set_space("RW MRC Hash", index, data, HASH_NV_SIZE, + rw_space_attributes, NULL, 0); + } } static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) @@ -183,6 +188,13 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) */ RETURN_ON_FAILURE(set_kernel_space(ctx->secdata_kernel)); + /* + * Define and set rec hash space, if available. No need to + * create the RW hash space because we will definitely boot + * once in normal mode before shipping, meaning that the space + * will get created with correct permissions while still in in + * our hands. + */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); @@ -304,7 +316,13 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) ctx->secdata_firmware, VB2_SECDATA_FIRMWARE_SIZE)); - /* Define and set rec hash space, if available. */ + /* + * Define and set rec hash space, if available. No need to + * create the RW hash space because we will definitely boot + * once in normal mode before shipping, meaning that the space + * will get created with correct permissions while still in in + * our hands. + */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); From c1040f3ef43bf906b71746e3e0a07dbb4a44febe Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 20 Oct 2020 10:42:26 -0700 Subject: [PATCH 152/354] mrc_cache: Add tpm_hash_index field to cache_region struct Pull selection of tpm hash index logic into cache_region struct. This CL also enables the storing of the MRC hash into the TPM NVRAM space for both recovery and non-recovery cases. This will affect all platforms with TPM2 enabled and use the MRC_CACHE driver. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami and lazor Change-Id: I1a744d6f40f062ca3aab6157b3747e6c1f6977f9 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46514 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/mrc_cache/mrc_cache.c | 25 ++++++++++++++++++------- src/security/vboot/mrc_cache_hash_tpm.c | 8 -------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 8d4df8f9b8..1bbb426b5d 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -46,6 +46,7 @@ struct cache_region { uint32_t cbmem_id; int type; int elog_slot; + uint32_t tpm_hash_index; int flags; }; @@ -54,6 +55,7 @@ static const struct cache_region recovery_training = { .cbmem_id = CBMEM_ID_MRCDATA, .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, + .tpm_hash_index = MRC_REC_HASH_NV_INDEX, #if CONFIG(HAS_RECOVERY_MRC_CACHE) .flags = RECOVERY_FLAG, #else @@ -66,6 +68,7 @@ static const struct cache_region normal_training = { .cbmem_id = CBMEM_ID_MRCDATA, .type = MRC_TRAINING_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + .tpm_hash_index = MRC_RW_HASH_NV_INDEX, .flags = NORMAL_FLAG | RECOVERY_FLAG, }; @@ -74,6 +77,7 @@ static const struct cache_region variable_data = { .cbmem_id = CBMEM_ID_VAR_MRCDATA, .type = MRC_VARIABLE_DATA, .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, + .tpm_hash_index = 0, .flags = NORMAL_FLAG | RECOVERY_FLAG, }; @@ -176,11 +180,15 @@ static int mrc_header_valid(struct region_device *rdev, struct mrc_metadata *md) return 0; } -static int mrc_data_valid(const struct mrc_metadata *md, +static int mrc_data_valid(int type, const struct mrc_metadata *md, void *data, size_t data_size) { uint16_t checksum; - uint32_t hash_idx = MRC_REC_HASH_NV_INDEX; + const struct cache_region *cr = lookup_region_type(type); + uint32_t hash_idx; + + if (cr == NULL) + return -1; if (md->data_size != data_size) return -1; @@ -193,7 +201,9 @@ static int mrc_data_valid(const struct mrc_metadata *md, return -1; } - if (CONFIG(MRC_SAVE_HASH_IN_TPM) && !mrc_cache_verify_hash(hash_idx, data, data_size)) + hash_idx = cr->tpm_hash_index; + if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM) && + !mrc_cache_verify_hash(hash_idx, data, data_size)) return -1; return 0; @@ -288,7 +298,7 @@ ssize_t mrc_cache_load_current(int type, uint32_t version, void *buffer, if (rdev_readat(&rdev, buffer, 0, data_size) != data_size) return -1; - if (mrc_data_valid(&md, buffer, data_size) < 0) + if (mrc_data_valid(type, &md, buffer, data_size) < 0) return -1; return data_size; @@ -315,7 +325,7 @@ void *mrc_cache_current_mmap_leak(int type, uint32_t version, return NULL; } - if (mrc_data_valid(&md, data, region_device_size) < 0) + if (mrc_data_valid(type, &md, data, region_device_size) < 0) return NULL; return data; @@ -395,7 +405,7 @@ static void update_mrc_cache_by_type(int type, const struct region_device *backing_rdev; struct region_device latest_rdev; const bool fail_bad_data = false; - uint32_t hash_idx = MRC_REC_HASH_NV_INDEX; + uint32_t hash_idx; cr = lookup_region(®ion, type); @@ -455,7 +465,8 @@ static void update_mrc_cache_by_type(int type, } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); log_event_cache_update(cr->elog_slot, UPDATE_SUCCESS); - if (CONFIG(MRC_SAVE_HASH_IN_TPM)) + hash_idx = cr->tpm_hash_index; + if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM)) mrc_cache_update_hash(hash_idx, new_data, new_data_size); } } diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index fede488e85..77c23f63e4 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -24,10 +24,6 @@ void mrc_cache_update_hash(uint32_t index, const uint8_t *data, size_t size) }; const uint8_t *hash_ptr = data_hash; - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return; - /* Initialize TPM driver. */ if (tlcl_lib_init() != VB2_SUCCESS) { printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); @@ -64,10 +60,6 @@ int mrc_cache_verify_hash(uint32_t index, const uint8_t *data, size_t size) uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return 1; - /* Calculate hash of data read from MRC_CACHE. */ if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, sizeof(data_hash))) { From a45f8959c02cd73d8eebe5e39c0fa9957bc05ae3 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Sat, 17 Oct 2020 00:53:41 -0700 Subject: [PATCH 153/354] mrc_cache: Remove unnecessary data checksum calculation When MRC_SAVE_HASH_IN_TPM is selected, we can just use the TPM hash to verify the MRC_CACHE data. Thus, we don't need to calculate the checksum anymore in this case. BUG=b:150502246 BRANCH=None TEST=make sure memory training still works on nami Change-Id: I1db4469da49755805b541f50c7ef2f9cdb749425 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46515 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/mrc_cache/mrc_cache.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 1bbb426b5d..3b98dbaa63 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -193,18 +193,19 @@ static int mrc_data_valid(int type, const struct mrc_metadata *md, if (md->data_size != data_size) return -1; - checksum = compute_ip_checksum(data, data_size); - - if (md->data_checksum != checksum) { - printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", - md->data_checksum, checksum); - return -1; - } - hash_idx = cr->tpm_hash_index; - if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM) && - !mrc_cache_verify_hash(hash_idx, data, data_size)) - return -1; + if (hash_idx && CONFIG(MRC_SAVE_HASH_IN_TPM)) { + if (!mrc_cache_verify_hash(hash_idx, data, data_size)) + return -1; + } else { + checksum = compute_ip_checksum(data, data_size); + + if (md->data_checksum != checksum) { + printk(BIOS_ERR, "MRC: data checksum mismatch: %x vs %x\n", + md->data_checksum, checksum); + return -1; + } + } return 0; } From 7ea4372d82e096cc1bbd1aeae9e04adc9f5ac083 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 16 Oct 2020 20:56:53 +0530 Subject: [PATCH 154/354] mb/google/dedede/variants/drawcia: update PL1 max and min power values Update PL1 max and min power values BUG=None BRANCH=None TEST=build and verify on dralat system Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 044ff08c2f..ac7a97e75a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -93,8 +93,8 @@ chip soc/intel/jasperlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 4800, - .max_power = 6000, + .min_power = 3800, + .max_power = 5800, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200, From fe6070f7280cfcc41fffded67789439531e8ab49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 4 Oct 2020 15:16:04 +0200 Subject: [PATCH 155/354] soc/intel/common: add Kconfig for PM Timer emulation support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/cannonlake/Kconfig | 1 + src/soc/intel/common/block/cpu/Kconfig | 8 ++++++++ src/soc/intel/elkhartlake/Kconfig | 1 + src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/jasperlake/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/tigerlake/Kconfig | 1 + 9 files changed, 16 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b8a2a136f3..dc9e823f93 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index da57931ad4..c1b5252aa8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS # CPU specific options select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select IOAPIC select PCR_COMMON_IOSF_1_0 select SSE2 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9bd9f43314..dc2be28f81 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -79,6 +79,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 995a95680c..9e95a8aa90 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -98,3 +98,11 @@ config INTEL_TME /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, it would get enabled. If CPU supports MKTME, this same config option enables MKTME. + +config CPU_SUPPORTS_PM_TIMER_EMULATION + bool + default n + help + Select this if the SoC's ucode supports PM ACPI timer emulation (Common + timer Copy), which is required to be able to disable the TCO PM ACPI + timer for power saving. diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7e78805648..40770d0172 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0343263256..027ed7ddf6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8efa361c11..ba7e62136c 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select COS_MAPPED_TO_MSB select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 4abe29eebe..14d4fa1781 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d1689dacb3..0021da5821 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB From dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 4 Oct 2020 14:48:05 +0200 Subject: [PATCH 156/354] soc/intel: convert XTAL frequency constant to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/Kconfig | 3 +++ src/soc/intel/alderlake/cpu.c | 12 +++++++----- src/soc/intel/alderlake/include/soc/cpu.h | 3 --- src/soc/intel/apollolake/Kconfig | 3 +++ src/soc/intel/apollolake/include/soc/cpu.h | 3 --- src/soc/intel/apollolake/pmutil.c | 12 +++++++----- src/soc/intel/cannonlake/Kconfig | 3 +++ src/soc/intel/cannonlake/cpu.c | 11 +++++++---- src/soc/intel/cannonlake/include/soc/cpu.h | 3 --- src/soc/intel/common/block/cpu/Kconfig | 5 +++++ src/soc/intel/elkhartlake/Kconfig | 3 +++ src/soc/intel/elkhartlake/cpu.c | 12 +++++++----- src/soc/intel/elkhartlake/include/soc/cpu.h | 3 --- src/soc/intel/icelake/Kconfig | 3 +++ src/soc/intel/icelake/cpu.c | 12 +++++++----- src/soc/intel/icelake/include/soc/cpu.h | 3 --- src/soc/intel/jasperlake/Kconfig | 3 +++ src/soc/intel/jasperlake/cpu.c | 12 +++++++----- src/soc/intel/jasperlake/include/soc/cpu.h | 3 --- src/soc/intel/skylake/Kconfig | 3 +++ src/soc/intel/skylake/cpu.c | 12 +++++++----- src/soc/intel/skylake/include/soc/cpu.h | 3 --- src/soc/intel/tigerlake/Kconfig | 3 +++ src/soc/intel/tigerlake/cpu.c | 12 +++++++----- src/soc/intel/tigerlake/include/soc/cpu.h | 3 --- 25 files changed, 85 insertions(+), 63 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dc9e823f93..1a3f0724ae 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -136,6 +136,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index ee8051d568..e6a21c170e 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -111,15 +111,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 3c11183831..71c2f47605 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -19,7 +19,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c1b5252aa8..69d42bdf19 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -157,6 +157,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 +config CPU_XTAL_HZ + default 19200000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 490820c3f6..38b830a16f 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -6,9 +6,6 @@ #include #include -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 - struct device; void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c6d2eec791..e0de93eae4 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -180,15 +180,17 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dc2be28f81..24f64b1887 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -245,6 +245,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 216 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ddedb3fed2..0622034217 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -114,19 +114,22 @@ static void enable_pm_timer_emulation(void) { msr_t msr; + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); } + static void set_energy_perf_bias(u8 policy) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index b356d3a9b8..3542a2b8a4 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -22,9 +22,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9e95a8aa90..9023b58d54 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -99,6 +99,11 @@ config INTEL_TME it would get enabled. If CPU supports MKTME, this same config option enables MKTME. +config CPU_XTAL_HZ + int + help + Base clock which virtually everything runs on. + config CPU_SUPPORTS_PM_TIMER_EMULATION bool default n diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 40770d0172..05077ad316 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -133,6 +133,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 382bbf7b01..271d244db9 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h index 6ee34f234c..ec3cd3ec01 100644 --- a/src/soc/intel/elkhartlake/include/soc/cpu.h +++ b/src/soc/intel/elkhartlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 027ed7ddf6..21da528daa 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -127,6 +127,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 2823fd7c4e..e76f61fa99 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index a23133367e..5dc22ded76 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index ba7e62136c..d5adc600bb 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -137,6 +137,9 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config CPU_XTAL_HZ + default 38400000 + config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 3a50929a9b..1944e5c269 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -105,15 +105,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index c61f2ee95f..40cebd4c06 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -21,9 +21,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 14d4fa1781..55e74cd360 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -241,6 +241,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 24000000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f1b40f6d01..5ec002322b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -169,15 +169,17 @@ static void configure_c_states(void) */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 740b3d3fb0..473068c210 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -25,9 +25,6 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 24MHz. */ -#define CTC_FREQ 24000000 - #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0021da5821..2b5f0baeb1 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -138,6 +138,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 +config CPU_XTAL_HZ + default 38400000 + config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index be056fb7a4..1a5165d1e5 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -111,15 +111,17 @@ static void configure_dca_cap(void) static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ msr_t msr; + + if (!CONFIG_CPU_XTAL_HZ) + return; + /* * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * (clock * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; + msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 47a41ebc99..2d6336a9c4 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -21,7 +21,4 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 38.4MHz. */ -#define CTC_FREQ 38400000 - #endif From f50ea988b09e7201e129848ab64e6e0e69bf56c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 19 Oct 2020 12:31:21 +0200 Subject: [PATCH 157/354] soc/intel,mb/*: get rid of legacy pad macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Furquan Shaikh --- src/mainboard/51nb/x210/gpio.h | 102 ++++----- src/mainboard/asrock/h110m/include/gpio.h | 80 +++---- src/mainboard/facebook/monolith/gpio.h | 190 ++++++++-------- src/mainboard/google/eve/gpio.h | 204 +++++++++--------- .../google/fizz/variants/baseboard/gpio.c | 200 ++++++++--------- .../google/fizz/variants/endeavour/gpio.c | 178 +++++++-------- .../google/fizz/variants/karma/gpio.c | 191 ++++++++-------- .../variants/asuka/include/variant/gpio.h | 202 ++++++++--------- .../variants/caroline/include/variant/gpio.h | 182 ++++++++-------- .../variants/cave/include/variant/gpio.h | 180 ++++++++-------- .../variants/chell/include/variant/gpio.h | 154 ++++++------- .../variants/glados/include/variant/gpio.h | 26 +-- .../variants/lars/include/variant/gpio.h | 184 ++++++++-------- .../variants/sentry/include/variant/gpio.h | 170 +++++++-------- .../google/poppy/variants/atlas/gpio.c | 170 +++++++-------- .../google/poppy/variants/baseboard/gpio.c | 158 +++++++------- .../google/poppy/variants/nami/gpio.c | 182 ++++++++-------- .../google/poppy/variants/nautilus/gpio.c | 176 +++++++-------- .../google/poppy/variants/nocturne/gpio.c | 176 +++++++-------- .../google/poppy/variants/rammus/gpio.c | 172 +++++++-------- .../google/poppy/variants/soraka/gpio.c | 178 +++++++-------- .../intel/cedarisland_crb/include/gpio.h | 12 +- .../variants/rvp11/include/variant/gpio.h | 30 +-- .../variants/rvp3/include/variant/gpio.h | 88 ++++---- .../variants/rvp7/include/variant/gpio.h | 54 ++--- .../variants/rvp8/include/variant/gpio.h | 68 +++--- src/mainboard/intel/kunimitsu/gpio.h | 176 +++++++-------- src/mainboard/intel/saddlebrook/gpio.h | 6 +- src/mainboard/kontron/bsl6/gpio.h | 62 +++--- src/mainboard/libretrend/lt1000/gpio.h | 164 +++++++------- src/mainboard/prodrive/hermes/Kconfig | 1 - src/mainboard/protectli/vault_kbl/gpio.h | 22 +- src/mainboard/purism/librem_skl/gpio.h | 170 +++++++-------- src/mainboard/razer/blade_stealth_kbl/gpio.h | 36 ++-- .../variants/x11ssh-tf/include/variant/gpio.h | 8 +- .../variants/x11ssm-f/include/variant/gpio.h | 8 +- src/soc/intel/common/block/gpio/Kconfig | 5 - .../block/include/intelblocks/gpio_defs.h | 28 --- src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/xeon_sp/Kconfig | 1 - 40 files changed, 2179 insertions(+), 2216 deletions(-) diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index 34ee409e00..53a7547f31 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -30,14 +30,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), PAD_CFG_GPO(GPP_A7, 1, DEEP), - PAD_NC(GPP_A8, 20K_PU), - PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), - PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_NC(GPP_A8, UP_20K), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), PAD_CFG_GPO(GPP_A11, 0, DEEP), PAD_CFG_GPO(GPP_A12, 0, PWROK), PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), PAD_NC(GPP_A18, NONE), @@ -45,7 +45,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A20, NONE), PAD_NC(GPP_A21, NONE), PAD_CFG_GPO(GPP_A22, 1, DEEP), - PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, DN_20K, DEEP, OFF, ACPI), PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), PAD_NC(GPP_B2, NONE), @@ -60,25 +60,25 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), PAD_NC(GPP_B15, NONE), PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), - PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), - PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, UP_20K, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, UP_20K, PLTRST, OFF, ACPI), PAD_NC(GPP_B19, NONE), - PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), - PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), - PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), - PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), - PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C4, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_C5, DN_20K, DEEP, OFF, ACPI), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ - PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), @@ -86,11 +86,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_C16, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C17, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C18, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C19, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), @@ -99,22 +99,22 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), - PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), - PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), - PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), - PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), - PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_D5, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D7, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D8, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_D14, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), @@ -136,16 +136,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), - PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), - PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E18, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), - PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), - PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), + PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), PAD_CFG_NF(GPD1, NONE, PWROK, NF1), PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), - PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), PAD_CFG_NF(GPD4, NONE, PWROK, NF1), PAD_CFG_NF(GPD5, NONE, PWROK, NF1), PAD_CFG_NF(GPD6, NONE, PWROK, NF1), @@ -158,14 +158,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), - PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), - PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F4, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, UP_20K, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, UP_20K, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, UP_20K, DEEP, NF2), PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 193579c6a1..9b2193b587 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -12,13 +12,13 @@ static const struct pad_config gpio_table[] = { /* GPP_A0 - RCIN# */ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ @@ -28,9 +28,9 @@ static const struct pad_config gpio_table[] = { /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), /* GPP_A12 - GPIO */ @@ -40,7 +40,7 @@ static const struct pad_config gpio_table[] = { /* GPP_A14 - SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* GPP_A16 - GPIO */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), /* GPP_A17 - GPIO */ @@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B7 - NC */ PAD_NC(GPP_B7, NONE), /* GPP_B8 - GPIO */ - PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B8, UP_5K, PLTRST, OFF), /* GPP_B9 - GPIO */ PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), /* GPP_B10 - GPIO */ @@ -92,7 +92,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B13 - PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), /* GPP_B16 - GPIO */ @@ -110,7 +110,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), + PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ @@ -158,7 +158,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C22 - UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* GPP_C23 - GPIO */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + PAD_CFG_GPI_SCI_LOW(GPP_C23, NONE, DEEP, LEVEL), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -200,9 +200,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D18 - GPIO */ PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_D19, UP_20K, PLTRST, NF1), /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_D20, UP_20K, PLTRST, NF1), /* GPP_D21 - GPIO */ PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), /* GPP_D22 - GPIO */ @@ -212,11 +212,11 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), /* GPP_E3 - CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* GPP_E4 - SATA_DEVSLP0 */ @@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = { /* GPP_F0 - GPIO */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), /* GPP_F2 - GPIO */ PAD_NC(GPP_F2, NONE), /* GPP_F3 - GPIO */ @@ -260,15 +260,15 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPP_F10 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* GPP_F11 - GPIO */ PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), /* GPP_F12 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), /* GPP_F13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), /* GPP_F14 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), /* GPP_F15 - USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* GPP_F16 - USB_OC5# */ @@ -304,7 +304,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G6 - GPIO */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G7 - GPIO */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G12 - GPIO */ _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G13 - GPIO */ @@ -328,17 +328,17 @@ static const struct pad_config gpio_table[] = { /* GPP_G14 - GPIO */ _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G15 - GPIO */ PAD_CFG_GPO(GPP_G15, 0, PLTRST), /* GPP_G16 - GPIO */ - PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), /* GPP_G17 - GPIO */ PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), /* GPP_G18 - GPIO */ - PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), /* GPP_G19 - SMI# */ PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* GPP_G20 - GPIO */ @@ -378,11 +378,11 @@ static const struct pad_config gpio_table[] = { /* GPP_H12 - GPIO */ PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), /* GPP_H13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), /* GPP_H14 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), /* GPP_H15 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), /* GPP_H16 - GPIO */ PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* GPP_H17 - GPIO */ @@ -408,7 +408,7 @@ static const struct pad_config gpio_table[] = { /* GPD2 - LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* GPD4 - SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* GPD5 - SLP_S4# */ @@ -444,15 +444,15 @@ static const struct pad_config gpio_table[] = { /* GPP_I5 - DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* GPP_I6 - DDPB_CTRLDATA */ - PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* GPP_I7 - DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* GPP_I8 - DDPC_CTRLDATA */ - PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* GPP_I9 - DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* GPP_I10 - DDPD_CTRLDATA */ - PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), }; /* Early pad configuration in romstage */ @@ -461,13 +461,13 @@ static const struct pad_config early_gpio_table[] = { /* GPP_A0 - RCIN# */ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ @@ -476,16 +476,16 @@ static const struct pad_config early_gpio_table[] = { /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/facebook/monolith/gpio.h b/src/mainboard/facebook/monolith/gpio.h index f0f6eef49d..69ffc6bce0 100644 --- a/src/mainboard/facebook/monolith/gpio.h +++ b/src/mainboard/facebook/monolith/gpio.h @@ -10,52 +10,52 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* PCH_RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LAD_0 */ PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1), +/* LAD_1 */ PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1), +/* LAD_2 */ PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1), +/* LAD_3 */ PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PCH_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* PM_CLKRUN_N */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* SLEEP */ PAD_CFG_NC(GPP_A11), /* available on the module not used here */ -/* NC */ PAD_CFG_NC(GPP_A12), +/* CLK_LPC_EC */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* CLKOUT_LPC_CN */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* SLEEP */ PAD_NC(GPP_A11, NONE), /* available on the module not used here */ +/* NC */ PAD_NC(GPP_A12, NONE), /* PCH_SYSWARN */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* KBC_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_A18), -/* NC */ PAD_CFG_NC(GPP_A19), -/* NC */ PAD_CFG_NC(GPP_A20), -/* NC */ PAD_CFG_NC(GPP_A21), -/* NC */ PAD_CFG_NC(GPP_A22), -/* NC */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* NC */ PAD_NC(GPP_A18, NONE), +/* NC */ PAD_NC(GPP_A19, NONE), +/* NC */ PAD_NC(GPP_A20, NONE), +/* NC */ PAD_NC(GPP_A21, NONE), +/* NC */ PAD_NC(GPP_A22, NONE), +/* NC */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_B3), -/* NC */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0 */ PAD_CFG_NC(GPP_B5), -/* SRCCLKREQ1 */ PAD_CFG_NC(GPP_B6), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3 */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5 */ PAD_CFG_NC(GPP_B10), +/* NC */ PAD_NC(GPP_B3, NONE), +/* NC */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0 */ PAD_NC(GPP_B5, NONE), +/* SRCCLKREQ1 */ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3 */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5 */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLTRST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_B15), -/* NC */ PAD_CFG_NC(GPP_B16), -/* NC */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* NC */ PAD_CFG_NC(GPP_B19), -/* NC */ PAD_CFG_NC(GPP_B20), -/* NC */ PAD_CFG_NC(GPP_B21), -/* BIOS_SEL */ PAD_CFG_NC(GPP_B22), +/* NC */ PAD_NC(GPP_B15, NONE), +/* NC */ PAD_NC(GPP_B16, NONE), +/* NC */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* NC */ PAD_NC(GPP_B19, NONE), +/* NC */ PAD_NC(GPP_B20, NONE), +/* NC */ PAD_NC(GPP_B21, NONE), +/* BIOS_SEL */ PAD_NC(GPP_B22, NONE), /* CB_OVT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_SCL */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), @@ -63,56 +63,56 @@ static const struct pad_config gpio_table[] = { /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SDA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0_ALERT */ PAD_CFG_NC(GPP_C5), +/* SML0_ALERT */ PAD_NC(GPP_C5, NONE), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* CPU_UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* CPU_UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* CPU_UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* CPU_UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_C12), -/* NC */ PAD_CFG_NC(GPP_C13), -/* NC */ PAD_CFG_NC(GPP_C14), -/* NC */ PAD_CFG_NC(GPP_C15), +/* NC */ PAD_NC(GPP_C12, NONE), +/* NC */ PAD_NC(GPP_C13, NONE), +/* NC */ PAD_NC(GPP_C14, NONE), +/* NC */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* NC */ PAD_CFG_NC(GPP_C18), -/* NC */ PAD_CFG_NC(GPP_C19), -/* NC */ PAD_CFG_NC(GPP_C20), -/* NC */ PAD_CFG_NC(GPP_C21), -/* EC_SCI# NOT USED */ PAD_CFG_NC(GPP_C22), -/* EC_SMI# NOT USED */ PAD_CFG_NC(GPP_C23), -/* TOUCH_SPI1_CS */ PAD_CFG_NC(GPP_D0), -/* TPM_PIRQ_N NOT USED */ PAD_CFG_NC(GPP_D1), -/* NC */ PAD_CFG_NC(GPP_D2), -/* NC */ PAD_CFG_NC(GPP_D3), -/* NC */ PAD_CFG_NC(GPP_D4), -/* NC */ PAD_CFG_NC(GPP_D5), -/* NC */ PAD_CFG_NC(GPP_D6), -/* NC */ PAD_CFG_NC(GPP_D7), -/* NC */ PAD_CFG_NC(GPP_D8), -/* NC */ PAD_CFG_NC(GPP_D9), -/* NC */ PAD_CFG_NC(GPP_D11), -/* NC */ PAD_CFG_NC(GPP_D12), -/* NC */ PAD_CFG_NC(GPP_D13), -/* NC */ PAD_CFG_NC(GPP_D14), -/* NC */ PAD_CFG_NC(GPP_D15), -/* NC */ PAD_CFG_NC(GPP_D16), -/* NC */ PAD_CFG_NC(GPP_D17), -/* NC */ PAD_CFG_NC(GPP_D18), -/* NC */ PAD_CFG_NC(GPP_D19), -/* NC */ PAD_CFG_NC(GPP_D20), -/* LID# NOT USED */ PAD_CFG_NC(GPP_D21), -/* NC */ PAD_CFG_NC(GPP_D22), -/* NC */ PAD_CFG_NC(GPP_D23), -/* NC */ PAD_CFG_NC(GPP_E0), -/* NC */ PAD_CFG_NC(GPP_E1), -/* NC */ PAD_CFG_NC(GPP_E2), -/* NC */ PAD_CFG_NC(GPP_E3), -/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E4), -/* DEVSLP0 TP */ PAD_CFG_NC(GPP_E5), -/* DEVSLP1 TP */ PAD_CFG_NC(GPP_E6), -/* NC */ PAD_CFG_NC(GPP_E7), +/* NC */ PAD_NC(GPP_C18, NONE), +/* NC */ PAD_NC(GPP_C19, NONE), +/* NC */ PAD_NC(GPP_C20, NONE), +/* NC */ PAD_NC(GPP_C21, NONE), +/* EC_SCI# NOT USED */ PAD_NC(GPP_C22, NONE), +/* EC_SMI# NOT USED */ PAD_NC(GPP_C23, NONE), +/* TOUCH_SPI1_CS */ PAD_NC(GPP_D0, NONE), +/* TPM_PIRQ_N NOT USED */ PAD_NC(GPP_D1, NONE), +/* NC */ PAD_NC(GPP_D2, NONE), +/* NC */ PAD_NC(GPP_D3, NONE), +/* NC */ PAD_NC(GPP_D4, NONE), +/* NC */ PAD_NC(GPP_D5, NONE), +/* NC */ PAD_NC(GPP_D6, NONE), +/* NC */ PAD_NC(GPP_D7, NONE), +/* NC */ PAD_NC(GPP_D8, NONE), +/* NC */ PAD_NC(GPP_D9, NONE), +/* NC */ PAD_NC(GPP_D11, NONE), +/* NC */ PAD_NC(GPP_D12, NONE), +/* NC */ PAD_NC(GPP_D13, NONE), +/* NC */ PAD_NC(GPP_D14, NONE), +/* NC */ PAD_NC(GPP_D15, NONE), +/* NC */ PAD_NC(GPP_D16, NONE), +/* NC */ PAD_NC(GPP_D17, NONE), +/* NC */ PAD_NC(GPP_D18, NONE), +/* NC */ PAD_NC(GPP_D19, NONE), +/* NC */ PAD_NC(GPP_D20, NONE), +/* LID# NOT USED */ PAD_NC(GPP_D21, NONE), +/* NC */ PAD_NC(GPP_D22, NONE), +/* NC */ PAD_NC(GPP_D23, NONE), +/* NC */ PAD_NC(GPP_E0, NONE), +/* NC */ PAD_NC(GPP_E1, NONE), +/* NC */ PAD_NC(GPP_E2, NONE), +/* NC */ PAD_NC(GPP_E3, NONE), +/* DEVSLP0 TP */ PAD_NC(GPP_E4, NONE), +/* DEVSLP0 TP */ PAD_NC(GPP_E5, NONE), +/* DEVSLP1 TP */ PAD_NC(GPP_E6, NONE), +/* NC */ PAD_NC(GPP_E7, NONE), /* SATA_LED_N */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC0_1 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC2_3 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -120,27 +120,27 @@ static const struct pad_config gpio_table[] = { /* USB2_OC6_7 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* DDPB_HPD0_C */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1_C */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2_C NC */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3_C NC */ PAD_CFG_NC(GPP_E16), +/* DDPD_HPD2_C NC */ PAD_NC(GPP_E15, NONE), +/* DDPE_HPD3_C NC */ PAD_NC(GPP_E16, NONE), /* EDP_HPD_C */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDAT */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDI2_DDC_SCL_L */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK NC */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDAT NC */ PAD_CFG_NC(GPP_E23), -/* NC */ PAD_CFG_NC(GPP_F0), -/* NC */ PAD_CFG_NC(GPP_F1), -/* NC */ PAD_CFG_NC(GPP_F2), -/* NC */ PAD_CFG_NC(GPP_F3), -/* NC */ PAD_CFG_NC(GPP_F4), -/* NC */ PAD_CFG_NC(GPP_F5), -/* NC */ PAD_CFG_NC(GPP_F6), -/* NC */ PAD_CFG_NC(GPP_F7), -/* NC */ PAD_CFG_NC(GPP_F8), -/* NC */ PAD_CFG_NC(GPP_F9), -/* NC */ PAD_CFG_NC(GPP_F10), -/* NC */ PAD_CFG_NC(GPP_F11), +/* DDI2_DDC_SDA_L */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK NC */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDAT NC */ PAD_NC(GPP_E23, NONE), +/* NC */ PAD_NC(GPP_F0, NONE), +/* NC */ PAD_NC(GPP_F1, NONE), +/* NC */ PAD_NC(GPP_F2, NONE), +/* NC */ PAD_NC(GPP_F3, NONE), +/* NC */ PAD_NC(GPP_F4, NONE), +/* NC */ PAD_NC(GPP_F5, NONE), +/* NC */ PAD_NC(GPP_F6, NONE), +/* NC */ PAD_NC(GPP_F7, NONE), +/* NC */ PAD_NC(GPP_F8, NONE), +/* NC */ PAD_NC(GPP_F9, NONE), +/* NC */ PAD_NC(GPP_F10, NONE), +/* NC */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_STROBE */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPP_F23 */ PAD_CFG_NC(GPP_F23), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_D0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_D1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_M_N */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* BIOS_RECOVERY NOT USED */ PAD_CFG_NC(GPD7), +/* BIOS_RECOVERY NOT USED */ PAD_NC(GPD7, NONE), /* CPU_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 21d322275e..607486be4c 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -31,69 +31,69 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP41 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP44 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP45 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP67 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP42 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* TP43 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), +/* SPKR */ PAD_NC(GPP_B14, NONE), /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), -/* SMBCLK */ PAD_CFG_NC(GPP_C0), -/* SMBDATA */ PAD_CFG_NC(GPP_C1), -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SMBCLK */ PAD_NC(GPP_C0, NONE), +/* SMBDATA */ PAD_NC(GPP_C1, NONE), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, @@ -109,59 +109,59 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ /* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, UP_20K, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */ /* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */ -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP48 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP244 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -176,8 +176,8 @@ static const struct pad_config gpio_table[] = { DEEP), /* DISPLAY is master */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* TP109 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -189,38 +189,38 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, 20K_PU, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, UP_20K, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP26 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP25 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP15 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ /* Ensure UART pins are in native mode for H1 */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index c6b0b01970..2ebc51ad04 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -7,46 +7,46 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, + EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -61,30 +61,30 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ -/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, UP_20K, DEEP), /* GPIO3 */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -96,55 +96,55 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ + PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP121 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP122 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP258 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -156,46 +156,46 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP191 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP192 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP190 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -204,20 +204,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -230,8 +230,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index d4be35fed3..add697f941 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -7,36 +7,36 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */ @@ -51,24 +51,24 @@ static const struct pad_config gpio_table[] = { /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */ /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP44 */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP98 */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP44 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP99 */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */ @@ -79,85 +79,85 @@ static const struct pad_config gpio_table[] = { /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP93 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP104 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP105 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP91 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP106 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP102 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP104 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP105 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP91 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP100 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP90 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP101 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP100 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP90 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP101 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, NONE), /* TPU_RST_PIN40 */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ /* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, NONE), /* TPU_RST_PIN42 */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP96 */ +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), /* T1037 */ +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* T1025 */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ +/* DDPD_HPD2 */ PAD_CFG_GPI_APIC_HIGH(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP43 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP48 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP42 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP37 */ -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP43 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP48 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP42 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP37 */ +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), /* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */ /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -166,20 +166,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP40 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP40 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP23 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP23 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP22 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP22 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP83 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP84 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP83 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP84 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 309222b4f9..2735fed671 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -7,35 +7,35 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), /* TP104 */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* TP104 */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), /* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_SPK_EN */ -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ /* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, @@ -44,8 +44,8 @@ static const struct pad_config gpio_table[] = { NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -60,29 +60,29 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* V3P3_CCD_EN */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -94,60 +94,59 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCH_I2C0_8625_SDA */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCH_I2C0_8625_SCL */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, - PLTRST), /* HP_IRQ_GPIO */ +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* PCH_DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* PCH_DMIC_DATA0 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* BOOT_BEEP_OVERRIDE */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, - PLTRST), /* TOUCHSCREEN_INT# */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, + NONE), /* TOUCHSCREEN_INT# */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -159,12 +158,12 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ @@ -177,53 +176,53 @@ static const struct pad_config gpio_table[] = { DEEP), /* I2S_2_FS_LRC */ /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S_2_TX_DAC */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -236,8 +235,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index b6743dc47b..b4c65baa90 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -48,138 +48,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -192,14 +192,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -207,16 +207,16 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 1f4bd6565a..24e7b33cc2 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -57,64 +57,64 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */ +/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* SD_CD_INT_L */ /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_CFG_GPI_SCI(GPP_B15, NONE, DEEP, EDGE_SINGLE, NONE), /* DIG EJECT */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -127,55 +127,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10), -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* TS_SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TS_SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -187,12 +187,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = { * SD write protect is not connected but is still sampled, so enable * native function and enable internal pull-down to disable. */ -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -224,16 +224,16 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index e1c2d585fe..7d000f5d6e 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -53,65 +53,65 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -123,55 +123,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), - PAD_CFG_NC(GPP_D9), - PAD_CFG_NC(GPP_D10), - PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21), -/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22), +/* TS_SPI_IO2 */ PAD_NC(GPP_D21, NONE), +/* TS_SPI_IO3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */ /* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */ -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NC(GPP_E22), - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -181,14 +181,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,24 +208,24 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1), - PAD_CFG_NC(GPD7), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, UP_20K, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, UP_20K, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, UP_20K, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, UP_20K, DEEP, NF1), + PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 06c6e4a8f7..6d415ca30a 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -47,51 +47,51 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* SM1ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ @@ -100,11 +100,11 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */ /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */ /* SML0ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */ -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -117,55 +117,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), /* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -175,13 +175,13 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), @@ -194,15 +194,15 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* RSVD */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -210,18 +210,18 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), /* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 5361744407..9ee00d2cf9 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -44,10 +44,10 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ /* GPP_A7 */ @@ -70,7 +70,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ /* GPP_B0 */ /* CORE_VID1 */ /* GPP_B1 */ /* VRALERT# */ /* GPP_B2 */ -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP), /* TRACKPAD */ /* CPU_GP3 */ /* GPP_B4 */ /* SRCCLKREQ0# */ /* GPP_B5 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ @@ -83,7 +83,7 @@ static const struct pad_config gpio_table[] = { /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ /* GPP_B14 */ /* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ /* GSPI0_MISO */ /* GPP_B17 */ /* GSPI0_MOSI */ /* GPP_B18 */ /* GSPI1_CS# */ /* GPP_B19 */ @@ -97,7 +97,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UART0_RXD */ /* GPP_C8 */ @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GPP_D0 */ /* GPP_D1 */ @@ -145,14 +145,14 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ /* GPP_E1 */ /* SATAXPCIE2 */ /* GPP_E2 */ /* CPU_GP0 */ /* GPP_E3 */ /* SATA_DEVSLP0 */ /* GPP_E4 */ /* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ /* SATALED# */ /* GPP_E8 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -160,8 +160,8 @@ static const struct pad_config gpio_table[] = { /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */ @@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* MIC_INT_L */ /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index d1785cea3c..3d00c353d7 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -43,124 +43,124 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* KEPLR_CLK_REQ */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_CLK_REQ */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), @@ -168,12 +168,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -186,14 +186,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -201,18 +201,18 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 60d93d4308..717e930d24 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -51,137 +51,137 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -201,7 +201,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -209,17 +209,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 3a15023894..d3ea6b537b 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -10,73 +10,73 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_A23, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_A23, NONE, DEEP, EDGE_SINGLE, INVERT), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -86,40 +86,40 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_C11), + PAD_NC(GPP_C11, NONE), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -133,9 +133,9 @@ static const struct pad_config gpio_table[] = { /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* C18 : I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_C18), + PAD_NC(GPP_C18, NONE), /* C19 : I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_C19), + PAD_NC(GPP_C19, NONE), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -143,24 +143,24 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D7, NONE, PLTRST), /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ PAD_CFG_GPO(GPP_D8, 0, DEEP), /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ @@ -172,9 +172,9 @@ static const struct pad_config gpio_table[] = { /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */ PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ @@ -184,30 +184,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> DISPLAY_DCR_EN */ PAD_CFG_GPO(GPP_E6, 1, DEEP), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -215,29 +215,29 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -246,7 +246,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */ @@ -260,7 +260,7 @@ static const struct pad_config gpio_table[] = { /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, UP_20K, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* F12 : EMMC_CMD */ @@ -286,7 +286,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -312,23 +312,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -392,14 +392,14 @@ static const struct pad_config ish_disabled_gpio_table[] = { /* A19 : GPP_A19 ==> TRACKPAD_INT_L * trackpad interrupt to PCH */ - PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A19, NONE, PLTRST), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 072b7618a0..dd97d1c6c4 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,30 +37,30 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */ @@ -68,54 +68,54 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> FP_INT */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C8, NONE, PLTRST), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ @@ -145,12 +145,12 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> EN_PP3300_DX_LTE */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D1 : SPI1_CLK ==> PEN_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP), /* D3 : SPI1_MOSI ==> PEN_RST_L */ @@ -162,23 +162,23 @@ static const struct pad_config gpio_table[] = { /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> PEN_EJECT_ODL -- for notification */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, UP_20K, DEEP), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> PEN_EJECT_ODL -- for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_D12, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> LTE_OFF_ODL */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D17 : DMIC_CLK1 */ @@ -197,23 +197,23 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config * __weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 62d1780c28..6dba783920 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -9,59 +9,59 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP22) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP24) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP15) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP23) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP46) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN#_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> PCH_SPK_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> NC(T3) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(T4) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */ @@ -71,15 +71,15 @@ static const struct pad_config gpio_table[] = { /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */ PAD_CFG_GPO(GPP_B9, 0, RSMRST), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> PM_SLP_R_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST#_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -89,34 +89,34 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(TP26) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(TP27) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(TP28) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(TP30) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SOC_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SOC_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC(TP917) */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ PAD_CFG_GPO(GPP_C7, 1, DEEP), /* C8 : UART0_RXD ==> NC(TP31) */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC(TP32) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */ @@ -142,44 +142,44 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> NC(TP926) */ - PAD_CFG_NC(GPP_C22), + PAD_NC(GPP_C22, NONE), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> PEN_IRQ# */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT# */ - PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D2, NONE, PLTRST), /* D3 : SPI1_MOSI ==> PEN_RST# */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ @@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_1_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> EMR_GARAGE_DET# - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E3, NONE, PLTRST), /* E4 : SATA_DEVSLP0 ==> BT_OFF# */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> EMR_GARAGE_DET# - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP), /* E9 : USB2_OCO# ==> USB_C0_OC# */ @@ -218,15 +218,15 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> DDR_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ @@ -238,9 +238,9 @@ static const struct pad_config gpio_table[] = { /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E22, NONE, DEEP, EDGE_SINGLE, INVERT), /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ @@ -250,7 +250,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -260,13 +260,13 @@ static const struct pad_config gpio_table[] = { /* F7 : I2C3_SCL ==> I2C_3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ - PAD_CFG_NC(GPP_F8), + PAD_NC(GPP_F8, NONE), /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ - PAD_CFG_NC(GPP_F9), + PAD_NC(GPP_F9, NONE), /* F10 : I2C5_SDA ==> NC */ - PAD_CFG_NC(GPP_F10), + PAD_NC(GPP_F10, NONE), /* F11 : I2C5_SCL ==> NC */ - PAD_CFG_NC(GPP_F11), + PAD_NC(GPP_F11, NONE), /* F12 : EMMC_CMD ==> EMMC_1_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ @@ -290,24 +290,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_1_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> NC */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 ==> NC */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 ==> NC */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 ==> NC */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 ==> NC */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# ==> NC */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK ==> NC */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP ==> SD_WP (not needed) */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -316,23 +316,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP44) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP41) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP38) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -353,13 +353,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, DN_20K, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -383,23 +383,23 @@ static const struct pad_config nami_default_sku_gpio_table[] = { static const struct pad_config no_dmic1_sku_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), }; static const struct pad_config pantheon_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), }; static const struct pad_config fpmcu_gpio_table[] = { /* B0 : CORE_VID0 ==> FPMCU_INT_L */ - PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_B0, NONE, DEEP), /* B1 : CORE_VID1 ==> FPMCU_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ @@ -417,7 +417,7 @@ static const struct pad_config fpmcu_gpio_table[] = { /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 555b532b2c..37378f93a7 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -9,25 +9,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -38,81 +38,81 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A21, NONE, PLTRST), /* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A22, NONE, PLTRST), /* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP722) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> CHP3_TP_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT3_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* B20 : GSPI1_CLK ==> LTE3_STRAP# - for SAR sensor presence */ - PAD_CFG_GPI(GPP_B20, 20K_PD, DEEP), + PAD_CFG_GPI(GPP_B20, DN_20K, DEEP), /* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE), + PAD_CFG_GPI_SCI(GPP_B21, NONE, DEEP, EDGE_SINGLE, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> CHP3_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> CHP3_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> CPU3_EC_IN_RW */ - PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ @@ -144,38 +144,38 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> NC */ - PAD_CFG_NC(GPP_D10), + PAD_NC(GPP_D10, NONE), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,51 +190,51 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB3_C1_OC1_L */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */ - PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP766) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> CHP1_CABC */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */ @@ -244,15 +244,15 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */ - PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, UP_5K, DEEP, NF1), /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */ - PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, UP_5K, DEEP, NF1), /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */ @@ -284,7 +284,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -301,7 +301,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> CHP3_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -310,23 +310,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> CHP3_SLPS3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> CHP3_SLPS4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP725) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> CHP3_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP724) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP742) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -343,10 +343,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -363,20 +363,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num) static const struct pad_config nautilus_default_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ - PAD_CFG_NF(GPP_E11, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E11, UP_5K, DEEP, NF1), }; static const struct pad_config lte_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> LTE1_P_SENSOR_INT_L */ - PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_A18, NONE, DEEP), /* D0 : SPI1_CS# ==> LTE_PWROFF# */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */ diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index d5888dd6f2..f5344584ba 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -8,60 +8,60 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0_R */ /* A2 : ESPI_IO1_R */ /* A3 : ESPI_IO2_R */ /* A4 : ESPI_IO3_R */ /* A5 : ESPI_CS_L_R */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK_R */ - PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : ISH_GP6 */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : SPKR_RST_L */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), /* A20 : ISH_GP2 ==> ISH_UART0_RXD */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* B1 : CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> FCAM_PWR_EN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B6, NONE, DEEP), /* B7 : SRCCLKREQ2# ==> PCIE_NVME_CLKREQ_ODL */ @@ -69,17 +69,17 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* B19 : GSPI1_CS# ==> PCH_FPMCU_SPI_CS_L_R */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_FPMCU_SPI_CLK_R */ @@ -97,32 +97,32 @@ static const struct pad_config gpio_table[] = { /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SM1ALERT# ==> PCHHOT# */ - PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# */ - PAD_CFG_NF(GPP_C5, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_C5, DN_20K, DEEP, NF1), /* C6 : SM1CLK ==> EC_IN_RW_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> FPMCU_INT */ - PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, EDGE_SINGLE, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C11, UP_20K, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -146,34 +146,34 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> RCAM_PWR_EN */ PAD_CFG_GPO(GPP_D7, 0, DEEP), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> PCH_FCAM_CLK_EN */ PAD_CFG_GPO(GPP_D13, 0, DEEP), /* D14 : ISH_UART0_TXD ==> PCH_RCAM_CLK_EN */ @@ -183,46 +183,46 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> NC */ - PAD_CFG_NC(GPP_D23), + PAD_NC(GPP_D23, NONE), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> WLAN_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E3 : DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ - PAD_CFG_TERM_GPO(GPP_E11, 0, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 0, DN_20K, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ @@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = { /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD_3V3 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> DDPB_CTRLDATA */ - PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> DDPC_CTRLDATA */ - PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -253,11 +253,11 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> NC */ - PAD_CFG_NC(GPP_F4), + PAD_NC(GPP_F4, NONE), /* F5 : I2C2_SCL ==> NC */ - PAD_CFG_NC(GPP_F5), + PAD_NC(GPP_F5, NONE), /* F6 : I2C3_SDA ==> PCH_I2C3_FCAM_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_FCAM_1V8_SCL */ @@ -293,24 +293,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -350,7 +350,7 @@ static const struct pad_config early_gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ @@ -359,10 +359,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 9bb497ec95..8e9e5c01c5 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(T0804) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(T0805) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(T0501) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(T0806) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(T0913) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,48 +37,48 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> TRACKPAD_INT_L for wakeup event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -88,38 +88,38 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(T0807) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(T0808) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(T0809) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(T0810) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> BT_OFF# */ PAD_CFG_GPO(GPP_C8, 1, DEEP), /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC(T0817) */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ @@ -145,105 +145,105 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC(T0818) */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC(T0819) */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC(T0820) */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC(T0815) */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC(T0816) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : ISH_UART0_CTS# ==> DMIC_CLK1_PCH */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 ==> NC(T0703) */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> DMIC_CLK0_PCH */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> DMIC_DATA0_PCH */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN I2C OPERATION ENABLE/DISABLE. */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> NC(T0504) */ - PAD_CFG_NC(GPP_E11), + PAD_NC(GPP_E11, NONE), /* E12 : USB2_OC3# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD_ODL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(T0602) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK ==> SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP ==> NC(T0701) */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(T0912) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(T0911) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(T0905) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -356,10 +356,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 33bdb290e1..9d52773271 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,87 +37,87 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ @@ -145,42 +145,42 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,30 +190,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 3 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -354,10 +354,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index cd15fed084..da2175d669 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -12,15 +12,15 @@ static const struct pad_config gpio_table[] = { /* GPP_A0 - ESPI_ALERT1# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), /* GPP_A1 - ESPI_IO0 */ - PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), /* GPP_A2 - ESPI_IO1 */ - PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), /* GPP_A3 - ESPI_IO2 */ - PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), /* GPP_A4 - ESPI_IO3 */ - PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), /* GPP_A5 - ESPI_CS0# */ - PAD_CFG_NF(GPP_A5, 20K_PU, DEEP, NF3), + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF3), /* GPP_A6 - ESPI_CS1# */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), /* GPP_A7 - ESPI_ALERT0# */ @@ -28,7 +28,7 @@ static const struct pad_config gpio_table[] = { /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - ESPI_CLK */ - PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* GPP_A10 - CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* GPP_A11 - GPIO */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index 0417543d31..4f7f002bff 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -60,7 +60,7 @@ static const struct pad_config gpio_table[] = { /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* EC_HID_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), /* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), @@ -72,14 +72,14 @@ static const struct pad_config gpio_table[] = { /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* GPP_A23 */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), /* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP), /* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP), /* HSJ_MIC_DET */ /* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), -/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* M.2 BT UART wake */ PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP), /* WIFI_CLK_REQ */ /* KEPLR_CLK_REQ */ /* SRCCLKREQ3# */ /* GPP_B8 */ @@ -88,9 +88,9 @@ static const struct pad_config gpio_table[] = { /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES), +/* GPP_B_14_SPKR */ PAD_CFG_GPI_SMI(GPP_B14, NONE, DEEP, EDGE_SINGLE, INVERT), /* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP), /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), @@ -167,14 +167,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), /* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP), /* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP), -/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP), +/* I2C2_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, DEEP), /* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP), /* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP), /* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP), -/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F9, NONE, DEEP), /* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP), /* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), -/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES), +/* EMMC_CMD */ PAD_CFG_GPI_SCI(GPP_F12, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), /* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), /* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), @@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = { /* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), /* GPP_F23 */ -/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP), +/* SD_CMD */ PAD_CFG_GPI_APIC_HIGH(GPP_G0, DN_20K, DEEP), /* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* SD_DATA2 */ PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT), /* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), -/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP), +/* SD_WP */ PAD_CFG_GPI_APIC_HIGH(GPP_G7, NONE, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP), -/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* TBD */ PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT), /* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), /* TBD */ /* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP), -/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES), +/* TBD */ PAD_CFG_GPI_SCI(GPP_G18, NONE, DEEP, EDGE_SINGLE, INVERT), /* TBD */ /* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP), -/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP), +/* TBD */ PAD_CFG_GPI_APIC_HIGH(GPP_G21, DN_20K, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP), /* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP), @@ -240,7 +240,7 @@ static const struct pad_config gpio_table[] = { /* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), -/* DDSP_HPD_3 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDSP_HPD_3 */ PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT), /* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), /* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index 1ed86b74f9..e0292cfa86 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -28,35 +28,35 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, DN_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, DN_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, DN_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, DN_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), -/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), -/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* V0.85A_VID0 */ PAD_NC(GPP_B0, NONE), +/* V0.85A_VID1 */ PAD_NC(GPP_B1, NONE), /* GP_VRALERTB */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT0 */ PAD_NC(GPP_B5, NONE), /* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), @@ -67,22 +67,22 @@ static const struct pad_config gpio_table[] = { /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), /* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* TBT_CIO */ PAD_CFG_NC(GPP_B17), -/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* TBT_CIO */ PAD_NC(GPP_B17, NONE), +/* SLOT1_WAKE */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, PLTRST), /* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), @@ -91,8 +91,8 @@ static const struct pad_config gpio_table[] = { /* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -117,35 +117,35 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), /* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP), /* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, PLTRST), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), @@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* UIM_SIM_DET */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -186,7 +186,7 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index 4ead52c282..ff4647f1d2 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -48,10 +48,10 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), /* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), @@ -59,33 +59,33 @@ static const struct pad_config gpio_table[] = { /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* ISH_GP5 */ PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC_HIGH(GPP_B5, NONE, DEEP), /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES), -/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES), -/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES), +/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, PLTRST, EDGE_SINGLE, INVERT), +/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_SCI(GPP_B17, UP_20K, PLTRST, EDGE_SINGLE, INVERT), +/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, EDGE_SINGLE, INVERT), /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), /* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_HIGH(GPP_C5, DN_20K, DEEP), /* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, DN_20K, DEEP, NF1), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), @@ -120,13 +120,13 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), /* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, DN_20K, DEEP), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SSD_PEDET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST), @@ -138,15 +138,15 @@ static const struct pad_config gpio_table[] = { /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), -/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), /* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), @@ -170,7 +170,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -182,7 +182,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index b2d72c6c9c..37193cfcda 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -44,28 +44,28 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), -/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), -/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), -/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), -/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), +/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3), +/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF3), +/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF3), +/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF3), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), /* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), /* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), /* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), /* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), +/* PCHHOTB */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), @@ -85,8 +85,8 @@ static const struct pad_config gpio_table[] = { /* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), -/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), /* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), @@ -94,14 +94,14 @@ static const struct pad_config gpio_table[] = { /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), -/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1), -/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES), +/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, UP_20K, DEEP,NF1), +/* SATA_DEVSLP_3 */ PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, INVERT), /* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), -/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* SATA_SCLOCK */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), -/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP), -/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP), -/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP), +/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC_HIGH(GPP_F12, NONE, DEEP), +/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, DEEP), +/* H_SKTOCC_N */ PAD_CFG_GPI_APIC_HIGH(GPP_F14, NONE, DEEP), /* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), @@ -110,44 +110,44 @@ static const struct pad_config gpio_table[] = { /* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), /* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), /* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), -/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), -/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* FAN_TACH_2 */ PAD_CFG_GPI_SCI(GPP_G2, NONE, DEEP, EDGE_SINGLE, INVERT), +/* FAN_TACH_3 */ PAD_CFG_GPI_SCI(GPP_G3, NONE, DEEP, EDGE_SINGLE, INVERT), /* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), -/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP), -/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES), +/* FAN_TACH_5 */ PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, DEEP), +/* FAN_TACH_6 */ PAD_CFG_GPI_SCI(GPP_G6, NONE, DEEP, EDGE_SINGLE, INVERT), /* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), -/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* GSXDOUT */ PAD_CFG_GPI_SCI(GPP_G12, DN_20K, DEEP, EDGE_SINGLE, INVERT), /* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), -/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES), +/* GSXDIN */ PAD_CFG_GPI_SCI(GPP_G14, NONE, DEEP, EDGE_SINGLE, INVERT), /* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), /* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), -/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP), +/* NMIB */ PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, DEEP), /* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), -/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP), -/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), +/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, DEEP), +/* P_INTF_N */ PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), /* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), /* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), /* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), /* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), -/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP), -/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP), -/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP), +/* SML3CLK */ PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, DEEP), +/* SML3DATA */ PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, DEEP), +/* SML3ALERTB */ PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, DEEP), /* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), /* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), /* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), -/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDSP_HPD_1 */ PAD_CFG_GPI_SMI(GPP_I3, NONE, DEEP, EDGE_SINGLE, INVERT), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, DN_20K, DEEP, NF1), /* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), -/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 3317f113e7..2cd0196137 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -51,138 +51,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -210,17 +210,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index 255f278db3..a574ac589d 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -75,7 +75,7 @@ static const struct pad_config gpio_table[] = { /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), /* GSPI0_CS# */ /* GPP_B15 */ /* WLAN_PCIE_WAKE */ /* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), @@ -84,11 +84,11 @@ static const struct pad_config gpio_table[] = { /* CODEC_SPI_CLK */ /* CODEC_SPI_MISO */ /* CODEC_SPI_MOSI */ -/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF1), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, DN_20K, DEEP, NF1), /* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0ALERT# */ /* GPP_C5 */ diff --git a/src/mainboard/kontron/bsl6/gpio.h b/src/mainboard/kontron/bsl6/gpio.h index a76c9679b9..d6e976ee10 100644 --- a/src/mainboard/kontron/bsl6/gpio.h +++ b/src/mainboard/kontron/bsl6/gpio.h @@ -11,21 +11,21 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), - PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), - PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), - PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), - PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), PAD_CFG_GPO(GPP_A12, 1, PLTRST), PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), PAD_CFG_GPO(GPP_B17, 1, DEEP), @@ -58,11 +58,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), - PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PU, DEEP), + PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPI_ACPI_SCI(GPP_C2, NONE, DEEP, YES), + PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), @@ -110,14 +110,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_D22, 0, DEEP), PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), - PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), - PAD_CFG_GPI_ACPI_SCI(GPP_E7, NONE, DEEP, YES), + PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -125,20 +125,20 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), - PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, NONE), + PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), - PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), - PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), @@ -154,23 +154,23 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), PAD_CFG_GPO(GPP_G4, 1, DEEP), - PAD_CFG_GPI_APIC(GPP_G5, NONE, PLTRST), - PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, PLTRST, YES), + PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), PAD_CFG_GPO(GPP_G7, 1, DEEP), PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), - PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, PLTRST, YES), + PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), PAD_CFG_GPO(GPP_G13, 1, PLTRST), - PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, PLTRST, YES), + PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), PAD_CFG_GPO(GPP_G15, 0, PLTRST), - PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), - PAD_CFG_GPI_APIC(GPP_G20, NONE, PLTRST), - PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), + PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), PAD_CFG_GPO(GPP_G22, 1, PLTRST), PAD_CFG_GPO(GPP_G23, 1, PLTRST), @@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), - PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), - PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), PAD_CFG_GPO(GPP_H17, 1, PLTRST), PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), @@ -202,7 +202,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), PAD_CFG_GPO(GPD1, 0, PWROK), PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), PAD_CFG_NF(GPD4, NONE, PWROK, NF1), PAD_CFG_NF(GPD5, NONE, PWROK, NF1), PAD_CFG_NF(GPD6, NONE, PWROK, NF1), diff --git a/src/mainboard/libretrend/lt1000/gpio.h b/src/mainboard/libretrend/lt1000/gpio.h index fde917efd9..7e0e0a7348 100644 --- a/src/mainboard/libretrend/lt1000/gpio.h +++ b/src/mainboard/libretrend/lt1000/gpio.h @@ -17,46 +17,46 @@ static const struct pad_config gpio_table[] = { /* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP), /* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), @@ -65,100 +65,100 @@ static const struct pad_config gpio_table[] = { /* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), -/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ -/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* SML0ALERT# */ PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), +/* SML1CLK */ PAD_NC(GPP_C6, NONE), /* RESERVED */ +/* SML1DATA */ PAD_NC(GPP_C7, NONE), /* RESERVED */ /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_NC(GPP_C14, NONE), +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), /* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), /* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), -/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_NC(GPP_C23, NONE), -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), /* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), /* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), -/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), /* SATAXPCI0 */ PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), /* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), /* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -169,14 +169,14 @@ static const struct pad_config gpio_table[] = { /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), -/* BATLOW# */ PAD_CFG_NC(GPD0), +/* BATLOW# */ PAD_NC(GPD0, NONE), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NC(GPD2), +/* LAN_WAKE# */ PAD_NC(GPD2, NONE), /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index d4b57fa49a..a8a22711d6 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -8,7 +8,6 @@ config BOARD_PRODRIVE_HERMES_BASEBOARD select SUPERIO_ASPEED_AST2400 select DRIVERS_ASPEED_AST_COMMON select DRIVERS_ASPEED_AST2050 - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h index 4af4b1476a..7ec5a8a62b 100644 --- a/src/mainboard/protectli/vault_kbl/gpio.h +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -11,21 +11,21 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* ISH_GP6 */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -48,7 +48,7 @@ static const struct pad_config gpio_table[] = { /* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), @@ -123,7 +123,7 @@ static const struct pad_config gpio_table[] = { /* DDI4_HPD */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_NC(GPP_E17, NONE), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -163,7 +163,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_NC(GPD0, NONE), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE_N */ PAD_NC(GPD2, NONE), -/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), diff --git a/src/mainboard/purism/librem_skl/gpio.h b/src/mainboard/purism/librem_skl/gpio.h index b6ec486325..240205b0e5 100644 --- a/src/mainboard/purism/librem_skl/gpio.h +++ b/src/mainboard/purism/librem_skl/gpio.h @@ -17,47 +17,47 @@ static const struct pad_config gpio_table[] = { /* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A18, NONE, DEEP), /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* ISH_GP2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A20, NONE, DEEP), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16), -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), /* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), @@ -66,100 +66,100 @@ static const struct pad_config gpio_table[] = { /* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), /* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), -/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ -/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* SML0ALERT# */ PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), +/* SML1CLK */ PAD_NC(GPP_C6, NONE), /* RESERVED */ +/* SML1DATA */ PAD_NC(GPP_C7, NONE), /* RESERVED */ /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NC(GPP_C12), -/* UART1_TXD */ PAD_CFG_NC(GPP_C13), -/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), -/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_NC(GPP_C14, NONE), +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C16, NONE, DEEP), /* I2C0_SCL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C17, NONE, DEEP), /* I2C1_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C18, NONE, DEEP), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NC(GPP_C20), -/* UART2_TXD */ PAD_CFG_NC(GPP_C21), -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), -/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_NC(GPP_C23, NONE), -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP), -/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, DN_20K, DEEP, NF1), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, DN_20K, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), -/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), -/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCI0 */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE), +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC_HIGH(GPP_E22, NONE, DEEP), /* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* I2C5_SDA */ PAD_CFG_NC(GPP_F10), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -170,14 +170,14 @@ static const struct pad_config gpio_table[] = { /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), -/* BATLOW# */ PAD_CFG_NC(GPD0), +/* BATLOW# */ PAD_NC(GPD0, NONE), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), -/* LAN_WAKE# */ PAD_CFG_NC(GPD2), +/* LAN_WAKE# */ PAD_NC(GPD2, NONE), /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 1ba1ad9e2a..6b29a2ccd6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -19,13 +19,13 @@ static const struct pad_config gpio_table[] = { /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), @@ -48,22 +48,22 @@ static const struct pad_config gpio_table[] = { /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), +/* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), +/* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), @@ -116,8 +116,8 @@ static const struct pad_config gpio_table[] = { /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), @@ -125,11 +125,11 @@ static const struct pad_config gpio_table[] = { /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(20K_PD)), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index bbaad7d8c6..a6db277891 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C19, NONE), PAD_NC(GPP_C20, NONE), PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_C23, NONE), /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), PAD_CFG_GPO(GPP_D1, 1, DEEP), - PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_D3, NONE), PAD_CFG_GPO(GPP_D4, 0, PLTRST), PAD_NC(GPP_D5, NONE), @@ -116,7 +116,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), PAD_NC(GPP_E7, NONE), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), @@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F2, NONE), PAD_NC(GPP_F3, NONE), PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), PAD_CFG_GPO(GPP_F6, 1, PLTRST), PAD_CFG_GPO(GPP_F7, 1, PLTRST), PAD_CFG_GPO(GPP_F8, 1, PLTRST), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index f5e71ad45e..8c9d08e5ef 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -82,13 +82,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C19, NONE), PAD_NC(GPP_C20, NONE), PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_C23, NONE), /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), - PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_D3, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), PAD_NC(GPP_D5, NONE), @@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), PAD_NC(GPP_E7, NONE), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), @@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F2, NONE), PAD_NC(GPP_F3, NONE), PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 753d8e0a7e..7e8970646f 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -24,11 +24,6 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY bool default n -# Used to provide support for legacy macros -config SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS - bool - default n - # Indicate if multiple ACPI devices are used for each gpio community. config SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES bool diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 31bbde0ce2..422720b921 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -302,40 +302,12 @@ PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) - -#define PAD_CFG_GPI_APIC(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) - -#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) - -#define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ - PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - -#define PAD_CFG_GPI_ACPI_SMI(pad, pull, rst, inv) \ - PAD_CFG_GPI_SMI(pad, pull, rst, EDGE_SINGLE, inv) - -#define PAD_CFG_NC(pad) PAD_NC(pad, NONE) - -#define PAD_CFG1_PULL_20K_PU PAD_CFG1_PULL_UP_20K -#define PAD_CFG1_PULL_5K_PU PAD_CFG1_PULL_UP_5K -#define PAD_CFG1_PULL_20K_PD PAD_CFG1_PULL_DN_20K -#define PAD_CFG0_TRIG_EDGE PAD_CFG0_TRIG_EDGE_SINGLE -#define PAD_CFG0_RX_POL_YES PAD_CFG0_RX_POL_INVERT - -#else /* General purpose input, routed to APIC */ #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) -#endif /* General purpose input, routed to APIC - with IOStandby Config*/ #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 55e74cd360..2478113c35 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -51,7 +51,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index e449409c4f..a83a3c3572 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -47,7 +47,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER From 8fed9d638dcb7ce89880714eb58373205722f749 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 21 Oct 2020 11:33:53 +0200 Subject: [PATCH 158/354] mb/supermicro/x11-lga1151-series: Follow up GPIO macro changes Following commit f50ea988b a couple of symbols are gone, so follow up that change for this board as well. Change-Id: I09fd3a107447eb45bb46b7f0f821377943f140b2 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/46621 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../variants/x11ssh-f/include/variant/gpio.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h index 93e0574409..449349dc6c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h @@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C19, NONE), PAD_NC(GPP_C20, NONE), PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_C23, NONE), /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), PAD_CFG_GPO(GPP_D1, 1, DEEP), - PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_D3, NONE), PAD_CFG_GPO(GPP_D4, 0, PLTRST), PAD_NC(GPP_D5, NONE), @@ -116,7 +116,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E4, NONE), PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), PAD_NC(GPP_E7, NONE), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), @@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F2, NONE), PAD_NC(GPP_F3, NONE), PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), PAD_CFG_GPO(GPP_F6, 1, PLTRST), PAD_CFG_GPO(GPP_F7, 1, PLTRST), PAD_CFG_GPO(GPP_F8, 1, PLTRST), From 2ac743330c2668abae9eb1d5a01ad1b86ba918a9 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 7 Mar 2020 11:15:03 +0100 Subject: [PATCH 159/354] mb/asus/f2a85-m_pro: Enable UART A in Super I/O MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, the serial console does not work. With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below. Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40. Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`. coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31 APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET `AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues. PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 […] done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... CPU_CLUSTER: 0 init […] Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits. TEST=Receive (some) coreboot log messages over the serial console. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/f2a85-m/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 8413cd3863..27d5517b9f 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO + select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA From 63032439f4278125b3a01d33d056761dd1ae8cba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 17:34:54 +0200 Subject: [PATCH 160/354] {cpu,soc}/intel: replace AES-NI locking by common implemenation call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deduplicate code by using the new common cpu code implementation of AES-NI locking. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_2065x/model_2065x_init.c | 6 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 6 +---- src/include/cpu/intel/msr.h | 1 + src/soc/intel/apollolake/cpu.c | 10 ++++----- src/soc/intel/common/block/cpu/cpulib.c | 1 + .../common/block/include/intelblocks/msr.h | 3 --- src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/denverton_ns/cpu.c | 8 ++----- src/soc/intel/skylake/cpu.c | 22 +------------------ 9 files changed, 12 insertions(+), 46 deletions(-) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index b4a91ea658..65b28c0a0e 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -216,11 +216,7 @@ static void model_2065x_init(struct device *cpu) /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); - if (!intel_ht_sibling()) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - } + set_aesni_lock(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d23772a23f..5af5ff905e 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -470,11 +470,7 @@ static void model_206ax_init(struct device *cpu) /* Thermal throttle activation offset */ configure_thermal_target(); - if (!intel_ht_sibling()) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - } + set_aesni_lock(); /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 0d11b5eece..51b73950d6 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -6,6 +6,7 @@ */ #define MSR_FEATURE_CONFIG 0x13c +#define AESNI_DISABLE (1 << 1) #define AESNI_LOCK (1 << 0) #endif /* CPU_INTEL_MSR_H */ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 72f983f3dd..0ae170b44d 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -43,12 +44,6 @@ static const struct reg_script core_msr_script[] = { #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), - /* - * Enable and Lock the Advanced Encryption Standard (AES-NI) - * feature register - */ - REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, - FEATURE_CONFIG_LOCK), REG_SCRIPT_END }; @@ -62,6 +57,9 @@ void soc_core_init(struct device *cpu) /* Set core MSRs */ reg_script_run(core_msr_script); + + set_aesni_lock(); + /* * Enable ACPI PM timer emulation, which also lets microcode know * location of ACPI_BASE_ADDRESS. This also enables other features diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9092df1796..854da2ea1e 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 2ef4561341..2e12bf071d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -24,9 +24,6 @@ #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_VALUE 0x13 -#define MSR_FEATURE_CONFIG 0x13c -#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL -#define FEATURE_CONFIG_LOCK (1 << 0) #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 798d473cad..89bbbb0c45 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b1eda9b54d..7cee5be39d 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -59,12 +60,7 @@ static void denverton_core_init(struct device *cpu) msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) { - msr = rdmsr(MSR_FEATURE_CONFIG); - msr.lo |= FEATURE_CONFIG_LOCK; /* Lock AES-NI */ - wrmsr(MSR_FEATURE_CONFIG, msr); - } + set_aesni_lock(); /* Enable Turbo */ enable_turbo(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5ec002322b..e716c66620 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -186,25 +186,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -/* - * Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling - * as suggested in Intel document 325384-070US. - */ -static void cpu_lock_aesni(void) -{ - msr_t msr; - - /* Only run once per core as specified in the MSR datasheet */ - if (intel_ht_sibling()) - return; - - msr = rdmsr(MSR_FEATURE_CONFIG); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; - wrmsr(MSR_FEATURE_CONFIG, msr); - } -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -227,8 +208,7 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); - /* Lock AES-NI MSR */ - cpu_lock_aesni(); + set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); From fb620109a4dc96f4cba47a24fe93cd954dba902a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:04:36 +0200 Subject: [PATCH 161/354] mb/google/dedede: drop obsolete ISST workaround MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early JSL silicon hang while booting Linux with ISST enabled. The malfunctioning silicon revisions have been used only for development purposes and have been phased out. Thus, drop the ISST workaround. Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Nico Huber --- src/mainboard/google/dedede/mainboard.c | 16 ---------------- .../baseboard/include/baseboard/variants.h | 3 --- .../dedede/variants/waddledee/Makefile.inc | 1 - .../google/dedede/variants/waddledee/variant.c | 16 ---------------- .../dedede/variants/waddledoo/Makefile.inc | 2 -- .../google/dedede/variants/waddledoo/variant.c | 16 ---------------- 6 files changed, 54 deletions(-) delete mode 100644 src/mainboard/google/dedede/variants/waddledee/variant.c delete mode 100644 src/mainboard/google/dedede/variants/waddledoo/variant.c diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index 45b25809cd..23b15969c8 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -29,19 +29,6 @@ static void mainboard_update_soc_chip_config(void) } } -__weak void variant_isst_override(void) -{ - /* - * Implement the override only if the board uses very early/initial revisions of - * Silicon. Otherwise nothing to override. - */ -} - -static void mainboard_config_isst(void *unused) -{ - variant_isst_override(); -} - static void mainboard_init(void *chip_info) { const struct pad_config *base_pads; @@ -79,6 +66,3 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, }; - -/* Configure ISST before CPU initialization */ -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_config_isst, NULL); diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bd94ef4df3..dc855c63cd 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,7 +36,4 @@ int variant_memory_sku(void); */ bool variant_mem_is_half_populated(void); -/* Variant Intel Speed Shift Technology override */ -void variant_isst_override(void); - #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index 93f34f81e0..e835c698be 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -3,4 +3,3 @@ romstage-y += memory.c ramstage-y += gpio.c -ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledee/variant.c b/src/mainboard/google/dedede/variants/waddledee/variant.c deleted file mode 100644 index ac3cf581d9..0000000000 --- a/src/mainboard/google/dedede/variants/waddledee/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index eda535c992..566f5cc767 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,5 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-or-later romstage-y += memory.c - -ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/variant.c b/src/mainboard/google/dedede/variants/waddledoo/variant.c deleted file mode 100644 index ac3cf581d9..0000000000 --- a/src/mainboard/google/dedede/variants/waddledoo/variant.c +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void variant_isst_override(void) -{ - config_t *cfg = config_of_soc(); - uint32_t board_ver; - - /* Override/Disable ISST in boards where board version is not populated. */ - if (google_chromeec_get_board_version(&board_ver)) - cfg->speed_shift_enable = 0; -} From 0088b3df28938d03039e78a780508d5351adea13 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Fri, 16 Oct 2020 00:29:36 +0800 Subject: [PATCH 162/354] mb/google/zork: Update telemetry settings for morphius Correct the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. BUG=b:168265881 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472 Reviewed-by: Martin Roth Reviewed-by: Chris Wang Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/morphius/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 43a94390a3..ecadb072c1 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -16,9 +16,9 @@ chip soc/amd/picasso register "sustained_power_limit" = "12000" #mw register "thermctl_limit" = "100" #degrees C - register "telemetry_vddcr_vdd_slope" = "78709" #mA + register "telemetry_vddcr_vdd_slope" = "62852" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29035" #mA + register "telemetry_vddcr_soc_slope" = "28022" #mA register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode From 9cc148d8c50df689e6647132746026c3354a2700 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Sun, 18 Oct 2020 17:19:22 +0800 Subject: [PATCH 163/354] mb/google/zork: update USB 2.0 controller Lane Parameter for morphius Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level" and "Disconnect Threshold Adjustment". COMPDISTUNE0: 0x3->0x7 TXVREFTUNE0: 0x6->0xf BUG=b:162614573 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 registers are set correctly 3. test with servo v4 type-c, it's working expectedly. 4. U2 SI pass Signed-off-by: Kevin Chiu Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537 Reviewed-by: Rob Barnes Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../google/zork/variants/morphius/overridetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index ecadb072c1..66b371be04 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -35,6 +35,19 @@ chip soc/amd/picasso .ports.xhci0_port2 = 1, /* Left USB3A port 2 */ }" + # USB 2.0 strength + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, From 4fc4a37038c9dffc7bec603af9e787a269e65dbf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 20 Oct 2020 15:41:51 +0200 Subject: [PATCH 164/354] 3rdparty/amd_blobs: update submodule pointer This now tracks a recently created upstream repository located at https://github.com/amd/firmware_binaries BUG=b:166107781 Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- 3rdparty/amd_blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index e393a885c8..8c668ab552 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d +Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b From 947dc64d21e75af94bfddb36ad6b921d47a1e453 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sun, 4 Oct 2020 01:15:19 +0200 Subject: [PATCH 165/354] mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree The mainboard has a PS/2 port, so enable the keyboard controller in the devicetree. The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux, probably as ACPI code still needs to be added. Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/45998 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 2aa2d89b08..c9de54c05c 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -37,7 +37,12 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0x70 = 4 end device pnp 2e.3 off end # COM2/IR - device pnp 2e.5 off end # Keyboard + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 + irq 0x72 = 12 + end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 io 0xe0 = 0x7f From 9f7b36a540a89a594bcdeeda77be82801cb8b88d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 14:42:08 +0200 Subject: [PATCH 166/354] mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers The `io` statement will prepare a 16-bit write, hence use `irq` for miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge 0x61 writes into 0x60). Note, using `irq` is still just a hack as these are neither I/O nor IRQs, but it's common practice in coreboot. Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 124 +++++++++--------- 1 file changed, 61 insertions(+), 63 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index c9de54c05c..c05857f6d0 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,83 +45,81 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - io 0xe0 = 0x7f - io 0xe1 = 0x10 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0xff - io 0xe5 = 0xff - io 0xe6 = 0xff - io 0xe7 = 0xff - io 0xec = 0x00 - io 0xed = 0xff - io 0xf4 = 0xff - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xf8 = 0x00 + irq 0xe0 = 0x7f + irq 0xe1 = 0x10 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0xff + irq 0xe5 = 0xff + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xec = 0x00 + irq 0xed = 0xff + irq 0xf4 = 0xff + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x00 end device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - io 0x30 = 0x00 - io 0x60 = 0x00 - io 0x61 = 0x00 - io 0xe0 = 0xff - io 0xe1 = 0xff - io 0xe2 = 0xff - io 0xe3 = 0xff - io 0xe4 = 0xff - io 0xf0 = 0xff - io 0xf1 = 0x28 - io 0xf2 = 0x00 - io 0xf3 = 0x00 - io 0xf4 = 0x08 - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0xff + irq 0x30 = 0x00 + io 0x60 = 0x00 + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe4 = 0xff + irq 0xf0 = 0xff + irq 0xf1 = 0x28 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x08 + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0xff end device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - io 0x30 = 0xfe - io 0xe0 = 0xff - io 0xe1 = 0x90 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0x7f - io 0xe5 = 0x76 - io 0xe6 = 0x00 - io 0xe7 = 0x00 - io 0xe8 = 0x00 - io 0xe9 = 0x00 - io 0xea = 0x00 - io 0xeb = 0x00 - io 0xee = 0x00 - io 0xf0 = 0xff - io 0xf1 = 0x7b - io 0xf2 = 0x00 - io 0xf4 = 0xff - io 0xf5 = 0xef - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xfe = 0x00 + irq 0x30 = 0xfe + irq 0xe0 = 0xff + irq 0xe1 = 0x90 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0x7f + irq 0xe5 = 0x76 + irq 0xe6 = 0x00 + irq 0xe7 = 0x00 + irq 0xe8 = 0x00 + irq 0xe9 = 0x00 + irq 0xea = 0x00 + irq 0xeb = 0x00 + irq 0xee = 0x00 + irq 0xf0 = 0xff + irq 0xf1 = 0x7b + irq 0xf2 = 0x00 + irq 0xf4 = 0xff + irq 0xf5 = 0xef + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xfe = 0x00 end device pnp 2e.a on # ACPI - io 0xe6 = 0x4c - io 0xe7 = 0x11 - io 0xf2 = 0x5d + irq 0xe6 = 0x4c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x30 = 0x01 - io 0x60 = 0x02 - io 0x61 = 0x90 - io 0xe2 = 0x7f - io 0xe4 = 0xf1 + irq 0x30 = 0x01 + io 0x60 = 0x0290 + irq 0xe2 = 0x7f + irq 0xe4 = 0xf1 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f off # GPIO Push-pull/Open-drain selection - io 0xe6 = 7f + irq 0xe6 = 7f end device pnp 2e.14 off # PORT80 UART - io 0xe0 = 0x00 + irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep end From 2a507f734ed54bddd3381638bfc588bc84c301d1 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 4 Oct 2020 15:00:04 +0200 Subject: [PATCH 167/354] mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off The 0x30 register is eventually controlled by coreboot's pnp_enable_resources() based on the on/off setting. Other register settings were grouped with their respective "virtual" LDN, where possible. Note, this temporarily breaks LDN 8 settings, as coreboot will ignore configuration for disabled devices. Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46014 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../asus/f2a85-m/devicetree_f2a85-m_pro.cb | 31 +++++++++++++------ 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index c05857f6d0..3f9135c76d 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -61,8 +61,7 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0xf7 = 0x00 irq 0xf8 = 0x00 end - device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - irq 0x30 = 0x00 + device pnp 2e.8 off # WDT1, GPIO0, GPIO1 io 0x60 = 0x00 irq 0xe0 = 0xff irq 0xe1 = 0xff @@ -78,29 +77,42 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0xf6 = 0x00 irq 0xf7 = 0xff end - device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - irq 0x30 = 0xfe + device pnp 2e.009 off # GPIO8 + end + device pnp 2e.109 on # GPIO1 + end + device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff irq 0xe1 = 0x90 irq 0xe2 = 0x00 irq 0xe3 = 0x00 + irq 0xe9 = 0x00 + end + device pnp 2e.309 on # GPIO3 irq 0xe4 = 0x7f irq 0xe5 = 0x76 irq 0xe6 = 0x00 irq 0xe7 = 0x00 - irq 0xe8 = 0x00 - irq 0xe9 = 0x00 irq 0xea = 0x00 - irq 0xeb = 0x00 - irq 0xee = 0x00 + irq 0xfe = 0x00 + end + device pnp 2e.409 on # GPIO4 + irq 0xe8 = 0x00 irq 0xf0 = 0xff irq 0xf1 = 0x7b irq 0xf2 = 0x00 + irq 0xee = 0x00 + end + device pnp 2e.509 on # GPIO5 + irq 0xeb = 0x00 irq 0xf4 = 0xff irq 0xf5 = 0xef irq 0xf6 = 0x00 irq 0xf7 = 0x00 - irq 0xfe = 0x00 + end + device pnp 2e.609 on # GPIO6 + end + device pnp 2e.709 on # GPIO7 end device pnp 2e.a on # ACPI irq 0xe6 = 0x4c @@ -108,7 +120,6 @@ chip northbridge/amd/agesa/family15tn/root_complex irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - irq 0x30 = 0x01 io 0x60 = 0x0290 irq 0xe2 = 0x7f irq 0xe4 = 0xf1 From 3e4a14e153f6c77c257e03584364c58f1a2ae8dc Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sun, 18 Oct 2020 15:04:41 -0700 Subject: [PATCH 168/354] device: Export enable_static_device() function The work done by enable_static_devices() and scan_generic_bus() is common and can be used by other device handlers to enable a single static device. Signed-off-by: Duncan Laurie Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46541 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/device/root_device.c | 33 ++++++++++++++------------------- src/include/device/device.h | 1 + 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 640ea505d4..1f51786153 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -7,6 +7,18 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; +void enable_static_device(struct device *dev) +{ + if (dev->chip_ops && dev->chip_ops->enable_dev) + dev->chip_ops->enable_dev(dev); + + if (dev->ops && dev->ops->enable) + dev->ops->enable(dev); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(dev), + dev->enabled ? "enabled" : "disabled"); +} + /** * Enable devices on static buses. * @@ -32,15 +44,7 @@ void enable_static_devices(struct device *bus) for (link = bus->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); + enable_static_device(child); } } } @@ -58,18 +62,9 @@ void scan_generic_bus(struct device *bus) link->secondary = ++bus_max; for (child = link->children; child; child = child->sibling) { - - if (child->chip_ops && child->chip_ops->enable_dev) - child->chip_ops->enable_dev(child); - - if (child->ops && child->ops->enable) - child->ops->enable(child); - + enable_static_device(child); printk(BIOS_DEBUG, "bus: %s[%d]->", dev_path(child->bus->dev), child->bus->link_num); - - printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); } } diff --git a/src/include/device/device.h b/src/include/device/device.h index 031091ab48..3a0795e526 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -358,6 +358,7 @@ static inline DEVTREE_CONST void *config_of_soc(void) return config_of(pcidev_on_root(0, 0)); } +void enable_static_device(struct device *dev); void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); From bf6962225659818c308ad323e35f181ce9c9c13b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sun, 18 Oct 2020 15:10:00 -0700 Subject: [PATCH 169/354] device: Allow virtual/generic devices under PCI in devicetree This change allows a generic device to be described in the devicetree under a PCI device, such as a root port. Previously any device under a PCI device was expected to also be a PCI device and that does not allow for a virtual/generic device to be present, for example to provide ACPI properties for a root port. The changes are: - Ignore non-PCI devices found under a PCI device when scanning and do not print an error for each devfn scanned. - Don't treat non-PCI devices as leftover and remove them, instead enable them as a static device. - Don't attempt to configure a static device in the tree that is not a PCIe device type. With these changes it is now possible to have a generic device under a PCI device, for example in a USB4/TBT root port (PCIe hotplug device) this generic device will add ACPI properties for the PCIe tunnel routed to the external port: device pci 07.0 on chip soc/intel/common/block/pcie device generic 0 on end end end TEST=boot on volteer with the USB4 root port devices in chipset.cb and ensure they are enabled properly and there are no errors printed in the coreboot log, and that the device properties are created in the SSDT. Signed-off-by: Duncan Laurie Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46542 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 25 +++++++++++++++---------- src/device/pciexp_device.c | 4 ++++ 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ce3e50967a..691ad6b316 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1006,16 +1006,11 @@ static struct device *pci_scan_get_dev(struct bus *bus, unsigned int devfn) prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { - if (dev->path.type == DEVICE_PATH_PCI) { - if (dev->path.pci.devfn == devfn) { - /* Unlink from the list. */ - *prev = dev->sibling; - dev->sibling = NULL; - break; - } - } else { - printk(BIOS_ERR, "child %s not a PCI device\n", - dev_path(dev)); + if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == devfn) { + /* Unlink from the list. */ + *prev = dev->sibling; + dev->sibling = NULL; + break; } prev = &dev->sibling; } @@ -1283,6 +1278,16 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, prev = &bus->children; for (dev = bus->children; dev; dev = dev->sibling) { + + /* + * If static device is not PCI then enable it here and don't + * treat it as a leftover device. + */ + if (dev->path.type != DEVICE_PATH_PCI) { + enable_static_device(dev); + continue; + } + /* * The device is only considered leftover if it is not hidden * and it has a Vendor ID of 0 (the default for a device that diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865152..8d4bb9849d 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -180,6 +180,8 @@ static void pciexp_enable_ltr(struct device *dev) for (bus = dev->link_list ; bus ; bus = bus->next) { for (child = bus->children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI) + continue; pciexp_configure_ltr(child); if (child->ops && child->ops->scan_bus) pciexp_enable_ltr(child); @@ -478,6 +480,8 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI) + continue; if ((child->path.pci.devfn < min_devfn) || (child->path.pci.devfn > max_devfn)) { continue; From fcbf18c5df6013c31e99662887be5c4e8bb2cf24 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sun, 18 Oct 2020 15:03:21 -0700 Subject: [PATCH 170/354] soc/intel/common: Fix ACPI device name for USB4 DMA device The USB4 host interface (DMA) devices need to use SA_DEVFN_* instead of SA_DEV_* when determining the ACPI name. The matching names are removed from the SOC-level ACPI name handler since they are provided by this driver now. TEST=boot on volteer and ensure TDM0 device is in the SSDT. Signed-off-by: Duncan Laurie Change-Id: If778bda82b80593452a590962dbffef6eff6484a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/usb4/usb4.c | 4 ++-- src/soc/intel/tigerlake/chip.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index 7c545f6043..df2dfdde37 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -15,9 +15,9 @@ static const char *tbt_dma_acpi_name(const struct device *dev) { switch (dev->path.pci.devfn) { - case SA_DEV_TCSS_DMA0: + case SA_DEVFN_TCSS_DMA0: return "TDM0"; - case SA_DEV_TCSS_DMA1: + case SA_DEVFN_TCSS_DMA1: return "TDM1"; default: return NULL; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 98ed55ca58..46c043fce9 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -68,8 +68,6 @@ const char *soc_acpi_name(const struct device *dev) case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; - case SA_DEVFN_TCSS_DMA0: return "TDM0"; - case SA_DEVFN_TCSS_DMA1: return "TDM1"; case SA_DEVFN_TBT0: return "TRP0"; case SA_DEVFN_TBT1: return "TRP1"; case SA_DEVFN_TBT2: return "TRP2"; From 389cb30ceddba90ce2d7dd0fa0cec1ff54ff1ae4 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sun, 18 Oct 2020 15:01:22 -0700 Subject: [PATCH 171/354] soc/intel/common: Fix/clean up USB4 PCIe virtual/generic driver This driver is for the root port device and needs to reference the parent device for its ACPI scope. Similarly for the debug output it needs to use the parent device, and fall back to the chip name if config->desc is not provided in the devicetree. The UID property is removed. This value is not the same as the port number; according to some docs it should be unique but it is not fully clear what it should be tied to. Regardless, it is not used by the Thunderbolt driver in the kernel. I also renamed some functions/structures to be clear that this is just an ACPI driver for the PCIe root port and not a driver for the root port itself. As part of this I removed the PCI based resource operations and the scan bus function since this device does not have children itself. Finally I added a detailed comment with an example describing what the driver is for and what properties it generates. TEST=boot on volteer and ensure the USB4 root port device and properties are added to the SSDT as described by the comment in chip.h. Signed-off-by: Duncan Laurie Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/usb4/chip.h | 54 +++++++++++++++++++++++++- src/soc/intel/common/block/usb4/pcie.c | 34 +++++++--------- 2 files changed, 67 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/common/block/usb4/chip.h b/src/soc/intel/common/block/usb4/chip.h index f2eee4d34c..41f4ed6cab 100644 --- a/src/soc/intel/common/block/usb4/chip.h +++ b/src/soc/intel/common/block/usb4/chip.h @@ -3,10 +3,62 @@ #ifndef __DRIVERS_INTEL_USB4_PCIE_H__ #define __DRIVERS_INTEL_USB4_PCIE_H__ +/* + * This virtual generic driver provides the ACPI properties for an + * Intel USB4/TBT PCIe Root Port which is already declared in the DSDT, + * + * The associated USB4 port number is obtained from the generic ID and + * the related host interface (DMA) device is provided by the devicetree. + * + * The "ExternalFacingPort", and "HotPlugSupportInD3" properties are defined at + * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports + * + * Example: PCIe Root Port 2 via USB4 host interface 1 port 0: + * + * device pci 0d.3 alias tbt_dma1 on end # \_SB.PCI0.TDM1 + * device pci 07.2 alias tbt_pcie_rp2 on # \_SB.PCI0.TRP2 + * chip soc/intel/common/block/usb4 + * use tbt_dma1 as usb4_port # USB4 host interface for this root port + * device generic 0 on end # USB4 port number on this host interface + * end + * end + * + * The host interface and PCIe Root Port are declared in the DSDT: + * + * Scope (\_SB.PCI0) { + * Device (TDM1) { + * Name (_ADR, 0x000d0003) + * } + * Device (TRP2) { + * Name (_ADR, 0x00070002) + * } + * } + * + * This driver will provide the following properties in the SSDT: + * + * Scope (\_SB.PCI0.TRP2) { + * Name (_DSD, Package () { + * ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + * Package () { + * Package () { "usb4-host-interface", \_SB.PCI0.TDM1 }, + * Package () { "usb4-port-number", 0 }, + * }, + * ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), + * Package () { + * Package () { "HotPlugSupportInD3", 1 }, + * }, + * ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), + * Package () { + * Package () { "ExternalFacingPort", 1 }, + * }, + * } + * } + */ + struct soc_intel_common_block_usb4_config { const char *desc; - /* Pointer to USB4 device that this PCIe root port is routed to. */ + /* USB4 host interface (DMA device) that this PCIe root port is routed to. */ DEVTREE_CONST struct device *usb4_port; }; diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index e37d5f4125..eae9027511 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -4,19 +4,14 @@ #include #include #include -#include -#include -#include -#include #include -#include #include "chip.h" #define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" #define PCI_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" #if CONFIG(HAVE_ACPI_TABLES) -static void usb4_pcie_fill_ssdt(const struct device *dev) +static void usb4_pcie_acpi_fill_ssdt(const struct device *dev) { const struct soc_intel_common_block_usb4_config *config; const struct device *parent; @@ -43,14 +38,15 @@ static void usb4_pcie_fill_ssdt(const struct device *dev) /* Get ACPI path to USB4 device. */ usb4_path = acpi_device_path(config->usb4_port); if (!usb4_path) { - printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port\n", __func__); + printk(BIOS_ERR, "%s: Unable to find ACPI path for usb4_port %s\n", + __func__, dev_path(config->usb4_port)); return; } usb4_path = strdup(usb4_path); port_id = dev->path.generic.id; - acpigen_write_scope(acpi_device_path(dev)); + acpigen_write_scope(acpi_device_path(parent)); /* Add pointer to USB4 port controller. */ dsd = acpi_dp_new_table("_DSD"); @@ -65,33 +61,31 @@ static void usb4_pcie_fill_ssdt(const struct device *dev) /* Indicate that port is external. */ pkg = acpi_dp_new_table(PCI_EXTERNAL_PORT_UUID); acpi_dp_add_integer(pkg, "ExternalFacingPort", 1); - acpi_dp_add_integer(pkg, "UID", port_id); acpi_dp_add_package(dsd, pkg); acpi_dp_write(dsd); acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc, dev_path(dev)); + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(parent), + config->desc ? : dev->chip_ops->name, dev_path(parent)); } #endif -static struct device_operations usb4_dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, +static struct device_operations usb4_pcie_acpi_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = usb4_pcie_fill_ssdt, + .acpi_fill_ssdt = usb4_pcie_acpi_fill_ssdt, #endif }; -static void pcie_enable(struct device *dev) +static void usb4_pcie_acpi_enable(struct device *dev) { - dev->ops = &usb4_dev_ops; + dev->ops = &usb4_pcie_acpi_dev_ops; } struct chip_operations soc_intel_common_block_usb4_ops = { - CHIP_NAME("Intel USB4 Root Port") - .enable_dev = pcie_enable + CHIP_NAME("Intel USB4 PCIe Root Port") + .enable_dev = usb4_pcie_acpi_enable }; From 3e69c0a07787d9f55915181c39ba4dbaeb258a05 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 21 Oct 2020 19:00:04 +0200 Subject: [PATCH 172/354] cpu/intel/common: Fix regression MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the logic introduced in CB:46276 "cpu/intel/common: only lock AES-NI when supported" which needs to be negated. Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634 Reviewed-by: Christian Walter Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/cpu/intel/common/common_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 45680146ad..a54e89183f 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -273,7 +273,7 @@ void set_aesni_lock(void) if (!CONFIG(SET_MSR_AESNI_LOCK_BIT)) return; - if (cpu_get_feature_flags_ecx() & CPUID_AES) + if (!(cpu_get_feature_flags_ecx() & CPUID_AES)) return; /* Only run once per core as specified in the MSR datasheet */ From cf5d58328fe004d967466be42de62d6bab4c3133 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Tue, 13 Oct 2020 18:33:04 -0700 Subject: [PATCH 173/354] drivers/intel/gma: Increase vbt_data size With TGL FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Due to which cbfsf_decompression_info check failed when trying to load vbt binary from cbfs because vbt decompressed_size was greater than vbt_data size. This caused Graphics init and fw screen issues. Increase the vbt_data to 9KiB to accommodate new vbt binary. BUG=b:170656067 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46374 Tested-by: build bot (Jenkins) Reviewed-by: Dossym Nurmukhanov Reviewed-by: Nick Vaccaro Reviewed-by: Angel Pons Reviewed-by: Duncan Laurie --- src/drivers/intel/gma/opregion.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 7682af199b..8f1d2e6373 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -19,7 +19,7 @@ const char *mainboard_vbt_filename(void) return "vbt.bin"; } -static char vbt_data[8 * KiB]; +static char vbt_data[9 * KiB]; static size_t vbt_data_sz; void *locate_vbt(size_t *vbt_size) From 095bbf969d47a06388be65e944352f1936c4e1f2 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 30 Sep 2020 23:09:29 +0000 Subject: [PATCH 174/354] acpigen: Add option for reserved bits in Field Add an option for unused/reserved bits in a Field definition, allowing for declarations that do not start at bit 0: Field (UART, AnyAcc, NoLock, Preserve) { , 7, /* RESERVED */ BITF, /* Used bit */ } These just use byte 0 instead of a name. Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 14 +++++++++++++- src/include/acpi/acpigen.h | 5 +++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 5b45ebd3a8..a3beb1054f 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -505,6 +505,12 @@ static void acpigen_write_field_name(const char *name, uint32_t size) acpigen_write_field_length(size); } +static void acpigen_write_field_reserved(uint32_t size) +{ + acpigen_emit_byte(0); + acpigen_write_field_length(size); +} + /* * Generate ACPI AML code for Field * Arg0: region name @@ -515,6 +521,7 @@ static void acpigen_write_field_name(const char *name, uint32_t size) * struct fieldlist l[] = { * FIELDLIST_OFFSET(0x84), * FIELDLIST_NAMESTR("PMCS", 2), + * FIELDLIST_RESERVED(6), * }; * acpigen_write_field("UART", l, ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK | * FIELD_PRESERVE); @@ -522,7 +529,8 @@ static void acpigen_write_field_name(const char *name, uint32_t size) * Field (UART, AnyAcc, NoLock, Preserve) * { * Offset (0x84), - * PMCS, 2 + * PMCS, 2, + * , 6, * } */ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t count, @@ -546,6 +554,10 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou acpigen_write_field_name(l[i].name, l[i].bits); current_bit_pos += l[i].bits; break; + case RESERVED: + acpigen_write_field_reserved(l[i].bits); + current_bit_pos += l[i].bits; + break; case OFFSET: acpigen_write_field_offset(l[i].bits, current_bit_pos); current_bit_pos = l[i].bits; diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index c30f8449b6..10e328b8b8 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -158,6 +158,10 @@ enum { .name = X, \ .bits = Y, \ } +#define FIELDLIST_RESERVED(X) { .type = RESERVED, \ + .name = "", \ + .bits = X, \ + } #define FIELD_ANYACC 0 #define FIELD_BYTEACC 1 @@ -174,6 +178,7 @@ enum { enum field_type { OFFSET, NAME_STRING, + RESERVED, FIELD_TYPE_MAX, }; From 8e391d3452902ac1a71124118e811eaf378d0779 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 30 Sep 2020 23:17:41 +0000 Subject: [PATCH 175/354] acpigen: Add helpers for common Store operations Add helpers for some store operations: Store(INTEGER, NAME) ex: Store (100, SAVE) Store(INTEGER, OP) ex: Store (100, Local0) Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 16 ++++++++++++++++ src/include/acpi/acpigen.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index a3beb1054f..ee7c90cf01 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1243,6 +1243,22 @@ void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst) acpigen_emit_namestring(dst); } +/* Store (src, "namestr") */ +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_namestring(dst); +} + +/* Store (src, dst) */ +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst) +{ + acpigen_write_store(); + acpigen_write_integer(src); + acpigen_emit_byte(dst); +} + /* Or (arg1, arg2, res) */ void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) { diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 10e328b8b8..e44326790b 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -361,6 +361,8 @@ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, const char * const dev_states[], size_t dev_states_count); void acpigen_write_sleep(uint64_t sleep_ms); void acpigen_write_store(void); +void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst); +void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); From 36858208e6e06fdda2698e9a66a8e27f6d9acd24 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 6 Oct 2020 21:01:51 +0000 Subject: [PATCH 176/354] acpigen: Add ShiftLeft function helper Provide a helper function for the ACPI shift left operator that uses the same operator for the source and result. ShiftLeft (OP, count, OP) Signed-off-by: Duncan Laurie Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 8 ++++++++ src/include/acpi/acpigen.h | 1 + 2 files changed, 9 insertions(+) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index ee7c90cf01..0ed3708016 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1381,6 +1381,14 @@ void acpigen_write_else(void) acpigen_write_len_f(); } +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count) +{ + acpigen_emit_byte(SHIFT_LEFT_OP); + acpigen_emit_byte(src_result); + acpigen_write_integer(count); + acpigen_emit_byte(ZERO_OP); +} + void acpigen_write_to_buffer(uint8_t src, uint8_t dst) { acpigen_emit_byte(TO_BUFFER_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index e44326790b..cb9e9c97ab 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -378,6 +378,7 @@ void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val); void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); void acpigen_write_else(void); +void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); void acpigen_write_to_integer(uint8_t src, uint8_t dst); void acpigen_write_to_integer_from_namestring(const char *source, uint8_t dst_op); From 30c3f91d33a8308db80a730c6df27553d8fdb072 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 9 Oct 2020 04:48:53 +0000 Subject: [PATCH 177/354] acpigen: Make gpio set/get arguments const The 'struct acpi_gpio' arguments passed to acpigen functions are not modified so they can be made const, which allows drivers to also use a const pointer. Signed-off-by: Duncan Laurie Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 8 ++++---- src/include/acpi/acpigen.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 0ed3708016..e2fe2cfaa4 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1865,7 +1865,7 @@ int __weak acpigen_soc_clear_tx_gpio(unsigned int gpio_num) * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); @@ -1873,7 +1873,7 @@ int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) return acpigen_soc_set_tx_gpio(gpio->pins[0]); } -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio) { if (gpio->active_low) return acpigen_soc_set_tx_gpio(gpio->pins[0]); @@ -1881,7 +1881,7 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } -void acpigen_get_rx_gpio(struct acpi_gpio *gpio) +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_read_rx_gpio(gpio->pins[0]); @@ -1889,7 +1889,7 @@ void acpigen_get_rx_gpio(struct acpi_gpio *gpio) acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } -void acpigen_get_tx_gpio(struct acpi_gpio *gpio) +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio) { acpigen_soc_get_tx_gpio(gpio->pins[0]); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index cb9e9c97ab..e0d95cdbfe 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -499,8 +499,8 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); * * Returns 0 on success and -1 on error. */ -int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); -int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +int acpigen_enable_tx_gpio(const struct acpi_gpio *gpio); +int acpigen_disable_tx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a RX GPIO value based on the GPIO polarity. @@ -508,7 +508,7 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); * This function ends up calling acpigen_soc_get_rx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_rx_gpio(struct acpi_gpio *gpio); +void acpigen_get_rx_gpio(const struct acpi_gpio *gpio); /* * Helper function for getting a TX GPIO value based on the GPIO polarity. @@ -516,7 +516,7 @@ void acpigen_get_rx_gpio(struct acpi_gpio *gpio); * This function ends up calling acpigen_soc_get_tx_gpio to make callbacks * into SoC acpigen code */ -void acpigen_get_tx_gpio(struct acpi_gpio *gpio); +void acpigen_get_tx_gpio(const struct acpi_gpio *gpio); /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, From 3502960e50c5380af875c7d43e51040a8ed25623 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 9 Oct 2020 17:50:25 +0000 Subject: [PATCH 178/354] acpigen: Make acpigen_write_opregion() argument const This structure is not modified so it can be made const and allow the calling function to also declare it as a const structure. Signed-off-by: Duncan Laurie Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/acpi/acpigen.c | 2 +- src/include/acpi/acpigen.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index e2fe2cfaa4..7b7258469f 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -408,7 +408,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores) * len is region length. * OperationRegion(regionname, regionspace, regionoffset, regionlength) */ -void acpigen_write_opregion(struct opregion *opreg) +void acpigen_write_opregion(const struct opregion *opreg) { /* OpregionOp */ acpigen_emit_ext_op(OPREGION_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index e0d95cdbfe..d06d20c8e7 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -429,7 +429,7 @@ void acpigen_write_rom(void *bios, const size_t length); * This function takes input region name, region space, region offset & region * length. */ -void acpigen_write_opregion(struct opregion *opreg); +void acpigen_write_opregion(const struct opregion *opreg); /* * Generate ACPI AML code for Mutex * This function takes mutex name and initial value. From cbbdcb330d7885824623014e6e589a4eebe9d9d4 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Tue, 22 Sep 2020 19:45:41 +0800 Subject: [PATCH 179/354] soc/mediatek/mt8192: Add board-specific regulator APIs To enable DVFS, DRAM driver needs to access four different regulators that SoC can't access directly and need board-specific implementations. To support that we need to define the getter and setter APIs for those regulators. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- .../mediatek/common/include/soc/regulator.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/soc/mediatek/common/include/soc/regulator.h diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h new file mode 100644 index 0000000000..258d5503f1 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_REGULATOR_H +#define SOC_MEDIATEK_COMMON_REGULATOR_H + +#include + +enum mtk_regulator { + MTK_REGULATOR_VDD1, + MTK_REGULATOR_VDD2, + MTK_REGULATOR_VDDQ, + MTK_REGULATOR_VMDDR, +}; + +void mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv); +uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator); + +#endif /* SOC_MEDIATEK_COMMON_REGULATOR_H */ From aa752158a6873ae7651c191f09bd6aa5137725f6 Mon Sep 17 00:00:00 2001 From: Ikjoon Jang Date: Fri, 8 May 2020 12:35:35 +0800 Subject: [PATCH 180/354] soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE BRANCH=none BUG=b:159079785 TEST=1. Checkout https://review.trustedfirmware.org/c/4334 2. emerge-asurada coreboot chromeos-bootimage 3. boot asurada Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce Signed-off-by: Ikjoon Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46382 Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/Kconfig | 1 + src/soc/mediatek/mt8192/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 1d1cf7b79e..18d9d41ef3 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -5,6 +5,7 @@ config SOC_MEDIATEK_MT8192 select ARCH_VERSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAVE_UART_SPECIAL if SOC_MEDIATEK_MT8192 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b047ce9394..fb3b11de8c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -36,6 +36,8 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +BL31_MAKEARGS += PLAT=mt8192 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include From 5ed4d63fe12b9dc744a15a76c136132cc42308db Mon Sep 17 00:00:00 2001 From: Nicolas Boichat Date: Tue, 19 May 2020 14:24:33 +0800 Subject: [PATCH 181/354] mb/google/asurada: enable SPI devices Configure and initialize EC and TPM on Asurada. BUG=none TEST=boot asurada Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385 Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/asurada/Kconfig | 4 ++-- src/mainboard/google/asurada/bootblock.c | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 894d5666b5..7c93815ae8 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER config DRIVER_TPM_SPI_BUS hex - default 0x0 + default 0x5 # On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). @@ -49,6 +49,6 @@ config BOOT_DEVICE_SPI_FLASH_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0x2 + default 0x1 endif diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 5dcae8c79b..cce14381f6 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); } From c47ed6e8c3106b243f6c1df23d21785bdf61bd10 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Tue, 26 May 2020 23:49:21 +0800 Subject: [PATCH 182/354] mb/google/asurada: Add Chrome OS GPIOs Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs. BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None Signed-off-by: Hung-Te Lin Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/mainboard/google/asurada/Makefile.inc | 3 +++ src/mainboard/google/asurada/bootblock.c | 4 ++++ src/mainboard/google/asurada/chromeos.c | 23 +++++++++++++++++++++-- src/mainboard/google/asurada/gpio.h | 20 ++++++++++++++++++++ 4 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/asurada/gpio.h diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index c74253994c..02fb8300e0 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,12 +2,15 @@ subdirs-y += sdram_params/ bootblock-y += memlayout.ld bootblock-y += bootblock.c +bootblock-y += chromeos.c verstage-y += memlayout.ld +verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index cce14381f6..04e8898d85 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,8 +3,12 @@ #include #include +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 8f9fa5334c..a57392bc04 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -5,16 +5,35 @@ #include #include +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); } int tis_plat_irq_status(void) { - return 0; + return gpio_eint_poll(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000000..90de583f77 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) + +void setup_chromeos_gpios(void); + +#endif From 17df7d634d296a6da8496fa3c1d5feeb7f573019 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Tue, 20 Oct 2020 23:10:55 -0700 Subject: [PATCH 183/354] security/vboot: Remove all tpm 1.2 functions for mrc hash in the tpm Since MRC_SAVE_HASH_IN_TPM depends on TPM2, we can now remove the tpm 1.2 versions of functions that deal with mrc hash in the tpm as it will not be used by tpm 1.2 boards. Also move all antirollback functions that deal with mrc hash in the tpm under CONFIG(TPM2). BUG=b:150502246 BRANCH=None TEST=make sure boards are still compiling on coreboot Jenkins Change-Id: I446dde36ce2233fc40687892da1fb515ce35b82b Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46615 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Furquan Shaikh --- src/security/vboot/secdata_tpm.c | 111 ++++++++++++------------------- 1 file changed, 41 insertions(+), 70 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0304b923fb..65d9c83a34 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -71,6 +71,8 @@ uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) return TPM_SUCCESS; } +#if CONFIG(TPM2) + static uint32_t read_space_mrc_hash(uint32_t index, uint8_t *data) { RETURN_ON_FAILURE(tlcl_read(index, data, @@ -85,7 +87,6 @@ static uint32_t read_space_mrc_hash(uint32_t index, uint8_t *data) */ static const uint8_t mrc_hash_data[HASH_NV_SIZE] = { }; -#if CONFIG(TPM2) /* * Different sets of NVRAM space attributes apply to the "ro" spaces, * i.e. those which should not be possible to delete or modify once @@ -208,6 +209,45 @@ uint32_t antirollback_lock_space_firmware(void) return tlcl_lock_nv_write(FIRMWARE_NV_INDEX); } +uint32_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size) +{ + if (size != HASH_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " + "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, + size); + return TPM_E_READ_FAILURE; + } + return read_space_mrc_hash(index, data); +} + +uint32_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, uint32_t size) +{ + uint8_t spc_data[HASH_NV_SIZE]; + uint32_t rv; + + if (size != HASH_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " + "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, + size); + return TPM_E_WRITE_FAILURE; + } + + rv = read_space_mrc_hash(index, spc_data); + if (rv == TPM_E_BADINDEX) { + /* + * If space is not defined already for hash, define + * new space. + */ + VBDEBUG("TPM: Initializing hash space.\n"); + return set_mrc_hash_space(index, data); + } + + if (rv != TPM_SUCCESS) + return rv; + + return safe_write(index, data, size); +} + uint32_t antirollback_lock_space_mrc_hash(uint32_t index) { return tlcl_lock_nv_write(index); @@ -250,18 +290,6 @@ static uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) } } -static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) -{ - RETURN_ON_FAILURE(safe_define_space(index, - TPM_NV_PER_GLOBALLOCK | - TPM_NV_PER_PPWRITE, - HASH_NV_SIZE)); - RETURN_ON_FAILURE(safe_write(index, data, - HASH_NV_SIZE)); - - return TPM_SUCCESS; -} - static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { TPM_PERMANENT_FLAGS pflags; @@ -316,16 +344,6 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) ctx->secdata_firmware, VB2_SECDATA_FIRMWARE_SIZE)); - /* - * Define and set rec hash space, if available. No need to - * create the RW hash space because we will definitely boot - * once in normal mode before shipping, meaning that the space - * will get created with correct permissions while still in in - * our hands. - */ - if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) - RETURN_ON_FAILURE(set_mrc_hash_space(MRC_REC_HASH_NV_INDEX, mrc_hash_data)); - return TPM_SUCCESS; } @@ -334,14 +352,6 @@ uint32_t antirollback_lock_space_firmware(void) return tlcl_set_global_lock(); } -uint32_t antirollback_lock_space_mrc_hash(uint32_t index) -{ - /* - * Nothing needs to be done here, since global lock is already set while - * locking firmware space. - */ - return TPM_SUCCESS; -} #endif /** @@ -434,45 +444,6 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx) return safe_write(KERNEL_NV_INDEX, ctx->secdata_kernel, size); } -uint32_t antirollback_read_space_mrc_hash(uint32_t index, uint8_t *data, uint32_t size) -{ - if (size != HASH_NV_SIZE) { - VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " - "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, - size); - return TPM_E_READ_FAILURE; - } - return read_space_mrc_hash(index, data); -} - -uint32_t antirollback_write_space_mrc_hash(uint32_t index, const uint8_t *data, uint32_t size) -{ - uint8_t spc_data[HASH_NV_SIZE]; - uint32_t rv; - - if (size != HASH_NV_SIZE) { - VBDEBUG("TPM: Incorrect buffer size for hash idx 0x%x. " - "(Expected=0x%x Actual=0x%x).\n", index, HASH_NV_SIZE, - size); - return TPM_E_WRITE_FAILURE; - } - - rv = read_space_mrc_hash(index, spc_data); - if (rv == TPM_E_BADINDEX) { - /* - * If space is not defined already for hash, define - * new space. - */ - VBDEBUG("TPM: Initializing hash space.\n"); - return set_mrc_hash_space(index, data); - } - - if (rv != TPM_SUCCESS) - return rv; - - return safe_write(index, data, size); -} - vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) { uint32_t rv; From a693fa06cd32da8239f820d833bb7a1bf55bf351 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Tue, 20 Oct 2020 11:11:06 +0800 Subject: [PATCH 184/354] dedede: Create metaknight variant Create the metaknight variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:169813211 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_METAKNIGHT Signed-off-by: Tim Chen Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Angel Pons --- src/mainboard/google/dedede/Kconfig | 2 + src/mainboard/google/dedede/Kconfig.name | 5 +++ .../variants/metaknight/include/variant/ec.h | 8 ++++ .../metaknight/include/variant/gpio.h | 8 ++++ .../variants/metaknight/memory/Makefile.inc | 5 +++ .../metaknight/memory/dram_id.generated.txt | 1 + .../metaknight/memory/mem_parts_used.txt | 6 +++ .../variants/metaknight/overridetree.cb | 42 +++++++++++++++++++ 8 files changed, 77 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc create mode 100644 src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/dedede/variants/metaknight/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 597516cd88..6da65052cd 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE default "Magolor" if BOARD_GOOGLE_MAGOLOR + default "Metaknight" if BOARD_GOOGLE_METAKNIGHT config MAX_CPUS int @@ -124,5 +125,6 @@ config VARIANT_DIR default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR + default "metaknight" if BOARD_GOOGLE_METAKNIGHT endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 563a309c45..689df68846 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -63,3 +63,8 @@ config BOARD_GOOGLE_MAGOLOR select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_METAKNIGHT + bool "-> Metaknight" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt new file mode 100644 index 0000000000..59381dcf5b --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb new file mode 100644 index 0000000000..404024b1d6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end From bc744f5893fc4d53275ed26dd8d968011c6a09c1 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 17 Apr 2020 16:16:49 +0200 Subject: [PATCH 185/354] drivers/smmstore: Implement SMMSTORE version 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Matt DeVillier --- Documentation/drivers/index.md | 1 + Documentation/drivers/smmstorev2.md | 221 ++++++++++++++++++ payloads/libpayload/include/coreboot_tables.h | 1 + src/commonlib/include/commonlib/cbmem_id.h | 1 + .../include/commonlib/coreboot_tables.h | 17 ++ src/drivers/smmstore/Kconfig | 12 + src/drivers/smmstore/Makefile.inc | 1 + src/drivers/smmstore/ramstage.c | 76 ++++++ src/drivers/smmstore/smi.c | 83 ++++++- src/drivers/smmstore/store.c | 197 ++++++++++++++++ src/include/smmstore.h | 94 +++++++- src/lib/coreboot_table.c | 6 + 12 files changed, 702 insertions(+), 8 deletions(-) create mode 100644 Documentation/drivers/smmstorev2.md create mode 100644 src/drivers/smmstore/ramstage.c diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index e215c6ab11..508beaf40a 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -7,3 +7,4 @@ they allow to easily reuse existing code accross platforms. * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) * [SoundWire](soundwire.md) +* [SMMSTOREv2](smmstorev2.md) diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md new file mode 100644 index 0000000000..cb79b8b6b8 --- /dev/null +++ b/Documentation/drivers/smmstorev2.md @@ -0,0 +1,221 @@ +# SMM based flash storage driver Version 2 + +This documents the API exposed by the x86 system management based +storage driver. + +## SMMSTOREv2 + +SMMSTOREv2 is a [SMM] mediated driver to read from, write to and erase +a predefined region in flash. It can be enabled by setting +`CONFIG_SMMSTORE=y` and `CONFIG_SMMSTORE_V2=y` in menuconfig. + +This can be used by the OS or the payload to implement persistent +storage to hold for instance configuration data, without needing to +implement a (platform specific) storage driver in the payload itself. + +### Storage size and alignment + +SMMSTORE version 2 requires a minimum alignment of 64 KiB, which should +be supported by all flash chips. Not having to perform read-modify-write +operations is desired, as it reduces complexity and potential for bugs. + +This can be used by a FTW (FaultTolerantWrite) implementation that uses +at least two regions in an A/B update scheme. The FTW implementation in +EDK2 uses three different regions in the store: + +- The variable store +- The FTW spare block +- The FTW working block + +All regions must be block-aligned, and the FTW spare size must be larger +than that of the variable store. FTW working block can be much smaller. +With 64 KiB as block size, the minimum size of the FTW-enabled store is: + +- The variable store: 1 block = 64 KiB +- The FTW spare block: 2 blocks = 2 * 64 KiB +- The FTW working block: 1 block = 64 KiB + +Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB. + +## API + +The API provides read and write access to an unformatted block storage. + +### Storage region + +By default SMMSTOREv2 will operate on a separate FMAP region called +`SMMSTORE`. The default generated FMAP will include such a region. On +systems with a locked FMAP, e.g. in an existing vboot setup with a +locked RO region, the option exists to add a cbfsfile called `smm_store` +in the `RW_LEGACY` (if CHROMEOS) or in the `COREBOOT` FMAP regions. It +is recommended for new builds using a handcrafted FMD that intend to +make use of SMMSTORE to include a sufficiently large `SMMSTORE` FMAP +region. It is mandatory to align the `SMMSTORE` region to 64KiB for +compatibility with the largest flash erase operation. + +When a default generated FMAP is used, the size of the FMAP region is +equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least 64 KiB. +To support a fault tolerant write mechanism, at least a multiple of +this size is recommended. + +### Communication buffer + +To prevent malicious ring0 code to access arbitrary memory locations, +SMMSTOREv2 uses a communication buffer in CBMEM/HOB for all transfers. +This buffer has to be at least 64 KiB in size and must be installed +before calling any of the SMMSTORE read or write operations. Usually, +coreboot will install this buffer to transfer data between ring0 and +the [SMM] handler. + +In order to get the communication buffer address, the payload or OS +has to read the coreboot table with tag `0x0039`, containing: + +```C +struct lb_smmstorev2 { + uint32_t tag; + uint32_t size; + uint32_t num_blocks; /* Number of writeable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in byte */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ +}; +``` + +The absence of this coreboot table entry indicates that there's no +SMMSTOREv2 support. + +### Blocks + +The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks +called *blocks*. Every block is at least the size of 64KiB to support +arbitrary NOR flash erase ops. A payload or OS must make no further +assumptions about the block or communication buffer size. + +### Generating the SMI + +SMMSTOREv2 is called via an SMI, which is generated via a write to the +IO port defined in the smi_cmd entry of the FADT ACPI table. `%al` +contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO +port. `%ah` contains the SMMSTOREv2 command. `%ebx` contains the +parameter buffer to the SMMSTOREv2 command. + +### Return values + +If a command succeeds, SMMSTOREv2 will return with +`SMMSTORE_RET_SUCCESS=0` in `%eax`. On failure SMMSTORE will return +`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands +`SMMSTORE_REG_UNSUPPORTED=2` is returned. + +**NOTE 1**: The caller **must** check the return value and should make +no assumption on the returned data if `%eax` does not contain +`SMMSTORE_RET_SUCCESS`. + +**NOTE 2**: If the SMI returns without changing `%ax`, it can be assumed +that the SMMSTOREv2 feature is not installed. + +### Calling arguments + +SMMSTOREv2 supports 3 subcommands that are passed via `%ah`, the +additional calling arguments are passed via `%ebx`. + +**NOTE**: The size of the struct entries are in the native word size of +smihandler. This means 32 bits in almost all cases. + +#### - SMMSTORE_CMD_INIT = 4 + +This installs the communication buffer to use and thus enables the +SMMSTORE handler. This command can only be executed once and is done +by the firmware. Calling this function at runtime has no effect. + +The additional parameter buffer `%ebx` contains a pointer to the +following struct: + +```C +struct smmstore_params_init { + uint32_t com_buffer; + uint32_t com_buffer_size; +} __packed; +``` + +INPUT: +- `com_buffer`: Physical address of the communication buffer (CBMEM) +- `com_buffer_size`: Size in bytes of the communication buffer + +#### - SMMSTORE_CMD_RAW_READ = 5 + +SMMSTOREv2 allows reading arbitrary data. It is up to the caller to +initialize the store with meaningful data before using it. + +The additional parameter buffer `%ebx` contains a pointer to the +following struct: + +```C +struct smmstore_params_raw_read { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; +``` + +INPUT: +- `bufsize`: Size of data to read within the communication buffer +- `bufoffset`: Offset within the communication buffer +- `block_id`: Block to read from + +#### - SMMSTORE_CMD_RAW_WRITE = 6 + +SMMSTOREv2 allows writing arbitrary data. It is up to the caller to +erase a block before writing it. + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_raw_write { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; +``` + +INPUT: +- `bufsize`: Size of data to write within the communication buffer +- `bufoffset`: Offset within the communication buffer +- `block_id`: Block to write to + +#### - SMMSTORE_CMD_RAW_CLEAR = 7 + +SMMSTOREv2 allows clearing blocks. A cleared block will read as `0xff`. +By providing multiple blocks the caller can implement a fault tolerant +write mechanism. It is up to the caller to clear blocks before writing +to them. + + +```C +struct smmstore_params_raw_clear { + uint32_t block_id; +} __packed; +``` + +INPUT: +- `block_id`: Block to erase + +#### Security + +Pointers provided by the payload or OS are checked to not overlap with +SMM. This protects the SMM handler from being compromised. + +As all information is exchanged using the communication buffer and +coreboot tables, there's no risk that a malicious application capable +of issuing SMIs could extract arbitrary data or modify the currently +running kernel. + +## External links + +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf) +Note that this differs significantly from coreboot's implementation. + +[SMM]: ../security/smm.md diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bf8c0d9303..bfdd21e692 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -79,6 +79,7 @@ enum { CB_TAG_MMC_INFO = 0x0035, CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, + CB_TAG_SMMSTOREV2 = 0x0039, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a06bc..6b4d60469e 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -68,6 +68,7 @@ #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 #define CBMEM_ID_FSP_LOGO 0x4c4f474f +#define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6393c01e6e..44060025b3 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -80,6 +80,7 @@ enum { LB_TAG_TCPA_LOG = 0x0036, LB_TAG_FMAP = 0x0037, LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, + LB_TAG_SMMSTOREV2 = 0x0039, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -484,4 +485,20 @@ struct cmos_checksum { #define CHECKSUM_PCBIOS 1 }; +/* SMMSTOREv2 record + * This record contains information to use SMMSTOREv2. + */ + +struct lb_smmstorev2 { + uint32_t tag; + uint32_t size; + uint32_t num_blocks; /* Number of writeable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ +}; + #endif diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 7ee8676014..ba8268e378 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -6,6 +6,18 @@ config SMMSTORE default y if PAYLOAD_TIANOCORE select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP +config SMMSTORE_V2 + bool "Use version 2 of SMMSTORE API" + depends on SMMSTORE + default n + help + Version 2 of SMMSTORE allows secure communication with SMM and + makes no assumptions on the structure of the data stored within. + It splits the store into chunks to allows fault tolerant writes. + + By using version 2 you cannot make use of software that expects + a version 1 SMMSTORE. + config SMMSTORE_IN_CBFS bool default n diff --git a/src/drivers/smmstore/Makefile.inc b/src/drivers/smmstore/Makefile.inc index 1cafe3a3cf..90bcdece9d 100644 --- a/src/drivers/smmstore/Makefile.inc +++ b/src/drivers/smmstore/Makefile.inc @@ -1,3 +1,4 @@ ramstage-$(CONFIG_SMMSTORE) += store.c +ramstage-$(CONFIG_SMMSTORE_V2) += ramstage.c smm-$(CONFIG_SMMSTORE) += store.c smi.c diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c new file mode 100644 index 0000000000..ef80e221bc --- /dev/null +++ b/src/drivers/smmstore/ramstage.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smmstore_params_info info; + +void lb_smmstorev2(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_smmstorev2 *store; + const struct cbmem_entry *e; + + e = cbmem_entry_find(CBMEM_ID_SMM_COMBUFFER); + if (!e) + return; + + rec = lb_new_record(header); + store = (struct lb_smmstorev2 *)rec; + + store->tag = LB_TAG_SMMSTOREV2; + store->size = sizeof(*store); + store->com_buffer = (uintptr_t)cbmem_entry_start(e); + store->com_buffer_size = cbmem_entry_size(e); + store->mmap_addr = info.mmap_addr; + store->num_blocks = info.num_blocks; + store->block_size = info.block_size; + store->apm_cmd = APM_CNT_SMMSTORE; +} + +static void init_store(void *unused) +{ + struct smmstore_params_init args; + uint32_t eax = ~0; + uint32_t ebx; + + if (smmstore_get_info(&info) < 0) { + printk(BIOS_INFO, "SMMSTORE: Failed to get meta data\n"); + return; + } + + void *ptr = cbmem_add(CBMEM_ID_SMM_COMBUFFER, info.block_size); + if (!ptr) { + printk(BIOS_ERR, "SMMSTORE: Failed to add com buffer\n"); + return; + } + + args.com_buffer = (uintptr_t)ptr; + args.com_buffer_size = info.block_size; + ebx = (uintptr_t)&args; + + printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n"); + + /* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */ + __asm__ __volatile__ ( + "outb %%al, %%dx" + : "=a" (eax) + : "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE), + "b" (ebx), + "d" (APM_CNT) + : "memory"); + + if (eax != SMMSTORE_RET_SUCCESS) { + printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n"); + return; + } +} + +/* The SMI APM handler is installed at DEV_INIT phase */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, init_store, NULL); diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index b21423e90e..b90338c619 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -23,8 +23,7 @@ static int range_check(void *start, size_t size) return 0; } -/* Param is usually EBX, ret in EAX */ -uint32_t smmstore_exec(uint8_t command, void *param) +static uint32_t smmstorev1_exec(uint8_t command, void *param) { uint32_t ret = SMMSTORE_RET_FAILURE; @@ -66,13 +65,89 @@ uint32_t smmstore_exec(uint8_t command, void *param) ret = SMMSTORE_RET_SUCCESS; break; } - default: printk(BIOS_DEBUG, - "Unknown SMM store command: 0x%02x\n", command); + "Unknown SMM store v1 command: 0x%02x\n", command); ret = SMMSTORE_RET_UNSUPPORTED; break; } return ret; } + +static uint32_t smmstorev2_exec(uint8_t command, void *param) +{ + uint32_t ret = SMMSTORE_RET_FAILURE; + + switch (command) { + case SMMSTORE_CMD_INIT: { + printk(BIOS_DEBUG, "Init SMM store\n"); + struct smmstore_params_init *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + void *buf = (void *)(uintptr_t)params->com_buffer; + + if (range_check(buf, params->com_buffer_size) != 0) + break; + + if (smmstore_init(buf, params->com_buffer_size) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_READ: { + printk(BIOS_DEBUG, "Raw read from SMM store, param = %p\n", param); + struct smmstore_params_raw_read *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawread_region(params->block_id, params->bufoffset, + params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_WRITE: { + printk(BIOS_DEBUG, "Raw write to SMM store, param = %p\n", param); + struct smmstore_params_raw_write *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawwrite_region(params->block_id, params->bufoffset, + params->bufsize) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + case SMMSTORE_CMD_RAW_CLEAR: { + printk(BIOS_DEBUG, "Raw clear SMM store, param = %p\n", param); + struct smmstore_params_raw_clear *params = param; + + if (range_check(params, sizeof(*params)) != 0) + break; + + if (smmstore_rawclear_region(params->block_id) == 0) + ret = SMMSTORE_RET_SUCCESS; + break; + } + default: + printk(BIOS_DEBUG, + "Unknown SMM store v2 command: 0x%02x\n", command); + ret = SMMSTORE_RET_UNSUPPORTED; + break; + } + + return ret; +} + +uint32_t smmstore_exec(uint8_t command, void *param) +{ + if (!param) + return SMMSTORE_RET_FAILURE; + + if (CONFIG(SMMSTORE_V2)) + return smmstorev2_exec(command, param); + else + return smmstorev1_exec(command, param); +} diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 252ea8d47b..9f9ab0199d 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -262,3 +262,200 @@ int smmstore_clear_region(void) return 0; } + + +/* Implementation of Version 2 */ + +static bool store_initialized; +static struct mem_region_device mdev_com_buf; + +static int smmstore_rdev_chain(struct region_device *rdev) +{ + if (!store_initialized) + return -1; + + return rdev_chain_full(rdev, &mdev_com_buf.rdev); +} + +/** + * Call once before using the store. In SMM this must be called through an + * APM SMI handler providing the communication buffer address and length. + */ +int smmstore_init(void *buf, size_t len) +{ + if (!buf || len < SMM_BLOCK_SIZE) + return -1; + + if (store_initialized) + return -1; + + mem_region_device_rw_init(&mdev_com_buf, buf, len); + + store_initialized = true; + + return 0; +} + +#if ENV_RAMSTAGE +/** + * Provide metadata for the coreboot tables. + * Must only be called in ramstage, but not in SMM. + */ +int smmstore_get_info(struct smmstore_params_info *out) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_ERR, "smm store: lookup of store failed\n"); + return -1; + } + + if (!IS_ALIGNED(region_device_offset(&store), SMM_BLOCK_SIZE)) { + printk(BIOS_ERR, "smm store: store not aligned to block size\n"); + return -1; + } + + out->block_size = SMM_BLOCK_SIZE; + out->num_blocks = region_device_sz(&store) / SMM_BLOCK_SIZE; + + /* FIXME: Broken EDK2 always assumes memory mapped Firmware Block Volumes */ + out->mmap_addr = (uintptr_t)rdev_mmap_full(&store); + + printk(BIOS_DEBUG, "smm store: %d # blocks with size 0x%x\n", + out->num_blocks, out->block_size); + + return 0; +} +#endif + +/* Returns -1 on error, 0 on success */ +static int lookup_block_in_store(struct region_device *store, uint32_t block_id) +{ + if (lookup_store(store) < 0) { + printk(BIOS_ERR, "smm store: lookup of store failed\n"); + return -1; + } + + if ((block_id * SMM_BLOCK_SIZE) >= region_device_sz(store)) { + printk(BIOS_ERR, "smm store: block ID out of range\n"); + return -1; + } + + return 0; +} + +/* Returns NULL on error, pointer from rdev_mmap on success */ +static void *mmap_com_buf(struct region_device *com_buf, uint32_t offset, uint32_t bufsize) +{ + if (smmstore_rdev_chain(com_buf) < 0) { + printk(BIOS_ERR, "smm store: lookup of com buffer failed\n"); + return NULL; + } + + if (offset >= region_device_sz(com_buf)) { + printk(BIOS_ERR, "smm store: offset out of range\n"); + return NULL; + } + + void *ptr = rdev_mmap(com_buf, offset, bufsize); + if (!ptr) + printk(BIOS_ERR, "smm store: not enough space for new data\n"); + + return ptr; +} + +/** + * Reads the specified block of the SMMSTORE and places it in the communication + * buffer. + * @param block_id The id of the block to operate on + * @param offset Offset within the block. + * Must be smaller than the block size. + * @param bufsize Size of chunk to read within the block. + * Must be smaller than the block size. + + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawread_region(uint32_t block_id, uint32_t offset, uint32_t bufsize) +{ + struct region_device store; + struct region_device com_buf; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + void *ptr = mmap_com_buf(&com_buf, offset, bufsize); + if (!ptr) + return -1; + + printk(BIOS_DEBUG, "smm store: reading %p block %d, offset=0x%x, size=%x\n", + ptr, block_id, offset, bufsize); + + ssize_t ret = rdev_readat(&store, ptr, block_id * SMM_BLOCK_SIZE + offset, bufsize); + rdev_munmap(&com_buf, ptr); + if (ret < 0) + return -1; + + return 0; +} + +/** + * Writes the specified block of the SMMSTORE by reading it from the communication + * buffer. + * @param block_id The id of the block to operate on + * @param offset Offset within the block. + * Must be smaller than the block size. + * @param bufsize Size of chunk to read within the block. + * Must be smaller than the block size. + + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawwrite_region(uint32_t block_id, uint32_t offset, uint32_t bufsize) +{ + struct region_device store; + struct region_device com_buf; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + if (rdev_chain(&store, &store, block_id * SMM_BLOCK_SIZE + offset, bufsize)) { + printk(BIOS_ERR, "smm store: not enough space for new data\n"); + return -1; + } + + void *ptr = mmap_com_buf(&com_buf, offset, bufsize); + if (!ptr) + return -1; + + printk(BIOS_DEBUG, "smm store: writing %p block %d, offset=0x%x, size=%x\n", + ptr, block_id, offset, bufsize); + + ssize_t ret = rdev_writeat(&store, ptr, 0, bufsize); + rdev_munmap(&com_buf, ptr); + if (ret < 0) + return -1; + + return 0; +} + +/** + * Erases the specified block of the SMMSTORE. The communication buffer remains untouched. + * + * @param block_id The id of the block to operate on + * + * @return Returns -1 on error, 0 on success. + */ +int smmstore_rawclear_region(uint32_t block_id) +{ + struct region_device store; + + if (lookup_block_in_store(&store, block_id) < 0) + return -1; + + ssize_t ret = rdev_eraseat(&store, block_id * SMM_BLOCK_SIZE, SMM_BLOCK_SIZE); + if (ret != SMM_BLOCK_SIZE) { + printk(BIOS_ERR, "smm store: erasing block failed\n"); + return -1; + } + + return 0; +} diff --git a/src/include/smmstore.h b/src/include/smmstore.h index ff0b72001a..2c37ca39b9 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -10,10 +10,18 @@ #define SMMSTORE_RET_FAILURE 1 #define SMMSTORE_RET_UNSUPPORTED 2 +/* Version 1 */ #define SMMSTORE_CMD_CLEAR 1 #define SMMSTORE_CMD_READ 2 #define SMMSTORE_CMD_APPEND 3 +/* Version 2 */ +#define SMMSTORE_CMD_INIT 4 +#define SMMSTORE_CMD_RAW_READ 5 +#define SMMSTORE_CMD_RAW_WRITE 6 +#define SMMSTORE_CMD_RAW_CLEAR 7 + +/* Version 1 */ struct smmstore_params_read { void *buf; ssize_t bufsize; @@ -26,12 +34,90 @@ struct smmstore_params_append { size_t valsize; }; -/* SMM responder */ +/* Version 2 */ +/* + * The Version 2 protocol separates the SMMSTORE into 64KiB blocks, each + * of which can be read/written/cleared in an independent manner. The + * data format isn't specified. See documentation page for more details. + */ + +#define SMM_BLOCK_SIZE (64 * KiB) + +/* + * Sets the communication buffer to use for read and write operations. + */ +struct smmstore_params_init { + uint32_t com_buffer; + uint32_t com_buffer_size; +} __packed; + +/* + * Returns the number of blocks the SMMSTORE supports and their size. + * For EDK2 this should be at least two blocks with 64 KiB each. + * The mmap_addr is set the memory mapped physical address of the SMMSTORE. + */ +struct smmstore_params_info { + uint32_t num_blocks; + uint32_t block_size; + uint32_t mmap_addr; +} __packed; + +/* + * Reads a chunk of raw data with size @bufsize from the block specified by + * @block_id starting at @bufoffset. + * The read data is placed in memory pointed to by @buf. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_write { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Writes a chunk of raw data with size @bufsize to the block specified by + * @block_id starting at @bufoffset. + * + * @block_id must be less than num_blocks + * @bufoffset + @bufsize must be less than block_size + */ +struct smmstore_params_raw_read { + uint32_t bufsize; + uint32_t bufoffset; + uint32_t block_id; +} __packed; + +/* + * Erases the specified block. + * + * @block_id must be less than num_blocks + */ +struct smmstore_params_raw_clear { + uint32_t block_id; +} __packed; + + +/* SMM handler */ uint32_t smmstore_exec(uint8_t command, void *param); -/* implementation */ +/* Implementation of Version 1 */ int smmstore_read_region(void *buf, ssize_t *bufsize); -int smmstore_append_data(void *key, uint32_t key_sz, - void *value, uint32_t value_sz); +int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); + +/* Implementation of Version 2 */ +int smmstore_init(void *buf, size_t len); +int smmstore_rawread_region(uint32_t block_id, uint32_t offset, uint32_t bufsize); +int smmstore_rawwrite_region(uint32_t block_id, uint32_t offset, uint32_t bufsize); +int smmstore_rawclear_region(uint32_t block_id); +#if ENV_RAMSTAGE +int smmstore_get_info(struct smmstore_params_info *info); +#endif + +/* Advertise SMMSTORE v2 support */ +struct lb_header; +void lb_smmstorev2(struct lb_header *header); + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9148405879..857f5a52c3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -20,6 +20,8 @@ #include #include #include +#include + #if CONFIG(USE_OPTION_TABLE) #include #endif @@ -548,6 +550,10 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) add_cbmem_pointers(head); + /* SMMSTORE v2 */ + if (CONFIG(SMMSTORE_V2)) + lb_smmstorev2(head); + /* Add board-specific table entries, if any. */ lb_board(head); From 2560ad3233a2212a5346755137c9a333df14d004 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 28 Sep 2020 15:23:35 -0600 Subject: [PATCH 186/354] soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt() Prepare for common ACPI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845 Reviewed-by: Stefan Reinauer Reviewed-by: Jay Talbott Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/acpi.c | 28 ++++++++++++++++++---------- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 7 +++++++ 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index a1ebc4ae92..8d3e86a10b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -130,13 +130,18 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; @@ -151,26 +156,29 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->duty_offset = 1; fadt->day_alrm = 0xd; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | + fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - /* General-Purpose Event Registers */ + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index db1d3d2bd2..d0b82e57db 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -52,6 +52,13 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE); +} + /* * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() * with a call from the common/function or find another way to call this at the correct place From 97321db21da8a1166b03bc8259c8a3adc83b191f Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 28 Sep 2020 23:35:08 -0600 Subject: [PATCH 187/354] soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c De-duplicate and prepare for common ACPI. Move common northbridge ACPI code to nb_acpi.c. There are a few differences between the skx and cpx defined FSP hob names and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)). Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Jay Talbott Reviewed-by: Arthur Heymans --- src/soc/intel/xeon_sp/Makefile.inc | 2 +- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 465 ------------------------ src/soc/intel/xeon_sp/nb_acpi.c | 508 +++++++++++++++++++++++++++ src/soc/intel/xeon_sp/skx/soc_acpi.c | 466 ------------------------ 4 files changed, 509 insertions(+), 932 deletions(-) create mode 100644 src/soc/intel/xeon_sp/nb_acpi.c diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 3bbf6b725e..8a26c14acc 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index d0b82e57db..fab221166c 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -255,468 +255,3 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) return current; } - -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - unsigned int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; - - memory_map = get_system_memory_map(); - assert(memory_map != NULL); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - unsigned int nodes = xeon_sp_get_socket_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8 + nodes * nodes; - return current; -} - -/* - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACK0 stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int port) -{ - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else - return -1; -} - -/* - * This function adds PCIe bridge device entry in DMAR table. If it is called - * in the context of ATSR subtable, it adds ATSR subtable when it is first called. - */ -static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, - bool is_atsr, bool *first) -{ - - if (get_stack_for_port(port) != stack) - return 0; - - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; - - const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - return 0; - - unsigned long atsr_size = 0; - unsigned long pci_br_size = 0; - if (is_atsr == true && first && *first == true) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", 0, pcie_seg); - atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); - *first = false; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); - - return (atsr_size + pci_br_size); -} - -static unsigned long acpi_create_drhd(unsigned long current, int socket, - int stack, const IIO_UDS *hob) -{ - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - - uint32_t enum_id; - unsigned long tmp = current; - - uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - uint32_t reg_base = - hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); - - /* Do not generate DRHD for non-PCIe stack */ - if (!reg_base) - return current; - - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - - // Add PCH IOAPIC - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - } - - // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); - - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } - - // Add PCIe Ports - if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int p = PORT_0; p < MAX_PORTS; ++p) - current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, - iio_resource, pcie_seg, false, NULL); - - // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } - } - - // Add HPET - if (socket == 0 && stack == CSTACK) { - uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count - printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", - __func__, hpet_capid, num_hpets); - //BIT 15 - if (num_hpets && (num_hpets != 0x1f) && - (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { - printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); - } - } - - acpi_dmar_drhd_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) -{ - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - unsigned long tmp = current; - bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " - "vtd_mmio_cap: 0x%llx\n", - __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); - - // ATSR is applicable only for platform supporting device IOTLBs - // through the VT-d extended capability register - assert(vtd_mmio_cap != 0xffffffffffffffff); - if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 - continue; - - for (int p = PORT_0; p < MAX_PORTS; ++p) { - if (socket == 0 && p == PORT_0) - continue; - current += acpi_create_dmar_ds_pci_br_for_port(current, p, - stack, iio_resource, pcie_seg, true, &first); - } - } - if (tmp != current) - acpi_dmar_atsr_fixup(tmp, current); - } - - return current; -} - -static unsigned long acpi_create_rmrr(unsigned long current) -{ - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_rhsa(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " - "Proximity Domain: 0x%x\n", vtd_base, socket); - current += acpi_create_dmar_rhsa(current, vtd_base, socket); - } - } - - return current; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - // DRHD - for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { - int socket = iio; - if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry - socket = 0; - - if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack, hob); - current = acpi_create_drhd(current, socket, CSTACK, hob); - } else { - for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack, hob); - } - } - - // RMRR - current = acpi_create_rmrr(current); - - // Root Port ATS Capability - current = acpi_create_atsr(current, hob); - - // RHSA - current = acpi_create_rhsa(current); - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_dmar_t *dmar; - - const config_t *const config = config_of(device); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* DMAR */ - if (config->vtd_support) { - current = ALIGN(current, 8); - dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - } - - return current; -} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c new file mode 100644 index 0000000000..1329feb0d6 --- /dev/null +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -0,0 +1,508 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* Northbridge(NUMA) ACPI table generation. SRAT, SLIT, etc */ + +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + unsigned int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + unsigned int mmap_index; + + memory_map = get_system_memory_map(); + assert(memory_map != NULL); + printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + unsigned int nodes = xeon_sp_get_socket_count(); +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + int nodes = get_cpu_count(); +#endif /* SOC_INTEL_SKYLAKE_SP */ + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8 + nodes * nodes; + return current; +} + +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +static int get_stack_for_port(int port) +{ +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +#endif /* SOC_INTEL_COOPERLAKE_SP */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else if (port >= PORT_4A && port <= PORT_4D) + return PSTACK3; // MCP0 + else if (port >= PORT_5A && port <= PORT_5D) + return PSTACK4; // MCP1 + else + return -1; +#endif /* SOC_INTEL_SKYLAKE_SP */ +} + +/* + * This function adds PCIe bridge device entry in DMAR table. If it is called + * in the context of ATSR subtable, it adds ATSR subtable when it is first called. + */ +static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, + int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + bool is_atsr, bool *first) +{ + + if (get_stack_for_port(port) != stack) + return 0; + + const uint32_t bus = iio_resource.StackRes[stack].BusBase; + const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + + const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + return 0; + + unsigned long atsr_size = 0; + unsigned long pci_br_size = 0; + if (is_atsr == true && first && *first == true) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", 0, pcie_seg); + atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); + *first = false; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); + + return (atsr_size + pci_br_size); +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, + int stack, const IIO_UDS *hob) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + /* Do not generate DRHD for non-PCIe stack */ + if (!reg_base) + return current; + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = PORT_0; p < MAX_PORTS; ++p) + current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, + iio_resource, pcie_seg, false, NULL); + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) +{ + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = iio_resource.StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = PORT_0; p < MAX_PORTS; ++p) { + if (socket == 0 && p == PORT_0) + continue; + current += acpi_create_dmar_ds_pci_br_for_port(current, p, + stack, iio_resource, pcie_seg, true, &first); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack, hob); + current = acpi_create_drhd(current, socket, CSTACK, hob); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack, hob); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // Root Port ATS Capability + current = acpi_create_atsr(current, hob); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const config_t *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 9c07ec7021..b6b39f2989 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -153,469 +153,3 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) return current; } - -/* Northbridge SRAT,SLIT, etc. Make a common entry point and use. */ -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) -{ - const struct SystemMemoryMapHob *memory_map; - unsigned int mmap_index; - - memory_map = get_system_memory_map(); - assert(memory_map != NULL); - printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); - - mmap_index = 0; - for (int e = 0; e < memory_map->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; - uint64_t addr = - (uint64_t) ((uint64_t)mem_element->BaseAddress << - MEM_ADDR_64MB_SHIFT_BITS); - uint64_t size = - (uint64_t) ((uint64_t)mem_element->ElementSize << - MEM_ADDR_64MB_SHIFT_BITS); - - printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " - "ElementSize: 0x%x, reserved: %d\n", - e, addr, mem_element->BaseAddress, size, - mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); - - assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); - - /* skip reserved memory region */ - if (mem_element->Type & MEM_TYPE_RESERVED) - continue; - - /* skip if this address is already added */ - bool skip = false; - for (int idx = 0; idx < mmap_index; ++idx) { - uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + - srat_mem[idx].base_address_low; - if (addr == base_addr) { - skip = true; - break; - } - } - if (skip) - continue; - - srat_mem[mmap_index].type = 1; /* Memory affinity structure */ - srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); - srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); - srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); - srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); - srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; - if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; - ++mmap_index; - } - - return mmap_index; -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; - unsigned int mem_count; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - mem_count = get_srat_memory_entries(srat_mem); - for (int i = 0; i < mem_count; ++i) { - printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " - "length: 0x%x%x, proximity_domain: %d, flags: %x\n", - i, srat_mem[i].length, - srat_mem[i].base_address_high, srat_mem[i].base_address_low, - srat_mem[i].length_high, srat_mem[i].length_low, - srat_mem[i].proximity_domain, srat_mem[i].flags); - memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); - current += srat_mem[i].length; - } - - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - int nodes = get_cpu_count(); - - uint8_t *p = (uint8_t *)current; - memset(p, 0, 8 + nodes * nodes); - *p = (uint8_t)nodes; - p += 8; - - /* this assumes fully connected socket topology */ - for (int i = 0; i < nodes; i++) { - for (int j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8+nodes*nodes; - return current; -} - - -static int get_stack_for_port(int p) -{ - if (p == 0) - return CSTACK; - else if (p >= PORT_1A && p <= PORT_1D) - return PSTACK0; - else if (p >= PORT_2A && p <= PORT_2D) - return PSTACK1; - else if (p >= PORT_3A && p <= PORT_3D) - return PSTACK2; - else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK3; // MCP0 - else - return PSTACK4; // MCP1 -} - -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) -{ - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - - uint32_t enum_id; - unsigned long tmp = current; - - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - uint32_t reg_base = - hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); - - // Add DRHD Hardware Unit - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - - // Add PCH IOAPIC - if (socket == 0 && stack == CSTACK) { - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); - } - - // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); - - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); - } - } - - // Add PCIe Ports - if (socket != 0 || stack != CSTACK) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, - bus, dev, func); - } - - // Add VMD - if (hob->PlatformData.VMDStackEnable[socket][stack] && - stack >= PSTACK0 && stack <= PSTACK2) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, - bus, VMD_DEV_NUM, VMD_FUNC_NUM); - } - } - - // Add HPET - if (socket == 0 && stack == CSTACK) { - uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); - uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count - printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", - __func__, hpet_capid, num_hpets); - //BIT 15 - if (num_hpets && (num_hpets != 0x1f) && - (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { - printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); - } - } - - acpi_dmar_drhd_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_atsr(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - unsigned long tmp = current; - bool first = true; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " - "vtd_mmio_cap: 0x%llx\n", - __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); - - // ATSR is applicable only for platform supporting device IOTLBs - // through the VT-d extended capability register - assert(vtd_mmio_cap != 0xffffffffffffffff); - if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 - continue; - - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - if (socket == 0 && p == 0) - continue; - if (get_stack_for_port(p) != stack) - continue; - - uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; - uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; - - u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), - PCI_VENDOR_ID); - if (id == 0xffffffff) - continue; - - if (first) { - printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", - 0, pcie_seg); - current += acpi_create_dmar_atsr(current, 0, pcie_seg); - first = 0; - } - - printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); - current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); - } - } - if (tmp != current) - acpi_dmar_atsr_fixup(tmp, current); - } - - return current; -} - -static unsigned long acpi_create_rmrr(unsigned long current) -{ - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - - return current; -} - -static unsigned long acpi_create_rhsa(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; - if (!vtd_base) - continue; - - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " - "Proximity Domain: 0x%x\n", vtd_base, socket); - current += acpi_create_dmar_rhsa(current, vtd_base, socket); - } - } - - return current; -} - -static unsigned long acpi_fill_dmar(unsigned long current) -{ - size_t hob_size; - const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - - // DRHD - for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { - int socket = iio; - if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry - socket = 0; - - if (socket == 0) { - for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); - } else { - for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - } - } - - // RMRR - current = acpi_create_rmrr(current); - - // ATSR - causes hang - current = acpi_create_atsr(current); - - // RHSA - current = acpi_create_rhsa(current); - - return current; -} - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_dmar_t *dmar; - - const config_t *const config = config_of(device); - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - /* DMAR */ - if (config->vtd_support) { - current = ALIGN(current, 8); - dmar = (acpi_dmar_t *)current; - printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", - (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); - acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); - current += dmar->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); - } - - return current; -} From 985d956833180679bcd8da8c9bbac7522d1f8b8e Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 5 Oct 2020 17:11:13 -0600 Subject: [PATCH 188/354] soc/intel/xeon_sp/skx/: Clean up soc_util.c Remove unused c_util.c helper functions and clean up soc_util.h in preparation for merging common code with cpx/. Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094 Reviewed-by: Arthur Heymans Reviewed-by: Jay Talbott Tested-by: build bot (Jenkins) --- .../intel/xeon_sp/skx/include/soc/soc_util.h | 30 ++++----- src/soc/intel/xeon_sp/skx/soc_util.c | 62 +------------------ 2 files changed, 12 insertions(+), 80 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 0eac8368e0..d641f76a3d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -5,34 +5,26 @@ #include #include -#include -#include struct iiostack_resource { uint8_t no_of_stacks; STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -uintptr_t get_tolm(uint32_t bus); -void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); -uintptr_t get_cha_mmcfg_base(uint32_t bus); -uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory - -uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); - -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); void get_iiostack_info(struct iiostack_resource *info); -int get_threads_per_package(void); -int get_platform_thread_count(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); - -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, - uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); - -const struct SystemMemoryMapHob *get_system_memory_map(void); void xeonsp_init_cpu_config(void); -void set_bios_init_completion(void); + void config_reset_cpl3_csrs(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread); + +int get_platform_thread_count(void); +int get_threads_per_package(void); +const struct SystemMemoryMapHob *get_system_memory_map(void); + +void set_bios_init_completion(void); + #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 50f091ec94..8b29e7f848 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -17,61 +17,6 @@ #include #include -/* - * Get TOLM CSR B0:D5:F0:Offset_d0h - */ -uintptr_t get_tolm(uint32_t bus) -{ - uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TOLM_CSR); - uintptr_t addr = w & 0xfc000000; - printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr); - return addr; -} - -void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit) -{ - uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TSEG_BASE_CSR); - uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), - VTD_TSEG_LIMIT_CSR); - *base = w1 & 0xfff00000; - *limit = wh & 0xfff00000; -} - -/* - * Get MMCFG CSR B1:D29:F1:Offset_C0h - */ -uintptr_t get_cha_mmcfg_base(uint32_t bus) -{ - uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, - CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR); - uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, - CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4); - uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26); - printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n", - wl, wh, addr); - return addr; -} - -uint32_t top_of_32bit_ram(void) -{ - uintptr_t mmcfg, tolm; - uint32_t bus0 = 0, bus1 = 0; - uint32_t base = 0, limit = 0; - - get_cpubusnos(&bus0, &bus1, NULL, NULL); - - mmcfg = get_cha_mmcfg_base(bus1); - tolm = get_tolm(bus0); - printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n", - bus0, bus1, mmcfg, tolm); - get_tseg_base_lim(bus0, &base, &limit); - printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit); - - /* We will use TSEG base as the top of DRAM */ - return base; -} /* * +-------------------------+ TOLM @@ -101,12 +46,7 @@ uint32_t top_of_32bit_ram(void) * +-------------------------+ */ -uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) -{ - return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset); -} - -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { size_t hob_size; const IIO_UDS *hob; From 92eab64a43098849dd0784c11620e3dbe9d8eb35 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 15 Oct 2020 19:43:33 +0200 Subject: [PATCH 189/354] configs: Add TXT-enabled config for Asrock B85M Pro4 This config selects the necessary options to enable Intel TXT on the Asrock B85M Pro4, and allows the code to be build-tested. Note that the current TXT code will not work, as it was written for Broadwell-DE. Subsequent commits will adapt the code as necessary to work on Haswell. Compatible BIOS and SINIT ACMs can be retrieved from a firmware update for the Supermicro X10SLH. As they are not in the blobs repository, use the STM binary as a placeholder so as to allow build-testing the code. Change-Id: Ibf8db5fdfac5b527520023277c6370f6efa71717 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46489 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../config.asrock_b85m_pro4.tpm2_txt_placeholder_acms | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms diff --git a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms new file mode 100644 index 0000000000..856701fee8 --- /dev/null +++ b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms @@ -0,0 +1,10 @@ +# Known-working configuration to boot with TXT enabled. Since BIOS +# and SINIT ACM blobs are missing, use something else as placeholder. +# Used ACMs were extracted from a Supermicro X10SLH firmware update. +CONFIG_VENDOR_ASROCK=y +CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_USER_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" +CONFIG_INTEL_TXT_LOGGING=y From 5a6daa6b7288eed6561d90fdb7afebbc01ade869 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 15 Oct 2020 23:48:25 +0200 Subject: [PATCH 190/354] sec/intel/txt: Move DPR size to Kconfig Instead of hardcoding the size in code, expose it as a Kconfig symbol. This allows platform code to program the size in the MCH DPR register. Change-Id: I9b9bcfc7ceefea6882f8133a6c3755da2e64a80c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46491 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/Kconfig | 9 +++++++++ src/security/intel/txt/ramstage.c | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 3dd912ea6e..b1d0475edf 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -31,6 +31,15 @@ config INTEL_TXT_SINITACM_FILE access to Intel resources. Or for some platforms found inside the blob repository. +config INTEL_TXT_DPR_SIZE + int + range 0 255 + default 3 + help + Specify the size the DPR region needs to have. On at least Haswell, + the MRC does not have an input to specify the size of DPR, so this + field is only used to check if the programmed size is large enough. + config INTEL_TXT_LOGGING bool "Enable verbose logging" help diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index f532a2fbd8..8d9f5d9b3c 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -254,7 +254,7 @@ static void lockdown_intel_txt(void *unused) return; } - if (dpr.size < 3) { + if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) { printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); return; } From 28d040840998aa616b403fb9325238374d3730b8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 00:47:45 +0200 Subject: [PATCH 191/354] sec/intel/txt/common.c: Only log ACM error on failure The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is set, or if CBnT is supported and bit 61 is set. Moreover, this is only applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers). This allows TXT to work on client platforms, where these registers are regular scratchpads and are not necessarily written to by the BIOS ACM. Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/security/intel/txt/common.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 5f8a976946..737ab0a4be 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -303,8 +303,6 @@ int intel_txt_run_bios_acm(const u8 input_params) intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); return -1; } - if (intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)) != 1) - return -1; return 0; } From 08de7d6bbd69758db9b0840213590a18933aa185 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 01:01:14 +0200 Subject: [PATCH 192/354] sec/intel/txt: Add and fill in BIOS Specification info This is not critical to function, but is nice to have. Change-Id: Ieb5f41f3e4c5644a31606434916c35542d35617a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46493 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/security/intel/txt/ramstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8d9f5d9b3c..5d0d1217fa 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -298,6 +298,7 @@ static void lockdown_intel_txt(void *unused) */ struct { struct txt_biosdataregion bdr; + struct txt_bios_spec_ver_element spec; struct txt_heap_acm_element heap_acm; struct txt_extended_data_element_header end; } __packed data = {0}; @@ -350,6 +351,13 @@ static void lockdown_intel_txt(void *unused) data.bdr.support_acpi_ppi = 0; data.bdr.platform_type = 0; + /* Fill in the version of the used TXT BIOS Specification */ + data.spec.header.type = HEAP_EXTDATA_TYPE_BIOS_SPEC_VER; + data.spec.header.size = sizeof(data.spec); + data.spec.ver_major = 2; + data.spec.ver_minor = 1; + data.spec.ver_revision = 0; + /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; data.heap_acm.header.size = sizeof(data.heap_acm); From 8f7e2a3add50f53361704a0e16466dd4c91e2416 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 01:07:18 +0200 Subject: [PATCH 193/354] sec/intel/txt/ramstage.c: Extract heap init into a function Heap initialization is self-contained, so place it into a separate function. Also, do it after the MSEG registers have been written, so that all register writes are grouped together. This has no impact. Change-Id: Id108f4cfcd2896d881d9ba267888f7ed5dd984fa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46494 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/ramstage.c | 197 +++++++++++++++--------------- 1 file changed, 101 insertions(+), 96 deletions(-) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 5d0d1217fa..2d56d1fd61 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -194,103 +194,8 @@ static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length) } } -/** - * Finalize the TXT device. - * - * - Lock TXT register. - * - Protect TSEG using DMA protected regions. - * - Setup TXT regions. - * - Place SINIT ACM in TXT_SINIT memory segment. - * - Fill TXT BIOSDATA region. - */ -static void lockdown_intel_txt(void *unused) +static void txt_initialize_heap(void) { - const uint64_t status = read64((void *)TXT_SPAD); - - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - if (status & ACMSTS_TXT_DISABLED) - return; - - printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); - - /* Lock TXT config, unlocks TXT_HEAP_BASE */ - if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { - printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); - printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); - return; - } - - /* - * Document Number: 558294 - * Chapter 5.5.6.1 DMA Protection Memory Region - */ - - const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & - TXT_CAPABILITIES_DPR); - printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); - - if (dpr_capable) { - /* Verify the DPR settings on the MCH and mirror them to TXT public space */ - union dpr_register dpr = txt_get_chipset_dpr(); - - printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw); - - printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n", - (dpr.top - dpr.size) * MiB, dpr.size); - - // DPR TODO: implement SA_ENABLE_DPR in the intelblocks - - if (!dpr.lock) { - printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n"); - return; - } - - if (!dpr.epm || !dpr.prs) { - printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n"); - return; - } - - if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) { - printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); - return; - } - - if (dpr.top * MiB != tseg_base) { - printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n"); - return; - } - - /* Clear reserved bits */ - dpr.prs = 0; - dpr.epm = 0; - - write64((void *)TXT_DPR, dpr.raw); - - printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", - read32((void *)TXT_DPR)); - } - - /* - * Document Number: 558294 - * Chapter 5.5.6.3 Intel TXT Heap Memory Region - */ - write64((void *)TXT_HEAP_SIZE, 0xE0000); - write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); - - /* - * Document Number: 558294 - * Chapter 5.5.6.2 SINIT Memory Region - */ - write64((void *)TXT_SINIT_SIZE, 0x20000); - write64((void *)TXT_SINIT_BASE, - ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - - read64((void *)TXT_SINIT_SIZE), 4096)); - /* * BIOS Data Format * Chapter C.2 @@ -392,6 +297,104 @@ static void lockdown_intel_txt(void *unused) /* SinitMLEData */ /* FIXME: Does firmware need to write this? */ push_sinit_heap(&heap_struct, NULL, 0); +} + +/** + * Finalize the TXT device. + * + * - Lock TXT register. + * - Protect TSEG using DMA protected regions. + * - Setup TXT regions. + * - Place SINIT ACM in TXT_SINIT memory segment. + * - Fill TXT BIOSDATA region. + */ +static void lockdown_intel_txt(void *unused) +{ + const uint64_t status = read64((void *)TXT_SPAD); + + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + if (status & ACMSTS_TXT_DISABLED) + return; + + printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); + + /* Lock TXT config, unlocks TXT_HEAP_BASE */ + if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { + printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); + printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); + return; + } + + /* + * Document Number: 558294 + * Chapter 5.5.6.1 DMA Protection Memory Region + */ + + const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + TXT_CAPABILITIES_DPR); + printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); + + if (dpr_capable) { + /* Verify the DPR settings on the MCH and mirror them to TXT public space */ + union dpr_register dpr = txt_get_chipset_dpr(); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR 0x%08x\n", dpr.raw); + + printk(BIOS_DEBUG, "TEE-TXT: MCH DPR base @ 0x%08x size %u MiB\n", + (dpr.top - dpr.size) * MiB, dpr.size); + + // DPR TODO: implement SA_ENABLE_DPR in the intelblocks + + if (!dpr.lock) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR not locked.\n"); + return; + } + + if (!dpr.epm || !dpr.prs) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR protection not active.\n"); + return; + } + + if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); + return; + } + + if (dpr.top * MiB != tseg_base) { + printk(BIOS_ERR, "TEE-TXT: MCH DPR top does not equal TSEG base.\n"); + return; + } + + /* Clear reserved bits */ + dpr.prs = 0; + dpr.epm = 0; + + write64((void *)TXT_DPR, dpr.raw); + + printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", + read32((void *)TXT_DPR)); + } + + /* + * Document Number: 558294 + * Chapter 5.5.6.3 Intel TXT Heap Memory Region + */ + write64((void *)TXT_HEAP_SIZE, 0xE0000); + write64((void *)TXT_HEAP_BASE, + ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); + + /* + * Document Number: 558294 + * Chapter 5.5.6.2 SINIT Memory Region + */ + write64((void *)TXT_SINIT_SIZE, 0x20000); + write64((void *)TXT_SINIT_BASE, + ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - + read64((void *)TXT_SINIT_SIZE), 4096)); /* * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. @@ -404,6 +407,8 @@ static void lockdown_intel_txt(void *unused) write64((void *)TXT_MSEG_SIZE, 0); write64((void *)TXT_MSEG_BASE, 0); + txt_initialize_heap(); + if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_regions(); } From c037695c195595d9ecc2112d0359b37cfe253345 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 01:12:00 +0200 Subject: [PATCH 194/354] sec/intel/txt/ramstage.c: Do not init the heap on S3 resume It causes problems on Haswell: SINIT detects that the heap tables differ in size, and then issues a Class Code 9, Major Error Code 1 TXT reset. Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/ramstage.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 2d56d1fd61..00e9ce72a2 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -407,7 +407,9 @@ static void lockdown_intel_txt(void *unused) write64((void *)TXT_MSEG_SIZE, 0); write64((void *)TXT_MSEG_BASE, 0); - txt_initialize_heap(); + /* Only initialize the heap on regular boots */ + if (!acpi_is_wakeup_s3()) + txt_initialize_heap(); if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_regions(); From 8a285fd8a5dabbf6adaf96e4101917ede7c98316 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 10:49:12 +0200 Subject: [PATCH 195/354] sec/intel/txt: Allow skipping ACM NOP function This is merely used to test whether the BIOS ACM calling code is working properly. There's no need to do this on production platforms. Testing on Haswell showed that running this NOP function breaks S3 resume with TXT. Add a Kconfig bool to control whether the NOP function is to be invoked. Change-Id: Ibf461c18a96f1add7867e1320726fadec65b7184 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46496 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/Kconfig | 6 ++++++ src/security/intel/txt/ramstage.c | 23 +++++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index b1d0475edf..d3ef2a64db 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -40,6 +40,12 @@ config INTEL_TXT_DPR_SIZE the MRC does not have an input to specify the size of DPR, so this field is only used to check if the programmed size is large enough. +config INTEL_TXT_TEST_BIOS_ACM_CALLING_CODE + bool "Test BIOS ACM calling code with NOP function" + help + Run a NOP function of the BIOS ACM to check that the ACM calling code + is functioning properly. Use in pre-production environments only! + config INTEL_TXT_LOGGING bool "Enable verbose logging" help diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 00e9ce72a2..c39194ba47 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -151,17 +151,20 @@ static void init_intel_txt(void *unused) return; } - printk(BIOS_INFO, "TEE-TXT: Testing BIOS ACM calling code...\n"); + if (CONFIG(INTEL_TXT_TEST_BIOS_ACM_CALLING_CODE)) { + printk(BIOS_INFO, "TEE-TXT: Testing BIOS ACM calling code...\n"); - /* - * Test BIOS ACM code. - * ACM should do nothing on reserved functions, and return an error code - * in TXT_BIOSACM_ERRORCODE. Tests showed that this is not true. - * Use special function "NOP" that does 'nothing'. - */ - if (intel_txt_run_bios_acm(ACMINPUT_NOP) < 0) { - printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM with NOP function.\n"); - return; + /* + * Test BIOS ACM code. + * ACM should do nothing on reserved functions, and return an error code + * in TXT_BIOSACM_ERRORCODE. Tests showed that this is not true. + * Use special function "NOP" that does 'nothing'. + */ + if (intel_txt_run_bios_acm(ACMINPUT_NOP) < 0) { + printk(BIOS_ERR, + "TEE-TXT: Error calling BIOS ACM with NOP function.\n"); + return; + } } if (status & (ACMSTS_BIOS_TRUSTED | ACMSTS_IBB_MEASURED)) { From e70a3f8822d6c1e0b0f1dc86464acfb24c80b450 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 10:58:57 +0200 Subject: [PATCH 196/354] sec/intel/txt: Always run SCHECK on regular boots When Boot Guard is disabled or not available, the IBB might not even exist. This is the case on traditional (non-ULT) Haswell, for example. Leave the S3 resume check as-is for now. Skylake and newer may need to run SCHECK on resume as well, but I lack the hardware to test this on. Change-Id: I70231f60d4d4c5bc8ee0fcbb0651896256fdd391 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46497 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/ramstage.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index c39194ba47..86bf7aa428 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -168,15 +168,16 @@ static void init_intel_txt(void *unused) } if (status & (ACMSTS_BIOS_TRUSTED | ACMSTS_IBB_MEASURED)) { + printk(BIOS_INFO, "TEE-TXT: Logging IBB measurements...\n"); log_ibb_measurements(); + } - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); - if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { - printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); - return; - } + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); + if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { + printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); + return; } } } From 6c4028dd3ddf571ef2e992de8d9927b598f7cd6b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 11:52:40 +0200 Subject: [PATCH 197/354] sec/intel/txt: Only run LockConfig for LT-SX LockConfig only exists on Intel TXT for Servers. Check whether this is supported using GETSEC[PARAMETERS]. This eliminates a spurious error for Client TXT platforms such as Haswell, and is a no-op on TXT for Servers. Change-Id: Ibb7b0eeba1489dc522d06ab27eafcaa0248b7083 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46498 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/ramstage.c | 22 +++++++++++++++++----- src/security/intel/txt/txt_register.h | 3 +-- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 86bf7aa428..76eeaaffef 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -316,6 +316,7 @@ static void lockdown_intel_txt(void *unused) { const uint64_t status = read64((void *)TXT_SPAD); + uint32_t txt_feature_flags = 0; uintptr_t tseg_base; size_t tseg_size; @@ -324,13 +325,24 @@ static void lockdown_intel_txt(void *unused) if (status & ACMSTS_TXT_DISABLED) return; - printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); + /* + * Document Number: 558294 + * Chapter 5.4.3 Detection of Intel TXT Capability + */ - /* Lock TXT config, unlocks TXT_HEAP_BASE */ - if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { - printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); - printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); + if (!getsec_parameter(NULL, NULL, NULL, NULL, NULL, &txt_feature_flags)) return; + + /* LockConfig only exists on Intel TXT for Servers */ + if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) { + printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); + + /* Lock TXT config, unlocks TXT_HEAP_BASE */ + if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { + printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); + printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); + return; + } } /* diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index bbf0a7e72d..c19ec13799 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -132,8 +132,7 @@ #define IA32_GETSEC_SMCTRL 7 #define IA32_GETSEC_WAKEUP 8 -#define GETSEC_PARAMS_TXT_EXT (1ul << 5) -#define GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT (1ul << 1) +#define GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT (1ul << 5) #define GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK (1ul << 6) /* ACM defines */ From 84641c81834841fa6cdad19d06b06c05ba899825 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 29 Aug 2020 02:52:09 +0200 Subject: [PATCH 198/354] nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC option The MRC will perform PCI enumeration, and if it detects a VGA device in a PEG slot, it will disable the IGD and not reserve any memory for it. Since the memory map is locked by the time MRC finishes, the IGD can not be enabled afterwards. Changing this behavior requires patching the MRC. Hiding the PEG devices from MRC allows the IGD to be used even when a dedicated graphics card is present. However, MRC will not program the PEG AFE settings as it should, which can cause stability problems at higher PCIe link speeds. Thus, restrict this workaround to only run when the HASWELL_HIDE_PEG_FROM_MRC option is enabled. This allows the IGD to be disabled and the PEG AFE settings to be programmed when a dedicated graphics card is to be enabled, which results in increased stability. The most ideal way to fix this problem for good is to implement native platform init. Native init is necessary to make Nvidia Optimus usable. Tested on Asrock B85M Pro4, using the PEG slot with a dedicated graphics card as well as without. Graphics in both situations function properly. Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45534 Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/Kconfig | 9 +++++++++ src/northbridge/intel/haswell/early_init.c | 23 ++++++++++++++++------ 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 84be33df4e..04ab373ce2 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -78,6 +78,15 @@ config MRC_FILE The path and filename of the file to use as System Agent binary. +config HASWELL_HIDE_PEG_FROM_MRC + bool "Hide PEG devices from MRC to work around hardcoded MRC behavior" + default y + help + If set, hides all PEG devices from MRC. This allows the iGPU + to be used even when a dedicated graphics card is present. + However, it prevents MRC from programming PEG AFE registers, + which can make PEG devices unstable. When unsure, choose N. + config PRE_GRAPHICS_DELAY int "Graphics initialization delay in ms" default 0 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d0de..79cc27724c 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -84,13 +84,24 @@ static void start_peg2_link_training(const pci_devfn_t dev) printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); /* - * Hide the PEG device while the MRC runs. This is because the MRC makes - * configurations that are not ideal if it sees a VGA device in a PEG slot, - * and it locks registers preventing changes to these configurations. + * The MRC will perform PCI enumeration, and if it detects a VGA + * device in a PEG slot, it will disable the IGD and not reserve + * any memory for it. Since the memory map is locked by the time + * MRC finishes, the IGD can't be enabled afterwards. Wonderful. + * + * If one really wants to enable the Intel iGPU as primary, hide + * all PEG devices during MRC execution. This will trick the MRC + * into thinking there aren't any, and will enable the IGD. Note + * that PEG AFE settings will not be programmed, which may cause + * stability problems at higher PCIe link speeds. The most ideal + * way to fix this problem for good is to implement native init. */ - pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); - peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; - printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); + if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) { + pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0); + peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; + printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", + PCI_FUNC(PCI_DEV2DEVFN(dev))); + } } void haswell_unhide_peg(void) From 7b4d67cf42d7bb0718f2542075f76e5b0cb56548 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 20 Oct 2020 14:17:42 +0200 Subject: [PATCH 199/354] sec/intel/txt: Extract BIOS ACM loading into a function Tested on Asrock B85M Pro4, still boots with TXT enabled. Change-Id: I0b04955b341848ea8627a9c3ffd6a68cd49c3858 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46593 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/common.c | 73 ++++++++++++++++++++------------- 1 file changed, 45 insertions(+), 28 deletions(-) diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 737ab0a4be..88e2b5dddb 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -210,29 +210,28 @@ static int validate_acm(const void *ptr) } /* - * Test all bits for TXT execution. - * - * @return 0 on success + * Prepare to run the BIOS ACM: mmap it from the CBFS and verify that it + * can be launched. Returns pointer to ACM on success, NULL on failure. */ -int intel_txt_run_bios_acm(const u8 input_params) +static void *intel_txt_prepare_bios_acm(struct region_device *acm, size_t *acm_len) { struct cbfsf file; - void *acm_data; - struct region_device acm; - size_t acm_len; - int ret; + void *acm_data = NULL; + + if (!acm || !acm_len) + return NULL; if (cbfs_boot_locate(&file, CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL)) { printk(BIOS_ERR, "TEE-TXT: Couldn't locate BIOS ACM in CBFS.\n"); - return -1; + return NULL; } - cbfs_file_data(&acm, &file); - acm_data = rdev_mmap_full(&acm); - acm_len = region_device_sz(&acm); - if (!acm_data || acm_len == 0) { + cbfs_file_data(acm, &file); + acm_data = rdev_mmap_full(acm); + *acm_len = region_device_sz(acm); + if (!acm_data || *acm_len == 0) { printk(BIOS_ERR, "TEE-TXT: Couldn't map BIOS ACM from CBFS.\n"); - return -1; + return NULL; } /* @@ -242,8 +241,8 @@ int intel_txt_run_bios_acm(const u8 input_params) */ if (!IS_ALIGNED((uintptr_t)acm_data, 4096)) { printk(BIOS_ERR, "TEE-TXT: BIOS ACM isn't mapped at page boundary.\n"); - rdev_munmap(&acm, acm_data); - return -1; + rdev_munmap(acm, acm_data); + return NULL; } /* @@ -251,20 +250,20 @@ int intel_txt_run_bios_acm(const u8 input_params) * SAFER MODE EXTENSIONS REFERENCE. * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D */ - if (!IS_ALIGNED(acm_len, 64)) { + if (!IS_ALIGNED(*acm_len, 64)) { printk(BIOS_ERR, "TEE-TXT: BIOS ACM size isn't multiple of 64.\n"); - rdev_munmap(&acm, acm_data); - return -1; + rdev_munmap(acm, acm_data); + return NULL; } /* * The ACM should be aligned to it's size, but that's not possible, as * some ACMs are not power of two. Use the next power of two for verification. */ - if (!IS_ALIGNED((uintptr_t)acm_data, (1UL << log2_ceil(acm_len)))) { + if (!IS_ALIGNED((uintptr_t)acm_data, (1UL << log2_ceil(*acm_len)))) { printk(BIOS_ERR, "TEE-TXT: BIOS ACM isn't aligned to its size.\n"); - rdev_munmap(&acm, acm_data); - return -1; + rdev_munmap(acm, acm_data); + return NULL; } /* @@ -272,22 +271,40 @@ int intel_txt_run_bios_acm(const u8 input_params) * a page (4 KiB) of unused memory after the BIOS ACM. On Haswell, failure * to do so will cause a TXT reset with Class Code 5, Major Error Code 2. */ - if (popcnt(ALIGN_UP(acm_len, 4096)) > get_var_mtrr_count()) { + if (popcnt(ALIGN_UP(*acm_len, 4096)) > get_var_mtrr_count()) { printk(BIOS_ERR, "TEE-TXT: Not enough MTRRs to cache this BIOS ACM's size.\n"); - rdev_munmap(&acm, acm_data); - return -1; + rdev_munmap(acm, acm_data); + return NULL; } if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_acm_info(acm_data); - ret = validate_acm(acm_data); + const int ret = validate_acm(acm_data); if (ret < 0) { printk(BIOS_ERR, "TEE-TXT: Validation of ACM failed with: %d\n", ret); - rdev_munmap(&acm, acm_data); - return ret; + rdev_munmap(acm, acm_data); + return NULL; } + return acm_data; +} + +/* + * Test all bits for TXT execution. + * + * @return 0 on success + */ +int intel_txt_run_bios_acm(const u8 input_params) +{ + struct region_device acm; + size_t acm_len; + + void *acm_data = intel_txt_prepare_bios_acm(&acm, &acm_len); + + if (!acm_data) + return -1; + /* Call into assembly which invokes the referenced ACM */ getsec_enteraccs(input_params, (uintptr_t)acm_data, acm_len); From 01490258bb26a1bbb7b41e0cf8100ec4d42082cb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 21 Oct 2020 00:19:00 +0200 Subject: [PATCH 200/354] sec/intel/txt: Add `enable_getsec_or_reset` function This can be used to enable GETSEC/SMX in the IA32_FEATURE_CONTROL MSR, and will be put to use on Haswell in subsequent commits. Change-Id: I5a82e515c6352b6ebbc361c6a53ff528c4b6cdba Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46606 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/getsec.c | 31 +++++++++++++++++++++++++++++ src/security/intel/txt/txt_getsec.h | 2 ++ 2 files changed, 33 insertions(+) diff --git a/src/security/intel/txt/getsec.c b/src/security/intel/txt/getsec.c index 422f10d7c8..af9b7bb471 100644 --- a/src/security/intel/txt/getsec.c +++ b/src/security/intel/txt/getsec.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include #include +#include #include #include "txt_register.h" @@ -40,6 +44,33 @@ static bool getsec_enabled(void) return true; } +void enable_getsec_or_reset(void) +{ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + + if (!(msr.lo & FEATURE_CONTROL_LOCK_BIT)) { + /* + * MSR not locked, enable necessary GETSEC and VMX settings. + * We do not lock this MSR here, though. + */ + msr.lo |= 0xff06; + wrmsr(IA32_FEATURE_CONTROL, msr); + + } else if ((msr.lo & 0xff06) != 0xff06) { + /* + * MSR is locked without necessary GETSEC and VMX settings. + * This can happen after internally reflashing a coreboot + * image with different settings, and then doing a warm + * reboot. Perform a full reset in order to unlock the MSR. + */ + printk(BIOS_NOTICE, + "IA32_FEATURE_CONTROL MSR locked with GETSEC and/or VMX disabled.\n" + "Will perform a full reset to unlock this MSR.\n"); + + full_reset(); + } +} + /** * Get information as returned by getsec[PARAMETER]. * Arguments can be set to NULL if not needed. diff --git a/src/security/intel/txt/txt_getsec.h b/src/security/intel/txt/txt_getsec.h index 8e663d51b0..78171a7d5a 100644 --- a/src/security/intel/txt/txt_getsec.h +++ b/src/security/intel/txt/txt_getsec.h @@ -5,6 +5,8 @@ #include +void enable_getsec_or_reset(void); + bool getsec_parameter(uint32_t *version_mask, uint32_t *version_numbers_supported, uint32_t *max_size_acm_area, From 8f8cb95fe92170220ccf7ad44f22073fee561c40 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 20 Oct 2020 23:03:45 +0200 Subject: [PATCH 201/354] sec/intel/txt: Split MTRR setup ASM code into a macro If necessary, SCLEAN needs to run in early romstage, where DRAM is not working yet. In fact, that the DRAM isn't working is the reason to run SCLEAN in the first place. Before running GETSEC, CAR needs to be torn down, as MTRRs have to be reprogrammed to cache the BIOS ACM. Further, running SCLEAN leaves the system in an undefined state, where the only sane thing to do is reset the platform. Thus, invoking SCLEAN requires specific assembly prologue and epilogue sections before and after MTRR setup, and neither DRAM nor CAR may be relied upon for the MTRR setup. In order to handle this without duplicating the MTRR setup code, place it in a macro on a separate file. This needs to be a macro because the call and return instructions rely on the stack being usable, and it is not the case for SCLEAN. The MTRR code clobbers many registers, but no other choice remains when the registers cannot be saved anywhere else. Tested on Asrock B85M Pro4, BIOS ACM can still be launched. Change-Id: I2f5e82f57b458ca1637790ddc1ddc14bba68ac49 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46603 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/security/intel/txt/getsec_enteraccs.S | 74 +++----------------- src/security/intel/txt/getsec_mtrr_setup.inc | 74 ++++++++++++++++++++ 2 files changed, 84 insertions(+), 64 deletions(-) create mode 100644 src/security/intel/txt/getsec_mtrr_setup.inc diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index be038b0607..be3a1b4f0b 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -4,7 +4,7 @@ #include #include -#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) +#include "getsec_mtrr_setup.inc" .macro PUSH_MSR x movl $(\x), %ecx @@ -166,15 +166,6 @@ cond_clear_var_mtrrs: * Intel TXT Software Development Guide (Document: 315168-015) */ - /* - * Important note: The MTRRs must cache less than a page (4 KiB) - * of unused memory after the BIOS ACM. Failure to do so will - * result in a TXT reset with Class Code 5, Major Error Code 2. - * - * The caller must have checked that there are enough variable - * MTRRs to cache the ACM size prior to invoking this routine. - */ - /* Determine size of AC module */ movl 12(%ebp), %eax /* %eax = acmbase */ movl $1, %ebx @@ -191,60 +182,15 @@ cond_clear_var_mtrrs: movd %eax, %xmm0 /* XMM0: Base address of next MTRR */ movd %ebx, %xmm1 /* XMM1: Remaining size to cache */ - /* Get the number of variable MTRRs */ - movl $(MTRR_CAP_MSR), %ecx - rdmsr - andl $(0xff), %eax - - /* Initialize ECX */ - movl $(MTRR_PHYS_BASE(0)), %ecx - - jmp cond_allocate_var_mtrrs - -body_allocate_var_mtrrs: - - /* Program MTRR base */ - xorl %edx, %edx - movd %xmm0, %eax - orl $(MTRR_TYPE_WRBACK), %eax - wrmsr - incl %ecx /* Move index to MTRR_PHYS_MASK */ - - /* Temporarily transfer MSR index to EDX so that CL can be used */ - movl %ecx, %edx - - /* Determine next size to cache */ - bsr %ebx, %ecx - movl $(1), %ebx - shl %cl, %ebx /* Can only use CL here */ - - /* Restore ECX */ - movl %edx, %ecx - - /* Update saved base address */ - addl %ebx, %eax - movd %eax, %xmm0 - - /* Update saved remaining size */ - movd %xmm1, %eax - subl %ebx, %eax - movd %eax, %xmm1 - - /* Program MTRR mask */ - movl MTRR_HIGH_MASK, %edx - xorl %eax, %eax - subl %ebx, %eax /* %eax = 4GIB - size to cache */ - orl $(MTRR_PHYS_MASK_VALID), %eax - wrmsr - incl %ecx /* Move index to next MTRR_PHYS_BASE */ - -cond_allocate_var_mtrrs: - - /* Check if we still need to cache something */ - movd %xmm1, %ebx - andl %ebx, %ebx - - jnz body_allocate_var_mtrrs + /* + * Important note: The MTRRs must cache less than a page (4 KiB) + * of unused memory after the BIOS ACM. Failure to do so will + * result in a TXT reset with Class Code 5, Major Error Code 2. + * + * The caller must have checked that there are enough variable + * MTRRs to cache the ACM size prior to invoking this routine. + */ + SET_UP_MTRRS_FOR_BIOS_ACM /* * Now that the variable MTRRs have been set up, enable them. diff --git a/src/security/intel/txt/getsec_mtrr_setup.inc b/src/security/intel/txt/getsec_mtrr_setup.inc new file mode 100644 index 0000000000..15e8cc17ad --- /dev/null +++ b/src/security/intel/txt/getsec_mtrr_setup.inc @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) + +/* + * Configure the MTRRs to cache the BIOS ACM. No general-purpose + * registers are preserved. Inputs are taken from SSE registers: + * + * %xmm0: BIOS ACM base + * %xmm1: BIOS ACM size + * + * These two SSE registers are not preserved, but the others are. + */ +.macro SET_UP_MTRRS_FOR_BIOS_ACM + + /* Get the number of variable MTRRs */ + movl $(MTRR_CAP_MSR), %ecx + rdmsr + andl $(0xff), %eax + + /* Initialize ECX */ + movl $(MTRR_PHYS_BASE(0)), %ecx + + jmp cond_allocate_var_mtrrs + +body_allocate_var_mtrrs: + + /* Program MTRR base */ + xorl %edx, %edx + movd %xmm0, %eax + orl $(MTRR_TYPE_WRBACK), %eax + wrmsr + incl %ecx /* Move index to MTRR_PHYS_MASK */ + + /* Temporarily transfer MSR index to EDX so that CL can be used */ + movl %ecx, %edx + + /* Determine next size to cache */ + bsr %ebx, %ecx + movl $(1), %ebx + shl %cl, %ebx /* Can only use CL here */ + + /* Restore ECX */ + movl %edx, %ecx + + /* Update saved base address */ + addl %ebx, %eax + movd %eax, %xmm0 + + /* Update saved remaining size */ + movd %xmm1, %eax + subl %ebx, %eax + movd %eax, %xmm1 + + /* Program MTRR mask */ + movl MTRR_HIGH_MASK, %edx + xorl %eax, %eax + subl %ebx, %eax /* %eax = 4GIB - size to cache */ + orl $(MTRR_PHYS_MASK_VALID), %eax + wrmsr + incl %ecx /* Move index to next MTRR_PHYS_BASE */ + +cond_allocate_var_mtrrs: + + /* Check if we still need to cache something */ + movd %xmm1, %ebx + andl %ebx, %ebx + + jnz body_allocate_var_mtrrs + +.endm From 8972750b266f97975949821f1075a1104dd2f915 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 12 Oct 2020 11:26:14 -0600 Subject: [PATCH 202/354] src/soc/intel/xeon_sp/skx: Update get_iiostack_info() Add Pci64BitResourceAllocation return value to get_iiostack_info(). This matches cpx function and is used in future de-duplication. Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307 Reviewed-by: Stefan Reinauer Reviewed-by: Jay Talbott Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/skx/include/soc/soc_util.h | 2 +- src/soc/intel/xeon_sp/skx/soc_util.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index d641f76a3d..76f7c8be4b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -11,7 +11,7 @@ struct iiostack_resource { STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -void get_iiostack_info(struct iiostack_resource *info); +uint8_t get_iiostack_info(struct iiostack_resource *info); void xeonsp_init_cpu_config(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 8b29e7f848..3b37ca3c48 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -288,7 +288,7 @@ int get_platform_thread_count(void) return get_cpu_count() * get_threads_per_package(); } -void get_iiostack_info(struct iiostack_resource *info) +uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -310,6 +310,8 @@ void get_iiostack_info(struct iiostack_resource *info) memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } + + return hob->PlatformData.Pci64BitResourceAllocation; } #if ENV_RAMSTAGE From 8066fda9ed53da095b17188e3b96265810534985 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 19 Oct 2020 15:52:52 -0600 Subject: [PATCH 203/354] soc/intel/xeon_sp: Move ACPI prototypes from chip.h Prepare for common ACPI. Move the soc ACPI function prototypes from cpx and skx chip.h to include/soc/acpi.h. Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/cpx/acpi.c | 2 -- src/soc/intel/xeon_sp/cpx/chip.h | 6 ------ src/soc/intel/xeon_sp/cpx/soc_acpi.c | 2 -- src/soc/intel/xeon_sp/include/soc/acpi.h | 5 +++++ src/soc/intel/xeon_sp/skx/acpi.c | 2 -- src/soc/intel/xeon_sp/skx/chip.h | 4 ---- src/soc/intel/xeon_sp/skx/soc_acpi.c | 2 -- 7 files changed, 5 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 8d3e86a10b..658c951648 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -23,8 +23,6 @@ #include #include -#include "chip.h" - static int acpi_sci_irq(void) { int sci_irq = 9; diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e7c146c291..434b343bb2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -99,10 +99,4 @@ struct soc_intel_xeon_sp_cpx_config { typedef struct soc_intel_xeon_sp_cpx_config config_t; -/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ -void cpx_generate_p_state_entries(int core, int cores_per_package); -int calculate_power(int tdp, int p1_ratio, int ratio); -void uncore_inject_dsdt(void); -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); - #endif diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index fab221166c..cf84334449 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -17,8 +17,6 @@ #include #include -#include "chip.h" - /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 6a76ef222b..b46914dbde 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -22,4 +22,9 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, void motherboard_fill_fadt(acpi_fadt_t *fadt); +void cpx_generate_p_state_entries(int core, int cores_per_package); +int calculate_power(int tdp, int p1_ratio, int ratio); +void uncore_inject_dsdt(void); +unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); + #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index cbafbdb07b..c446a51f8c 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -15,8 +15,6 @@ #include #include -#include "chip.h" - acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = 0; diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index adb70e58d0..08608997b3 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -76,8 +76,4 @@ struct soc_intel_xeon_sp_skx_config { typedef struct soc_intel_xeon_sp_skx_config config_t; -/* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ -void uncore_inject_dsdt(void); -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); - #endif diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b6b39f2989..afbcf840bd 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -18,8 +18,6 @@ #include #include -#include "chip.h" - /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) { From 521a03f30331ff89f3ac8d94cad03b8443ebf4ff Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 19 Oct 2020 13:46:59 -0600 Subject: [PATCH 204/354] soc/intel/xeon_sp: Move uncore_inject_dsdt() call Prepare for common ACPI code. Move uncore_inject_dsdt() to the uncore device acpi_inject_dsdt call. Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/cpx/acpi.c | 3 --- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 6 +----- src/soc/intel/xeon_sp/include/soc/acpi.h | 2 +- src/soc/intel/xeon_sp/skx/acpi.c | 3 --- src/soc/intel/xeon_sp/skx/soc_acpi.c | 6 +----- src/soc/intel/xeon_sp/uncore.c | 4 ++++ 6 files changed, 7 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 658c951648..5a908dabbf 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -214,9 +214,6 @@ void southbridge_inject_dsdt(const struct device *device) acpigen_write_name_dword("NVSA", (uint32_t)gnvs); acpigen_pop_len(); } - - /* Add IIOStack ACPI Resource Templates */ - uncore_inject_dsdt(); } int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index cf84334449..19d196d351 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -57,11 +57,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_WAKE); } -/* - * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() - * with a call from the common/function or find another way to call this at the correct place - */ -void uncore_inject_dsdt(void) +void uncore_inject_dsdt(const struct device *device) { struct iiostack_resource stack_info = {0}; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index b46914dbde..75859e8353 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -24,7 +24,7 @@ void motherboard_fill_fadt(acpi_fadt_t *fadt); void cpx_generate_p_state_entries(int core, int cores_per_package); int calculate_power(int tdp, int p1_ratio, int ratio); -void uncore_inject_dsdt(void); +void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index c446a51f8c..f0b7df9c38 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -247,9 +247,6 @@ void southbridge_inject_dsdt(const struct device *device) acpigen_write_name_dword("NVSA", (uint32_t)gnvs); acpigen_pop_len(); } - - // Add IIOStack ACPI Resource Templates - uncore_inject_dsdt(); } diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index afbcf840bd..56ed0ce17b 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -55,11 +55,7 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } -/* - * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() - * with a call from the common/function or find another way to call this at the correct place - */ -void uncore_inject_dsdt(void) +void uncore_inject_dsdt(const struct device *device) { size_t hob_size; const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a549acb0f6..332b9a44a3 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -274,6 +275,9 @@ static struct device_operations mmapvtd_ops = { .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_inject_dsdt = uncore_inject_dsdt, +#endif }; static const unsigned short mmapvtd_ids[] = { From 3fc04842cbe22fa29ea416fe746a8ee986605118 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 19 Oct 2020 16:08:27 -0600 Subject: [PATCH 205/354] soc/intel/xeon_sp/skx: Move skx specific FADT setting Prepare for common ACPI. Move the skx specific FADT settings from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt() to match common/block/acpi.c. Change-Id: I04873d13d822de514acbb58501171285bd5b020e Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/skx/acpi.c | 73 +++++++++------------------- src/soc/intel/xeon_sp/skx/soc_acpi.c | 42 ++++++++++++++++ 2 files changed, 64 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index f0b7df9c38..c14e7c8aea 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -137,82 +137,53 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->sci_int = acpi_sci_irq(); - /* TODO: enabled SMM mode switch when SMM handlers are set up. */ - if (0 && permanent_smi_handler()) { + if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } - /* Power Control */ fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); - /* Control Registers - Length */ fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; - fadt->duty_width = 0; - /* RTC Registers */ - fadt->day_alrm = 0x0d; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; - /* PM1 Status & PM1 Enable */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - /* PM1 Control Registers */ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; + fadt->x_gpe0_blk.addrh = 0; } unsigned long southbridge_write_acpi_tables(const struct device *device, diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 56ed0ce17b..7462d72b7a 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -55,6 +55,48 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SEALED_CASE); + fadt->flags |= ACPI_FADT_SLEEP_TYPE; + + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + +} + void uncore_inject_dsdt(const struct device *device) { size_t hob_size; From 7a25fb8e69d4fa18b6e4b8ec1ed0b54f37151577 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 19 Oct 2020 16:32:05 -0600 Subject: [PATCH 206/354] soc/intel/xeon_sp: Rename cpx_generate_p_state_entries() Prepare for common ACPI. Rename cpx_generated_p_state_entries() to the common soc_power_states_generation() function. Add empty soc_power_states_generation() to skx. Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/xeon_sp/cpx/acpi.c | 5 +++-- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 4 ++-- src/soc/intel/xeon_sp/include/soc/acpi.h | 1 - src/soc/intel/xeon_sp/skx/soc_acpi.c | 4 ++++ 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 5a908dabbf..3066dda22e 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -261,8 +261,9 @@ void generate_cpu_entries(const struct device *device) /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - /* Generate P-state tables */ - cpx_generate_p_state_entries(core_id, threads_per_package); + /* Soc specific power states generation */ + soc_power_states_generation(core_id, threads_per_package); + acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 19d196d351..88205173b6 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -123,8 +123,8 @@ void uncore_inject_dsdt(const struct device *device) acpigen_pop_len(); } -/* To be renamed soc_power_states_generation() */ -void cpx_generate_p_state_entries(int core, int cores_per_package) +/* TODO: See if we can use the common generate_p_state_entries */ +void soc_power_states_generation(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; int coord_type, power_max, power_unit, num_entries; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 75859e8353..61639d2a84 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -22,7 +22,6 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, void motherboard_fill_fadt(acpi_fadt_t *fadt); -void cpx_generate_p_state_entries(int core, int cores_per_package); int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 7462d72b7a..df2550c54a 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -171,6 +171,10 @@ void uncore_inject_dsdt(const struct device *device) acpigen_pop_len(); } +void soc_power_states_generation(int core, int cores_per_package) +{ +} + unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) { struct device *cpu; From 9190345bf071261a0764c9cfbe1472f974e2bd19 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 22 Oct 2020 23:06:04 +0200 Subject: [PATCH 207/354] soc/intel/xeon_sp/skx: Add missing includes Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed some indirect header inclusions, which resulted in a build failure. Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi Reviewed-by: Tim Wawrzynczak Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/skx/chip.c | 1 + src/soc/intel/xeon_sp/skx/cpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb9f3..4324660f47 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include struct pci_resource { struct device *dev; diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index ea9f531886..bf712c3618 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "chip.h" From 3398f3152cf005d1e8219feacac1e1ec4fe50095 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 16 Jun 2020 11:54:38 +0800 Subject: [PATCH 208/354] soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: CK Hu Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/Makefile.inc | 1 + src/soc/mediatek/mt8192/mmu_operations.c | 30 ++++++++++++++++++++++++ src/soc/mediatek/mt8192/soc.c | 2 ++ 3 files changed, 33 insertions(+) create mode 100644 src/soc/mediatek/mt8192/mmu_operations.c diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index fb3b11de8c..8b2831cc6b 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c new file mode 100644 index 0000000000..fb3620eb82 --- /dev/null +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 9850fa6fbe..6978406cac 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -2,6 +2,7 @@ #include #include +#include #include static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { From 3827f56fe1f97c4dc19af94782ed9cce89cec723 Mon Sep 17 00:00:00 2001 From: Xi Chen Date: Tue, 20 Oct 2020 17:55:14 +0800 Subject: [PATCH 209/354] soc/mediatek/mt8192: add dram log prefix 1 Add dram log prefix: [MEM] 2 Print error code when memtest fails. Signed-off-by: Xi Chen Change-Id: I6c53c9cecf5996227a3e343fc703b9880d9afeac Reviewed-on: https://review.coreboot.org/c/coreboot/+/46585 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/memory.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index b5363b0712..5820fbf294 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -15,14 +15,14 @@ static int mt_mem_test(const struct dramc_data *dparam) const struct ddr_base_info *ddr_info = &dparam->ddr_info; for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { - int i = complex_mem_test(addr, 0x2000); + int result = complex_mem_test(addr, 0x2000); - printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s\n", - (i == 0) ? "pass" : "fail"); - - if (i != 0) { - printk(BIOS_ERR, "DRAM memory test failed\n"); + if (result != 0) { + printk(BIOS_ERR, + "[MEM] complex R/W mem test failed: %d\n", result); return -1; + } else { + printk(BIOS_DEBUG, "[MEM] complex R/W mem test passed\n"); } addr += ddr_info->rank_size[rank]; From 0263e0ff65d50a616e1ae04ab0837c0d90118d19 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 21 Oct 2020 22:46:14 -0700 Subject: [PATCH 210/354] sc7180: enable RECOVERY_MRC_CACHE Enable caching of memory training data for recovery as well as normal mode because memory training is taking too long in recovery as well. This required creating a space in the fmap for RECOVERY_MRC_CACHE. BUG=b:150502246 BRANCH=None TEST=Run power_state:rec twice on lazor. Ensure that on first boot, memory training occurs and on second boot, memory training is skipped. Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/trogdor/chromeos.fmd | 5 ++++- src/soc/qualcomm/common/qclib.c | 26 +++++------------------ src/soc/qualcomm/sc7180/Kconfig | 1 + 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index d5324eee49..f6960761ef 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -14,7 +14,10 @@ FLASH@0x0 8M { RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_MRC_CACHE(PRESERVE) 8K + UNIFIED_MRC_CACHE(PRESERVE) 16K { + RECOVERY_MRC_CACHE 8K + RW_MRC_CACHE 8K + } RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d4796a2e7c..93588904b5 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -74,14 +74,6 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te) } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { - /* - * Don't store training data if we're in recovery mode - * because we always want to retrain due to - * possibility of RW training data possibly being - * updated to a different format. - */ - if (vboot_recovery_mode_enabled()) - return; assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION, (const void *)te->blob_address, te->size)); @@ -138,20 +130,12 @@ void qclib_load_and_run(void) /* output area, QCLib fills in DDR details */ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); - /* - * We never want to use training data when booting into - * recovery mode. - */ - if (vboot_recovery_mode_enabled()) { + /* Attempt to load DDR Training Blob */ + data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, + _ddr_training, REGION_SIZE(ddr_training)); + if (data_size < 0) { + printk(BIOS_ERR, "Unable to load previous training data.\n"); memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } else { - /* Attempt to load DDR Training Blob */ - data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, - _ddr_training, REGION_SIZE(ddr_training)); - if (data_size < 0) { - printk(BIOS_ERR, "Unable to load previous training data.\n"); - memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } } qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index c37aff9db3..4cd1c41cac 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -19,6 +19,7 @@ config SOC_QUALCOMM_SC7180 select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select CACHE_MRC_SETTINGS + select HAS_RECOVERY_MRC_CACHE select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 From e3fd00f9e8a65ddb9c54622fd095c252c5c36cf8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 13:43:07 +0200 Subject: [PATCH 211/354] soc/intel/broadwell: Guard MCHBAR macro parameters Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46336 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/include/soc/systemagent.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index c2c5cc8ada..f81d5a00b2 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -80,9 +80,9 @@ /* MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x)) +#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR_PEI_VERSION 0x5034 #define BIOS_RESET_CPL 0x5da8 From 488bbe2c880b883461cc551d45de4d6541b28400 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 31 Aug 2020 18:07:02 +0800 Subject: [PATCH 212/354] mb/google/dedede/var/drawcia: Add MIPI camera support To support mipi WFC. 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 in devicetree BUG=b:163879470, b:171258890, b:170936728, b:167938257 TEST=Build and boot to OS. Capture frames using camera app. Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/44939 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Henry Sun Reviewed-by: Andy Yeh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig.name | 4 + .../dedede/variants/drawcia/overridetree.cb | 87 +++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 689df68846..31495a1552 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -21,6 +21,8 @@ config BOARD_GOOGLE_DRAWCIA select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" @@ -28,6 +30,8 @@ config BOARD_GOOGLE_DRAWCIA_LEGACY select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_MADOO bool "-> Madoo" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ac7a97e75a..594212190a 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -65,6 +65,21 @@ chip soc/intel/jasperlake register "tcc_offset" = "20" # TCC of 85C device domain 0 on + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{1,4}" + register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end + device pci 04.0 on chip drivers/intel/dptf # Default DPTF Policy for all drawcia boards if not overridden @@ -198,6 +213,78 @@ chip soc/intel/jasperlake device i2c 15 on end end end # I2C 2 + device pci 15.3 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + + register "nvm_size" = "0x0400" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x08" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end # I2C 3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" From eef5cadca8b656ddd745f74557c1c7b62a144688 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 19 Oct 2020 22:08:25 -0600 Subject: [PATCH 213/354] mb/google/dedede: Update the flash ROM layout for RW regions RW_LEGACY region needs to be 1 MiB to accommodate any alternate firmware. Hence update the flash ROM layout as below: * Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to RW_LEGACY region so that it grows to 1 MiB. * Remove VBLOCK_DEV region which is not used. * Re-size the ELOG region to 4 KiB since that is the maximum size of the ELOG mirror buffer. * Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that size is used in those regions. * Resize SHARED_DATA region to 4 KiB since no more than that size is used in that region. * Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB. BUG=b:167943992, b:167498108 TEST=Build and boot to OS in Drawlat. Ensure that the firmware test setup and flash map test are successful. Ensure that the event logs are synced properly between reboots. Ensure that the suspend/resume sequence is working fine. Ensure that the ChromeOS firmware update completes successfully for the boot image with updated flash map and the system boots fine after the update. Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569 Reviewed-by: Paul Menzel Reviewed-by: Maulik V Vaghela Reviewed-by: Julius Werner Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/dedede/chromeos-dedede-16MiB.fmd | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 09b2abc208..0e21c4c91b 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -4,29 +4,28 @@ FLASH@0xff000000 0x1000000 { SI_ME@0x1000 0x380000 } SI_BIOS@0x381000 0xc7f000 { - RW_LEGACY(CBFS)@0x0 0x1000 - RW_SECTION_A@0x1000 0x420000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x40ffc0 - RW_FWID_A@0x41ffc0 0x40 + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x3a27c0 + RW_FWID_A@0x3a47c0 0x40 } - RW_SECTION_B@0x421000 0x420000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x40ffc0 - RW_FWID_B@0x41ffc0 0x40 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x3a27c0 + RW_FWID_B@0x3a47c0 0x40 } - RW_MISC@0x841000 0x3e000 { + RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x3000 - RW_SHARED@0x33000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x37000 0x2000 - RW_NVRAM(PRESERVE)@0x39000 0x5000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } # Make WP_RO region align with SPI vendor # memory protected range specification. From a10229269a2800403df589e2f7840e52eee589a4 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 20 Oct 2020 11:12:47 -0600 Subject: [PATCH 214/354] mb/google/zork/woomax: Adjust disconnect threshold The disconnect voltage needs to be adjusted up because the HS DC voltage level is 0xF. BUG=b:170879690 TEST=Servo_v4 USB hub functions BRANCH=zork Change-Id: If8662015a45c57e457b4593e55af888084842f58 Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/zork/variants/woomax/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 19d66fcfbd..e9d66f9a77 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -24,7 +24,7 @@ chip soc/amd/picasso # End : OPN Performance Configuration #USB 2.0 strength register "usb_2_port_tune_params[0]" = "{ - .com_pds_tune = 0x03, + .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, @@ -36,7 +36,7 @@ chip soc/amd/picasso }" register "usb_2_port_tune_params[3]" = "{ - .com_pds_tune = 0x03, + .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, From eef615c0f564185380fd93e29a191f926e813d03 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 22 Oct 2020 20:09:12 +0800 Subject: [PATCH 215/354] mb/google/zork: update telemetry settings for morphius Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD Slope: 62852 -> 62641 SOC Slope: 28022 -> 28333 BUG=b:170531252 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Marshall Dawson --- src/mainboard/google/zork/variants/morphius/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 66b371be04..e04a62e654 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -16,9 +16,9 @@ chip soc/amd/picasso register "sustained_power_limit" = "12000" #mw register "thermctl_limit" = "100" #degrees C - register "telemetry_vddcr_vdd_slope" = "62852" #mA + register "telemetry_vddcr_vdd_slope" = "62641" #mA register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28022" #mA + register "telemetry_vddcr_soc_slope" = "28333" #mA register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode From 90f71918fba37739e0a4e46f8983a62a53a3eb12 Mon Sep 17 00:00:00 2001 From: Jason Glenesk Date: Tue, 13 Oct 2020 04:35:09 -0700 Subject: [PATCH 216/354] vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h Remove all typedefs and cleanup references to all structs and enums. BUG=b:159061802 TEST=Boot morphius to shell. Signed-off-by: Jason Glenesk Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/psp_verstage/fch.c | 4 +- src/soc/amd/picasso/psp_verstage/svc.c | 20 ++-- .../amd/picasso/psp_verstage/vboot_crypto.c | 4 +- .../include/bl_uapp/bl_syscall_public.h | 97 ++++++++----------- 4 files changed, 57 insertions(+), 68 deletions(-) diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 89e7014550..7d0b856545 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -70,7 +70,7 @@ static void aoac_set_bar(void *bar) static struct { const char *name; struct { - FCH_IO_DEVICE device; + enum fch_io_device device; uint32_t arg0; } args; void (*set_bar)(void *bar); @@ -90,7 +90,7 @@ static struct { uintptr_t *map_spi_rom(void) { uintptr_t *addr = NULL; - struct SPIROM_INFO spi = {0}; + struct spirom_info spi = {0}; if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index b847276d84..acc9c70318 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -53,14 +53,14 @@ void svc_delay_in_usec(uint32_t delay) SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); } -uint32_t svc_get_spi_rom_info(SPIROM_INFO *spi_rom_info) +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) { uint32_t retval = 0; SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); return retval; } -uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_map_fch_dev(enum fch_io_device io_device, uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) { uint32_t retval = 0; @@ -70,7 +70,7 @@ uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, return retval; } -uint32_t svc_unmap_fch_dev(FCH_IO_DEVICE io_device, void *io_device_axi_addr) +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) { uint32_t retval = 0; assert(io_device < FCH_IO_DEVICE_END); @@ -96,7 +96,7 @@ uint32_t svc_unmap_spi_rom(void *spi_rom_addr) } uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset, DIR_OFFSET_OPERATION operation) + uint32_t *bios_dir_offset, enum dir_offset_operation operation) { uint32_t retval = 0; assert(operation < DIR_OFFSET_OPERATION_MAX); @@ -105,7 +105,7 @@ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, return retval; } -uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, +uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size) { uint32_t retval = 0; @@ -114,7 +114,7 @@ uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, return retval; } -uint32_t svc_read_timer_val(PSP_TIMER_TYPE type, uint64_t *counter_value) +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) { unsigned int retval = 0; assert(type < PSP_TIMER_TYPE_MAX); @@ -122,7 +122,7 @@ uint32_t svc_read_timer_val(PSP_TIMER_TYPE type, uint64_t *counter_value) return retval; } -uint32_t svc_reset_system(RESET_TYPE reset_type) +uint32_t svc_reset_system(enum reset_type reset_type) { unsigned int retval = 0; assert(reset_type < RESET_TYPE_MAX); @@ -144,21 +144,21 @@ uint32_t svc_get_max_workbuf_size(uint32_t *size) return retval; } -uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode) +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) { uint32_t retval = 0; SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval); return retval; } -uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *rsa_params) +uint32_t svc_rsa_pkcs_verify(const struct rsapkcs_verify_params *rsa_params) { uint32_t retval = 0; SVC_CALL1(SVC_RSAPKCS_VERIFY, rsa_params, retval); return retval; } -uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param) +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) { uint32_t retval = 0; SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); diff --git a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c index d9364d0ebe..3f7151ac11 100644 --- a/src/soc/amd/picasso/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/picasso/psp_verstage/vboot_crypto.c @@ -11,7 +11,7 @@ #include #include -static struct SHA_GENERIC_DATA_T sha_op; +static struct sha_generic_data sha_op; static uint32_t sha_op_size_remaining; static uint8_t __attribute__((aligned(32))) sha_hash[64]; @@ -113,7 +113,7 @@ vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key, * Since PSP expects everything in LE and *inout is BE array, * we'll use workbuf for temporary buffer for endian conversion. */ - MOD_EXP_PARAMS mod_exp_param; + struct mod_exp_params mod_exp_param; unsigned int key_bytes = key->arrsize * sizeof(uint32_t); uint32_t *sig_swapped = workbuf32; uint32_t *output_buffer = &workbuf32[key->arrsize]; diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 93f987bfaa..c057295185 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -60,8 +60,7 @@ #define PSP_INFO_PRODUCTION_SILICON 0x00000002UL #define PSP_INFO_VALID 0x80000000UL -typedef struct MOD_EXP_PARAMS_T -{ +struct mod_exp_params { char *pExponent; // Exponent address unsigned int ExpSize; // Exponent size in bytes char *pModulus; // Modulus address @@ -69,10 +68,9 @@ typedef struct MOD_EXP_PARAMS_T char *pMessage; // Message address, same size as ModulusSize char *pOutput; // Output address; Must be big enough to hold the // data of ModulusSize -} MOD_EXP_PARAMS; +}; -typedef struct _RSAPSS_VERIFY_PARAMS_T -{ +struct rsapss_verify_params { char *pHash; // Message digest to verify the RSA signature unsigned int HashLen; // hash length in bytes char *pModulus; // Modulus address @@ -80,10 +78,9 @@ typedef struct _RSAPSS_VERIFY_PARAMS_T char *pExponent; // Exponent address unsigned int ExpSize; // Exponent length in bytes char *pSig; // Signature to be verified, same size as ModulusSize -} RSAPSS_VERIFY_PARAMS; +}; -typedef struct RSAPKCS_VERIFY_PARAMS_T -{ +struct rsapkcs_verify_params { char *pHash; // Message digest to verify the RSA signature unsigned int HashLen; // hash length in bytes char *pModulus; // Modulus address @@ -91,19 +88,18 @@ typedef struct RSAPKCS_VERIFY_PARAMS_T char *pExponent; // Exponent address unsigned int ExpSize; // Exponent length in bytes char *pSig; // Signature to be verified, same size as ModulusSize -} RSAPKCS_VERIFY_PARAMS; +}; -typedef enum _PSP_BOOT_MODE -{ +enum psp_boot_mode { PSP_BOOT_MODE_S0 = 0x0, PSP_BOOT_MODE_S0i3_RESUME = 0x1, PSP_BOOT_MODE_S3_RESUME = 0x2, PSP_BOOT_MODE_S4 = 0x3, PSP_BOOT_MODE_S5_COLD = 0x4, PSP_BOOT_MODE_S5_WARM = 0x5, -} PSP_BOOT_MODE; +}; -typedef enum FCH_IO_DEVICE { +enum fch_io_device { FCH_IO_DEVICE_SPI, FCH_IO_DEVICE_I2C, FCH_IO_DEVICE_GPIO, @@ -114,68 +110,61 @@ typedef enum FCH_IO_DEVICE { FCH_IO_DEVICE_IOPORT, FCH_IO_DEVICE_END, -} FCH_IO_DEVICE; +}; /* Svc_UpdatePspBiosDir can be used to GET or SET the PSP or BIOS directory * offsets. This enum is used to specify whether it is a GET or SET operation. */ -typedef enum DIR_OFFSET_OPERATION_E { +enum dir_offset_operation { DIR_OFFSET_GET = 0x0, DIR_OFFSET_SET, DIR_OFFSET_OPERATION_MAX -} DIR_OFFSET_OPERATION; +}; -typedef enum FCH_I2C_CONTROLLER_ID_E -{ +enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_2 = 2, FCH_I2C_CONTROLLER_ID_3 = 3, FCH_I2C_CONTROLLER_ID_4 = 4, FCH_I2C_CONTROLLER_ID_MAX, -} FCH_I2C_CONTROLLER_ID; +}; -typedef enum UAPP_COPYBUF -{ +enum uapp_copybuf { UAPP_COPYBUF_CHROME_WORKBUF = 0x0, UAPP_COPYBUF_MAX = 0x1, -} UAPP_COPYBUF; +}; -typedef struct SPIROM_INFO -{ +struct spirom_info { void *SpiBiosSysHubBase; void *SpiBiosSmnBase; uint32_t SpiBiosSize; -} SPIROM_INFO; +}; -typedef enum PSP_TIMER_TYPE { +enum psp_timer_type { PSP_TIMER_TYPE_CHRONO = 0, PSP_TIMER_TYPE_RTC = 1, PSP_TIMER_TYPE_MAX = 2, -} PSP_TIMER_TYPE; +}; -typedef enum RESET_TYPE -{ +enum reset_type { RESET_TYPE_COLD = 0, RESET_TYPE_WARM = 1, RESET_TYPE_MAX = 2, -} RESET_TYPE; +}; /* SHA types same as ccp SHA type in crypto.h */ -typedef enum SHA_TYPE -{ +enum sha_type { SHA_TYPE_256, SHA_TYPE_512 -} SHA_TYPE; +}; /* All SHA operation supported */ -typedef enum SHA_OPERATION_MODE -{ +enum sha_operation_mode { SHA_GENERIC -} SHA_OPERATION_MODE; +}; /* SHA Supported Data Structures */ -typedef struct SHA_GENERIC_DATA_T -{ - SHA_TYPE SHAType; +struct sha_generic_data { + enum sha_type SHAType; uint8_t *Data; uint32_t DataLen; uint32_t DataMemType; @@ -185,7 +174,7 @@ typedef struct SHA_GENERIC_DATA_T uint32_t IntermediateMsgLen; uint32_t Init; uint32_t Eom; -} SHA_GENERIC_DATA; +}; /* * Exit to the main Boot Loader. This does not return back to user application. @@ -231,7 +220,7 @@ void svc_debug_print_ex(uint32_t dword0, */ uint32_t svc_wait_10ns_multiple(uint32_t multiple); -/* Description - Returns the current boot mode from the type PSP_BOOT_MODE found in +/* Description - Returns the current boot mode from the enum psp_boot_mode found in * bl_public.h. * * Inputs - boot_mode - Output parameter passed in R0 @@ -261,7 +250,7 @@ void svc_delay_in_usec(uint32_t delay); * * Return value: BL_OK or error code */ -uint32_t svc_get_spi_rom_info(SPIROM_INFO *spi_rom_info); +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info); /* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...) * @@ -273,7 +262,7 @@ uint32_t svc_get_spi_rom_info(SPIROM_INFO *spi_rom_info); * * Return value: BL_OK or error code */ -uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_map_fch_dev(enum fch_io_device io_device, uint32_t arg1, uint32_t arg2, void **io_device_axi_addr); /* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice() @@ -284,7 +273,7 @@ uint32_t svc_map_fch_dev(FCH_IO_DEVICE io_device, * * Return value: BL_OK or error code */ -uint32_t svc_unmap_fch_dev(FCH_IO_DEVICE io_device, +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr); /* Map the SPIROM FLASH device address space @@ -324,7 +313,7 @@ uint32_t svc_unmap_spi_rom(void *spi_rom_addr); * Return value: BL_OK or error code */ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, - uint32_t *bios_dir_offset, DIR_OFFSET_OPERATION operation); + uint32_t *bios_dir_offset, enum dir_offset_operation operation); /* Copies the data that is shared by verstage to the PSP BL owned memory * @@ -333,7 +322,7 @@ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, * address - Address in UAPP controlled/owned memory * size - Total size of memory to copy (max 16Kbytes) */ -uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, +uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size); /* @@ -345,7 +334,7 @@ uint32_t svc_save_uapp_data(UAPP_COPYBUF type, void *address, * counter_value - [out] return the raw counter value read from * RTC or CHRONO_LO/HI counter register */ -uint32_t svc_read_timer_val( PSP_TIMER_TYPE type, uint64_t *counter_value ); +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value ); /* * Reset the system @@ -353,7 +342,7 @@ uint32_t svc_read_timer_val( PSP_TIMER_TYPE type, uint64_t *counter_value ); * Parameters: * reset_type - Cold or Warm reset */ -uint32_t svc_reset_system(RESET_TYPE reset_type); +uint32_t svc_reset_system(enum reset_type reset_type); /* * Write postcode to Port-80 @@ -374,27 +363,27 @@ uint32_t svc_get_max_workbuf_size(uint32_t *size); /* * Generic SHA call for SHA, SHA_OTP, SHA_HMAC */ -uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode); +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode); /* * RSA PSS Verification of signature and data * * Parameters: - * RSAPSS_VERIFY_PARAMS - Pointer to RSA PSS parameters + * rsapss_verify_params - Pointer to RSA PSS parameters * * Return value: BL_OK or error code */ -uint32_t svc_rsa_pss_verify(const RSAPSS_VERIFY_PARAMS *params); +uint32_t svc_rsa_pss_verify(const struct rsapss_verify_params *params); /* * RSA PKCS Verification of signature and data * * Parameters: - * RSAPKCS_VERIFY_PARAMS - Pointer to RSA PKCS parameters + * struct rsapkcs_verify_params - Pointer to RSA PKCS parameters * * Return value: BL_OK or error code */ -uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); +uint32_t svc_rsa_pkcs_verify(const struct rsapkcs_verify_params *params); /* Calculate ModEx * @@ -403,7 +392,7 @@ uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); * * Return value: BL_OK or error code */ -uint32_t svc_modexp(MOD_EXP_PARAMS *mod_exp_param); +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); /* C entry point for the Bootloader Userspace Application */ void Main(void); From 6f44874598feabb77b47ce1e914a462ca567f144 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 14:05:18 +0200 Subject: [PATCH 217/354] soc/intel/broadwell: Drop reg-script from early SA init Haswell does not use reg-script, but does more or less the same thing. Adapt Broadwell to ease the eventual unification with Haswell. Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46339 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../intel/broadwell/romstage/systemagent.c | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 6f6db62525..6bf7ba7a59 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -3,40 +3,40 @@ #include #include #include -#include #include #include #include #include -static const struct reg_script systemagent_early_init_script[] = { - REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1), - REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1), - REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1), +static void broadwell_setup_bars(void) +{ + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + + MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; + MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; /* Set C0000-FFFFF to access RAM on both reads and writes */ - REG_PCI_WRITE8(PAM0, 0x30), - REG_PCI_WRITE8(PAM1, 0x33), - REG_PCI_WRITE8(PAM2, 0x33), - REG_PCI_WRITE8(PAM3, 0x33), - REG_PCI_WRITE8(PAM4, 0x33), - REG_PCI_WRITE8(PAM5, 0x33), - REG_PCI_WRITE8(PAM6, 0x33), - - /* Device enable: IGD and Mini-HD */ - REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN), - - REG_SCRIPT_END -}; + pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); + pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); + pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); +} void systemagent_early_init(void) { const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); - reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script); + broadwell_setup_bars(); + + /* Device enable: IGD and Mini-HD */ + pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); if (vtd_capable) { /* setup BARs: zeroize top 32 bits; set enable bit */ From 2436ac037ba06863c126e4152d9bd3bcde9cab1c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 20:03:49 +0200 Subject: [PATCH 218/354] soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/broadwell/lpc.c | 118 +++++++++++++++++++--------------- 1 file changed, 65 insertions(+), 53 deletions(-) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b3f4fe5b2a..495f1343b7 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -201,59 +201,71 @@ static const struct reg_script pch_misc_init_script[] = { }; /* Magic register settings for power management */ -static const struct reg_script pch_pm_init_script[] = { - REG_PCI_WRITE8(0xa9, 0x46), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101), - REG_PCI_RMW32(0xac, ~0x00200000, 0), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), +static void pch_pm_init_magic(struct device *dev) +{ + pci_write_config8(dev, 0xa9, 0x46); + + RCBA32_AND_OR(0x232c, ~1, 0); + + RCBA32_OR(0x1100, 0x0000c13f); + + RCBA32_AND_OR(0x2320, ~0x60, 0x10); + + RCBA32(0x3314) = 0x00012fff; + + RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400); + + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3368) = 0x00041400; + RCBA32(0x3388) = 0x3f8ddbff; + RCBA32(0x33ac) = 0x00007001; + RCBA32(0x33b0) = 0x00181900; + RCBA32(0x33c0) = 0x00060A00; + RCBA32(0x33d0) = 0x06200840; + RCBA32(0x3a28) = 0x01010101; + RCBA32(0x3a2c) = 0x040c0404; + RCBA32(0x3a9c) = 0x9000000a; + RCBA32(0x2b1c) = 0x03808033; + RCBA32(0x2b34) = 0x80000009; + RCBA32(0x3348) = 0x022ddfff; + RCBA32(0x334c) = 0x00000001; + RCBA32(0x3358) = 0x0001c000; + RCBA32(0x3380) = 0x3f8ddbff; + RCBA32(0x3384) = 0x0001c7e1; + RCBA32(0x338c) = 0x0001c7e1; + RCBA32(0x3398) = 0x0001c000; + RCBA32(0x33a8) = 0x00181900; + RCBA32(0x33dc) = 0x00080000; + RCBA32(0x33e0) = 0x00000001; + RCBA32(0x3a20) = 0x0000040c; + RCBA32(0x3a24) = 0x01010101; + RCBA32(0x3a30) = 0x01010101; + + pci_update_config32(dev, 0xac, ~0x00200000, 0); + + RCBA32_OR(0x0410, 0x00000003); + RCBA32_OR(0x2618, 0x08000000); + RCBA32_OR(0x2300, 0x00000002); + RCBA32_OR(0x2600, 0x00000008); + + RCBA32(0x33b4) = 0x00007001; + RCBA32(0x3350) = 0x022ddfff; + RCBA32(0x3354) = 0x00000001; + /* Power Optimizer */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000), - REG_SCRIPT_END -}; + RCBA32_OR(0x33d4, 0x08000000); + RCBA32_OR(0x33c8, 0x00000080); + + RCBA32(0x2b10) = 0x0000883c; + RCBA32(0x2b14) = 0x1e0a4616; + RCBA32(0x2b24) = 0x40000005; + RCBA32(0x2b20) = 0x0005db01; + RCBA32(0x3a80) = 0x05145005; + RCBA32(0x3a84) = 0x00001005; + + RCBA32_OR(0x33d4, 0x2fff2fb1); + RCBA32_OR(0x33c8, 0x00008000); +} static void pch_enable_mphy(void) { @@ -320,7 +332,7 @@ static void pch_pm_init(struct device *dev) pch_enable_mphy(); - reg_script_run_on_dev(dev, pch_pm_init_script); + pch_pm_init_magic(dev); if (pch_is_wpt()) { RCBA32_OR(0x33e0, (1 << 4) | (1 << 1)); From f2e2b9688e48bef26dcb6a178a01b92073333e4e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 20:19:40 +0200 Subject: [PATCH 219/354] soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46351 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/lpc.c | 75 +++++++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 22 deletions(-) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 495f1343b7..ccd372cbc9 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -172,33 +171,65 @@ static void pch_power_options(struct device *dev) enable_alt_smi(config->alt_gp_smi_en); } -static const struct reg_script pch_misc_init_script[] = { - /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ - REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), - (1 << 3)|(1 << 11)|(1 << 12)), +static void pch_misc_init(struct device *dev) +{ + u8 reg8; + u16 reg16; + u32 reg32; + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + /* Prepare sleep mode */ - REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), + reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 &= ~SLP_TYP; + reg32 |= SCI_EN; + outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + + /* Set up NMI on errors */ + reg8 = inb(0x61); + reg8 &= ~0xf0; /* Higher nibble must be 0 */ + reg8 |= (1 << 2); /* PCI SERR# disable for now */ + outb(reg8, 0x61); + /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), + reg8 = inb(0x70); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + outb(reg8, 0x70); + /* Indicate DRAM init done for MRC */ - REG_PCI_OR8(GEN_PMCON_2, (1 << 7)), + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); + /* Enable BIOS updates outside of SMM */ - REG_PCI_RMW8(0xdc, ~(1 << 5), 0), + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + /* Clear status bits to prevent unexpected wake */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + RCBA32_OR(0x3310, 0x2f); + + RCBA32_AND_OR(0x3f02, ~0xf, 0); + /* Enable PCIe Releaxed Order */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), + RCBA32_OR(0x2314, (1 << 31) | (1 << 7)), + RCBA32_OR(0x1114, (1 << 15) | (1 << 14)), + /* Setup SERIRQ, enable continuous mode */ - REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !CONFIG(SERIRQ_CONTINUOUS_MODE) - REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), -#endif - REG_SCRIPT_END -}; + reg8 = pci_read_config8(dev, SERIRQ_CNTL); + reg8 |= 1 << 7; + + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + reg8 |= 1 << 6; + + pci_write_config8(dev, SERIRQ_CNTL, reg8); +} /* Magic register settings for power management */ static void pch_pm_init_magic(struct device *dev) @@ -427,7 +458,7 @@ static void lpc_init(struct device *dev) /* Legacy initialization */ isa_dma_init(); sb_rtc_init(); - reg_script_run_on_dev(dev, pch_misc_init_script); + pch_misc_init(dev); /* Interrupt configuration */ pch_enable_ioapic(dev); From dd558fd0cf81886fdc1b6f2bb5045031a69f55cd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 20:49:23 +0200 Subject: [PATCH 220/354] soc/intel/broadwell: Use common early SMBus code Disabling interrupts and clearing errors was being done twice, once in the `smbus_enable_iobar` reg-script, and another in `enable_smbus`. Change-Id: I58558996bd693b302764965a5bed8b96db363833 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/romstage/Makefile.inc | 1 - src/soc/intel/broadwell/romstage/smbus.c | 35 ------------------- 3 files changed, 1 insertion(+), 36 deletions(-) delete mode 100644 src/soc/intel/broadwell/romstage/smbus.c diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 0ea5dbd065..35129af8b7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index a53cd95cd5..edfec30fdc 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -5,6 +5,5 @@ romstage-y += power_state.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-y += smbus.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c deleted file mode 100644 index a000255ca9..0000000000 --- a/src/soc/intel/broadwell/romstage/smbus.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -uintptr_t smbus_base(void) -{ - return SMBUS_BASE_ADDRESS; -} - -int smbus_enable_iobar(uintptr_t base) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); - return 0; -} From ac0281447824adbac93a1d0c66e565029797d44d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:11:43 +0200 Subject: [PATCH 221/354] soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46356 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Nico Huber --- src/soc/intel/broadwell/memmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index fb9a834f6c..e4c787a016 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -35,8 +35,8 @@ void *cbmem_top_chipset(void) void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); - uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG); + uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM); tseg = ALIGN_DOWN(tseg, 1 * MiB); bgsm = ALIGN_DOWN(bgsm, 1 * MiB); From 6fe7986daf7d7915f27b2e30aa120fce7d834c6e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:39:13 +0200 Subject: [PATCH 222/354] nb/intel/haswell: Drop unnecessary register read Reading MAD_CHNL has no effect, so there's no need to read it here. Change-Id: I8d2aa4787de7f54f49d161f61c9c0abaa811cb83 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46361 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/raminit.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00ff16..aaeaadf9ae 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -227,8 +227,6 @@ void setup_sdram_meminfo(struct pei_data *pei_data) memset(mem_info, 0, sizeof(struct memory_info)); - /* FIXME: Do we need to read MCHBAR32(MAD_CHNL) ? (Answer: Nope) */ - MCHBAR32(MAD_CHNL); addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); From 6791ad221be29d079eeb484edd01089e19f16026 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:44:08 +0200 Subject: [PATCH 223/354] nb/intel/haswell: Make MAD_DIMM_* registers indexed This allows using the macro in a loop, for instance. Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/raminit.c | 8 ++++---- src/northbridge/intel/haswell/registers/mchbar.h | 4 +--- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index aaeaadf9ae..7fd6b3f83e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -65,8 +65,8 @@ static void report_memory_config(void) int i; addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -227,8 +227,8 @@ void setup_sdram_meminfo(struct pei_data *pei_data) memset(mem_info, 0, sizeof(struct memory_info)); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index d6e59abe02..60e16e0b98 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -5,9 +5,7 @@ /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ +#define MAD_DIMM(ch) (0x5004 + (ch) * 4) #define MC_INIT_STATE_G 0x5030 #define MRC_REVISION 0x5034 /* MRC Revision */ From 0117e4eae3ea8d72c24a013ecd5cf3ff510a258c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:34:27 +0200 Subject: [PATCH 224/354] nb/intel/haswell: Constify pointers to strings Jenkins complains about it. Change-Id: I20abdd01ca2b93e8a4de31664ff48651e7268d25 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46368 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 7fd6b3f83e..fbe4cd5d2c 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -51,7 +51,7 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input, mrc_size); } -static const char *ecc_decoder[] = { +static const char *const ecc_decoder[] = { "inactive", "active on IO", "disabled on IO", From 1ca6b531eef43c675b73ee47a59afd2e28d57d7e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:43:00 +0200 Subject: [PATCH 225/354] nb/intel/haswell: Drop ASM to call into MRC Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.) did it for Sandy Bridge, and this commit does it for Haswell. Tested on Asrock B85M Pro4, still boots with MRC. Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46370 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/raminit.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index fbe4cd5d2c..b23f07252e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -108,7 +108,8 @@ static void report_memory_config(void) */ void sdram_initialize(struct pei_data *pei_data) { - unsigned long entry; + int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); + uint32_t type = CBFS_TYPE_MRC; struct cbfsf f; @@ -137,11 +138,9 @@ void sdram_initialize(struct pei_data *pei_data) die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); + entry = rdev_mmap_full(&f.data); if (entry) { - int rv; - asm volatile ("call *%%ecx\n\t" - :"=a" (rv) : "c" (entry), "a" (pei_data)); + int rv = entry(pei_data); /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) From 7f454e4cbd7d4442e94641bf4ed01c8668735364 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:49:03 +0200 Subject: [PATCH 226/354] nb/intel/haswell: Correct designation of MRC version Do not use `System Agent version` to refer to the MRC version, which is what the register being printed contains under normal circumstances. Use the code from Broadwell, which also happens to be indented with tabs. Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46371 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/raminit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index b23f07252e..83654fe58f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -164,11 +164,11 @@ void sdram_initialize(struct pei_data *pei_data) die("UEFI PEI System Agent not found.\n"); } - /* For reference, print the System Agent version after executing the UEFI PEI stage */ + /* Print the MRC version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); - printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - (version >> 24) & 0xff, (version >> 16) & 0xff, - (version >> 8) & 0xff, (version >> 0) & 0xff); + printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); } From 9f3bc371029161699d1d249bbb36cb9a73d9fc93 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:57:10 +0200 Subject: [PATCH 227/354] nb/intel/sandybridge: Correct designation of MRC version Do not use `System Agent version` to refer to the MRC version, which is what the register being printed contains under normal circumstances. Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/raminit_mrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 697862f661..444ecf8cc7 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -176,9 +176,9 @@ void sdram_initialize(struct pei_data *pei_data) if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); - /* For reference, print the System Agent version after executing the UEFI PEI stage */ + /* Print the MRC version after executing the UEFI PEI stage */ u32 version = MCHBAR32(MRC_REVISION); - printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", + printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, (version >> 0) & 0xff); From 5d92aa5882c13dd11fe6fa155d2dea3371856871 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 14 Oct 2020 00:02:37 +0200 Subject: [PATCH 228/354] haswell/broadwell: Fix typos of `BCLK` Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Felix Singer --- src/cpu/intel/haswell/haswell_init.c | 8 ++++---- src/soc/intel/broadwell/cpu.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index ac5dec6277..e03d30fba0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,8 +207,8 @@ int haswell_is_ult(void) return ult; } -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +247,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -259,7 +259,7 @@ static void calibrate_24mhz_bclk(void) return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02bba..179cd43e3a 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include #include -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -77,7 +77,7 @@ static void calibrate_24mhz_bclk(void) return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } From 8cb8374e3c8b3236527796df210ac3d6bbaf3065 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 18:28:29 +0200 Subject: [PATCH 229/354] sb/intel/lynxpoint: Drop space after casts Casts can be considered unary operators, so drop the space. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46528 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Felix Singer --- src/southbridge/intel/lynxpoint/acpi.c | 6 +++--- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- src/southbridge/intel/lynxpoint/sata.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b378..ce1b109342 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -14,7 +14,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); /* fill out header fields */ memcpy(header->signature, "HPET", 4); @@ -37,7 +37,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) hpet->min_tick = 0x0080; header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); + acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) @@ -66,7 +66,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) memcpy(&ssdt->asl_compiler_id, ASLC, 4); ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 956d1d24de..6a5dd40644 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -108,7 +108,7 @@ int early_pch_init(void) RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); /* Mainboard RCBA settings */ mainboard_config_rcba(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fad83b1612..a161087302 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -715,7 +715,7 @@ void southbridge_inject_dsdt(const struct device *dev) /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)gnvs); acpigen_pop_len(); } } @@ -748,7 +748,7 @@ static unsigned long southbridge_write_acpi_tables(const struct device *device, */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; + hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = acpi_align_current(current); acpi_create_intel_hpet(hpet); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 57824dfe90..308d3c32ce 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -149,8 +149,8 @@ static void sata_init(struct device *dev) write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x03, config->sata_port_map); - (void) read32(abar + 0x03); /* Read back 1 */ - (void) read32(abar + 0x03); /* Read back 2 */ + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x09); /* Enable DEVSLP */ From a0cb713ce2caa065ae9d2de71f02d4cb2fd4914d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 17:40:05 +0200 Subject: [PATCH 230/354] soc/intel/broadwell: Revise SA lockdown sequence The MC_LOCK register was written twice and SA PM no longer has a lock bit. Update the sequence as per the Broadwell BIOS Specification, but keep the registers sorted by type. Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46324 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/finalize.c | 31 +++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 300301bbf9..ce8ab37217 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -13,6 +13,15 @@ #include #include +/* + * 16.6 System Agent Configuration Locking + * "5th Generation Intel Core Processor Family BIOS Specification" + * Document Number 535094 + * Revision 2.2.0, August 2014 + * + * To ease reading, first lock PCI registers, then MCHBAR registers. + * Write the MC Lock register first, since more than one bit gets set. + */ const struct reg_script system_agent_finalize_script[] = { REG_PCI_OR16(0x50, 1 << 0), /* GGC */ REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ @@ -25,17 +34,15 @@ const struct reg_script system_agent_finalize_script[] = { REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), /* DDR PTM */ REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), - REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ + REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ REG_SCRIPT_END }; @@ -76,16 +83,18 @@ static void broadwell_finalize(void *unused) reg_script_run_on_dev(sa_dev, system_agent_finalize_script); + /* Read+Write the following registers */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); + spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); - /* Read+Write the following registers */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + /* Read+Write the following register */ RCBA32(0x21a4) = RCBA32(0x21a4); /* Indicate finalize step with post code */ From 82654b3fe64e46be31cec206798c80a7616e9ee9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:45:45 +0200 Subject: [PATCH 231/354] nb/intel/haswell/raminit.c: Clean up local variables Remove unnecessary arrays, use unsigned types for non-negative values and constify where possible. Also define NUM_CHANNELS and NUM_SLOTS. Change-Id: Ie4eb79d9c48194538c0ee41dca48ea32798ad8c6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46363 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/raminit.c | 25 +++++++------------ .../intel/haswell/registers/mchbar.h | 4 +++ 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 83654fe58f..63d70f792f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -61,12 +61,9 @@ static const char *const ecc_decoder[] = { /* Print out the memory controller configuration, as per the values in its registers. */ static void report_memory_config(void) { - u32 addr_decoder_common, addr_decode_chan[2]; int i; - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_chan[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_chan[1] = MCHBAR32(MAD_DIMM(1)); + const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -76,8 +73,8 @@ static void report_memory_config(void) (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_chan); i++) { - u32 ch_conf = addr_decode_chan[i]; + for (i = 0; i < NUM_CHANNELS; i++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); @@ -214,10 +211,9 @@ static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) void setup_sdram_meminfo(struct pei_data *pei_data) { - u32 addr_decode_ch[2]; struct memory_info *mem_info; struct dimm_info *dimm; - int ddr_frequency, dimm_size, ch, d_num; + int ch, d_num; int dimm_cnt = 0; mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); @@ -226,16 +222,13 @@ void setup_sdram_meminfo(struct pei_data *pei_data) memset(mem_info, 0, sizeof(struct memory_info)); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); + const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; - ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; - - for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { - u32 ch_conf = addr_decode_ch[ch]; + for (ch = 0; ch < NUM_CHANNELS; ch++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(ch)); /* DIMMs A/B */ - for (d_num = 0; d_num < 2; d_num++) { - dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; + for (d_num = 0; d_num < NUM_SLOTS; d_num++) { + const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; if (dimm_size) { dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 60e16e0b98..96d08bfc22 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -3,6 +3,10 @@ #ifndef __HASWELL_REGISTERS_MCHBAR_H__ #define __HASWELL_REGISTERS_MCHBAR_H__ +/* Memory controller characteristics */ +#define NUM_CHANNELS 2 +#define NUM_SLOTS 2 + /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_DIMM(ch) (0x5004 + (ch) * 4) From ffc505b99521054c339eab49ee3d83e8a9418144 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 17 Oct 2020 17:48:56 +0200 Subject: [PATCH 232/354] soc/intel/broadwell: Drop reg-script to finalize SA There's no need to use reg-script to do this. Since Haswell does not use reg-script, drop it here to ease comparisons between both platforms. Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46525 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/finalize.c | 63 +++++++++++++++--------------- 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index ce8ab37217..b795f46ce2 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -22,30 +23,37 @@ * To ease reading, first lock PCI registers, then MCHBAR registers. * Write the MC Lock register first, since more than one bit gets set. */ -const struct reg_script system_agent_finalize_script[] = { - REG_PCI_OR16(0x50, 1 << 0), /* GGC */ - REG_PCI_OR32(0x5c, 1 << 0), /* DPR */ - REG_PCI_OR32(0x78, 1 << 10), /* ME */ - REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */ - REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */ - REG_PCI_OR32(0xa0, 1 << 0), /* TOM */ - REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */ - REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */ - REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */ - REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */ - REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5), /* DDR PTM */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31), - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */ - REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */ +static void broadwell_systemagent_finalize(void) +{ + struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); - REG_SCRIPT_END -}; + pci_or_config16(host_bridge, 0x50, 1 << 0); /* GGC */ + pci_or_config32(host_bridge, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(host_bridge, 0x78, 1 << 10); /* ME */ + pci_or_config32(host_bridge, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(host_bridge, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(host_bridge, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(host_bridge, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(host_bridge, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(host_bridge, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(host_bridge, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(host_bridge, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32(0x50fc) |= 0x8f; /* MC */ + MCHBAR32(0x5500) |= 1 << 0; /* PAVP */ + MCHBAR32(0x5880) |= 1 << 5; /* DDR PTM */ + MCHBAR32(0x7000) |= 1 << 31; + MCHBAR32(0x77fc) |= 1 << 0; + MCHBAR32(0x7ffc) |= 1 << 0; + MCHBAR32(0x6800) |= 1 << 31; + MCHBAR32(0x6020) |= 1 << 0; /* UMA GFX */ + MCHBAR32(0x63fc) |= 1 << 0; /* VTDTRK */ + + /* Read+write the following */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); +} const struct reg_script pch_finalize_script[] = { #if !CONFIG(EM100PRO_SPI_CONSOLE) @@ -77,16 +85,9 @@ const struct reg_script pch_finalize_script[] = { static void broadwell_finalize(void *unused) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - printk(BIOS_DEBUG, "Finalizing chipset.\n"); - reg_script_run_on_dev(sa_dev, system_agent_finalize_script); - - /* Read+Write the following registers */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + broadwell_systemagent_finalize(); spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); From 67e1d359debb8b6aa6107811d1f4fee5f356708f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 13:47:00 +0200 Subject: [PATCH 233/354] soc/intel/broadwell: Sort SA registers in ascending order Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46337 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../intel/broadwell/include/soc/systemagent.h | 41 +++++++++++-------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index f81d5a00b2..3b56e9d316 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -29,8 +29,6 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ #define DEVEN_D7EN (1 << 14) @@ -45,6 +43,11 @@ #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define PAM0 0x80 #define PAM1 0x81 @@ -60,14 +63,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2) -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ #define REMAPBASE 0x90 /* Remap base. */ #define REMAPLIMIT 0x98 /* Remap limit. */ #define TOM 0xa0 /* Top of DRAM in memory controller space. */ @@ -78,6 +74,13 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */ #define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) @@ -85,20 +88,23 @@ #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 + #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define MCH_PAIR 0x5418 #define GDXCBAR 0x5420 -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 #define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 @@ -108,7 +114,8 @@ #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 -/* Errors are returned back in bits 7:0. */ + +/* Errors are returned back in bits 7:0 */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 @@ -117,8 +124,8 @@ #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_RESET_CPL 0x5da8 /* System Agent identification */ u8 systemagent_revision(void); From 9ab02cb5fc86297bfcd52d266a07c95b8ee3d6e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 13:56:25 +0200 Subject: [PATCH 234/354] soc/intel/broadwell/finalize.c: Use register names Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ida1266f52fcc06577bd876f2cf3e3324ced6ab9d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46338 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/finalize.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index b795f46ce2..af720740af 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -27,17 +27,17 @@ static void broadwell_systemagent_finalize(void) { struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); - pci_or_config16(host_bridge, 0x50, 1 << 0); /* GGC */ - pci_or_config32(host_bridge, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(host_bridge, 0x78, 1 << 10); /* ME */ - pci_or_config32(host_bridge, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(host_bridge, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(host_bridge, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(host_bridge, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(host_bridge, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(host_bridge, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(host_bridge, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(host_bridge, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(host_bridge, GGC, 1 << 0); + pci_or_config32(host_bridge, DPR, 1 << 0); + pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10); + pci_or_config32(host_bridge, REMAPBASE, 1 << 0); + pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0); + pci_or_config32(host_bridge, TOM, 1 << 0); + pci_or_config32(host_bridge, TOUUD, 1 << 0); + pci_or_config32(host_bridge, BDSM, 1 << 0); + pci_or_config32(host_bridge, BGSM, 1 << 0); + pci_or_config32(host_bridge, TSEG, 1 << 0); + pci_or_config32(host_bridge, TOLUD, 1 << 0); MCHBAR32(0x50fc) |= 0x8f; /* MC */ MCHBAR32(0x5500) |= 1 << 0; /* PAVP */ From ec05de6f54d89d4cfa86aea56cabbf52238f36e5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 14:25:57 +0200 Subject: [PATCH 235/354] soc/intel/broadwell: Define RCBA register LCAP This register has a name. Use it. Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46340 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: HAOUAS Elyes --- src/soc/intel/broadwell/finalize.c | 4 ++-- src/soc/intel/broadwell/include/soc/rcba.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index af720740af..4196144369 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -95,8 +95,8 @@ static void broadwell_finalize(void *unused) /* Lock */ RCBA32_OR(0x3a6c, 0x00000001); - /* Read+Write the following register */ - RCBA32(0x21a4) = RCBA32(0x21a4); + /* Read+Write this R/WO register */ + RCBA32(LCAP) = RCBA32(LCAP); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h index 3bacb9d5b6..0c63eb276c 100644 --- a/src/soc/intel/broadwell/include/soc/rcba.h +++ b/src/soc/intel/broadwell/include/soc/rcba.h @@ -48,6 +48,8 @@ #define PIRQG 6 #define PIRQH 7 +#define LCAP 0x21a4 + /* IO Buffer Programming */ #define IOBPIRI 0x2330 #define IOBPD 0x2334 From cc2708797ea0a4b19da4bf4ef49459220088f432 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 20:33:35 +0200 Subject: [PATCH 236/354] soc/intel/broadwell: Drop reg-script usage from bootblock PCH init Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46352 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/bootblock/pch.c | 88 ++++++++++++++----------- 1 file changed, 51 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 27d9a3e8d6..7f6d0d52d9 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -46,49 +45,64 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } -const struct reg_script pch_early_init_script[] = { - /* Setup southbridge BARs */ - REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), - REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), - REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), - REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), - REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), +static void pch_enable_bars(void) +{ + /* Set up southbridge BARs */ + pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); - /* Set COM1/COM2 decode range */ - REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), - /* Enable legacy decode ranges */ - REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | - COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), + pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); - /* Enable IOAPIC */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), - /* Read back for posted write */ - REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), + pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN); - /* Set HPET address and enable it */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), - /* Read back for posted write */ - REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), - /* Enable HPET to start counter */ - REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), + pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1); - /* Disable reset */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), - /* TCO timer halt */ - REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), - - /* Enable upper 128 bytes of CMOS */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), - - /* Disable unused device (always) */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), - - REG_SCRIPT_END -}; + /* Enable GPIO functionality. */ + pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN); +} static void pch_early_lpc(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); + pch_enable_bars(); + + /* Set COM1/COM2 decode range */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_config); + + /* Enable IOAPIC */ + RCBA16(OIC) = 0x0100; + + /* Read back for posted write */ + (void)RCBA16(OIC); + + /* Set HPET address and enable it */ + RCBA32_AND_OR(HPTC, ~3, 1 << 7); + + /* + * Reading the register back guarantees that the write is + * done before we use the configured base address below. + */ + (void)RCBA32(HPTC); + + /* Enable HPET to start counter */ + setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0); + + /* Disable reset */ + RCBA32_OR(GCS, 1 << 5); + + /* TCO timer halt */ + u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); + reg16 |= TCO_TMR_HLT; + outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); + + /* Enable upper 128 bytes of CMOS */ + RCBA32_OR(RC, 1 << 2); + + /* Disable unused device (always) */ + RCBA32_OR(FD, PCH_DISABLE_ALWAYS); } void bootblock_early_southbridge_init(void) From 7fa445e385cae66f8c696fb54cbd38dff49452c8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:14:32 +0200 Subject: [PATCH 237/354] soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c Other Intel northbridges have this function in this file. Change-Id: I9f084e760ec438d662484455212b5c40a8448928 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/memmap.c | 14 ++++++++++++++ src/soc/intel/broadwell/romstage/romstage.c | 13 ------------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index e4c787a016..f7e58af598 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -3,6 +3,7 @@ /* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ +#include #include #include #include @@ -43,3 +44,16 @@ void smm_region(uintptr_t *start, size_t *size) *start = tseg; *size = bgsm - tseg; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, + MTRR_TYPE_WRBACK); +} diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 3b7aa40049..83e5b73836 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,19 +16,6 @@ #include #include -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); -} - /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) { From 0d0f43f9d36f3a942322486b486b98f7ae5cd70d Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 2 Sep 2020 15:37:00 -0700 Subject: [PATCH 238/354] soc/intel/tigerlake: Add Acoustic features Expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRateFor BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.h | 53 ++++++++++++++++++++++++++++ src/soc/intel/tigerlake/fsp_params.c | 8 +++++ 2 files changed, 61 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index bcf71b1e62..fb6cda0919 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -68,6 +68,33 @@ enum lpm_state_mask { | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; +/* + * VR domains. The domains are IA,GT,SA,VLCC and FIVR. + */ +enum vr_domains { + VR_DOMAIN_IA, + VR_DOMAIN_GT, + VR_DOMAIN_SA, + VR_DOMAIN_VLCC, + VR_DOMAIN_FIVR, + VR_DOMAIN_MAX +}; + +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16 +}; + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ @@ -143,6 +170,32 @@ struct soc_intel_tigerlake_config { /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* + * Acoustic Noise Mitigation + * 0 - Disable + * 1 - Enable noise mitigation + */ + uint8_t AcousticNoiseMitigation; + + /* + * Offset 0x054B - Disable Fast Slew Rate for Deep Package + * C States for VR domains. Disable Fast Slew Rate for Deep + * Package C States based on Acoustic Noise Mitigation feature + * enabled. The domains are IA,GT,SA,VLCC and FIVR. + * 0 - False + * 1 - True + */ + uint8_t FastPkgCRampDisable[VR_DOMAIN_MAX]; + + /* + * Offset 0x0550 - Slew Rate configuration for Deep Package + * C States for VR domains. Slew Rate configuration for Deep + * Package C States for VR domains based on Acoustic Noise + * Mitigation feature enabled. The domains are IA,GT,SA,VLCC and FIVR. + * Slew rates are defined as enum slew_rate. + */ + uint8_t SlowSlewRate[VR_DOMAIN_MAX]; + /* SATA related */ uint8_t SataEnable; uint8_t SataMode; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444bbd5..887241b5c2 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -256,6 +256,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } + params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + memcpy(¶ms->SlowSlewRate, &config->SlowSlewRate, + ARRAY_SIZE(config->SlowSlewRate) * sizeof(config->SlowSlewRate[0])); + + memcpy(¶ms->FastPkgCRampDisable, &config->FastPkgCRampDisable, + ARRAY_SIZE(config->FastPkgCRampDisable) * + sizeof(config->FastPkgCRampDisable[0])); + /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; From 84275161a9c7c417c57b5403214d496e17fd66a4 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 2 Sep 2020 15:47:31 -0700 Subject: [PATCH 239/354] mb/google/volteer: Add settings for noise mitgation Enable acoustic noise mitgation for volteer platforms. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Shaunak Saha Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45053 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../google/volteer/variants/delbin/overridetree.cb | 11 +++++++++++ .../google/volteer/variants/volteer/overridetree.cb | 11 +++++++++++ .../google/volteer/variants/volteer2/overridetree.cb | 11 +++++++++++ 3 files changed, 33 insertions(+) diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 21b1f0761e..5ecfccfba0 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,17 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on device ref i2c0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 2c120d59c7..c5b4c72927 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -49,6 +49,17 @@ chip soc/intel/tigerlake register "HybridStorageMode" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on device ref ipu on end device ref i2c0 on diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index d49a52a89b..2db1f087ef 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -7,6 +7,17 @@ chip soc/intel/tigerlake register "HybridStorageMode" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + device domain 0 on device ref dptf on chip drivers/intel/dptf From 7a957543b53c2c55b396fb0a7572a7955832ff56 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:22:01 +0200 Subject: [PATCH 240/354] soc/intel/broadwell/romstage/romstage.c: Clean up includes Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ibbffe152e511065dc265155555c56446fbb70405 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46358 Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/romstage/romstage.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 83e5b73836..2e5db76ce9 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -1,20 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include -#include #include -#include #include -#include #include -#include #include #include #include #include #include -#include +#include +#include /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) From 0a9ac9f4fbb5e1d771364ead9d74af6d963494dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:31:31 +0200 Subject: [PATCH 241/354] soc/intel/broadwell/romstage/pch.c: Drop reg-script usage Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46359 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/romstage/pch.c | 54 ++++++++++---------------- 1 file changed, 21 insertions(+), 33 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 9afb4e4d51..d68e17eee2 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -15,7 +14,8 @@ #include #include -const struct reg_script pch_interrupt_init_script[] = { +static void pch_route_interrupts(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -28,38 +28,26 @@ const struct reg_script pch_interrupt_init_script[] = { */ /* Device interrupt pin register (board specific) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP, - (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP, - (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */ - DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */ - DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */ - DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */ - DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */ - DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */ - DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */ - DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */ - DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)), - - REG_SCRIPT_END -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ +} static void pch_enable_lpc(void) { @@ -76,7 +64,7 @@ static void pch_enable_lpc(void) void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); + pch_route_interrupts(); pch_enable_lpc(); From 239c966e48da3c651c79eb2b8936a6c3fdaea984 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 21:34:53 +0200 Subject: [PATCH 242/354] soc/intel/broadwell: Relocate `report_memory_config` function This allows us to make it static, like it is on Haswell. Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46360 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../intel/broadwell/include/soc/romstage.h | 1 - src/soc/intel/broadwell/romstage/raminit.c | 41 +++++++++++++++++++ .../broadwell/romstage/report_platform.c | 41 ------------------- 3 files changed, 41 insertions(+), 42 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index f45419c10b..721e23f5f5 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -19,7 +19,6 @@ void raminit(struct pei_data *pei_data); struct chipset_power_state; struct chipset_power_state *fill_power_state(void); void report_platform_info(void); -void report_memory_config(void); void set_max_freq(void); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 0580ca69b0..fb780cfbbb 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -21,6 +21,47 @@ #include #include +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + /* * Find PEI executable in coreboot filesystem and execute it. */ diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 938f3ebd37..4ed84d7cea 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -180,44 +180,3 @@ void report_platform_info(void) report_pch_info(); report_igd_info(); } - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -void report_memory_config(void) -{ - u32 addr_decoder_common, addr_decode_ch[2]; - int i; - - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} From 430f1c57649f81c596cf3ad1575e24ab881ec82c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:01:48 +0200 Subject: [PATCH 243/354] soc/intel/broadwell: Align raminit-related code with Haswell Use Haswell MCHBAR register names and align cosmetics of functions. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46364 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/broadwell/include/soc/systemagent.h | 7 ++++- src/soc/intel/broadwell/romstage/raminit.c | 27 +++++++++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 3b56e9d316..920b710d40 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -87,7 +87,10 @@ #define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR_PEI_VERSION 0x5034 +#define MAD_CHNL 0x5000 +#define MAD_DIMM(ch) (0x5004 + 4 * (ch)) + +#define MRC_REVISION 0x5034 #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 @@ -127,6 +130,8 @@ #define BIOS_RESET_CPL 0x5da8 +#define MC_BIOS_DATA 0x5e04 + /* System Agent identification */ u8 systemagent_revision(void); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index fb780cfbbb..00419fc307 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -27,33 +27,38 @@ */ static void report_memory_config(void) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, + (addr_decoder_common >> 0) & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); + + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", @@ -128,10 +133,10 @@ void raminit(struct pei_data *pei_data) die("pei_data version mismatch\n"); /* Print the MRC version after executing the UEFI PEI stage. */ - u32 version = MCHBAR32(MCHBAR_PEI_VERSION); + u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); From 973c9d45adc7f205a68c005083d21f2337616404 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:28:23 +0200 Subject: [PATCH 244/354] soc/intel/broadwell: Fix copy-pasted copy-paste error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code with this error was copy-pasted from Haswell. It was fixed with commit dab81a4 (northbridge/intel/haswell: Fix copy paste error) for Haswell. Do the same for Broadwell. Given that LP SKUs only support one DIMM per channel, this change makes no difference in practice. Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46366 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/soc/intel/broadwell/romstage/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 00419fc307..4977b351f7 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -61,7 +61,7 @@ static void report_memory_config(void) printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } From 162a73759901e0292bb7da593c31391bc0230bc0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:37:07 +0200 Subject: [PATCH 245/354] soc/intel/broadwell: Remove unnecessary array The MAD_DIMM registers can be read within the loop just fine. Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46369 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/include/soc/systemagent.h | 3 +++ src/soc/intel/broadwell/romstage/raminit.c | 7 ++----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 920b710d40..cc0dc4f0c5 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -87,6 +87,9 @@ #define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) +/* Memory controller characteristics */ +#define NUM_CHANNELS 2 + #define MAD_CHNL 0x5000 #define MAD_DIMM(ch) (0x5004 + 4 * (ch)) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 4977b351f7..65e386a7c7 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -27,12 +27,9 @@ */ static void report_memory_config(void) { - u32 addr_decode_ch[2]; int i; const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); @@ -42,8 +39,8 @@ static void report_memory_config(void) (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; + for (i = 0; i < NUM_CHANNELS; i++) { + const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); From 29a52c8308ab270c46c1d859db308ba1de5d1e81 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:32:55 +0200 Subject: [PATCH 246/354] soc/intel/broadwell: Add ECC config reporting This has been taken from Haswell, and is just to reduce differences. Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/romstage/raminit.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 65e386a7c7..7020ddfe0d 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -21,6 +21,13 @@ #include #include +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + /* * Dump in the log memory controller configuration as read from the memory * controller registers. @@ -43,7 +50,7 @@ static void report_memory_config(void) const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); From 10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 11 Oct 2020 14:05:32 +0200 Subject: [PATCH 247/354] {cpu,soc}/intel: deduplicate cpu code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/common/common.h | 6 +++ src/cpu/intel/common/common_init.c | 43 ++++++++++++++++++++ src/cpu/intel/haswell/haswell.h | 1 - src/cpu/intel/haswell/haswell_init.c | 42 ------------------- src/cpu/intel/model_2065x/model_2065x.h | 1 - src/cpu/intel/model_2065x/model_2065x_init.c | 9 ---- src/cpu/intel/model_206ax/model_206ax.h | 1 - src/cpu/intel/model_206ax/model_206ax_init.c | 37 ----------------- src/include/cpu/intel/msr.h | 2 + src/soc/intel/alderlake/cpu.c | 41 +------------------ src/soc/intel/alderlake/include/soc/msr.h | 1 - src/soc/intel/broadwell/cpu.c | 42 ------------------- src/soc/intel/broadwell/include/soc/msr.h | 1 - src/soc/intel/cannonlake/cpu.c | 41 ------------------- src/soc/intel/cannonlake/include/soc/msr.h | 1 - src/soc/intel/denverton_ns/include/soc/msr.h | 1 - src/soc/intel/elkhartlake/cpu.c | 41 +------------------ src/soc/intel/elkhartlake/include/soc/msr.h | 1 - src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/icelake/cpu.c | 41 +------------------ src/soc/intel/icelake/include/soc/msr.h | 1 - src/soc/intel/jasperlake/cpu.c | 41 +------------------ src/soc/intel/jasperlake/include/soc/msr.h | 1 - src/soc/intel/skylake/cpu.c | 42 ------------------- src/soc/intel/skylake/include/soc/msr.h | 1 - src/soc/intel/tigerlake/cpu.c | 41 +------------------ src/soc/intel/tigerlake/include/soc/msr.h | 1 - 27 files changed, 57 insertions(+), 425 deletions(-) diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 57a51e5538..dd8c2b8a27 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -33,4 +33,10 @@ bool intel_ht_sibling(void); */ void set_aesni_lock(void); +void enable_lapic_tpr(void); + +void configure_dca_cap(void); + +void set_energy_perf_bias(u8 policy); + #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index a54e89183f..f4bf245c2f 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "common.h" @@ -286,3 +287,45 @@ void set_aesni_lock(void) msr_set(MSR_FEATURE_CONFIG, AESNI_LOCK); } + +void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERF_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERF_BIAS, msr); + + printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); +} diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index b336e4c2c6..fd1ce9e912 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -28,7 +28,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e03d30fba0..32b6a9daf4 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -577,29 +577,6 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -622,25 +599,6 @@ static void set_max_ratio(void) ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "CPU: energy policy set to %u\n", policy); -} - static void configure_mca(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 1e3d41835a..566f82ed89 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,6 @@ #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 65b28c0a0e..db433536cf 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -148,15 +148,6 @@ static void configure_misc(void) wrmsr(IA32_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index e24993ceb4..eb340adee9 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -15,7 +15,6 @@ #define FLEX_RATIO_EN (1 << 16) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 5af5ff905e..7fb412c0ca 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -338,29 +338,6 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -383,20 +360,6 @@ static void set_max_ratio(void) ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); -} - static void configure_mca(void) { msr_t msr; diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 51b73950d6..9dbea776dd 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -9,4 +9,6 @@ #define AESNI_DISABLE (1 << 1) #define AESNI_LOCK (1 << 0) +#define MSR_PIC_MSG_CONTROL 0x2e + #endif /* CPU_INTEL_MSR_H */ diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index e6a21c170e..9b7cc3e4dd 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -86,29 +87,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -128,23 +106,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/alderlake/include/soc/msr.h b/src/soc/intel/alderlake/include/soc/msr.h index 67e09dcf41..954fce0a82 100644 --- a/src/soc/intel/alderlake/include/soc/msr.h +++ b/src/soc/intel/alderlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 179cd43e3a..00460c6282 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -311,29 +311,6 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -359,25 +336,6 @@ static void set_max_ratio(void) ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "CPU: energy policy set to %u\n", policy); -} - static void configure_mca(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 1e47b4429e..b8ed3328cc 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0622034217..b6b921a29b 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -83,29 +83,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - /* * The emulated ACPI timer allows replacing of the ACPI timer * (PM1_TMR) to have no impart on the system. @@ -129,24 +106,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } - -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 57d109b318..1c902d5abb 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_PL3_CONTROL 0x615 #define MSR_VR_MISC_CONFIG2 0x636 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 9199689ed7..1f64235a14 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -3,7 +3,6 @@ #ifndef _DENVERTON_NS_MSR_H_ #define _DENVERTON_NS_MSR_H_ -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 271d244db9..c51f3fa550 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -80,29 +81,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -122,23 +100,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/elkhartlake/include/soc/msr.h b/src/soc/intel/elkhartlake/include/soc/msr.h index 67e09dcf41..954fce0a82 100644 --- a/src/soc/intel/elkhartlake/include/soc/msr.h +++ b/src/soc/intel/elkhartlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 21da528daa..57367495ad 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM + select CPU_INTEL_COMMON select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e76f61fa99..b739d74db6 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -80,29 +81,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -122,23 +100,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/icelake/include/soc/msr.h b/src/soc/intel/icelake/include/soc/msr.h index 67e09dcf41..954fce0a82 100644 --- a/src/soc/intel/icelake/include/soc/msr.h +++ b/src/soc/intel/icelake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 1944e5c269..6f071c33f9 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -80,29 +81,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -122,23 +100,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/jasperlake/include/soc/msr.h b/src/soc/intel/jasperlake/include/soc/msr.h index 67e09dcf41..954fce0a82 100644 --- a/src/soc/intel/jasperlake/include/soc/msr.h +++ b/src/soc/intel/jasperlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e716c66620..fcec0cefba 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -83,48 +83,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); -} - static void configure_c_states(void) { msr_t msr; diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 3ef9da2a15..92e8215567 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 1a5165d1e5..e13712d05f 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -86,29 +87,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void enable_pm_timer_emulation(void) { msr_t msr; @@ -128,23 +106,6 @@ static void enable_pm_timer_emulation(void) wrmsr(MSR_EMULATE_PM_TIMER, msr); } -static void set_energy_perf_bias(u8 policy) -{ - msr_t msr; - int ecx; - - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) - return; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h index 67e09dcf41..954fce0a82 100644 --- a/src/soc/intel/tigerlake/include/soc/msr.h +++ b/src/soc/intel/tigerlake/include/soc/msr.h @@ -5,7 +5,6 @@ #include -#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_VR_MISC_CONFIG2 0x636 #endif From 062b92ef654a97648380a1a9a9fe34229ee76e31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 20 Oct 2020 14:27:09 +0200 Subject: [PATCH 248/354] cpu/intel/common: rework code previously moved to common cpu code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/common/common.h | 6 +++++ src/cpu/intel/common/common_init.c | 36 ++++++++---------------------- src/include/cpu/intel/msr.h | 1 + src/include/cpu/x86/msr.h | 3 ++- 4 files changed, 18 insertions(+), 28 deletions(-) diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index dd8c2b8a27..fdacd1f74b 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -33,10 +33,16 @@ bool intel_ht_sibling(void); */ void set_aesni_lock(void); +/* Enable local CPU APIC TPR (Task Priority Register) updates */ void enable_lapic_tpr(void); +/* Enable DCA (Direct Cache Access) */ void configure_dca_cap(void); +/* + * Set EPB (Energy Performance Bias) + * Possible values are 0 (performance) to 15 (powersave). + */ void set_energy_perf_bias(u8 policy); #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index f4bf245c2f..d0b66d4815 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -8,6 +8,8 @@ #include #include "common.h" +#define CPUID_6_ECX_EPB (1 << 3) + void set_vmx_and_lock(void) { set_feature_ctrl_vmx(); @@ -290,42 +292,22 @@ void set_aesni_lock(void) void enable_lapic_tpr(void) { - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); + msr_unset(MSR_PIC_MSG_CONTROL, TPR_UPDATES_DISABLE); } void configure_dca_cap(void) { - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } + if (cpu_get_feature_flags_ecx() & CPUID_DCA) + msr_set(IA32_PLATFORM_DCA_CAP, DCA_TYPE0_EN); } void set_energy_perf_bias(u8 policy) { - msr_t msr; - int ecx; + u8 epb = policy & ENERGY_POLICY_MASK; - /* Determine if energy efficient policy is supported. */ - ecx = cpuid_ecx(0x6); - if (!(ecx & (1 << 3))) + if (!(cpuid_ecx(6) & CPUID_6_ECX_EPB)) return; - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); + msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb); + printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb); } diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 9dbea776dd..a2165f365a 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -10,5 +10,6 @@ #define AESNI_LOCK (1 << 0) #define MSR_PIC_MSG_CONTROL 0x2e +#define TPR_UPDATES_DISABLE (1 << 10) #endif /* CPU_INTEL_MSR_H */ diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 058419fd1e..5ae3ddf93a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,11 +48,12 @@ #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 +#define ENERGY_POLICY_MASK 0xf #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define SMRR_PHYSBASE_MSR 0x1F2 #define SMRR_PHYSMASK_MSR 0x1F3 #define IA32_PLATFORM_DCA_CAP 0x1f8 +#define DCA_TYPE0_EN (1 << 0) #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 From d3318cfe498bf53d8ce7d1cd55afad4a93705216 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 19 Oct 2020 14:16:48 +0800 Subject: [PATCH 249/354] mb/google/zork: update USB 2.0 controller Lane Parameter for berknip Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of "HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers. COMPDISTUNE0: 0x3->0x7 TXVREFTUNE0: 0x6->0xf BUG=b:166398726 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 register is set correctly. 3. U2 SI all pass Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../zork/variants/berknip/overridetree.cb | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 674d5574be..d97a2b5780 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -21,6 +21,54 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration + # USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0xf, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ From 72f4dda6b7d1de5eef1df1d32be4595067c4a15d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 00:23:20 +0200 Subject: [PATCH 250/354] sb/intel/lynxpoint/pcie: Fix clock gating routine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The use of `1 < 5` as a bit mask was obviously a typo. Correct it as `1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states. Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/pcie.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 112c9d3fa3..4a245b1899 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -283,8 +283,7 @@ static void pcie_enable_clock_gating(void) /* Update PECR1 register. */ pci_or_config8(dev, 0xe8, 1); - /* FIXME: Are we supposed to update this register with a constant boolean? */ - pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_or_config8(dev, 0x324, 1 << 5); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) From 76b8bc220122efd3774b0bddf5d2f229401fac46 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 23 Jul 2020 02:32:27 +0200 Subject: [PATCH 251/354] nb/intel/haswell: Set up Root Complex topology System BIOS must program some of the Root Complex Topology Capability Structure registers located in configuration space, specs say. So do it. Tested on Asrock B85M Pro4, still boots. Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43744 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/haswell.h | 10 +++ src/northbridge/intel/haswell/northbridge.c | 65 +++++++++++++++++++ .../intel/haswell/registers/epbar.h | 4 ++ 3 files changed, 79 insertions(+) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7728..b160f83876 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -20,6 +20,14 @@ #include "registers/host_bridge.h" +/* Device 0:1.0 PCI configuration space (PCIe Graphics) */ + +#define PEG_DCAP2 0xc4 /* 32bit */ + +#define PEG_ESD 0x144 /* 32bit */ +#define PEG_LE1D 0x150 /* 32bit */ +#define PEG_LE1A 0x158 /* 64bit */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ #define MSAC 0x62 /* Multi Size Aperture Control */ @@ -59,6 +67,7 @@ #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) +#define EPBAR64(x) *((volatile u64 *)(DEFAULT_EPBAR + (x))) #include "registers/epbar.h" @@ -69,6 +78,7 @@ #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR64(x) *((volatile u64 *)(DEFAULT_DMIBAR + (x))) #include "registers/dmibar.h" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 5619d95728..9cf564f474 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -498,12 +498,77 @@ static void northbridge_dmi_init(void) } } +static void northbridge_topology_init(void) +{ + const u32 eple_a[3] = { EPLE2A, EPLE3A, EPLE4A }; + const u32 eple_d[3] = { EPLE2D, EPLE3D, EPLE4D }; + + u32 reg32; + + /* Set the CID1 Egress Port 0 Root Topology */ + reg32 = EPBAR32(EPESD); + reg32 &= ~(0xff << 16); + reg32 |= 1 << 16; + EPBAR32(EPESD) = reg32; + + reg32 = EPBAR32(EPLE1D); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + EPBAR32(EPLE1D) = reg32; + EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + + for (unsigned int i = 0; i <= 2; i++) { + const struct device *const dev = pcidev_on_root(1, i); + + if (!dev || !dev->enabled) + continue; + + EPBAR64(eple_a[i]) = (u64)PCI_DEV(0, 1, i); + + reg32 = EPBAR32(eple_d[i]); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + EPBAR32(eple_d[i]) = reg32; + + pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); + pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1A + 4, 0); + pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); + + /* Read and write to lock register */ + pci_or_config32(dev, PEG_DCAP2, 0); + } + + /* Set the CID1 DMI Port Root Topology */ + reg32 = DMIBAR32(DMIESD); + reg32 &= ~(0xff << 16); + reg32 |= 1 << 16; + DMIBAR32(DMIESD) = reg32; + + reg32 = DMIBAR32(DMILE1D); + reg32 &= ~(0xffff << 16); + reg32 |= 1 | (2 << 16); + DMIBAR32(DMILE1D) = reg32; + DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + + DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + reg32 = DMIBAR32(DMILE2D); + reg32 &= ~(0xff << 16); + reg32 |= 1 | (1 << 16); + DMIBAR32(DMILE2D) = reg32; + + /* Program RO and Write-Once Registers */ + DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); + DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; init_egress(); northbridge_dmi_init(); + northbridge_topology_init(); /* Enable Power Aware Interrupt Routing. */ pair = MCHBAR8(INTRDIRCTL); diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h index 963ceaddf4..699a2ba578 100644 --- a/src/northbridge/intel/haswell/registers/epbar.h +++ b/src/northbridge/intel/haswell/registers/epbar.h @@ -20,5 +20,9 @@ #define EPLE1A 0x058 /* 64bit */ #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ +#define EPLE3D 0x070 /* 32bit */ +#define EPLE3A 0x078 /* 64bit */ +#define EPLE4D 0x080 /* 32bit */ +#define EPLE4A 0x088 /* 64bit */ #endif /* __HASWELL_REGISTERS_EPBAR_H__ */ From 7bbf45ed3f6460b1f25f60c3d055fff604d1df00 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 22 Oct 2020 23:55:24 +0200 Subject: [PATCH 252/354] nb/intel/haswell: Generalise northbridge chip name The code is known to work on processors other than just i7's. Change-Id: I8be83bf51315547b29ab2b239e953554d3a323a0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/haswell/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9cf564f474..88ccd710f3 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -638,6 +638,6 @@ static void enable_dev(struct device *dev) } struct chip_operations northbridge_intel_haswell_ops = { - CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") + CHIP_NAME("Intel Haswell integrated Northbridge") .enable_dev = enable_dev, }; From 9d7431c848d9f8ec35d9407521164b2b5bb83bf0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 22 Oct 2020 23:55:39 +0200 Subject: [PATCH 253/354] nb/intel/ironlake: Generalise northbridge chip name The code is known to work on processors other than just i7's. Also, use the northbridge's name (Ironlake) in place of the CPU's (Arrandale). Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/ironlake/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 2cffa29abf..0047c2f849 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -225,7 +225,7 @@ static void enable_dev(struct device *dev) } struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") + CHIP_NAME("Intel Ironlake integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; From 6642b44b292c9cbbf83905ed89aa00b19c79ddca Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 21 Sep 2020 21:03:46 +0200 Subject: [PATCH 254/354] nb/intel/ironlake: Add more host bridge PCI IDs The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. The current coreboot code seems to be able to change the device ID of the host bridge, but it seems to be missing a warm reset so that the device ID changes. Account for the 'mysterious' device IDs in the northbridge driver, so that booting an OS has a chance to work. For the sake of completeness, add the PCI device IDs for Clarkdale. Although only Arrandale is known to work, both of them are Ironlake. It is possible that the Management Engine handles changing the PCI device ID, which would not happen when using a broken ME firmware. Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/ironlake/northbridge.c | 32 +++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 0047c2f849..68dcf7d13f 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -202,10 +202,34 @@ static struct device_operations mc_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const struct pci_driver mc_driver_ard __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Arrandale DRAM controller */ +/* + * The host bridge PCI device ID can be changed by the firmware. There + * is no documentation about it, though. There's 'official' IDs, which + * appear in spec updates and Windows drivers, and 'mysterious' IDs, + * which Intel doesn't want OSes to know about and thus are not listed. + * + * The current coreboot code seems to be able to change the device ID + * of the host bridge, but it seems to be missing a warm reset so that + * the device ID changes. Account for the 'mysterious' device IDs in + * the northbridge driver, so that booting an OS has a chance to work. + */ +static const unsigned short pci_device_ids[] = { + /* 'Official' DIDs */ + 0x0040, /* Clarkdale */ + 0x0044, /* Arrandale */ + 0x0048, /* Unknown, but it appears in OS drivers and raminit */ + + /* Mysterious DIDs, taken from Linux' intel-agp driver */ + 0x0062, /* Arrandale A-? */ + 0x0069, /* Clarkdale K-0 */ + 0x006a, /* Arrandale K-0 */ + 0 +}; + +static const struct pci_driver mc_driver_ilk __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; static struct device_operations cpu_bus_ops = { From 3e33be2e69267b2212a98579f16643fe3c51b6b1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 16 Sep 2020 12:50:59 +0200 Subject: [PATCH 255/354] nb/intel/gm45: Add more DMIBAR/EPBAR registers Add definitions for more DMIBAR/EPBAR registers, and specify their sizes as well. Also, expand a comment as the registers' purpose is now known. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/gm45.h | 59 ++++++++++++++++++++++------ src/northbridge/intel/gm45/pcie.c | 52 ++++++++++++------------ src/northbridge/intel/gm45/raminit.c | 8 ++-- 3 files changed, 77 insertions(+), 42 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 95457fb4b7..0fec20c1f2 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -359,14 +359,29 @@ enum { #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) -#define DMIVC0RCTL 0x14 -#define DMIVC1RCTL 0x20 -#define DMIVC1RSTS 0x26 -#define DMIESD 0x44 -#define DMILE1D 0x50 -#define DMILE1A 0x58 -#define DMILE2D 0x60 -#define DMILE2A 0x68 +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ /* * EPBAR @@ -376,10 +391,30 @@ enum { #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) -#define EPESD 0x44 -#define EPLE1D 0x50 -#define EPLE1A 0x58 -#define EPLE2D 0x60 +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 0eb1287f3b..ce49d6200d 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -10,34 +10,34 @@ static void init_egress(void) { /* VC0: TC0 only */ - EPBAR8(0x14) &= 1; - EPBAR8(0x4) = (EPBAR8(0x4) & ~7) | 1; + EPBAR8(EPVC0RCTL) &= 1; + EPBAR8(EPPVCCAP1) = (EPBAR8(EPPVCCAP1) & ~7) | 1; /* VC1: isoch */ - EPBAR32(0x28) = 0x0a0a0a0a; - EPBAR32(0x1c) = (EPBAR32(0x1c) & ~(127 << 16)) | (0x0a << 16); + EPBAR32(EPVC1MTS) = 0x0a0a0a0a; + EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~(127 << 16)) | (0x0a << 16); /* VC1: ID1, TC7 */ - EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24); - EPBAR8(0x20) = (EPBAR8(0x20) & 1) | (1 << 7); + EPBAR32(EPVC1RCTL) = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); + EPBAR8(EPVC1RCTL) = (EPBAR8(EPVC1RCTL) & 1) | (1 << 7); /* VC1 ARB table: setup and enable */ - EPBAR32(0x100) = 0x55555555; - EPBAR32(0x104) = 0x55555555; - EPBAR32(0x108) = 0x55555555; - EPBAR32(0x10c) = 0x55555555; - EPBAR32(0x110) = 0x55555555; - EPBAR32(0x114) = 0x55555555; - EPBAR32(0x118) = 0x55555555; - EPBAR32(0x11c) = 0x00005555; - EPBAR32(0x20) |= 1 << 16; + EPBAR32(EP_PORTARB(0)) = 0x55555555; + EPBAR32(EP_PORTARB(1)) = 0x55555555; + EPBAR32(EP_PORTARB(2)) = 0x55555555; + EPBAR32(EP_PORTARB(3)) = 0x55555555; + EPBAR32(EP_PORTARB(4)) = 0x55555555; + EPBAR32(EP_PORTARB(5)) = 0x55555555; + EPBAR32(EP_PORTARB(6)) = 0x55555555; + EPBAR32(EP_PORTARB(7)) = 0x00005555; + EPBAR32(EPVC1RCTL) |= 1 << 16; - while ((EPBAR8(0x26) & 1) != 0); + while ((EPBAR8(EPVC1RSTS) & 1) != 0); /* VC1: enable */ - EPBAR32(0x20) |= 1 << 31; + EPBAR32(EPVC1RCTL) |= 1 << 31; - while ((EPBAR8(0x26) & 2) != 0); + while ((EPBAR8(EPVC1RSTS) & 2) != 0); } /* MCH side */ @@ -46,16 +46,16 @@ static void init_dmi(int b2step) { /* VC0: TC0 only */ DMIBAR8(DMIVC0RCTL) &= 1; - DMIBAR8(0x4) = (DMIBAR8(0x4) & ~7) | 1; + DMIBAR8(DMIPVCCAP1) = (DMIBAR8(DMIPVCCAP1) & ~7) | 1; /* VC1: ID1, TC7 */ - DMIBAR32(0x20) = (DMIBAR32(0x20) & ~(7 << 24)) | (1 << 24); - DMIBAR8(0x20) = (DMIBAR8(0x20) & 1) | (1 << 7); + DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); + DMIBAR8(DMIVC1RCTL) = (DMIBAR8(DMIVC1RCTL) & 1) | (1 << 7); /* VC1: enable */ - DMIBAR32(0x20) |= 1 << 31; + DMIBAR32(DMIVC1RCTL) |= 1 << 31; - while ((DMIBAR8(0x26) & 2) != 0); + while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0); /* additional configuration. */ DMIBAR32(0x200) |= 3 << 13; @@ -223,11 +223,11 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) the endpoint (ICH), but ICH doesn't give any limits. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) - DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once) + DMIBAR8(DMILCTL) |= (3 << 0); // enable ASPM L0s, L1 (write-once) else - DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once) + DMIBAR8(DMILCTL) |= (1 << 0); // enable ASPM L0s (write-once) /* timing */ - DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15); + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~(63 << 12)) | (2 << 12) | (2 << 15); DMIBAR8(0x208 + 3) = 0; DMIBAR32(0x208) &= ~(3 << 20); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7fc97f01a1..f9d7c8fbed 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1128,7 +1128,7 @@ static void clock_crossing_setup(const fsb_clock_t fsb, } } -/* Program egress VC1 timings. */ +/* Program egress VC1 isoch timings. */ static void vc1_program_timings(const fsb_clock_t fsb) { const u32 timings_by_fsb[][2] = { @@ -1136,9 +1136,9 @@ static void vc1_program_timings(const fsb_clock_t fsb) /* FSB 800MHz */ { 0x14, 0x00f000f0 }, /* FSB 667MHz */ { 0x10, 0x00c000c0 }, }; - EPBAR8(0x2c) = timings_by_fsb[fsb][0]; - EPBAR32(0x38) = timings_by_fsb[fsb][1]; - EPBAR32(0x3c) = timings_by_fsb[fsb][1]; + EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0]; + EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1]; + EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1]; } #define DEFAULT_PCI_MMIO_SIZE 2048 From ae2a5228277f3c5b00c29e6f9567ced67309f064 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 16 Sep 2020 13:25:02 +0200 Subject: [PATCH 256/354] nb/intel/gm45: Introduce memmap.h Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45451 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/gm45/gm45.h | 9 +-------- src/northbridge/intel/gm45/memmap.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 8 deletions(-) create mode 100644 src/northbridge/intel/gm45/memmap.h diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 0fec20c1f2..8be18733d1 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -170,14 +170,7 @@ enum { #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ #define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */ -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 - -#define IOMMU_BASE1 0xfed90000 -#define IOMMU_BASE2 0xfed91000 -#define IOMMU_BASE3 0xfed92000 -#define IOMMU_BASE4 0xfed93000 +#include "memmap.h" /* * D0:F0 diff --git a/src/northbridge/intel/gm45/memmap.h b/src/northbridge/intel/gm45/memmap.h new file mode 100644 index 0000000000..c0706d0442 --- /dev/null +++ b/src/northbridge/intel/gm45/memmap.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ + +#define DEFAULT_MCHBAR 0xfed14000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 + +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 + +#endif /* __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ */ From 2f30e8ca03602c14fd98527f1ea54d2a80e4fd63 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 16 Sep 2020 13:29:21 +0200 Subject: [PATCH 257/354] nb/intel/gm45: Clean up header handling There's no need to have ACPI guards in `gm45.h`, since the only things the ASL files require are the base address definitions in `memmap.h`. Also, remove the southbridge include from `gm45.h` and place it only in the files that actually require something from it. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/acpi/gm45.asl | 3 ++- src/northbridge/intel/gm45/early_init.c | 1 + src/northbridge/intel/gm45/gm45.h | 9 --------- src/northbridge/intel/gm45/pcie.c | 1 + 4 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e712..e4d8d66993 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../gm45.h" +#include "../memmap.h" +#include #include /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e362841fb3..86f71d6ff8 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -2,6 +2,7 @@ #include #include +#include #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 8be18733d1..4d8a923c57 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include - -#ifndef __ACPI__ - #include typedef enum { @@ -163,8 +159,6 @@ enum { VCO_5333 = 2, }; -#endif - /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ @@ -409,8 +403,6 @@ enum { #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ -#ifndef __ACPI__ - void gm45_early_init(void); void gm45_early_reset(void); @@ -460,5 +452,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index ce49d6200d..fd7ce527a1 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "gm45.h" From 84fa224b53b726bec2a75dfdedd234bf60b0246e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 24 Oct 2020 11:53:47 +0200 Subject: [PATCH 258/354] sb/intel/lynxpoint: Use spaces around `|` Coding style says so. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 8 ++++---- src/southbridge/intel/lynxpoint/serialio.c | 2 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/southbridge/intel/lynxpoint/usb_ehci.c | 2 +- src/southbridge/intel/lynxpoint/usb_xhci.c | 4 ++-- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 6a5dd40644..03191d1c9a 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -43,7 +43,7 @@ static void pch_enable_bars(void) /* Enable ACPI BAR */ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a161087302..5108fa55b5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -265,7 +265,7 @@ static void pch_power_options(struct device *dev) /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(0x3310) = reg32; reg16 = RCBA16(0x3f02); @@ -345,10 +345,10 @@ static void lpt_lp_pm_init(struct device *dev) /* Set RCBA CIR28 0x3A84 based on SATA port enables */ data = 0x00001005; /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) data |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) data |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = data; @@ -489,7 +489,7 @@ static void pch_fixups(struct device *dev) * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); RCBA32_OR(0x21a8, 0x3); } diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 224e0f4ef6..4fb84a5fb9 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -119,7 +119,7 @@ static void serialio_init_once(int acpi_mode) { if (acpi_mode) { /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ - RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); + RCBA32_OR(ACPIIRQEN, (1 << 13) | (1 << 7) | (1 << 6) | (1 << 5)); } /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 8498a6cdb1..f616473fb9 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -17,7 +17,7 @@ static void pch_smbus_init(struct device *dev) /* Enable clock gating */ /* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */ reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)); pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index a6bc5c6bcb..f121aa84ce 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -119,7 +119,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) static void usb_ehci_clock_gating(struct device *dev) { /* IOBP 0xE5004001[7:6] = 11b */ - pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 60312a4fe7..a6c9eb1fc1 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -235,7 +235,7 @@ static void usb_xhci_clock_gating(struct device *dev) u32 reg32; /* IOBP 0xE5004001[7:6] = 11b */ - pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); + pch_iobp_update(0xe5004001, ~0, (1 << 7) | (1 << 6)); reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ @@ -248,7 +248,7 @@ static void usb_xhci_clock_gating(struct device *dev) reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ - reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); + reg32 |= (1 << 21) | (1 << 20) | (1 << 18) | (1 << 17) | (1 << 8); } /* Avoid writing upper byte as it is write-once */ From cbcbb6767e24c2568bb6444df8dfafdeec019ef4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 00:11:26 +0200 Subject: [PATCH 259/354] sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null Use either a regular null check or `config_of` to avoid bugs. Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46665 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/fadt.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 48 +++++++++++----------- src/southbridge/intel/lynxpoint/serialio.c | 2 +- src/southbridge/intel/lynxpoint/usb_xhci.c | 2 +- 4 files changed, 28 insertions(+), 26 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 9ae6d34d3c..dee0601571 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -61,7 +61,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - if (cfg->docking_supported) + if (cfg && cfg->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5108fa55b5..29cd53f703 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -138,10 +138,8 @@ static void pch_pirq_init(struct device *dev) } } -static void pch_gpi_routing(struct device *dev) +static void pch_gpi_routing(struct device *dev, config_t *config) { - /* Get the chip configuration */ - config_t *config = dev->chip_info; u32 reg32 = 0; /* An array would be much nicer here, or some @@ -173,8 +171,6 @@ static void pch_power_options(struct device *dev) u16 reg16; u32 reg32; const char *state; - /* Get the chip configuration */ - config_t *config = dev->chip_info; u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -243,19 +239,23 @@ static void pch_power_options(struct device *dev) reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME pci_write_config16(dev, GEN_PMCON_1, reg16); - /* - * Set the board's GPI routing on LynxPoint-H. - * This is done as part of GPIO configuration on LynxPoint-LP. - */ - if (pch_is_lp()) - pch_gpi_routing(dev); + if (dev->chip_info) { + config_t *config = dev->chip_info; - /* GPE setup based on device tree configuration */ - enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); + /* + * Set the board's GPI routing on LynxPoint-H. + * This is done as part of GPIO configuration on LynxPoint-LP. + */ + if (pch_is_lp()) + pch_gpi_routing(dev, config); - /* SMI setup based on device tree configuration */ - enable_alt_smi(config->alt_gp_smi_en); + /* GPE setup based on device tree configuration */ + enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, + config->gpe0_en_3, config->gpe0_en_4); + + /* SMI setup based on device tree configuration */ + enable_alt_smi(config->alt_gp_smi_en); + } /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT @@ -345,10 +345,10 @@ static void lpt_lp_pm_init(struct device *dev) /* Set RCBA CIR28 0x3A84 based on SATA port enables */ data = 0x00001005; /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) + if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) data |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) + if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) data |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = data; @@ -636,7 +636,6 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); @@ -651,10 +650,13 @@ static void pch_lpc_add_io_resources(struct device *dev) pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); /* LPC Generic IO Decode range. */ - pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); - pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); + if (dev->chip_info) { + config_t *config = dev->chip_info; + pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); + } } static void pch_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 4fb84a5fb9..199cf9f896 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -131,7 +131,7 @@ static void serialio_init_once(int acpi_mode) static void serialio_init(struct device *dev) { - struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + struct southbridge_intel_lynxpoint_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index a6c9eb1fc1..6a58d41a18 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -328,7 +328,7 @@ static void usb_xhci_init(struct device *dev) /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); - } else if (config->xhci_default) { + } else if (config && config->xhci_default) { /* Route all ports to XHCI */ apm_control(APM_CNT_ROUTE_ALL_XHCI); } From f92f27370d4fbeacfbebe69faf542317f06c8785 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 25 Sep 2020 00:44:52 +0200 Subject: [PATCH 260/354] soc/intel/broadwell: Use get_{pmbase,gpiobase} This is to align Broadwell and Lynx Point. Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pmutil.c | 76 +++++++++++++++------------- src/soc/intel/broadwell/smihandler.c | 9 ++-- 2 files changed, 47 insertions(+), 38 deletions(-) diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index c96ed18b8a..e63a981456 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -19,6 +19,12 @@ #include #include #include +#include + +static inline uint16_t get_gpiobase(void) +{ + return GPIO_BASE_ADDRESS; +} /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -59,17 +65,17 @@ static void print_gpio_status(u32 status, int start) /* Enable events in PM1 control register */ void enable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt |= mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* Disable events in PM1 control register */ void disable_pm1_control(u32 mask) { - u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + u32 pm1_cnt = inl(get_pmbase() + PM1_CNT); pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt, get_pmbase() + PM1_CNT); } /* @@ -79,8 +85,8 @@ void disable_pm1_control(u32 mask) /* Clear and return PM1 status register */ static u16 reset_pm1_status(void) { - u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); + u16 pm1_sts = inw(get_pmbase() + PM1_STS); + outw(pm1_sts, get_pmbase() + PM1_STS); return pm1_sts; } @@ -117,7 +123,7 @@ u16 clear_pm1_status(void) /* Set the PM1 register to events */ void enable_pm1(u16 events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + outw(events, get_pmbase() + PM1_EN); } /* @@ -127,8 +133,8 @@ void enable_pm1(u16 events) /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); + u32 smi_sts = inl(get_pmbase() + SMI_STS); + outl(smi_sts, get_pmbase() + SMI_STS); return smi_sts; } @@ -177,17 +183,17 @@ u32 clear_smi_status(void) /* Enable SMI event */ void enable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* Disable SMI event */ void disable_smi(u32 mask) { - u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 smi_en = inl(get_pmbase() + SMI_EN); smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + outl(smi_en, get_pmbase() + SMI_EN); } /* @@ -200,9 +206,9 @@ static u32 reset_alt_smi_status(void) u32 alt_sts, alt_en; /* Low Power variant moves this to GPIO region as dword */ - alt_sts = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - outl(alt_sts, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_STS); - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); /* Only report enabled events */ return alt_sts & alt_en; @@ -235,9 +241,9 @@ void enable_alt_smi(u32 mask) { u32 alt_en; - alt_en = inl(GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN); alt_en |= mask; - outl(alt_en, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN); + outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN); } /* @@ -247,9 +253,9 @@ void enable_alt_smi(u32 mask) /* Clear TCO status and return events that are enabled and active */ static u32 reset_tco_status(void) { - u32 tcobase = ACPI_BASE_ADDRESS + 0x60; + u32 tcobase = get_pmbase() + 0x60; u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(ACPI_BASE_ADDRESS + 0x68); + u32 tco_en = inl(get_pmbase() + 0x68); /* Don't clear BOOT_STS before SECOND_TO_STS */ outl(tco_sts & ~(1 << 18), tcobase + 0x04); @@ -301,7 +307,7 @@ u32 clear_tco_status(void) void enable_tco_sci(void) { /* Clear pending events */ - outl(ACPI_BASE_ADDRESS + GPE0_STS(3), TCOSCI_STS); + outl(get_pmbase() + GPE0_STS(3), TCOSCI_STS); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); @@ -314,10 +320,10 @@ void enable_tco_sci(void) /* Clear a GPE0 status and return events that are enabled and active */ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { - u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg); - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg); + u32 gpe0_sts = inl(get_pmbase() + sts_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg); - outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg); + outl(gpe0_sts, get_pmbase() + sts_reg); /* Only report enabled events */ return gpe0_sts & gpe0_en; @@ -376,10 +382,12 @@ u32 clear_gpe_status(void) /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { - outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); - outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); - outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); - outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u16 pmbase = get_pmbase(); + + outl(set1, pmbase + GPE0_EN(GPE_31_0)); + outl(set2, pmbase + GPE0_EN(GPE_63_32)); + outl(set3, pmbase + GPE0_EN(GPE_94_64)); + outl(set4, pmbase + GPE0_EN(GPE_STD)); } /* Disable all GPE */ @@ -391,17 +399,17 @@ void disable_all_gpe(void) /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + u32 gpe0_en = inl(get_pmbase() + GPE0_EN(GPE_STD)); gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); + outl(gpe0_en, get_pmbase() + GPE0_EN(GPE_STD)); } int acpi_sci_irq(void) @@ -434,10 +442,10 @@ int acpi_sci_irq(void) int platform_is_resuming(void) { - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(inw(get_pmbase() + PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(inl(get_pmbase() + PM1_CNT)) == ACPI_S3; } /* STM Support */ diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 4a12d786dd..fd5d4522fa 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -133,6 +133,7 @@ static void southbridge_smi_sleep(void) u32 reg32; u8 slp_typ; u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; + u16 pmbase = get_pmbase(); /* save and recover RTC port values */ u8 tmp70, tmp72; @@ -146,7 +147,7 @@ static void southbridge_smi_sleep(void) disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -225,7 +226,7 @@ static void southbridge_smi_sleep(void) * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(pmbase + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); @@ -393,7 +394,7 @@ static void southbridge_smi_gpi(void) static void southbridge_smi_mc(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -436,7 +437,7 @@ static void southbridge_smi_tco(void) static void southbridge_smi_periodic(void) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = inl(get_pmbase() + SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) From 385ce9f4f8574f3346b430fc72bb58ce4d7f10ce Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 10:40:23 +0200 Subject: [PATCH 261/354] nb/intel/haswell/finalize.c: Use PCI register names Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46677 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce1eb..bff03440fa 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -5,17 +5,17 @@ void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ - pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ - pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ From 63837b0af094177902f51ce257265f4a6e374256 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 10:46:37 +0200 Subject: [PATCH 262/354] nb/intel/haswell/finalize.c: Drop obsolete SA PM lock This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect. Tested on Asrock B85M Pro4, still boots. Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index bff03440fa..ca10146584 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,7 +18,6 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); From 97f0d81503be2053a544e80b61732ff5d5479ef0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 10:53:31 +0200 Subject: [PATCH 263/354] nb/intel/haswell/finalize.c: Lock PCU DDR PTM This register has a lock bit. The Haswell System Agent BIOS Spec revision 0.6.0 indicates it needs to be set, thus set it. Note that Broadwell already locks this register. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 1 + src/northbridge/intel/haswell/registers/mchbar.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca10146584..efbaf68074 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,6 +18,7 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 96d08bfc22..bd99cee585 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -24,6 +24,8 @@ /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ #define MMIO_PAVP_MSG 0x5500 +#define PCU_DDR_PTM_CTL 0x5880 + /* Some power MSRs are also represented in MCHBAR */ #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 From 8cc39a5fae28c02d344b2401bb489898f369929f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 11:00:14 +0200 Subject: [PATCH 264/354] nb/intel/haswell/finalize.c: Lock down MC ARB register The Haswell System Agent BIOS Spec revision 0.6.0 indicates this register needs to be locked, and Broadwell already locks it. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 1 + src/northbridge/intel/haswell/registers/mchbar.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index efbaf68074..1c83110a60 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -24,6 +24,7 @@ void intel_northbridge_haswell_finalize_smm(void) MCHBAR32_OR(REQLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); + MCHBAR32_OR(MCARBLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index bd99cee585..97ae433412 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -47,5 +47,6 @@ #define REQLIM 0x6800 #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc +#define MCARBLCK 0x7ffc #endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ From 6fe3c06614dd423ad9a364c5f578e8c1764de65e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 11:02:48 +0200 Subject: [PATCH 265/354] nb/intel/haswell/finalize.c: Align MC locking with Broadwell Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down. Tested on Asrock B85M Pro4, still boots and register is still locked. Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1c83110a60..22f98625aa 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,6 +17,9 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); + /* Memory Controller Lockdown */ + MCHBAR32(MC_LOCK) |= 0x8f; + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ @@ -26,9 +29,6 @@ void intel_northbridge_haswell_finalize_smm(void) MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; - /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); From f27662f5baa4367e555aa180c02846543a6b5692 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 11:07:41 +0200 Subject: [PATCH 266/354] nb/intel/haswell/finalize.c: Align with Broadwell Reorder register writes to match the locking order in Broadwell. Tested on Asrock B85M Pro4, still boots and registers are still locked. Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 22f98625aa..1600a42625 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,12 +22,12 @@ void intel_northbridge_haswell_finalize_smm(void) MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ /* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); From ebf800c538f45c406838dbd0746b5a387d01fc3b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 11:24:07 +0200 Subject: [PATCH 267/354] nb/intel/haswell/early_init.c: Remove invalid register writes MRC does not use the value of SSKPD, and will overwrite it with constant values at the end of memory initialisation. Since coreboot does not rely on this particular bit's value, it is safe to drop the writes to set it. MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any documentation or code I have access to; not even for Sandy/Ivy Bridge, the platform where this mysterious register write originally came from. These workarounds were copied from Sandy Bridge, but do not apply to Haswell. They were dropped on Broadwell, so drop them for Haswell too. Tested on Asrock B85M Pro4, still boots. Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/early_init.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 79cc27724c..a0e4211f02 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -146,16 +146,6 @@ static void haswell_setup_misc(void) reg32 = MCHBAR32(SAPMCTL); MCHBAR32(SAPMCTL) = reg32 | 1; - /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(SSKPD + 4); - reg32 |= (1UL << 31); - MCHBAR32(SSKPD + 4) = reg32; - - /* VLW (Virtual Legacy Wire?) */ - reg32 = MCHBAR32(0x6120); - reg32 &= ~(1 << 0); - MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); MCHBAR32(INTRDIRCTL) = reg32; From 14cd17a5fb607f61c1a971dc80da8d16e5fa03d6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 14:49:36 +0200 Subject: [PATCH 268/354] soc/intel/broadwell/gma.c: Align `igd_setup_panel` with Haswell Rename it, add a print and factor out refclock value into a variable. Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46688 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/gma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index ba453cdb27..8ccd2783c7 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -281,7 +281,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -static void igd_setup_panel(struct device *dev) +static void gma_setup_panel(struct device *dev) { config_t *conf = config_of(dev); u32 reg32; @@ -326,7 +326,8 @@ static void igd_setup_panel(struct device *dev) Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ - const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + const unsigned int refclock = 24 * MHz; + const unsigned int hz_limit = refclock / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken2; @@ -340,7 +341,12 @@ static void igd_setup_panel(struct device *dev) } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + printk(BIOS_INFO, + "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", + refclock / MHz, pwm_increment, pwm_period, + DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period)); + /* Start with a 50% duty cycle. */ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); @@ -532,7 +538,7 @@ static void igd_init(struct device *dev) gtt_write(0xa008, rp1_gfx_freq << 24); /* Post VBIOS panel setup */ - igd_setup_panel(dev); + gma_setup_panel(dev); /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); From e153a35029ac6ee5874a9cef45594410aa6e61b8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 14:53:59 +0200 Subject: [PATCH 269/354] nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel` This is to reduce differences between Haswell and Broadwell. Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/haswell/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 5a6bb8e1de..2368e7bf86 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -287,7 +287,7 @@ static void init_display_planes(void) static void gma_setup_panel(struct device *dev) { - struct northbridge_intel_haswell_config *conf = dev->chip_info; + struct northbridge_intel_haswell_config *conf = config_of(dev); u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); From db3047c57b9690fc00f7f12e9bf3ac6d5f8e844b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 14:56:19 +0200 Subject: [PATCH 270/354] nb/intel/haswell/gma.c: Move log message to the right place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The message was being printed too early, possibly because it was relocated around alongside the rest of the code. Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46690 Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2368e7bf86..dc7b629a2e 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -290,8 +290,6 @@ static void gma_setup_panel(struct device *dev) struct northbridge_intel_haswell_config *conf = config_of(dev); u32 reg32; - printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(PCH_PORT_HOTPLUG); if (!reg32) { @@ -493,7 +491,8 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } - /* Post panel init */ + printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); + gma_pm_init_post_vbios(dev); gma_enable_swsci(); From da59ca94cf8004d225edfc07103d06d1beaf2fc1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 14:59:37 +0200 Subject: [PATCH 271/354] nb/intel/haswell/gma.c: Drop space after unary `!` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I72f75f3df50af362874818f2c1883a6a1c741087 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46691 Reviewed-by: Swift Geek (Sebastian Grzywna) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index dc7b629a2e..989d100585 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -485,7 +485,7 @@ static void gma_func0_init(struct device *dev) } } - if (! lightup_ok) { + if (!lightup_ok) { printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); mdelay(CONFIG_PRE_GRAPHICS_DELAY); pci_dev_init(dev); From a8ddc89d27ed72cf328ef82f5f3c0bdbe6b9f7f1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 23 Oct 2020 19:29:24 +0530 Subject: [PATCH 272/354] vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432 List of changes: 1. FSP-M Header: - Add new UPD GpioOverride - Change help text for PlatformDebugConsent UPD - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust Reservedxx UPD Offset - PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew by 4 elements Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 168 ++++---- .../intel/fsp/fsp2_0/alderlake/FspsUpd.h | 395 +++++++++--------- 2 files changed, 291 insertions(+), 272 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 8c4582a4ea..a4b885db47 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -241,13 +241,12 @@ typedef struct { UINT8 SpdAddressTable[16]; /** Offset 0x0148 - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options.\Manual: Do not use Platform Debug Consent to override other debug-relevant - policies, but the user must set each debug option manually, aimed at advanced users.\n - Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix + is viable\n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual **/ UINT8 PlatformDebugConsent; @@ -425,107 +424,107 @@ typedef struct { /** Offset 0x0230 - Reserved **/ - UINT8 Reserved13[2]; + UINT8 Reserved13; -/** Offset 0x0232 - Program GPIOs for LFP on DDI port-A device +/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x0233 - Program GPIOs for LFP on DDI port-B device +/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortBConfig; -/** Offset 0x0234 - Enable or disable HPD of DDI port A +/** Offset 0x0233 - Enable or disable HPD of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortAHpd; -/** Offset 0x0235 - Enable or disable HPD of DDI port B +/** Offset 0x0234 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x0236 - Enable or disable HPD of DDI port C +/** Offset 0x0235 - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x0237 - Enable or disable HPD of DDI port 1 +/** Offset 0x0236 - Enable or disable HPD of DDI port 1 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPort1Hpd; -/** Offset 0x0238 - Enable or disable HPD of DDI port 2 +/** Offset 0x0237 - Enable or disable HPD of DDI port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Hpd; -/** Offset 0x0239 - Enable or disable HPD of DDI port 3 +/** Offset 0x0238 - Enable or disable HPD of DDI port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Hpd; -/** Offset 0x023A - Enable or disable HPD of DDI port 4 +/** Offset 0x0239 - Enable or disable HPD of DDI port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Hpd; -/** Offset 0x023B - Enable or disable DDC of DDI port A +/** Offset 0x023A - Enable or disable DDC of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortADdc; -/** Offset 0x023C - Enable or disable DDC of DDI port B +/** Offset 0x023B - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x023D - Enable or disable DDC of DDI port C +/** Offset 0x023C - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x023E - Enable DDC setting of DDI Port 1 +/** Offset 0x023D - Enable DDC setting of DDI Port 1 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort1Ddc; -/** Offset 0x023F - Enable DDC setting of DDI Port 2 +/** Offset 0x023E - Enable DDC setting of DDI Port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Ddc; -/** Offset 0x0240 - Enable DDC setting of DDI Port 3 +/** Offset 0x023F - Enable DDC setting of DDI Port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Ddc; -/** Offset 0x0241 - Enable DDC setting of DDI Port 4 +/** Offset 0x0240 - Enable DDC setting of DDI Port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Ddc; -/** Offset 0x0242 - Reserved +/** Offset 0x0241 - Reserved **/ - UINT8 Reserved14[142]; + UINT8 Reserved14[143]; /** Offset 0x02D0 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -666,192 +665,192 @@ typedef struct { /** Offset 0x065D - Reserved **/ - UINT8 Reserved27[19]; + UINT8 Reserved27[91]; -/** Offset 0x0670 - Enable PCIE RP Mask +/** Offset 0x06B8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x0674 - Reserved +/** Offset 0x06BC - Reserved **/ UINT8 Reserved28[2]; -/** Offset 0x0676 - Enable HD Audio Link +/** Offset 0x06BE - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x0677 - Reserved +/** Offset 0x06BF - Reserved **/ UINT8 Reserved29[3]; -/** Offset 0x067A - Enable HD Audio DMIC_N Link +/** Offset 0x06C2 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x067C - DMIC ClkA Pin Muxing (N - DMIC number) +/** Offset 0x06C4 - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x0684 - DMIC ClkB Pin Muxing +/** Offset 0x06CC - DMIC ClkB Pin Muxing Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x068C - Enable HD Audio DSP +/** Offset 0x06D4 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x068D - Reserved +/** Offset 0x06D5 - Reserved **/ UINT8 Reserved30[3]; -/** Offset 0x0690 - DMIC Data Pin Muxing +/** Offset 0x06D8 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x0698 - Enable HD Audio SSP0 Link +/** Offset 0x06E0 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x069E - Enable HD Audio SoundWire#N Link +/** Offset 0x06E6 - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x06A2 - iDisp-Link Frequency +/** Offset 0x06EA - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x06A3 - iDisp-Link T-mode +/** Offset 0x06EB - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x06A4 - iDisplay Audio Codec disconnection +/** Offset 0x06EC - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x06A5 - Debug Interfaces +/** Offset 0x06ED - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x06A6 - Serial Io Uart Debug Controller Number +/** Offset 0x06EE - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x06A7 - Reserved +/** Offset 0x06EF - Reserved **/ UINT8 Reserved31[13]; -/** Offset 0x06B4 - ISA Serial Base selection +/** Offset 0x06FC - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x06B5 - Reserved +/** Offset 0x06FD - Reserved **/ UINT8 Reserved32[4]; -/** Offset 0x06B9 - MRC Safe Config +/** Offset 0x0701 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x06BA - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x0702 - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x06BB - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x0703 - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x06BC - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x0704 - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x06BD - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x0705 - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x06BE - TCSS USB HOST (xHCI) Enable +/** Offset 0x0706 - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x06BF - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x0707 - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x06C0 - TCSS DMA0 Enable +/** Offset 0x0708 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x06C1 - TCSS DMA1 Enable +/** Offset 0x0709 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x06C2 - Reserved +/** Offset 0x070A - Reserved **/ UINT8 Reserved33[2]; -/** Offset 0x06C4 - Early Command Training +/** Offset 0x070C - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x06C5 - Reserved +/** Offset 0x070D - Reserved **/ UINT8 Reserved34[65]; -/** Offset 0x0706 - Ch Hash Mask +/** Offset 0x074E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0708 - Reserved +/** Offset 0x0750 - Reserved **/ UINT8 Reserved35[64]; -/** Offset 0x0748 - PcdSerialDebugLevel +/** Offset 0x0790 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -860,70 +859,81 @@ typedef struct { **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0749 - Reserved +/** Offset 0x0791 - Reserved **/ UINT8 Reserved36[2]; -/** Offset 0x074B - Safe Mode Support +/** Offset 0x0793 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x074C - Reserved +/** Offset 0x0794 - Reserved **/ UINT8 Reserved37[2]; -/** Offset 0x074E - TCSS USB Port Enable +/** Offset 0x0796 - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x074F - Reserved +/** Offset 0x0797 - Reserved **/ UINT8 Reserved38[50]; -/** Offset 0x0781 - Skip external display device scanning +/** Offset 0x07C9 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0782 - Reserved +/** Offset 0x07CA - Reserved **/ UINT8 Reserved39; -/** Offset 0x0783 - Lock PCU Thermal Management registers +/** Offset 0x07CB - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0784 - Reserved +/** Offset 0x07CC - Reserved **/ UINT8 Reserved40[129]; -/** Offset 0x0805 - Skip CPU replacement check +/** Offset 0x084D - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0806 - Reserved +/** Offset 0x084E - Reserved **/ UINT8 Reserved41[292]; -/** Offset 0x092A - Serial Io Uart Debug Mode +/** Offset 0x0972 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x092B - Reserved +/** Offset 0x0973 - Reserved **/ - UINT8 Reserved42[517]; + UINT8 Reserved42[183]; + +/** Offset 0x0A2A - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0A2B - Reserved +**/ + UINT8 Reserved43[349]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -943,11 +953,11 @@ typedef struct { FSP_M_CONFIG FspmConfig; -/** Offset 0x0B30 +/** Offset 0x0B88 **/ - UINT8 UnusedUpdSpace32[6]; + UINT8 UnusedUpdSpace33[6]; -/** Offset 0x0B36 +/** Offset 0x0B8E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 7ec577a7b5..685eeeb6c4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -80,6 +80,7 @@ typedef struct { #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ typedef struct { @@ -121,107 +122,111 @@ typedef struct { **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x0072 - Enable USB2 ports +/** Offset 0x0072 - Reserved +**/ + UINT8 Reserved2[34]; + +/** Offset 0x0094 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x0082 - Enable USB3 ports +/** Offset 0x00A4 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x008C - Enable xDCI controller +/** Offset 0x00AE - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x008D - Reserved +/** Offset 0x00AF - Reserved **/ - UINT8 Reserved2[28]; + UINT8 Reserved3[26]; -/** Offset 0x00A9 - Enable SATA +/** Offset 0x00C9 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x00AA - SATA Mode +/** Offset 0x00CA - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x00AB - SPIn Device Mode +/** Offset 0x00CB - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[7]; -/** Offset 0x00B2 - Reserved +/** Offset 0x00D2 - Reserved **/ - UINT8 Reserved3[35]; + UINT8 Reserved4[35]; -/** Offset 0x00D5 - SPIn Default Chip Select Mode HW/SW +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW **/ UINT8 SerialIoSpiCsMode[7]; -/** Offset 0x00DC - SPIn Default Chip Select State Low/High +/** Offset 0x00FC - SPIn Default Chip Select State Low/High Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High **/ UINT8 SerialIoSpiCsState[7]; -/** Offset 0x00E3 - UARTn Device Mode +/** Offset 0x0103 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x00EA - Reserved +/** Offset 0x010A - Reserved **/ - UINT8 Reserved4[65]; + UINT8 Reserved5[65]; -/** Offset 0x012B - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0132 - Reserved +/** Offset 0x0152 - Reserved **/ - UINT8 Reserved5[2]; + UINT8 Reserved6[2]; -/** Offset 0x0134 - SerialIoUartRtsPinMuxPolicy +/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartRtsPinMuxPolicy[7]; -/** Offset 0x0150 - SerialIoUartCtsPinMuxPolicy +/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values. **/ UINT32 SerialIoUartCtsPinMuxPolicy[7]; -/** Offset 0x016C - SerialIoUartRxPinMuxPolicy +/** Offset 0x018C - SerialIoUartRxPinMuxPolicy Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values. **/ UINT32 SerialIoUartRxPinMuxPolicy[7]; -/** Offset 0x0188 - SerialIoUartTxPinMuxPolicy +/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values. **/ UINT32 SerialIoUartTxPinMuxPolicy[7]; -/** Offset 0x01A4 - UART Number For Debug Purpose +/** Offset 0x01C4 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. @@ -229,169 +234,169 @@ typedef struct { **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x01A5 - Reserved +/** Offset 0x01C5 - Reserved **/ - UINT8 Reserved6[7]; + UINT8 Reserved7[7]; -/** Offset 0x01AC - I2Cn Device Mode +/** Offset 0x01CC - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x01B4 - Serial IO I2C SDA Pin Muxing +/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x01D4 - Serial IO I2C SCL Pin Muxing +/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x01F4 - Reserved +/** Offset 0x0214 - Reserved **/ - UINT8 Reserved7[192]; + UINT8 Reserved8[192]; -/** Offset 0x02B4 - USB Per Port HS Preemphasis Bias +/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2PhyPetxiset[16]; -/** Offset 0x02C4 - USB Per Port HS Transmitter Bias +/** Offset 0x02E4 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2PhyTxiset[16]; -/** Offset 0x02D4 - USB Per Port HS Transmitter Emphasis +/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2PhyPredeemp[16]; -/** Offset 0x02E4 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2PhyPehalfbit[16]; -/** Offset 0x02F4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x02FE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x0308 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x0312 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x031C - Reserved +/** Offset 0x033C - Reserved **/ - UINT8 Reserved8[80]; + UINT8 Reserved9[80]; -/** Offset 0x036C - Enable LAN +/** Offset 0x038C - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x036D - Reserved +/** Offset 0x038D - Reserved **/ - UINT8 Reserved9[11]; + UINT8 Reserved10[11]; -/** Offset 0x0378 - PCIe PTM enable/disable +/** Offset 0x0398 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. **/ UINT8 PciePtm[28]; -/** Offset 0x0394 - Reserved +/** Offset 0x03B4 - Reserved **/ - UINT8 Reserved10[81]; + UINT8 Reserved11[81]; -/** Offset 0x03E5 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage +/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. **/ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; -/** Offset 0x03E6 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage +/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention mode voltage. **/ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; -/** Offset 0x03E7 - Reserved +/** Offset 0x0407 - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved12; -/** Offset 0x03E8 - Transition time in microseconds from Off (0V) to High Current Mode Voltage +/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x03EA - Reserved +/** Offset 0x040A - Reserved **/ - UINT8 Reserved12[50]; + UINT8 Reserved13[50]; -/** Offset 0x041C - CNVi Configuration +/** Offset 0x043C - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x041D - CNVi BT Core +/** Offset 0x043D - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x041E - CNVi BT Audio Offload +/** Offset 0x043E - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x041F - Reserved +/** Offset 0x043F - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved14; -/** Offset 0x0420 - CNVi RF_RESET pin muxing - Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) - or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +/** Offset 0x0440 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0424 - CNVi CLKREQ pin muxing - Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) - or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in - GpioPins*.h. +/** Offset 0x0444 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* + in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x0428 - Reserved +/** Offset 0x0448 - Reserved **/ - UINT8 Reserved14[166]; + UINT8 Reserved15[174]; -/** Offset 0x04CE - CdClock Frequency selection +/** Offset 0x04F6 - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, @@ -399,293 +404,297 @@ typedef struct { **/ UINT8 CdClock; -/** Offset 0x04CF - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x04F7 - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x04D0 - Enable D3 Hot in TCSS +/** Offset 0x04F8 - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x04D1 - Reserved +/** Offset 0x04F9 - Reserved **/ - UINT8 Reserved15[3]; + UINT8 Reserved16[3]; -/** Offset 0x04D4 - TypeC port GPIO setting +/** Offset 0x04FC - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl = AlderLake) **/ UINT32 IomTypeCPortPadCfg[8]; -/** Offset 0x04F4 - Reserved +/** Offset 0x051C - Reserved **/ - UINT8 Reserved16[8]; + UINT8 Reserved17[8]; -/** Offset 0x04FC - Enable D3 Cold in TCSS +/** Offset 0x0524 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x04FD - Reserved +/** Offset 0x0525 - Reserved **/ - UINT8 Reserved17[8]; + UINT8 Reserved18[8]; -/** Offset 0x0505 - Enable VMD controller +/** Offset 0x052D - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x0506 - Reserved +/** Offset 0x052E - Reserved **/ - UINT8 Reserved18[108]; + UINT8 Reserved19[120]; -/** Offset 0x0572 - TCSS Aux Orientation Override Enable +/** Offset 0x05A6 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x0574 - TCSS HSL Orientation Override Enable +/** Offset 0x05A8 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x0576 - Reserved +/** Offset 0x05AA - Reserved **/ - UINT8 Reserved19[2]; + UINT8 Reserved20[2]; -/** Offset 0x0578 - ITBT Root Port Enable +/** Offset 0x05AC - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x057C - Reserved +/** Offset 0x05B0 - Reserved **/ - UINT8 Reserved20[2]; + UINT8 Reserved21[2]; -/** Offset 0x057E - ITbtConnectTopology Timeout value +/** Offset 0x05B2 - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x0580 - Reserved +/** Offset 0x05B4 - Reserved **/ - UINT8 Reserved21[7]; + UINT8 Reserved22[7]; -/** Offset 0x0587 - Enable/Disable PTM +/** Offset 0x05BB - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x058B - Reserved +/** Offset 0x05BF - Reserved **/ - UINT8 Reserved22[201]; + UINT8 Reserved23[200]; -/** Offset 0x0654 - Skip Multi-Processor Initialization +/** Offset 0x0687 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0655 - Reserved +/** Offset 0x0688 - Reserved **/ - UINT8 Reserved23[11]; + UINT8 Reserved24[8]; -/** Offset 0x0660 - CpuMpPpi +/** Offset 0x0690 - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x0664 - Reserved +/** Offset 0x0694 - Reserved **/ - UINT8 Reserved24[68]; + UINT8 Reserved25[70]; -/** Offset 0x06A8 - Enable Power Optimizer +/** Offset 0x06DA - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x06A9 - Reserved +/** Offset 0x06DB - Reserved **/ - UINT8 Reserved25[33]; + UINT8 Reserved26[33]; -/** Offset 0x06CA - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x06CB - Reserved +/** Offset 0x06FD - Reserved **/ - UINT8 Reserved26[2]; + UINT8 Reserved27[2]; -/** Offset 0x06CD - Enable PCH ISH SPI pins assigned +/** Offset 0x06FF - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x06CE - Enable PCH ISH UART pins assigned +/** Offset 0x0700 - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x06D0 - Enable PCH ISH I2C pins assigned +/** Offset 0x0702 - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x06D3 - Enable PCH ISH GP pins assigned +/** Offset 0x0705 - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[8]; -/** Offset 0x06DB - Reserved +/** Offset 0x070D - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; -/** Offset 0x06DD - Enable LOCKDOWN BIOS LOCK +/** Offset 0x070F - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x06DE - Reserved +/** Offset 0x0710 - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved29[2]; -/** Offset 0x06E0 - RTC Cmos Memory Lock +/** Offset 0x0712 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x06E1 - Enable PCIE RP HotPlug +/** Offset 0x0713 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[28]; -/** Offset 0x06FD - Reserved +/** Offset 0x072F - Reserved **/ - UINT8 Reserved29[56]; + UINT8 Reserved30[56]; -/** Offset 0x0735 - Enable PCIE RP Clk Req Detect +/** Offset 0x0767 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x0751 - PCIE RP Advanced Error Report +/** Offset 0x0783 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x076D - Reserved +/** Offset 0x079F - Reserved **/ - UINT8 Reserved30[196]; + UINT8 Reserved31[196]; -/** Offset 0x0831 - PCIE RP Max Payload +/** Offset 0x0863 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[28]; -/** Offset 0x084D - Touch Host Controller Port 0 Assignment +/** Offset 0x087F - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x084E - Reserved +/** Offset 0x0880 - Reserved **/ - UINT8 Reserved31[6]; + UINT8 Reserved32[5]; -/** Offset 0x0854 - Touch Host Controller Port 1 Assignment +/** Offset 0x0885 - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x0855 - Reserved +/** Offset 0x0886 - Reserved **/ - UINT8 Reserved32[91]; + UINT8 Reserved33[91]; -/** Offset 0x08B0 - PCIE RP Aspm +/** Offset 0x08E1 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[28]; -/** Offset 0x08CC - PCIE RP L1 Substates +/** Offset 0x08FD - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x08E8 - PCIE RP Ltr Enable +/** Offset 0x0919 - Reserved +**/ + UINT8 Reserved34[28]; + +/** Offset 0x0935 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0904 - Reserved +/** Offset 0x0951 - Reserved **/ - UINT8 Reserved33[102]; + UINT8 Reserved35[105]; -/** Offset 0x096A - PCH Sata Pwr Opt Enable +/** Offset 0x09BA - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x096B - Reserved +/** Offset 0x09BB - Reserved **/ - UINT8 Reserved34[50]; + UINT8 Reserved36[50]; -/** Offset 0x099D - Enable SATA Port DmVal +/** Offset 0x09ED - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x09A5 - Reserved +/** Offset 0x09F5 - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved37; -/** Offset 0x09A6 - Enable SATA Port DmVal +/** Offset 0x09F6 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x09B6 - Reserved +/** Offset 0x0A06 - Reserved **/ - UINT8 Reserved36[62]; + UINT8 Reserved38[62]; -/** Offset 0x09F4 - USB2 Port Over Current Pin +/** Offset 0x0A44 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A04 - USB3 Port Over Current Pin +/** Offset 0x0A54 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A0E - Reserved +/** Offset 0x0A5E - Reserved **/ - UINT8 Reserved37[14]; + UINT8 Reserved39[14]; -/** Offset 0x0A1C - Enable 8254 Static Clock Gating +/** Offset 0x0A6C - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -693,7 +702,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A1D - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A6D - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -701,22 +710,22 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A1E - Reserved +/** Offset 0x0A6E - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved40; -/** Offset 0x0A1F - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A6F - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A20 - Reserved +/** Offset 0x0A70 - Reserved **/ - UINT8 Reserved39[113]; + UINT8 Reserved41[113]; -/** Offset 0x0A91 - Enable PS_ON. +/** Offset 0x0AE1 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -724,29 +733,29 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0A92 - Reserved +/** Offset 0x0AE2 - Reserved **/ - UINT8 Reserved40[310]; + UINT8 Reserved42[310]; -/** Offset 0x0BC8 - RpPtmBytes +/** Offset 0x0C18 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0BCC - Reserved +/** Offset 0x0C1C - Reserved **/ - UINT8 Reserved41[99]; + UINT8 Reserved43[99]; -/** Offset 0x0C2F - Enable/Disable IGFX PmSupport +/** Offset 0x0C7F - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C30 - Reserved +/** Offset 0x0C80 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved44; -/** Offset 0x0C31 - GT Frequency Limit +/** Offset 0x0C81 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -760,22 +769,22 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x0C32 - Reserved +/** Offset 0x0C82 - Reserved **/ - UINT8 Reserved43[24]; + UINT8 Reserved45[24]; -/** Offset 0x0C4A - Enable or Disable HWP +/** Offset 0x0C9A - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C4B - Reserved +/** Offset 0x0C9B - Reserved **/ - UINT8 Reserved44[8]; + UINT8 Reserved46[8]; -/** Offset 0x0C53 - TCC Activation Offset +/** Offset 0x0CA3 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -783,63 +792,63 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0C54 - Reserved +/** Offset 0x0CA4 - Reserved **/ - UINT8 Reserved45[34]; + UINT8 Reserved47[34]; -/** Offset 0x0C76 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CC6 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0C77 - Reserved +/** Offset 0x0CC7 - Reserved **/ - UINT8 Reserved46[197]; + UINT8 Reserved48[197]; -/** Offset 0x0D3C - Enable LOCKDOWN SMI +/** Offset 0x0D8C - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D3D - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D8D - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D3E - Unlock all GPIO pads +/** Offset 0x0D8E - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D3F - Reserved +/** Offset 0x0D8F - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved49; -/** Offset 0x0D40 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D90 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; + UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0D70 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DC8 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0DA0 - Reserved +/** Offset 0x0E00 - Reserved **/ - UINT8 Reserved48[289]; + UINT8 Reserved50[313]; -/** Offset 0x0EC1 - LpmStateEnableMask +/** Offset 0x0F39 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0EC2 - Reserved +/** Offset 0x0F3A - Reserved **/ - UINT8 Reserved49[766]; + UINT8 Reserved51[766]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -858,11 +867,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x11C0 +/** Offset 0x1238 **/ - UINT8 UnusedUpdSpace49[6]; + UINT8 UnusedUpdSpace48[6]; -/** Offset 0x11C6 +/** Offset 0x123E **/ UINT16 UpdTerminator; } FSPS_UPD; From 28371e282690dd32ea78a52479331463215e18df Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 23 Oct 2020 19:36:25 +0530 Subject: [PATCH 273/354] soc/intel/alderlake/romstage: Skip GPIO configuration from FSP Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases TEST=Able to build and boot ADLRVP to OS. Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/soc/intel/alderlake/romstage/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 38c1a1b279..868d75e9da 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -157,6 +157,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) From fe152de6976d4e8dd3aaf9cd4cb3db925e144b5e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 15:01:20 +0200 Subject: [PATCH 274/354] nb/intel/haswell/gma.c: Drop unused `set_translation_table` function Change-Id: I6c65a5a74a83b8da299245fd6f4a7ae7c1ed30c3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46692 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 41 ------------------------- src/northbridge/intel/haswell/haswell.h | 1 - 2 files changed, 42 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 989d100585..9627945412 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -120,47 +120,6 @@ u32 map_oprom_vendev(u32 vendev) return new_vendev; } -/** FIXME: Seems to be outdated. */ -/* - * GTT is the Global Translation Table for the graphics pipeline. It is used to translate - * graphics addresses to physical memory addresses. As in the CPU, GTTs map 4K pages. - * - * The setgtt function adds a further bit of flexibility: it allows you to set a range (the - * first two parameters) to point to a physical address (third parameter); the physical address - * is incremented by a count (fourth parameter) for each GTT in the range. - * - * Why do it this way? For ultrafast startup, we can point all the GTT entries to point to one - * page, and set that page to 0s: - * - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * - * this takes about 2 ms, and is a win because zeroing the page takes up to 200 ms. - * - * This call sets the GTT to point to a linear range of pages starting at physbase. - */ - -#define GTT_PTE_BASE (2 << 20) - -void set_translation_table(int start, int end, u64 base, int inc) -{ - int i; - - for (i = start; i < end; i++){ - u64 physical_address = base + i * inc; - - /* swizzle the 32:39 bits to 4:11 */ - u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1; - - /* - * Note: we've confirmed by checking the values that MRC does no useful - * setup before we run this. - */ - gtt_write(GTT_PTE_BASE + i * 4, word); - gtt_read(GTT_PTE_BASE + i * 4); - } -} - static struct resource *gtt_res = NULL; u32 gtt_read(u32 reg) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b160f83876..edca2b6330 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -90,7 +90,6 @@ void mb_late_romstage_setup(void); /* optional */ void haswell_early_initialization(void); void haswell_late_initialization(void); -void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); void report_platform_info(void); From 9a264d7ac93455d90c73644afc8b099472251392 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 24 Oct 2020 08:39:24 +0200 Subject: [PATCH 275/354] mb/lippert/frontrunner-af: Add board URL Change-Id: If58d87296ed6fb176d4bc42ba6f6f39ca069adfd Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46714 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../frontrunner-af/variants/frontrunner-af/board_info.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt index 4a443cdaf0..00f3dcb22c 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt @@ -1,4 +1,5 @@ Category: half +Board URL: https://www.adlinktech.com/Products/PC104SBCs/PC_104_Plus_SBCs/CM2-GF ROM package: SOIC8 ROM protocol: SPI ROM socketed: n From 79b4df2d08d2a4fa3bd430476e30aebd78f2c256 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 24 Oct 2020 08:44:49 +0200 Subject: [PATCH 276/354] mb/lippert/frontrunner-af: Remove unused header include Change-Id: If1d4128055a0fd50d109b4aa04c7d0c8ebb2f6c5 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46715 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../lippert/frontrunner-af/variants/frontrunner-af/bootblock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c index 070da4e7b5..4bb4c10550 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) From 6a8990110eb20d33db1661a8921be5f0e632583a Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 24 Oct 2020 08:48:27 +0200 Subject: [PATCH 277/354] mb/lippert/frontrunner-af: Add blank line in code Adding the blank line reduces the differences with the variant toucan-af. Change-Id: I58bfc99109a2df2eab54a562dc13e7bd946890d9 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/46716 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../lippert/frontrunner-af/variants/frontrunner-af/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c index 71d0f415df..e32e125cd2 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c @@ -79,6 +79,7 @@ static void init(struct device *dev) iomux_write8(190, 1); iomux_write8(191, 1); iomux_write8(192, 1); + /* just in case anyone cares */ if (!fch_gpio_state(197)) printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); From 08e5b65f46e9173451567fd95c7792b595f70a69 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 15:38:17 +0200 Subject: [PATCH 278/354] nb/intel/haswell/gma.c: Drop unused ChromeOS include Change-Id: I598fe743354ea429d6821b95be7d209a9fcf9f0c Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46693 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 9627945412..66c8d2d40d 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -21,10 +21,6 @@ #include "chip.h" #include "haswell.h" -#if CONFIG(CHROMEOS) -#include -#endif - struct gt_reg { u32 reg; u32 andmask; From cb2080f551f0aef75c989d0ba005860376e20538 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 15:45:44 +0200 Subject: [PATCH 279/354] soc/intel/broadwell: Drop `broadwell_pci_ops` This is essentially a duplicate of `pci_dev_ops_pci`. Change-Id: I06a21ebd759c35910cd753d3079ea7902868e89d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46697 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/adsp.c | 2 +- src/soc/intel/broadwell/chip.c | 4 ---- src/soc/intel/broadwell/gma.c | 2 +- src/soc/intel/broadwell/hda.c | 2 +- src/soc/intel/broadwell/include/soc/ramstage.h | 2 -- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/me.c | 2 +- src/soc/intel/broadwell/minihd.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/serialio.c | 2 +- src/soc/intel/broadwell/smbus.c | 2 +- src/soc/intel/broadwell/systemagent.c | 2 +- src/soc/intel/broadwell/xhci.c | 2 +- 13 files changed, 11 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 15858e1024..220ad6f269 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -128,7 +128,7 @@ static struct device_operations adsp_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = adsp_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 16afcce60c..9358c78b62 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -43,7 +43,3 @@ struct chip_operations soc_intel_broadwell_ops = { .enable_dev = &broadwell_enable, .init = &broadwell_init_pre_device, }; - -struct pci_operations broadwell_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem -}; diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 8ccd2783c7..c77f5c4476 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -590,7 +590,7 @@ static struct device_operations igd_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &igd_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 16408252d5..04390d1342 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -139,7 +139,7 @@ static struct device_operations hda_ops = { .enable_resources = &pci_dev_enable_resources, .init = &hda_init, .enable = &hda_enable, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 18a23e1341..0b6ef0d61b 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -16,6 +16,4 @@ void broadwell_run_reference_code(void); static inline void broadwell_run_reference_code(void) { } #endif -extern struct pci_operations broadwell_pci_ops; - #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index ccd372cbc9..dd4e15c80a 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -652,7 +652,7 @@ static struct device_operations device_ops = { .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, .scan_bus = &scan_static_bus, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 7449902575..80ffe2b9ac 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -1041,7 +1041,7 @@ static struct device_operations device_ops = { .enable = &intel_me_enable, .init = &intel_me_init, .final = &intel_me_finalize, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index a39c496ce5..6d96eb363d 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -95,7 +95,7 @@ static struct device_operations minihd_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index b1d953ef73..c9168325e2 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -270,7 +270,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index dbe194a223..766f5dd048 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -273,7 +273,7 @@ static struct device_operations device_ops = { .set_resources = &serialio_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &serialio_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 31715c7182..0bc2c2b234 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -79,7 +79,7 @@ static struct device_operations smbus_ops = { .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 91816be680..0837e0ce27 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -435,7 +435,7 @@ static struct device_operations systemagent_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = systemagent_init, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short systemagent_ids[] = { diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 526781d1c4..baaf5ba6e6 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -201,7 +201,7 @@ static struct device_operations usb_xhci_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &broadwell_pci_ops, + .ops_pci = &pci_dev_ops_pci, .init = xhci_init, }; From e866a2fde43b0c75aa8ce29291c8b44dffe8e65c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 15:54:33 +0200 Subject: [PATCH 280/354] soc/intel/broadwell: Merge `chip.c` into `systemagent.c` Prepare to break down Broadwell into CPU, northbridge and southbridge. Change-Id: Ic844cc3bbff760fa0eed9d81208bbeef39577e9d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46698 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/chip.c | 45 --------------------------- src/soc/intel/broadwell/systemagent.c | 38 ++++++++++++++++++++++ 3 files changed, 38 insertions(+), 46 deletions(-) delete mode 100644 src/soc/intel/broadwell/chip.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 786fe2ae5e..e24b949fb5 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -18,7 +18,6 @@ bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c ramstage-y += adsp.c -ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += cpu_info.c smm-y += cpu_info.c diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c deleted file mode 100644 index 9358c78b62..0000000000 --- a/src/soc/intel/broadwell/chip.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -static struct device_operations pci_domain_ops = { - .read_resources = &pci_domain_read_resources, - .set_resources = &pci_domain_set_resources, - .scan_bus = &pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = &broadwell_init_cpus, -}; - -static void broadwell_enable(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } - } -} - -struct chip_operations soc_intel_broadwell_ops = { - CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, - .init = &broadwell_init_pre_device, -}; diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 0837e0ce27..4b4848b4ef 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -451,3 +452,40 @@ static const struct pci_driver systemagent_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = systemagent_ids }; + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = &broadwell_init_cpus, +}; + +static void broadwell_enable(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + broadwell_pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_broadwell_ops = { + CHIP_NAME("Intel Broadwell") + .enable_dev = &broadwell_enable, + .init = &broadwell_init_pre_device, +}; From d3d50e027f8c5b4b2a19450fa89ed0e07d69ce8e Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Wed, 23 Sep 2020 16:23:41 -0600 Subject: [PATCH 281/354] soc/intel/xeon_sp/acpi: Add pch.asl Add ASL for the PCH. Initially, this only contains soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL may be added in the future. Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836 Reviewed-by: Stefan Reinauer Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/acpi/pch.asl | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/soc/intel/xeon_sp/acpi/pch.asl diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/pch.asl new file mode 100644 index 0000000000..98a5fdd50d --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pch.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file should be included in the proper platform ACPI \_SB PCI scope */ + +/* LPC 0:1f.0 */ +#include From 6871d51125dcf7c091c9c461c3e9b8bfa681217d Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Wed, 12 Aug 2020 20:55:41 +0800 Subject: [PATCH 282/354] mb/google/asurada: fix EC commands timeout The Asurada EC is using the large packet (256B) mode, and we were seeing lots of timeout errors on various commands. The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000, and that is too small for large packet running in 1M so we should change EC SPI to the same value that kernel is using (3M). BUG=b:161509047 TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot Signed-off-by: Hung-Te Lin Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/mainboard/google/asurada/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 04e8898d85..647555a339 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -7,7 +7,7 @@ void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); setup_chromeos_gpios(); gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); From 71e86d66a6633e94f0cf3077570ffbbd26e6e629 Mon Sep 17 00:00:00 2001 From: Xi Chen Date: Wed, 21 Oct 2020 15:41:06 +0800 Subject: [PATCH 283/354] soc/mediatek/mt8192: update descriptions for dram config MEMORY_TEST, MT8192_DRAM_DVFS Signed-off-by: Xi Chen Change-Id: I2e714c0ce588e48bbe6bd8e59c03bdb69dea01e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46616 Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/Kconfig | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 18d9d41ef3..8425005a86 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -33,10 +33,16 @@ config MT8192_DRAM_DVFS bool default n help - This options enables DRAM calibration with multiple frequencies (low, - medium and high) for DVFS feature. + This option enables DRAM calibration with multiple frequencies (low, + medium and high frequency groups, with total 7 frequencies) for DVFS + feature. All supported data rates are: 800, 1200, 1600, 1866, 2400, + 3200, 4266. config MEMORY_TEST bool default y + help + This option enables memory basic compare test to verify the DRAM read + or write is as expected. + endif From 9572dd895324ae18c186b1238770422b2d9240a6 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 21 Oct 2020 16:43:08 +0200 Subject: [PATCH 284/354] include/device/azalia_device: Fix typo Change-Id: Iee2ffb3b5170cd4c630f2b26d1eb418b239a8e23 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/46629 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/device/azalia_device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9246d4bc87..d682772e26 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -54,7 +54,7 @@ enum azalia_pin_type { STEREO_MONO_1_4, ATAPI, RCA, - OPTIONAL, + OPTICAL, OTHER_DIGITAL, OTHER_ANALOG, MULTICHANNEL_ANALOG, From d3108d6c898e7789dc7e5c193158476bca7c4a6e Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Wed, 21 Oct 2020 11:16:08 +0800 Subject: [PATCH 285/354] mb/google/volteer/var/voxel: Disable SRCCLKREQ1# According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel. BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/voxel/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b010..e8be8e3eb3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf From e738a7e337a7446a7dee6e1ddb540c4fa4919a26 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 20 Oct 2020 20:53:27 +0800 Subject: [PATCH 286/354] mb/google/volteer/var/terrador: Disable SRCCLKREQ1# According to the schematic, SRCCLKREQ1# is not connected, so disable it for terrador and todor. BUG=b:171278849 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592 Tested-by: build bot (Jenkins) Reviewed-by: Sheng-Liang Pan Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/terrador/overridetree.cb | 3 +++ src/mainboard/google/volteer/variants/todor/overridetree.cb | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 001d5f6835..ae26e79558 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -16,6 +16,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 001d5f6835..ae26e79558 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -16,6 +16,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf From 7d1a137b845ad0b4d1aa1553070b26411b899cf6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 21 Oct 2020 10:42:25 +0800 Subject: [PATCH 287/354] mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- .../google/volteer/variants/baseboard/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7486aef84c..b76f627873 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -103,10 +103,10 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[1]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA register "SataEnable" = "1" From f209b18df3b66d78a9838787182d40fc72eee010 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 20 Oct 2020 02:44:53 +0800 Subject: [PATCH 288/354] mb/google/zork: Update style of check on cbi return values Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition. BUG=None TEST=check with empty CBI value Signed-off-by: Eric Lai Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566 Reviewed-by: Martin Roth Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/baseboard/helpers.c | 8 ++++---- src/mainboard/google/zork/variants/berknip/gpio.c | 2 +- src/mainboard/google/zork/variants/dalboz/gpio.c | 2 +- src/mainboard/google/zork/variants/dirinboz/gpio.c | 2 +- src/mainboard/google/zork/variants/ezkinil/gpio.c | 2 +- src/mainboard/google/zork/variants/morphius/gpio.c | 2 +- src/mainboard/google/zork/variants/trembyle/gpio.c | 2 +- src/mainboard/google/zork/variants/vilboz/gpio.c | 2 +- src/mainboard/google/zork/variants/woomax/gpio.c | 2 +- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d95ab823f6..cc07fe18d6 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -57,7 +57,7 @@ static int get_fw_config(uint32_t *val) return 0; } - if (google_chromeec_cbi_get_fw_config(&known_value)) { + if (google_chromeec_cbi_get_fw_config(&known_value) != 0) { printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); return -1; } @@ -95,7 +95,7 @@ bool variant_uses_v3_schematics(void) if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_SCHEMATICS)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS) @@ -111,7 +111,7 @@ bool variant_uses_v3_6_schematics(void) if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS) @@ -136,7 +136,7 @@ bool variant_has_active_low_wifi_power(void) if (!CONFIG(VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH)) return true; - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) return false; if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c index c8cb10fa71..ae2d02a48d 100644 --- a/src/mainboard/google/zork/variants/berknip/gpio.c +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -61,7 +61,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c index 7600d4c8ce..2b46938e9b 100644 --- a/src/mainboard/google/zork/variants/dalboz/gpio.c +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -47,7 +47,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 8da85b6720..7f9582c9b6 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -36,7 +36,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 0ec1ab23da..d2dd104e89 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -81,7 +81,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 8da0de4f60..9b36e3747e 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -69,7 +69,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 1) { diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c index 9931479cc0..4d73ea0122 100644 --- a/src/mainboard/google/zork/variants/trembyle/gpio.c +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -60,7 +60,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version <= 2) { diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 12b303a9c5..91ed61a5c2 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -25,7 +25,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) * and so apply overrides. If board version is provided by the EC, then apply overrides * if version < 2. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 1; if (board_version < 2) { diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index ebbcbea624..cb98df7d41 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -60,7 +60,7 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) uint32_t board_version; /* If board version cannot be read, assume it is board_version 0. */ - if (google_chromeec_cbi_get_board_version(&board_version)) + if (google_chromeec_cbi_get_board_version(&board_version) != 0) board_version = 0; if (board_version == 0) { From 92f46aaac7104c62ab3956dc32af5ccbddc944f1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 15 Sep 2020 08:42:17 +0200 Subject: [PATCH 289/354] src: Include when appropriate Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/drivers/ipmi/ipmi_kcs_ops.c | 1 + src/drivers/ipmi/ipmi_kcs_ops_premem.c | 1 + src/include/device/pnp_ops.h | 1 - src/mainboard/51nb/x210/romstage.c | 1 - src/mainboard/asus/a88xm-e/romstage.c | 1 - src/mainboard/asus/am1i-a/bootblock.c | 1 + src/mainboard/asus/f2a85-m/romstage.c | 1 - src/mainboard/dell/optiplex_9010/sch5545_ec.c | 1 - src/mainboard/facebook/fbg1701/ramstage.c | 1 - src/mainboard/lenovo/t440p/smihandler.c | 1 + src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/ironlake/romstage.c | 1 + src/soc/intel/baytrail/bootblock/bootblock.c | 1 + src/soc/intel/braswell/bootblock/bootblock.c | 1 + src/soc/intel/braswell/southcluster.c | 1 - src/soc/intel/broadwell/lpc.c | 1 - src/soc/intel/broadwell/smbus.c | 1 - src/soc/intel/cannonlake/finalize.c | 1 - src/soc/intel/common/block/pmc/pmc.c | 1 - src/soc/intel/denverton_ns/lpc.c | 1 - src/soc/intel/denverton_ns/pmc.c | 1 - src/soc/intel/elkhartlake/finalize.c | 1 - src/soc/intel/icelake/finalize.c | 1 - src/soc/intel/jasperlake/finalize.c | 1 - src/soc/intel/skylake/finalize.c | 1 - src/soc/intel/tigerlake/finalize.c | 1 - src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 1 - src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h | 1 - src/southbridge/intel/common/finalize.c | 1 - src/southbridge/intel/common/smi.c | 1 - src/southbridge/intel/ibexpeak/early_pch.c | 1 + src/southbridge/intel/lynxpoint/early_pch.c | 1 - 34 files changed, 8 insertions(+), 26 deletions(-) diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 7fa28e3df5..dd8f34c148 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -8,6 +8,7 @@ * end */ +#include #include #include #include diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c index d799be1310..e1ae0dc3e5 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops_premem.c +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 15d31156ed..b57be454a4 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -4,7 +4,6 @@ #define __DEVICE_PNP_OPS_H__ #include -#include #include #if ENV_PNP_SIMPLE_DEVICE diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index 2112e2587f..38652b5068 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -3,7 +3,6 @@ #include #include #include -#include #include static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c index 0354513d6b..a25195539a 100644 --- a/src/mainboard/asus/a88xm-e/romstage.c +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index 4cfa5b1c6a..6e71962cee 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 24861c79a6..6b1c75ef50 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 8894d8b5d4..d11ba97fff 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 59832a47fd..be995731ec 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index 8cc5135e6f..de48240e88 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 05a4cf21f4..d8e82fcb74 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index ce8d504211..0ba7342178 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f5940..dea4f9b72b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index e5ecafe2a2..6b9f3d0e83 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 46f12e7646..fa8283c9f2 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index c5569a4df1..10ac02584d 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 87ace88b2b..e4b6295417 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index dd4e15c80a..8b85a0420d 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index 0bc2c2b234..70655fc891 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 6ef43b97f8..3fe00ba8cc 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e33b7..5bfad71909 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 228e0f65ae..e40d248491 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 64121449f5..8755825db2 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index a1cfd8be29..2e0f2c845e 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 395bd395c4..14dbc06810 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 61b8e33527..d879db94fc 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 9edc7a2e18..6b8576a593 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 44e6806162..332bddeb77 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -6,7 +6,6 @@ * Chapter number: 4, 29 */ -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 965bb66088..bb0f877560 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -14,7 +14,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index ab8537881b..6b84f70d3b 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,7 +26,6 @@ #define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#include #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 59d429747c..975d839e67 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 0dbc48cea5..20926e579e 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac0095ee..ace09e292f 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 03191d1c9a..465aa1e710 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include From fc66ab6959e7c9d9b8edc87d39a05f6a5103d2ef Mon Sep 17 00:00:00 2001 From: Frank Wu Date: Mon, 21 Sep 2020 15:25:19 +0800 Subject: [PATCH 290/354] mb/google/zork/vilboz: Enable SAR proximity sensor STH9324 BUG=b:161759253 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage firmware log: \_SB.I2C2.SEMTECH SX9324: SAR Proximity Sensor at I2C: 02:28 kernel log: INFO kernel: [ 11.238644] sx932x i2c-STH9324:00: initial compensation success Signed-off-by: Frank Wu Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45565 Reviewed-by: Paul Menzel Reviewed-by: Kangheui Won Reviewed-by: Sam McNally Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/vilboz/gpio.c | 9 +++++++-- .../google/zork/variants/vilboz/overridetree.cb | 7 +++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 91ed61a5c2..6fba0e2595 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -16,6 +16,11 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { PAD_GPO(GPIO_140, HIGH), }; +static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { + /* P sensor INT */ + PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -33,6 +38,6 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) return bid_1_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram); + return vilboz_gpio_set_stage_ram; } diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a93beb5bd8..a61c027156 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -142,5 +142,12 @@ chip soc/amd/picasso register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/generic + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" + device i2c 28 on end + end end end # chip soc/amd/picasso From cbcd8a02fc8d5c251ef61a681d6e6cfa0c9a8965 Mon Sep 17 00:00:00 2001 From: Amanda Huang Date: Thu, 22 Oct 2020 10:31:39 +0800 Subject: [PATCH 291/354] mb/google/octopus/var/fleex: Add new SKU for LTE touch New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off for LTE sku and only use Wifi SAR table for non-LTE sku. BUG=b:168001586 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4 and 5. Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4 Signed-off-by: Amanda Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/fleex/variant.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index f1ec818bb3..522faa9d7b 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -5,11 +5,11 @@ #include #include -#define LTE_SKU 4 +#define MIN_LTE_SKU 4 static bool is_lte_sku(void) { - return (google_chromeec_get_board_sku() == LTE_SKU); + return (google_chromeec_get_board_sku() >= MIN_LTE_SKU); } void variant_smi_sleep(u8 slp_typ) From 278ad21fa9dfb2abe8b5bcfab820c0e08e0c02e7 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Tue, 6 Oct 2020 01:40:53 -0700 Subject: [PATCH 292/354] src/drivers/ipmi: Add function to get BMC revision Provide a way to get BMC revision. Tested=On OCP Delta Lake, function can get BMC revision well. Signed-off-by: Tim Chu Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46070 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/drivers/ipmi/ipmi_kcs.h | 2 ++ src/drivers/ipmi/ipmi_kcs_ops.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 501e5dd8c6..33ddd5f016 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -33,6 +33,8 @@ extern int ipmi_kcs_message(int port, int netfn, int lun, int cmd, * returns CB_SUCCESS on success and CB_ERR if an error occurred. */ enum cb_err ipmi_kcs_premem_init(const u16 port, const u16 device); +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision); + struct ipmi_rsp { uint8_t lun; uint8_t cmd; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index dd8f34c148..362f17ac2b 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -29,6 +29,9 @@ static u8 ipmi_revision_major = 0x1; static u8 ipmi_revision_minor = 0x0; +static u8 bmc_revision_major = 0x0; +static u8 bmc_revision_minor = 0x0; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -145,6 +148,9 @@ static void ipmi_kcs_init(struct device *dev) ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); @@ -273,6 +279,18 @@ static void ipmi_ssdt(const struct device *dev) } #endif +void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_revision) +{ + if (!bmc_revision_major || !bmc_revision_minor) { + printk(BIOS_ERR, "IPMI: BMC revision missing\n"); + *ipmi_bmc_major_revision = 0; + *ipmi_bmc_minor_revision = 0; + } else { + *ipmi_bmc_major_revision = bmc_revision_major; + *ipmi_bmc_minor_revision = bmc_revision_minor; + } +} + #if CONFIG(GENERATE_SMBIOS_TABLES) static int ipmi_smbios_data(struct device *dev, int *handle, unsigned long *current) From 5ec02680eb816160bc9f4af2c6385ed3d9e90fbf Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Tue, 6 Oct 2020 03:25:54 -0700 Subject: [PATCH 293/354] mb/ocp/deltalake: Use BMC version to represent ec version In deltalake, there's no embedded controller and BMC version is used to represent ec version. TEST=Build with CB:45138 and CB:46070 Execute "dmidecode -t 0" to check if the firmware version is correct Signed-off-by: Tim Chu Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/mainboard/ocp/deltalake/ramstage.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 74a4468626..9d570900b1 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -26,6 +26,21 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; +/* + * Update SMBIOS type 0 ec version. + * In deltalake, BMC version is used to represent ec version. + * In current version of OpenBMC, it follows IPMI v2.0 to define minor revision as BCD + * encoded, so the format of it must be transferred before send to SMBIOS. + */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + uint8_t bmc_major_revision, bmc_minor_revision; + + ipmi_bmc_version(&bmc_major_revision, &bmc_minor_revision); + *ec_major_revision = bmc_major_revision & 0x7f; /* bit[6:0] Major Firmware Revision */ + *ec_minor_revision = ((bmc_minor_revision / 16) * 10) + (bmc_minor_revision % 16); +} + /* Override SMBIOS 2 Location In Chassis from BMC */ const char *smbios_mainboard_location_in_chassis(void) { From 2c70708a78d137f322bc32556b5b3a13962dfa46 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 19 Oct 2020 17:40:02 +0200 Subject: [PATCH 294/354] soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID This is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration. Tested on Prodrive Hermes. Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/smbus/smbus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 8ba9d7a7b1..59870fbdc8 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -77,6 +77,7 @@ static struct device_operations smbus_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_SMBUS, PCI_DEVICE_ID_INTEL_CNL_SMBUS, + PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER, From 90f01ece00204f26f4d61ae88f4d34f932f45c5c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 19 Oct 2020 18:55:35 +0200 Subject: [PATCH 295/354] soc/intel/common/block/smbus: Add define for I2C_EN Change-Id: Iecccc363f492985555019f2390bd53472a000ba9 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/46563 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/smbus/smbuslib.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h index 5b4e6eb126..38e0d870ae 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.h +++ b/src/soc/intel/common/block/smbus/smbuslib.h @@ -9,6 +9,8 @@ /* PCI Configuration Space : SMBus */ #define HOSTC 0x40 #define HST_EN (1 << 0) +#define I2C_EN (1 << 2) + /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 From 6c02ca696207d809c7c0a035cf4caef1d88dd1e5 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 21 Oct 2020 11:53:22 +0800 Subject: [PATCH 296/354] mb/google/octopus/var/fleex: Add goodix touch pad support Add goodix touch pad as below: HWID : GXTP7288 CID : PNP0C50 I2C address : 0x2C I2C speed : 400Khz HID Descriptor Address : 0x20 BUG=b:171351666 BRANCH=octopus TEST=build image and verify goodix touch pad working. Signed-off-by: Eric Lai Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614 Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- .../google/octopus/variants/fleex/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 0b81752f72..679b101037 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -128,6 +128,15 @@ chip soc/intel/apollolake register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end # - I2C 6 device pci 17.3 on chip drivers/i2c/generic From 4622a2fe828a220d4c1a12945aed4937214f7d93 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 22 Oct 2020 15:12:32 +0200 Subject: [PATCH 297/354] security/tpm/tspi/crtm: Add line break to debug messages Add line break at debug messages. Tested on Facebook FBG1701 Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/46659 Reviewed-by: Christian Walter Reviewed-by: Wim Vervoorn Tested-by: build bot (Jenkins) --- src/security/tpm/tspi/crtm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index d9c62e1e14..eb0744209c 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -112,10 +112,10 @@ uint32_t tspi_measure_cbfs_hook(struct cbfsf *fh, const char *name) if (!tcpa_log_available()) { if (tspi_init_crtm() != VB2_SUCCESS) { printk(BIOS_WARNING, - "Initializing CRTM failed!"); + "Initializing CRTM failed!\n"); return 0; } - printk(BIOS_DEBUG, "CRTM initialized."); + printk(BIOS_DEBUG, "CRTM initialized.\n"); } cbfsf_file_type(fh, &cbfs_type); From e836d1121474c46c41a18425df421232ff3d3a21 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Wed, 21 Oct 2020 17:22:25 +0800 Subject: [PATCH 298/354] mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR Enable front camera power in ramstage. BUG=b:169170677 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: YH Lin --- src/mainboard/google/volteer/variants/voxel/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index b5d070baf0..6e5fc0bae5 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -114,7 +114,7 @@ static const struct pad_config override_gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPO(GPP_D17, 1, DEEP), /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), From 308c1b79768a0cb1c48a150f8a75da71dec99b5f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 27 Sep 2020 13:57:04 +0200 Subject: [PATCH 299/354] console/init: Drop CONSOLE_LEVEL_CONST We limited the configurability of the debug level to stages that have a `.data` section. This is not really a requirement, because a `.bss` section should suffice and we always have that now. We want to make the debug level configurable early but also want to avoid calling get_option() early, as an error therein could result in no console output at all. Hence, we compromise and start using get_option() from the second console init on. TEST=Booted QEMU once with `debug_level=Debug` and once with `debug_level=Notice`. On the second boot, most messages vanished for all stages but the bootblock. Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765 Reviewed-by: Angel Pons Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/console/init.c | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad664..c59807785c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -8,40 +8,25 @@ #include #include -/* Mutable console log level only allowed when RAM comes online. */ -#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION +#define FIRST_CONSOLE (ENV_BOOTBLOCK || (CONFIG(NO_BOOTBLOCK_CONSOLE) && ENV_ROMSTAGE)) static int console_inited; -static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +static int console_loglevel; static inline int get_log_level(void) { if (console_inited == 0) return -1; - if (CONSOLE_LEVEL_CONST) - return get_console_loglevel(); return console_loglevel; } -static inline void set_log_level(int new_level) -{ - if (CONSOLE_LEVEL_CONST) - return; - - console_loglevel = new_level; -} - static void init_log_level(void) { - int debug_level = get_console_loglevel(); + console_loglevel = get_console_loglevel(); - if (CONSOLE_LEVEL_CONST) - return; - - get_option(&debug_level, "debug_level"); - - set_log_level(debug_level); + if (!FIRST_CONSOLE) + get_option(&console_loglevel, "debug_level"); } int console_log_level(int msg_level) From 03102794115230e623ecb95e50e5d7f899956b84 Mon Sep 17 00:00:00 2001 From: Benjamin Doron Date: Thu, 22 Oct 2020 16:36:29 +0000 Subject: [PATCH 300/354] util/intelp2m: Fix typos Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697 Signed-off-by: Benjamin Doron Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/intelp2m/description.md | 6 +++--- util/intelp2m/fields/cb/cb.go | 6 +++--- util/intelp2m/fields/fsp/fsp.go | 6 +++--- util/intelp2m/main.go | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index 9ca56b979e..1aaee40ca0 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -23,9 +23,9 @@ the coreboot project. 0 - inteltool.log (default) 1 - gpio.h 2 - your template -(shell)$ ./intelp2m -t 1 -file coreboot/src/mainboard/youboard/gpio.h +(shell)$ ./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h ``` -You can also add add a template to 'parser/template.go' for your file type with +You can also add a template to 'parser/template.go' for your file type with the configuration of the pads. platform type is set using the -p option (Sunrise by default): @@ -35,7 +35,7 @@ platform type is set using the -p option (Sunrise by default): snr - Sunrise PCH with Skylake/Kaby Lake CPU lbg - Lewisburg PCH with Xeon SP CPU apl - Apollo Lake SoC - cnl - CannonLake-LP or Whiskeylake/Coffelake/Cometlake-U SoC + cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC (default "snr") (shell)$ ./intelp2m -p -file path/to/inteltool.log diff --git a/util/intelp2m/fields/cb/cb.go b/util/intelp2m/fields/cb/cb.go index 2a87cdaa88..3bda62e719 100644 --- a/util/intelp2m/fields/cb/cb.go +++ b/util/intelp2m/fields/cb/cb.go @@ -19,11 +19,11 @@ type field struct { } // generate - wrapper for generating bitfield macros string -// fileds : field structure -func generate(fileds ...*field) { +// fields : field structure +func generate(fields ...*field) { macro := common.GetMacro() var allhidden bool = true - for _, field := range fileds { + for _, field := range fields { if field.unhide { allhidden = false macro.Or() diff --git a/util/intelp2m/fields/fsp/fsp.go b/util/intelp2m/fields/fsp/fsp.go index fa26b5a5c9..360333afd5 100644 --- a/util/intelp2m/fields/fsp/fsp.go +++ b/util/intelp2m/fields/fsp/fsp.go @@ -15,10 +15,10 @@ type field struct { } // generate - wrapper for generating bitfield macros string -// fileds : field structure -func generate(fileds ...*field) { +// fields : field structure +func generate(fields ...*field) { macro := common.GetMacro() - for _, field := range fileds { + for _, field := range fields { if field.override != nil { // override if necessary field.override(field.configmap, field.value) diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index a7bbc91079..511f54d0d0 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -67,9 +67,9 @@ func main() { "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ - "\tcnl - CannonLake-LP or Whiskeylake/Coffelake/Cometlake-U SoC\n") + "\tcnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC\n") - filedstyle := flag.String("fld", "none", "set fileds macros style:\n"+ + fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+ "\tcb - use coreboot style for bit fields macros\n"+ "\tfsp - use fsp style\n"+ "\traw - do not convert, print as is\n") @@ -106,8 +106,8 @@ func main() { os.Exit(1) } - if config.FldStyleSet(*filedstyle) != 0 { - fmt.Printf("Error! Unknown bit fields style option -%s!\n", *filedstyle) + if config.FldStyleSet(*fieldstyle) != 0 { + fmt.Printf("Error! Unknown bit fields style option -%s!\n", *fieldstyle) os.Exit(1) } From 6267cc523b4a6f716060214d06a8226412a65837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:07:44 +0200 Subject: [PATCH 301/354] soc/intel: drop unneeded ISST configuration code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/cpu.c | 28 ---------------------------- src/soc/intel/cannonlake/cpu.c | 28 ---------------------------- src/soc/intel/elkhartlake/cpu.c | 28 ---------------------------- src/soc/intel/icelake/cpu.c | 28 ---------------------------- src/soc/intel/jasperlake/cpu.c | 28 ---------------------------- src/soc/intel/skylake/cpu.c | 28 ---------------------------- src/soc/intel/tigerlake/cpu.c | 28 ---------------------------- 7 files changed, 196 deletions(-) diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 9b7cc3e4dd..39a42651bd 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -31,31 +31,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -122,9 +97,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index b6b921a29b..20da942f84 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -27,31 +27,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -158,9 +133,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index c51f3fa550..720a295e15 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -25,31 +25,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -116,9 +91,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index b739d74db6..ea2b3574b2 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -25,31 +25,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -152,9 +127,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 6f071c33f9..312fc7d7af 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -25,31 +25,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -116,9 +91,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index fcec0cefba..1682503d4b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,31 +27,6 @@ #include "chip.h" -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { config_t *conf = config_of_soc(); @@ -163,9 +138,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index e13712d05f..d7234e7191 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -31,31 +31,6 @@ static void soc_fsp_load(void) fsps_load(romstage_handoff_is_resume()); } -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { msr_t msr; @@ -122,9 +97,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); From d5a45470c816bc8a8bdc43951c9e4c4a592b55d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:27:59 +0200 Subject: [PATCH 302/354] soc/intel/skl: replace conditional on dt option reading CPUID for CPPC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 275e77df1a..637092be97 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -35,6 +35,8 @@ #include "chip.h" +#define CPUID_6_EAX_ISST (1 << 7) + /* * List of suported C-states in this processor. */ @@ -379,7 +381,7 @@ void generate_cpu_entries(const struct device *device) printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config->speed_shift_enable) { + if (cpuid_eax(6) & CPUID_6_EAX_ISST) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); @@ -405,7 +407,7 @@ void generate_cpu_entries(const struct device *device) cores_per_package); } - if (config->speed_shift_enable) + if (cpuid_eax(6) & CPUID_6_EAX_ISST) acpigen_write_CPPC_method(); acpigen_pop_len(); From a64b4f454894988a9c043d53d00b493852f261a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:36:29 +0200 Subject: [PATCH 303/354] mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Frans Hendriks --- src/mainboard/51nb/x210/devicetree.cb | 3 --- src/mainboard/asrock/h110m/devicetree.cb | 3 --- src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 3 --- src/mainboard/facebook/monolith/devicetree.cb | 3 --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 3 --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 1 - src/mainboard/google/eve/devicetree.cb | 1 - src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/glados/devicetree.cb | 3 --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 -- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 1 - src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 -- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 2 -- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 - src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 - src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 3 --- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 2 -- .../intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 --- .../intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 --- .../intel/coffeelake_rvp/variants/baseboard/devicetree.cb | 3 --- src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb | 3 --- src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 3 --- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 3 --- src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb | 3 --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 --- src/mainboard/intel/saddlebrook/devicetree.cb | 3 --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 --- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 --- src/mainboard/kontron/bsl6/devicetree.cb | 2 -- src/mainboard/libretrend/lt1000/devicetree.cb | 3 --- .../prodrive/hermes/variants/baseboard/overridetree.cb | 2 -- src/mainboard/protectli/vault_kbl/devicetree.cb | 2 -- src/mainboard/purism/librem_skl/devicetree.cb | 3 --- src/mainboard/purism/librem_whl/devicetree.cb | 3 --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 3 --- src/mainboard/siemens/chili/variants/base/devicetree.cb | 1 - src/mainboard/siemens/chili/variants/chili/devicetree.cb | 1 - src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 3 --- src/mainboard/system76/lemp9/devicetree.cb | 3 --- src/soc/intel/alderlake/chip.h | 2 -- src/soc/intel/cannonlake/chip.h | 2 -- src/soc/intel/elkhartlake/chip.h | 2 -- src/soc/intel/icelake/chip.h | 3 +-- src/soc/intel/jasperlake/chip.h | 2 -- src/soc/intel/skylake/chip.h | 3 +-- src/soc/intel/tigerlake/chip.h | 3 --- 51 files changed, 2 insertions(+), 116 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 294ae44022..561bd6f54b 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -28,9 +28,6 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d6f29a20e9..57acd33570 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -18,9 +18,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 8f256ad7fb..e8827bf6de 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index bb11d064b3..15ab7efb71 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -29,9 +29,6 @@ chip soc/intel/skylake # "Intel SpeedStep Technology" register "eist_enable" = "1" - # "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11da31..4713589608 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -136,9 +136,6 @@ chip soc/intel/jasperlake register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 775c54815e..bbb63bcc61 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -134,9 +134,6 @@ chip soc/intel/tigerlake register "gpio_pm[3]" = "0" register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aa6af87c3a..de3b5ca8ea 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a2550bb475..519e53ba6c 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -227,7 +227,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "dptf_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 9c11e807e8..703ef5b775 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -305,7 +305,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_psyspl2 = 90, .psys_pmax = 120, diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 12312e980a..2dfb71f2c0 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -30,9 +30,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 10ad029e40..cdd83df114 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -29,8 +29,6 @@ chip soc/intel/cannonlake register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" - # Enable Speed Shift Technology support - register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" # Enable DPTF diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 9f9d9518d6..3797fb0135 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -59,7 +59,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0dc9131aaf..0b3d6c0346 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -246,7 +246,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 167bd036d6..d408f9ee93 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -266,8 +266,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" - register "tcc_offset" = "3" # TCC of 97C register "power_limits_config" = "{ .psys_pmax = 101, diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ed21492946..b7d171b6ff 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -268,7 +268,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0a29601c39..ab1588af80 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -54,8 +54,6 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - # Set speed_shift_enable to 1 to enable P-States, and 0 to disable - register "speed_shift_enable" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 591e0fb478..2334a179df 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -225,7 +225,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 18W for AML-Y register "power_limits_config" = "{ .tdp_pl2_override = 18, diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b3570d73b2..c69875597d 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -247,7 +247,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b1d9a36159..3ff9b30637 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e1ee6c9be8..17d0127ce6 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/cannonlake # USB2 PHY Power gating register "PchUsb2PhySusPgDisable" = "1" - register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "satapwroptimize" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b76f627873..2a62505757 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -230,9 +230,6 @@ chip soc/intel/tigerlake register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 818f32f9fa..73055010ca 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -13,8 +13,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - # Enable Speed Shift Technology/HWP support - register "speed_shift_enable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e10059887e..1110bc1e32 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -60,9 +60,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bf7aa1e962..42023149a9 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -57,9 +57,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 0b40a5c359..12b1c47f33 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -43,9 +43,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 49303da030..1215628dbc 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -152,9 +152,6 @@ chip soc/intel/icelake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index a1c32c99be..e8c6e8f5c4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -152,9 +152,6 @@ chip soc/intel/icelake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b9aec378fb..61a5e70695 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -122,9 +122,6 @@ chip soc/intel/jasperlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 8de089de90..e17c8b71f3 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ chip soc/intel/skylake # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 3afff4506e..07afb7bd1b 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index a25cb8c579..5c64326e3e 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -14,9 +14,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 09ab2583c1..de93c99aa2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,9 +115,6 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 25c229332a..4078894bfd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -119,9 +119,6 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 357f8fa1fa..ef1f0d4a5f 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -2,8 +2,6 @@ chip soc/intel/skylake - register "speed_shift_enable" = "1" - register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d47eca8a48..911690f053 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -30,9 +30,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 071fc5fc95..04e6774f65 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -126,8 +126,6 @@ chip soc/intel/cannonlake # Thermal register "tcc_offset" = "6" # TCC of 94C - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" # Disable S0ix register "s0ix_enable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 2a4b1e9ffd..e6e748a247 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,8 +17,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" register "eist_enable" = "1" # Disable DPTF diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 23c57120f1..2c73280148 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -37,9 +37,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index 497a4cca4d..205033230b 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -24,9 +24,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 28, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index edf13335a2..4f8ceb6815 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000c1641" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 505e9a4852..cca88384ff 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -4,7 +4,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1" register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 5a2fc01e37..3c9d968506 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -4,7 +4,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "RMT" = "0" - register "speed_shift_enable" = "1" register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index dd0e520365..e7b26dc5de 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,9 +3,6 @@ chip soc/intel/skylake register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # FSP Configuration register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 277570ece9..84c0312c3f 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index aaf03f510f..428fd4deeb 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -185,8 +185,6 @@ struct soc_intel_alderlake_config { uint8_t HeciEnabled; /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 69a2cf2f48..7f428a21f0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -261,8 +261,6 @@ struct soc_intel_cannonlake_config { /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5037147d74..26d0f0d666 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -149,8 +149,6 @@ struct soc_intel_elkhartlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 386e77520a..e1b697e3c7 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -169,8 +169,7 @@ struct soc_intel_icelake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; + /* Enable VR specific mailbox command * 00b - no VR specific cmd sent * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 4410de9310..5e9053063b 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -149,8 +149,6 @@ struct soc_intel_jasperlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2584d5d809..41482f10bd 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -461,8 +461,7 @@ struct soc_intel_skylake_config { */ u8 HeciEnabled; u8 PmTimerDisabled; - /* Intel Speed Shift Technology */ - u8 speed_shift_enable; + /* * Enable VR specific mailbox command * 000b - Don't Send any VR command diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb6cda0919..f752b5f415 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -271,9 +271,6 @@ struct soc_intel_tigerlake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Intel Speed Shift Technology */ - uint8_t speed_shift_enable; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; From 6f1754d090e79f6e4d06780a494b62a83a5d8fcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 29 Sep 2020 17:26:58 +0200 Subject: [PATCH 304/354] soc/intel/icl: enable common CPU code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 57367495ad..3b3d4793ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -11,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select SET_IA32_FC_LOCK_BIT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP From e874b1c1794406aa9adcd00a06cdb713b50b88ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 14 Oct 2020 19:17:35 +0200 Subject: [PATCH 305/354] cpu/intel/common: implement the two missing CPPC v2 autonomous registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This implements the two missing registers for the CPPC Hardware Autonomous mode (HWP) to the CPPC v2 package. The right values can be determined via Intel SDM and the ACPI 6.3 spec. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel Reviewed-by: Matt Delco --- src/cpu/intel/common/common_init.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index d0b66d4815..3ea8f36ea8 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -239,11 +239,23 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) if (version >= 2) { /* Autonomous Selection Enable is populated below */ - /* Autonomous Activity Window Register */ - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + msr.addrl = IA32_HWP_REQUEST; - /* Energy Performance Preference Register */ - config->regs[CPPC_PERF_PREF] = unsupported; + /* + * Autonomous Activity Window Register + * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, + */ + msr.bit_width = 10; + msr.bit_offset = 32; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr; + + /* + * Autonomous Energy Performance Preference Register + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, + */ + msr.bit_width = 8; + msr.bit_offset = 24; + config->regs[CPPC_PERF_PREF] = msr; /* Reference Performance */ config->regs[CPPC_REF_PERF] = unsupported; From e61391738ff55243e14d1692dd4746d4345e63ce Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Sat, 12 Sep 2020 23:13:50 +0800 Subject: [PATCH 306/354] mb/ocp/deltalake: Override coreboot log level via VPD Tested=On OCP Delta Lake, log level can be changed via VPD. Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang --- src/mainboard/ocp/deltalake/Kconfig | 1 + src/mainboard/ocp/deltalake/Makefile.inc | 2 +- src/mainboard/ocp/deltalake/loglevel_vpd.c | 20 ++++++++++++++++++++ src/mainboard/ocp/deltalake/vpd.h | 4 ++++ 4 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/ocp/deltalake/loglevel_vpd.c diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index ff5599c007..bb907f1af7 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -3,6 +3,7 @@ if BOARD_OCP_DELTALAKE config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 + select CONSOLE_OVERRIDE_LOGLEVEL select HAVE_ACPI_TABLES select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index be6af246ed..e961a3423a 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -7,6 +7,6 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - +all-$(CONFIG_CONSOLE_OVERRIDE_LOGLEVEL) += loglevel_vpd.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/loglevel_vpd.c b/src/mainboard/ocp/deltalake/loglevel_vpd.c new file mode 100644 index 0000000000..3faf37a0ea --- /dev/null +++ b/src/mainboard/ocp/deltalake/loglevel_vpd.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "vpd.h" + +int get_console_loglevel(void) +{ + int log_level = COREBOOT_LOG_LEVEL_DEFAULT; + char val_str[VPD_LEN]; + + if (vpd_gets(COREBOOT_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + log_level = (int)atol(val_str); + if (log_level < 0 || log_level >= BIOS_NEVER) + log_level = COREBOOT_LOG_LEVEL_DEFAULT; + } + return log_level; +} diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d025..43070c2a16 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,8 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* coreboot log level */ +#define COREBOOT_LOG_LEVEL "coreboot_log_level" +#define COREBOOT_LOG_LEVEL_DEFAULT 4 + #endif From 0141f0d6b899d0f177cce5820a5fc7c6dad0c13d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Oct 2020 10:22:34 +0200 Subject: [PATCH 307/354] sb/amd/*/*/smbus.h: Make 'smbus.h' uniform Reformat 'smbus.h' files and add missing . Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45892 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/southbridge/amd/agesa/hudson/smbus.h | 40 ++++++++++++------------ src/southbridge/amd/cimx/sb800/smbus.h | 39 ++++++++++------------- src/southbridge/amd/pi/hudson/smbus.h | 4 +-- 3 files changed, 38 insertions(+), 45 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 6381d97e9a..96ff5748be 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -5,29 +5,29 @@ #include -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 0a1b279d5b..d058bc869f 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -3,33 +3,26 @@ #ifndef _SB800_SMBUS_H_ #define _SB800_SMBUS_H_ +#include + #define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc -/*//SB00.H -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 -*/ - -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index 239891065d..96ff5748be 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -26,8 +26,8 @@ #define RC_INDXC 1 #define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. From 8ccc8fdf26a9172ef8023e91630bdf88239170c7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Oct 2020 10:59:56 +0200 Subject: [PATCH 308/354] sb/amd/*/*/pci_devs.h: Reduce the difference Also add missing Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45894 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/southbridge/amd/agesa/hudson/pci_devs.h | 144 +++++++++---------- src/southbridge/amd/cimx/sb800/pci_devs.h | 148 ++++++++++---------- src/southbridge/amd/pi/hudson/pci_devs.h | 42 +++--- 3 files changed, 169 insertions(+), 165 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index 94417aaf70..d67395c9ee 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -5,103 +5,103 @@ #include -#define BUS0 0 +#define BUS0 0 /* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7814 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) /* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7800 -#define AHCI_DEVID_MS 0x7801 -#define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7800 +#define AHCI_DEVID_MS 0x7801 +#define AHCI_DEVID_AMD 0x7804 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -#define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x7807 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -#define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x16 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x7808 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* SMBUS */ -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x780B +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* IDE */ #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -# define IDE_DEVID 0x780C -# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +#define IDE_DEVID 0x780C +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif /* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -#define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x780D +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV +#define LPC_FUNC 3 +#define LPC_DEVID 0x780E +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -# define SB_PCI_PORT_DEVID 0x780F -# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +#define SB_PCI_PORT_DEVID 0x780F +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ -#define SD_DEV 0x14 -#define SD_FUNC 7 -#define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7806 +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) /* PCIe Ports */ #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -#define SB_PCIE_PORT1_DEVID 0x7820 -#define SB_PCIE_PORT2_DEVID 0x7821 -#define SB_PCIE_PORT3_DEVID 0x7822 -#define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif #endif /* _AGESA_HUDSON_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h index 8f730e3353..91825ba16e 100644 --- a/src/southbridge/amd/cimx/sb800/pci_devs.h +++ b/src/southbridge/amd/cimx/sb800/pci_devs.h @@ -5,86 +5,88 @@ #include -#define BUS0 0 +#define BUS0 0 /* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -# define SATA_IDE_DEVID 0x4390 -# define AHCI_DEVID 0x4391 -# define RAID_DEVID 0x4392 -# define RAID5_DEVID 0x4393 -# define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x4390 +#define AHCI_DEVID 0x4391 +#define RAID_DEVID 0x4392 +#define RAID5_DEVID 0x4393 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -# define OHCI_DEVID 0x4397 -# define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -# define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -# define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -# define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x4397 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -# define EHCI_DEVID 0x4396 -# define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -# define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -# define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) - -/* IDE */ -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -# define IDE_DEVID 0x439C -# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -# define HDA_DEVID 0x4383 -# define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) - -/* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -# define SB_PCI_PORT_DEVID 0x4384 -# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) - -/* PCIe Ports */ -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -# define SB_PCIE_PORT1_DEVID 0x43A0 -# define SB_PCIE_PORT2_DEVID 0x43A1 -# define SB_PCIE_PORT3_DEVID 0x43A2 -# define SB_PCIE_PORT4_DEVID 0x43A3 -# define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -# define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -# define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -# define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x16 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x4396 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* Fusion Controller Hub */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -# define LPC_DEVID 0x439D -# define SMBUS_DEVID 0x4385 -# define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x4385 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) + +/* IDE */ +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +#define IDE_DEVID 0x439C +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) + +/* HD Audio */ +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x4383 +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV +#define LPC_FUNC 3 +#define LPC_DEVID 0x439D +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) + +/* PCI Ports */ +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +#define SB_PCI_PORT_DEVID 0x4384 +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) + +/* PCIe Ports */ +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x43A0 +#define SB_PCIE_PORT2_DEVID 0x43A1 +#define SB_PCIE_PORT3_DEVID 0x43A2 +#define SB_PCIE_PORT4_DEVID 0x43A3 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif /* _CIMX_SB800_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 7c29380e18..5dece330f9 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -3,18 +3,20 @@ #ifndef _PI_HUDSON_PCI_DEVS_H_ #define _PI_HUDSON_PCI_DEVS_H_ +#include + #define BUS0 0 /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 #define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define XHCI2_DEV 0x10 #define XHCI2_FUNC 1 #define XHCI2_DEVID 0x7814 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -22,7 +24,7 @@ #define SATA_IDE_DEVID 0x7800 #define AHCI_DEVID_MS 0x7801 #define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) /* OHCI */ #define OHCI1_DEV 0x12 @@ -34,10 +36,10 @@ #define OHCI4_DEV 0x14 #define OHCI4_FUNC 5 #define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) /* EHCI */ #define EHCI1_DEV 0x12 @@ -47,48 +49,48 @@ #define EHCI3_DEV 0x16 #define EHCI3_FUNC 2 #define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 #define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) /* IDE */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) #define IDE_DEV 0x14 #define IDE_FUNC 1 #define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) #endif /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 #define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) +#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_DEV PCU_DEV #define LPC_FUNC 3 #define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) +#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) /* PCI Ports */ #define SB_PCI_PORT_DEV 0x14 #define SB_PCI_PORT_FUNC 4 #define SB_PCI_PORT_DEVID 0x780F -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) +#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 #define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) /* PCIe Ports */ #if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) @@ -101,10 +103,10 @@ #define SB_PCIE_PORT2_DEVID 0x7821 #define SB_PCIE_PORT3_DEVID 0x7822 #define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) #endif #endif /* _PI_HUDSON_PCI_DEVS_H_ */ From 8ae391d199016a83f11db8724bb8e780441afa3b Mon Sep 17 00:00:00 2001 From: Morgan Jang Date: Tue, 6 Oct 2020 16:26:17 +0800 Subject: [PATCH 309/354] arch/x86/smbios: Populate SMBIOS type 7 with cache information SMBIOS has a field to display the cache size, which is currently set to UNKNOWN unconditionally, multiply the cache size of L1 and L2 by the number of cores. TEST=Execute "dmidecode -t 7" to check if the cache information is correct for Deltalake platform Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04 Signed-off-by: Morgan Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068 Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 57 ++++++++++++++++++++++++++++++++++++++----- src/include/smbios.h | 11 +++++++++ 2 files changed, 62 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 2995eceb9d..19b6f5d989 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -478,6 +478,51 @@ unsigned int __weak smbios_processor_family(struct cpuid_result res) return (res.eax > 0) ? 0x0c : 0x6; } +unsigned int __weak smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; +} + +unsigned int __weak smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_UNKNOWN; +} + +unsigned int __weak smbios_cache_conf_operation_mode(u8 level) +{ + return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */ +} + +static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache) +{ + size_t max_logical_cpus_sharing_cache = 0; + size_t number_of_cpus_per_package = 0; + size_t max_logical_cpus_per_package = 0; + struct cpuid_result res; + + if (!cpu_have_cpuid()) + return 1; + + res = cpuid(1); + + max_logical_cpus_per_package = (res.ebx >> 16) & 0xff; + + max_logical_cpus_sharing_cache = ((res_deterministic_cache.eax >> 14) & 0xfff) + 1; + + /* Check if it's last level cache */ + if (max_logical_cpus_sharing_cache == max_logical_cpus_per_package) + return 1; + + if (cpuid_get_max_func() >= 0xb) { + res = cpuid_ext(0xb, 1); + number_of_cpus_per_package = res.ebx & 0xff; + } else { + number_of_cpus_per_package = max_logical_cpus_per_package; + } + + return number_of_cpus_per_package / max_logical_cpus_sharing_cache; +} + static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -662,7 +707,6 @@ static int smbios_write_type7(unsigned long *current, { struct smbios_type7 *t = (struct smbios_type7 *)*current; int len = sizeof(struct smbios_type7); - static unsigned int cnt = 0; char buf[8]; memset(t, 0, sizeof(struct smbios_type7)); @@ -670,13 +714,13 @@ static int smbios_write_type7(unsigned long *current, t->handle = handle; t->length = len - 2; - snprintf(buf, sizeof(buf), "CACHE%x", cnt++); + snprintf(buf, sizeof(buf), "CACHE%x", level); t->socket_designation = smbios_add_string(t->eos, buf); t->cache_configuration = SMBIOS_CACHE_CONF_LEVEL(level) | SMBIOS_CACHE_CONF_LOCATION(0) | /* Internal */ SMBIOS_CACHE_CONF_ENABLED(1) | /* Enabled */ - SMBIOS_CACHE_CONF_OPERATION_MODE(3); /* Unknown */ + SMBIOS_CACHE_CONF_OPERATION_MODE(smbios_cache_conf_operation_mode(level)); if (max_cache_size < (SMBIOS_CACHE_SIZE_MASK * KiB)) { t->max_cache_size = max_cache_size / KiB; @@ -716,7 +760,7 @@ static int smbios_write_type7(unsigned long *current, t->supported_sram_type = sram_type; t->current_sram_type = sram_type; t->cache_speed = 0; /* Unknown */ - t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->error_correction_type = smbios_cache_error_correction_type(level); t->system_cache_type = type; len = t->length + smbios_string_table_len(t->eos); @@ -811,7 +855,8 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; - const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets + * get_number_of_caches(res); if (!cache_type) /* No more caches in the system */ @@ -840,7 +885,7 @@ static int smbios_write_type7_cache_parameters(unsigned long *current, const int h = (*handle)++; update_max(len, *max_struct_size, smbios_write_type7(current, h, - level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, + level, smbios_cache_sram_type(), associativity, type, cache_size, cache_size)); if (type4) { diff --git a/src/include/smbios.h b/src/include/smbios.h index 8033d6ca98..6a19655b31 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -61,6 +61,10 @@ unsigned int smbios_processor_characteristics(void); struct cpuid_result; unsigned int smbios_processor_family(struct cpuid_result res); +unsigned int smbios_cache_error_correction_type(u8 level); +unsigned int smbios_cache_sram_type(void); +unsigned int smbios_cache_conf_operation_mode(u8 level); + /* Used by mainboard to add port information of type 8 */ struct port_information; int smbios_write_type8(unsigned long *current, int *handle, @@ -501,6 +505,13 @@ enum smbios_cache_associativity { #define SMBIOS_CACHE_SIZE2_UNIT_64KB (1UL << 31) #define SMBIOS_CACHE_SIZE2_MASK 0x7fffffff +/* define for cache operation mode */ + +#define SMBIOS_CACHE_OP_MODE_WRITE_THROUGH 0 +#define SMBIOS_CACHE_OP_MODE_WRITE_BACK 1 +#define SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS 2 +#define SMBIOS_CACHE_OP_MODE_UNKNOWN 3 + struct smbios_type7 { u8 type; u8 length; From ba4a4909a87eac31878513eb6ad9123c5d87704b Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 23 Sep 2020 15:36:30 -0600 Subject: [PATCH 310/354] sconfig: Split up sconfig-generated static.h Currently sconfig generates a `static.h` to accompany `static.c`. However, some payloads may decide they would like to consume the FW_CONFIG macros as well. The current state of `static.h` makes this impossible (relying on `device/device.h`). This patch splits up `static.h` into 3 files: `static.h, `static_devices.h`, and `static_fw_config.h`. `static.h` simply includes the other two `.h` files to ensure no changes are needed to other code. `static_devices.h` contains the extern'd definitions of the device names recently introduced to sconfig. `static_fw_config.h` contains the FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a payload which wishes to use FW_CONFIG. Also refactor the generation of all these output files, as the code was getting messy. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro --- Makefile.inc | 6 ++ util/sconfig/main.c | 131 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 110 insertions(+), 27 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 297f7b1a16..a6418b1327 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -611,6 +611,12 @@ SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) DEVICETREE_STATIC_H := $(obj)/static.h SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) +DEVICETREE_DEVICENAMES_H := $(obj)/static_devices.h +SCONFIG_OPTIONS += --output_d=$(DEVICETREE_DEVICENAMES_H) + +DEVICETREE_FWCONFIG_H := $(obj)/static_fw_config.h +SCONFIG_OPTIONS += --output_f=$(DEVICETREE_FWCONFIG_H) + $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index bff721548b..4f13293a98 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1,9 +1,11 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include /* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ +#include #include #include #include @@ -528,9 +530,6 @@ static void emit_fw_config(FILE *fil) if (!field) return; - fprintf(fil, "\n/* firmware configuration */\n"); - fprintf(fil, "#include \n"); - while (field) { struct fw_config_option *option = field->options; uint32_t mask; @@ -1094,7 +1093,8 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next /* Emit probe structures. */ if (ptr->probe && (emit_fw_config_probe(fil, ptr) < 0)) { - fclose(head); + if (head) + fclose(head); fclose(fil); exit(1); } @@ -1355,9 +1355,12 @@ static void usage(void) printf("usage: sconfig \n"); printf(" -c | --output_c : Path to output static.c file (required)\n"); printf(" -r | --output_h : Path to header static.h file (required)\n"); + printf(" -d | --output_d : Path to header static_devices.h file (required)\n"); + printf(" -f | --output_f : Path to header static_fw_config.h file (required)\n"); printf(" -m | --mainboard_devtree : Path to mainboard devicetree file (required)\n"); printf(" -o | --override_devtree : Path to override devicetree file (optional)\n"); printf(" -p | --chipset_devtree : Path to chipset/SOC devicetree file (optional)\n"); + exit(1); } @@ -1721,6 +1724,54 @@ static void parse_override_devicetree(const char *file, struct device *dev) override_devicetree(&base_root_bus, dev->bus); } +static void generate_outputh(FILE *f, const char *fw_conf_header, const char *device_header) +{ + fprintf(f, "#ifndef __STATIC_DEVICE_TREE_H\n"); + fprintf(f, "#define __STATIC_DEVICE_TREE_H\n\n"); + + fprintf(f, "#include <%s>\n", fw_conf_header); + fprintf(f, "#include <%s>\n\n", device_header); + + fprintf(f, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); +} + +static void generate_outputc(FILE *f, const char *static_header) +{ + fprintf(f, "#include \n"); + fprintf(f, "#include \n"); + fprintf(f, "#include \n"); + fprintf(f, "#include <%s>\n", static_header); + emit_chip_headers(f, chip_header.next); + fprintf(f, "\n#define STORAGE static __unused DEVTREE_CONST\n\n"); + + walk_device_tree(NULL, NULL, &base_root_dev, inherit_subsystem_ids); + fprintf(f, "\n/* pass 0 */\n"); + walk_device_tree(f, NULL, &base_root_dev, pass0); + walk_device_tree(NULL, NULL, &base_root_dev, update_references); + fprintf(f, "\n/* chip configs */\n"); + emit_chip_configs(f); + fprintf(f, "\n/* pass 1 */\n"); + walk_device_tree(f, NULL, &base_root_dev, pass1); +} + +static void generate_outputd(FILE *gen, FILE *dev) +{ + fprintf(dev, "#ifndef __STATIC_DEVICES_H\n"); + fprintf(dev, "#define __STATIC_DEVICES_H\n\n"); + fprintf(dev, "#include \n\n"); + fprintf(dev, "/* expose_device_names */\n"); + walk_device_tree(gen, dev, &base_root_dev, expose_device_names); + fprintf(dev, "\n#endif /* __STATIC_DEVICE_NAMES_H */\n"); +} + +static void generate_outputf(FILE *f) +{ + fprintf(f, "#ifndef __STATIC_FW_CONFIG_H\n"); + fprintf(f, "#define __STATIC_FW_CONFIG_H\n\n"); + emit_fw_config(f); + fprintf(f, "\n#endif /* __STATIC_FW_CONFIG_H */\n"); +} + int main(int argc, char **argv) { static const struct option long_options[] = { @@ -1729,6 +1780,8 @@ int main(int argc, char **argv) { "chipset_devtree", 1, NULL, 'p' }, { "output_c", 1, NULL, 'c' }, { "output_h", 1, NULL, 'r' }, + { "output_d", 1, NULL, 'd' }, + { "output_f", 1, NULL, 'f' }, { "help", 1, NULL, 'h' }, { } }; @@ -1737,9 +1790,11 @@ int main(int argc, char **argv) const char *chipset_devtree = NULL; const char *outputc = NULL; const char *outputh = NULL; + const char *outputd = NULL; + const char *outputf = NULL; int opt, option_index; - while ((opt = getopt_long(argc, argv, "m:o:p:c:r:h", long_options, + while ((opt = getopt_long(argc, argv, "m:o:p:c:r:d:f:h", long_options, &option_index)) != EOF) { switch (opt) { case 'm': @@ -1757,13 +1812,19 @@ int main(int argc, char **argv) case 'r': outputh = strdup(optarg); break; + case 'd': + outputd = strdup(optarg); + break; + case 'f': + outputf = strdup(optarg); + break; case 'h': default: usage(); } } - if (!base_devtree || !outputc || !outputh) + if (!base_devtree || !outputc || !outputh || !outputd || !outputf) usage(); if (chipset_devtree) { @@ -1793,33 +1854,49 @@ int main(int argc, char **argv) fclose(autogen); exit(1); } - fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); - fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); - fprintf(autohead, "#include \n\n"); - emit_fw_config(autohead); - fprintf(autogen, "#include \n"); - fprintf(autogen, "#include \n\n"); - fprintf(autogen, "#include \n"); - emit_chip_headers(autogen, chip_header.next); - fprintf(autogen, "\n#define STORAGE static __unused DEVTREE_CONST\n\n"); + FILE *autodev = fopen(outputd, "w"); + if (!autodev) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputd); + perror(NULL); + fclose(autogen); + fclose(autohead); + exit(1); + } - walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); - fprintf(autogen, "\n/* pass 0 */\n"); - walk_device_tree(autogen, autohead, &base_root_dev, pass0); - walk_device_tree(autogen, autohead, &base_root_dev, update_references); - fprintf(autogen, "\n/* chip configs */\n"); - emit_chip_configs(autogen); - fprintf(autogen, "\n/* pass 1 */\n"); - walk_device_tree(autogen, autohead, &base_root_dev, pass1); + FILE *autofwconf = fopen(outputf, "w"); + if (!autofwconf) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputf); + perror(NULL); + fclose(autogen); + fclose(autohead); + fclose(autodev); + exit(1); + } - /* Expose static devicenames to global namespace. */ - fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + char *f = strdup(outputf); + assert(f); + char *d = strdup(outputd); + assert(d); + char *h = strdup(outputh); + assert(h); + + const char *fw_conf_header = basename(f); + const char *device_header = basename(d); + const char *static_header = basename(h); + + generate_outputh(autohead, fw_conf_header, device_header); + generate_outputc(autogen, static_header); + generate_outputd(autogen, autodev); + generate_outputf(autofwconf); - fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); fclose(autohead); fclose(autogen); + fclose(autodev); + fclose(autofwconf); + free(f); + free(d); + free(h); return 0; } From 7c80de63287f0f0c61e2326da2b59509b9eef704 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 1 Oct 2020 13:00:00 -0600 Subject: [PATCH 311/354] ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h directly from the Chromium OS EC repo at SHA edd8b73e8, with the exception of changing the copyright header to SPDX format. Signed-off-by: Tim Wawrzynczak Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45937 Reviewed-by: Caveh Jalali Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec_commands.h | 172 ++++++++++++++++++++++++++- 1 file changed, 167 insertions(+), 5 deletions(-) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4e40c6dee5..241ec393c6 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -414,6 +414,7 @@ extern "C" { /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 + /* * This header file is used in coreboot both in C and ACPI code. The ACPI code * is pre-processed to handle constants but the ASL compiler is unable to @@ -1253,6 +1254,7 @@ struct ec_response_get_protocol_info { uint32_t flags; } __ec_align4; + /*****************************************************************************/ /* Get/Set miscellaneous values */ @@ -1662,6 +1664,7 @@ struct ec_params_flash_erase_v1 { /* Rollback information flash region protected now */ #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) + /** * struct ec_params_flash_protect - Parameters for the flash protect command. * @mask: Bits in flags to apply. @@ -1758,6 +1761,7 @@ struct ec_response_vbnvcontext { uint8_t block[EC_VBNV_BLOCK_SIZE]; } __ec_align4; + /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 @@ -1775,6 +1779,7 @@ struct ec_response_flash_spi_info { uint8_t sr1, sr2; } __ec_align1; + /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 @@ -1786,6 +1791,7 @@ struct ec_params_flash_select { uint8_t select; } __ec_align4; + /** * Request random numbers to be generated and returned. * Can be used to test the random number generator is truly random. @@ -2196,6 +2202,7 @@ struct ec_response_lightbar { struct lightbar_params_v0 get_params_v0; struct lightbar_params_v1 get_params_v1; + struct lightbar_params_v2_timing get_params_v2_timing; struct lightbar_params_v2_tap get_params_v2_tap; struct lightbar_params_v2_oscillation get_params_v2_osc; @@ -2819,6 +2826,7 @@ struct ec_params_motion_sense { uint16_t scale[3]; } sensor_scale; + /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -3287,6 +3295,7 @@ struct ec_response_thermal_get_threshold { uint16_t value; } __ec_align2; + /* The version 1 structs are visible. */ enum ec_temp_thresholds { EC_TEMP_THRESH_WARN = 0, @@ -3402,6 +3411,7 @@ struct ec_params_tmp006_set_calibration_v1 { float val[0]; } __ec_align4; + /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 @@ -3799,6 +3809,7 @@ struct ec_response_keyboard_factory_test { #define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 + #define EC_CMD_MKBP_WAKE_MASK 0x0069 enum ec_mkbp_event_mask_action { /* Retrieve the value of a wake mask. */ @@ -3876,6 +3887,7 @@ struct ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ + /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host @@ -3905,6 +3917,10 @@ struct ec_response_host_event_mask { /* * Unified host event programming interface - Should be used by newer versions * of BIOS/OS to program host events and masks + * + * EC returns: + * - EC_RES_INVALID_PARAM: Action or mask type is unknown. + * - EC_RES_ACCESS_DENIED: Action is prohibited for specified mask type. */ struct ec_params_host_event { @@ -4473,6 +4489,7 @@ struct ec_response_charge_state { }; } __ec_align4; + /* * Set maximum battery charging current. */ @@ -4801,6 +4818,7 @@ struct ec_response_i2c_passthru_protect { uint8_t status; /* Status flags (0: unlocked, 1: locked) */ } __ec_align1; + /*****************************************************************************/ /* * HDMI CEC commands @@ -5273,15 +5291,23 @@ struct ec_response_pd_status { #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE BIT(0) -#define PD_EVENT_POWER_CHANGE BIT(1) -#define PD_EVENT_IDENTITY_RECEIVED BIT(2) -#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) + struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ } __ec_align4; -/* Set USB type-C port role and muxes */ +/* + * Set USB type-C port role and muxes + * + * Deprecated in favor of TYPEC_STATUS and TYPEC_CONTROL commands. + * + * TODO(b/169771803): TCPMv2: Remove EC_CMD_USB_PD_CONTROL + */ #define EC_CMD_USB_PD_CONTROL 0x0101 enum usb_pd_control_role { @@ -6334,6 +6360,142 @@ struct ec_response_typec_discovery { struct svid_mode_info svids[0]; } __ec_align1; +/* USB Type-C commands for AP-controlled device policy. */ +#define EC_CMD_TYPEC_CONTROL 0x0132 + +enum typec_control_command { + TYPEC_CONTROL_COMMAND_EXIT_MODES, + TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, +}; + +struct ec_params_typec_control { + uint8_t port; + uint8_t command; /* enum typec_control_command */ + uint16_t reserved; + + /* + * This section will be interpreted based on |command|. Define a + * placeholder structure to avoid having to increase the size and bump + * the command version when adding new sub-commands. + */ + union { + uint32_t clear_events_mask; + uint8_t placeholder[128]; + }; +} __ec_align1; + +/* + * Gather all status information for a port. + * + * Note: this covers many of the return fields from the deprecated + * EC_CMD_USB_PD_CONTROL command, except those that are redundant with the + * discovery data. The "enum pd_cc_states" is defined with the deprecated + * EC_CMD_USB_PD_CONTROL command. + * + * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. + * + * Version 0 of command is under development + * TODO(b/167700356): Remove this statement when version 0 is finalized + */ +#define EC_CMD_TYPEC_STATUS 0x0133 + +/* + * Power role. + * + * Note this is also used for PD header creation, and values align to those in + * the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.4 Port Power Role). + */ +enum pd_power_role { + PD_ROLE_SINK = 0, + PD_ROLE_SOURCE = 1 +}; + +/* + * Data role. + * + * Note this is also used for PD header creation, and the first two values + * align to those in the Power Delivery Specification Revision 3.0 (See + * 6.2.1.1.6 Port Data Role). + */ +enum pd_data_role { + PD_ROLE_UFP = 0, + PD_ROLE_DFP = 1, + PD_ROLE_DISCONNECTED = 2, +}; + +enum pd_vconn_role { + PD_ROLE_VCONN_OFF = 0, + PD_ROLE_VCONN_SRC = 1, +}; + +/* + * Note: BIT(0) may be used to determine whether the polarity is CC1 or CC2, + * regardless of whether a debug accessory is connected. + */ +enum tcpc_cc_polarity { + /* + * _CCx: is used to indicate the polarity while not connected to + * a Debug Accessory. Only one CC line will assert a resistor and + * the other will be open. + */ + POLARITY_CC1 = 0, + POLARITY_CC2 = 1, + + /* + * _CCx_DTS is used to indicate the polarity while connected to a + * SRC Debug Accessory. Assert resistors on both lines. + */ + POLARITY_CC1_DTS = 2, + POLARITY_CC2_DTS = 3, + + /* + * The current TCPC code relies on these specific POLARITY values. + * Adding in a check to verify if the list grows for any reason + * that this will give a hint that other places need to be + * adjusted. + */ + POLARITY_COUNT +}; + +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) + +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) + +struct ec_params_typec_status { + uint8_t port; +} __ec_align1; + +struct ec_response_typec_status { + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t reserved1; /* Reserved for future use */ + + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t reserved2; /* Reserved for future use */ + + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded USB mux state */ + + char tc_state[32]; /* TC state name */ + + uint32_t events; /* PD_STATUS_EVENT bitmask */ + + /* TODO(b/167700356): Add revisions and source cap PDOs */ +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ From b11b731e80344a6460fb36010bb3785fd0ab59ca Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 22 Oct 2020 00:23:32 -0600 Subject: [PATCH 312/354] Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration" This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc. CB:45857 overrides the GPIO PM configuration if Cr50 does not support long interrupt pulse width. More recent Cr50 Firmware versions support long pulse width and hence the GPIO PM can take the default configuration. BUG=None TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of suspend/resume sequence, warm and cold reboot cycles each are successful. Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Reviewed-by: Evan Green --- .../google/dedede/acpi/mainboard.asl | 45 ------------------- src/mainboard/google/dedede/dsdt.asl | 7 --- 2 files changed, 52 deletions(-) delete mode 100644 src/mainboard/google/dedede/acpi/mainboard.asl diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl deleted file mode 100644 index 0fa27da0a5..0000000000 --- a/src/mainboard/google/dedede/acpi/mainboard.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -Method (PGPM, 1, Serialized) -{ - For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++) - { - \_SB.PCI0.CGPM (Local0, Arg0) - } -} - -/* - * Method called from _PTS prior to system sleep state entry - * Enables dynamic clock gating for all 5 GPIO communities - */ -Method (MPTS, 1, Serialized) -{ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) -} - -/* - * Method called from _WAK prior to system sleep state wakeup - * Disables dynamic clock gating for all 5 GPIO communities - */ -Method (MWAK, 1, Serialized) -{ - PGPM (0) -} - -/* - * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - PGPM (0) - } -} diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 1698c881f1..39cc25e156 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -27,9 +27,6 @@ DefinitionBlock( #include #include } - - /* Mainboard hooks */ - #include "acpi/mainboard.asl" } #if CONFIG(VARIANT_HAS_CAMERA_ACPI) @@ -37,10 +34,6 @@ DefinitionBlock( #include #endif - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include - /* Chrome OS specific */ #include From 468c46df25612e1928f632a78d26fcbb74ad4281 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 22 Oct 2020 00:36:16 -0600 Subject: [PATCH 313/354] Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration" This reverts commit 5acea15d63e821a1bc416d206162ed030cd5d57c. This change got accidentally merged. There is no need for mainboard to override chip configuration. BUG=None TEST=Build and boot Drawlat to OS. Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/soc/intel/jasperlake/fsp_params.c | 8 -------- src/soc/intel/jasperlake/include/soc/ramstage.h | 1 - 2 files changed, 9 deletions(-) diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index cb0070a879..db27234067 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -78,11 +78,6 @@ static void parse_devicetree(FSP_S_CONFIG *params) sizeof(config->SerialIoUartMode)); } -__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config) -{ - /* Override settings per board. */ -} - /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -91,9 +86,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_jasperlake_config *config = config_of_soc(); - /* Allow mainboard to override any chip config */ - mainboard_update_soc_chip_config(config); - /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h index 1de8e37758..8188fbdb84 100644 --- a/src/soc/intel/jasperlake/include/soc/ramstage.h +++ b/src/soc/intel/jasperlake/include/soc/ramstage.h @@ -9,7 +9,6 @@ #include void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config); void soc_init_pre_device(void *chip_info); #endif From 05fa5b2450df748e813251a7c93f89cb2c6c6b6c Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 23 Oct 2020 13:11:36 +0200 Subject: [PATCH 314/354] tests: Add test region and symbol macros to Some modules require and operate on memory regions and symbols. This macros systematize how they are defined in testing code. Signed-off-by: Jakub Czapiga Change-Id: I314028c201732416bb3d5446a4c8585e055073e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46684 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons Reviewed-by: Paul Fagerburg --- tests/include/tests/test.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tests/include/tests/test.h b/tests/include/tests/test.h index 4dc9988fde..ceb965462e 100644 --- a/tests/include/tests/test.h +++ b/tests/include/tests/test.h @@ -14,4 +14,18 @@ #include #include +/* + * Set symbol value and make it global. + */ +#define TEST_SYMBOL(symbol, address) asm(".set " #symbol ", " #address "\n\t.globl " #symbol) + +/* + * Define memory region for testing purpose. + * + * Create buffer with specified name and size. + * Create end symbol for it. + */ +#define TEST_REGION(region, size) uint8_t _##region[size]; \ + TEST_SYMBOL(_e##region, _##region + size) + #endif /* _TESTS_TEST_H */ From 466a378b9a6e5cc4dd5f90cc158b39842098639d Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Mon, 5 Oct 2020 10:44:46 +0200 Subject: [PATCH 315/354] tests: Add lib/imd-test test case Implement unit tests for src/lib/imd.c module. Signed-off-by: Jakub Czapiga Signed-off-by: Anna Karas Signed-off-by: Jan Dabros Change-Id: I3902f8638669440144064ce0e3756918338f4068 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46457 Reviewed-by: Angel Pons Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- tests/lib/Makefile.inc | 5 + tests/lib/imd-test.c | 763 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 768 insertions(+) create mode 100644 tests/lib/imd-test.c diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index b66d386787..3062bcaa70 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -3,6 +3,7 @@ tests-y += string-test tests-y += b64_decode-test tests-y += hexstrtobin-test +tests-y += imd-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -13,3 +14,7 @@ b64_decode-test-srcs += src/lib/b64_decode.c hexstrtobin-test-srcs += tests/lib/hexstrtobin-test.c hexstrtobin-test-srcs += src/lib/hexstrtobin.c + +imd-test-srcs += tests/lib/imd-test.c +imd-test-srcs += tests/stubs/console.c +imd-test-srcs += src/lib/imd.c \ No newline at end of file diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c new file mode 100644 index 0000000000..dce542cf8f --- /dev/null +++ b/tests/lib/imd-test.c @@ -0,0 +1,763 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Auxiliary functions and definitions. */ + +#define LG_ROOT_SIZE align_up_pow2(sizeof(struct imd_root_pointer) +\ + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)) +#define LG_ENTRY_ALIGN (2 * sizeof(int32_t)) +#define LG_ENTRY_SIZE (2 * sizeof(int32_t)) +#define LG_ENTRY_ID 0xA001 + +#define SM_ROOT_SIZE LG_ROOT_SIZE +#define SM_ENTRY_ALIGN sizeof(uint32_t) +#define SM_ENTRY_SIZE sizeof(uint32_t) +#define SM_ENTRY_ID 0xB001 + +#define INVALID_REGION_ID 0xC001 + +static uint32_t align_up_pow2(uint32_t x) +{ + return (1 << log2_ceil(x)); +} + +static size_t max_entries(size_t root_size) +{ + return (root_size - sizeof(struct imd_root_pointer) - sizeof(struct imd_root)) + / sizeof(struct imd_entry); +} + +/* + * Mainly, we should check that imd_handle_init() aligns upper_limit properly + * for various inputs. Upper limit is the _exclusive_ address, so we expect + * ALIGN_DOWN. + */ +static void test_imd_handle_init(void **state) +{ + int i; + void *base; + struct imd imd; + uintptr_t test_inputs[] = { + 0, /* Lowest possible address */ + 0xA000, /* Fits in 16 bits, should not get rounded down*/ + 0xDEAA, /* Fits in 16 bits */ + 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ + 0xF0F0F0F0, /* Fits in 32 bits */ + ((1ULL << 32) + 4), /* Just above 32-bit limit */ + 0x6666777788889000, /* Fits in 64 bits, should not get rounded down */ + ((1ULL << 60) - 100) /* Very large address, fitting in 64 bits */ + }; + + for (i = 0; i < ARRAY_SIZE(test_inputs); i++) { + base = (void *)test_inputs[i]; + + imd_handle_init(&imd, (void *)base); + + assert_int_equal(imd.lg.limit % LIMIT_ALIGN, 0); + assert_int_equal(imd.lg.limit, ALIGN_DOWN(test_inputs[i], LIMIT_ALIGN)); + assert_ptr_equal(imd.lg.r, NULL); + + /* Small allocations not initialized */ + assert_ptr_equal(imd.sm.limit, NULL); + assert_ptr_equal(imd.sm.r, NULL); + } +} + +static void test_imd_handle_init_partial_recovery(void **state) +{ + void *base; + struct imd imd = {0}; + const struct imd_entry *entry; + + imd_handle_init_partial_recovery(&imd); + assert_null(imd.lg.limit); + assert_null(imd.sm.limit); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_null(imd.sm.limit); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_add(&imd, SMALL_REGION_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_non_null(imd.sm.limit); + assert_ptr_equal(imd.lg.r + entry->start_offset + LG_ENTRY_SIZE, imd.sm.limit); + assert_non_null(imd.sm.r); + + free(base); +} + +static void test_imd_create_empty(void **state) +{ + struct imd imd = {0}; + void *base; + struct imd_root *r; + struct imd_entry *e; + + /* Expect imd_create_empty to fail, since imd handle is not initialized */ + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + base = malloc(sizeof(struct imd_root_pointer) + sizeof(struct imd_root)); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Try incorrect sizes */ + assert_int_equal(-1, imd_create_empty(&imd, + sizeof(struct imd_root_pointer), + LG_ENTRY_ALIGN)); + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, 2 * LG_ROOT_SIZE)); + + /* Working case */ + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Only large allocation initialized with one entry for the root region */ + r = (struct imd_root *) (imd.lg.r); + assert_non_null(r); + + e = &r->entries[r->num_entries - 1]; + + assert_int_equal(max_entries(LG_ROOT_SIZE), r->max_entries); + assert_int_equal(1, r->num_entries); + assert_int_equal(0, r->flags); + assert_int_equal(LG_ENTRY_ALIGN, r->entry_align); + assert_int_equal(0, r->max_offset); + assert_ptr_equal(e, &r->entries); + + assert_int_equal(IMD_ENTRY_MAGIC, e->magic); + assert_int_equal(0, e->start_offset); + assert_int_equal(LG_ROOT_SIZE, e->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, e->id); + + free(base); +} + +static void test_imd_create_tiered_empty(void **state) +{ + void *base; + size_t sm_region_size, lg_region_wrong_size; + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *sm_entry; + + /* Uninitialized imd handle */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + LG_ROOT_SIZE, SM_ENTRY_ALIGN)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Too small root_size for small region */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + sizeof(int32_t), 2 * sizeof(int32_t))); + + /* Fail when large region doesn't have capacity for more than 1 entry */ + lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + sizeof(struct imd_entry); + assert_int_equal(-1, imd_create_tiered_empty(&imd, lg_region_wrong_size, + LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + + /* One entry for root_region and one for small allocations */ + assert_int_equal(2, r->num_entries); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, fst_lg_entry->magic); + assert_int_equal(0, fst_lg_entry->start_offset); + assert_int_equal(LG_ROOT_SIZE, fst_lg_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, fst_lg_entry->id); + + /* Calculated like in imd_create_tiered_empty */ + sm_region_size = max_entries(SM_ROOT_SIZE) * SM_ENTRY_ALIGN; + sm_region_size += SM_ROOT_SIZE; + sm_region_size = ALIGN_UP(sm_region_size, LG_ENTRY_ALIGN); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(IMD_ENTRY_MAGIC, snd_lg_entry->magic); + assert_int_equal(-sm_region_size, snd_lg_entry->start_offset); + assert_int_equal(CBMEM_ID_IMD_SMALL, snd_lg_entry->id); + + assert_int_equal(sm_region_size, snd_lg_entry->size); + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + + sm_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, sm_entry->magic); + assert_int_equal(0, sm_entry->start_offset); + assert_int_equal(SM_ROOT_SIZE, sm_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, sm_entry->id); + + free(base); +} + +/* Tests for imdr_recover. */ +static void test_imd_recover(void **state) +{ + int32_t offset_copy, max_offset_copy; + uint32_t rp_magic_copy, num_entries_copy; + uint32_t e_align_copy, e_magic_copy, e_id_copy; + uint32_t size_copy, diff; + void *base; + struct imd imd = {0}; + struct imd_root_pointer *rp; + struct imd_root *r; + struct imd_entry *lg_root_entry, *sm_root_entry, *ptr; + const struct imd_entry *lg_entry; + + /* Fail when the limit for lg was not set. */ + imd.lg.limit = (uintptr_t) NULL; + assert_int_equal(-1, imd_recover(&imd)); + + /* Set the limit for lg. */ + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Fail when the root pointer is not valid. */ + rp = (void *)imd.lg.limit - sizeof(struct imd_root_pointer); + assert_non_null(rp); + assert_int_equal(IMD_ROOT_PTR_MAGIC, rp->magic); + + rp_magic_copy = rp->magic; + rp->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + rp->magic = rp_magic_copy; + + /* Set the root pointer. */ + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + assert_int_equal(2, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); + + /* Fail if the number of entries exceeds the maximum number of entries. */ + r = imd.lg.r; + num_entries_copy = r->num_entries; + r->num_entries = r->max_entries + 1; + assert_int_equal(-1, imd_recover(&imd)); + r->num_entries = num_entries_copy; + + /* Fail if entry align is not a power of 2. */ + e_align_copy = r->entry_align; + r->entry_align++; + assert_int_equal(-1, imd_recover(&imd)); + r->entry_align = e_align_copy; + + /* Fail when an entry is not valid. */ + lg_root_entry = &r->entries[0]; + e_magic_copy = lg_root_entry->magic; + lg_root_entry->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + lg_root_entry->magic = e_magic_copy; + + /* Add new entries: large and small. */ + lg_entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(lg_entry); + assert_int_equal(3, r->num_entries); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(2, ((struct imd_root *)imd.sm.r)->num_entries); + + /* Fail when start_addr is lower than low_limit. */ + r = imd.lg.r; + max_offset_copy = r->max_offset; + r->max_offset = lg_entry->start_offset + sizeof(int32_t); + assert_int_equal(-1, imd_recover(&imd)); + r->max_offset = max_offset_copy; + + /* Fail when start_addr is at least imdr->limit. */ + offset_copy = lg_entry->start_offset; + ptr = (struct imd_entry *)lg_entry; + ptr->start_offset = (void *)imd.lg.limit - (void *)r; + assert_int_equal(-1, imd_recover(&imd)); + ptr->start_offset = offset_copy; + + /* Fail when (start_addr + e->size) is higher than imdr->limit. */ + size_copy = lg_entry->size; + diff = (void *)imd.lg.limit - ((void *)r + lg_entry->start_offset); + ptr->size = diff + 1; + assert_int_equal(-1, imd_recover(&imd)); + ptr->size = size_copy; + + /* Succeed if small region is not present. */ + sm_root_entry = &r->entries[1]; + e_id_copy = sm_root_entry->id; + sm_root_entry->id = 0; + assert_int_equal(0, imd_recover(&imd)); + sm_root_entry->id = e_id_copy; + + assert_int_equal(0, imd_recover(&imd)); + + free(base); +} + +static void test_imd_limit_size(void **state) +{ + void *base; + struct imd imd = {0}; + size_t root_size, max_size; + + max_size = align_up_pow2(sizeof(struct imd_root_pointer) + + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)); + + assert_int_equal(-1, imd_limit_size(&imd, max_size)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + root_size = align_up_pow2(sizeof(struct imd_root_pointer) + + sizeof(struct imd_root) + 2 * sizeof(struct imd_entry)); + imd.lg.r = (void *)imd.lg.limit - root_size; + + imd_create_empty(&imd, root_size, LG_ENTRY_ALIGN); + assert_int_equal(-1, imd_limit_size(&imd, root_size - 1)); + assert_int_equal(0, imd_limit_size(&imd, max_size)); + + /* Cannot create such a big entry */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, max_size - root_size + 1)); + + free(base); +} + +static void test_imd_lockdown(void **state) +{ + struct imd imd = {0}; + struct imd_root *r_lg, *r_sm; + + assert_int_equal(-1, imd_lockdown(&imd)); + + imd.lg.r = malloc(sizeof(struct imd_root)); + if (imd.lg.r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + r_lg = (struct imd_root *) (imd.lg.r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_lg->flags & IMD_FLAG_LOCKED); + + imd.sm.r = malloc(sizeof(struct imd_root)); + if (imd.sm.r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + r_sm = (struct imd_root *) (imd.sm.r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_sm->flags & IMD_FLAG_LOCKED); + + free(imd.lg.r); + free(imd.sm.r); +} + +static void test_imd_region_used(void **state) +{ + struct imd imd = {0}; + struct imd_entry *first_entry, *new_entry; + struct imd_root *r; + size_t size; + void *imd_base; + void *base; + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + + imd_base = malloc(LIMIT_ALIGN); + if (imd_base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)imd_base)); + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + r = (struct imd_root *)imd.lg.r; + first_entry = &r->entries[r->num_entries - 1]; + + assert_int_equal(r + first_entry->start_offset, (uintptr_t)base); + assert_int_equal(first_entry->size, size); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + new_entry = &r->entries[r->num_entries - 1]; + + assert_true((void *)r + new_entry->start_offset == base); + assert_int_equal(first_entry->size + new_entry->size, size); + + free(imd_base); +} + +static void test_imd_entry_add(void **state) +{ + int i; + struct imd imd = {0}; + size_t entry_size = 0; + size_t used_size; + ssize_t entry_offset; + void *base; + struct imd_root *r, *sm_r, *lg_r; + struct imd_entry *first_entry, *new_entry; + uint32_t num_entries_copy; + int32_t max_offset_copy; + + /* No small region case. */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + r = (struct imd_root *)imd.lg.r; + first_entry = &r->entries[r->num_entries - 1]; + + /* Cannot add an entry when root is locked. */ + r->flags = IMD_FLAG_LOCKED; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->flags = 0; + + /* Fail when the maximum number of entries has been reached. */ + num_entries_copy = r->num_entries; + r->num_entries = r->max_entries; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->num_entries = num_entries_copy; + + /* Fail when entry size is 0 */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, 0)); + + /* Fail when entry size (after alignment) overflows imd total size. */ + entry_size = 2049; + max_offset_copy = r->max_offset; + r->max_offset = -entry_size; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->max_offset = max_offset_copy; + + /* Finally succeed. */ + entry_size = 2 * sizeof(int32_t); + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + assert_int_equal(2, r->num_entries); + + new_entry = &r->entries[r->num_entries - 1]; + assert_int_equal(sizeof(struct imd_entry), (void *)new_entry - (void *)first_entry); + + assert_int_equal(IMD_ENTRY_MAGIC, new_entry->magic); + assert_int_equal(LG_ENTRY_ID, new_entry->id); + assert_int_equal(entry_size, new_entry->size); + + used_size = ALIGN_UP(entry_size, r->entry_align); + entry_offset = first_entry->start_offset - used_size; + assert_int_equal(entry_offset, new_entry->start_offset); + + /* Use small region case. */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + lg_r = imd.lg.r; + sm_r = imd.sm.r; + + /* All five new entries should be added to small allocations */ + for (i = 0; i < 5; i++) { + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(i+2, sm_r->num_entries); + assert_int_equal(2, lg_r->num_entries); + } + + /* But next should fall back on large region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(6, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* + * Small allocation is created when occupies less than 1/4 of available + * small region. Verify this. + */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4 + 1)); + assert_int_equal(1, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* Next two should go into small region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4)); + assert_int_equal(2, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* (1/4 * 3/4) */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 16 * 3)); + assert_int_equal(3, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + free(base); +} + +static void test_imd_entry_find(void **state) +{ + struct imd imd = {0}; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_non_null(imd_entry_find(&imd, LG_ENTRY_ID)); + assert_non_null(imd_entry_find(&imd, SMALL_REGION_ID)); + + /* Try invalid id, should fail */ + assert_null(imd_entry_find(&imd, INVALID_REGION_ID)); + + free(base); +} + +static void test_imd_entry_find_or_add(void **state) +{ + struct imd imd = {0}; + const struct imd_entry *entry; + struct imd_root *r; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *)imd.lg.r; + + assert_int_equal(entry->id, LG_ENTRY_ID); + assert_int_equal(2, r->num_entries); + assert_non_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + free(base); +} + +static void test_imd_entry_size(void **state) +{ + struct imd_entry entry = { .size = LG_ENTRY_SIZE }; + + assert_int_equal(LG_ENTRY_SIZE, imd_entry_size(&entry)); + + entry.size = 0; + assert_int_equal(0, imd_entry_size(&entry)); +} + +static void test_imd_entry_at(void **state) +{ + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *e = NULL; + const struct imd_entry *entry; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Fail when entry is NULL */ + assert_null(imd_entry_at(&imd, e)); + + entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *)imd.lg.r; + assert_ptr_equal((void *)r + entry->start_offset, imd_entry_at(&imd, entry)); + + free(base); +} + +static void test_imd_entry_id(void **state) +{ + struct imd_entry entry = { .id = LG_ENTRY_ID }; + + assert_int_equal(LG_ENTRY_ID, imd_entry_id(&entry)); +} + +static void test_imd_entry_remove(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_root *r; + const struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + const struct imd_entry *e = NULL; + + /* Uninitialized handle */ + assert_int_equal(-1, imd_entry_remove(&imd, e)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + assert_int_equal(2, r->num_entries); + fst_lg_entry = &r->entries[0]; + snd_lg_entry = &r->entries[1]; + + /* Only last entry can be removed */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + r->flags = IMD_FLAG_LOCKED; + assert_int_equal(-1, imd_entry_remove(&imd, snd_lg_entry)); + r->flags = 0; + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + fst_sm_entry = &r->entries[0]; + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_sm_entry)); + assert_int_equal(1, r->num_entries); + + r = imd.lg.r; + assert_int_equal(0, imd_entry_remove(&imd, snd_lg_entry)); + assert_int_equal(1, r->num_entries); + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + assert_int_equal(1, r->num_entries); + + free(base); +} + +static void test_imd_cursor_init(void **state) +{ + struct imd imd = {0}; + struct imd_cursor cursor; + + assert_int_equal(-1, imd_cursor_init(NULL, NULL)); + assert_int_equal(-1, imd_cursor_init(NULL, &cursor)); + assert_int_equal(-1, imd_cursor_init(&imd, NULL)); + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + assert_ptr_equal(cursor.imdr[0], &imd.lg); + assert_ptr_equal(cursor.imdr[1], &imd.sm); +} + +static void test_imd_cursor_next(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_cursor cursor; + struct imd_root *r; + const struct imd_entry *entry; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + cursor.current_imdr = 3; + cursor.current_entry = 0; + assert_null(imd_cursor_next(&cursor)); + + cursor.current_imdr = 0; + assert_null(imd_cursor_next(&cursor)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(fst_lg_entry->id, entry->id); + assert_ptr_equal(fst_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(snd_lg_entry->id, entry->id); + assert_ptr_equal(snd_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + r = imd.sm.r; + fst_sm_entry = &r->entries[0]; + assert_int_equal(fst_sm_entry->id, entry->id); + assert_ptr_equal(fst_sm_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_null(entry); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_imd_handle_init), + cmocka_unit_test(test_imd_handle_init_partial_recovery), + cmocka_unit_test(test_imd_create_empty), + cmocka_unit_test(test_imd_create_tiered_empty), + cmocka_unit_test(test_imd_recover), + cmocka_unit_test(test_imd_limit_size), + cmocka_unit_test(test_imd_lockdown), + cmocka_unit_test(test_imd_region_used), + cmocka_unit_test(test_imd_entry_add), + cmocka_unit_test(test_imd_entry_find), + cmocka_unit_test(test_imd_entry_find_or_add), + cmocka_unit_test(test_imd_entry_size), + cmocka_unit_test(test_imd_entry_at), + cmocka_unit_test(test_imd_entry_id), + cmocka_unit_test(test_imd_entry_remove), + cmocka_unit_test(test_imd_cursor_init), + cmocka_unit_test(test_imd_cursor_next), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + From 28b68ae4fe69bb4bb43b205cb6aa1fd1caa35e32 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 24 Sep 2020 20:18:26 +0200 Subject: [PATCH 316/354] soc/amd/picasso/acpi: Convert to ASL 2.0 syntax Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/amd/picasso/acpi/cpu.asl | 6 +++--- src/soc/amd/picasso/acpi/pci_int.asl | 2 +- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 18 +++++++++--------- src/soc/amd/picasso/acpi/sleepstates.asl | 12 ++++++------ 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index eb646dec1e..e1b7498f09 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -48,7 +48,7 @@ External (\_SB.C007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 8)) { + If (\PCNT >= 8) { Return (Package () { \_SB.C000, @@ -60,7 +60,7 @@ Method (PPKG) \_SB.C006, \_SB.C007 }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { + } ElseIf (\PCNT >= 4) { Return (Package () { \_SB.C000, @@ -68,7 +68,7 @@ Method (PPKG) \_SB.C002, \_SB.C003 }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { + } ElseIf (\PCNT >= 2) { Return (Package () { \_SB.C000, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 2a2a561c8f..8114c52043 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -3,7 +3,7 @@ Method(\_PIC, 0x01, NotSerialized) { printf("PIC MODE: %o", Arg0) - Store(Arg0, PMOD) + PMOD = Arg0 } /* PIC Possible Resource Values */ diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 9208e136f7..f627a28039 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -9,14 +9,14 @@ External(\_SB.ALIB, MethodObj) Method(_OSC,4) { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) } Else { CreateDWordField(Arg3,0,CDW1) - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) } } @@ -78,15 +78,15 @@ Method(_CRS, 0) { * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) - Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) + BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index 88c6efc960..03d28bb4f8 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -3,25 +3,25 @@ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) If (CONFIG(HAVE_ACPI_RESUME)) { - Store(0x0D, SSFG) + SSFG = 0x0D } If (CONFIG(DISABLE_ACPI_HIBERNATE)) { - Store(And(SSFG, 0xF7), SSFG) + SSFG &= 0xF7 } /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -If (And(SSFG, 0x01)) { +If (SSFG & 0x01) { Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ } -If (And(SSFG, 0x02)) { +If (SSFG & 0x02) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } -If (And(SSFG, 0x04)) { +If (SSFG & 0x04) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } -If (And(SSFG, 0x08)) { +If (SSFG & 0x08) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ } From 91893ee7857fde783150ea14e376fb63d159aa4d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 23 Oct 2020 01:40:41 +0000 Subject: [PATCH 317/354] inteltool: initial Hewitt Lake support Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5 Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/inteltool/inteltool.c | 2 ++ util/inteltool/inteltool.h | 1 + 2 files changed, 3 insertions(+) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 91a8b7e025..aadd0fb3c4 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -140,6 +140,8 @@ static const struct { "10th generation (Comet Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3, "10th generation (Comet Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE, + "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index e7d32a3b25..77ad61f410 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -298,6 +298,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ +#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */ /* Intel GPUs */ From f3b1a53858299fd29f442b597212aecf75f84cbe Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 23 Oct 2020 01:42:25 +0000 Subject: [PATCH 318/354] inteltool: Only use real graphics devices Right now IGD is hard coded to 0:2.0 and if that device is there, it is blindly used, even if it is not a graphics device. Look at the PCI class to make sure we're not using the wrong device. Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8 Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/inteltool/inteltool.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index aadd0fb3c4..3fb7707a2a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -773,13 +773,13 @@ int main(int argc, char *argv[]) } gfx = pci_get_dev(pacc, 0, 0, 0x02, 0); - if (gfx) { pci_fill_info(gfx, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS); - - if (gfx->vendor_id != PCI_VENDOR_ID_INTEL) - gfx = 0; + if ((gfx->device_class & 0xff00) != 0x0300) + gfx = NULL; + else if (gfx->vendor_id != PCI_VENDOR_ID_INTEL) + gfx = NULL; } if (sb->device_id == PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC) { From 9d50efe19dad26eba3285c3295b804490b81b0e7 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 22 Oct 2020 22:10:12 +0000 Subject: [PATCH 319/354] ectool: Add newline to warning message Cosmetic fix: $ sudo ./ectool -p Cannot get EC ports from /proc/ioports, fallback to default.EC RAM: Change-Id: Icc2b5bbbbfe7685e4fe512af029ce00b33a26daa Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46666 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Angel Pons --- util/ectool/ectool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index 0b238c4bb7..cb6f280f4c 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -127,7 +127,7 @@ int main(int argc, char *argv[]) if (get_ports && get_ec_ports() != 0) fprintf(stderr, "Cannot get EC ports from /proc/ioports, " - "fallback to default."); + "fallback to default.\n"); if (iopl(3)) { printf("You need to be root.\n"); From 3a7825983c506d5a521862bfa5700a87c525227d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 22 Oct 2020 22:16:20 +0000 Subject: [PATCH 320/354] ectool: Don't ignore fgets return code Change-Id: I12dc449e06dee31b4b0811ab23c6e8635cf31512 Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46667 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/ectool/ec.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/ectool/ec.c b/util/ectool/ec.c index f30d12f976..a189a094b5 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -167,7 +167,10 @@ int get_ec_ports(void) return -1; while (!feof(fp) && (data == 0 || cmd == 0)) { - fgets(line, sizeof(line), fp); + if (fgets(line, sizeof(line), fp) == NULL) { + fprintf(stderr, "Can not read from /proc/ioports.\n"); + break; + } if (strstr(line, "EC data") != NULL) data = strtol(line, NULL, 16); From bfa46e25e013af461b940ecd79d8b27bedecbc14 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 24 Oct 2020 17:02:25 +0200 Subject: [PATCH 321/354] libpayload: Add Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/libpayload/include/stdbool.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 payloads/libpayload/include/stdbool.h diff --git a/payloads/libpayload/include/stdbool.h b/payloads/libpayload/include/stdbool.h new file mode 100644 index 0000000000..33858d51f2 --- /dev/null +++ b/payloads/libpayload/include/stdbool.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __STDBOOL_H +#define __STDBOOL_H + +#define bool _Bool +#define false 0 +#define true (!false) + +#endif From f56d65266c618ebc4e9254752f20dd73eea199f1 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 24 Oct 2020 17:39:59 +0200 Subject: [PATCH 322/354] libpayload/curses: Use Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- payloads/libpayload/curses/PDCurses/curses.h | 9 +-------- payloads/libpayload/curses/curses.h | 2 +- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/curses/PDCurses/curses.h b/payloads/libpayload/curses/PDCurses/curses.h index 5f651fef44..45245ae0b1 100644 --- a/payloads/libpayload/curses/PDCurses/curses.h +++ b/payloads/libpayload/curses/PDCurses/curses.h @@ -41,6 +41,7 @@ PDCurses portable platform definitions list: /*----------------------------------------------------------------------*/ #include +#include #include #include /* Required by X/Open usage below */ @@ -48,12 +49,6 @@ PDCurses portable platform definitions list: # include #endif -#if defined(__cplusplus) || defined(__cplusplus__) || defined(__CPLUSPLUS) -extern "C" -{ -# define bool _bool -#endif - /*---------------------------------------------------------------------- * * PDCurses Manifest Constants @@ -82,8 +77,6 @@ extern "C" * */ -typedef unsigned char bool; /* PDCurses Boolean type */ - #ifdef CHTYPE_LONG # if _LP64 typedef unsigned int chtype; diff --git a/payloads/libpayload/curses/curses.h b/payloads/libpayload/curses/curses.h index 1699250de6..b802adb3f4 100644 --- a/payloads/libpayload/curses/curses.h +++ b/payloads/libpayload/curses/curses.h @@ -87,7 +87,7 @@ * User-definable tweak to disable the include of . */ #ifndef NCURSES_ENABLE_STDBOOL_H -#define NCURSES_ENABLE_STDBOOL_H 0 //// XXX +#define NCURSES_ENABLE_STDBOOL_H 1 #endif /* From d9e543a5f9e0aa3c844e82fedf2499f30c0f9e69 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 24 Oct 2020 17:19:15 +0200 Subject: [PATCH 323/354] libpayload/keyboard: Use `bool` as return type Use `bool` whenever `0` was used to indicate an error. The mixing of different types for return values was mildly confusing and potentially dangerous with the i8042 API close by that uses `0` for success. Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- payloads/libpayload/drivers/i8042/keyboard.c | 20 +++++++++++--------- payloads/libpayload/include/libpayload.h | 3 ++- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index eb94199ec0..2dec3a38f2 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -27,6 +27,8 @@ * SUCH DAMAGE. */ +#include + #include #include #include @@ -169,14 +171,14 @@ static struct layout_maps keyboard_layouts[] = { #endif }; -static unsigned char keyboard_cmd(unsigned char cmd) +static bool keyboard_cmd(unsigned char cmd) { i8042_write_data(cmd); return i8042_wait_read_ps2() == 0xfa; } -int keyboard_havechar(void) +bool keyboard_havechar(void) { return i8042_data_ready_ps2(); } @@ -306,13 +308,13 @@ int keyboard_set_layout(char *country) } static struct console_input_driver cons = { - .havekey = keyboard_havechar, + .havekey = (int (*)(void))keyboard_havechar, .getchar = keyboard_getchar, .input_type = CONSOLE_INPUT_TYPE_EC, }; /* Enable keyboard translated */ -static int enable_translated(void) +static bool enable_translated(void) { if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { int cmd = i8042_read_data_ps2(); @@ -321,19 +323,19 @@ static int enable_translated(void) i8042_write_data(cmd); } else { printf("ERROR: i8042_cmd WR_CMD failed!\n"); - return 0; + return false; } } else { printf("ERROR: i8042_cmd RD_CMD failed!\n"); - return 0; + return false; } - return 1; + return true; } /* Set scancode set 1 */ -static int set_scancode_set(void) +static bool set_scancode_set(void) { - unsigned int ret; + bool ret; ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); if (!ret) { printf("ERROR: Keyboard set scancode failed!\n"); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index b761f042b9..fa501a7801 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -42,6 +42,7 @@ #ifndef _LIBPAYLOAD_H #define _LIBPAYLOAD_H +#include #include #include #include @@ -186,7 +187,7 @@ int add_reset_handler(void (*new_handler)(void)); */ void keyboard_init(void); void keyboard_disconnect(void); -int keyboard_havechar(void); +bool keyboard_havechar(void); unsigned char keyboard_get_scancode(void); int keyboard_getchar(void); int keyboard_set_layout(char *country); From 4a30d42c4a3a317400d2d93c110b57d22d1c8265 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 21 Oct 2020 17:54:40 -0700 Subject: [PATCH 324/354] vboot: Disable vboot functions in SMM SMM does not have access to CBMEM and therefore cannot access any persistent state like the vboot context. This makes it impossible to query vboot state like the developer mode switch or the currently active RW CBFS. However some code (namely the PC80 option table) does CBFS accesses in SMM. This is currently worked around by directly using cbfs_locate_file_in_region() with the COREBOOT region. By disabling vboot functions explicitly in SMM, we can get rid of that and use normal CBFS APIs in this code. Signed-off-by: Julius Werner Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46645 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/security/vboot/vboot_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index f2cff659ba..e64f6632a7 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -45,7 +45,7 @@ void verstage_mainboard_early_init(void); void verstage_mainboard_init(void); /* Check boot modes */ -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) && !ENV_SMM int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); int vboot_can_enable_udc(void); From 11298542cd8d6107e76d2905e55fc913be017ed1 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 9 Oct 2020 16:09:41 -0700 Subject: [PATCH 325/354] cbfstool: Don't build unneeded commonlib sources These sources are built but not used by cbfstool. The only .c file in commonlib/ it really needs is fsp_relocate.c. Get rid of the others. Signed-off-by: Julius Werner Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46253 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- util/cbfstool/Makefile.inc | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index bc2ff48fe0..ca1d79e8bb 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -23,10 +23,7 @@ cbfsobj += rmodule.o cbfsobj += xdr.o cbfsobj += partitioned_file.o # COMMONLIB -cbfsobj += cbfs.o cbfsobj += fsp_relocate.o -cbfsobj += mem_pool.o -cbfsobj += region.o # FMAP cbfsobj += fmap.o cbfsobj += kv_pair.o @@ -72,10 +69,6 @@ ifitobj += partitioned_file.o ifitobj += cbfs-mkstage.o ifitobj += cbfs-mkpayload.o ifitobj += rmodule.o -# COMMONLIB -ifitobj += cbfs.o -ifitobj += mem_pool.o -ifitobj += region.o # FMAP ifitobj += fmap.o ifitobj += kv_pair.o @@ -205,10 +198,6 @@ $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_scanner.o: TOOLCFLAGS += -Wno-unused-function # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -# Tolerate commonlib warnings -$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual -$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate lz4 warnings $(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes $(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes From 43439f6d49b104e0e2310ed675b487736ca8fea7 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 23 Oct 2020 15:54:46 +0200 Subject: [PATCH 326/354] lib/edid: Add missing name descriptor presence flag EDID parser internal flag c->has_name_descriptor was never set. It was causing decode_edid() function to return NON_CONFORMANT instead of CONFORMANT even when EDID frame was correct. Signed-off-by: Jakub Czapiga Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Fagerburg Reviewed-by: Angel Pons --- src/lib/edid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/edid.c b/src/lib/edid.c index f20d23959e..cd7a47ac78 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -261,6 +261,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, extract_string(x + 5, &c->has_valid_string_termination, EDID_ASCII_STRING_LENGTH)); + c->has_name_descriptor = 1; return 1; case 0xFD: { From 955ce24afc1e6fd1ec3ea00efbadf62626a16c0a Mon Sep 17 00:00:00 2001 From: Nick Chen Date: Wed, 30 Sep 2020 17:16:36 +0800 Subject: [PATCH 327/354] mb/google/volteer: Add a DPTF policy for Eldrid 1. Enable dptf feature and remove fan control part from overridetree.cb 2. Update tcc offset to 5 3. Follow thermal validation and update PL2 max_power to 51 BUG=b:167931578, b:170357248 Signed-off-by: Nick Chen Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/eldrid/overridetree.cb | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 5fcd456d40..7fd65767fc 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -1,5 +1,15 @@ chip soc/intel/tigerlake + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + + register "tcc_offset" = "5" # TCC of 95 register "TcssAuxOri" = "1" register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" @@ -58,7 +68,39 @@ chip soc/intel/tigerlake }" device domain 0 on - device ref dptf off end + device ref dptf on + # DPTF Policy for Eldrid board + chip drivers/intel/dptf + + ## Disable Active Policy from baseboard + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,95,5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60,6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,80,SHUTDOWN)" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" From bd21476f99785b83f45ad4ec02ed4e140505f912 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 15 Oct 2020 14:39:21 +0800 Subject: [PATCH 328/354] mb/google/kukui: change Jacuzzi followers LCMID to fixed value The LCM ID is not really used on Jacuzzi followers and the reference design expects ADC to return 0. However, there were hardware design issues so the returned value became unexpected numbers. - Juniper and Kappa returns 1. - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot. - Cerise and Stern usually returns 0, and sometimes 1. To fix that, we are changing LCM ID to fixed value for Jacuzzi followers. BUG=b:170916885,b:171365301 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. check burnet/esche skuid correctly Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu --- src/mainboard/google/kukui/Kconfig | 6 ++++++ src/mainboard/google/kukui/boardid.c | 18 ++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 2237efa076..23a41691f9 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -77,4 +77,10 @@ config BOARD_SDRAM_TABLE_OFFSET default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN default 0x0 +config BOARD_OVERRIDE_LCM_ID + hex + default 0x1 if BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_KAPPA || BOARD_GOOGLE_DAMU + default 0x1 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE + default 0x0 + endif diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 47b0d9bcd7..6c7547c21a 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -1,5 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* + * The boardid.c should provide board_id, sku_id, and ram_code. + * board_id is provided by ec/google/chromeec/ec_boardid.c. + * sku_id and ram_code are defined in this file. + */ + #include #include #include @@ -169,7 +175,15 @@ static uint8_t wfc_id(void) return 0; } -/* board_id is provided by ec/google/chromeec/ec_boardid.c */ +/* Returns the ID for LCD module (type of panel). */ +static uint8_t lcm_id(void) +{ + /* LCM is unused on Jacuzzi followers. */ + if (CONFIG(BOARD_GOOGLE_JACUZZI_COMMON)) + return CONFIG_BOARD_OVERRIDE_LCM_ID; + + return get_adc_index(LCM_ID_CHANNEL); +} uint32_t sku_id(void) { @@ -200,7 +214,7 @@ uint32_t sku_id(void) * ADC4[4bit/L] = SKU ID from board straps. */ cached_sku_id = (wfc_id() << 8 | - get_adc_index(LCM_ID_CHANNEL) << 4 | + lcm_id() << 4 | get_adc_index(SKU_ID_CHANNEL)); return cached_sku_id; From 8f594b7319c395bc09c711de05ff53f181c0c43d Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Fri, 23 Oct 2020 15:20:22 -0700 Subject: [PATCH 329/354] cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN Integer handling issues: Potentially overflowing expression "1 << size_msb" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: CID 1435825 and 1435826 Signed-off-by: Jonathan Zhang Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711 Reviewed-by: Marc Jones Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/x86/mtrr/mtrr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 284a1139ab..cb7ecdc963 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -484,9 +484,9 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, * size. The maximum size is calculated by a function of the * min base bit set and maximum size bit set. */ if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; + mtrr_size = 1ULL << size_msb; else - mtrr_size = 1 << addr_lsb; + mtrr_size = 1ULL << addr_lsb; if (var_state->prepare_msrs) prep_var_mtrr(var_state, base, mtrr_size, mtrr_type); From 12b376c87ff9367133618866659d2a5987d3e9a5 Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Wed, 21 Oct 2020 11:26:48 +0800 Subject: [PATCH 330/354] mb/google/dedede/var/magolor: Configure I2C high and low time Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Ren Kuo Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- .../dedede/variants/magolor/overridetree.cb | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index f41e9fab6b..625546e7ff 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -25,18 +25,42 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" From ce19f4f8ad069bf1ba85578ffb416e2a1eb9f1c9 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 18:48:43 -0600 Subject: [PATCH 331/354] util/testing: Remove test for util/broadcom/secimage util/broadcom/secimage was removed in commit aea00f496b1, so don't try to test it anymore. Signed-off-by: Martin Roth Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/testing/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index fb36c71a54..494055e749 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -115,8 +115,6 @@ test-tools: @echo "Build testing $(TOOLLIST)" $(foreach tool, $(TOOLLIST), $(MAKE) -C util/$(tool) clean ; ) $(foreach tool, $(TOOLLIST), echo "Building $(tool)";export MFLAGS= ;export MAKEFLAGS= ;$(MAKE) -C util/$(tool) all V=$(V) Q=$(Q) || exit 1; ) - echo "Testing broadcom/secimage" - $(MAKE) -C util/broadcom/secimage test @echo "Running gitconfig tests" @for test in $$(find util/gitconfig/test -maxdepth 1 \ -type f -executable); do \ From 99af210456d346187692e0b7b982b01c28006ab0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:39:17 +0200 Subject: [PATCH 332/354] mb/google/auron: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/devicetree.cb | 115 +++++++++--------- .../variants/auron_paine/overridetree.cb | 12 +- .../auron/variants/auron_yuna/overridetree.cb | 12 +- .../auron/variants/buddy/overridetree.cb | 50 ++++---- .../auron/variants/gandof/overridetree.cb | 12 +- .../auron/variants/lulu/overridetree.cb | 12 +- .../auron/variants/samus/overridetree.cb | 42 ++++--- 7 files changed, 135 insertions(+), 120 deletions(-) diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a3097624fe..09593b7b53 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,27 +15,6 @@ chip soc/intel/broadwell # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - register "s0ix_enable" = "1" device cpu_cluster 0 on @@ -46,40 +25,64 @@ chip soc/intel/broadwell device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + +# chip soc/intel/broadwell/pch + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sio_acpi_mode" = "1" + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal +# end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 60aef30a58..dc70085dd0 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index da80fecba8..b46e34cf83 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f14896425a..45229bad6d 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,32 +7,34 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "sata_devslp_disable" = "0x1" - - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - register "s0ix_enable" = "0" device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus +# chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus +# end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 75c202d663..eae7999ea2 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 60aef30a58..dc70085dd0 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index c5d27476c7..710fa95cac 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,30 +10,32 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - register "sata_port0_gen3_tx" = "0x72" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" # Disable S0ix for now register "s0ix_enable" = "0" - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 15.3 on end # GSPI0 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - device pci 1d.0 off end # USB2 EHCI +# chip soc/intel/broadwell/pch + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI +# end end end From bd8e6dd2ca99f3ba79f1474a3afe0c518b504d44 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 15:07:07 -0600 Subject: [PATCH 333/354] util/docker: Update coreboot-sdk with additional tools - cscope: Run cscope targets - ctags: Run ctags targets - pbzip2: Allow compression on all cpu cores Signed-off-by: Martin Roth Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-sdk/Dockerfile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 007e9afc7b..749b543149 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -24,11 +24,13 @@ RUN \ bzip2 \ ccache \ cmake \ + cscope \ curl \ device-tree-compiler \ dh-autoreconf \ diffutils \ doxygen \ + exuberant-ctags \ flex \ g++ \ gawk \ @@ -62,6 +64,7 @@ RUN \ nasm \ openssl \ patch \ + pbzip2 \ pkg-config \ python2 \ python3 \ From b86d2b09354a5a27dec0e73221ca7b4c794976bd Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 15:09:44 -0600 Subject: [PATCH 334/354] util/docker: Update coreboot-sdk to set python2 as default Even though both python2 and python3 are now installed to the SDK, the default python program is not. This sets the default to python2. Signed-off-by: Martin Roth Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-sdk/Dockerfile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 749b543149..0ae63c8d2c 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -79,6 +79,7 @@ RUN \ xz-utils \ zlib1g-dev \ && apt-get clean \ + && update-alternatives --install /usr/bin/python python /usr/bin/python2 1 \ && ln -s /usr/bin/automake /usr/bin/automake-1.15 \ && ln -s /usr/bin/aclocal /usr/bin/aclocal-1.15 From ebeec5aed3cd2c5b1d68bf139385a96fe6795abc Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 15:16:00 -0600 Subject: [PATCH 335/354] util/docker: Update coreboot-sdk consolidate coreboot build Because docker saves a container for every run command, by breaking the coreboot build into 3 commands, it greatly increased the size of the docker containers needed. When combined as one run command, the coreboot repo that is downloaded, along with the coreboot test build are deleted before the container is created. Since those directories are deleted in a later run command, they don't even make it into the final container, and just force coreboot-sdk users to download extra data for no reason. While splitting the build may help with debugging failures when creating the docker container, that debugging can be done locally by splitting up a working copy. Signed-off-by: Martin Roth Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-sdk/Dockerfile | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 0ae63c8d2c..3946814274 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -84,21 +84,17 @@ RUN \ && ln -s /usr/bin/aclocal /usr/bin/aclocal-1.15 RUN \ - cd /root && \ + cd /tmp && \ git clone https://review.coreboot.org/coreboot && \ cd coreboot && \ - git checkout {{DOCKER_COMMIT}} - -RUN \ + git checkout {{DOCKER_COMMIT}}; \ if echo {{CROSSGCC_PARAM}} | grep -q ^all; then \ - make -C/root/coreboot/util/crossgcc/ build_clang \ + make -C /tmp/coreboot/util/crossgcc/ build_clang \ BUILD_LANGUAGES=c,ada CPUS=$(nproc) DEST=/opt/xgcc; \ - fi - -RUN \ - make -C/root/coreboot/util/crossgcc/ {{CROSSGCC_PARAM}} \ + fi; \ + make -C /tmp/coreboot/util/crossgcc/ {{CROSSGCC_PARAM}} \ BUILD_LANGUAGES=c,ada CPUS=$(nproc) DEST=/opt/xgcc && \ - rm -rf /root/coreboot + rm -rf /tmp/coreboot RUN mkdir /home/coreboot/.ccache && \ chown coreboot:coreboot /home/coreboot/.ccache && \ From 7d520ff98f45c357399cad18ed382c125edd3a32 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 15:19:40 -0600 Subject: [PATCH 336/354] util/docker: Add tests to coreboot-sdk build process This tests some of the basic targets that coreboot-sdk needs to be able to run. I was running most of these tests manually after creating the sdk image, but adding it into the Dockerfile makes sure they get run. Signed-off-by: Martin Roth Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-sdk/Dockerfile | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 3946814274..26078e8823 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -110,3 +110,33 @@ ENV PATH $PATH:/opt/xgcc/bin ENV SDK_VERSION={{SDK_VERSION}} ENV SDK_COMMIT={{DOCKER_COMMIT}} USER coreboot + +# Test the built image +RUN mkdir -p /tmp/work && \ + cd /tmp/work && \ + git clone https://review.coreboot.org/bios_extract.git && \ + make -C bios_extract && \ + git clone https://review.coreboot.org/memtest86plus.git && \ + make -C memtest86plus && \ + git clone https://review.coreboot.org/flashrom.git && \ + CONFIG_EVERYTHING=yes make -C flashrom && \ + git clone https://review.coreboot.org/em100.git && \ + make -C em100 && \ + git clone https://review.coreboot.org/coreboot.git && \ + make -C coreboot CPUS=$(nproc) test-abuild && \ + \ + make -C coreboot olddefconfig && \ + make -C coreboot all -j && \ + make -C coreboot printall && \ + make -C coreboot filelist && \ + make -C coreboot ctags-project && \ + make -C coreboot cscope-project && \ + \ + make -C coreboot doxygen -j && \ + make -C coreboot test-payloads&& \ + make -C coreboot test-tools -j && \ + make -C coreboot test-lint -j && \ + make -C coreboot test-cleanup -j && \ + make -C coreboot CPUS=$(nproc) crostools && \ + cd && \ + rm -rf /tmp/work/ From a266299490167a9c7f5f6f663a16a6af03678e3c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 18:24:34 -0600 Subject: [PATCH 337/354] util/docker: Update agent-root to node-root for jenkins Jenkins has changed the name of the build directory, so it's not currently building out of memory, it's writing to the SSD. This changes the build back to tmpfs. Signed-off-by: Martin Roth Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-jenkins-node/Dockerfile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 0442efcb16..e9d866b31a 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -35,13 +35,13 @@ RUN mkdir /var/run/sshd && \ chmod 0755 /var/run/sshd && \ /usr/bin/ssh-keygen -A -# Create /cb-build as a tmpfs directory to build in +# Create tmpfs directories to build in RUN mkdir /cb-build && \ chown coreboot:coreboot /cb-build && \ echo "tmpfs /cb-build tmpfs rw,mode=1777 0 0" > /etc/fstab && \ - mkdir -p /home/coreboot/agent-root/workspace && \ - chown -R coreboot:coreboot /home/coreboot/agent-root && \ - echo "tmpfs /home/coreboot/agent-root/workspace tmpfs rw,mode=1777 0 0" >> /etc/fstab && \ + mkdir -p /home/coreboot/node-root/workspace && \ + chown -R coreboot:coreboot /home/coreboot/node-root && \ + echo "tmpfs /home/coreboot/node-root/workspace tmpfs rw,mode=1777 0 0" >> /etc/fstab && \ chown coreboot:coreboot /home/coreboot/.ccache && \ echo "tmpfs /home/coreboot/.ccache tmpfs rw,mode=1777 0 0" >> /etc/fstab @@ -53,8 +53,8 @@ RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ VOLUME /data/cache ENTRYPOINT mount /cb-build && \ - mount /home/coreboot/agent-root/workspace && \ - chown -R coreboot:coreboot /home/coreboot/agent-root && \ + mount /home/coreboot/node-root/workspace && \ + chown -R coreboot:coreboot /home/coreboot/node-root && \ mount /home/coreboot/.ccache && \ chown coreboot:coreboot /home/coreboot/.ccache && \ /usr/sbin/sshd -p 49151 -D From 2aba15fce15eca22dd458c852e453f6a79347e41 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 18:44:35 -0600 Subject: [PATCH 338/354] util/docker: Update atime mount point options for jenkins - The ccache files don't need atime. - Enable strict atime for the git repos. This will help find unused files. Signed-off-by: Martin Roth Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/docker/coreboot-jenkins-node/Dockerfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index e9d866b31a..36b77d6398 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -38,10 +38,10 @@ RUN mkdir /var/run/sshd && \ # Create tmpfs directories to build in RUN mkdir /cb-build && \ chown coreboot:coreboot /cb-build && \ - echo "tmpfs /cb-build tmpfs rw,mode=1777 0 0" > /etc/fstab && \ + echo "tmpfs /cb-build tmpfs rw,mode=1777,noatime 0 0" > /etc/fstab && \ mkdir -p /home/coreboot/node-root/workspace && \ chown -R coreboot:coreboot /home/coreboot/node-root && \ - echo "tmpfs /home/coreboot/node-root/workspace tmpfs rw,mode=1777 0 0" >> /etc/fstab && \ + echo "tmpfs /home/coreboot/node-root/workspace tmpfs rw,mode=1777,strictatime,atime 0 0" >> /etc/fstab && \ chown coreboot:coreboot /home/coreboot/.ccache && \ echo "tmpfs /home/coreboot/.ccache tmpfs rw,mode=1777 0 0" >> /etc/fstab From b0432778661eb32a85f5f67aaef8d94aa9516114 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 18:57:03 -0600 Subject: [PATCH 339/354] util/testing: Update test-abuild output directories This matches the what-jenkins-does target. Signed-off-by: Martin Roth Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/testing/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 494055e749..88728841a3 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -99,8 +99,8 @@ test-lint: test-abuild: rm -rf coreboot-builds-chromeos coreboot-builds - export COREBOOT_BUILD_DIR=coreboot-builds-chromeos; util/abuild/abuild -B -e $(if $(TEST_NOCCACHE),,-y) -c $(CPUS) -p $(TEST_PAYLOAD) -x - util/abuild/abuild -B -e $(if $(TEST_NOCCACHE),,-y) -c $(CPUS) -p $(TEST_PAYLOAD) + util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/chromeos -B -e $(if $(TEST_NOCCACHE),,-y) -c $(CPUS) -p $(TEST_PAYLOAD) -x + util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/default -B -e $(if $(TEST_NOCCACHE),,-y) -c $(CPUS) -p $(TEST_PAYLOAD) test-payloads: $(MAKE) -C payloads/libpayload test-configs -j $(CPUS) V=$(V) Q=$(Q) MFLAGS= MAKEFLAGS= $(if $(TEST_NOCCACHE),,CONFIG_LP_CCACHE=y) From 93122a7e777890d4f28c1477bef60db98c65c26e Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 25 Oct 2020 19:02:15 -0600 Subject: [PATCH 340/354] util/testing: Allow what-jenkins-does to skip lint testing The linters touch every file under src and probably util. This makes it difficult to see what files have been accessed by the builder. The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins build that looks for unused files. Signed-off-by: Martin Roth Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/testing/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 88728841a3..d09419682a 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -79,8 +79,10 @@ COREBOOT_BUILD_DIR?=coreboot-builds what-jenkins-does: rm -rf $(COREBOOT_BUILD_DIR)/chromeos $(COREBOOT_BUILD_DIR)/default +ifneq ($(JENKINS_SKIP_LINT_TESTS),y) util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit +endif util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/chromeos $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/default $(ABUILD_OPTIONS) $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) From 05b883ed24a120dba83e84d9326aedf32d3522eb Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 13 Oct 2020 15:12:01 +0200 Subject: [PATCH 341/354] device: Rephrase bus master Kconfig option Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index b69a254b80..cbe970f170 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -520,7 +520,7 @@ config PCIEXP_PLUGIN_SUPPORT default y config PCI_ALLOW_BUS_MASTER - bool "Allow PCI bus master bit to be enabled by coreboot" + bool "Allow coreboot to set optional PCI bus master bits" default y help For security reasons, bus mastering should be enabled as late as From fd3dde3e33c470b29ff953e82ca68f404d766bec Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Sun, 4 Oct 2020 23:07:33 +0800 Subject: [PATCH 342/354] mb/google/octopus/var/garg: fix LTE power sequence in reboot state invoke LTE power off function to meet LTE power sequence while DUT is in reboot state. BUG=b:167565015 BRANCH=octopus TEST=build and verify on the DUT with LTE Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022 Reviewed-by: Patrick Georgi Reviewed-by: Marco Chen Reviewed-by: Henry Sun Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/garg/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc index ba865e9f82..7ee7e70d4b 100644 --- a/src/mainboard/google/octopus/variants/garg/Makefile.inc +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c + +smm-y += variant.c From 5b511f98b5cd4ad03ae05fbcf5c1bdb665918cec Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Sat, 24 Oct 2020 01:36:00 +0800 Subject: [PATCH 343/354] mb/google/octopus/var/garg: Disable XHCI LFPS power management by sku LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:171478764 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701 Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- .../octopus/variants/garg/overridetree.cb | 1 + .../google/octopus/variants/garg/variant.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index f3c580d2c0..971d0d8b7c 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -192,4 +192,5 @@ chip soc/intel/apollolake # Disable compliance mode register "DisableComplianceMode" = "1" + register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 7c84f2696b..0a6574d1a6 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -8,6 +8,7 @@ #include #include #include +#include const char *mainboard_vbt_filename(void) { @@ -42,3 +43,21 @@ void variant_smi_sleep(u8 slp_typ) return; } } + +void variant_update_devtree(struct device *dev) +{ + struct soc_intel_apollolake_config *cfg = NULL; + + cfg = (struct soc_intel_apollolake_config *)dev->chip_info; + + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { + switch (google_chromeec_get_board_sku()) { + case SKU_17_LTE: + case SKU_18_LTE_TS: + cfg->disable_xhci_lfps_pm = 1; + return; + default: + return; + } + } +} From 441c63d5f08272833603fdfb53bc61ec1f503e78 Mon Sep 17 00:00:00 2001 From: Andrey Pronin Date: Sun, 25 Oct 2020 13:00:30 -0700 Subject: [PATCH 344/354] security/vboot: fix policy digest for nvmem spaces This CL fixes the policy digest that restricts deleting the nvmem spaces to specific PCR0 states. BRANCH=none BUG=b:140958855 TEST=verified that nvmem spaces created with this digest can be deleted in the intended states, and cannot be deleted in other states (test details for ChromeOS - in BUG comments). Change-Id: I3cb7d644fdebda71cec3ae36de1dc76387e61ea7 Signed-off-by: Andrey Pronin Reviewed-on: https://review.coreboot.org/c/coreboot/+/46772 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/security/vboot/secdata_tpm.c | 46 +++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 65d9c83a34..0e14575f61 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -109,13 +109,41 @@ static const TPMA_NV rw_space_attributes = { }; /* - * This policy digest was obtained using TPM2_PolicyPCR - * selecting only PCR_0 with a value of all zeros. + * This policy digest was obtained using TPM2_PolicyOR on 3 digests + * corresponding to a sequence of + * -) TPM2_PolicyCommandCode(TPM_CC_NV_UndefineSpaceSpecial), + * -) TPM2_PolicyPCR(PCR0, ). + * where is + * 1) all zeros = initial, unextended state: + * - Value to extend to initial PCR0: + * + * - Resulting PCR0: + * 0000000000000000000000000000000000000000000000000000000000000000 + * - Policy digest for PolicyCommandCode + PolicyPCR: + * 4B44FC4192DB5AD7167E0135708FD374890A06BFB56317DF01F24F2226542A3F + * 2) result of extending (SHA1(0x00|0x01|0x00) | 00s to SHA256 size) + * - Value to extend to initial PCR0: + * 62571891215b4efc1ceab744ce59dd0b66ea6f73000000000000000000000000 + * - Resulting PCR0: + * 9F9EA866D3F34FE3A3112AE9CB1FBABC6FFE8CD261D42493BC6842A9E4F93B3D + * - Policy digest for PolicyCommandCode + PolicyPCR: + * CB5C8014E27A5F7586AAE42DB4F9776A977BCBC952CA61E33609DA2B2C329418 + * 3) result of extending (SHA1(0x01|0x01|0x00) | 00s to SHA256 size) + * - Value to extend to initial PCR0: + * 47ec8d98366433dc002e7721c9e37d5067547937000000000000000000000000 + * - Resulting PCR0: + * 2A7580E5DA289546F4D2E0509CC6DE155EA131818954D36D49E027FD42B8C8F8 + * - Policy digest for PolicyCommandCode + PolicyPCR: + * E6EF4F0296AC3EF0F53906480985B1BE8058E0E517E5F74A5B8A415EFE339D87 + * Values #2 and #3 correspond to two forms of recovery mode as extended by + * vb2api_get_pcr_digest(). + * As a result, the digest allows deleting the space with UndefineSpaceSpecial + * at early RO stages (before extending PCR0) or from recovery mode. */ -static const uint8_t pcr0_unchanged_policy[] = { - 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, - 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, - 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; +static const uint8_t pcr0_allowed_policy[] = { + 0x44, 0x44, 0x79, 0x00, 0xCB, 0xB8, 0x3F, 0x5B, 0x15, 0x76, 0x56, + 0x50, 0xEF, 0x96, 0x98, 0x0A, 0x2B, 0x96, 0x6E, 0xA9, 0x09, 0x04, + 0x4A, 0x01, 0xB8, 0x5F, 0xA5, 0x4A, 0x96, 0xFC, 0x59, 0x84}; /* Nothing special in the TPM2 path yet. */ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) @@ -154,7 +182,7 @@ static uint32_t set_firmware_space(const void *firmware_blob) { return set_space("firmware", FIRMWARE_NV_INDEX, firmware_blob, VB2_SECDATA_FIRMWARE_SIZE, ro_space_attributes, - pcr0_unchanged_policy, sizeof(pcr0_unchanged_policy)); + pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); } static uint32_t set_kernel_space(const void *kernel_blob) @@ -167,8 +195,8 @@ static uint32_t set_mrc_hash_space(uint32_t index, const uint8_t *data) { if (index == MRC_REC_HASH_NV_INDEX) { return set_space("RO MRC Hash", index, data, HASH_NV_SIZE, - ro_space_attributes, pcr0_unchanged_policy, - sizeof(pcr0_unchanged_policy)); + ro_space_attributes, pcr0_allowed_policy, + sizeof(pcr0_allowed_policy)); } else { return set_space("RW MRC Hash", index, data, HASH_NV_SIZE, rw_space_attributes, NULL, 0); From fc38e8834132f83ed59e6b0f59bd90c940edd991 Mon Sep 17 00:00:00 2001 From: Wenbin Mei Date: Tue, 19 May 2020 09:49:54 +0800 Subject: [PATCH 345/354] mb/google/asurada: Configure pinctrl for SD and MMC The pins for SD and MMC must be configured properly so we can access them in payloads. Signed-off-by: Wenbin Mei Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/mainboard/google/asurada/mainboard.c | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 9146d7bc1d..7a37df5764 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -2,10 +2,71 @@ #include #include +#include +#include #include +#define MSDC0_DRV_MASK 0x3fffffff +#define MSDC1_DRV_MASK 0x3ffff000 +#define MSDC0_DRV_VALUE 0x24924924 +#define MSDC1_DRV_VALUE 0x24924000 + +static void configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ + clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); +} + +static void configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RM_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 10mA */ + clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); +} + static void mainboard_init(struct device *dev) { + configure_emmc(); + configure_sdcard(); setup_usb_host(); } From bd0a222ab44277ab48b8bf95419ae310b8ccf82e Mon Sep 17 00:00:00 2001 From: CK Hu Date: Wed, 1 Jul 2020 15:01:04 +0800 Subject: [PATCH 346/354] mb/google/asurada: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. Signed-off-by: CK Hu Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/asurada/mainboard.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7a37df5764..8699ede772 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,16 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include "gpio.h" + +#include + #define MSDC0_DRV_MASK 0x3fffffff #define MSDC1_DRV_MASK 0x3ffff000 #define MSDC0_DRV_VALUE 0x24924924 #define MSDC1_DRV_VALUE 0x24924000 +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(¶m_reset.h); +} + static void configure_emmc(void) { void *gpio_base = (void *)IOCFG_TL_BASE; @@ -68,6 +84,8 @@ static void mainboard_init(struct device *dev) configure_emmc(); configure_sdcard(); setup_usb_host(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) From 83a2a007c783bf4fc37d29bdaae3a7b8a208b88e Mon Sep 17 00:00:00 2001 From: Jingle Hsu Date: Tue, 27 Oct 2020 11:33:24 +0800 Subject: [PATCH 347/354] mb/ocp/deltalake: Rename motherboard_fill_fadt() Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/ocp/deltalake/fadt.c | 2 +- src/soc/intel/xeon_sp/include/soc/acpi.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/ocp/deltalake/fadt.c b/src/mainboard/ocp/deltalake/fadt.c index b9fcd582ef..6306e03e30 100644 --- a/src/mainboard/ocp/deltalake/fadt.c +++ b/src/mainboard/ocp/deltalake/fadt.c @@ -3,7 +3,7 @@ #include #include -void motherboard_fill_fadt(acpi_fadt_t *fadt) +void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 61639d2a84..60d6321be4 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -20,7 +20,6 @@ typedef struct { unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void motherboard_fill_fadt(acpi_fadt_t *fadt); int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); From 160cb331fca8d7a389b25bce30cb3e3cc3a7b4cc Mon Sep 17 00:00:00 2001 From: Morgan Jang Date: Tue, 27 Oct 2020 11:34:43 +0800 Subject: [PATCH 348/354] soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 88205173b6..d60684bccb 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -53,8 +53,7 @@ uint32_t soc_read_sci_irq_select(void) void soc_fill_fadt(acpi_fadt_t *fadt) { /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE); + fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } void uncore_inject_dsdt(const struct device *device) From bdd863689dd2902e2999971b8bf9ea3d811aab8a Mon Sep 17 00:00:00 2001 From: Morgan Jang Date: Wed, 7 Oct 2020 14:02:49 +0800 Subject: [PATCH 349/354] src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7 TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/Makefile.inc | 2 +- src/soc/intel/xeon_sp/ramstage.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 src/soc/intel/xeon_sp/ramstage.c diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 8a26c14acc..ffc55b6d4a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c new file mode 100644 index 0000000000..68d5d4658c --- /dev/null +++ b/src/soc/intel/xeon_sp/ramstage.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + switch (level) { + case 1: + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; + case 2: + case 3: + return SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS; + default: + return SMBIOS_CACHE_OP_MODE_UNKNOWN; + } +} From e828554ee046c3f5b1acdcef46a5e2724a42048a Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 27 Sep 2020 15:26:41 +0300 Subject: [PATCH 350/354] mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scope The corresponding devices and objects are already included in the System Bus ACPI scope inside uncore.asl. There is no need to do this again in the DSDT of the motherboard. Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/ocp/tiogapass/dsdt.asl | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 4aff668cff..d5b7b42b13 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -18,9 +18,5 @@ DefinitionBlock( #include #include - - // Xeon-SP ACPI tables - Scope (\_SB) { - #include - } + #include } From 71b546773daa57682c480196f4ed167dd060b54c Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 26 Oct 2020 17:09:01 +0900 Subject: [PATCH 351/354] mb/google/nightfury: Set internal pull-down for GPP_D19 Add internal pull-down for GPP_D19 to improve DMIC noise issue on nightfury. BUG=b:171669255 BRANCH=firmware-hatch-12672.B TEST=Built and checked GPP_D19 voltage after booting Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816 Tested-by: build bot (Jenkins) Reviewed-by: Bob Moragues Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/nightfury/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 951723ebeb..eb6217ded9 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -37,6 +37,8 @@ static const struct pad_config gpio_table[] = { /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, DN_20K, DEEP, NF1), /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ PAD_NC(GPP_E4, NONE), From 6ad856825a0c4b2c2d64b633e7cb83fcb4dd8ff2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Mon, 26 Oct 2020 11:40:41 -0600 Subject: [PATCH 352/354] drivers/mrc_cache: Fix size comparison in mrc_cache update `mrc_cache_needs_update` is comparing the "new size" of the MRC data (minus metadata size) to the size including the metadata, which causes the driver to think the data has changed, and so it will rewrite the MRC cache on every boot. This patch removes the metadata size from the comparison. BUG=b:171513942 BRANCH=volteer TEST=1) Memory training data gets written the on a boot where the data was wiped out. 2) Memory training data does not get written back on every subsequent boot. Signed-off-by: Tim Wawrzynczak Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46824 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen Reviewed-by: Furquan Shaikh --- src/drivers/mrc_cache/mrc_cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3b98dbaa63..eb43123c67 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -337,10 +337,10 @@ static bool mrc_cache_needs_update(const struct region_device *rdev, const void *new_data, size_t new_data_size) { void *mapping, *data_mapping; - size_t size = region_device_sz(rdev); + size_t old_data_size = region_device_sz(rdev) - sizeof(struct mrc_metadata); bool need_update = false; - if (new_data_size != size) + if (new_data_size != old_data_size) return true; mapping = rdev_mmap_full(rdev); From ccb1119738ed6b9d922f051faa0162b545e31f7b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 15 Oct 2020 11:14:15 +0200 Subject: [PATCH 353/354] sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variables The Kconfig variables are used in the C code for cbfs file names but not in the Makefiles adding them. Change-Id: Ie35508d54ae91292f06de9827f0fb543ad81734d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46454 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/security/intel/txt/Makefile.inc | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 39c3ad1dff..712ab589d5 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -9,24 +9,25 @@ ramstage-y += getsec_enteraccs.S ramstage-y += ramstage.c ramstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c -cbfs-files-y += txt_bios_acm.bin -txt_bios_acm.bin-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) -txt_bios_acm.bin-type := raw -txt_bios_acm.bin-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) +cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) +$(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) +$(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-type := raw +$(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) ifneq ($(CONFIG_INTEL_TXT_SINITACM_FILE),"") -cbfs-files-y += txt_sinit_acm.bin -txt_sinit_acm.bin-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) -txt_sinit_acm.bin-type := raw -txt_sinit_acm.bin-align := 0x10 -txt_sinit_acm.bin-compression := lzma +cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_SINIT_ACM) +$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) +$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-type := raw +$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-align := 0x10 +$(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-compression := lzma endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) INTERMEDIATE+=add_acm_fit add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) - $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< + $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ + -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< # Initial BootBlock files ibb-files := $(foreach file,$(cbfs-files), \ From 3603960d4d8836b1995edfad880d9b1471c10de1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 15 Oct 2020 13:52:20 +0200 Subject: [PATCH 354/354] sec/intel/txt/Kconfig: Remove the menu for including ACMs This is consistent with how other binaries (e.g. FSP) are added via Kconfig. This also makes it more visible that things need to be configured. Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46455 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/security/intel/txt/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index d3ef2a64db..80be7c29e9 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -13,8 +13,6 @@ config INTEL_TXT if INTEL_TXT -menu "Intel" - config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE @@ -71,6 +69,4 @@ config INTEL_TXT_CBFS_SINIT_ACM string default "txt_sinit_acm.bin" -endmenu # Intel - endif