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cpu/x86/mtrr: Make useful MTRR functions available for all boot stages

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This patch migrates a few useful MTRR functions as below from
`earlymtrr.c` file to newly created common stage file `mtrrlib.c`.
1. get_free_var_mtrr
2. set_var_mtrr
3. clear_all_var_mtrr

These functions can be used to perform the MTRR programming from IA
common code SPI driver as `fast_spi.c` without requiring two separate
implementations for early boot stage (till romstage) and for ramstage
onwards.

BUG=b:225766934
TEST=Able to build and boot google/redrix board to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c62a04a36d3169545c3128b4231992ad9b3699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2022-03-30 23:44:52 +05:30 committed by Felix Held
parent 6de1d9ff4e
commit 3ad00d0c89
3 changed files with 70 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/x86/mtrr/Makefile.inc
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@ -1,5 +1,10 @@
ramstage-y += mtrr.c ramstage-y += mtrr.c
ramstage-y += mtrrlib.c
romstage-y += mtrrlib.c
bootblock-y += mtrrlib.c
verstage_x86-y += mtrrlib.c
romstage-y += earlymtrr.c romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c bootblock-y += earlymtrr.c
verstage_x86-y += earlymtrr.c verstage_x86-y += earlymtrr.c

60
src/cpu/x86/mtrr/earlymtrr.c
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@ -6,66 +6,6 @@
#include <console/console.h> #include <console/console.h>
#include <commonlib/bsd/helpers.h> #include <commonlib/bsd/helpers.h>
/* Get first available variable MTRR.
* Returns var# if available, else returns -1.
*/
int get_free_var_mtrr(void)
{
msr_t maskm;
int vcnt;
int i;
vcnt = get_var_mtrr_count();
/* Identify the first var mtrr which is not valid. */
for (i = 0; i < vcnt; i++) {
maskm = rdmsr(MTRR_PHYS_MASK(i));
if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
return i;
}
/* No free var mtrr. */
return -1;
}
void set_var_mtrr(
unsigned int reg, unsigned int base, unsigned int size,
unsigned int type)
{
/* Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
if (!IS_POWER_OF_2(size))
printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
if (size < 4 * KiB)
printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
if (base % size != 0)
printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
size);
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
void clear_all_var_mtrr(void)
{
msr_t mtrr = {0, 0};
int vcnt;
int i;
vcnt = get_var_mtrr_count();
for (i = 0; i < vcnt; i++) {
wrmsr(MTRR_PHYS_MASK(i), mtrr);
wrmsr(MTRR_PHYS_BASE(i), mtrr);
}
}
void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg) void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg)
{ {
ctx->upper_mask = (1U << (cpu_phys_address_size() - 32)) - 1; ctx->upper_mask = (1U << (cpu_phys_address_size() - 32)) - 1;

65
src/cpu/x86/mtrr/mtrrlib.c Normal file
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@ -0,0 +1,65 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <console/console.h>
/* Get first available variable MTRR.
* Returns var# if available, else returns -1.
*/
int get_free_var_mtrr(void)
{
msr_t maskm;
int vcnt;
int i;
vcnt = get_var_mtrr_count();
/* Identify the first var mtrr which is not valid. */
for (i = 0; i < vcnt; i++) {
maskm = rdmsr(MTRR_PHYS_MASK(i));
if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
return i;
}
/* No free var mtrr. */
return -1;
}
void set_var_mtrr(
unsigned int reg, unsigned int base, unsigned int size, unsigned int type)
{
/* Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
if (!IS_POWER_OF_2(size))
printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
if (size < 4 * KiB)
printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
if (base % size != 0)
printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
size);
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
void clear_all_var_mtrr(void)
{
msr_t mtrr = {0, 0};
int vcnt;
int i;
vcnt = get_var_mtrr_count();
for (i = 0; i < vcnt; i++) {
wrmsr(MTRR_PHYS_MASK(i), mtrr);
wrmsr(MTRR_PHYS_BASE(i), mtrr);
}
}