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soc/intel/apollolake: Only use 8 bits for afterg3

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In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e)
(source Intel document #569262). Only use 8 bits, in the same way as
most other Intel SOCs do, for pmc_soc_set_afterg3_en.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
2023-05-03 21:15:24 +01:00
committed by Felix Held
parent 8bf53c0162
commit 3b56cffa8a
1 changed files with 7 additions and 6 deletions
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13
src/soc/intel/apollolake/pmutil.c
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@@ -223,15 +223,16 @@ uint16_t get_pmbase(void)
return (uint16_t)ACPI_BASE_ADDRESS; return (uint16_t)ACPI_BASE_ADDRESS;
} }
/* Set which power state system will be after reapplying the power (from G3 State) */
void pmc_soc_set_afterg3_en(const bool on) void pmc_soc_set_afterg3_en(const bool on)
{ {
const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; uint8_t reg8;
uint32_t reg32; uint8_t *const pmcbase = pmc_mmio_regs();
reg32 = read32p(gen_pmcon1); reg8 = read8(pmcbase + GEN_PMCON_A);
if (on) if (on)
reg32 &= ~SLEEP_AFTER_POWER_FAIL; reg8 &= ~SLEEP_AFTER_POWER_FAIL;
else else
reg32 |= SLEEP_AFTER_POWER_FAIL; reg8 |= SLEEP_AFTER_POWER_FAIL;
write32p(gen_pmcon1, reg32); write8(pmcbase + GEN_PMCON_A, reg8);
} }