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cpu/intel/pineview: Include speedstep

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Needed to generate cpu entries.

Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Arthur Heymans
2017-04-28 22:36:17 +02:00
committed by Stefan Reinauer
parent 27e1801ea7
commit 3b633bbf1d
2 changed files with 2 additions and 0 deletions
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src/cpu/intel/socket_FCBGA559/Makefile.inc
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@ -6,6 +6,7 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c