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Kconfig: Update default hex values to start with 0x

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Kconfig hex values don't need to be in quotes, and should start with
'0x'.  If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.

A check for this has been added to the Kconfig lint tool.

Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
2016-09-30 14:43:01 -06:00
parent cc3365a039
commit 3b87812f00
28 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/Kconfig
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@ -634,7 +634,7 @@ config IOAPIC
config CACHE_ROM_SIZE_OVERRIDE config CACHE_ROM_SIZE_OVERRIDE
hex hex
default 0 default 0x0
# TODO: Can probably be removed once all chipsets have kconfig options for it. # TODO: Can probably be removed once all chipsets have kconfig options for it.
config VIDEO_MB config VIDEO_MB

2
src/console/Kconfig
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@ -330,7 +330,7 @@ config CMOS_POST
config CMOS_POST_OFFSET config CMOS_POST_OFFSET
hex "Offset into CMOS to store POST codes" hex "Offset into CMOS to store POST codes"
depends on CMOS_POST depends on CMOS_POST
default 0 default 0x0
help help
If CMOS_POST is enabled then an offset into CMOS must be provided. If CMOS_POST is enabled then an offset into CMOS must be provided.
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value

4
src/device/Kconfig
View File

@ -288,7 +288,7 @@ endif # EARLY_PCI_BRIDGE
config SUBSYSTEM_VENDOR_ID config SUBSYSTEM_VENDOR_ID
hex "Override PCI Subsystem Vendor ID" hex "Override PCI Subsystem Vendor ID"
depends on PCI depends on PCI
default "0x0000" default 0x0000
help help
This config option will override the devicetree settings for This config option will override the devicetree settings for
PCI Subsystem Vendor ID. PCI Subsystem Vendor ID.
@ -296,7 +296,7 @@ config SUBSYSTEM_VENDOR_ID
config SUBSYSTEM_DEVICE_ID config SUBSYSTEM_DEVICE_ID
hex "Override PCI Subsystem Device ID" hex "Override PCI Subsystem Device ID"
depends on PCI depends on PCI
default "0x0000" default 0x0000
help help
This config option will override the devicetree settings for This config option will override the devicetree settings for
PCI Subsystem Device ID. PCI Subsystem Device ID.

4
src/drivers/i2c/tpm/Kconfig
View File

@ -22,12 +22,12 @@ endchoice
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex "I2C TPM chip bus" hex "I2C TPM chip bus"
default 9 # FIXME, workaround for Kconfig BS default 0x9 # FIXME, workaround for Kconfig BS
depends on I2C_TPM depends on I2C_TPM
config DRIVER_TPM_I2C_ADDR config DRIVER_TPM_I2C_ADDR
hex "I2C TPM chip address" hex "I2C TPM chip address"
default 2 # FIXME, workaround for Kconfig BS default 0x2 # FIXME, workaround for Kconfig BS
depends on I2C_TPM depends on I2C_TPM
config DRIVER_TPM_I2C_IRQ config DRIVER_TPM_I2C_IRQ

2
src/drivers/pc80/tpm/Kconfig
View File

@ -25,7 +25,7 @@ config TPM_TIS_BASE_ADDRESS
config TPM_PIRQ config TPM_PIRQ
hex hex
default 0 default 0x0
depends on LPC_TPM depends on LPC_TPM
help help
This can be used to specify a PIRQ to use instead of SERIRQ, This can be used to specify a PIRQ to use instead of SERIRQ,

2
src/drivers/spi/tpm/Kconfig
View File

@ -4,7 +4,7 @@ config SPI_TPM
config DRIVER_TPM_SPI_BUS config DRIVER_TPM_SPI_BUS
hex "SPI bus TPM chip is connected to" hex "SPI bus TPM chip is connected to"
default 0 default 0x0
depends on SPI_TPM depends on SPI_TPM
config DRIVER_TPM_SPI_CHIP config DRIVER_TPM_SPI_CHIP

2
src/ec/google/chromeec/Kconfig
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@ -72,7 +72,7 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
config EC_GOOGLE_CHROMEEC_SPI_CHIP config EC_GOOGLE_CHROMEEC_SPI_CHIP
depends on EC_GOOGLE_CHROMEEC_SPI depends on EC_GOOGLE_CHROMEEC_SPI
hex hex
default 0 default 0x0
config EC_GOOGLE_CHROMEEC_BOARDNAME config EC_GOOGLE_CHROMEEC_BOARDNAME
depends on EC_GOOGLE_CHROMEEC depends on EC_GOOGLE_CHROMEEC

2
src/mainboard/asus/a8v-e_deluxe/Kconfig
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@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0 default 0x0
config MAX_CPUS config MAX_CPUS
int int

2
src/mainboard/asus/a8v-e_se/Kconfig
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@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0 default 0x0
config MAX_CPUS config MAX_CPUS
int int

2
src/mainboard/asus/k8v-x/Kconfig
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@ -44,7 +44,7 @@ config AGP_APERTURE_SIZE
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0 default 0x0
config MAX_CPUS config MAX_CPUS
int int

2
src/mainboard/asus/kcma-d8/Kconfig
View File

@ -53,7 +53,7 @@ config DCACHE_RAM_SIZE
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string

2
src/mainboard/asus/kfsn4-dre/Kconfig
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@ -43,7 +43,7 @@ config DCACHE_RAM_SIZE
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string

2
src/mainboard/asus/kgpe-d16/Kconfig
View File

@ -54,7 +54,7 @@ config DCACHE_RAM_SIZE
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string

2
src/mainboard/asus/m2v/Kconfig
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@ -42,7 +42,7 @@ config MAINBOARD_PART_NUMBER
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0 default 0x0
config MAX_CPUS config MAX_CPUS
int int

4
src/mainboard/google/gru/Kconfig
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@ -65,7 +65,7 @@ config DRAM_SIZE_MB
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 5 default 0x5
config BOOT_DEVICE_SPI_FLASH_BUS config BOOT_DEVICE_SPI_FLASH_BUS
int int
@ -73,7 +73,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex
default 0 default 0x0
config DRIVER_TPM_I2C_ADDR config DRIVER_TPM_I2C_ADDR
hex hex

2
src/mainboard/google/nyan/Kconfig
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@ -72,7 +72,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 0x1
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

2
src/mainboard/google/nyan_big/Kconfig
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@ -73,7 +73,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 0x1
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

2
src/mainboard/google/nyan_blaze/Kconfig
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@ -74,7 +74,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 0x1
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

2
src/mainboard/google/oak/Kconfig
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@ -50,7 +50,7 @@ config MAINBOARD_VENDOR
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 0 default 0x0
config DRIVER_TPM_I2C_BUS config DRIVER_TPM_I2C_BUS
hex hex

2
src/mainboard/google/peach_pit/Kconfig
View File

@ -42,7 +42,7 @@ config DRAM_SIZE_MB
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 2 default 0x2
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
int int

2
src/mainboard/google/veyron/Kconfig
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@ -54,7 +54,7 @@ config MAINBOARD_VENDOR
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 0 default 0x0
config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int int

2
src/mainboard/hp/dl165_g6_fam10/Kconfig
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@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string

2
src/mainboard/msi/ms7135/Kconfig
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@ -38,7 +38,7 @@ config MAX_PHYSICAL_CPUS
config HT_CHAIN_UNITID_BASE config HT_CHAIN_UNITID_BASE
hex hex
default 0 default 0x0
config HT_CHAIN_END_UNITID_BASE config HT_CHAIN_END_UNITID_BASE
hex hex

2
src/mainboard/tyan/s2912_fam10/Kconfig
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@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string

2
src/mainboard/winent/mb6047/Kconfig
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@ -40,7 +40,7 @@ config MAX_PHYSICAL_CPUS
config HT_CHAIN_UNITID_BASE config HT_CHAIN_UNITID_BASE
hex hex
default 0 default 0x0
config HT_CHAIN_END_UNITID_BASE config HT_CHAIN_END_UNITID_BASE
hex hex

2
src/soc/intel/broadwell/Kconfig
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@ -167,7 +167,7 @@ config INTEL_PCH_UART_CONSOLE
config INTEL_PCH_UART_CONSOLE_NUMBER config INTEL_PCH_UART_CONSOLE_NUMBER
hex "Serial IO UART number to use for console" hex "Serial IO UART number to use for console"
default "0x0" default 0x0
depends on INTEL_PCH_UART_CONSOLE depends on INTEL_PCH_UART_CONSOLE
config TTYS0_BASE config TTYS0_BASE

10
src/southbridge/amd/cimx/sb800/Kconfig
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@ -39,8 +39,8 @@ config ENABLE_IDE_COMBINED_MODE
config IDE_COMBINED_MODE config IDE_COMBINED_MODE
hex hex
default "0x0" if ENABLE_IDE_COMBINED_MODE default 0x0 if ENABLE_IDE_COMBINED_MODE
default "0x1" if !ENABLE_IDE_COMBINED_MODE default 0x1 if !ENABLE_IDE_COMBINED_MODE
choice choice
prompt "SATA Mode" prompt "SATA Mode"
@ -70,9 +70,9 @@ endchoice
config SB800_SATA_MODE config SB800_SATA_MODE
hex hex
depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
default "0x0" if SB800_SATA_IDE default 0x0 if SB800_SATA_IDE
default "0x1" if SB800_SATA_RAID default 0x1 if SB800_SATA_RAID
default "0x2" if SB800_SATA_AHCI default 0x2 if SB800_SATA_AHCI
config SB_SUPERIO_HWM config SB_SUPERIO_HWM
bool bool

2
src/vendorcode/google/chromeos/Kconfig
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@ -212,7 +212,7 @@ config VBOOT_KEYBLOCK_VERSION
config VBOOT_KEYBLOCK_PREAMBLE_FLAGS config VBOOT_KEYBLOCK_PREAMBLE_FLAGS
hex "Keyblock preamble flags" hex "Keyblock preamble flags"
default 0 default 0x0
endmenu # Keys endmenu # Keys