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soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN

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BUG=b:151161585
BRANCH=none
TEST=build and boot ripto/volteer and check FSP logs for lockdown
parameters

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I63cec8a718285f424914e426d0399ed821588dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim
2020-03-20 12:17:14 -07:00
committed by Patrick Georgi
parent aecbe7a988
commit 3ba64ca3d1
1 changed files with 14 additions and 0 deletions
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14
src/soc/intel/tigerlake/fsp_params.c
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@ -9,6 +9,7 @@
#include <fsp/util.h>
#include <intelblocks/lpss.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@ -97,6 +98,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < 8; i++)
params->IomTypeCPortPadCfg[i] = 0x09000000;
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->PchLockDownGlobalSmi = 0;
params->PchLockDownBiosInterface = 0;
params->PchUnlockGpioPads = 1;
params->RtcMemoryLock = 0;
} else {
params->PchLockDownGlobalSmi = 1;
params->PchLockDownBiosInterface = 1;
params->PchUnlockGpioPads = 0;
params->RtcMemoryLock = 1;
}
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;