diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 247d4f5189..70385d425c 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -37,11 +37,32 @@ chip soc/intel/tigerlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" +# eSPI (soc/intel/tigerlake/espi.c) + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0E01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0F01" + # Finalize (soc/intel/tigerlake/finalize.c) # PM Timer Enabled register "PmTimerDisabled" = "0" # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + # Enable C6 DRAM register "enable_c6dram" = "1" @@ -155,17 +176,6 @@ chip soc/intel/tigerlake # Graphics (soc/intel/tigerlake/graphics.c) #TODO register "gfx" = "GMA_STATIC_DISPLAYS(0)" -# LPC (soc/intel/tigerlake/lpc.c) - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F (Port 80) - register "gen1_dec" = "0x000c0081" - # Address 0x88: Decode 0x68 - 0x6F (PMC) - register "gen2_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen3_dec" = "0x00fc0E01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen4_dec" = "0x00fc0F01" - # PMC (soc/intel/tigerlake/pmc.c) # TODO: Disable deep Sx states register "deep_s3_enable_ac" = "0" @@ -185,7 +195,6 @@ chip soc/intel/tigerlake # Disable HECI register "HeciEnabled" = "0" - # Actual device tree device cpu_cluster 0 on device lapic 0 on end