arch/x86: SSE2 implies SSE support

Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

src/cpu/amd/family_10h-family_15h/Kconfig

@@ -4,7 +4,6 @@ config CPU_AMD_MODEL_10XXX
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
-	select SSE
 	select SSE2
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC

src/cpu/intel/haswell/Kconfig

@@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_MONOTONIC_TIMER
 	select SMP
 	select MMX
-	select SSE
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE

src/cpu/intel/model_2065x/Kconfig

@@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
-	select SSE
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE

src/cpu/intel/socket_FCBGA1023/Kconfig

@@ -6,7 +6,6 @@ if CPU_INTEL_SOCKET_FCBGA1023
 config SOCKET_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select MMX
-	select SSE
 	select SSE2
 
 endif

src/soc/amd/stoneyridge/Kconfig

@@ -62,7 +62,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SMM_TSEG
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
-	select SSE
 	select SSE2
 	select RTC
 	select SOC_AMD_PSP_SELECTABLE_SMU_FW