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Move SB800 clock init earlier

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Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.

Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Scott Duplichan
2011-06-21 20:05:19 -05:00
committed by Marc Jones
parent d367b00c5b
commit 3c74a2ab2c
1 changed files with 15 additions and 11 deletions
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26
src/mainboard/asrock/e350m1/romstage.c
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@@ -55,6 +55,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr(0xc0010062, 0); __writemsr(0xc0010062, 0);
if (boot_cpu()) {
u8 reg8;
// SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
// Program SB800 MiscCntrl
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
}
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
sb_poweron_init(); sb_poweron_init();
@@ -63,17 +78,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
} }
//reg8 = pmio_read(0x24);
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
//pmio_write(0x24, reg8);
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
post_code(0x34); post_code(0x34);