inteltool: add support for CannonPoint-LP

Add support for CannonPoint-LP U Premium
(CoffeeLake-U and WhiskeyLake-U)

GPIO info taken from:
- Intel doc #337867-002
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h

Test: Read GPIOs from out-of-tree WhiskeyLake-U board

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
2019-06-11 23:23:46 -05:00
committed by Patrick Georgi
parent e32ded82f0
commit 3c78445ad9
9 changed files with 366 additions and 0 deletions

View File

@@ -156,6 +156,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b
#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
#define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145
@@ -294,6 +295,8 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */
#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */